* [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT
@ 2017-01-25 17:26 Chris Wilson
2017-01-26 7:30 ` Joonas Lahtinen
2017-01-26 12:35 ` Paulo Zanoni
0 siblings, 2 replies; 4+ messages in thread
From: Chris Wilson @ 2017-01-25 17:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
Remove WaGsvDisableTurbo and WaRsUseTimeoutMode as these were only for
pre-production Broxton devices, and this code is now defunct.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 35 +++--------------------------------
1 file changed, 3 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a58c0edd7578..6cf3fb8e12cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4935,10 +4935,6 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
{
- /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- return 0;
-
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
WARN_ON(val > dev_priv->rps.max_freq);
WARN_ON(val < dev_priv->rps.min_freq);
@@ -5353,22 +5349,6 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
{
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- /*
- * BIOS could leave the Hw Turbo enabled, so need to explicitly
- * clear out the Control register just to avoid inconsitency
- * with debugfs interface, which will show Turbo as enabled
- * only and that is not expected by the User after adding the
- * WaGsvDisableTurbo. Apart from this there is no problem even
- * if the Turbo is left enabled in the Control register, as the
- * Up/Down interrupts would remain masked.
- */
- gen9_disable_rps(dev_priv);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
- return;
- }
-
/* Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RC_VIDEO_FREQ,
GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
@@ -5428,18 +5408,9 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
if (intel_enable_rc6() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
- /* WaRsUseTimeoutMode:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
- I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
- GEN7_RC_CTL_TO_MODE |
- rc6_mask);
- } else {
- I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
- I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
- GEN6_RC_CTL_EI_MODE(1) |
- rc6_mask);
- }
+ I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ I915_WRITE(GEN6_RC_CONTROL,
+ GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
/*
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
--
2.11.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT
2017-01-25 17:26 [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT Chris Wilson
@ 2017-01-26 7:30 ` Joonas Lahtinen
2017-01-26 9:05 ` Chris Wilson
2017-01-26 12:35 ` Paulo Zanoni
1 sibling, 1 reply; 4+ messages in thread
From: Joonas Lahtinen @ 2017-01-26 7:30 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Mika Kuoppala
On ke, 2017-01-25 at 17:26 +0000, Chris Wilson wrote:
> Remove WaGsvDisableTurbo and WaRsUseTimeoutMode as these were only for
> pre-production Broxton devices, and this code is now defunct.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT
2017-01-26 7:30 ` Joonas Lahtinen
@ 2017-01-26 9:05 ` Chris Wilson
0 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2017-01-26 9:05 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx, Mika Kuoppala
On Thu, Jan 26, 2017 at 09:30:14AM +0200, Joonas Lahtinen wrote:
> On ke, 2017-01-25 at 17:26 +0000, Chris Wilson wrote:
> > Remove WaGsvDisableTurbo and WaRsUseTimeoutMode as these were only for
> > pre-production Broxton devices, and this code is now defunct.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Checked with trybot to make sure CI had no BXT-A1 and pushed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT
2017-01-25 17:26 [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT Chris Wilson
2017-01-26 7:30 ` Joonas Lahtinen
@ 2017-01-26 12:35 ` Paulo Zanoni
1 sibling, 0 replies; 4+ messages in thread
From: Paulo Zanoni @ 2017-01-26 12:35 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Mika Kuoppala
Em Qua, 2017-01-25 às 17:26 +0000, Chris Wilson escreveu:
> Remove WaGsvDisableTurbo and WaRsUseTimeoutMode as these were only
> for
> pre-production Broxton devices, and this code is now defunct.
Can you please also patch intel_detect_preproduction_hw()?
Thanks,
Paulo
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 35 +++--------------------------
> ------
> 1 file changed, 3 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index a58c0edd7578..6cf3fb8e12cc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4935,10 +4935,6 @@ static u32 gen6_rps_pm_mask(struct
> drm_i915_private *dev_priv, u8 val)
> * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
> static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
> {
> - /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A*
> */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - return 0;
> -
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> WARN_ON(val > dev_priv->rps.max_freq);
> WARN_ON(val < dev_priv->rps.min_freq);
> @@ -5353,22 +5349,6 @@ static void gen9_enable_rps(struct
> drm_i915_private *dev_priv)
> {
> intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>
> - /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A*
> */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - /*
> - * BIOS could leave the Hw Turbo enabled, so need to
> explicitly
> - * clear out the Control register just to avoid
> inconsitency
> - * with debugfs interface, which will show Turbo as
> enabled
> - * only and that is not expected by the User after
> adding the
> - * WaGsvDisableTurbo. Apart from this there is no
> problem even
> - * if the Turbo is left enabled in the Control
> register, as the
> - * Up/Down interrupts would remain masked.
> - */
> - gen9_disable_rps(dev_priv);
> - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> - return;
> - }
> -
> /* Program defaults and thresholds for RPS*/
> I915_WRITE(GEN6_RC_VIDEO_FREQ,
> GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
> @@ -5428,18 +5408,9 @@ static void gen9_enable_rc6(struct
> drm_i915_private *dev_priv)
> if (intel_enable_rc6() & INTEL_RC6_ENABLE)
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> DRM_INFO("RC6 %s\n", onoff(rc6_mask &
> GEN6_RC_CTL_RC6_ENABLE));
> - /* WaRsUseTimeoutMode:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
> - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> - GEN7_RC_CTL_TO_MODE |
> - rc6_mask);
> - } else {
> - I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms
> per EI */
> - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> - GEN6_RC_CTL_EI_MODE(1) |
> - rc6_mask);
> - }
> + I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI
> */
> + I915_WRITE(GEN6_RC_CONTROL,
> + GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
>
> /*
> * 3b: Enable Coarse Power Gating only when RC6 is enabled.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-01-26 12:35 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-25 17:26 [PATCH] drm/i915: Remove early pre-production RPS workarounds for BXT Chris Wilson
2017-01-26 7:30 ` Joonas Lahtinen
2017-01-26 9:05 ` Chris Wilson
2017-01-26 12:35 ` Paulo Zanoni
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