Re: [PATCH v5 3/8] ARM: dts: rockchip: add timer entries to rk3188 SoC

From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Alexander Kochetkov <al.kochet@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	Thomas Gleixner <tglx@linutronix.de>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	Caesar Wang <wxt@rock-chips.com>,
	Huang Tao <huangtao@rock-chips.com>
Subject: Re: [PATCH v5 3/8] ARM: dts: rockchip: add timer entries to rk3188 SoC
Date: Mon, 30 Jan 2017 12:04:28 +0100	[thread overview]
Message-ID: <20170130110428.GC2206@mai> (raw)
In-Reply-To: <1485260203-14216-4-git-send-email-al.kochet@gmail.com>

On Tue, Jan 24, 2017 at 03:16:38PM +0300, Alexander Kochetkov wrote:
> The patch add two timers to all rk3188 based boards.
> 
> The first timer is from alive subsystem and it act as a backup
> for the local timers at sleep time. It act the same as other
> SoC rockchip timers already present in kernel.

It is up to the RTC to wake up the system from suspend and there is no
idle state stopping the local timers on these SoCs. So, the rockchip timers
won't be ever used on the rk3188, right ?

> The second timer is from CPU subsystem and act as replacement
> for the arm-global-timer clocksource and sched clock. It run
> at stable frequency 24MHz.

This patch should go after the rockchip timer patches.

> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
> Reviwed-by: Heiko Stübner <heiko@sntech.de>
> ---
>  arch/arm/boot/dts/rk3188.dtsi |   16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
> index 869e189..bcf8e03 100644
> --- a/arch/arm/boot/dts/rk3188.dtsi
> +++ b/arch/arm/boot/dts/rk3188.dtsi
> @@ -106,6 +106,22 @@
>  		};
>  	};
>  
> +	timer3: timer@2000e000 {
> +		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
> +		reg = <0x2000e000 0x20>;
> +		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
> +		clock-names = "timer", "pclk";
> +	};
> +
> +	timer6: timer@200380a0 {
> +		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
> +		reg = <0x200380a0 0x20>;
> +		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
> +		clock-names = "timer", "pclk";
> +	};
> +
>  	i2s0: i2s@1011a000 {
>  		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
>  		reg = <0x1011a000 0x2000>;
> -- 
> 1.7.9.5
> 

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