[U-Boot] [PATCH v3 00/13] sunxi: Allwinner H5 and OrangePi PC2 support

[U-Boot] [PATCH v3 00/13] sunxi: Allwinner H5 and OrangePi PC2 support

[Andre Przywara]

Hi,

some small changes as requested by reviewers (many thanks for that!)

Maxime, Jagan,
given I get some ACKs or RBs on the remaining patches, is this good
to go for 2017.03 still?

Cheers,
Andre.

--------------------------
This series introduces support for the Allwinner H5 SoC with four
Cortex-A53 cores. The SoC's peripherals are very similar to the H3,
although the cores and the BROM/SRAM layout resembles the A64.
The first 8 patches contain some fixes and refactoring, to make code
sharing between the three mentioned SoCs easier.
Patch 09/13 adds support for the H5 DRAM controller, by extending
the already existing combined H3/A64 DRAM code.
Patch 10/13 renames the existing CONFIG_MACH_SUN8I_H3 config symbol to
let it be used by all peripheral code that can be shared between the
H3 and H5. Patch 11/13 introduces the H5 SoC config option into Kconfig,
which defines this shared symbol as well.
Patch 12/13 adds an easy device tree, which actually uses the H3 .dtsi
and overwrites nodes which are different. This is good enough for U-Boot,
the DT will be changed anyway once we get the DT merged into the Linux
kernel.
The final patch then adds the defconfig for the OrangePi PC2 board.
Since this board comes with soldered SPI flash, we enable support for
it in the SPL. This has been tested by writing the SPI flash with some
special sunxi-fel version. The BROM loaded and executed the SPL, which
in turn loaded and executed U-Boot proper. Both parts are 64-bit only
for now.
Ethernet support is enabled, but fails at the moment since the EMAC
driver does not support setting a GPIO to enable the external Gigabit PHY.

At the moment this build suffers from the same problem as the A64: the
ATF is missing, so Linux won't boot easily. With the RFC version of the
SPL FIT extension series on the list, applied on top of this one this
should now be solved.

This series is on top of origin/master.

Please have a look and let me know your opinion!

Cheers,
Andre.

Changelog v2..v3:
- Adding ACKs and RBs
- remove not needed CONFIG_MACH_SUN50I_H5_64
- move ARM_CORTEX_CPU_IS_UP to arch/arm/Kconfig

Changelog v1..v2:
- Adding Maxime's ACKs
- new patch 2 and 3 to rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY
- renaming CONFIG symbol name for single core SoCs
- fixing one checkpatch issue (some are left, though)
- mentioning methodology and reason for missing data in DRAM driver
- renaming shared config symbol to CONFIG_MACH_SUNXI_H3_H5
- updated to lastest origin/master

Andre Przywara (13):
  sunxi: fix ACTLR.SMP assembly routine
  ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY
  fsl: ls102x: remove redundant GENERIC_TIMER_CLK
  sunxi: simplify ACTLR.SMP bit set #ifdef
  sunxi: configs: merge sun9i and sun50i SPL memory definitions
  sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM
  sunxi: provide ARMv8 mem_map for every ARM64 board
  SPI: SPL: sunxi: fix 64-bit build
  sunxi: DRAM: add Allwinner H5 support
  sunxi: prepare for sharing MACH_SUN8I_H3 config symbol
  sunxi: introduce Allwinner H5 config option
  sunxi: dts: add basic OrangePi PC 2 device tree file
  sunxi: configs: add basic OrangePi PC 2 defconfig

 arch/arm/Kconfig                              |   4 +
 arch/arm/cpu/armv7/ls102xa/psci.S             |   2 +-
 arch/arm/cpu/armv7/ls102xa/timer.c            |   2 +-
 arch/arm/cpu/armv7/nonsec_virt.S              |   4 +-
 arch/arm/cpu/armv7/sunxi/psci.c               |   2 +-
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts       | 147 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |   4 +-
 arch/arm/include/asm/arch-sunxi/cpu.h         |   1 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |   4 +-
 arch/arm/include/asm/arch-sunxi/dram.h        |   2 +-
 arch/arm/include/asm/arch-sunxi/spl.h         |   2 +-
 arch/arm/mach-sunxi/Makefile                  |   2 +-
 arch/arm/mach-sunxi/board.c                   |  12 +--
 arch/arm/mach-sunxi/clock_sun6i.c             |   6 +-
 arch/arm/mach-sunxi/cpu_info.c                |   2 +
 arch/arm/mach-sunxi/dram_sun8i_h3.c           |  97 ++++++++++++++---
 arch/arm/mach-sunxi/usb_phy.c                 |   4 +-
 board/sunxi/Kconfig                           |  28 ++++-
 board/sunxi/MAINTAINERS                       |   5 +
 board/sunxi/board.c                           |   6 +-
 configs/orangepi_pc2_defconfig                |  16 +++
 drivers/mtd/spi/Kconfig                       |   2 +-
 drivers/mtd/spi/sunxi_spi_spl.c               |  16 +--
 drivers/net/sun8i_emac.c                      |   2 +-
 drivers/power/Kconfig                         |   4 +-
 drivers/usb/host/ehci-sunxi.c                 |   2 +-
 include/configs/exynos-common.h               |   2 +-
 include/configs/ls1021aiot.h                  |   7 +-
 include/configs/ls1021aqds.h                  |   7 +-
 include/configs/ls1021atwr.h                  |   7 +-
 include/configs/mx7_common.h                  |   2 +-
 include/configs/sun50i.h                      |   1 -
 include/configs/sunxi-common.h                |  24 ++---
 scripts/config_whitelist.txt                  |   1 -
 35 files changed, 332 insertions(+), 99 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-h5-orangepi-pc2.dts
 create mode 100644 configs/orangepi_pc2_defconfig

-- 
2.8.2

[U-Boot] [PATCH v3 01/13] sunxi: fix ACTLR.SMP assembly routine

[Andre Przywara]

If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/mach-sunxi/board.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 52be5b0..58fbacb 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -188,7 +188,8 @@ void s_init(void)
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
 		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
+		"mcr p15, 0, r0, c1, c0, 1\n"
+		::: "r0");
 #endif
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 	/* Enable non-secure access to some peripherals */
-- 
2.8.2

[U-Boot] [PATCH v3 02/13] ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY

[Andre Przywara]

Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
 arch/arm/cpu/armv7/nonsec_virt.S | 4 ++--
 arch/arm/cpu/armv7/sunxi/psci.c  | 2 +-
 board/sunxi/board.c              | 6 +++---
 include/configs/exynos-common.h  | 2 +-
 include/configs/ls1021aiot.h     | 2 +-
 include/configs/ls1021aqds.h     | 2 +-
 include/configs/ls1021atwr.h     | 2 +-
 include/configs/mx7_common.h     | 2 +-
 include/configs/sun50i.h         | 1 -
 include/configs/sunxi-common.h   | 2 +-
 scripts/config_whitelist.txt     | 1 -
 11 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 95ce938..e39aba7 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -188,11 +188,11 @@ ENTRY(_nonsec_init)
  * we do this here instead.
  * But first check if we have the generic timer.
  */
-#ifdef CONFIG_TIMER_CLK_FREQ
+#ifdef COUNTER_FREQUENCY
 	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
 	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits
 	cmp	r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
-	ldreq	r1, =CONFIG_TIMER_CLK_FREQ
+	ldreq	r1, =COUNTER_FREQUENCY
 	mcreq	p15, 0, r1, c14, c0, 0		@ write CNTFRQ
 #endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 766b8c7..104dc90 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -46,7 +46,7 @@ static u32 __secure cp15_read_cntp_ctl(void)
 	return val;
 }
 
-#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
+#define ONE_MS (COUNTER_FREQUENCY / 1000)
 
 static void __secure __mdelay(u32 ms)
 {
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5365638..b966012 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -100,14 +100,14 @@ int board_init(void)
 		 * we avoid the risk of writing to it.
 		 */
 		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
-		if (freq != CONFIG_TIMER_CLK_FREQ) {
+		if (freq != COUNTER_FREQUENCY) {
 			debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
-			      freq, CONFIG_TIMER_CLK_FREQ);
+			      freq, COUNTER_FREQUENCY);
 #ifdef CONFIG_NON_SECURE
 			printf("arch timer frequency is wrong, but cannot adjust it\n");
 #else
 			asm volatile("mcr p15, 0, %0, c14, c0, 0"
-				     : : "r"(CONFIG_TIMER_CLK_FREQ));
+				     : : "r"(COUNTER_FREQUENCY));
 #endif
 		}
 	}
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 7868c86..ccb335e 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -23,7 +23,7 @@
 
 /* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
-#define CONFIG_TIMER_CLK_FREQ		CONFIG_SYS_CLK_FREQ
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index b422863..31f71f1 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -252,7 +252,7 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 3c255aa..fbef0be 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -509,7 +509,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7100d96..43a993b 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -379,7 +379,7 @@
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ		12500000
+#define COUNTER_FREQUENCY		12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		256
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index bdacedc..6c954a9 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -21,7 +21,7 @@
 #define CONFIG_MXC_GPT_HCLK
 #define CONFIG_SYSCOUNTER_TIMER
 #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
-#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_BOOTM_LEN	0x1000000
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
index 3e5708b..1b7bfb6 100644
--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -18,7 +18,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	1
 
-#define COUNTER_FREQUENCY	CONFIG_TIMER_CLK_FREQ
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 3ac96da..0f40c7f 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -53,7 +53,7 @@
 #endif
 
 /* CPU */
-#define CONFIG_TIMER_CLK_FREQ		24000000
+#define COUNTER_FREQUENCY		24000000
 
 /*
  * The DRAM Base differs between some models. We cannot use macros for the
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 37ce51a..6333aa6 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -6541,7 +6541,6 @@ CONFIG_TI816X_EVM_DDR3
 CONFIG_TI816X_USE_EMIF0
 CONFIG_TI816X_USE_EMIF1
 CONFIG_TI81XX
-CONFIG_TIMER_CLK_FREQ
 CONFIG_TIMESTAMP
 CONFIG_TIZEN
 CONFIG_TI_KEYSTONE_SERDES
-- 
2.8.2

[U-Boot] [PATCH v3 03/13] fsl: ls102x: remove redundant GENERIC_TIMER_CLK

[Andre Przywara]

Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/psci.S  | 2 +-
 arch/arm/cpu/armv7/ls102xa/timer.c | 2 +-
 include/configs/ls1021aiot.h       | 5 -----
 include/configs/ls1021aqds.h       | 5 -----
 include/configs/ls1021atwr.h       | 5 -----
 5 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3d41d37..e1dc5f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -37,7 +37,7 @@
 
 	.align	5
 
-#define	ONE_MS		(GENERIC_TIMER_CLK / 1000)
+#define	ONE_MS		(COUNTER_FREQUENCY / 1000)
 #define	RESET_WAIT	(30 * ONE_MS)
 
 .globl	psci_version
diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c
index e6a32ca..d5237d2 100644
--- a/arch/arm/cpu/armv7/ls102xa/timer.c
+++ b/arch/arm/cpu/armv7/ls102xa/timer.c
@@ -62,7 +62,7 @@ int timer_init(void)
 	/* Enable System Counter */
 	writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
 
-	freq = GENERIC_TIMER_CLK;
+	freq = COUNTER_FREQUENCY;
 	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 
 	/* Set PL1 Physical Timer Ctrl */
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 31f71f1..d4ba080 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -36,11 +36,6 @@
 #define CONFIG_CMD_EXT2
 #endif
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index fbef0be..cb9f1ea 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -27,11 +27,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 43a993b..2647ef5 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -56,11 +56,6 @@
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 #endif
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK		12500000
-
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 
-- 
2.8.2

[U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Andre Przywara]

Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/Kconfig            | 4 ++++
 arch/arm/mach-sunxi/board.c | 5 +----
 board/sunxi/Kconfig         | 2 ++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fc36723..98791c0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
 	  ARM_SOC_BOOT0_HOOK which contains the required assembler
 	  preprocessor code.
 
+config ARM_CORTEX_CPU_IS_UP
+	bool
+	default n
+
 config USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy"
 	default y
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 58fbacb..fdcf68e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -180,10 +180,7 @@ void s_init(void)
 	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 #endif
 
-#if defined CONFIG_MACH_SUN6I || \
-    defined CONFIG_MACH_SUN7I || \
-    defined CONFIG_MACH_SUN8I || \
-    defined CONFIG_MACH_SUN9I
+#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 37b4252..ea0d658 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -50,12 +50,14 @@ choice
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7
+	select ARM_CORTEX_CPU_IS_UP
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7
+	select ARM_CORTEX_CPU_IS_UP
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
-- 
2.8.2

[U-Boot] [PATCH v3 05/13] sunxi: configs: merge sun9i and sun50i SPL memory definitions

[Andre Przywara]

For some reason we were pretty conservative when defining the maximum
SPL size for the Allwinner A80(sun9i) SoC.
According to the manual the SRAM A1 is even 40KB, but the BROM
probably still has the 32 KiB load limit. For the sake of simplicity,
merge the SPL memory definitions for the A64 and A80 SoCs, since both
SoC share the BROM/SRAM A1 memory layout.
This helps to further simplify this is in the next patch.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 include/configs/sunxi-common.h | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 0f40c7f..2b67827 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -186,12 +186,9 @@
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 #endif
 
-#if defined(CONFIG_MACH_SUN9I)
-#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* ? KiB on sun9i */
-#elif defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
 #define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun50i */
+#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun9/50i */
 #else
 #define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
-- 
2.8.2

[U-Boot] [PATCH v3 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

[Andre Przywara]

Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/include/asm/arch-sunxi/spl.h |  2 +-
 board/sunxi/Kconfig                   |  6 ++++++
 include/configs/sunxi-common.h        | 19 +++++++------------
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index 5d7ab55..831d0c0 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -12,7 +12,7 @@
 #define SPL_SIGNATURE		"SPL" /* marks "sunxi" SPL header */
 #define SPL_HEADER_VERSION	1
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 #define SPL_ADDR		0x10000
 #else
 #define SPL_ADDR		0x0
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ea0d658..688cb12 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
 config SPL_SERIAL_SUPPORT
 	default y
 
+config SUNXI_HIGH_SRAM
+	bool
+	default n
+
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
@@ -120,6 +124,7 @@ config MACH_SUN8I_H3
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
+	select SUNXI_HIGH_SRAM
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 
@@ -127,6 +132,7 @@ config MACH_SUN50I
 	bool "sun50i (Allwinner A64)"
 	select ARM64
 	select SUNXI_GEN_SUN6I
+	select SUNXI_HIGH_SRAM
 	select SUPPORT_SPL
 
 endchoice
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 2b67827..0997dfa 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -86,7 +86,7 @@
 
 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 /*
  * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
  * slightly bigger. Note that it is possible to map the first 32 KiB of the
@@ -186,29 +186,24 @@
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 #endif
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_SUNXI_HIGH_SRAM
 #define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun9/50i */
+#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB */
+#define LOW_LEVEL_SRAM_STACK		0x00018000
 #else
 #define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
+#define LOW_LEVEL_SRAM_STACK		0x00008000	/* End of sram */
 #endif
 
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
 #ifndef CONFIG_ARM64
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
 #endif
 
 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
 
-#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
-/* FIXME: 40 KiB instead of 32 KiB ? */
-#define LOW_LEVEL_SRAM_STACK		0x00018000
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#else
-/* end of 32 KiB in sram */
-#define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#endif
 
 /* I2C */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-- 
2.8.2

[U-Boot] [PATCH v3 07/13] sunxi: provide ARMv8 mem_map for every ARM64 board

[Andre Przywara]

Every armv8 board needs the memory map, so change the #ifdef to
ARM64 to avoid enumerating every single board or SoC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/mach-sunxi/board.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index fdcf68e..96764d1 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -40,7 +40,7 @@ struct fel_stash {
 
 struct fel_stash fel_stash __attribute__((section(".data")));
 
-#ifdef CONFIG_MACH_SUN50I
+#ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 
 static struct mm_region sunxi_mem_map[] = {
-- 
2.8.2

[U-Boot] [PATCH v3 08/13] SPI: SPL: sunxi: fix 64-bit build

[Andre Przywara]

Addresses passed on to readl and writel are expected to be of the same
size as a pointer. Change the parameter types of sunxi_spi0_read_data()
to make the compiler happy and allow a warning-free aarch64 compile.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/mtd/spi/sunxi_spi_spl.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c
index a24c115..852abd4 100644
--- a/drivers/mtd/spi/sunxi_spi_spl.c
+++ b/drivers/mtd/spi/sunxi_spi_spl.c
@@ -185,14 +185,14 @@ static void spi0_deinit(void)
 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 
 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
-				 u32 spi_ctl_reg,
-				 u32 spi_ctl_xch_bitmask,
-				 u32 spi_fifo_reg,
-				 u32 spi_tx_reg,
-				 u32 spi_rx_reg,
-				 u32 spi_bc_reg,
-				 u32 spi_tc_reg,
-				 u32 spi_bcc_reg)
+				 ulong spi_ctl_reg,
+				 ulong spi_ctl_xch_bitmask,
+				 ulong spi_fifo_reg,
+				 ulong spi_tx_reg,
+				 ulong spi_rx_reg,
+				 ulong spi_bc_reg,
+				 ulong spi_tc_reg,
+				 ulong spi_bcc_reg)
 {
 	writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 	writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
-- 
2.8.2

[U-Boot] [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Andre Przywara]

The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.
Register setup differences between H5 and H3 are courtesy of Jens Kuske.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
 arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97 +++++++++++++++++++++++++++++------
 2 files changed, 82 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 6f96a97..e8e670e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -15,5 +15,6 @@
 
 #define SOCID_A64	0x1689
 #define SOCID_H3	0x1680
+#define SOCID_H5	0x1718
 
 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 9f7cc7f..d681a9d 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
 	writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
 }
 
+static void mctl_set_master_priority_h5(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+	/* enable bandwidth limit windows and set windows size 1us */
+	writel(399, &mctl_com->tmr);
+	writel((1 << 16), &mctl_com->bwcr);
+
+	/* set cpu high priority */
+	writel(0x00000001, &mctl_com->mapr);
+
+	/* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+	 * they initialise it */
+	MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
+	MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
+	MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
+	MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
+	MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);
+	MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
+	MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);
+	MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);
+	MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);
+	MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);
+	MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);
+	MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
+}
+
 static void mctl_set_master_priority(uint16_t socid)
 {
 	switch (socid) {
@@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
 	case SOCID_A64:
 		mctl_set_master_priority_a64();
 		return;
+	case SOCID_H5:
+		mctl_set_master_priority_h5();
+		return;
 	}
 }
 
@@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
 
 	/* set two rank timing */
 	clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
-			(0x66 << 8) | (0x10 << 0));
+			((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
 
 	/* set PHY interface timing, write latency and read latency configure */
 	writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
@@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
 				CCM_DRAMCLK_CFG_DIV(1) |
 				CCM_DRAMCLK_CFG_SRC_PLL11 |
 				CCM_DRAMCLK_CFG_UPD);
-	} else if (socid == SOCID_H3) {
+	} else if (socid == SOCID_H3 || socid == SOCID_H5) {
 		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
 		clrsetbits_le32(&ccm->dram_clk_cfg,
 				CCM_DRAMCLK_CFG_DIV_MASK |
@@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
 	setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 	udelay(10);
 
-	writel(0xc00e, &mctl_ctl->clken);
+	writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
 	udelay(500);
 }
 
@@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 
 	/* setting VTC, default disable all VT */
 	clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
-	clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+	if (socid == SOCID_H5)
+		setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
+	else
+		clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
 
 	/* increase DFI_PHY_UPD clock */
 	writel(PROTECT_MAGIC, &mctl_com->protect);
@@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	udelay(100);
 
 	/* set dramc odt */
-	for (i = 0; i < 4; i++)
-		clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
-				(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
-				(0x3 << 14),
-				IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
-					DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF);
+	for (i = 0; i < 4; i++) {
+		u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
+				(0x3 << 12) | (0x3 << 14);
+		u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+				DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
+
+		if (socid == SOCID_H5) {
+			clearmask |= 0x2 << 8;
+			setmask |= 0x4 << 8;
+		}
+		clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
+	}
 
 	/* AC PDR should always ON */
-	setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+	clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
+			0x1 << 1);
 
 	/* set DQS auto gating PD mode */
 	setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
@@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 		/* dphy & aphy phase select 270 degree */
 		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 				(0x1 << 10) | (0x2 << 8));
-	} else if (socid == SOCID_A64) {
+	} else if (socid == SOCID_A64 || socid == SOCID_H5) {
 		/* dphy & aphy phase select ? */
 		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 				(0x0 << 10) | (0x3 << 8));
@@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 
 		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
 			      PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
-	} else if (socid == SOCID_A64) {
+	} else if (socid == SOCID_A64 || socid == SOCID_H5) {
 		clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
 
 		mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
 			      PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+		/* no PIR_QSGATE for H5 ???? */
 	}
 
 	/* detect ranks and bus width */
@@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	/* set PGCR3, CKE polarity */
 	if (socid == SOCID_H3)
 		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
-	else if (socid == SOCID_A64)
+	else if (socid == SOCID_A64 || socid == SOCID_H5)
 		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
 
 	/* power down zq calibration module for power save */
@@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
 	   3,  4,  0,  3,  4,  1,  4,  0,			\
 	   1,  1,  0,  1, 13,  5,  4      }
 
+#define SUN8I_H5_DX_READ_DELAYS					\
+	{{ 14, 15, 17, 17, 17, 17, 17, 18, 17,  3,  3 },	\
+	 { 21, 21, 12, 22, 21, 21, 21, 21, 21,  3,  3 },	\
+	 { 16, 19, 19, 17, 22, 22, 21, 22, 19,  3,  3 },	\
+	 { 21, 21, 22, 22, 20, 21, 19, 19, 19,  3,  3 } }
+#define SUN8I_H5_DX_WRITE_DELAYS				\
+	{{  1,  2,  3,  4,  3,  4,  4,  4,  6,  6,  6 },	\
+	 {  6,  6,  6,  5,  5,  5,  5,  5,  6,  6,  6 },	\
+	 {  0,  2,  4,  2,  6,  5,  5,  5,  6,  6,  6 },	\
+	 {  3,  3,  3,  2,  2,  1,  1,  1,  4,  4,  4 } }
+#define SUN8I_H5_AC_DELAYS					\
+	{  0,  0,  5,  5,  0,  0,  0,  0,			\
+	   0,  0,  0,  0,  3,  3,  3,  3,			\
+	   3,  3,  3,  3,  3,  3,  3,  3,			\
+	   3,  3,  3,  3,  2,  0,  0      }
+
 unsigned long sunxi_dram_init(void)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
@@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void)
 		.dx_read_delays  = SUN50I_A64_DX_READ_DELAYS,
 		.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN50I_A64_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I_H5)
+		.dx_read_delays  = SUN8I_H5_DX_READ_DELAYS,
+		.dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
+		.ac_delays	 = SUN8I_H5_AC_DELAYS,
 #endif
 	};
 /*
@@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void)
 	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
+#elif defined(CONFIG_MACH_SUN50I_H5)
+	uint16_t socid = SOCID_H5;
 #endif
 
 	mctl_sys_init(socid, &para);
@@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void)
 	if (socid == SOCID_H3)
 		writel(0x0c000400, &mctl_ctl->odtcfg);
 
-	if (socid == SOCID_A64) {
-		setbits_le32(&mctl_ctl->vtfcr, 2 << 8);
+	if (socid == SOCID_A64 || socid == SOCID_H5) {
+		setbits_le32(&mctl_ctl->vtfcr,
+			     (socid == SOCID_H5 ? 3 : 2) << 8);
 		clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
 	}
 
-- 
2.8.2

[U-Boot] [PATCH v3 10/13] sunxi: prepare for sharing MACH_SUN8I_H3 config symbol

[Andre Przywara]

The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  4 ++--
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |  4 ++--
 arch/arm/include/asm/arch-sunxi/dram.h        |  2 +-
 arch/arm/mach-sunxi/Makefile                  |  2 +-
 arch/arm/mach-sunxi/board.c                   |  2 +-
 arch/arm/mach-sunxi/clock_sun6i.c             |  6 +++---
 arch/arm/mach-sunxi/usb_phy.c                 |  4 ++--
 board/sunxi/Kconfig                           | 14 +++++++++-----
 drivers/mtd/spi/Kconfig                       |  2 +-
 drivers/net/sun8i_emac.c                      |  2 +-
 drivers/power/Kconfig                         |  4 ++--
 drivers/usb/host/ehci-sunxi.c                 |  2 +-
 12 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 3f87672..1bfb48b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -242,7 +242,7 @@ struct sunxi_ccm_reg {
 /* ahb_gate0 offsets */
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
@@ -293,7 +293,7 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 /*
  * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 3c85222..ea672fe 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
 #define SUNXI_USB2_BASE			0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE		0x01c19000
 #define SUNXI_USB0_BASE			0x01c1a000
 #define SUNXI_USB1_BASE			0x01c1b000
@@ -94,7 +94,7 @@
 #define SUNXI_KEYPAD_BASE		0x01c23000
 #define SUNXI_TZPC_BASE			0x01c23400
 
-#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \
 defined(CONFIG_MACH_SUN50I)
 /* SID address space starts at 0x01c1400, but e-fuse is@offset 0x200 */
 #define SUNXI_SIDC_BASE			0x01c14000
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 53e6d47..1dc8220 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,7 +24,7 @@
 #include <asm/arch/dram_sun8i_a33.h>
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include <asm/arch/dram_sun8i_a83t.h>
-#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#elif defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #include <asm/arch/dram_sun8i_h3.h>
 #elif defined(CONFIG_MACH_SUN9I)
 #include <asm/arch/dram_sun9i.h>
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba11..efab481 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -48,7 +48,7 @@ obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUN8I_H3)	+= dram_sun8i_h3.o
+obj-$(CONFIG_MACH_SUNXI_H3_H5)	+= dram_sun8i_h3.o
 obj-$(CONFIG_MACH_SUN9I)	+= dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)	+= dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 96764d1..5e03d03 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -98,7 +98,7 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index d123b3a..4762fbf 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -22,7 +22,7 @@ void clock_init_safe(void)
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 	struct sunxi_prcm_reg * const prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
@@ -51,7 +51,7 @@ void clock_init_safe(void)
 
 void clock_init_sec(void)
 {
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
@@ -152,7 +152,7 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 	const int max_n = 32;
 	int k = 1, m = 2;
 
-#ifdef CONFIG_MACH_SUN8I_H3
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 	clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
 			CCM_PLL5_TUN_INIT_FREQ_MASK,
 			CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index 278587b..9bf0b56 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,10 +146,10 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
 	}
 }
 
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
-#if defined CONFIG_MACH_SUN8I_H3
+#if defined CONFIG_MACH_SUNXI_H3_H5
 	if (phy->id == 0)
 		clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
 #endif
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 688cb12..bbd6a3c 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -47,6 +47,11 @@ config SUNXI_GEN_SUN6I
 	watchdog, etc.
 
 
+config MACH_SUNXI_H3_H5
+	bool
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
 choice
 	prompt "Sunxi SoC Variant"
 	optional
@@ -117,8 +122,7 @@ config MACH_SUN8I_H3
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
+	select MACH_SUNXI_H3_H5
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN9I
@@ -140,7 +144,7 @@ endchoice
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
 	bool
-	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
+	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
 	bool "reserve space for Allwinner boot0 header"
@@ -328,7 +332,7 @@ config OLD_SUNXI_KERNEL_COMPAT
 
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
-	default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
+	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 	default ""
 	---help---
 	Set the card detect pin for mmc0, leave empty to not use cd. This
@@ -493,7 +497,7 @@ config AXP_GPIO
 
 config VIDEO
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
-	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
+	depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1f23c8e..5ca0a71 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -132,7 +132,7 @@ if SPL
 
 config SPL_SPI_SUNXI
 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
-	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I
+	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
 	---help---
 	Enable support for SPI Flash. This option allows SPL to read from
 	sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index abd9cc8..dda9adc 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -62,7 +62,7 @@
 
 #define AHB_GATE_OFFSET_EPHY	0
 
-#if defined(CONFIG_MACH_SUN8I_H3)
+#if defined(CONFIG_MACH_SUNXI_H3_H5)
 #define SUN8I_GPD8_GMAC		2
 #else
 #define SUN8I_GPD8_GMAC		4
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index f2c5629..64e5bc2 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -12,7 +12,7 @@ choice
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
 	default AXP818_POWER if MACH_SUN8I_A83T
-	default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I
+	default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
 
 config SUNXI_NO_PMIC
 	bool "board without a pmic"
@@ -60,7 +60,7 @@ config AXP818_POWER
 
 config SY8106A_POWER
 	bool "SY8106A pmic support"
-	depends on MACH_SUN8I_H3
+	depends on MACH_SUNXI_H3_H5
 	---help---
 	Select this to enable support for the SY8106A pmic found on some
 	H3 boards.
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 5bb97ff..068f24f 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -45,7 +45,7 @@ static int ehci_usb_probe(struct udevice *dev)
 	 * clocks resp. phys.
 	 */
 	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
-#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #endif
 	priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
-- 
2.8.2

[U-Boot] [PATCH v3 11/13] sunxi: introduce Allwinner H5 config option

[Andre Przywara]

The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/cpu_info.c | 2 ++
 board/sunxi/Kconfig            | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index f1f6fd5..85633cc 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -91,6 +91,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
 	puts("CPU:   Allwinner A64 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_H5
+	puts("CPU:   Allwinner H5 (SUN50I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index bbd6a3c..d8243c9 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -139,6 +139,12 @@ config MACH_SUN50I
 	select SUNXI_HIGH_SRAM
 	select SUPPORT_SPL
 
+config MACH_SUN50I_H5
+	bool "sun50i (Allwinner H5)"
+	select ARM64
+	select MACH_SUNXI_H3_H5
+	select SUNXI_HIGH_SRAM
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
-- 
2.8.2

[U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Andre Przywara]

The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/dts/Makefile                   |   2 +
 arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++++++++
 2 files changed, 149 insertions(+)
 create mode 100644 arch/arm/dts/sun50i-h5-orangepi-pc2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 796b24d..aa90526 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
 	sun8i-h3-nanopi-neo.dtb
+dtb-$(CONFIG_MACH_SUN50I_H5) += \
+	sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
new file mode 100644
index 0000000..de60f78
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+/ {
+	model = "OrangePi PC 2";
+	compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+		cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x40000000 0x40000000>;
+	};
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac;
+	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&gic {
+	compatible = "arm,gic-400";
+};
+
+&mmc0 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc",
+		     "allwinner,sun5i-a13-mmc";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy at 1 {
+		reg = <1>;
+	};
+};
-- 
2.8.2

[U-Boot] [PATCH v3 13/13] sunxi: configs: add basic OrangePi PC 2 defconfig

[Andre Przywara]

The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 board/sunxi/MAINTAINERS        |  5 +++++
 configs/orangepi_pc2_defconfig | 16 ++++++++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 configs/orangepi_pc2_defconfig

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2321b8b..3f21129 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -242,6 +242,11 @@ M:	Icenowy Zheng <icenowy@aosc.xyz>
 S:	Maintained
 F:	configs/orangepi_zero_defconfig
 
+ORANGEPI PC 2 BOARD
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/orangepi_pc2_defconfig
+
 R16 EVB PARROT BOARD
 M:	Quentin Schulz <quentin.schulz@free-electrons.com>
 S:	Maintained
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
new file mode 100644
index 0000000..353c6a0
--- /dev/null
+++ b/configs/orangepi_pc2_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_SPL=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-- 
2.8.2

[U-Boot] [PATCH v3 05/13] sunxi: configs: merge sun9i and sun50i SPL memory definitions

[Maxime Ripard]

On Wed, Feb 01, 2017 at 01:36:02AM +0000, Andre Przywara wrote:
> For some reason we were pretty conservative when defining the maximum
> SPL size for the Allwinner A80(sun9i) SoC.
> According to the manual the SRAM A1 is even 40KB, but the BROM
> probably still has the 32 KiB load limit. For the sake of simplicity,
> merge the SPL memory definitions for the A64 and A80 SoCs, since both
> SoC share the BROM/SRAM A1 memory layout.
> This helps to further simplify this is in the next patch.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 11/13] sunxi: introduce Allwinner H5 config option

[Maxime Ripard]

On Wed, Feb 01, 2017 at 01:36:08AM +0000, Andre Przywara wrote:
> The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
> As the peripherals and the pinmuxing are almost identical, we piggy
> back on the shared MACH_SUN8I_H3_H5 config symbol.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Maxime Ripard]

On Wed, Feb 01, 2017 at 01:36:09AM +0000, Andre Przywara wrote:
> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
> and changing the differing components accordingly.
> This is a preliminary device tree mostly for U-Boot's own sake, it
> is expected to be updated once the official DT gets accepted upstream.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 13/13] sunxi: configs: add basic OrangePi PC 2 defconfig

[Maxime Ripard]

On Wed, Feb 01, 2017 at 01:36:10AM +0000, Andre Przywara wrote:
> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> Add a (64-bit only) defconfig defining the required options to build
> the U-Boot proper.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 13/13] sunxi: configs: add basic OrangePi PC 2 defconfig

[André Przywara]

On 02/02/17 12:27, Maxime Ripard wrote:
> On Wed, Feb 01, 2017 at 01:36:10AM +0000, Andre Przywara wrote:
>> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
>> Add a (64-bit only) defconfig defining the required options to build
>> the U-Boot proper.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> 
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks a lot!

I realised yesterday that rebasing against current master requires three
additional not-defines to be added - for the SPL partitions stuff.
So we need:
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

in the _defconfig to avoid pulling that code in and blowing up the SPL size.

I would like to wait how the fix for the SPL stack issue will look like
and then decide whether I send a v4 or a fixup patch.

Cheers,
Andre.

[U-Boot] [PATCH v3 01/13] sunxi: fix ACTLR.SMP assembly routine

[Jagan Teki]

n Wed, Feb 1, 2017 at 2:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> If we take the liberty to use register r0 to perform our bit set, we
> should be nice enough to tell the compiler about it.
> Add r0 to the clobber list to avoid potential mayhem.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Jagan Teki <jagan@openedev.com>

-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 02/13] ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
> frequency of the ARM Generic Timer (aka. arch timer).
> ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
> purpose. It seems useful to unify them.
> Since there are less occurences of the latter version, lets convert all
> users over to COUNTER_FREQUENCY.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: York Sun <york.sun@nxp.com>

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 03/13] fsl: ls102x: remove redundant GENERIC_TIMER_CLK

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Some Freescale boards used an extra version of the constant to hold the
> Generic Timer frequency. This can easily be covered by the now unified
> COUNTER_FREQUENCY constant, so remove this extra variable from those
> boards.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: York Sun <york.sun@nxp.com>

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Instead of enumerating all SoC families that need that bit set, let's
> just express this more clearly: The SMP bits needs to be set on
> SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
> other way round, so we use ! CPU_IS_UP and ! ARM64.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/Kconfig            | 4 ++++
>  arch/arm/mach-sunxi/board.c | 5 +----
>  board/sunxi/Kconfig         | 2 ++
>  3 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fc36723..98791c0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
>           ARM_SOC_BOOT0_HOOK which contains the required assembler
>           preprocessor code.
>
> +config ARM_CORTEX_CPU_IS_UP
> +       bool
> +       default n

Better to place this in sunxi, since no other code using this expect
sunxi and the name CORTEX may also refer arm64 use something 32
related.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 05/13] sunxi: configs: merge sun9i and sun50i SPL memory definitions

[Jagan Teki]

On Thu, Feb 2, 2017 at 1:25 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Wed, Feb 01, 2017 at 01:36:02AM +0000, Andre Przywara wrote:
>> For some reason we were pretty conservative when defining the maximum
>> SPL size for the Allwinner A80(sun9i) SoC.
>> According to the manual the SRAM A1 is even 40KB, but the BROM
>> probably still has the 32 KiB load limit. For the sake of simplicity,
>> merge the SPL memory definitions for the A64 and A80 SoCs, since both
>> SoC share the BROM/SRAM A1 memory layout.
>> This helps to further simplify this is in the next patch.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
> while the first SRAM region is mapped at address 0.
> With the extended physical memory support of the A80 this was changed,
> so the BROM is now at address 0 and the SRAM region starts right behind
> this at 64KB. This configuration seems to be called "high SRAM".
> Instead of enumerating the SoCs which have copied this configuration,
> let's call a spade a spade and introduce a Kconfig option for this setup.
> SoCs implementing this (A80, A64 and H5, so far), can then select this
> configuration.
> Simplify the config header definition on the way.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/include/asm/arch-sunxi/spl.h |  2 +-
>  board/sunxi/Kconfig                   |  6 ++++++
>  include/configs/sunxi-common.h        | 19 +++++++------------
>  3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
> index 5d7ab55..831d0c0 100644
> --- a/arch/arm/include/asm/arch-sunxi/spl.h
> +++ b/arch/arm/include/asm/arch-sunxi/spl.h
> @@ -12,7 +12,7 @@
>  #define SPL_SIGNATURE          "SPL" /* marks "sunxi" SPL header */
>  #define SPL_HEADER_VERSION     1
>
> -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
> +#ifdef CONFIG_SUNXI_HIGH_SRAM
>  #define SPL_ADDR               0x10000
>  #else
>  #define SPL_ADDR               0x0
> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
> index ea0d658..688cb12 100644
> --- a/board/sunxi/Kconfig
> +++ b/board/sunxi/Kconfig
> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
>  config SPL_SERIAL_SUPPORT
>         default y
>
> +config SUNXI_HIGH_SRAM
> +       bool
> +       default n

Write some help text, once written

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 07/13] sunxi: provide ARMv8 mem_map for every ARM64 board

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Every armv8 board needs the memory map, so change the #ifdef to
> ARM64 to avoid enumerating every single board or SoC.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/mach-sunxi/board.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 08/13] SPI: SPL: sunxi: fix 64-bit build

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Addresses passed on to readl and writel are expected to be of the same
> size as a pointer. Change the parameter types of sunxi_spi0_read_data()
> to make the compiler happy and allow a warning-free aarch64 compile.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
> and changing the differing components accordingly.
> This is a preliminary device tree mostly for U-Boot's own sake, it
> is expected to be updated once the official DT gets accepted upstream.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  arch/arm/dts/Makefile                   |   2 +
>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++++++++

Please squash 13/13 with this, I would see a single patch for initial support.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

[Andre Przywara]

Hi Jagan,

thanks for the review!

On 03/02/17 11:04, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
>> while the first SRAM region is mapped at address 0.
>> With the extended physical memory support of the A80 this was changed,
>> so the BROM is now at address 0 and the SRAM region starts right behind
>> this at 64KB. This configuration seems to be called "high SRAM".
>> Instead of enumerating the SoCs which have copied this configuration,
>> let's call a spade a spade and introduce a Kconfig option for this setup.
>> SoCs implementing this (A80, A64 and H5, so far), can then select this
>> configuration.
>> Simplify the config header definition on the way.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>>  arch/arm/include/asm/arch-sunxi/spl.h |  2 +-
>>  board/sunxi/Kconfig                   |  6 ++++++
>>  include/configs/sunxi-common.h        | 19 +++++++------------
>>  3 files changed, 14 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
>> index 5d7ab55..831d0c0 100644
>> --- a/arch/arm/include/asm/arch-sunxi/spl.h
>> +++ b/arch/arm/include/asm/arch-sunxi/spl.h
>> @@ -12,7 +12,7 @@
>>  #define SPL_SIGNATURE          "SPL" /* marks "sunxi" SPL header */
>>  #define SPL_HEADER_VERSION     1
>>
>> -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
>> +#ifdef CONFIG_SUNXI_HIGH_SRAM
>>  #define SPL_ADDR               0x10000
>>  #else
>>  #define SPL_ADDR               0x0
>> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
>> index ea0d658..688cb12 100644
>> --- a/board/sunxi/Kconfig
>> +++ b/board/sunxi/Kconfig
>> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
>>  config SPL_SERIAL_SUPPORT
>>         default y
>>
>> +config SUNXI_HIGH_SRAM
>> +       bool
>> +       default n
> 
> Write some help text, once written

I wanted originally, but then saw that none of the invisible options (no
text after bool) have a help text, mainly because it will probably never
be shown.
I can still add some help text here for documentation purposes, or in
some other place. Or leave it up for the commit message to cover that.

Cheers,
Andre.

> 
> Reviewed-by: Jagan Teki <jagan@openedev.com>
> 
> thanks!
> 

[U-Boot] [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Jagan Teki]

On Feb 1, 2017 2:37 AM, "Andre Przywara" <andre.przywara@arm.com> wrote:

The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.


Can you split this patch with delay line params as separate patch.


Register setup differences between H5 and H3 are courtesy of Jens Kuske.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
 arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97 +++++++++++++++++++++++++++++-
-----
 2 files changed, 82 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 6f96a97..e8e670e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -15,5 +15,6 @@

 #define SOCID_A64      0x1689
 #define SOCID_H3       0x1680
+#define SOCID_H5       0x1718

 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_
sun8i_h3.c
index 9f7cc7f..d681a9d 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
        writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
 }

+static void mctl_set_master_priority_h5(void)
+{
+       struct sunxi_mctl_com_reg * const mctl_com =
+                       (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+       /* enable bandwidth limit windows and set windows size 1us */
+       writel(399, &mctl_com->tmr);
+       writel((1 << 16), &mctl_com->bwcr);


I'm not fond of using direct numerical values make code unhealthy please
use macros with bitops. Note that this comment will apply rest of the code
where it applies.

+
+       /* set cpu high priority */
+       writel(0x00000001, &mctl_com->mapr);
+
+       /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+        * they initialise it */
+       MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
+       MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
+       MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
+       MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
+       MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);
+       MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
+       MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);
+       MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);
+       MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);
+       MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);
+       MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);
+       MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
+}
+
 static void mctl_set_master_priority(uint16_t socid)
 {
        switch (socid) {
@@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
        case SOCID_A64:
                mctl_set_master_priority_a64();
                return;
+       case SOCID_H5:
+               mctl_set_master_priority_h5();
+               return;
        }
 }

@@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid,
struct dram_para *para)

        /* set two rank timing */
        clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
-                       (0x66 << 8) | (0x10 << 0));
+                       ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 <<
0));

        /* set PHY interface timing, write latency and read latency
configure */
        writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
@@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct
dram_para *para)
                                CCM_DRAMCLK_CFG_DIV(1) |
                                CCM_DRAMCLK_CFG_SRC_PLL11 |
                                CCM_DRAMCLK_CFG_UPD);
-       } else if (socid == SOCID_H3) {
+       } else if (socid == SOCID_H3 || socid == SOCID_H5) {
                clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
                clrsetbits_le32(&ccm->dram_clk_cfg,
                                CCM_DRAMCLK_CFG_DIV_MASK |
@@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct
dram_para *para)
        setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
        udelay(10);

-       writel(0xc00e, &mctl_ctl->clken);
+       writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
        udelay(500);
 }

@@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)

        /* setting VTC, default disable all VT */
        clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
-       clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+       if (socid == SOCID_H5)
+               setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
+       else
+               clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);

        /* increase DFI_PHY_UPD clock */
        writel(PROTECT_MAGIC, &mctl_com->protect);
@@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
        udelay(100);

        /* set dramc odt */
-       for (i = 0; i < 4; i++)
-               clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
-                               (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
-                               (0x3 << 14),
-                               IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
-                                       DX_GCR_ODT_DYNAMIC :
DX_GCR_ODT_OFF);
+       for (i = 0; i < 4; i++) {
+               u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
+                               (0x3 << 12) | (0x3 << 14);
+               u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+                               DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
+
+               if (socid == SOCID_H5) {
+                       clearmask |= 0x2 << 8;
+                       setmask |= 0x4 << 8;
+               }
+               clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
+       }

        /* AC PDR should always ON */
-       setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+       clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11)
: 0,
+                       0x1 << 1);

        /* set DQS auto gating PD mode */
        setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
@@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
                /* dphy & aphy phase select 270 degree */
                clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
8),
                                (0x1 << 10) | (0x2 << 8));
-       } else if (socid == SOCID_A64) {
+       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
                /* dphy & aphy phase select ? */
                clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
8),
                                (0x0 << 10) | (0x3 << 8));
@@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)

                mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
                              PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
-       } else if (socid == SOCID_A64) {
+       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
                clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);

                mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL |
PIR_PHYRST |
                              PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
+               /* no PIR_QSGATE for H5 ???? */
        }

        /* detect ranks and bus width */
@@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
        /* set PGCR3, CKE polarity */
        if (socid == SOCID_H3)
                writel(0x00aa0060, &mctl_ctl->pgcr[3]);
-       else if (socid == SOCID_A64)
+       else if (socid == SOCID_A64 || socid == SOCID_H5)
                writel(0xc0aa0060, &mctl_ctl->pgcr[3]);

        /* power down zq calibration module for power save */
@@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct
dram_para *para)
           3,  4,  0,  3,  4,  1,  4,  0,                       \
           1,  1,  0,  1, 13,  5,  4      }

+#define SUN8I_H5_DX_READ_DELAYS                                        \
+       {{ 14, 15, 17, 17, 17, 17, 17, 18, 17,  3,  3 },        \
+        { 21, 21, 12, 22, 21, 21, 21, 21, 21,  3,  3 },        \
+        { 16, 19, 19, 17, 22, 22, 21, 22, 19,  3,  3 },        \
+        { 21, 21, 22, 22, 20, 21, 19, 19, 19,  3,  3 } }
+#define SUN8I_H5_DX_WRITE_DELAYS                               \
+       {{  1,  2,  3,  4,  3,  4,  4,  4,  6,  6,  6 },        \
+        {  6,  6,  6,  5,  5,  5,  5,  5,  6,  6,  6 },        \
+        {  0,  2,  4,  2,  6,  5,  5,  5,  6,  6,  6 },        \
+        {  3,  3,  3,  2,  2,  1,  1,  1,  4,  4,  4 } }
+#define SUN8I_H5_AC_DELAYS                                     \
+       {  0,  0,  5,  5,  0,  0,  0,  0,                       \
+          0,  0,  0,  0,  3,  3,  3,  3,                       \
+          3,  3,  3,  3,  3,  3,  3,  3,                       \
+          3,  3,  3,  3,  2,  0,  0      }
+
 unsigned long sunxi_dram_init(void)
 {
        struct sunxi_mctl_com_reg * const mctl_com =
@@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void)
                .dx_read_delays  = SUN50I_A64_DX_READ_DELAYS,
                .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
                .ac_delays       = SUN50I_A64_AC_DELAYS,
+#elif defined(CONFIG_MACH_SUN50I_H5)
+               .dx_read_delays  = SUN8I_H5_DX_READ_DELAYS,
+               .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
+               .ac_delays       = SUN8I_H5_AC_DELAYS,
 #endif
        };
 /*
@@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void)
        uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN50I)
        uint16_t socid = SOCID_A64;
+#elif defined(CONFIG_MACH_SUN50I_H5)
+       uint16_t socid = SOCID_H5;
 #endif

        mctl_sys_init(socid, &para);
@@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void)
        if (socid ==

[U-Boot] [linux-sunxi] Re: [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Chen-Yu Tsai]

Hi,

On Fri, Feb 3, 2017 at 11:26 PM, Jagan Teki <jagan@openedev.com> wrote:
> On Feb 1, 2017 2:37 AM, "Andre Przywara" <andre.przywara@arm.com> wrote:
>
> The DRAM controller in the Allwinner H5 SoC is again very similar to
> the one in the H3 and A64.
> Based on the existing socid parameter, add support for this controller
> by reusing the bulk of the code and only deviating where needed.
> These new bits set or cleared here and there have been mostly found by
> looking at DRAM register dumps after using the H5 boot0 and comparing
> them to what we set in the code. So for now it's mostly unclear what
> those bits actually mean - hence the missing names and comments.
> Also add the delay line parameters taken from the boot0 and libdram
> disassembly.
>
>
> Can you split this patch with delay line params as separate patch.

It looks like the delay lines are for the H5, merely taken from
different sources. They are and should be part of the same patch
adding support for DRAM on the H5.

>
> Register setup differences between H5 and H3 are courtesy of Jens Kuske.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
>  arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97
> +++++++++++++++++++++++++++++------
>  2 files changed, 82 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 6f96a97..e8e670e 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -15,5 +15,6 @@
>
>  #define SOCID_A64      0x1689
>  #define SOCID_H3       0x1680
> +#define SOCID_H5       0x1718
>
>  #endif /* _SUNXI_CPU_H */
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
> b/arch/arm/mach-sunxi/dram_sun8i_h3.c
> index 9f7cc7f..d681a9d 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
> @@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
>         writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
>  }
>
> +static void mctl_set_master_priority_h5(void)
> +{
> +       struct sunxi_mctl_com_reg * const mctl_com =
> +                       (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
> +
> +       /* enable bandwidth limit windows and set windows size 1us */
> +       writel(399, &mctl_com->tmr);
> +       writel((1 << 16), &mctl_com->bwcr);
>
>
> I'm not fond of using direct numerical values make code unhealthy please use
> macros with bitops. Note that this comment will apply rest of the code where
> it applies.

I think you are being unreasonable. The commit message clearly states that
the added code either comes from register dumps, disassembled blobs, or
comparison of released code:

"""
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
"""

For this particular instance, see

https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/u-boot-sunxi/arch/arm/cpu/armv7/sun8iw11p1/dram/lib-dram/mctl_hal.c#L197

which gives the exact same comment, and no named macros. Adding a macro
for it and calling it H5_DRAM_BW_UNKNOWN_MAGIC is not an improvement.
Same goes for the next few lines.

Allwinner has _never_ released documents for the DRAM controllers or DRAM PHYs,
and only sometimes releases code for DRAM init for some SoCs, sometimes with
questionable licenses (or lack of), of which some don't match what is actually
seen in provided blobs. Considering what the community has access to. This
patch seems to be quite good.

Regards
ChenYu

>
> +
> +       /* set cpu high priority */
> +       writel(0x00000001, &mctl_com->mapr);
> +
> +       /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
> +        * they initialise it */
> +       MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
> +       MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
> +       MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
> +       MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
> +       MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);
> +       MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
> +       MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);
> +       MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);
> +       MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);
> +       MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);
> +       MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);
> +       MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
> +}
> +
>  static void mctl_set_master_priority(uint16_t socid)
>  {
>         switch (socid) {
> @@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
>         case SOCID_A64:
>                 mctl_set_master_priority_a64();
>                 return;
> +       case SOCID_H5:
> +               mctl_set_master_priority_h5();
> +               return;
>         }
>  }
>
> @@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid,
> struct dram_para *para)
>
>         /* set two rank timing */
>         clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
> -                       (0x66 << 8) | (0x10 << 0));
> +                       ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 <<
> 0));
>
>         /* set PHY interface timing, write latency and read latency
> configure */
>         writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
> @@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct
> dram_para *para)
>                                 CCM_DRAMCLK_CFG_DIV(1) |
>                                 CCM_DRAMCLK_CFG_SRC_PLL11 |
>                                 CCM_DRAMCLK_CFG_UPD);
> -       } else if (socid == SOCID_H3) {
> +       } else if (socid == SOCID_H3 || socid == SOCID_H5) {
>                 clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
>                 clrsetbits_le32(&ccm->dram_clk_cfg,
>                                 CCM_DRAMCLK_CFG_DIV_MASK |
> @@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct
> dram_para *para)
>         setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
>         udelay(10);
>
> -       writel(0xc00e, &mctl_ctl->clken);
> +       writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
>         udelay(500);
>  }
>
> @@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct
> dram_para *para)
>
>         /* setting VTC, default disable all VT */
>         clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
> -       clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
> +       if (socid == SOCID_H5)
> +               setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
> +       else
> +               clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
>
>         /* increase DFI_PHY_UPD clock */
>         writel(PROTECT_MAGIC, &mctl_com->protect);
> @@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct
> dram_para *para)
>         udelay(100);
>
>         /* set dramc odt */
> -       for (i = 0; i < 4; i++)
> -               clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
> -                               (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
> -                               (0x3 << 14),
> -                               IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
> -                                       DX_GCR_ODT_DYNAMIC :
> DX_GCR_ODT_OFF);
> +       for (i = 0; i < 4; i++) {
> +               u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
> +                               (0x3 << 12) | (0x3 << 14);
> +               u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
> +                               DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
> +
> +               if (socid == SOCID_H5) {
> +                       clearmask |= 0x2 << 8;
> +                       setmask |= 0x4 << 8;
> +               }
> +               clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
> +       }
>
>         /* AC PDR should always ON */
> -       setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
> +       clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) :
> 0,
> +                       0x1 << 1);
>
>         /* set DQS auto gating PD mode */
>         setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
> @@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct
> dram_para *para)
>                 /* dphy & aphy phase select 270 degree */
>                 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
> 8),
>                                 (0x1 << 10) | (0x2 << 8));
> -       } else if (socid == SOCID_A64) {
> +       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
>                 /* dphy & aphy phase select ? */
>                 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
> 8),
>                                 (0x0 << 10) | (0x3 << 8));
> @@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct
> dram_para *para)
>
>                 mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
>                               PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
> -       } else if (socid == SOCID_A64) {
> +       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
>                 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
>
>                 mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST
> |
>                               PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
> +               /* no PIR_QSGATE for H5 ???? */
>         }
>
>         /* detect ranks and bus width */
> @@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct
> dram_para *para)
>         /* set PGCR3, CKE polarity */
>         if (socid == SOCID_H3)
>                 writel(0x00aa0060, &mctl_ctl->pgcr[3]);
> -       else if (socid == SOCID_A64)
> +       else if (socid == SOCID_A64 || socid == SOCID_H5)
>                 writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
>
>         /* power down zq calibration module for power save */
> @@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para
> *para)
>            3,  4,  0,  3,  4,  1,  4,  0,                       \
>            1,  1,  0,  1, 13,  5,  4      }
>
> +#define SUN8I_H5_DX_READ_DELAYS                                        \
> +       {{ 14, 15, 17, 17, 17, 17, 17, 18, 17,  3,  3 },        \
> +        { 21, 21, 12, 22, 21, 21, 21, 21, 21,  3,  3 },        \
> +        { 16, 19, 19, 17, 22, 22, 21, 22, 19,  3,  3 },        \
> +        { 21, 21, 22, 22, 20, 21, 19, 19, 19,  3,  3 } }
> +#define SUN8I_H5_DX_WRITE_DELAYS                               \
> +       {{  1,  2,  3,  4,  3,  4,  4,  4,  6,  6,  6 },        \
> +        {  6,  6,  6,  5,  5,  5,  5,  5,  6,  6,  6 },        \
> +        {  0,  2,  4,  2,  6,  5,  5,  5,  6,  6,  6 },        \
> +        {  3,  3,  3,  2,  2,  1,  1,  1,  4,  4,  4 } }
> +#define SUN8I_H5_AC_DELAYS                                     \
> +       {  0,  0,  5,  5,  0,  0,  0,  0,                       \
> +          0,  0,  0,  0,  3,  3,  3,  3,                       \
> +          3,  3,  3,  3,  3,  3,  3,  3,                       \
> +          3,  3,  3,  3,  2,  0,  0      }
> +
>  unsigned long sunxi_dram_init(void)
>  {
>         struct sunxi_mctl_com_reg * const mctl_com =
> @@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void)
>                 .dx_read_delays  = SUN50I_A64_DX_READ_DELAYS,
>                 .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
>                 .ac_delays       = SUN50I_A64_AC_DELAYS,
> +#elif defined(CONFIG_MACH_SUN50I_H5)
> +               .dx_read_delays  = SUN8I_H5_DX_READ_DELAYS,
> +               .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
> +               .ac_delays       = SUN8I_H5_AC_DELAYS,
>  #endif
>         };
>  /*
> @@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void)
>         uint16_t socid = SOCID_H3;
>  #elif defined(CONFIG_MACH_SUN50I)
>         uint16_t socid = SOCID_A64;
> +#elif defined(CONFIG_MACH_SUN50I_H5)
> +       uint16_t socid = SOCID_H5;
>  #endif
>
>         mctl_sys_init(socid, &para);
> @@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void)
>         if (socid ==
>
>
> --
> You received this message because you are subscribed to the Google Groups
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> To unsubscribe from this group and stop receiving emails from it, send an
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[U-Boot] [linux-sunxi] Re: [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Andre Przywara]

Hi,

Chen-Yu, thanks for your comments.

On 03/02/17 16:36, Chen-Yu Tsai wrote:
> Hi,
> 
> On Fri, Feb 3, 2017 at 11:26 PM, Jagan Teki <jagan@openedev.com> wrote:
>> On Feb 1, 2017 2:37 AM, "Andre Przywara" <andre.przywara@arm.com> wrote:
>>
>> The DRAM controller in the Allwinner H5 SoC is again very similar to
>> the one in the H3 and A64.
>> Based on the existing socid parameter, add support for this controller
>> by reusing the bulk of the code and only deviating where needed.
>> These new bits set or cleared here and there have been mostly found by
>> looking at DRAM register dumps after using the H5 boot0 and comparing
>> them to what we set in the code. So for now it's mostly unclear what
>> those bits actually mean - hence the missing names and comments.
>> Also add the delay line parameters taken from the boot0 and libdram
>> disassembly.
>>
>>
>> Can you split this patch with delay line params as separate patch.
> 
> It looks like the delay lines are for the H5, merely taken from
> different sources. They are and should be part of the same patch
> adding support for DRAM on the H5.

Yeah, I think they really belong into this patch. I don't see how
separating them would help, short of creating bisectability problems.

>>
>> Register setup differences between H5 and H3 are courtesy of Jens Kuske.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>>  arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
>>  arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97
>> +++++++++++++++++++++++++++++------
>>  2 files changed, 82 insertions(+), 16 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
>> b/arch/arm/include/asm/arch-sunxi/cpu.h
>> index 6f96a97..e8e670e 100644
>> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
>> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
>> @@ -15,5 +15,6 @@
>>
>>  #define SOCID_A64      0x1689
>>  #define SOCID_H3       0x1680
>> +#define SOCID_H5       0x1718
>>
>>  #endif /* _SUNXI_CPU_H */
>> diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
>> b/arch/arm/mach-sunxi/dram_sun8i_h3.c
>> index 9f7cc7f..d681a9d 100644
>> --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
>> +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
>> @@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
>>         writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
>>  }
>>
>> +static void mctl_set_master_priority_h5(void)
>> +{
>> +       struct sunxi_mctl_com_reg * const mctl_com =
>> +                       (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
>> +
>> +       /* enable bandwidth limit windows and set windows size 1us */
>> +       writel(399, &mctl_com->tmr);
>> +       writel((1 << 16), &mctl_com->bwcr);
>>
>>
>> I'm not fond of using direct numerical values make code unhealthy please use
>> macros with bitops. Note that this comment will apply rest of the code where
>> it applies.
> 
> I think you are being unreasonable. The commit message clearly states that
> the added code either comes from register dumps, disassembled blobs, or
> comparison of released code:
> 
> """
> These new bits set or cleared here and there have been mostly found by
> looking at DRAM register dumps after using the H5 boot0 and comparing
> them to what we set in the code. So for now it's mostly unclear what
> those bits actually mean - hence the missing names and comments.
> """
> 
> For this particular instance, see
> 
> https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/u-boot-sunxi/arch/arm/cpu/armv7/sun8iw11p1/dram/lib-dram/mctl_hal.c#L197
> 
> which gives the exact same comment, and no named macros. Adding a macro
> for it and calling it H5_DRAM_BW_UNKNOWN_MAGIC is not an improvement.
> Same goes for the next few lines.
> 
> Allwinner has _never_ released documents for the DRAM controllers or DRAM PHYs,
> and only sometimes releases code for DRAM init for some SoCs, sometimes with
> questionable licenses (or lack of), of which some don't match what is actually
> seen in provided blobs. Considering what the community has access to. This
> patch seems to be quite good.

I think we have some sort of rewrite of this code ahead of us anyway,
hopefully we can address some of these points then in a reasonable manner.
But until then I'd like to keep it at "399" instead of using
WINDOW_SIZE_1US or _guessing_ how this is computed from some frequency.

Cheers,
Andre.

>>
>> +
>> +       /* set cpu high priority */
>> +       writel(0x00000001, &mctl_com->mapr);
>> +
>> +       /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
>> +        * they initialise it */
>> +       MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
>> +       MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
>> +       MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
>> +       MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
>> +       MBUS_CONF(    VE, true, HIGHEST, 0, 1900, 1500, 1000);
>> +       MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
>> +       MBUS_CONF(  NAND, true,    HIGH, 0,  256,  128,   64);
>> +       MBUS_CONF(    SS, true, HIGHEST, 0,  256,  128,   64);
>> +       MBUS_CONF(    TS, true, HIGHEST, 0,  256,  128,   64);
>> +       MBUS_CONF(    DI, true,    HIGH, 0, 1024,  256,   64);
>> +       MBUS_CONF(    DE, true, HIGHEST, 3, 3400, 2400, 1024);
>> +       MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
>> +}
>> +
>>  static void mctl_set_master_priority(uint16_t socid)
>>  {
>>         switch (socid) {
>> @@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
>>         case SOCID_A64:
>>                 mctl_set_master_priority_a64();
>>                 return;
>> +       case SOCID_H5:
>> +               mctl_set_master_priority_h5();
>> +               return;
>>         }
>>  }
>>
>> @@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid,
>> struct dram_para *para)
>>
>>         /* set two rank timing */
>>         clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
>> -                       (0x66 << 8) | (0x10 << 0));
>> +                       ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 <<
>> 0));
>>
>>         /* set PHY interface timing, write latency and read latency
>> configure */
>>         writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
>> @@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct
>> dram_para *para)
>>                                 CCM_DRAMCLK_CFG_DIV(1) |
>>                                 CCM_DRAMCLK_CFG_SRC_PLL11 |
>>                                 CCM_DRAMCLK_CFG_UPD);
>> -       } else if (socid == SOCID_H3) {
>> +       } else if (socid == SOCID_H3 || socid == SOCID_H5) {
>>                 clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
>>                 clrsetbits_le32(&ccm->dram_clk_cfg,
>>                                 CCM_DRAMCLK_CFG_DIV_MASK |
>> @@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct
>> dram_para *para)
>>         setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
>>         udelay(10);
>>
>> -       writel(0xc00e, &mctl_ctl->clken);
>> +       writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
>>         udelay(500);
>>  }
>>
>> @@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct
>> dram_para *para)
>>
>>         /* setting VTC, default disable all VT */
>>         clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
>> -       clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
>> +       if (socid == SOCID_H5)
>> +               setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
>> +       else
>> +               clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
>>
>>         /* increase DFI_PHY_UPD clock */
>>         writel(PROTECT_MAGIC, &mctl_com->protect);
>> @@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct
>> dram_para *para)
>>         udelay(100);
>>
>>         /* set dramc odt */
>> -       for (i = 0; i < 4; i++)
>> -               clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
>> -                               (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
>> -                               (0x3 << 14),
>> -                               IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
>> -                                       DX_GCR_ODT_DYNAMIC :
>> DX_GCR_ODT_OFF);
>> +       for (i = 0; i < 4; i++) {
>> +               u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
>> +                               (0x3 << 12) | (0x3 << 14);
>> +               u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
>> +                               DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
>> +
>> +               if (socid == SOCID_H5) {
>> +                       clearmask |= 0x2 << 8;
>> +                       setmask |= 0x4 << 8;
>> +               }
>> +               clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
>> +       }
>>
>>         /* AC PDR should always ON */
>> -       setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
>> +       clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) :
>> 0,
>> +                       0x1 << 1);
>>
>>         /* set DQS auto gating PD mode */
>>         setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
>> @@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct
>> dram_para *para)
>>                 /* dphy & aphy phase select 270 degree */
>>                 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
>> 8),
>>                                 (0x1 << 10) | (0x2 << 8));
>> -       } else if (socid == SOCID_A64) {
>> +       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
>>                 /* dphy & aphy phase select ? */
>>                 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 <<
>> 8),
>>                                 (0x0 << 10) | (0x3 << 8));
>> @@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct
>> dram_para *para)
>>
>>                 mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
>>                               PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
>> -       } else if (socid == SOCID_A64) {
>> +       } else if (socid == SOCID_A64 || socid == SOCID_H5) {
>>                 clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
>>
>>                 mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST
>> |
>>                               PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
>> +               /* no PIR_QSGATE for H5 ???? */
>>         }
>>
>>         /* detect ranks and bus width */
>> @@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct
>> dram_para *para)
>>         /* set PGCR3, CKE polarity */
>>         if (socid == SOCID_H3)
>>                 writel(0x00aa0060, &mctl_ctl->pgcr[3]);
>> -       else if (socid == SOCID_A64)
>> +       else if (socid == SOCID_A64 || socid == SOCID_H5)
>>                 writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
>>
>>         /* power down zq calibration module for power save */
>> @@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para
>> *para)
>>            3,  4,  0,  3,  4,  1,  4,  0,                       \
>>            1,  1,  0,  1, 13,  5,  4      }
>>
>> +#define SUN8I_H5_DX_READ_DELAYS                                        \
>> +       {{ 14, 15, 17, 17, 17, 17, 17, 18, 17,  3,  3 },        \
>> +        { 21, 21, 12, 22, 21, 21, 21, 21, 21,  3,  3 },        \
>> +        { 16, 19, 19, 17, 22, 22, 21, 22, 19,  3,  3 },        \
>> +        { 21, 21, 22, 22, 20, 21, 19, 19, 19,  3,  3 } }
>> +#define SUN8I_H5_DX_WRITE_DELAYS                               \
>> +       {{  1,  2,  3,  4,  3,  4,  4,  4,  6,  6,  6 },        \
>> +        {  6,  6,  6,  5,  5,  5,  5,  5,  6,  6,  6 },        \
>> +        {  0,  2,  4,  2,  6,  5,  5,  5,  6,  6,  6 },        \
>> +        {  3,  3,  3,  2,  2,  1,  1,  1,  4,  4,  4 } }
>> +#define SUN8I_H5_AC_DELAYS                                     \
>> +       {  0,  0,  5,  5,  0,  0,  0,  0,                       \
>> +          0,  0,  0,  0,  3,  3,  3,  3,                       \
>> +          3,  3,  3,  3,  3,  3,  3,  3,                       \
>> +          3,  3,  3,  3,  2,  0,  0      }
>> +
>>  unsigned long sunxi_dram_init(void)
>>  {
>>         struct sunxi_mctl_com_reg * const mctl_com =
>> @@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void)
>>                 .dx_read_delays  = SUN50I_A64_DX_READ_DELAYS,
>>                 .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
>>                 .ac_delays       = SUN50I_A64_AC_DELAYS,
>> +#elif defined(CONFIG_MACH_SUN50I_H5)
>> +               .dx_read_delays  = SUN8I_H5_DX_READ_DELAYS,
>> +               .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
>> +               .ac_delays       = SUN8I_H5_AC_DELAYS,
>>  #endif
>>         };
>>  /*
>> @@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void)
>>         uint16_t socid = SOCID_H3;
>>  #elif defined(CONFIG_MACH_SUN50I)
>>         uint16_t socid = SOCID_A64;
>> +#elif defined(CONFIG_MACH_SUN50I_H5)
>> +       uint16_t socid = SOCID_H5;
>>  #endif
>>
>>         mctl_sys_init(socid, &para);
>> @@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void)
>>         if (socid ==
>>
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to linux-sunxi+unsubscribe at googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

[U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Andre Przywara]

Hi,

On 03/02/17 11:14, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
>> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
>> and changing the differing components accordingly.
>> This is a preliminary device tree mostly for U-Boot's own sake, it
>> is expected to be updated once the official DT gets accepted upstream.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>  arch/arm/dts/Makefile                   |   2 +
>>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++++++++
> 
> Please squash 13/13 with this, I would see a single patch for initial support.

How comes?
I think those two are really separate topics, and having a DT file in
this directory really doesn't hurt anything, until it actually gets
referenced in the next patch.
I'd keep DT patches separate, really, and in general always would prefer
more, but smaller patches to fewer, but bigger ones.

Cheers,
Andre.

[U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Andre Przywara]

Hi,

On 03/02/17 10:52, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> Instead of enumerating all SoC families that need that bit set, let's
>> just express this more clearly: The SMP bits needs to be set on
>> SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
>> other way round, so we use ! CPU_IS_UP and ! ARM64.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>>  arch/arm/Kconfig            | 4 ++++
>>  arch/arm/mach-sunxi/board.c | 5 +----
>>  board/sunxi/Kconfig         | 2 ++
>>  3 files changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index fc36723..98791c0 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
>>           ARM_SOC_BOOT0_HOOK which contains the required assembler
>>           preprocessor code.
>>
>> +config ARM_CORTEX_CPU_IS_UP
>> +       bool
>> +       default n
> 
> Better to place this in sunxi, since no other code using this expect
> sunxi and the name CORTEX may also refer arm64 use something 32
> related.

Sigh, can you please check back with Maxime on what's the right thing here?
http://lists.denx.de/pipermail/u-boot/2017-January/279417.html

If it's about the name, shall we use ARM_CORTEX_V7_CPU_IS_UP?

I was briefly tempted to unify all ACTLR.SMP bit sets from all over the
ARM code, but this looks like a can of worms to me, so I'd rather keep
this one closed.

Cheers,
Andre.

[U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Maxime Ripard]

On Mon, Feb 06, 2017 at 10:18:14AM +0000, Andre Przywara wrote:
> Hi,
> 
> On 03/02/17 11:14, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> >> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
> >> and changing the differing components accordingly.
> >> This is a preliminary device tree mostly for U-Boot's own sake, it
> >> is expected to be updated once the official DT gets accepted upstream.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >> ---
> >>  arch/arm/dts/Makefile                   |   2 +
> >>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++++++++
> > 
> > Please squash 13/13 with this, I would see a single patch for initial support.
> 
> How comes?
> I think those two are really separate topics, and having a DT file in
> this directory really doesn't hurt anything, until it actually gets
> referenced in the next patch.
> I'd keep DT patches separate, really, and in general always would prefer
> more, but smaller patches to fewer, but bigger ones.

I concur.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Maxime Ripard]

On Mon, Feb 06, 2017 at 11:29:26AM +0000, Andre Przywara wrote:
> Hi,
> 
> On 03/02/17 10:52, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> Instead of enumerating all SoC families that need that bit set, let's
> >> just express this more clearly: The SMP bits needs to be set on
> >> SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
> >> other way round, so we use ! CPU_IS_UP and ! ARM64.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >>  arch/arm/Kconfig            | 4 ++++
> >>  arch/arm/mach-sunxi/board.c | 5 +----
> >>  board/sunxi/Kconfig         | 2 ++
> >>  3 files changed, 7 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index fc36723..98791c0 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
> >>           ARM_SOC_BOOT0_HOOK which contains the required assembler
> >>           preprocessor code.
> >>
> >> +config ARM_CORTEX_CPU_IS_UP
> >> +       bool
> >> +       default n
> > 
> > Better to place this in sunxi, since no other code using this expect
> > sunxi and the name CORTEX may also refer arm64 use something 32
> > related.
> 
> Sigh, can you please check back with Maxime on what's the right thing here?
> http://lists.denx.de/pipermail/u-boot/2017-January/279417.html
> 
> If it's about the name, shall we use ARM_CORTEX_V7_CPU_IS_UP?
> 
> I was briefly tempted to unify all ACTLR.SMP bit sets from all over the
> ARM code, but this looks like a can of worms to me, so I'd rather keep
> this one closed.

There's at least one other SoC in a similar situation (imx7 solo), so
I think it should really be made generic. I don't really care about
the name though, but keeping it in sunxi is just creating yet another
candidate for a duplicated and redundant option.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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