[PATCH 05/12] MIPS: BRIDGE: Clean-up bridge.h header file

[Joshua Kinard <kumba@gentoo.org>]

From: Joshua Kinard <kumba@gentoo.org>

Apply a number of clean-ups to arch/mips/include/asm/pci/bridge.h:
 - Replace (0x1 << x) shifts with BIT(x) or BIT_ULL
 - Replace (mask << x) shifts with GENMASK or GENMASK_ULL
 - Clean-up several multi-line macros for readability
 - Other whitespace and comment fixes as needed

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
---
 arch/mips/include/asm/pci/bridge.h | 520 ++++++++++++++-------------
 1 file changed, 280 insertions(+), 240 deletions(-)

diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index 3206245d1ed6..248a390e89b3 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -388,79 +388,80 @@ typedef struct bridge_err_cmdword_s {
  *    Bridge register bit field definitions
  */
 
-/* Widget part number of bridge */
+/* Widget part numbers. */
 #define BRIDGE_WIDGET_PART_NUM		0xc002
 #define XBRIDGE_WIDGET_PART_NUM		0xd002
 
-/* Manufacturer of bridge */
+/* Widget manufacturer numbers. */
 #define BRIDGE_WIDGET_MFGR_NUM		0x036
 #define XBRIDGE_WIDGET_MFGR_NUM		0x024
 
-/* Revision numbers for known Bridge revisions */
+/* Widget revision numbers. */
 #define BRIDGE_REV_A			0x1
 #define BRIDGE_REV_B			0x2
 #define BRIDGE_REV_C			0x3
 #define BRIDGE_REV_D			0x4
 
 /* Bridge widget status register bits definition */
-
-#define BRIDGE_STAT_LLP_REC_CNT		(0xFFu << 24)
-#define BRIDGE_STAT_LLP_TX_CNT		(0xFF << 16)
-#define BRIDGE_STAT_FLASH_SELECT	(0x1 << 6)
-#define BRIDGE_STAT_PCI_GIO_N		(0x1 << 5)
-#define BRIDGE_STAT_PENDING		(0x1F << 0)
+#define BRIDGE_STAT_LLP_REC_CNT		GENMASK(31, 24)
+#define BRIDGE_STAT_LLP_TX_CNT		GENMASK(23, 16)
+#define BRIDGE_STAT_FLASH_SELECT	BIT(6)
+#define BRIDGE_STAT_PCI_GIO_N		BIT(5)
+#define BRIDGE_STAT_PENDING		GENMASK(4, 0)
 
 /* Bridge widget control register bits definition */
-#define BRIDGE_CTRL_FLASH_WR_EN		(0x1ul << 31)
-#define BRIDGE_CTRL_EN_CLK50		(0x1 << 30)
-#define BRIDGE_CTRL_EN_CLK40		(0x1 << 29)
-#define BRIDGE_CTRL_EN_CLK33		(0x1 << 28)
+#define BRIDGE_CTRL_FLASH_WR_EN		BIT(31)
+#define BRIDGE_CTRL_EN_CLK50		BIT(30)
+#define BRIDGE_CTRL_EN_CLK40		BIT(29)
+#define BRIDGE_CTRL_EN_CLK33		BIT(28)
 #define BRIDGE_CTRL_RST(n)		((n) << 24)
-#define BRIDGE_CTRL_RST_MASK		(BRIDGE_CTRL_RST(0xF))
-#define BRIDGE_CTRL_RST_PIN(x)		(BRIDGE_CTRL_RST(0x1 << (x)))
-#define BRIDGE_CTRL_IO_SWAP		(0x1 << 23)
-#define BRIDGE_CTRL_MEM_SWAP		(0x1 << 22)
-#define BRIDGE_CTRL_PAGE_SIZE		(0x1 << 21)
-#define BRIDGE_CTRL_SS_PAR_BAD		(0x1 << 20)
-#define BRIDGE_CTRL_SS_PAR_EN		(0x1 << 19)
+#define BRIDGE_CTRL_RST_MASK		GENMASK(27, 24)
+#define BRIDGE_CTRL_RST_PIN(x)		(BRIDGE_CTRL_RST(1UL << (x)))
+#define BRIDGE_CTRL_IO_SWAP		BIT(23)
+#define BRIDGE_CTRL_MEM_SWAP		BIT(22)
+#define BRIDGE_CTRL_PAGE_SIZE		BIT(21)
+#define BRIDGE_CTRL_SS_PAR_BAD		BIT(20)
+#define BRIDGE_CTRL_SS_PAR_EN		BIT(19)
 #define BRIDGE_CTRL_SSRAM_SIZE(n)	((n) << 17)
 #define BRIDGE_CTRL_SSRAM_SIZE_MASK	(BRIDGE_CTRL_SSRAM_SIZE(0x3))
 #define BRIDGE_CTRL_SSRAM_512K		(BRIDGE_CTRL_SSRAM_SIZE(0x3))
 #define BRIDGE_CTRL_SSRAM_128K		(BRIDGE_CTRL_SSRAM_SIZE(0x2))
 #define BRIDGE_CTRL_SSRAM_64K		(BRIDGE_CTRL_SSRAM_SIZE(0x1))
 #define BRIDGE_CTRL_SSRAM_1K		(BRIDGE_CTRL_SSRAM_SIZE(0x0))
-#define BRIDGE_CTRL_F_BAD_PKT		(0x1 << 16)
+#define BRIDGE_CTRL_F_BAD_PKT		BIT(16)
 #define BRIDGE_CTRL_LLP_XBAR_CRD(n)	((n) << 12)
 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK	(BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
-#define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)
-#define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)
-#define BRIDGE_CTRL_SYS_END		(0x1 << 9)
+#define BRIDGE_CTRL_CLR_RLLP_CNT	BIT(11)
+#define BRIDGE_CTRL_CLR_TLLP_CNT	BIT(10)
+#define BRIDGE_CTRL_SYS_END		BIT(9)
 #define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)
 #define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))
 #define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)
 #define BRIDGE_CTRL_WIDGET_ID_MASK	(BRIDGE_CTRL_WIDGET_ID(0xf))
 
 /* Bridge Response buffer Error Upper Register bit fields definition */
-#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
-#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
-#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
-#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
-#define BRIDGE_RESP_ERRRUPPR_BUFMASK	(0xFFFF)
-
-#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)	\
-			(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
-				BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
-
-#define BRIDGE_RESP_ERRUPPR_DEVICE(x)	\
-			(((x) &	 BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
-				 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT	(20)
+#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK					\
+	(0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT	(16)
+#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK					\
+	(0xf << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+#define BRIDGE_RESP_ERRRUPPR_BUFMASK	(0xffff)
+
+#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)					\
+	(((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >>			\
+		BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
+
+#define BRIDGE_RESP_ERRUPPR_DEVICE(x)					\
+	(((x) &	 BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >>			\
+		 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
 
 /* Bridge direct mapping register bits definition */
 #define BRIDGE_DIRMAP_W_ID_SHFT		20
-#define BRIDGE_DIRMAP_W_ID		(0xf << BRIDGE_DIRMAP_W_ID_SHFT)
-#define BRIDGE_DIRMAP_RMF_64		(0x1 << 18)
-#define BRIDGE_DIRMAP_ADD512		(0x1 << 17)
-#define BRIDGE_DIRMAP_OFF		(0x1ffff << 0)
+#define BRIDGE_DIRMAP_W_ID		GENMASK(23, BRIDGE_DIRMAP_W_ID_SHFT)
+#define BRIDGE_DIRMAP_RMF_64		BIT(18)
+#define BRIDGE_DIRMAP_ADD512		BIT(17)
+#define BRIDGE_DIRMAP_OFF		GENMASK(16, 0)
 #define BRIDGE_DIRMAP_OFF_ADDRSHFT	(31)	/* lsbit of DIRMAP_OFF is xtalk address bit 31 */
 
 /* Bridge Arbitration register bits definition */
@@ -468,85 +469,98 @@ typedef struct bridge_err_cmdword_s {
 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK	BRIDGE_ARB_REQ_WAIT_TICK(0x3)
 #define BRIDGE_ARB_REQ_WAIT_EN(x)	((x) << 8)
 #define BRIDGE_ARB_REQ_WAIT_EN_MASK	BRIDGE_ARB_REQ_WAIT_EN(0xff)
-#define BRIDGE_ARB_FREEZE_GNT		(1 << 6)
-#define BRIDGE_ARB_HPRI_RING_B2		(1 << 5)
-#define BRIDGE_ARB_HPRI_RING_B1		(1 << 4)
-#define BRIDGE_ARB_HPRI_RING_B0		(1 << 3)
-#define BRIDGE_ARB_LPRI_RING_B2		(1 << 2)
-#define BRIDGE_ARB_LPRI_RING_B1		(1 << 1)
-#define BRIDGE_ARB_LPRI_RING_B0		(1 << 0)
+#define BRIDGE_ARB_FREEZE_GNT		BIT(6)
+#define BRIDGE_ARB_HPRI_RING_B2		BIT(5)
+#define BRIDGE_ARB_HPRI_RING_B1		BIT(4)
+#define BRIDGE_ARB_HPRI_RING_B0		BIT(3)
+#define BRIDGE_ARB_LPRI_RING_B2		BIT(2)
+#define BRIDGE_ARB_LPRI_RING_B1		BIT(1)
+#define BRIDGE_ARB_LPRI_RING_B0		BIT(0)
 
 /* Bridge Bus time-out register bits definition */
 #define BRIDGE_BUS_PCI_RETRY_HLD(x)	((x) << 16)
 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK	BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
-#define BRIDGE_BUS_GIO_TIMEOUT		(1 << 12)
+#define BRIDGE_BUS_GIO_TIMEOUT		BIT(12)
 #define BRIDGE_BUS_PCI_RETRY_CNT(x)	((x) << 0)
 #define BRIDGE_BUS_PCI_RETRY_MASK	BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
 
 /* Bridge interrupt status register bits definition */
-#define BRIDGE_ISR_MULTI_ERR		(0x1u << 31)
-#define BRIDGE_ISR_PMU_ESIZE_FAULT	(0x1 << 30)
-#define BRIDGE_ISR_UNEXP_RESP		(0x1 << 29)
-#define BRIDGE_ISR_BAD_XRESP_PKT	(0x1 << 28)
-#define BRIDGE_ISR_BAD_XREQ_PKT		(0x1 << 27)
-#define BRIDGE_ISR_RESP_XTLK_ERR	(0x1 << 26)
-#define BRIDGE_ISR_REQ_XTLK_ERR		(0x1 << 25)
-#define BRIDGE_ISR_INVLD_ADDR		(0x1 << 24)
-#define BRIDGE_ISR_UNSUPPORTED_XOP	(0x1 << 23)
-#define BRIDGE_ISR_XREQ_FIFO_OFLOW	(0x1 << 22)
-#define BRIDGE_ISR_LLP_REC_SNERR	(0x1 << 21)
-#define BRIDGE_ISR_LLP_REC_CBERR	(0x1 << 20)
-#define BRIDGE_ISR_LLP_RCTY		(0x1 << 19)
-#define BRIDGE_ISR_LLP_TX_RETRY		(0x1 << 18)
-#define BRIDGE_ISR_LLP_TCTY		(0x1 << 17)
-#define BRIDGE_ISR_SSRAM_PERR		(0x1 << 16)
-#define BRIDGE_ISR_PCI_ABORT		(0x1 << 15)
-#define BRIDGE_ISR_PCI_PARITY		(0x1 << 14)
-#define BRIDGE_ISR_PCI_SERR		(0x1 << 13)
-#define BRIDGE_ISR_PCI_PERR		(0x1 << 12)
-#define BRIDGE_ISR_PCI_MST_TIMEOUT	(0x1 << 11)
+#define BRIDGE_ISR_MULTI_ERR		BIT(31)
+#define BRIDGE_ISR_PMU_ESIZE_FAULT	BIT(30)
+#define BRIDGE_ISR_UNEXP_RESP		BIT(29)
+#define BRIDGE_ISR_BAD_XRESP_PKT	BIT(28)
+#define BRIDGE_ISR_BAD_XREQ_PKT		BIT(27)
+#define BRIDGE_ISR_RESP_XTLK_ERR	BIT(26)
+#define BRIDGE_ISR_REQ_XTLK_ERR		BIT(25)
+#define BRIDGE_ISR_INVLD_ADDR		BIT(24)
+#define BRIDGE_ISR_UNSUPPORTED_XOP	BIT(23)
+#define BRIDGE_ISR_XREQ_FIFO_OFLOW	BIT(22)
+#define BRIDGE_ISR_LLP_REC_SNERR	BIT(21)
+#define BRIDGE_ISR_LLP_REC_CBERR	BIT(20)
+#define BRIDGE_ISR_LLP_RCTY		BIT(19)
+#define BRIDGE_ISR_LLP_TX_RETRY		BIT(18)
+#define BRIDGE_ISR_LLP_TCTY		BIT(17)
+#define BRIDGE_ISR_SSRAM_PERR		BIT(16)
+#define BRIDGE_ISR_PCI_ABORT		BIT(15)
+#define BRIDGE_ISR_PCI_PARITY		BIT(14)
+#define BRIDGE_ISR_PCI_SERR		BIT(13)
+#define BRIDGE_ISR_PCI_PERR		BIT(12)
+#define BRIDGE_ISR_PCI_MST_TIMEOUT	BIT(11)
 #define BRIDGE_ISR_GIO_MST_TIMEOUT	BRIDGE_ISR_PCI_MST_TIMEOUT
-#define BRIDGE_ISR_PCI_RETRY_CNT	(0x1 << 10)
-#define BRIDGE_ISR_XREAD_REQ_TIMEOUT	(0x1 << 9)
-#define BRIDGE_ISR_GIO_B_ENBL_ERR	(0x1 << 8)
-#define BRIDGE_ISR_INT_MSK		(0xff << 0)
-#define BRIDGE_ISR_INT(x)		(0x1 << (x))
-
-#define BRIDGE_ISR_LINK_ERROR		\
-		(BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|	\
-		 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|		\
+#define BRIDGE_ISR_PCI_RETRY_CNT	BIT(10)
+#define BRIDGE_ISR_XREAD_REQ_TIMEOUT	BIT(9)
+#define BRIDGE_ISR_GIO_B_ENBL_ERR	BIT(8)
+#define BRIDGE_ISR_INT_MSK		GENMASK(7, 0)
+#define BRIDGE_ISR_INT(x)		BIT((x))
+
+#define BRIDGE_ISR_LINK_ERROR						\
+		(BRIDGE_ISR_LLP_REC_SNERR |				\
+		 BRIDGE_ISR_LLP_REC_CBERR |				\
+		 BRIDGE_ISR_LLP_RCTY |					\
+		 BRIDGE_ISR_LLP_TX_RETRY |				\
 		 BRIDGE_ISR_LLP_TCTY)
 
-#define BRIDGE_ISR_PCIBUS_PIOERR	\
-		(BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
+#define BRIDGE_ISR_PCIBUS_PIOERR					\
+		(BRIDGE_ISR_PCI_MST_TIMEOUT |				\
+		 BRIDGE_ISR_PCI_ABORT)
 
-#define BRIDGE_ISR_PCIBUS_ERROR		\
-		(BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|		\
-		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|		\
+#define BRIDGE_ISR_PCIBUS_ERROR						\
+		(BRIDGE_ISR_PCIBUS_PIOERR |				\
+		 BRIDGE_ISR_PCI_PERR |					\
+		 BRIDGE_ISR_PCI_SERR |					\
+		 BRIDGE_ISR_PCI_RETRY_CNT |				\
 		 BRIDGE_ISR_PCI_PARITY)
 
-#define BRIDGE_ISR_XTALK_ERROR		\
-		(BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
-		 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|	\
-		 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|	\
-		 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|	\
+#define BRIDGE_ISR_XTALK_ERROR						\
+		(BRIDGE_ISR_XREAD_REQ_TIMEOUT |				\
+		 BRIDGE_ISR_XREQ_FIFO_OFLOW |				\
+		 BRIDGE_ISR_UNSUPPORTED_XOP |				\
+		 BRIDGE_ISR_INVLD_ADDR |				\
+		 BRIDGE_ISR_REQ_XTLK_ERR |				\
+		 BRIDGE_ISR_RESP_XTLK_ERR |				\
+		 BRIDGE_ISR_BAD_XREQ_PKT |				\
+		 BRIDGE_ISR_BAD_XRESP_PKT |				\
 		 BRIDGE_ISR_UNEXP_RESP)
 
-#define BRIDGE_ISR_ERRORS		\
-		(BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|		\
-		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|		\
+#define BRIDGE_ISR_ERRORS						\
+		(BRIDGE_ISR_LINK_ERROR |				\
+		 BRIDGE_ISR_PCIBUS_ERROR |				\
+		 BRIDGE_ISR_XTALK_ERROR |				\
+		 BRIDGE_ISR_SSRAM_PERR |				\
 		 BRIDGE_ISR_PMU_ESIZE_FAULT)
 
-/*
- * List of Errors which are fatal and kill the system
- */
-#define BRIDGE_ISR_ERROR_FATAL		\
-		((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
-		 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
+/* List of Errors which are fatal and kill the system */
+#define BRIDGE_ISR_ERROR_FATAL						\
+		((BRIDGE_ISR_XTALK_ERROR &				\
+		  ~BRIDGE_ISR_XREAD_REQ_TIMEOUT) |			\
+		 BRIDGE_ISR_PCI_SERR |					\
+		 BRIDGE_ISR_PCI_PARITY)
 
-#define BRIDGE_ISR_ERROR_DUMP		\
-		(BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|	\
-		 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
+#define BRIDGE_ISR_ERROR_DUMP						\
+		(BRIDGE_ISR_PCIBUS_ERROR |				\
+		 BRIDGE_ISR_PMU_ESIZE_FAULT |				\
+		 BRIDGE_ISR_XTALK_ERROR |				\
+		 BRIDGE_ISR_SSRAM_PERR)
 
 /* Bridge interrupt enable register bits definition */
 #define BRIDGE_IMR_UNEXP_RESP		BRIDGE_ISR_UNEXP_RESP
@@ -577,60 +591,73 @@ typedef struct bridge_err_cmdword_s {
 #define BRIDGE_IMR_INT(x)		BRIDGE_ISR_INT(x)
 
 /* Bridge interrupt reset register bits definition */
-#define BRIDGE_IRR_MULTI_CLR		(0x1 << 6)
-#define BRIDGE_IRR_CRP_GRP_CLR		(0x1 << 5)
-#define BRIDGE_IRR_RESP_BUF_GRP_CLR	(0x1 << 4)
-#define BRIDGE_IRR_REQ_DSP_GRP_CLR	(0x1 << 3)
-#define BRIDGE_IRR_LLP_GRP_CLR		(0x1 << 2)
-#define BRIDGE_IRR_SSRAM_GRP_CLR	(0x1 << 1)
-#define BRIDGE_IRR_PCI_GRP_CLR		(0x1 << 0)
-#define BRIDGE_IRR_GIO_GRP_CLR		(0x1 << 0)
+#define BRIDGE_IRR_MULTI_CLR		BIT(6)
+#define BRIDGE_IRR_CRP_GRP_CLR		BIT(5)
+#define BRIDGE_IRR_RESP_BUF_GRP_CLR	BIT(4)
+#define BRIDGE_IRR_REQ_DSP_GRP_CLR	BIT(3)
+#define BRIDGE_IRR_LLP_GRP_CLR		BIT(2)
+#define BRIDGE_IRR_SSRAM_GRP_CLR	BIT(1)
+#define BRIDGE_IRR_PCI_GRP_CLR		BIT(0)
+#define BRIDGE_IRR_GIO_GRP_CLR		BRIDGE_IRR_PCI_GRP_CLR
 #define BRIDGE_IRR_ALL_CLR		0x7f
 
-#define BRIDGE_IRR_CRP_GRP		(BRIDGE_ISR_UNEXP_RESP | \
-					 BRIDGE_ISR_XREQ_FIFO_OFLOW)
-#define BRIDGE_IRR_RESP_BUF_GRP		(BRIDGE_ISR_BAD_XRESP_PKT | \
-					 BRIDGE_ISR_RESP_XTLK_ERR | \
-					 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
-#define BRIDGE_IRR_REQ_DSP_GRP		(BRIDGE_ISR_UNSUPPORTED_XOP | \
-					 BRIDGE_ISR_BAD_XREQ_PKT | \
-					 BRIDGE_ISR_REQ_XTLK_ERR | \
-					 BRIDGE_ISR_INVLD_ADDR)
-#define BRIDGE_IRR_LLP_GRP		(BRIDGE_ISR_LLP_REC_SNERR | \
-					 BRIDGE_ISR_LLP_REC_CBERR | \
-					 BRIDGE_ISR_LLP_RCTY | \
-					 BRIDGE_ISR_LLP_TX_RETRY | \
-					 BRIDGE_ISR_LLP_TCTY)
-#define BRIDGE_IRR_SSRAM_GRP		(BRIDGE_ISR_SSRAM_PERR | \
-					 BRIDGE_ISR_PMU_ESIZE_FAULT)
-#define BRIDGE_IRR_PCI_GRP		(BRIDGE_ISR_PCI_ABORT | \
-					 BRIDGE_ISR_PCI_PARITY | \
-					 BRIDGE_ISR_PCI_SERR | \
-					 BRIDGE_ISR_PCI_PERR | \
-					 BRIDGE_ISR_PCI_MST_TIMEOUT | \
-					 BRIDGE_ISR_PCI_RETRY_CNT)
-
-#define BRIDGE_IRR_GIO_GRP		(BRIDGE_ISR_GIO_B_ENBL_ERR | \
-					 BRIDGE_ISR_GIO_MST_TIMEOUT)
+#define BRIDGE_IRR_CRP_GRP						\
+	(BRIDGE_ISR_UNEXP_RESP |					\
+	 BRIDGE_ISR_XREQ_FIFO_OFLOW)
+
+#define BRIDGE_IRR_RESP_BUF_GRP						\
+	(BRIDGE_ISR_BAD_XRESP_PKT |					\
+	 BRIDGE_ISR_RESP_XTLK_ERR |					\
+	 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+
+#define BRIDGE_IRR_REQ_DSP_GRP						\
+	(BRIDGE_ISR_UNSUPPORTED_XOP |					\
+	 BRIDGE_ISR_BAD_XREQ_PKT |					\
+	 BRIDGE_ISR_REQ_XTLK_ERR |					\
+	 BRIDGE_ISR_INVLD_ADDR)
+
+#define BRIDGE_IRR_LLP_GRP						\
+	(BRIDGE_ISR_LLP_REC_SNERR |					\
+	 BRIDGE_ISR_LLP_REC_CBERR |					\
+	 BRIDGE_ISR_LLP_RCTY |						\
+	 BRIDGE_ISR_LLP_TX_RETRY |					\
+	 BRIDGE_ISR_LLP_TCTY)
+
+#define BRIDGE_IRR_SSRAM_GRP						\
+	(BRIDGE_ISR_SSRAM_PERR |					\
+	 BRIDGE_ISR_PMU_ESIZE_FAULT)
+
+#define BRIDGE_IRR_PCI_GRP						\
+	(BRIDGE_ISR_PCI_ABORT |						\
+	 BRIDGE_ISR_PCI_PARITY |					\
+	 BRIDGE_ISR_PCI_SERR |						\
+	 BRIDGE_ISR_PCI_PERR |						\
+	 BRIDGE_ISR_PCI_MST_TIMEOUT |					\
+	 BRIDGE_ISR_PCI_RETRY_CNT)
+
+#define BRIDGE_IRR_GIO_GRP						\
+	(BRIDGE_ISR_GIO_B_ENBL_ERR |					\
+	 BRIDGE_ISR_GIO_MST_TIMEOUT)
 
 /* Bridge INT_DEV register bits definition */
-#define BRIDGE_INT_DEV_SHFT(n)		((n)*3)
+#define BRIDGE_INT_DEV_SHFT(n)		((n) * 3)
 #define BRIDGE_INT_DEV_MASK(n)		(0x7 << BRIDGE_INT_DEV_SHFT(n))
 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
 
 /* Bridge interrupt(x) register bits definition */
-#define BRIDGE_INT_ADDR_HOST		0x0003FF00
-#define BRIDGE_INT_ADDR_FLD		0x000000FF
+#define BRIDGE_INT_ADDR_HOST		GENMASK(17, 8)
+#define BRIDGE_INT_ADDR_FLD		GENMASK(7, 0)
 
-#define BRIDGE_TMO_PCI_RETRY_HLD_MASK	0x1f0000
-#define BRIDGE_TMO_GIO_TIMEOUT_MASK	0x001000
-#define BRIDGE_TMO_PCI_RETRY_CNT_MASK	0x0003ff
+/* Bridge timeout register bits definition */
+#define BRIDGE_TMO_PCI_RETRY_HLD_MASK	GENMASK(20, 16)
+#define BRIDGE_TMO_GIO_TIMEOUT_MASK	BIT(12)
+#define BRIDGE_TMO_PCI_RETRY_CNT_MASK	GENMASK(9, 0)
 
 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX	0x3ff
 
 /*
  * The NASID should be shifted by this amount and stored into the
- * interrupt(x) register.
+ * interrupt(x) register. (IP27/IP35 only)
  */
 #define BRIDGE_INT_ADDR_NASID_SHFT	8
 
@@ -638,76 +665,82 @@ typedef struct bridge_err_cmdword_s {
  * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
  * memory.
  */
-#define BRIDGE_INT_ADDR_DEST_IO		(1 << 17)
+#define BRIDGE_INT_ADDR_DEST_IO		BIT(17)
 #define BRIDGE_INT_ADDR_DEST_MEM	0
-#define BRIDGE_INT_ADDR_MASK		(1 << 17)
+#define BRIDGE_INT_ADDR_MASK		BIT(17)
 
 /* Bridge device(x) register bits definition */
-#define BRIDGE_DEV_ERR_LOCK_EN		0x10000000
-#define BRIDGE_DEV_PAGE_CHK_DIS		0x08000000
-#define BRIDGE_DEV_FORCE_PCI_PAR	0x04000000
-#define BRIDGE_DEV_VIRTUAL_EN		0x02000000
-#define BRIDGE_DEV_PMU_WRGA_EN		0x01000000
-#define BRIDGE_DEV_DIR_WRGA_EN		0x00800000
-#define BRIDGE_DEV_DEV_SIZE		0x00400000
-#define BRIDGE_DEV_RT			0x00200000
-#define BRIDGE_DEV_SWAP_PMU		0x00100000
-#define BRIDGE_DEV_SWAP_DIR		0x00080000
-#define BRIDGE_DEV_PREF			0x00040000
-#define BRIDGE_DEV_PRECISE		0x00020000
-#define BRIDGE_DEV_COH			0x00010000
-#define BRIDGE_DEV_BARRIER		0x00008000
-#define BRIDGE_DEV_GBR			0x00004000
-#define BRIDGE_DEV_DEV_SWAP		0x00002000
-#define BRIDGE_DEV_DEV_IO_MEM		0x00001000
-#define BRIDGE_DEV_OFF_MASK		0x00000fff
+#define BRIDGE_DEV_ERR_LOCK_EN		BIT(28)
+#define BRIDGE_DEV_PAGE_CHK_DIS		BIT(27)
+#define BRIDGE_DEV_FORCE_PCI_PAR	BIT(26)
+#define BRIDGE_DEV_VIRTUAL_EN		BIT(25)
+#define BRIDGE_DEV_PMU_WRGA_EN		BIT(24)
+#define BRIDGE_DEV_DIR_WRGA_EN		BIT(23)
+#define BRIDGE_DEV_DEV_SIZE		BIT(22)
+#define BRIDGE_DEV_RT			BIT(21)
+#define BRIDGE_DEV_SWAP_PMU		BIT(20)
+#define BRIDGE_DEV_SWAP_DIR		BIT(19)
+#define BRIDGE_DEV_PREF			BIT(18)
+#define BRIDGE_DEV_PRECISE		BIT(17)
+#define BRIDGE_DEV_COH			BIT(16)
+#define BRIDGE_DEV_BARRIER		BIT(15)
+#define BRIDGE_DEV_GBR			BIT(14)
+#define BRIDGE_DEV_DEV_SWAP		BIT(13)
+#define BRIDGE_DEV_DEV_IO_MEM		BIT(12)
+#define BRIDGE_DEV_OFF_MASK		GENMASK(11, 0)
 #define BRIDGE_DEV_OFF_ADDR_SHFT	20
 
-#define BRIDGE_DEV_PMU_BITS		(BRIDGE_DEV_PMU_WRGA_EN		| \
-					 BRIDGE_DEV_SWAP_PMU)
-#define BRIDGE_DEV_D32_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
-					 BRIDGE_DEV_SWAP_DIR		| \
-					 BRIDGE_DEV_PREF		| \
-					 BRIDGE_DEV_PRECISE		| \
-					 BRIDGE_DEV_COH			| \
-					 BRIDGE_DEV_BARRIER)
-#define BRIDGE_DEV_D64_BITS		(BRIDGE_DEV_DIR_WRGA_EN		| \
-					 BRIDGE_DEV_SWAP_DIR		| \
-					 BRIDGE_DEV_COH			| \
-					 BRIDGE_DEV_BARRIER)
+#define BRIDGE_DEV_PMU_BITS						\
+	(BRIDGE_DEV_PMU_WRGA_EN |					\
+	 BRIDGE_DEV_SWAP_PMU)
+
+#define BRIDGE_DEV_D32_BITS						\
+	(BRIDGE_DEV_DIR_WRGA_EN |					\
+	 BRIDGE_DEV_SWAP_DIR |						\
+	 BRIDGE_DEV_PREF |						\
+	 BRIDGE_DEV_PRECISE |						\
+	 BRIDGE_DEV_COH |						\
+	 BRIDGE_DEV_BARRIER)
+
+#define BRIDGE_DEV_D64_BITS						\
+	(BRIDGE_DEV_DIR_WRGA_EN |					\
+	 BRIDGE_DEV_SWAP_DIR |						\
+	 BRIDGE_DEV_COH |						\
+	 BRIDGE_DEV_BARRIER)
 
 /* Bridge Error Upper register bit field definition */
-#define BRIDGE_ERRUPPR_DEVMASTER	(0x1 << 20)	/* Device was master */
-#define BRIDGE_ERRUPPR_PCIVDEV		(0x1 << 19)	/* Virtual Req value */
+#define BRIDGE_ERRUPPR_DEVMASTER	BIT(20)	/* Device was master */
+#define BRIDGE_ERRUPPR_PCIVDEV		BIT(19)	/* Virtual Req value */
 #define BRIDGE_ERRUPPR_DEVNUM_SHFT	(16)
 #define BRIDGE_ERRUPPR_DEVNUM_MASK	(0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
-#define BRIDGE_ERRUPPR_DEVICE(err)	(((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
-#define BRIDGE_ERRUPPR_ADDRMASK		(0xFFFF)
+#define BRIDGE_ERRUPPR_DEVICE(err)					\
+	(((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
+#define BRIDGE_ERRUPPR_ADDRMASK		GENMASK(15, 0)
 
 /* Bridge interrupt mode register bits definition */
-#define BRIDGE_INTMODE_CLR_PKT_EN(x)	(0x1 << (x))
+#define BRIDGE_INTMODE_CLR_PKT_EN(x)	BIT((x))
 
-/* this should be written to the xbow's link_control(x) register */
-#define BRIDGE_CREDIT	3
+/* This should be written to the XBOW's link_control(x) register */
+#define BRIDGE_CREDIT			3
 
-/* RRB assignment register */
-#define BRIDGE_RRB_EN	0x8	/* after shifting down */
-#define BRIDGE_RRB_DEV	0x7	/* after shifting down */
-#define BRIDGE_RRB_VDEV 0x4	/* after shifting down */
-#define BRIDGE_RRB_PDEV 0x3	/* after shifting down */
+/* RRB assignment register -- value applies after shifting down */
+#define BRIDGE_RRB_EN			0x8
+#define BRIDGE_RRB_DEV			0x7
+#define BRIDGE_RRB_VDEV			0x4
+#define BRIDGE_RRB_PDEV			0x3
 
 /* RRB status register */
-#define BRIDGE_RRB_VALID(r)	(0x00010000<<(r))
-#define BRIDGE_RRB_INUSE(r)	(0x00000001<<(r))
+#define BRIDGE_RRB_VALID(r)		(0x00010000 << (r))
+#define BRIDGE_RRB_INUSE(r)		(0x00000001 << (r))
 
 /* RRB clear register */
-#define BRIDGE_RRB_CLEAR(r)	(0x00000001<<(r))
+#define BRIDGE_RRB_CLEAR(r)		(0x00000001 << (r))
 
-/* xbox system controller declarations */
-#define XBOX_BRIDGE_WID		8
-#define FLASH_PROM1_BASE	0xE00000 /* To read the xbox sysctlr status */
-#define XBOX_RPS_EXISTS		1 << 6	 /* RPS bit in status register */
-#define XBOX_RPS_FAIL		1 << 4	 /* RPS status bit in register */
+/* Xbox system controller declarations */
+#define XBOX_BRIDGE_WID			8
+#define FLASH_PROM1_BASE		0xe00000 /* Read Xbox sysctlr stat */
+#define XBOX_RPS_EXISTS			BIT(6)	 /* RPS bit in status reg */
+#define XBOX_RPS_FAIL			BIT(4)	 /* RPS status bit in reg */
 
 /* ========================================================================
  */
@@ -716,12 +749,12 @@ typedef struct bridge_err_cmdword_s {
  * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
  */
 /* XTALK addresses that map into Bridge Bus addr space */
-#define BRIDGE_PIO32_XTALK_ALIAS_BASE	0x000040000000L
-#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT	0x00007FFFFFFFL
-#define BRIDGE_PIO64_XTALK_ALIAS_BASE	0x000080000000L
-#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT	0x0000BFFFFFFFL
-#define BRIDGE_PCIIO_XTALK_ALIAS_BASE	0x000100000000L
-#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT	0x0001FFFFFFFFL
+#define BRIDGE_PIO32_XTALK_ALIAS_BASE	0x000040000000UL
+#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT	0x00007fffffffUL
+#define BRIDGE_PIO64_XTALK_ALIAS_BASE	0x000080000000UL
+#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT	0x0000bfffffffUL
+#define BRIDGE_PCIIO_XTALK_ALIAS_BASE	0x000100000000UL
+#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT	0x0001ffffffffUL
 
 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
 #define BRIDGE_MIN_PIO_ADDR_MEM		0x00000000	/* 1G PCI memory space */
@@ -753,15 +786,17 @@ typedef struct bridge_err_cmdword_s {
 #define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
 #define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE
 
-#define IS_PCI32_LOCAL(x)	((ulong_t)(x) < PCI32_MAPPED_BASE)
-#define IS_PCI32_MAPPED(x)	((ulong_t)(x) < PCI32_DIRECT_BASE && \
-					(ulong_t)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI32_DIRECT(x)	((ulong_t)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI64(x)		((ulong_t)(x) >= PCI64_BASE)
-
-/*
- * The GIO address space.
- */
+#define IS_PCI32_LOCAL(x)						\
+	((ulong_t)(x) < PCI32_MAPPED_BASE)
+#define IS_PCI32_MAPPED(x)						\
+	((ulong_t)(x) < PCI32_DIRECT_BASE && \
+	 (ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x)						\
+	((ulong_t)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI64(x)							\
+	((ulong_t)(x) >= PCI64_BASE)
+
+/* GIO address space. */
 /* Xtalk to GIO PIO */
 #define BRIDGE_GIO_MEM32_BASE		BRIDGE_PIO32_XTALK_ALIAS_BASE
 #define BRIDGE_GIO_MEM32_LIMIT		BRIDGE_PIO32_XTALK_ALIAS_LIMIT
@@ -772,29 +807,33 @@ typedef struct bridge_err_cmdword_s {
 #define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
 #define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE
 
-#define IS_GIO_LOCAL(x)		((ulong_t)(x) < GIO_MAPPED_BASE)
-#define IS_GIO_MAPPED(x)	((ulong_t)(x) < GIO_DIRECT_BASE && \
-					(ulong_t)(x) >= GIO_MAPPED_BASE)
-#define IS_GIO_DIRECT(x)	((ulong_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_LOCAL(x)							\
+	((ulong_t)(x) < GIO_MAPPED_BASE)
+#define IS_GIO_MAPPED(x)						\
+	((ulong_t)(x) < GIO_DIRECT_BASE && \
+	 (ulong_t)(x) >= GIO_MAPPED_BASE)
+#define IS_GIO_DIRECT(x)						\
+	((ulong_t)(x) >= GIO_MAPPED_BASE)
+
 
-/* PCI to xtalk mapping */
+/* PCI-to-Xtalk mapping */
 
 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
  * which xtalk address is accessed
  */
 #define BRIDGE_DIRECT_32_SEG_SIZE	BRIDGE_DMA_DIRECT_SIZE
-#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)		\
-	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +	\
-		((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
+#define BRIDGE_DIRECT_32_TO_XTALK(dir_off, adr)				\
+	((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +			\
+	 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
 
 /* 64-bit address attribute masks */
-#define PCI64_ATTR_TARG_MASK	0xf000000000000000
+#define PCI64_ATTR_TARG_MASK	GENMASK_ULL(63, 60)
 #define PCI64_ATTR_TARG_SHFT	60
-#define PCI64_ATTR_PREF		0x0800000000000000
-#define PCI64_ATTR_PREC		0x0400000000000000
-#define PCI64_ATTR_VIRTUAL	0x0200000000000000
-#define PCI64_ATTR_BAR		0x0100000000000000
-#define PCI64_ATTR_RMF_MASK	0x00ff000000000000
+#define PCI64_ATTR_PREF		BIT_ULL(59)
+#define PCI64_ATTR_PREC		BIT_ULL(58)
+#define PCI64_ATTR_VIRTUAL	BIT_ULL(57)
+#define PCI64_ATTR_BAR		BIT_ULL(56)
+#define PCI64_ATTR_RMF_MASK	GENMASK_ULL(55, 48)
 #define PCI64_ATTR_RMF_SHFT	48
 
 #ifndef __ASSEMBLY__
@@ -815,33 +854,34 @@ typedef union ate_u {
 } ate_t;
 #endif /* !__ASSEMBLY__ */
 
-#define ATE_V		0x01
-#define ATE_CO		0x02
-#define ATE_PREC	0x04
-#define ATE_PREF	0x08
-#define ATE_BAR		0x10
+#define ATE_V			0x01
+#define ATE_CO			0x02
+#define ATE_PREC		0x04
+#define ATE_PREF		0x08
+#define ATE_BAR			0x10
 
 #define ATE_PFNSHIFT		12
 #define ATE_TIDSHIFT		8
 #define ATE_RMFSHIFT		48
 
-#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
-				((xid)<<ATE_TIDSHIFT) | \
-				(attr)
+#define mkate(xaddr, xid, attr)						\
+	(((xaddr) & 0x0000fffffffff000ULL) |				\
+	 ((xid) << ATE_TIDSHIFT) |					\
+	 (attr))
 
 #define BRIDGE_INTERNAL_ATES	128
 
 struct bridge_controller {
-	struct pci_controller	pc;
-	struct resource		mem;
-	struct resource		io;
-	struct resource		busn;
-	bridge_t		*base;
-	nasid_t			nasid;
-	unsigned int		widget_id;
-	unsigned int		irq_cpu;
-	u64			baddr;
-	unsigned int		pci_int[8];
+	struct pci_controller pc;
+	struct resource mem;
+	struct resource io;
+	struct resource busn;
+	bridge_t *base;
+	nasid_t nasid;
+	u32 widget_id;
+	u32 irq_cpu;
+	u64 baddr;
+	u32 pci_int[8];
 };
 
 #define BRIDGE_CONTROLLER(bus) \
-- 
2.11.1