* [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw
@ 2017-02-08 18:10 Robert Bragg
2017-02-08 18:33 ` Ville Syrjälä
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Robert Bragg @ 2017-02-08 18:10 UTC (permalink / raw)
To: intel-gfx
This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 49fa8006c6a2..fa1b400a79d0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -776,6 +776,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableDopClockGating:bdw */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
+ WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-08 18:10 [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw Robert Bragg
@ 2017-02-08 18:33 ` Ville Syrjälä
2017-02-12 13:21 ` Robert Bragg
2017-02-09 8:02 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-12 14:22 ` ✓ Fi.CI.BAT: success for drm/i915: fix for WaDisableDopClockGating:bdw (rev2) Patchwork
2 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-02-08 18:33 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
On Wed, Feb 08, 2017 at 06:10:31PM +0000, Robert Bragg wrote:
> This workaround for BDW was incomplete as it also requires EUTC clock
> gating to be disabled via UCGCTL1.
IIRC that matches what I told Ben years ago when the w/a was first
being added, and matches what I put in the CHV code when it still
had this w/a. Presumably it still holds for BDW.
>
> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 49fa8006c6a2..fa1b400a79d0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -776,6 +776,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableDopClockGating:bdw */
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
> + WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
The UCGCTL registers aren't clobbered by GPU resets and whatnot, so
we've historically kept them in the init_clock_gating() side.
Also it's not a masked register, and I'm not sure not all the bits
default to 0, so you shouldn't perhaps just clobber them. Sadly the
spec seems to have gone mad and no longer shows the default values
for registers so I can't double check right now.
>
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-08 18:10 [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw Robert Bragg
2017-02-08 18:33 ` Ville Syrjälä
@ 2017-02-09 8:02 ` Patchwork
2017-02-12 14:22 ` ✓ Fi.CI.BAT: success for drm/i915: fix for WaDisableDopClockGating:bdw (rev2) Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-02-09 8:02 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: fix for WaDisableDopClockGating:bdw
URL : https://patchwork.freedesktop.org/series/19332/
State : success
== Summary ==
Series 19332v1 drm/i915: fix for WaDisableDopClockGating:bdw
https://patchwork.freedesktop.org/api/1.0/series/19332/revisions/1/mbox/
fi-bsw-n3050 total:252 pass:213 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:252 pass:230 dwarn:0 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:252 pass:225 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-ilk-650 total:252 pass:199 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:252 pass:231 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:252 pass:231 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:252 pass:229 dwarn:0 dfail:0 fail:2 skip:21
fi-skl-6260u total:252 pass:239 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:252 pass:232 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:252 pass:227 dwarn:4 dfail:0 fail:0 skip:21
fi-skl-6770hq total:252 pass:239 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:252 pass:220 dwarn:0 dfail:0 fail:0 skip:32
29b6014fdfab0a48deb05fc5cc5b33ba00042118 drm-tip: 2017y-02m-08d-21h-01m-50s UTC integration manifest
f8c4560 drm/i915: fix for WaDisableDopClockGating:bdw
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3744/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-08 18:33 ` Ville Syrjälä
@ 2017-02-12 13:21 ` Robert Bragg
2017-02-12 13:32 ` [PATCH v2] " Robert Bragg
0 siblings, 1 reply; 9+ messages in thread
From: Robert Bragg @ 2017-02-12 13:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel Graphics Development
On Wed, Feb 8, 2017 at 6:33 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 08, 2017 at 06:10:31PM +0000, Robert Bragg wrote:
>> This workaround for BDW was incomplete as it also requires EUTC clock
>> gating to be disabled via UCGCTL1.
>
> IIRC that matches what I told Ben years ago when the w/a was first
> being added, and matches what I put in the CHV code when it still
> had this w/a. Presumably it still holds for BDW.
Poking into this I see now that 3e470eaaee5 which removes the
corresponding, pre-production, w/a for CHV removed a write to UCGCTL1
which is missing for BDW.
>
>>
>> Signed-off-by: Robert Bragg <robert@sixbynine.org>
>> ---
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 49fa8006c6a2..fa1b400a79d0 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -776,6 +776,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
>> /* WaDisableDopClockGating:bdw */
>> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> DOP_CLOCK_GATING_DISABLE);
>> + WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>
> The UCGCTL registers aren't clobbered by GPU resets and whatnot, so
> we've historically kept them in the init_clock_gating() side.
Okey, I'll move here.
>
> Also it's not a masked register, and I'm not sure not all the bits
> default to 0, so you shouldn't perhaps just clobber them. Sadly the
> spec seems to have gone mad and no longer shows the default values
> for registers so I can't double check right now.
Ah, oops, I had a read modify write in i915-perf previously but yeah
this is no good. Moving this to broadwell_init_clock_gating() as a
read modify write is hopefully ok.
Thanks for the notes.
- Robert
>
>>
>> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>> GEN8_SAMPLER_POWER_BYPASS_DIS);
>> --
>> 2.11.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-12 13:21 ` Robert Bragg
@ 2017-02-12 13:32 ` Robert Bragg
2017-02-13 14:28 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Robert Bragg @ 2017-02-12 13:32 UTC (permalink / raw)
To: intel-gfx
This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.
v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
Signed-off-by: Robert Bragg <robert@sixbynine.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c0b0f5a4b9f1..3c13be8985f1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7229,6 +7229,14 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
| KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
lpt_init_clock_gating(dev_priv);
+
+ /* WaDisableDopClockGating:bdw
+ *
+ * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
+ * clock gating.
+ */
+ I915_WRITE(GEN6_UCGCTL1,
+ I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
}
static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d3d1e64f2498..d93d5f8f02d8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -825,7 +825,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
- /* WaDisableDopClockGating:bdw */
+ /* WaDisableDopClockGating:bdw
+ *
+ * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
+ * to disable EUTC clock gating.
+ */
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
--
2.11.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: fix for WaDisableDopClockGating:bdw (rev2)
2017-02-08 18:10 [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw Robert Bragg
2017-02-08 18:33 ` Ville Syrjälä
2017-02-09 8:02 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-02-12 14:22 ` Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-02-12 14:22 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: fix for WaDisableDopClockGating:bdw (rev2)
URL : https://patchwork.freedesktop.org/series/19332/
State : success
== Summary ==
Series 19332v2 drm/i915: fix for WaDisableDopClockGating:bdw
https://patchwork.freedesktop.org/api/1.0/series/19332/revisions/2/mbox/
fi-bdw-5557u total:252 pass:241 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:252 pass:213 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:252 pass:225 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:252 pass:202 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-skl-6260u total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:252 pass:235 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:252 pass:230 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:252 pass:224 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:252 pass:223 dwarn:0 dfail:0 fail:0 skip:29
f48164e93e75dbbe0bb9dac254779eeea08c0657 drm-tip: 2017y-02m-12d-11h-10m-28s UTC integration manifest
ad826f3 drm/i915: fix for WaDisableDopClockGating:bdw
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3780/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-12 13:32 ` [PATCH v2] " Robert Bragg
@ 2017-02-13 14:28 ` Ville Syrjälä
2017-02-13 14:54 ` Robert Bragg
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-02-13 14:28 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
On Sun, Feb 12, 2017 at 01:32:52PM +0000, Robert Bragg wrote:
> This workaround for BDW was incomplete as it also requires EUTC clock
> gating to be disabled via UCGCTL1.
>
> v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
>
> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Do we know if this fixes something real? And if so, do we want cc:stable?
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c0b0f5a4b9f1..3c13be8985f1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7229,6 +7229,14 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
>
> lpt_init_clock_gating(dev_priv);
> +
> + /* WaDisableDopClockGating:bdw
> + *
> + * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
> + * clock gating.
> + */
> + I915_WRITE(GEN6_UCGCTL1,
> + I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> }
>
> static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d3d1e64f2498..d93d5f8f02d8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -825,7 +825,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>
> - /* WaDisableDopClockGating:bdw */
> + /* WaDisableDopClockGating:bdw
> + *
> + * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
> + * to disable EUTC clock gating.
> + */
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
>
> --
> 2.11.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-13 14:28 ` Ville Syrjälä
@ 2017-02-13 14:54 ` Robert Bragg
2017-02-14 20:32 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Robert Bragg @ 2017-02-13 14:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel Graphics Development
On Mon, Feb 13, 2017 at 2:28 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Sun, Feb 12, 2017 at 01:32:52PM +0000, Robert Bragg wrote:
>> This workaround for BDW was incomplete as it also requires EUTC clock
>> gating to be disabled via UCGCTL1.
>>
>> v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
>>
>> Signed-off-by: Robert Bragg <robert@sixbynine.org>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do we know if this fixes something real? And if so, do we want cc:stable?
I looked at this as I was reviewing what workarounds I need to deal
with for gen8+ OA unit enabling. I had previously been applying this
WA within i915_perf.c with a long standing comment that I should cross
reference with VPG to see which platforms really needed it. So I just
noticed that i915 is now aiming to handle the WA but it looked
incomplete. I can't say I've observed the issue myself but my
understanding is that it may affect OA metrics in some cases.
Br,
- Robert
>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
>> 2 files changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index c0b0f5a4b9f1..3c13be8985f1 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7229,6 +7229,14 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
>> | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
>>
>> lpt_init_clock_gating(dev_priv);
>> +
>> + /* WaDisableDopClockGating:bdw
>> + *
>> + * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
>> + * clock gating.
>> + */
>> + I915_WRITE(GEN6_UCGCTL1,
>> + I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>> }
>>
>> static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index d3d1e64f2498..d93d5f8f02d8 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -825,7 +825,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
>> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
>> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
>>
>> - /* WaDisableDopClockGating:bdw */
>> + /* WaDisableDopClockGating:bdw
>> + *
>> + * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
>> + * to disable EUTC clock gating.
>> + */
>> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>> DOP_CLOCK_GATING_DISABLE);
>>
>> --
>> 2.11.1
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: fix for WaDisableDopClockGating:bdw
2017-02-13 14:54 ` Robert Bragg
@ 2017-02-14 20:32 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2017-02-14 20:32 UTC (permalink / raw)
To: Robert Bragg; +Cc: Intel Graphics Development
On Mon, Feb 13, 2017 at 02:54:01PM +0000, Robert Bragg wrote:
> On Mon, Feb 13, 2017 at 2:28 PM, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Sun, Feb 12, 2017 at 01:32:52PM +0000, Robert Bragg wrote:
> >> This workaround for BDW was incomplete as it also requires EUTC clock
> >> gating to be disabled via UCGCTL1.
> >>
> >> v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
> >>
> >> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Do we know if this fixes something real? And if so, do we want cc:stable?
>
> I looked at this as I was reviewing what workarounds I need to deal
> with for gen8+ OA unit enabling. I had previously been applying this
> WA within i915_perf.c with a long standing comment that I should cross
> reference with VPG to see which platforms really needed it. So I just
> noticed that i915 is now aiming to handle the WA but it looked
> incomplete. I can't say I've observed the issue myself but my
> understanding is that it may affect OA metrics in some cases.
OK. Sounds like it's not stable material at this point so I've gone
and pushed it to dinq. Thanks for the patch.
>
> Br,
> - Robert
>
> >
> >> ---
> >> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> >> 2 files changed, 13 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index c0b0f5a4b9f1..3c13be8985f1 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -7229,6 +7229,14 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> >> | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
> >>
> >> lpt_init_clock_gating(dev_priv);
> >> +
> >> + /* WaDisableDopClockGating:bdw
> >> + *
> >> + * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
> >> + * clock gating.
> >> + */
> >> + I915_WRITE(GEN6_UCGCTL1,
> >> + I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> >> }
> >>
> >> static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index d3d1e64f2498..d93d5f8f02d8 100644
> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> @@ -825,7 +825,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
> >> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
> >>
> >> - /* WaDisableDopClockGating:bdw */
> >> + /* WaDisableDopClockGating:bdw
> >> + *
> >> + * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
> >> + * to disable EUTC clock gating.
> >> + */
> >> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> >> DOP_CLOCK_GATING_DISABLE);
> >>
> >> --
> >> 2.11.1
> >
> > --
> > Ville Syrjälä
> > Intel OTC
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-02-14 20:32 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-08 18:10 [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw Robert Bragg
2017-02-08 18:33 ` Ville Syrjälä
2017-02-12 13:21 ` Robert Bragg
2017-02-12 13:32 ` [PATCH v2] " Robert Bragg
2017-02-13 14:28 ` Ville Syrjälä
2017-02-13 14:54 ` Robert Bragg
2017-02-14 20:32 ` Ville Syrjälä
2017-02-09 8:02 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-12 14:22 ` ✓ Fi.CI.BAT: success for drm/i915: fix for WaDisableDopClockGating:bdw (rev2) Patchwork
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