* [PATCH] drm/i915: Always pin contexts into the high GGTT
@ 2017-02-10 10:14 Chris Wilson
2017-02-10 10:29 ` Mika Kuoppala
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2017-02-10 10:14 UTC (permalink / raw)
To: intel-gfx
Now that we have fast top-down insertion into the drm_mm, we can use it
for frequent runtime operations like insertion of the context object,
whereas before we limited it to the one-off insertion of the pinned
kernel context. Keeping the active context objects out of the mappable
region of the global GTT (except under memory pressure) improves our
ability to allocate mappable aperture region without triggering a GPU
stall.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +---
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 +++---------
2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b21dbd44045e..697776d427b9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -773,11 +773,9 @@ static int execlists_context_pin(struct intel_engine_cs *engine,
}
GEM_BUG_ON(!ce->state);
- flags = PIN_GLOBAL;
+ flags = PIN_GLOBAL | PIN_HIGH;
if (ctx->ggtt_offset_bias)
flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
- if (i915_gem_context_is_kernel(ctx))
- flags |= PIN_HIGH;
ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d3d1e64f2498..8ae78b79178f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2004,7 +2004,7 @@ intel_ring_free(struct intel_ring *ring)
kfree(ring);
}
-static int context_pin(struct i915_gem_context *ctx, unsigned int flags)
+static int context_pin(struct i915_gem_context *ctx)
{
struct i915_vma *vma = ctx->engine[RCS].state;
int ret;
@@ -2019,7 +2019,7 @@ static int context_pin(struct i915_gem_context *ctx, unsigned int flags)
return ret;
}
- return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | flags);
+ return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | PIN_HIGH);
}
static int intel_ring_context_pin(struct intel_engine_cs *engine,
@@ -2034,13 +2034,7 @@ static int intel_ring_context_pin(struct intel_engine_cs *engine,
return 0;
if (ce->state) {
- unsigned int flags;
-
- flags = 0;
- if (i915_gem_context_is_kernel(ctx))
- flags = PIN_HIGH;
-
- ret = context_pin(ctx, flags);
+ ret = context_pin(ctx);
if (ret)
goto error;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Always pin contexts into the high GGTT
2017-02-10 10:14 [PATCH] drm/i915: Always pin contexts into the high GGTT Chris Wilson
@ 2017-02-10 10:29 ` Mika Kuoppala
2017-02-10 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-10 13:39 ` [PATCH] " Joonas Lahtinen
2 siblings, 0 replies; 5+ messages in thread
From: Mika Kuoppala @ 2017-02-10 10:29 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Now that we have fast top-down insertion into the drm_mm, we can use it
> for frequent runtime operations like insertion of the context object,
> whereas before we limited it to the one-off insertion of the pinned
> kernel context. Keeping the active context objects out of the mappable
> region of the global GTT (except under memory pressure) improves our
> ability to allocate mappable aperture region without triggering a GPU
> stall.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 4 +---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 12 +++---------
> 2 files changed, 4 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index b21dbd44045e..697776d427b9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -773,11 +773,9 @@ static int execlists_context_pin(struct intel_engine_cs *engine,
> }
> GEM_BUG_ON(!ce->state);
>
> - flags = PIN_GLOBAL;
> + flags = PIN_GLOBAL | PIN_HIGH;
> if (ctx->ggtt_offset_bias)
> flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
> - if (i915_gem_context_is_kernel(ctx))
> - flags |= PIN_HIGH;
>
> ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d3d1e64f2498..8ae78b79178f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2004,7 +2004,7 @@ intel_ring_free(struct intel_ring *ring)
> kfree(ring);
> }
>
> -static int context_pin(struct i915_gem_context *ctx, unsigned int flags)
> +static int context_pin(struct i915_gem_context *ctx)
> {
> struct i915_vma *vma = ctx->engine[RCS].state;
> int ret;
> @@ -2019,7 +2019,7 @@ static int context_pin(struct i915_gem_context *ctx, unsigned int flags)
> return ret;
> }
>
> - return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | flags);
> + return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | PIN_HIGH);
> }
>
> static int intel_ring_context_pin(struct intel_engine_cs *engine,
> @@ -2034,13 +2034,7 @@ static int intel_ring_context_pin(struct intel_engine_cs *engine,
> return 0;
>
> if (ce->state) {
> - unsigned int flags;
> -
> - flags = 0;
> - if (i915_gem_context_is_kernel(ctx))
> - flags = PIN_HIGH;
> -
> - ret = context_pin(ctx, flags);
> + ret = context_pin(ctx);
> if (ret)
> goto error;
> }
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 5+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Always pin contexts into the high GGTT
2017-02-10 10:14 [PATCH] drm/i915: Always pin contexts into the high GGTT Chris Wilson
2017-02-10 10:29 ` Mika Kuoppala
@ 2017-02-10 10:50 ` Patchwork
2017-02-10 13:39 ` [PATCH] " Joonas Lahtinen
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-02-10 10:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Always pin contexts into the high GGTT
URL : https://patchwork.freedesktop.org/series/19440/
State : success
== Summary ==
Series 19440v1 drm/i915: Always pin contexts into the high GGTT
https://patchwork.freedesktop.org/api/1.0/series/19440/revisions/1/mbox/
fi-bdw-5557u total:252 pass:241 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:252 pass:213 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:252 pass:225 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:252 pass:236 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:252 pass:202 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:252 pass:234 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:252 pass:232 dwarn:0 dfail:0 fail:2 skip:18
fi-skl-6260u total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:252 pass:235 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:252 pass:230 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:252 pass:242 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:252 pass:224 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:252 pass:223 dwarn:0 dfail:0 fail:0 skip:29
c46c80c1b1cdc18ed3d44ce289032946b48454c6 drm-tip: 2017y-02m-10d-09h-45m-22s UTC integration manifest
4d8c9f1 drm/i915: Always pin contexts into the high GGTT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3764/
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Always pin contexts into the high GGTT
2017-02-10 10:14 [PATCH] drm/i915: Always pin contexts into the high GGTT Chris Wilson
2017-02-10 10:29 ` Mika Kuoppala
2017-02-10 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-02-10 13:39 ` Joonas Lahtinen
2017-02-10 14:57 ` Chris Wilson
2 siblings, 1 reply; 5+ messages in thread
From: Joonas Lahtinen @ 2017-02-10 13:39 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On pe, 2017-02-10 at 10:14 +0000, Chris Wilson wrote:
> Now that we have fast top-down insertion into the drm_mm, we can use it
> for frequent runtime operations like insertion of the context object,
> whereas before we limited it to the one-off insertion of the pinned
> kernel context. Keeping the active context objects out of the mappable
> region of the global GTT (except under memory pressure) improves our
> ability to allocate mappable aperture region without triggering a GPU
> stall.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Always pin contexts into the high GGTT
2017-02-10 13:39 ` [PATCH] " Joonas Lahtinen
@ 2017-02-10 14:57 ` Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2017-02-10 14:57 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Fri, Feb 10, 2017 at 03:39:31PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-02-10 at 10:14 +0000, Chris Wilson wrote:
> > Now that we have fast top-down insertion into the drm_mm, we can use it
> > for frequent runtime operations like insertion of the context object,
> > whereas before we limited it to the one-off insertion of the pinned
> > kernel context. Keeping the active context objects out of the mappable
> > region of the global GTT (except under memory pressure) improves our
> > ability to allocate mappable aperture region without triggering a GPU
> > stall.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Thanks for the review, both of you. Pushed,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-02-10 10:14 [PATCH] drm/i915: Always pin contexts into the high GGTT Chris Wilson
2017-02-10 10:29 ` Mika Kuoppala
2017-02-10 10:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-02-10 13:39 ` [PATCH] " Joonas Lahtinen
2017-02-10 14:57 ` Chris Wilson
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