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From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
	bharata@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow
Date: Mon, 13 Feb 2017 12:54:14 +1100	[thread overview]
Message-ID: <20170213015414.GN25381@umbus> (raw)
In-Reply-To: <87k28yekze.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me>

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On Fri, Feb 10, 2017 at 09:49:17AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
> 
> > [ Unknown signature status ]
> > On Thu, Feb 09, 2017 at 04:04:04PM +0530, Nikunj A Dadhania wrote:
> >> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
> >> and corresponding defines. Moreover, CA32 is set when CA is set and
> >> OV32 is set when OV is set, there is no need to have a new
> >> fields in the CPUPPCState structure.
> >> 
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >
> > Um.. I don't quite understand this.  If CA always has the same value
> > as CA32, what's the point?
> 
> I am not clear either. I think that as CA was set for both 32/64-bit
> mode, that couldn't be changed for backward compatibility. CA32 should
> have affected only the instructions working one word variants.
> 
> Re-scanning the ISA 3.0, found this in 3.3.9 Fixed-Point Arithmetic
> Instructions:
> 
> =================================================================
> addic, addic., subfic, addc, subfc, adde, subfe,
> addme, subfme, addze, and subfze always set CA, to
> reflect the carry out of bit 0 in 64-bit mode and out of bit
> 32 in 32-bit mode. These instructions also always set
> CA32 to reflect the carry out of bit 32.
> =================================================================
> 
> Which is conflicting to what is said in 3.2.2 Fixed-Point Exception
> Register:
> =================================================================
> Carry32 (CA32)
> CA32 is set whenever CA is set, and is set to
> the same value that CA is defined to be set to
> in 32-bit mode.
> =================================================================

Well, that's certainly confusing.

Can you try and find out what's going on here within IBM, and repost
these patches once there's a straight story about how this bit works.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2017-02-13  2:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-09 10:33 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 1/6] target-ppc: generate exception for copy/paste Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 2/6] target-ppc: add slbieg instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 3/6] target-ppc: add slbsync implementation Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 4/6] target-ppc: add wait instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-10  0:10   ` David Gibson
2017-02-10  4:19     ` Nikunj A Dadhania
2017-02-13  1:54       ` David Gibson [this message]
2017-02-14  2:43       ` David Gibson
2017-02-14  3:05         ` Nikunj A Dadhania
2017-02-14  3:21           ` Richard Henderson
2017-02-16  5:08             ` Nikunj A Dadhania
2017-02-16 20:52               ` Richard Henderson
2017-02-17  4:47                 ` Nikunj A Dadhania
2017-02-17 19:33                   ` Richard Henderson
2017-02-09 10:34 ` [Qemu-devel] [PATCH 6/6] target-ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-10  0:28 ` [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 David Gibson

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