All of lore.kernel.org
 help / color / mirror / Atom feed
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: Richard Henderson <rth@twiddle.net>,
	David Gibson <david@gibson.dropbear.id.au>
Cc: bharata@linux.vnet.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow
Date: Fri, 17 Feb 2017 10:17:43 +0530	[thread overview]
Message-ID: <87y3x51l00.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> (raw)
In-Reply-To: <1d8317b8-208f-db66-0222-bf1beaaa965e@twiddle.net>

Richard Henderson <rth@twiddle.net> writes:

> On 02/16/2017 04:08 PM, Nikunj A Dadhania wrote:
>> Richard Henderson <rth@twiddle.net> writes:
>>
>>> On 02/14/2017 02:05 PM, Nikunj A Dadhania wrote:
>>>> Yes, you are right. I had a discussion with Paul Mackerras yesterday, he
>>>> explained to me in detail about the bits. I am working on the revised
>>>> implementation. Will detail it in the commit message.
>>>
>>> As you're working on this, consider changing the definition of cpu_ov such that
>>> the MSB is OV and bit 31 is OV32.
>>>
>>> E.g.
>>>
>>>
>>>   static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
>>>                                              TCGv arg1, TCGv arg2, int sub)
>>>   {
>>>       TCGv t0 = tcg_temp_new();
>>>
>>>       tcg_gen_xor_tl(cpu_ov, arg0, arg2);
>>>       tcg_gen_xor_tl(t0, arg1, arg2);
>>>       if (sub) {
>>>           tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
>>>       } else {
>>>           tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
>>>       }
>>>       tcg_temp_free(t0);
>>>       if (NARROW_MODE(ctx)) {
>>>           tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>>>       }
>>> -    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>>>       tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
>>>   }
>>>
>>>
>>> is all that is required for arithmetic to compute OV and OV32 into those two bits.
>>
>> How about the below?
>>
>> @@ -809,10 +809,11 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
>>          tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
>>      }
>>      tcg_temp_free(t0);
>> +    tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
>> +    tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
>>      if (NARROW_MODE(ctx)) {
>> -        tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>> +        tcg_gen_mov_tl(cpu_ov, cpu_ov32);
>>      }
>> -    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>>      tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
>>  }
>
> Why do you want to extract these bits?

Convinient to copy that to XER later.

Regards
Nikunj

  reply	other threads:[~2017-02-17  4:49 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-09 10:33 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 1/6] target-ppc: generate exception for copy/paste Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 2/6] target-ppc: add slbieg instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 3/6] target-ppc: add slbsync implementation Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 4/6] target-ppc: add wait instruction Nikunj A Dadhania
2017-02-09 10:34 ` [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-10  0:10   ` David Gibson
2017-02-10  4:19     ` Nikunj A Dadhania
2017-02-13  1:54       ` David Gibson
2017-02-14  2:43       ` David Gibson
2017-02-14  3:05         ` Nikunj A Dadhania
2017-02-14  3:21           ` Richard Henderson
2017-02-16  5:08             ` Nikunj A Dadhania
2017-02-16 20:52               ` Richard Henderson
2017-02-17  4:47                 ` Nikunj A Dadhania [this message]
2017-02-17 19:33                   ` Richard Henderson
2017-02-09 10:34 ` [Qemu-devel] [PATCH 6/6] target-ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-10  0:28 ` [Qemu-devel] [PATCH 0/6] POWER9 TCG enablements - part15 David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87y3x51l00.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me \
    --to=nikunj@linux.vnet.ibm.com \
    --cc=bharata@linux.vnet.ibm.com \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=rth@twiddle.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.