[PATCH v3] clk: renesas: mstp: ensure register writes complete

* [PATCH v3] clk: renesas: mstp: ensure register writes complete
@ 2017-02-14 16:08 Chris Brandt
  2017-02-14 19:00 ` Stephen Boyd
  0 siblings, 1 reply; 2+ messages in thread
From: Chris Brandt @ 2017-02-14 16:08 UTC (permalink / raw)
  To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
  Cc: Simon Horman, linux-clk, linux-renesas-soc, Chris Brandt

When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
* changed clk_readl to cpg_mstp_read to take into account 8-bit registers
* added Reviewed by Geert Uytterhoeven
v2:
* added Fixes because technically this is a bug fix
---
 drivers/clk/renesas/clk-mstp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 3ce819c..4067216 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -91,6 +91,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 		value |= bitmask;
 	cpg_mstp_write(group, value, group->smstpcr);
 
+	if (!group->mstpsr) {
+		/* dummy read to ensure write has completed */
+		cpg_mstp_read(group, group->smstpcr);
+		barrier_data(group->smstpcr);
+	}
+
 	spin_unlock_irqrestore(&group->lock, flags);
 
 	if (!enable || !group->mstpsr)
-- 
2.10.1

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