[PATCH v2 0/3] ARM: l2c: add l2c support for RZ/A1

[PATCH v2 0/3] ARM: l2c: add l2c support for RZ/A1

[Chris Brandt]

The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband
signals connected between the CPU and L2C. According the PL310 TRM,
sideband signals are optional.

If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands.

This series adds the option to not enable anything in the PL310 that
uses sidebands, and then adds L2C support to the RZ/A1 DT.

v2:
* Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a
  dummy l2c_write_sec function to keep FLZ from being enabled.


Chris Brandt (3):
  ARM: l2c: add pl310-no-sideband option
  ARM: shmobile: r7s72100: Enable L2 cache
  ARM: dts: r7s72100: add l2 cache

 Documentation/devicetree/bindings/arm/l2c2x0.txt |  2 ++
 arch/arm/boot/dts/r7s72100.dtsi                  | 10 ++++++++++
 arch/arm/mach-shmobile/setup-r7s72100.c          |  2 ++
 arch/arm/mm/cache-l2x0.c                         |  9 +++++++--
 4 files changed, 21 insertions(+), 2 deletions(-)

-- 
2.10.1

[PATCH v2 0/3] ARM: l2c: add l2c support for RZ/A1

[Chris Brandt]

The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband
signals connected between the CPU and L2C. According the PL310 TRM,
sideband signals are optional.

If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands.

This series adds the option to not enable anything in the PL310 that
uses sidebands, and then adds L2C support to the RZ/A1 DT.

v2:
* Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a
  dummy l2c_write_sec function to keep FLZ from being enabled.


Chris Brandt (3):
  ARM: l2c: add pl310-no-sideband option
  ARM: shmobile: r7s72100: Enable L2 cache
  ARM: dts: r7s72100: add l2 cache

 Documentation/devicetree/bindings/arm/l2c2x0.txt |  2 ++
 arch/arm/boot/dts/r7s72100.dtsi                  | 10 ++++++++++
 arch/arm/mach-shmobile/setup-r7s72100.c          |  2 ++
 arch/arm/mm/cache-l2x0.c                         |  9 +++++++--
 4 files changed, 21 insertions(+), 2 deletions(-)

-- 
2.10.1

[PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Chris Brandt]

If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands.

Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
 arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
index 917199f..85046d2 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -90,6 +90,8 @@ Optional properties:
 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
   <1> (forcibly enable), property absent (OS specific behavior,
   preferably retain firmware settings)
+- arm,pl310-no-sideband : disable all features that require sideband signals to
+  be connected between the CPU and L2 (PL310 only).
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2290be3..c744ac4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -57,6 +57,8 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
+static bool l2x0_no_sideband;
+
 /*
  * Common code for all cache controllers.
  */
@@ -620,7 +622,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 	u32 aux = l2x0_saved_regs.aux_ctrl;
 
 	if (rev >= L310_CACHE_ID_RTL_R2P0) {
-		if (cortex_a9) {
+		if (cortex_a9 && !l2x0_no_sideband) {
 			aux |= L310_AUX_CTRL_EARLY_BRESP;
 			pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
 		} else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
@@ -629,7 +631,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 		}
 	}
 
-	if (cortex_a9) {
+	if (cortex_a9 && !l2x0_no_sideband) {
 		u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
 		u32 acr = get_auxcr();
 
@@ -1200,6 +1202,9 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		*aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
 	}
 
+	if (of_property_read_bool(np, "arm,pl310-no-sideband"))
+		l2x0_no_sideband = true;
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
2.10.1


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[PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Chris Brandt]

If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
 Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
 arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
index 917199f..85046d2 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -90,6 +90,8 @@ Optional properties:
 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
   <1> (forcibly enable), property absent (OS specific behavior,
   preferably retain firmware settings)
+- arm,pl310-no-sideband : disable all features that require sideband signals to
+  be connected between the CPU and L2 (PL310 only).
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2290be3..c744ac4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -57,6 +57,8 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
+static bool l2x0_no_sideband;
+
 /*
  * Common code for all cache controllers.
  */
@@ -620,7 +622,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 	u32 aux = l2x0_saved_regs.aux_ctrl;
 
 	if (rev >= L310_CACHE_ID_RTL_R2P0) {
-		if (cortex_a9) {
+		if (cortex_a9 && !l2x0_no_sideband) {
 			aux |= L310_AUX_CTRL_EARLY_BRESP;
 			pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
 		} else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
@@ -629,7 +631,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 		}
 	}
 
-	if (cortex_a9) {
+	if (cortex_a9 && !l2x0_no_sideband) {
 		u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
 		u32 acr = get_auxcr();
 
@@ -1200,6 +1202,9 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		*aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
 	}
 
+	if (of_property_read_bool(np, "arm,pl310-no-sideband"))
+		l2x0_no_sideband = true;
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
2.10.1

[PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Chris Brandt]

If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
 Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
 arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
index 917199f..85046d2 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
@@ -90,6 +90,8 @@ Optional properties:
 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
   <1> (forcibly enable), property absent (OS specific behavior,
   preferably retain firmware settings)
+- arm,pl310-no-sideband : disable all features that require sideband signals to
+  be connected between the CPU and L2 (PL310 only).
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2290be3..c744ac4 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -57,6 +57,8 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
+static bool l2x0_no_sideband;
+
 /*
  * Common code for all cache controllers.
  */
@@ -620,7 +622,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 	u32 aux = l2x0_saved_regs.aux_ctrl;
 
 	if (rev >= L310_CACHE_ID_RTL_R2P0) {
-		if (cortex_a9) {
+		if (cortex_a9 && !l2x0_no_sideband) {
 			aux |= L310_AUX_CTRL_EARLY_BRESP;
 			pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
 		} else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
@@ -629,7 +631,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
 		}
 	}
 
-	if (cortex_a9) {
+	if (cortex_a9 && !l2x0_no_sideband) {
 		u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
 		u32 acr = get_auxcr();
 
@@ -1200,6 +1202,9 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		*aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
 	}
 
+	if (of_property_read_bool(np, "arm,pl310-no-sideband"))
+		l2x0_no_sideband = true;
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
2.10.1

[PATCH v2 2/3] ARM: shmobile: r7s72100: Enable L2 cache

[Chris Brandt]

Even though L2C is specified in the DT, you still need to add the aux
settings in the machine_desc.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* removed dummy l2c_write_sec function
---
 arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d46639f..319ca95 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
+	.l2c_aux_val    = 0,
+	.l2c_aux_mask   = ~0,
 	.init_early	= shmobile_init_delay,
 	.init_late	= shmobile_init_late,
 	.dt_compat	= r7s72100_boards_compat_dt,
-- 
2.10.1

[PATCH v2 2/3] ARM: shmobile: r7s72100: Enable L2 cache

[Chris Brandt]

Even though L2C is specified in the DT, you still need to add the aux
settings in the machine_desc.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* removed dummy l2c_write_sec function
---
 arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d46639f..319ca95 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
+	.l2c_aux_val    = 0,
+	.l2c_aux_mask   = ~0,
 	.init_early	= shmobile_init_delay,
 	.init_late	= shmobile_init_late,
 	.dt_compat	= r7s72100_boards_compat_dt,
-- 
2.10.1

[PATCH v2 3/3] ARM: dts: r7s72100: add l2 cache

[Chris Brandt]

Note that arm,pl301-no-sideband is required because the sideband signals
between the CPU and L2C were not connected in this SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* added "arm,pl310-no-sideband"
---
 arch/arm/boot/dts/r7s72100.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 74e684f..00b9972 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -177,6 +177,7 @@
 			compatible = "arm,cortex-a9";
 			reg = <0>;
 			clock-frequency = <400000000>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -368,6 +369,15 @@
 			<0xe8202000 0x1000>;
 	};
 
+	L2: cache-controller@3ffff000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x3ffff000 0x1000>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		arm,pl310-no-sideband;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	i2c0: i2c@fcfee000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
2.10.1

[PATCH v2 3/3] ARM: dts: r7s72100: add l2 cache

[Chris Brandt]

Note that arm,pl301-no-sideband is required because the sideband signals
between the CPU and L2C were not connected in this SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* added "arm,pl310-no-sideband"
---
 arch/arm/boot/dts/r7s72100.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 74e684f..00b9972 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -177,6 +177,7 @@
 			compatible = "arm,cortex-a9";
 			reg = <0>;
 			clock-frequency = <400000000>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -368,6 +369,15 @@
 			<0xe8202000 0x1000>;
 	};
 
+	L2: cache-controller at 3ffff000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x3ffff000 0x1000>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		arm,pl310-no-sideband;
+		cache-unified;
+		cache-level = <2>;
+	};
+
 	i2c0: i2c at fcfee000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
2.10.1

Re: [PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Rob Herring]

On Tue, Feb 07, 2017 at 12:09:27PM -0500, Chris Brandt wrote:
> If a PL310 is added to a system, but the sideband signals are not
> connected, some Cortex A9 optimizations cannot be used. In particular,
> enabling Full Line Zeros in the CA9 without sidebands connected will
> crash the system since the CA9 will expect the L2C to perform operations,
> yet the L2C never gets the commands.

I assume you are talking about just the AxUSER signals, not the 
AxCACHE signals too. That would be really broken. IIRC, the other AxUSER 
signals are just hints and no connection would not be a problem. This is 
the only one that requires coordination with enabling/disabling in the 
core. 

I think this should follow existing feature properties and explicitly 
disable the specific properties rather than have this indirection.

> 
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index 917199f..85046d2 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -90,6 +90,8 @@ Optional properties:
>  - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
>    <1> (forcibly enable), property absent (OS specific behavior,
>    preferably retain firmware settings)
> +- arm,pl310-no-sideband : disable all features that require sideband signals to
> +  be connected between the CPU and L2 (PL310 only).
>  
>  Example:
>  
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Re: [PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Rob Herring]

On Tue, Feb 07, 2017 at 12:09:27PM -0500, Chris Brandt wrote:
> If a PL310 is added to a system, but the sideband signals are not
> connected, some Cortex A9 optimizations cannot be used. In particular,
> enabling Full Line Zeros in the CA9 without sidebands connected will
> crash the system since the CA9 will expect the L2C to perform operations,
> yet the L2C never gets the commands.

I assume you are talking about just the AxUSER signals, not the 
AxCACHE signals too. That would be really broken. IIRC, the other AxUSER 
signals are just hints and no connection would not be a problem. This is 
the only one that requires coordination with enabling/disabling in the 
core. 

I think this should follow existing feature properties and explicitly 
disable the specific properties rather than have this indirection.

> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index 917199f..85046d2 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -90,6 +90,8 @@ Optional properties:
>  - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
>    <1> (forcibly enable), property absent (OS specific behavior,
>    preferably retain firmware settings)
> +- arm,pl310-no-sideband : disable all features that require sideband signals to
> +  be connected between the CPU and L2 (PL310 only).
>  
>  Example:
>  

[PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Rob Herring]

On Tue, Feb 07, 2017 at 12:09:27PM -0500, Chris Brandt wrote:
> If a PL310 is added to a system, but the sideband signals are not
> connected, some Cortex A9 optimizations cannot be used. In particular,
> enabling Full Line Zeros in the CA9 without sidebands connected will
> crash the system since the CA9 will expect the L2C to perform operations,
> yet the L2C never gets the commands.

I assume you are talking about just the AxUSER signals, not the 
AxCACHE signals too. That would be really broken. IIRC, the other AxUSER 
signals are just hints and no connection would not be a problem. This is 
the only one that requires coordination with enabling/disabling in the 
core. 

I think this should follow existing feature properties and explicitly 
disable the specific properties rather than have this indirection.

> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 9 +++++++--
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index 917199f..85046d2 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -90,6 +90,8 @@ Optional properties:
>  - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
>    <1> (forcibly enable), property absent (OS specific behavior,
>    preferably retain firmware settings)
> +- arm,pl310-no-sideband : disable all features that require sideband signals to
> +  be connected between the CPU and L2 (PL310 only).
>  
>  Example:
>  

RE: [PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Chris Brandt]

On Wednesday, February 15, 2017, Rob Herring wrote:
> On Tue, Feb 07, 2017 at 12:09:27PM -0500, Chris Brandt wrote:
> > If a PL310 is added to a system, but the sideband signals are not
> > connected, some Cortex A9 optimizations cannot be used. In particular,
> > enabling Full Line Zeros in the CA9 without sidebands connected will
> > crash the system since the CA9 will expect the L2C to perform
> > operations, yet the L2C never gets the commands.
> 
> I assume you are talking about just the AxUSER signals, not the AxCACHE
> signals too. That would be really broken. IIRC, the other AxUSER signals
> are just hints and no connection would not be a problem. This is the only
> one that requires coordination with enabling/disabling in the core.

Yes, just the AxUSER, hence none of the "2.5.5 Cortex-A9 optimizations" work.
Well, except "Store buffer device limitation" because that doesn't use sideband
signals.

Like you mentioned, having 'Early BRESP' enabled but not used doesn't hurt
anything. I was just blocking that so it would print out that it was enabled
and give users false hope (not that they are looking at the boot log that closely
anyway.) FLZ is the killer.


> I think this should follow existing feature properties and explicitly
> disable the specific properties rather than have this indirection.

I can change the code to:

  "arm,early-bresp-disable"
  "arm,fill-line-zero-disable"


As I said, blocking BRESP is only for keeping the log message from coming out.
If it's preferred to not block anything that doesn't break anything, I can just
add "arm,fill-line-zero-disable" only. Just let me know.


Chris

[PATCH v2 1/3] ARM: l2c: add pl310-no-sideband option

[Chris Brandt]

On Wednesday, February 15, 2017, Rob Herring wrote:
> On Tue, Feb 07, 2017 at 12:09:27PM -0500, Chris Brandt wrote:
> > If a PL310 is added to a system, but the sideband signals are not
> > connected, some Cortex A9 optimizations cannot be used. In particular,
> > enabling Full Line Zeros in the CA9 without sidebands connected will
> > crash the system since the CA9 will expect the L2C to perform
> > operations, yet the L2C never gets the commands.
> 
> I assume you are talking about just the AxUSER signals, not the AxCACHE
> signals too. That would be really broken. IIRC, the other AxUSER signals
> are just hints and no connection would not be a problem. This is the only
> one that requires coordination with enabling/disabling in the core.

Yes, just the AxUSER, hence none of the "2.5.5 Cortex-A9 optimizations" work.
Well, except "Store buffer device limitation" because that doesn't use sideband
signals.

Like you mentioned, having 'Early BRESP' enabled but not used doesn't hurt
anything. I was just blocking that so it would print out that it was enabled
and give users false hope (not that they are looking at the boot log that closely
anyway.) FLZ is the killer.


> I think this should follow existing feature properties and explicitly
> disable the specific properties rather than have this indirection.

I can change the code to:

  "arm,early-bresp-disable"
  "arm,fill-line-zero-disable"


As I said, blocking BRESP is only for keeping the log message from coming out.
If it's preferred to not block anything that doesn't break anything, I can just
add "arm,fill-line-zero-disable" only. Just let me know.


Chris