[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Icenowy Zheng]

2017?2?13? 15:17? Maxime Ripard <maxime.ripard@free-electrons.com>???
>
> Hi, 
>
> On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: 
> > @@ -0,0 +1,13 @@ 
> > +CONFIG_ARM=y 
> > +CONFIG_ARCH_SUNXI=y 
> > +# CONFIG_ARMV7_NONSEC is not set 
>
> Why? It doesn't have Trustzone? 

The CPU has Secure mode, but no TrustZone Peripheral Controller, neither SMP.

>
> Thanks, 
> Maxime 
>
> -- 
> Maxime Ripard, Free Electrons 
> Embedded Linux and Kernel engineering 
> http://free-electrons.com 

[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Maxime Ripard]

On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
> 
> 2017?2?13? 15:17? Maxime Ripard <maxime.ripard@free-electrons.com>???
> >
> > Hi, 
> >
> > On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: 
> > > @@ -0,0 +1,13 @@ 
> > > +CONFIG_ARM=y 
> > > +CONFIG_ARCH_SUNXI=y 
> > > +# CONFIG_ARMV7_NONSEC is not set 
> >
> > Why? It doesn't have Trustzone? 
> 
> The CPU has Secure mode, but no TrustZone Peripheral Controller,
> neither SMP.

Still, booting in HYP and having PSCI sounds like a good idea.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[André Przywara]

On 14/02/17 07:36, Maxime Ripard wrote:
> On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
>>
>> 2017?2?13? 15:17? Maxime Ripard <maxime.ripard@free-electrons.com>???
>>>
>>> Hi, 
>>>
>>> On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: 
>>>> @@ -0,0 +1,13 @@ 
>>>> +CONFIG_ARM=y 
>>>> +CONFIG_ARCH_SUNXI=y 
>>>> +# CONFIG_ARMV7_NONSEC is not set 
>>>
>>> Why? It doesn't have Trustzone? 
>>
>> The CPU has Secure mode, but no TrustZone Peripheral Controller,
>> neither SMP.
> 
> Still, booting in HYP and having PSCI sounds like a good idea.

Yes, so without this option Linux will run in secure state, if I am not
mistaken, which is discouraged. Instead we should enter Linux in
(non-secure) HYP mode [1], which will allow KVM, for instance. So I'd
recommend to remove this last line.
Whether we need PSCI on an UP system is a separate question, I don't
know from the top of my head if ARM(32) uses it for suspend/resume. But
anyway this is not implemented in U-Boot's PSCI implementation, IIRC.
So for just disabling PSCI we could use:

+# CONFIG_ARMV7_PSCI is not set

Cheers,
Andre.

[1] http://lxr.free-electrons.com/source/Documentation/arm/Booting#L188

[U-Boot] [linux-sunxi] Re: [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Chen-Yu Tsai]

On Thu, Feb 16, 2017 at 9:32 AM, Andr? Przywara <andre.przywara@arm.com> wrote:
> On 14/02/17 07:36, Maxime Ripard wrote:
>> On Mon, Feb 13, 2017 at 04:12:04PM +0800, Icenowy Zheng wrote:
>>>
>>> 2017?2?13? 15:17? Maxime Ripard <maxime.ripard@free-electrons.com>???
>>>>
>>>> Hi,
>>>>
>>>> On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote:
>>>>> @@ -0,0 +1,13 @@
>>>>> +CONFIG_ARM=y
>>>>> +CONFIG_ARCH_SUNXI=y
>>>>> +# CONFIG_ARMV7_NONSEC is not set
>>>>
>>>> Why? It doesn't have Trustzone?
>>>
>>> The CPU has Secure mode, but no TrustZone Peripheral Controller,
>>> neither SMP.
>>
>> Still, booting in HYP and having PSCI sounds like a good idea.
>
> Yes, so without this option Linux will run in secure state, if I am not
> mistaken, which is discouraged. Instead we should enter Linux in
> (non-secure) HYP mode [1], which will allow KVM, for instance. So I'd
> recommend to remove this last line.
> Whether we need PSCI on an UP system is a separate question, I don't
> know from the top of my head if ARM(32) uses it for suspend/resume. But
> anyway this is not implemented in U-Boot's PSCI implementation, IIRC.
> So for just disabling PSCI we could use:
>
> +# CONFIG_ARMV7_PSCI is not set

We'll need to add some more code (or disable some) though. If PSCI isn't
enabled, U-boot will try to bring up the cores (by calling some non-existent-
in-sunxi function) and put them in a holding pen.

I guess Icenowy can figure that bit out.

ChenYu

>
> Cheers,
> Andre.
>
> [1] http://lxr.free-electrons.com/source/Documentation/arm/Booting#L188
>
> --
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[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Maxime Ripard]

On Thu, Feb 16, 2017 at 01:32:19AM +0000, Andr? Przywara wrote:
> Whether we need PSCI on an UP system is a separate question, I don't
> know from the top of my head if ARM(32) uses it for suspend/resume. But
> anyway this is not implemented in U-Boot's PSCI implementation, IIRC.

Antoine (in CC) did this for the A13 in order to implement cpuidle.

http://lists.denx.de/pipermail/u-boot/2016-October/271038.html

So it's definitely something we can (and should) do.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Jagan Teki]

On Sat, Feb 11, 2017 at 4:41 PM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> Lichee Pi Zero is a development board with a V3s SoC.
>
> Add support for it.

Add some details about board/features ?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Maxime Ripard]

Hi,

On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote:
> @@ -0,0 +1,13 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +# CONFIG_ARMV7_NONSEC is not set

Why? It doesn't have Trustzone?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero

[Icenowy Zheng]

Lichee Pi Zero is a development board with a V3s SoC.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/dts/Makefile                    |  2 +
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83 ++++++++++++++++++++++++++++++++
 board/sunxi/MAINTAINERS                  |  5 ++
 configs/LicheePi_Zero_defconfig          | 13 +++++
 4 files changed, 103 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
 create mode 100644 configs/LicheePi_Zero_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 796b24d76e..a18528d989 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
 	sun8i-h3-nanopi-neo.dtb
+dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
 	sun50i-a64-pine64-plus.dtb \
 	sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
new file mode 100644
index 0000000000..3d9168cbae
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-v3s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Lichee Pi Zero";
+	compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins_a>;
+	pinctrl-names = "default";
+	broken-cd;
+	bus-width = <4>;
+	vmmc-supply = <&reg_vcc3v3>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2321b8b08f..640c26328a 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -182,6 +182,11 @@ M:	Jelle de Jong <jelledejong@powercraft.nl>
 S:	Maintained
 F:	configs/Lamobo_R1_defconfig
 
+LICHEEPI-ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/LicheePi_Zero_defconfig
+
 LINKSPRITE-PCDUINO BOARD
 M:	Zoltan Herpai <wigyori@uid0.hu>
 S:	Maintained
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
new file mode 100644
index 0000000000..42414a81a7
--- /dev/null
+++ b/configs/LicheePi_Zero_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+# CONFIG_ARMV7_NONSEC is not set
+CONFIG_MACH_SUN8I_V3S=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=14779
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_NETDEVICES is not set
-- 
2.11.0