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* [PATCH] i915/drm/HuC: Motivation behind having HuC
@ 2017-02-16  1:29 Anusha Srivatsa
  2017-02-16  1:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Anusha Srivatsa @ 2017-02-16  1:29 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lyncoln Cheng, Rodrigo Vivi

Correct the comment in intel_huc.c that tells the motivation
behind having HuC, a dedicated firmware for media.

Cc: Lyncoln Cheng <lyncoln.cheng@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_huc.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index c144609..0641afe 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -29,9 +29,14 @@
  * DOC: HuC Firmware
  *
  * Motivation:
- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
- * Efficiency Video Coding) operations. Userspace can use the firmware
- * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * HuC is designed to offload some of the media functions from
+ * the CPU to GPU. These include but are not limited to bitrate
+ * control, header parsing. For example in the case of bitrate control,
+ * driver invokes HuC in the beginning of each frame encoding pass,
+ * encode bitrate is adjusted by the calculation done by HuC. Both
+ * the HuC hardware and the encode hardcode reside in GPU. Using HuC
+ * will save unnecessary CPU-GPU synchronization
  *
  * Implementation:
  * The same firmware loader is used as the GuC. However, the actual
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* ✗ Fi.CI.BAT: failure for i915/drm/HuC: Motivation behind having HuC
  2017-02-16  1:29 [PATCH] i915/drm/HuC: Motivation behind having HuC Anusha Srivatsa
@ 2017-02-16  1:52 ` Patchwork
  2017-02-16  8:53 ` Patchwork
  2017-02-16 21:33 ` [PATCH] " Rodrigo Vivi
  2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-02-16  1:52 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

== Series Details ==

Series: i915/drm/HuC: Motivation behind having HuC
URL   : https://patchwork.freedesktop.org/series/19746/
State : failure

== Summary ==

Series 19746v1 i915/drm/HuC: Motivation behind having HuC
https://patchwork.freedesktop.org/api/1.0/series/19746/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a-frame-sequence:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup read-crc-pipe-b:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup read-crc-pipe-b-frame-sequence:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup suspend-read-crc-pipe-a:
                pass       -> DMESG-WARN (fi-snb-2520m)

fi-bdw-5557u     total:252  pass:238  dwarn:3   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:252  pass:210  dwarn:3   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:230  dwarn:3   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:222  dwarn:3   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:218  dwarn:3   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:233  dwarn:3   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:252  pass:233  dwarn:3   dfail:0   fail:0   skip:16 
fi-ilk-650       total:252  pass:199  dwarn:3   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:252  pass:239  dwarn:3   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:252  pass:232  dwarn:3   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:252  pass:239  dwarn:3   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:252  pass:217  dwarn:4   dfail:3   fail:0   skip:28 
fi-snb-2600      total:252  pass:220  dwarn:3   dfail:0   fail:0   skip:29 

890e171e84eb11944701de9d53c1162dd5c38142 drm-tip: 2017y-02m-15d-15h-34m-13s UTC integration manifest
e6810fc i915/drm/HuC: Motivation behind having HuC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3836/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* ✗ Fi.CI.BAT: failure for i915/drm/HuC: Motivation behind having HuC
  2017-02-16  1:29 [PATCH] i915/drm/HuC: Motivation behind having HuC Anusha Srivatsa
  2017-02-16  1:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-02-16  8:53 ` Patchwork
  2017-02-16 21:33 ` [PATCH] " Rodrigo Vivi
  2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-02-16  8:53 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

== Series Details ==

Series: i915/drm/HuC: Motivation behind having HuC
URL   : https://patchwork.freedesktop.org/series/19746/
State : failure

== Summary ==

Series 19746v1 i915/drm/HuC: Motivation behind having HuC
https://patchwork.freedesktop.org/api/1.0/series/19746/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup nonblocking-crc-pipe-a:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup nonblocking-crc-pipe-a-frame-sequence:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup nonblocking-crc-pipe-b:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup nonblocking-crc-pipe-b-frame-sequence:
                pass       -> DMESG-FAIL (fi-snb-2520m)
        Subgroup nonblocking-crc-pipe-c:
                skip       -> INCOMPLETE (fi-snb-2520m)

fi-bdw-5557u     total:252  pass:238  dwarn:3   dfail:0   fail:0   skip:11 
fi-bsw-n3050     total:252  pass:210  dwarn:3   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:230  dwarn:3   dfail:0   fail:0   skip:19 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:222  dwarn:3   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:218  dwarn:3   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:233  dwarn:3   dfail:0   fail:0   skip:16 
fi-hsw-4770r     total:252  pass:233  dwarn:3   dfail:0   fail:0   skip:16 
fi-ilk-650       total:252  pass:199  dwarn:3   dfail:0   fail:0   skip:50 
fi-ivb-3520m     total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-ivb-3770      total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-kbl-7500u     total:252  pass:231  dwarn:3   dfail:0   fail:0   skip:18 
fi-skl-6260u     total:252  pass:239  dwarn:3   dfail:0   fail:0   skip:10 
fi-skl-6700hq    total:252  pass:232  dwarn:3   dfail:0   fail:0   skip:17 
fi-skl-6700k     total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hq    total:252  pass:239  dwarn:3   dfail:0   fail:0   skip:10 
fi-snb-2520m     total:201  pass:176  dwarn:0   dfail:5   fail:0   skip:19 
fi-snb-2600      total:252  pass:220  dwarn:3   dfail:0   fail:0   skip:29 

5bec901e7ea94b6e656c8b0813c45c90d37a5673 drm-tip: 2017y-02m-16d-04h-31m-41s UTC integration manifest
249bb08 i915/drm/HuC: Motivation behind having HuC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3839/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] i915/drm/HuC: Motivation behind having HuC
  2017-02-16  1:29 [PATCH] i915/drm/HuC: Motivation behind having HuC Anusha Srivatsa
  2017-02-16  1:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
  2017-02-16  8:53 ` Patchwork
@ 2017-02-16 21:33 ` Rodrigo Vivi
  2 siblings, 0 replies; 4+ messages in thread
From: Rodrigo Vivi @ 2017-02-16 21:33 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx, Lyncoln Cheng, Rodrigo Vivi

This matches the description we got for release so,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Wed, Feb 15, 2017 at 5:29 PM, Anusha Srivatsa
<anusha.srivatsa@intel.com> wrote:
> Correct the comment in intel_huc.c that tells the motivation
> behind having HuC, a dedicated firmware for media.
>
> Cc: Lyncoln Cheng <lyncoln.cheng@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_huc.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index c144609..0641afe 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -29,9 +29,14 @@
>   * DOC: HuC Firmware
>   *
>   * Motivation:
> - * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> - * Efficiency Video Coding) operations. Userspace can use the firmware
> - * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * HuC is designed to offload some of the media functions from
> + * the CPU to GPU. These include but are not limited to bitrate
> + * control, header parsing. For example in the case of bitrate control,
> + * driver invokes HuC in the beginning of each frame encoding pass,
> + * encode bitrate is adjusted by the calculation done by HuC. Both
> + * the HuC hardware and the encode hardcode reside in GPU. Using HuC
> + * will save unnecessary CPU-GPU synchronization
>   *
>   * Implementation:
>   * The same firmware loader is used as the GuC. However, the actual
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-02-16 21:33 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-02-16  1:29 [PATCH] i915/drm/HuC: Motivation behind having HuC Anusha Srivatsa
2017-02-16  1:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-02-16  8:53 ` Patchwork
2017-02-16 21:33 ` [PATCH] " Rodrigo Vivi

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