From: Chris Brandt <chris.brandt@renesas.com> To: Simon Horman <horms+renesas@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>, Geert Uytterhoeven <geert@linux-m68k.org>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Russell King <linux@armlinux.org.uk>, Brad Mouring <brad.mouring@ni.com>, Andrey Smirnov <andrew.smirnov@gmail.com>, Arnd Bergmann <arnd@arndb.de>, Richard Cochran <rcochran@linutronix.de> Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Brandt <chris.brandt@renesas.com> Subject: [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 Date: Thu, 16 Feb 2017 10:37:23 -0500 [thread overview] Message-ID: <20170216153726.22919-1-chris.brandt@renesas.com> (raw) The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband signals connected between the CPU and L2C. According the PL310 TRM, sideband signals are optional. If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. This series adds the option to not enable anything in the PL310 that uses sidebands, and then adds L2C support to the RZ/A1 DT. v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a dummy l2c_write_sec function to keep FLZ from being enabled. Chris Brandt (3): ARM: l2c: allow CA9 optimizations to be disabled ARM: shmobile: r7s72100: Enable L2 cache ARM: dts: r7s72100: add l2 cache Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 4 files changed, 27 insertions(+), 2 deletions(-) -- 2.10.1
WARNING: multiple messages have this Message-ID (diff)
From: chris.brandt@renesas.com (Chris Brandt) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 Date: Thu, 16 Feb 2017 10:37:23 -0500 [thread overview] Message-ID: <20170216153726.22919-1-chris.brandt@renesas.com> (raw) The PL310 in the Renesas RZ/A1 SoC (R7S72100) does not have the sideband signals connected between the CPU and L2C. According the PL310 TRM, sideband signals are optional. If a PL310 is added to a system, but the sideband signals are not connected, some Cortex A9 optimizations cannot be used. In particular, enabling Full Line Zeros in the CA9 without sidebands connected will crash the system since the CA9 will expect the L2C to perform operations, yet the L2C never gets the commands. This series adds the option to not enable anything in the PL310 that uses sidebands, and then adds L2C support to the RZ/A1 DT. v3: * split "arm,pl310-no-sideband" into "arm,early-bresp-disable" and "arm,full-line-zero-disable" v2: * Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a dummy l2c_write_sec function to keep FLZ from being enabled. Chris Brandt (3): ARM: l2c: allow CA9 optimizations to be disabled ARM: shmobile: r7s72100: Enable L2 cache ARM: dts: r7s72100: add l2 cache Documentation/devicetree/bindings/arm/l2c2x0.txt | 3 +++ arch/arm/boot/dts/r7s72100.dtsi | 11 +++++++++++ arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ arch/arm/mm/cache-l2x0.c | 13 +++++++++++-- 4 files changed, 27 insertions(+), 2 deletions(-) -- 2.10.1
next reply other threads:[~2017-02-16 15:37 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-02-16 15:37 Chris Brandt [this message] 2017-02-16 15:37 ` [PATCH v3 0/3] ARM: l2c: add l2c support for RZ/A1 Chris Brandt 2017-02-16 15:37 ` [PATCH v3 1/3] ARM: l2c: allow CA9 optimizations to be disabled Chris Brandt 2017-02-16 15:37 ` Chris Brandt [not found] ` <20170216153726.22919-2-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> 2017-02-16 16:06 ` Russell King - ARM Linux 2017-02-16 16:06 ` Russell King - ARM Linux 2017-02-16 16:06 ` Russell King - ARM Linux [not found] ` <20170216153726.22919-1-chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> 2017-02-16 15:37 ` [PATCH v3 2/3] ARM: shmobile: r7s72100: Enable L2 cache Chris Brandt 2017-02-16 15:37 ` Chris Brandt 2017-02-16 15:37 ` Chris Brandt 2017-02-16 15:37 ` [PATCH v3 3/3] ARM: dts: r7s72100: add l2 cache Chris Brandt 2017-02-16 15:37 ` Chris Brandt
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