From: Sean Paul <seanpaul@chromium.org>
To: Chris Zhong <zyw@rock-chips.com>
Cc: john@metanate.com, dianders@chromium.org, tfiga@chromium.org,
heiko@sntech.de, yzq@rock-chips.com, mark.rutland@arm.com,
devicetree@vger.kernel.org, robh+dt@kernel.org,
galak@codeaurora.org, pawel.moll@arm.com, seanpaul@chromium.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
Date: Tue, 21 Feb 2017 10:40:10 -0500 [thread overview]
Message-ID: <20170221154010.GB25168@art_vandelay> (raw)
In-Reply-To: <1487577744-2855-7-git-send-email-zyw@rock-chips.com>
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
WARNING: multiple messages have this Message-ID (diff)
From: Sean Paul <seanpaul@chromium.org>
To: Chris Zhong <zyw@rock-chips.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
pawel.moll@arm.com, yzq@rock-chips.com,
linux-kernel@vger.kernel.org, dianders@chromium.org,
dri-devel@lists.freedesktop.org, tfiga@chromium.org,
linux-rockchip@lists.infradead.org, robh+dt@kernel.org,
galak@codeaurora.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
Date: Tue, 21 Feb 2017 10:40:10 -0500 [thread overview]
Message-ID: <20170221154010.GB25168@art_vandelay> (raw)
In-Reply-To: <1487577744-2855-7-git-send-email-zyw@rock-chips.com>
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: seanpaul@chromium.org (Sean Paul)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel
Date: Tue, 21 Feb 2017 10:40:10 -0500 [thread overview]
Message-ID: <20170221154010.GB25168@art_vandelay> (raw)
In-Reply-To: <1487577744-2855-7-git-send-email-zyw@rock-chips.com>
On Mon, Feb 20, 2017 at 04:02:22PM +0800, Chris Zhong wrote:
> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
> for some panel, it will cause the screen display is not normal, so
> increases the badnwidth to 1 / 0.8.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index c2d7674..a653384 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -532,8 +532,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
>
> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
> if (mpclk) {
> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> if (tmp < max_mbps)
> target_mbps = tmp;
> else
> --
> 2.6.3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
next prev parent reply other threads:[~2017-02-21 15:40 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-20 8:02 [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 1/7] dt-bindings: add rk3399 support for dw-mipi-rockchip Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 2/7] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 3/7] drm/rockchip/dsi: dw-mipi: correct the coding style Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 4/7] drm/rockchip/dsi: remove mode_valid function Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 5/7] dt-bindings: add power domain node for dw-mipi-rockchip Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` [RESEND PATCH v7 6/7] drm/rockchip/dsi: fix insufficient bandwidth of some panel Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-21 15:40 ` Sean Paul [this message]
2017-02-21 15:40 ` Sean Paul
2017-02-21 15:40 ` Sean Paul
2017-02-20 8:02 ` [RESEND PATCH v7 7/7] drm/rockchip/dsi: add dw-mipi power domain support Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-20 8:02 ` Chris Zhong
2017-02-21 15:39 ` [RESEND PATCH v7 0/7] Rockchip dw-mipi-dsi driver Sean Paul
2017-02-21 15:39 ` Sean Paul
2017-02-21 15:39 ` Sean Paul
2017-02-22 1:44 ` Chris Zhong
2017-02-22 1:44 ` Chris Zhong
2017-02-22 1:44 ` Chris Zhong
2017-02-22 13:43 ` John Keeping
2017-02-22 13:43 ` John Keeping
2017-02-22 13:43 ` John Keeping
2017-02-22 15:57 ` Sean Paul
2017-02-22 15:57 ` Sean Paul
2017-02-22 15:57 ` Sean Paul
2017-02-22 18:55 ` John Keeping
2017-02-22 18:55 ` John Keeping
2017-02-22 18:55 ` John Keeping
2017-02-22 22:10 ` Sean Paul
2017-02-22 22:10 ` Sean Paul
2017-02-22 22:10 ` Sean Paul
2017-02-23 0:25 ` Chris Zhong
2017-02-23 0:25 ` Chris Zhong
2017-02-23 0:25 ` Chris Zhong
2017-03-01 20:02 ` Sean Paul
2017-03-01 20:02 ` Sean Paul
2017-03-01 20:02 ` Sean Paul
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