* [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222
@ 2017-02-22 6:33 David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations David Gibson
` (44 more replies)
0 siblings, 45 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
The following changes since commit 796b288f7be875045670f963ce99991b3c8e96ac:
Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging (2017-02-21 15:48:22 +0000)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170222
for you to fetch changes up to fb6971c110387cf597b58c411658e3d15cc6c6fb:
hw/ppc/ppc405_uc.c: Avoid integer overflows (2017-02-22 14:28:53 +1100)
NOTE: This pull request hasn't passed the full set of tests I usually
run, because there seem to be problems with those on current master
anyway: some of "make check" seems to wedge, and a number of travis
builds timed out. AFAICT this series doesn't cause any failures that
aren't already present in upstream.
----------------------------------------------------------------
ppc patch queue for 2017-02-22
This pull request has:
* Yet more POWER9 instruction implementations
* Some extensions to the softfloat code which are necesssary for
some of those instructions
* Some preliminary patches in preparation for POWER9 softmmu
implementation
* Igor Mammedov's cleanups to unify hotplug cpu handling across
architectures
* Assorted bugfixes
The softfloat and cpu hotplug changes aren't entirely ppc specific (in
fact the hotplug stuff contains some pc specific patches). However
they're included here because ppc is one of the main beneficiaries,
and the series depend on some ppc specific patches.
----------------------------------------------------------------
Alex Zuepke (1):
target-ppc: fix Book-E TLB matching
Balamuruhan S (2):
target-ppc: implement load atomic instruction
target-ppc: implement store atomic instruction
Bharata B Rao (7):
target-ppc: Add xsmaxcdp and xsmincdp instructions
target-ppc: Add xsmaxjdp and xsminjdp instructions
softfloat: Add round-to-odd rounding mode
softfloat: Add float128_to_uint64_round_to_zero()
softfloat: Add float128_to_uint32_round_to_zero()
target-ppc: Implement round to odd variants of quad FP instructions
target-ppc: Add xscvqpudz and xscvqpuwz instructions
Igor Mammedov (11):
spapr: cpu core: separate child threads destruction from machine state operations
spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c
spapr: make cpu core unplug follow expected hotunplug call flow
machine: move possible_cpus to MachineState
pc: move pcms->possible_cpus init out of pc_cpus_init()
pc: calculate topology only once when possible_cpus is initialised
pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object
change CPUArchId.cpu type to Object*
spapr: reuse machine->possible_cpus instead of cores[]
machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag
Jose Ricardo Ziviani (4):
ppc: implement xsrqpi[x] instruction
ppc: implement xsrqpxp instruction
ppc: implement xssqrtqp instruction
ppc: implement xssubqp instruction
Laurent Vivier (3):
mac99: replace debug printf with trace points
ppc4xx: replace debug printf with trace points
spapr: replace debug printf with trace points
Nikunj A Dadhania (4):
target-ppc: generate exception for copy/paste
target-ppc: add slbieg instruction
target-ppc: add slbsync implementation
target-ppc: add wait instruction
Peter Maydell (1):
hw/ppc/ppc405_uc.c: Avoid integer overflows
Sam Bobroff (3):
spapr: fix off-by-one error in spapr_ovec_populate_dt()
target-ppc, tcg: fix usermode segfault with pthread_create()
hw/net/spapr_llan: 6 byte mac address device tree entry
Suraj Jitindar Singh (4):
target/ppc: Fix LPCR DPFD mask define
target/ppc/POWER9: Add ISAv3.00 MMU definition
target/ppc/POWER9: Adapt LPCR handling for POWER9
target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
Thomas Huth (3):
hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings
hw/pci-host/prep: Do not use hw_error() in realize function
hw/ppc/spapr: Check for valid page size when hot plugging memory
fpu/softfloat.c | 108 ++++++++++++-
hw/acpi/cpu.c | 2 +-
hw/core/machine.c | 31 ++++
hw/i386/pc.c | 126 +++++++--------
hw/net/spapr_llan.c | 18 ++-
hw/pci-host/prep.c | 11 +-
hw/ppc/mac_newworld.c | 15 +-
hw/ppc/pnv.c | 6 +-
hw/ppc/ppc405_uc.c | 6 +-
hw/ppc/ppc4xx_pci.c | 13 +-
hw/ppc/spapr.c | 255 ++++++++++++++++++++++++-----
hw/ppc/spapr_cpu_core.c | 137 +---------------
hw/ppc/spapr_ovec.c | 19 +--
hw/ppc/trace-events | 12 ++
include/fpu/softfloat.h | 5 +
include/hw/boards.h | 16 +-
include/hw/i386/pc.h | 1 -
include/hw/ppc/spapr.h | 1 -
include/hw/ppc/spapr_cpu_core.h | 6 -
linux-user/main.c | 3 +-
monitor.c | 4 +-
target/ppc/cpu-qom.h | 5 +-
target/ppc/cpu.h | 20 ++-
target/ppc/fpu_helper.c | 312 ++++++++++++++++++++++++++++++++++--
target/ppc/helper.h | 11 ++
target/ppc/internal.h | 3 +
target/ppc/kvm.c | 32 +++-
target/ppc/kvm_ppc.h | 7 +
target/ppc/mmu-hash64.c | 44 ++++-
target/ppc/mmu_helper.c | 4 +-
target/ppc/translate.c | 153 ++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 11 ++
target/ppc/translate/vsx-ops.inc.c | 21 +++
target/ppc/translate_init.c | 27 +++-
vl.c | 2 +-
35 files changed, 1093 insertions(+), 354 deletions(-)
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c David Gibson
` (43 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Split off destroying VCPU threads from drc callback
spapr_core_release() into new spapr_cpu_core_unrealizefn()
which takes care of internal cpu core state cleanup (i.e.
VCPU threads) and is called when object_unparent(core)
is called.
That leaves spapr_core_release() only with board mgmt
code, which will be moved to board related file in
follow up patch along with the rest on hotplug callbacks.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_cpu_core.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 9dddaeb..b9e5f80 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -111,11 +111,19 @@ char *spapr_get_cpu_core_type(const char *model)
static void spapr_core_release(DeviceState *dev, void *opaque)
{
+ sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ CPUCore *cc = CPU_CORE(dev);
+
+ spapr->cores[cc->core_id / smp_threads] = NULL;
+ object_unparent(OBJECT(dev));
+}
+
+static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
+{
sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
const char *typename = object_class_get_name(scc->cpu_class);
size_t size = object_type_get_instance_size(typename);
- sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
CPUCore *cc = CPU_CORE(dev);
int i;
@@ -129,11 +137,7 @@ static void spapr_core_release(DeviceState *dev, void *opaque)
cpu_remove_sync(cs);
object_unparent(obj);
}
-
- spapr->cores[cc->core_id / smp_threads] = NULL;
-
g_free(sc->threads);
- object_unparent(OBJECT(dev));
}
void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -368,6 +372,7 @@ void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
dc->realize = spapr_cpu_core_realize;
+ dc->unrealize = spapr_cpu_core_unrealizefn;
scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
g_assert(scc->cpu_class);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow David Gibson
` (42 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
spapr_core_pre_plug/spapr_core_plug/spapr_core_unplug() are managing
wiring CPU core into spapr machine state and not internal CPU core state.
So move them from spapr_cpu_core.c to spapr.c where other similar
(spapr_memory_[foo]plug()) callbacks are located, which also matches
x86 target practice.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 138 ++++++++++++++++++++++++++++++++++++++++
hw/ppc/spapr_cpu_core.c | 138 ----------------------------------------
include/hw/ppc/spapr_cpu_core.h | 6 --
3 files changed, 138 insertions(+), 144 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e465d7a..8c2efd8 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2488,6 +2488,144 @@ void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
return fdt;
}
+static void spapr_core_release(DeviceState *dev, void *opaque)
+{
+ sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ CPUCore *cc = CPU_CORE(dev);
+
+ spapr->cores[cc->core_id / smp_threads] = NULL;
+ object_unparent(OBJECT(dev));
+}
+
+static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
+ Error **errp)
+{
+ CPUCore *cc = CPU_CORE(dev);
+ int smt = kvmppc_smt_threads();
+ int index = cc->core_id / smp_threads;
+ sPAPRDRConnector *drc =
+ spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
+ sPAPRDRConnectorClass *drck;
+ Error *local_err = NULL;
+
+ if (index == 0) {
+ error_setg(errp, "Boot CPU core may not be unplugged");
+ return;
+ }
+
+ g_assert(drc);
+
+ drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ spapr_hotplug_req_remove_by_index(drc);
+}
+
+static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
+ Error **errp)
+{
+ sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
+ MachineClass *mc = MACHINE_GET_CLASS(spapr);
+ sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
+ CPUCore *cc = CPU_CORE(dev);
+ CPUState *cs = CPU(core->threads);
+ sPAPRDRConnector *drc;
+ Error *local_err = NULL;
+ void *fdt = NULL;
+ int fdt_offset = 0;
+ int index = cc->core_id / smp_threads;
+ int smt = kvmppc_smt_threads();
+
+ drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
+ spapr->cores[index] = OBJECT(dev);
+
+ g_assert(drc || !mc->query_hotpluggable_cpus);
+
+ /*
+ * Setup CPU DT entries only for hotplugged CPUs. For boot time or
+ * coldplugged CPUs DT entries are setup in spapr_build_fdt().
+ */
+ if (dev->hotplugged) {
+ fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
+ }
+
+ if (drc) {
+ sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
+ if (local_err) {
+ g_free(fdt);
+ spapr->cores[index] = NULL;
+ error_propagate(errp, local_err);
+ return;
+ }
+ }
+
+ if (dev->hotplugged) {
+ /*
+ * Send hotplug notification interrupt to the guest only in case
+ * of hotplugged CPUs.
+ */
+ spapr_hotplug_req_add_by_index(drc);
+ } else {
+ /*
+ * Set the right DRC states for cold plugged CPU.
+ */
+ if (drc) {
+ sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
+ drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
+ }
+ }
+}
+
+static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
+ Error **errp)
+{
+ MachineState *machine = MACHINE(OBJECT(hotplug_dev));
+ MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
+ sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
+ int spapr_max_cores = max_cpus / smp_threads;
+ int index;
+ Error *local_err = NULL;
+ CPUCore *cc = CPU_CORE(dev);
+ char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
+ const char *type = object_get_typename(OBJECT(dev));
+
+ if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
+ error_setg(&local_err, "CPU hotplug not supported for this machine");
+ goto out;
+ }
+
+ if (strcmp(base_core_type, type)) {
+ error_setg(&local_err, "CPU core type should be %s", base_core_type);
+ goto out;
+ }
+
+ if (cc->core_id % smp_threads) {
+ error_setg(&local_err, "invalid core id %d", cc->core_id);
+ goto out;
+ }
+
+ index = cc->core_id / smp_threads;
+ if (index < 0 || index >= spapr_max_cores) {
+ error_setg(&local_err, "core id %d out of range", cc->core_id);
+ goto out;
+ }
+
+ if (spapr->cores[index]) {
+ error_setg(&local_err, "core %d already populated", cc->core_id);
+ goto out;
+ }
+
+out:
+ g_free(base_core_type);
+ error_propagate(errp, local_err);
+}
+
static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index b9e5f80..55cd045 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -109,15 +109,6 @@ char *spapr_get_cpu_core_type(const char *model)
return core_type;
}
-static void spapr_core_release(DeviceState *dev, void *opaque)
-{
- sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- CPUCore *cc = CPU_CORE(dev);
-
- spapr->cores[cc->core_id / smp_threads] = NULL;
- object_unparent(OBJECT(dev));
-}
-
static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
{
sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
@@ -140,135 +131,6 @@ static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
g_free(sc->threads);
}
-void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp)
-{
- CPUCore *cc = CPU_CORE(dev);
- int smt = kvmppc_smt_threads();
- int index = cc->core_id / smp_threads;
- sPAPRDRConnector *drc =
- spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
- sPAPRDRConnectorClass *drck;
- Error *local_err = NULL;
-
- if (index == 0) {
- error_setg(errp, "Boot CPU core may not be unplugged");
- return;
- }
-
- g_assert(drc);
-
- drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
-
- spapr_hotplug_req_remove_by_index(drc);
-}
-
-void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp)
-{
- sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
- MachineClass *mc = MACHINE_GET_CLASS(spapr);
- sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
- CPUCore *cc = CPU_CORE(dev);
- CPUState *cs = CPU(core->threads);
- sPAPRDRConnector *drc;
- Error *local_err = NULL;
- void *fdt = NULL;
- int fdt_offset = 0;
- int index = cc->core_id / smp_threads;
- int smt = kvmppc_smt_threads();
-
- drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
- spapr->cores[index] = OBJECT(dev);
-
- g_assert(drc || !mc->query_hotpluggable_cpus);
-
- /*
- * Setup CPU DT entries only for hotplugged CPUs. For boot time or
- * coldplugged CPUs DT entries are setup in spapr_build_fdt().
- */
- if (dev->hotplugged) {
- fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
- }
-
- if (drc) {
- sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
- if (local_err) {
- g_free(fdt);
- spapr->cores[index] = NULL;
- error_propagate(errp, local_err);
- return;
- }
- }
-
- if (dev->hotplugged) {
- /*
- * Send hotplug notification interrupt to the guest only in case
- * of hotplugged CPUs.
- */
- spapr_hotplug_req_add_by_index(drc);
- } else {
- /*
- * Set the right DRC states for cold plugged CPU.
- */
- if (drc) {
- sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
- drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
- }
- }
-}
-
-void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp)
-{
- MachineState *machine = MACHINE(OBJECT(hotplug_dev));
- MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
- sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
- int spapr_max_cores = max_cpus / smp_threads;
- int index;
- Error *local_err = NULL;
- CPUCore *cc = CPU_CORE(dev);
- char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
- const char *type = object_get_typename(OBJECT(dev));
-
- if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
- error_setg(&local_err, "CPU hotplug not supported for this machine");
- goto out;
- }
-
- if (strcmp(base_core_type, type)) {
- error_setg(&local_err, "CPU core type should be %s", base_core_type);
- goto out;
- }
-
- if (cc->core_id % smp_threads) {
- error_setg(&local_err, "invalid core id %d", cc->core_id);
- goto out;
- }
-
- index = cc->core_id / smp_threads;
- if (index < 0 || index >= spapr_max_cores) {
- error_setg(&local_err, "core id %d out of range", cc->core_id);
- goto out;
- }
-
- if (spapr->cores[index]) {
- error_setg(&local_err, "core %d already populated", cc->core_id);
- goto out;
- }
-
-out:
- g_free(base_core_type);
- error_propagate(errp, local_err);
-}
-
static void spapr_cpu_core_realize_child(Object *child, Error **errp)
{
Error *local_err = NULL;
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index 50292f4..3c35665 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -34,12 +34,6 @@ typedef struct sPAPRCPUCoreClass {
ObjectClass *cpu_class;
} sPAPRCPUCoreClass;
-void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp);
char *spapr_get_cpu_core_type(const char *model);
-void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp);
-void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp);
void spapr_cpu_core_class_init(ObjectClass *oc, void *data);
#endif
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 04/43] ppc: implement xsrqpi[x] instruction David Gibson
` (41 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
spapr_core_unplug() were essentially spapr_core_unplug_request()
handler that requested CPU removal and registered callback
which did actual cpu core removali but it was called from
spapr_machine_device_unplug() which is intended for actual object
removal. Commit (cf632463 spapr: Memory hot-unplug support)
sort of fixed it introducing spapr_machine_device_unplug_request()
and calling spapr_core_unplug() but it hasn't renamed callback and
by mistake calls it from spapr_machine_device_unplug().
However spapr_machine_device_unplug() isn't ever called for
cpu core since spapr_core_release() doesn't follow expected
hotunplug call flow which is:
1: device_del() ->
hotplug_handler_unplug_request() ->
set destroy_cb()
2: destroy_cb() ->
hotplug_handler_unplug() ->
object_unparent // actual device removal
Fix it by renaming spapr_core_unplug() to spapr_core_unplug_request()
which is called from spapr_machine_device_unplug_request() and
making spapr_core_release() call hotplug_handler_unplug() which
will call spapr_machine_device_unplug() -> spapr_core_unplug()
to remove cpu core.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reveiwed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 8c2efd8..37cb338 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2488,7 +2488,8 @@ void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
return fdt;
}
-static void spapr_core_release(DeviceState *dev, void *opaque)
+static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
+ Error **errp)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
CPUCore *cc = CPU_CORE(dev);
@@ -2497,8 +2498,17 @@ static void spapr_core_release(DeviceState *dev, void *opaque)
object_unparent(OBJECT(dev));
}
-static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
- Error **errp)
+static void spapr_core_release(DeviceState *dev, void *opaque)
+{
+ HotplugHandler *hotplug_ctrl;
+
+ hotplug_ctrl = qdev_get_hotplug_handler(dev);
+ hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
+}
+
+static
+void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
+ Error **errp)
{
CPUCore *cc = CPU_CORE(dev);
int smt = kvmppc_smt_threads();
@@ -2719,7 +2729,7 @@ static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
error_setg(errp, "CPU hot unplug not supported on this machine");
return;
}
- spapr_core_unplug(hotplug_dev, dev, errp);
+ spapr_core_unplug_request(hotplug_dev, dev, errp);
}
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 04/43] ppc: implement xsrqpi[x] instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (2 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 05/43] ppc: implement xsrqpxp instruction David Gibson
` (40 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer
[with Inexact].
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 59 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/internal.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 12 ++++++++
5 files changed, 75 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9f5cafd..1ca384c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3277,3 +3277,62 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)
env->fpscr |= cc << FPSCR_FPRF;
env->crf[BF(opcode)] = cc;
}
+
+void helper_xsrqpi(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xb;
+ ppc_vsr_t xt;
+ uint8_t r = Rrm(opcode);
+ uint8_t ex = Rc(opcode);
+ uint8_t rmc = RMC(opcode);
+ uint8_t rmode = 0;
+ float_status tstat;
+
+ getVSR(rB(opcode) + 32, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+ helper_reset_fpstatus(env);
+
+ if (r == 0 && rmc == 0) {
+ rmode = float_round_ties_away;
+ } else if (r == 0 && rmc == 0x3) {
+ rmode = fpscr_rn;
+ } else if (r == 1) {
+ switch (rmc) {
+ case 0:
+ rmode = float_round_nearest_even;
+ break;
+ case 1:
+ rmode = float_round_to_zero;
+ break;
+ case 2:
+ rmode = float_round_up;
+ break;
+ case 3:
+ rmode = float_round_down;
+ break;
+ default:
+ abort();
+ }
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ set_float_rounding_mode(rmode, &tstat);
+ xt.f128 = float128_round_to_int(xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
+ xt.f128 = float128_snan_to_qnan(xt.f128);
+ }
+ }
+
+ if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
+ env->fp_status.float_exception_flags &= ~float_flag_inexact;
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+ float_check_status(env);
+ putVSR(rD(opcode) + 32, &xt, env);
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 85af9df..6a53ae0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -459,6 +459,7 @@ DEF_HELPER_2(xsrdpic, void, env, i32)
DEF_HELPER_2(xsrdpim, void, env, i32)
DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
+DEF_HELPER_2(xsrqpi, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 5a2fd68..5b5b180 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -186,6 +186,7 @@ EXTRACT_HELPER(DCM, 10, 6)
/* DFP Z23-form */
EXTRACT_HELPER(RMC, 9, 2)
+EXTRACT_HELPER(Rrm, 16, 1)
EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index a44c003..9868f01 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -833,6 +833,8 @@ GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
+
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 7dc9f6f..b095508 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -103,6 +103,18 @@ GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \
GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300)
+#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
+
+GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
+
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 05/43] ppc: implement xsrqpxp instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (3 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 04/43] ppc: implement xsrqpi[x] instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 06/43] ppc: implement xssqrtqp instruction David Gibson
` (39 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 56 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 59 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 1ca384c..b422442 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3336,3 +3336,59 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode)
float_check_status(env);
putVSR(rD(opcode) + 32, &xt, env);
}
+
+void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xb;
+ ppc_vsr_t xt;
+ uint8_t r = Rrm(opcode);
+ uint8_t rmc = RMC(opcode);
+ uint8_t rmode = 0;
+ floatx80 round_res;
+ float_status tstat;
+
+ getVSR(rB(opcode) + 32, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+ helper_reset_fpstatus(env);
+
+ if (r == 0 && rmc == 0) {
+ rmode = float_round_ties_away;
+ } else if (r == 0 && rmc == 0x3) {
+ rmode = fpscr_rn;
+ } else if (r == 1) {
+ switch (rmc) {
+ case 0:
+ rmode = float_round_nearest_even;
+ break;
+ case 1:
+ rmode = float_round_to_zero;
+ break;
+ case 2:
+ rmode = float_round_up;
+ break;
+ case 3:
+ rmode = float_round_down;
+ break;
+ default:
+ abort();
+ }
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ set_float_rounding_mode(rmode, &tstat);
+ round_res = float128_to_floatx80(xb.f128, &tstat);
+ xt.f128 = floatx80_to_float128(round_res, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
+ xt.f128 = float128_snan_to_qnan(xt.f128);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6a53ae0..9ce2e58 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -460,6 +460,7 @@ DEF_HELPER_2(xsrdpim, void, env, i32)
DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsrqpi, void, env, i32)
+DEF_HELPER_2(xsrqpxp, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 9868f01..91be201 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -834,6 +834,7 @@ GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index b095508..e58740b 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -114,6 +114,7 @@ GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
+GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 06/43] ppc: implement xssqrtqp instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (4 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 05/43] ppc: implement xsrqpxp instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 07/43] ppc: implement xssubqp instruction David Gibson
` (38 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
xssqrtqp: VSX Scalar Square Root Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 41 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index b422442..5c34438 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3392,3 +3392,41 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode)
putVSR(rD(opcode) + 32, &xt, env);
float_check_status(env);
}
+
+void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xb;
+ ppc_vsr_t xt;
+ float_status tstat;
+
+ getVSR(rB(opcode) + 32, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+ helper_reset_fpstatus(env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xsadddpo after round-to-odd is implemented */
+ abort();
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_sqrt(xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ xt.f128 = float128_snan_to_qnan(xb.f128);
+ } else if (float128_is_quiet_nan(xb.f128, &tstat)) {
+ xt.f128 = xb.f128;
+ } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
+ set_snan_bit_is_one(0, &env->fp_status);
+ xt.f128 = float128_default_nan(&env->fp_status);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9ce2e58..fbf80a7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -461,6 +461,7 @@ DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsrqpi, void, env, i32)
DEF_HELPER_2(xsrqpxp, void, env, i32)
+DEF_HELPER_2(xssqrtqp, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 91be201..bbd7d1a 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -835,6 +835,7 @@ GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index e58740b..bac3db2 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,6 +115,7 @@ GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
+GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x00000001),
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 07/43] ppc: implement xssubqp instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (5 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 06/43] ppc: implement xssqrtqp instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 08/43] hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings David Gibson
` (37 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
xssubqp: VSX Scalar Subtract Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 34 ++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 37 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 5c34438..48973a9 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3430,3 +3430,37 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
putVSR(rD(opcode) + 32, &xt, env);
float_check_status(env);
}
+
+void helper_xssubqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xa, xb;
+ float_status tstat;
+
+ getVSR(rA(opcode) + 32, &xa, env);
+ getVSR(rB(opcode) + 32, &xb, env);
+ getVSR(rD(opcode) + 32, &xt, env);
+ helper_reset_fpstatus(env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xssubqp after round-to-odd is implemented */
+ abort();
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_sub(xa.f128, xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
+ } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
+ float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fbf80a7..3956fd1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -462,6 +462,7 @@ DEF_HELPER_2(xsrdpiz, void, env, i32)
DEF_HELPER_2(xsrqpi, void, env, i32)
DEF_HELPER_2(xsrqpxp, void, env, i32)
DEF_HELPER_2(xssqrtqp, void, env, i32)
+DEF_HELPER_2(xssubqp, void, env, i32)
DEF_HELPER_2(xsaddsp, void, env, i32)
DEF_HELPER_2(xssubsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index bbd7d1a..a062203 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -836,6 +836,7 @@ GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsrqpi, 0x05, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsrqpxp, 0x05, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssqrtqp, 0x04, 0x19, 0x1B, PPC2_ISA300)
+GEN_VSX_HELPER_2(xssubqp, 0x04, 0x10, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index bac3db2..2202c0f 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -116,6 +116,7 @@ GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x00000001),
+GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0),
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 08/43] hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (6 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 07/43] ppc: implement xssubqp instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions David Gibson
` (36 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Thomas Huth <thuth@redhat.com>
error_report() already puts a prefix with the program name in front
of the error strings, so the "qemu:" prefix is not necessary here
anymore.
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4fab5c0..09f0d22 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -381,7 +381,7 @@ static void ppc_powernv_init(MachineState *machine)
fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
if (fw_size < 0) {
- error_report("qemu: could not load OPAL '%s'", fw_filename);
+ error_report("Could not load OPAL '%s'", fw_filename);
exit(1);
}
g_free(fw_filename);
@@ -393,7 +393,7 @@ static void ppc_powernv_init(MachineState *machine)
kernel_size = load_image_targphys(machine->kernel_filename,
KERNEL_LOAD_ADDR, 0x2000000);
if (kernel_size < 0) {
- error_report("qemu: could not load kernel'%s'",
+ error_report("Could not load kernel '%s'",
machine->kernel_filename);
exit(1);
}
@@ -405,7 +405,7 @@ static void ppc_powernv_init(MachineState *machine)
pnv->initrd_size = load_image_targphys(machine->initrd_filename,
pnv->initrd_base, 0x10000000); /* 128MB max */
if (pnv->initrd_size < 0) {
- error_report("qemu: could not load initial ram disk '%s'",
+ error_report("Could not load initial ram disk '%s'",
machine->initrd_filename);
exit(1);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (7 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 08/43] hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions David Gibson
` (35 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision
xsmincdp: VSX Scalar Minimum Type-C Double-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 44 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 48973a9..9d2688e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2679,6 +2679,44 @@ VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
+#define VSX_MAX_MINC(name, max) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ bool vxsnan_flag = false, vex_flag = false; \
+ \
+ getVSR(rA(opcode) + 32, &xa, env); \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
+ float64_is_any_nan(xb.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } else if ((max && \
+ !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
+ (!max && \
+ float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else { \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } \
+ \
+ vex_flag = fpscr_ve & vxsnan_flag; \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (!vex_flag) { \
+ putVSR(rD(opcode) + 32, &xt, env); \
+ } \
+} \
+
+VSX_MAX_MINC(xsmaxcdp, 1);
+VSX_MAX_MINC(xsmincdp, 0);
+
/* VSX_CMP - VSX floating point compare
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3956fd1..fe3267e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -431,6 +431,8 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xsmaxcdp, void, env, i32)
+DEF_HELPER_2(xsmincdp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index a062203..3251dca 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -808,6 +808,8 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 2202c0f..16a135f 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -200,6 +200,8 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
+GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
+GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (8 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt() David Gibson
` (34 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision
xsminjdp: VSX Scalar Minimum Type-J Double-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 61 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9d2688e..1b6cd3b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2717,6 +2717,61 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
VSX_MAX_MINC(xsmaxcdp, 1);
VSX_MAX_MINC(xsmincdp, 0);
+#define VSX_MAX_MINJ(name, max) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ bool vxsnan_flag = false, vex_flag = false; \
+ \
+ getVSR(rA(opcode) + 32, &xa, env); \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ if (unlikely(float64_is_any_nan(xa.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else if (unlikely(float64_is_any_nan(xb.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } else if (float64_is_zero(xa.VsrD(0)) && float64_is_zero(xb.VsrD(0))) { \
+ if (max) { \
+ if (!float64_is_neg(xa.VsrD(0)) || !float64_is_neg(xb.VsrD(0))) { \
+ xt.VsrD(0) = 0ULL; \
+ } else { \
+ xt.VsrD(0) = 0x8000000000000000ULL; \
+ } \
+ } else { \
+ if (float64_is_neg(xa.VsrD(0)) || float64_is_neg(xb.VsrD(0))) { \
+ xt.VsrD(0) = 0x8000000000000000ULL; \
+ } else { \
+ xt.VsrD(0) = 0ULL; \
+ } \
+ } \
+ } else if ((max && \
+ !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
+ (!max && \
+ float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else { \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } \
+ \
+ vex_flag = fpscr_ve & vxsnan_flag; \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (!vex_flag) { \
+ putVSR(rD(opcode) + 32, &xt, env); \
+ } \
+} \
+
+VSX_MAX_MINJ(xsmaxjdp, 1);
+VSX_MAX_MINJ(xsminjdp, 0);
+
/* VSX_CMP - VSX floating point compare
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fe3267e..cc81709 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -433,6 +433,8 @@ DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xsmaxcdp, void, env, i32)
DEF_HELPER_2(xsmincdp, void, env, i32)
+DEF_HELPER_2(xsmaxjdp, void, env, i32)
+DEF_HELPER_2(xsminjdp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 3251dca..8de8cd0 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -810,6 +810,8 @@ GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 16a135f..c1b71ad 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -202,6 +202,8 @@ GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
+GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
+GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt()
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (9 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 12/43] target-ppc: implement load atomic instruction David Gibson
` (33 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Sam Bobroff, David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
The last byte of the option vector was missing due to an off-by-one
error. Without this fix, client architecture support negotiation will
fail because the last byte of option vector 5, which contains the MMU
support, will be missed.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_ovec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c
index 3eb1d59..0bcf311 100644
--- a/hw/ppc/spapr_ovec.c
+++ b/hw/ppc/spapr_ovec.c
@@ -250,5 +250,5 @@ int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
}
}
- return fdt_setprop(fdt, fdt_offset, name, vec, vec_len);
+ return fdt_setprop(fdt, fdt_offset, name, vec, vec_len + 1);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 12/43] target-ppc: implement load atomic instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (10 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt() David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 13/43] target-ppc: implement store " David Gibson
` (32 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Balamuruhan S, Harish S, Athira Rajeev, Nikunj A Dadhania,
David Gibson
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
lwat: Load Word Atomic
ldat: Load Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ combine both lwat/ldat implementation using macro ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/internal.h | 2 ++
target/ppc/translate.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 5b5b180..1f441c6 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -133,6 +133,8 @@ EXTRACT_HELPER(UIMM4, 16, 4);
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
+/* lwat/stwat/ldat/lwat */
+EXTRACT_HELPER(FC, 11, 5);
/* Vector shift count */
EXTRACT_HELPER(VSH, 6, 4);
/* Mask start */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b48abae..ea2ec44 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2976,6 +2976,63 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, DEF_MEMOP(MO_UL))
+#define LD_ATOMIC(name, memop, tp, op, eop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* Fetch and add */ \
+ tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* Fetch and xor */ \
+ tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Fetch and or */ \
+ tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* Fetch and 'and' */ \
+ tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 8: /* Swap */ \
+ tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 4: /* Fetch and max unsigned */ \
+ case 5: /* Fetch and max signed */ \
+ case 6: /* Fetch and min unsigned */ \
+ case 7: /* Fetch and min signed */ \
+ case 16: /* compare and swap not equal */ \
+ case 24: /* Fetch and increment bounded */ \
+ case 25: /* Fetch and increment equal */ \
+ case 28: /* Fetch and decrement bounded */ \
+ gen_invalid(ctx); \
+ break; \
+ default: \
+ /* invoke data storage error handler */ \
+ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
+ } \
+ tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
+#if defined(TARGET_PPC64)
+LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6230,10 +6287,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
+GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
+GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 13/43] target-ppc: implement store atomic instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (11 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 12/43] target-ppc: implement load atomic instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 14/43] target-ppc: generate exception for copy/paste David Gibson
` (31 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Balamuruhan S, Harish S, Athira Rajeev, Nikunj A Dadhania,
David Gibson
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
stwat: Store Word Atomic
stdat: Store Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ implement stdat, use macro and combine both implementation ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ea2ec44..255735a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3033,6 +3033,56 @@ LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
#endif
+#define ST_ATOMIC(name, memop, tp, op) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* add and Store */ \
+ tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* xor and Store */ \
+ tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Or and Store */ \
+ tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* 'and' and Store */ \
+ tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 4: /* Store max unsigned */ \
+ case 5: /* Store max signed */ \
+ case 6: /* Store min unsigned */ \
+ case 7: /* Store min signed */ \
+ case 24: /* Store twin */ \
+ gen_invalid(ctx); \
+ break; \
+ default: \
+ /* invoke data storage error handler */ \
+ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
+ } \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
+#if defined(TARGET_PPC64)
+ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6288,11 +6338,13 @@ GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 14/43] target-ppc: generate exception for copy/paste
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (12 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 13/43] target-ppc: implement store " David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 15/43] target-ppc: add slbieg instruction David Gibson
` (30 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 255735a..80f9f15 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6132,6 +6132,19 @@ static inline void gen_cp_abort(DisasContext *ctx)
// Do Nothing
}
+#define GEN_CP_PASTE_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ /* Generate invalid exception until \
+ * we have an implementation of the copy \
+ * paste facility \
+ */ \
+ gen_invalid(ctx); \
+}
+
+GEN_CP_PASTE_NOOP(copy)
+GEN_CP_PASTE_NOOP(paste)
+
static void gen_tcheck(DisasContext *ctx)
{
if (unlikely(!ctx->tm_enabled)) {
@@ -6281,7 +6294,9 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 15/43] target-ppc: add slbieg instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (13 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 14/43] target-ppc: generate exception for copy/paste David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 16/43] target-ppc: add slbsync implementation David Gibson
` (29 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
slbieg: SLB Invalidate Entry Global
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/mmu-hash64.c | 16 ++++++++++++++--
target/ppc/translate.c | 14 ++++++++++++++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index cc81709..007a837 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -669,6 +669,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_1(slbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index bb78fb5..2791f29 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -115,7 +115,8 @@ void helper_slbia(CPUPPCState *env)
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+static void __helper_slbie(CPUPPCState *env, target_ulong addr,
+ target_ulong global)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc_slb_t *slb;
@@ -132,10 +133,21 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs
*/
- env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+ env->tlb_need_flush |=
+ (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH);
}
}
+void helper_slbie(CPUPPCState *env, target_ulong addr)
+{
+ __helper_slbie(env, addr, false);
+}
+
+void helper_slbieg(CPUPPCState *env, target_ulong addr)
+{
+ __helper_slbie(env, addr, true);
+}
+
int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
target_ulong esid, target_ulong vsid)
{
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 80f9f15..b0f3c3b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4484,6 +4484,19 @@ static void gen_slbie(DisasContext *ctx)
gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
+
+/* slbieg */
+static void gen_slbieg(DisasContext *ctx)
+{
+#if defined(CONFIG_USER_ONLY)
+ GEN_PRIV;
+#else
+ CHK_SV;
+
+ gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
+#endif /* defined(CONFIG_USER_ONLY) */
+}
+
#endif /* defined(TARGET_PPC64) */
/*** External control ***/
@@ -6439,6 +6452,7 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
+GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 16/43] target-ppc: add slbsync implementation
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (14 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 15/43] target-ppc: add slbieg instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction David Gibson
` (28 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
slbsync: SLB Synchoronize
The instruction provides an ordering function for the effects of all
slbieg instructions executed by the thread executing the slbsync
instruction.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b0f3c3b..b1a6aee 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4497,6 +4497,17 @@ static void gen_slbieg(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
+/* slbsync */
+static void gen_slbsync(DisasContext *ctx)
+{
+#if defined(CONFIG_USER_ONLY)
+ GEN_PRIV;
+#else
+ CHK_SV;
+ gen_check_tlb_flush(ctx, true);
+#endif /* defined(CONFIG_USER_ONLY) */
+}
+
#endif /* defined(TARGET_PPC64) */
/*** External control ***/
@@ -6453,6 +6464,7 @@ GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (15 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 16/43] target-ppc: add slbsync implementation David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 18/43] target-ppc, tcg: fix usermode segfault with pthread_create() David Gibson
` (27 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Use the available wait instruction implementation.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b1a6aee..3ba2616 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6391,6 +6391,7 @@ GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
#endif
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
+GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 18/43] target-ppc, tcg: fix usermode segfault with pthread_create()
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (16 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 19/43] mac99: replace debug printf with trace points David Gibson
` (26 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Sam Bobroff, David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
Programs run under qemu-ppc64 on an x86_64 host currently segfault
if they use pthread_create() due to the adjustment made to the NIP in
commit bd6fefe71cec5a0c7d2be4ac96307f25db56abf9.
This patch changes cpu_loop() to set the NIP back to the
pre-incremented value before calling do_syscall(), which causes the
correct address to be used for the new thread and corrects the fault.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
linux-user/main.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 4fd49ce..9645122 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1712,10 +1712,12 @@ void cpu_loop(CPUPPCState *env)
* in syscalls.
*/
env->crf[0] &= ~0x1;
+ env->nip += 4;
ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
env->gpr[5], env->gpr[6], env->gpr[7],
env->gpr[8], 0, 0);
if (ret == -TARGET_ERESTARTSYS) {
+ env->nip -= 4;
break;
}
if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
@@ -1723,7 +1725,6 @@ void cpu_loop(CPUPPCState *env)
Avoid corrupting register state. */
break;
}
- env->nip += 4;
if (ret > (target_ulong)(-515)) {
env->crf[0] |= 0x1;
ret = -ret;
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 19/43] mac99: replace debug printf with trace points
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (17 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 18/43] target-ppc, tcg: fix usermode segfault with pthread_create() David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 20/43] ppc4xx: " David Gibson
` (25 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/mac_newworld.c | 15 +++------------
hw/ppc/trace-events | 4 ++++
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 716aea6..68aaedc 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -72,6 +72,7 @@
#include "exec/address-spaces.h"
#include "hw/sysbus.h"
#include "qemu/cutils.h"
+#include "trace.h"
#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510
@@ -79,21 +80,11 @@
#define CLOCKFREQ (266UL * 1000UL * 1000UL)
#define BUSFREQ (100UL * 1000UL * 1000UL)
-/* debug UniNorth */
-//#define DEBUG_UNIN
-
-#ifdef DEBUG_UNIN
-#define UNIN_DPRINTF(fmt, ...) \
- do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define UNIN_DPRINTF(fmt, ...)
-#endif
-
/* UniN device */
static void unin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
+ trace_mac99_uninorth_write(addr, value);
if (addr == 0x0) {
*(int*)opaque = value;
}
@@ -109,7 +100,7 @@ static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
value = *(int*)opaque;
}
- UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
+ trace_mac99_uninorth_read(addr, value);
return value;
}
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index f46995c..6122a12 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -85,3 +85,7 @@ rs6000mc_presence_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+
+# hw/ppc/mac_newworld.c
+mac99_uninorth_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
+mac99_uninorth_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 20/43] ppc4xx: replace debug printf with trace points
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (18 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 19/43] mac99: replace debug printf with trace points David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 21/43] spapr: " David Gibson
` (24 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc4xx_pci.c | 13 +++----------
hw/ppc/trace-events | 4 ++++
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c
index 683218e..dc19682 100644
--- a/hw/ppc/ppc4xx_pci.c
+++ b/hw/ppc/ppc4xx_pci.c
@@ -26,13 +26,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"
-
-#undef DEBUG
-#ifdef DEBUG
-#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...)
-#endif /* DEBUG */
+#include "trace.h"
struct PCIMasterMap {
uint32_t la;
@@ -249,8 +243,7 @@ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
int slot = pci_dev->devfn >> 3;
- DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
- pci_dev->devfn, irq_num, slot);
+ trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
return slot - 1;
}
@@ -259,7 +252,7 @@ static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
qemu_irq *pci_irqs = opaque;
- DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
+ trace_ppc4xx_pci_set_irq(irq_num);
if (irq_num < 0) {
fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
return;
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 6122a12..f04bb1d 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -89,3 +89,7 @@ rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
# hw/ppc/mac_newworld.c
mac99_uninorth_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
mac99_uninorth_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
+
+# hw/ppc/ppc4xx_pci.c
+ppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot) "devfn %x irq %d -> %d"
+ppc4xx_pci_set_irq(int irq_num) "PCI irq %d"
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 21/43] spapr: replace debug printf with trace points
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (19 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 20/43] ppc4xx: " David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode David Gibson
` (23 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_ovec.c | 17 +++--------------
hw/ppc/trace-events | 4 ++++
2 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c
index 0bcf311..41df4c3 100644
--- a/hw/ppc/spapr_ovec.c
+++ b/hw/ppc/spapr_ovec.c
@@ -16,18 +16,9 @@
#include "qemu/bitmap.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
+#include "trace.h"
#include <libfdt.h>
-/* #define DEBUG_SPAPR_OVEC */
-
-#ifdef DEBUG_SPAPR_OVEC
-#define DPRINTFN(fmt, ...) \
- do { fprintf(stderr, fmt "\n", ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTFN(fmt, ...) \
- do { } while (0)
-#endif
-
#define OV_MAXBYTES 256 /* not including length byte */
#define OV_MAXBITS (OV_MAXBYTES * BITS_PER_BYTE)
@@ -210,8 +201,7 @@ sPAPROptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector)
for (i = 0; i < vector_len; i++) {
uint8_t entry = ldub_phys(&address_space_memory, addr + i);
if (entry) {
- DPRINTFN("read guest vector %2d, byte %3d / %3d: 0x%.2x",
- vector, i + 1, vector_len, entry);
+ trace_spapr_ovec_parse_vector(vector, i + 1, vector_len, entry);
guest_byte_to_bitmap(entry, ov->bitmap, i * BITS_PER_BYTE);
}
}
@@ -245,8 +235,7 @@ int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
for (i = 1; i < vec_len + 1; i++) {
vec[i] = guest_byte_from_bitmap(ov->bitmap, (i - 1) * BITS_PER_BYTE);
if (vec[i]) {
- DPRINTFN("encoding guest vector byte %3d / %3d: 0x%.2x",
- i, vec_len, vec[i]);
+ trace_spapr_ovec_populate_dt(i, vec_len, vec[i]);
}
}
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index f04bb1d..43d265f 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -56,6 +56,10 @@ spapr_drc_realize_child(uint32_t index, char *childname) "drc: 0x%"PRIx32", chil
spapr_drc_realize_complete(uint32_t index) "drc: 0x%"PRIx32
spapr_drc_unrealize(uint32_t index) "drc: 0x%"PRIx32
+# hw/ppc/spapr_ovec.c
+spapr_ovec_parse_vector(int vector, int byte, uint16_t vec_len, uint8_t entry) "read guest vector %2d, byte %3d / %3d: 0x%.2x"
+spapr_ovec_populate_dt(int byte, uint16_t vec_len, uint8_t entry) "encoding guest vector byte %3d / %3d: 0x%.2x"
+
# hw/ppc/spapr_rtas.c
spapr_rtas_set_indicator_invalid(uint32_t index) "sensor index: 0x%"PRIx32
spapr_rtas_set_indicator_not_supported(uint32_t index, uint32_t type) "sensor index: 0x%"PRIx32", type: %"PRIu32
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (20 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 21/43] spapr: " David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero() David Gibson
` (22 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
fpu/softfloat.c | 21 ++++++++++++++++++++-
include/fpu/softfloat.h | 2 ++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c295f31..5ccba76 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
case float_round_down:
roundIncrement = zSign ? 0x3ff : 0;
break;
+ case float_round_to_odd:
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ break;
default:
abort();
}
@@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
|| ( ( zExp == 0x7FD )
&& ( (int64_t) ( zSig + roundIncrement ) < 0 ) )
) {
+ bool overflow_to_inf = roundingMode != float_round_to_odd &&
+ roundIncrement != 0;
float_raise(float_flag_overflow | float_flag_inexact, status);
- return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 ));
+ return packFloat64(zSign, 0x7FF, -(!overflow_to_inf));
}
if ( zExp < 0 ) {
if (status->flush_to_zero) {
@@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zExp, uint64_t zSig,
if (isTiny && roundBits) {
float_raise(float_flag_underflow, status);
}
+ if (roundingMode == float_round_to_odd) {
+ /*
+ * For round-to-odd case, the roundIncrement depends on
+ * zSig which just changed.
+ */
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ }
}
}
if (roundBits) {
@@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}
@@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
if ( ( roundingMode == float_round_to_zero )
|| ( zSign && ( roundingMode == float_round_up ) )
|| ( ! zSign && ( roundingMode == float_round_down ) )
+ || (roundingMode == float_round_to_odd)
) {
return
packFloat128(
@@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 842ec6b..8a39028 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -180,6 +180,8 @@ enum {
float_round_up = 2,
float_round_to_zero = 3,
float_round_ties_away = 4,
+ /* Not an IEEE rounding mode: round to the closest odd mantissa value */
+ float_round_to_odd = 5,
};
/*----------------------------------------------------------------------------
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero()
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (21 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero() David Gibson
` (21 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Implement float128_to_uint64() and use that to implement
float128_to_uint64_round_to_zero()
This is required by xscvqpudz instruction of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
fpu/softfloat.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 2 ++
2 files changed, 61 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 5ccba76..47e4646 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6128,6 +6128,65 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *status)
}
/*----------------------------------------------------------------------------
+| Returns the result of converting the quadruple-precision floating-point value
+| `a' to the 64-bit unsigned integer format. The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode. If `a' is a NaN, the largest
+| positive integer is returned. If the conversion overflows, the
+| largest unsigned integer is returned. If 'a' is negative, the value is
+| rounded and zero is returned; negative values that do not round to zero
+| will raise the inexact exception.
+*----------------------------------------------------------------------------*/
+
+uint64_t float128_to_uint64(float128 a, float_status *status)
+{
+ flag aSign;
+ int aExp;
+ int shiftCount;
+ uint64_t aSig0, aSig1;
+
+ aSig0 = extractFloat128Frac0(a);
+ aSig1 = extractFloat128Frac1(a);
+ aExp = extractFloat128Exp(a);
+ aSign = extractFloat128Sign(a);
+ if (aSign && (aExp > 0x3FFE)) {
+ float_raise(float_flag_invalid, status);
+ if (float128_is_any_nan(a)) {
+ return LIT64(0xFFFFFFFFFFFFFFFF);
+ } else {
+ return 0;
+ }
+ }
+ if (aExp) {
+ aSig0 |= LIT64(0x0001000000000000);
+ }
+ shiftCount = 0x402F - aExp;
+ if (shiftCount <= 0) {
+ if (0x403E < aExp) {
+ float_raise(float_flag_invalid, status);
+ return LIT64(0xFFFFFFFFFFFFFFFF);
+ }
+ shortShift128Left(aSig0, aSig1, -shiftCount, &aSig0, &aSig1);
+ } else {
+ shift64ExtraRightJamming(aSig0, aSig1, shiftCount, &aSig0, &aSig1);
+ }
+ return roundAndPackUint64(aSign, aSig0, aSig1, status);
+}
+
+uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *status)
+{
+ uint64_t v;
+ signed char current_rounding_mode = status->float_rounding_mode;
+
+ set_float_rounding_mode(float_round_to_zero, status);
+ v = float128_to_uint64(a, status);
+ set_float_rounding_mode(current_rounding_mode, status);
+
+ return v;
+}
+
+/*----------------------------------------------------------------------------
| Returns the result of converting the quadruple-precision floating-point
| value `a' to the single-precision floating-point format. The conversion
| is performed according to the IEC/IEEE Standard for Binary Floating-Point
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 8a39028..a09ad0e 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -714,6 +714,8 @@ int32_t float128_to_int32(float128, float_status *status);
int32_t float128_to_int32_round_to_zero(float128, float_status *status);
int64_t float128_to_int64(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
+uint64_t float128_to_uint64(float128, float_status *status);
+uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
float64 float128_to_float64(float128, float_status *status);
floatx80 float128_to_floatx80(float128, float_status *status);
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero()
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (22 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero() David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 25/43] target-ppc: Implement round to odd variants of quad FP instructions David Gibson
` (20 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction
of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
fpu/softfloat.c | 28 ++++++++++++++++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 47e4646..485a006 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6188,6 +6188,34 @@ uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *status)
/*----------------------------------------------------------------------------
| Returns the result of converting the quadruple-precision floating-point
+| value `a' to the 32-bit unsigned integer format. The conversion
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic except that the conversion is always rounded toward zero.
+| If `a' is a NaN, the largest positive integer is returned. Otherwise,
+| if the conversion overflows, the largest unsigned integer is returned.
+| If 'a' is negative, the value is rounded and zero is returned; negative
+| values that do not round to zero will raise the inexact exception.
+*----------------------------------------------------------------------------*/
+
+uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *status)
+{
+ uint64_t v;
+ uint32_t res;
+ int old_exc_flags = get_float_exception_flags(status);
+
+ v = float128_to_uint64_round_to_zero(a, status);
+ if (v > 0xffffffff) {
+ res = 0xffffffff;
+ } else {
+ return v;
+ }
+ set_float_exception_flags(old_exc_flags, status);
+ float_raise(float_flag_invalid, status);
+ return res;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the quadruple-precision floating-point
| value `a' to the single-precision floating-point format. The conversion
| is performed according to the IEC/IEEE Standard for Binary Floating-Point
| Arithmetic.
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index a09ad0e..f1288ef 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -716,6 +716,7 @@ int64_t float128_to_int64(float128, float_status *status);
int64_t float128_to_int64_round_to_zero(float128, float_status *status);
uint64_t float128_to_uint64(float128, float_status *status);
uint64_t float128_to_uint64_round_to_zero(float128, float_status *status);
+uint32_t float128_to_uint32_round_to_zero(float128, float_status *status);
float32 float128_to_float32(float128, float_status *status);
float64 float128_to_float64(float128, float_status *status);
floatx80 float128_to_floatx80(float128, float_status *status);
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 25/43] target-ppc: Implement round to odd variants of quad FP instructions
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (23 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero() David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions David Gibson
` (19 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, Jose Ricardo Ziviani, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd
xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd
xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd
xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format using round to Odd
xssqrtqpo: VSX Scalar Square Root Quad-Precision using round to Odd
xssubqpo: VSX Scalar Subtract Quad-Precision using round to Odd
In addition, fix the invalid bitmask in the instruction encoding
of xssqrtqp[o].
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
CC: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 42 ++++++++++++++++++--------------------
target/ppc/translate/vsx-ops.inc.c | 2 +-
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 1b6cd3b..96f9801 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1850,12 +1850,11 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
getVSR(rD(opcode) + 32, &xt, env);
helper_reset_fpstatus(env);
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xsadddpo after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_add(xa.f128, xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
@@ -1930,19 +1929,18 @@ VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
void helper_xsmulqp(CPUPPCState *env, uint32_t opcode)
{
ppc_vsr_t xt, xa, xb;
+ float_status tstat;
getVSR(rA(opcode) + 32, &xa, env);
getVSR(rB(opcode) + 32, &xb, env);
getVSR(rD(opcode) + 32, &xt, env);
+ helper_reset_fpstatus(env);
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xsmulpo after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- helper_reset_fpstatus(env);
-
- float_status tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_mul(xa.f128, xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
@@ -2019,18 +2017,18 @@ VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
{
ppc_vsr_t xt, xa, xb;
+ float_status tstat;
getVSR(rA(opcode) + 32, &xa, env);
getVSR(rB(opcode) + 32, &xb, env);
getVSR(rD(opcode) + 32, &xt, env);
+ helper_reset_fpstatus(env);
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xsdivqpo after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- helper_reset_fpstatus(env);
- float_status tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_div(xa.f128, xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
@@ -2954,18 +2952,20 @@ VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
{
ppc_vsr_t xt, xb;
+ float_status tstat;
getVSR(rB(opcode) + 32, &xb, env);
memset(&xt, 0, sizeof(xt));
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xscvqpdpo after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- xt.VsrD(0) = float128_to_float64(xb.f128, &env->fp_status);
+ xt.VsrD(0) = float128_to_float64(xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(float128_is_signaling_nan(xb.f128,
- &env->fp_status))) {
+ &tstat))) {
float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0));
}
@@ -3496,12 +3496,11 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
memset(&xt, 0, sizeof(xt));
helper_reset_fpstatus(env);
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xsadddpo after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_sqrt(xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
@@ -3534,12 +3533,11 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode)
getVSR(rD(opcode) + 32, &xt, env);
helper_reset_fpstatus(env);
+ tstat = env->fp_status;
if (unlikely(Rc(opcode) != 0)) {
- /* TODO: Support xssubqp after round-to-odd is implemented */
- abort();
+ tstat.float_rounding_mode = float_round_to_odd;
}
- tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
xt.f128 = float128_sub(xa.f128, xb.f128, &tstat);
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index c1b71ad..e20ca32 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,7 +115,7 @@ GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
GEN_VSX_Z23FORM_300(xsrqpi, 0x05, 0x0, 0x0, 0x0),
GEN_VSX_Z23FORM_300(xsrqpxp, 0x05, 0x1, 0x0, 0x0),
-GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x00000001),
+GEN_VSX_XFORM_300_EO(xssqrtqp, 0x04, 0x19, 0x1B, 0x0),
GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0),
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (24 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 25/43] target-ppc: Implement round to odd variants of quad FP instructions David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define David Gibson
` (18 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Doubleword format
xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Word format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 96f9801..58aee64 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3086,6 +3086,8 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
0xffffffff80000000ULL)
+VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
+VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
* op - instruction mnemonic
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 007a837..6d77661 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -442,6 +442,8 @@ DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvqpdp, void, env, i32)
DEF_HELPER_2(xscvqpsdz, void, env, i32)
DEF_HELPER_2(xscvqpswz, void, env, i32)
+DEF_HELPER_2(xscvqpudz, void, env, i32)
+DEF_HELPER_2(xscvqpuwz, void, env, i32)
DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvsdqp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 8de8cd0..7f12908 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -819,6 +819,8 @@ GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index e20ca32..5030c4a 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -131,6 +131,8 @@ GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (25 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition David Gibson
` (17 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bc2a2ce..bb96dd5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -381,7 +381,7 @@ struct ppc_slb_t {
#define LPCR_ISL (1ull << (63 - 2))
#define LPCR_KBV (1ull << (63 - 3))
#define LPCR_DPFD_SHIFT (63 - 11)
-#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
+#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
#define LPCR_VRMASD_SHIFT (63 - 16)
#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
#define LPCR_RMLS_SHIFT (63 - 37)
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (26 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9 David Gibson
` (16 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-qom.h | 5 ++++-
target/ppc/mmu_helper.c | 2 ++
target/ppc/translate_init.c | 3 +--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index b7977ba..4e3132b 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -86,10 +86,13 @@ enum powerpc_mmu_t {
POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
| POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000004,
- /* FIXME Add POWERPC_MMU_3_OO defines */
/* Architecture 2.07 "degraded" (no 1T segments) */
POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
| 0x00000004,
+ /* Architecture 3.00 variant */
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
+ | POWERPC_MMU_64K
+ | POWERPC_MMU_AMR | 0x00000005,
};
/*****************************************************************************/
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f746f53..172a305 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
+ case POWERPC_MMU_3_00:
#endif /* defined(TARGET_PPC64) */
env->tlb_need_flush = 0;
tlb_flush(CPU(cpu));
@@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
case POWERPC_MMU_2_07a:
+ case POWERPC_MMU_3_00:
/* tlbie invalidate TLBs for all segments */
/* XXX: given the fact that there are too many segments to invalidate,
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 76f79fa..84bf125 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
- /* Using 2.07 defines until new radix model is added. */
- pcc->mmu_model = POWERPC_MMU_2_07;
+ pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
/* segment page size remain the same */
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (27 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv David Gibson
` (15 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 18 ++++++++++++++++++
target/ppc/mmu-hash64.c | 8 ++++++++
target/ppc/translate_init.c | 24 ++++++++++++++++++------
3 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bb96dd5..425e79d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -384,12 +384,19 @@ struct ppc_slb_t {
#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
#define LPCR_VRMASD_SHIFT (63 - 16)
#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
+/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
+#define LPCR_PECE_U_SHIFT (63 - 19)
+#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
+#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
#define LPCR_RMLS_SHIFT (63 - 37)
#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
#define LPCR_ILE (1ull << (63 - 38))
#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
+#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */
+#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */
#define LPCR_ONL (1ull << (63 - 45))
+#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */
#define LPCR_P7_PECE0 (1ull << (63 - 49))
#define LPCR_P7_PECE1 (1ull << (63 - 50))
#define LPCR_P7_PECE2 (1ull << (63 - 51))
@@ -398,11 +405,22 @@ struct ppc_slb_t {
#define LPCR_P8_PECE2 (1ull << (63 - 49))
#define LPCR_P8_PECE3 (1ull << (63 - 50))
#define LPCR_P8_PECE4 (1ull << (63 - 51))
+/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
+#define LPCR_PECE_L_SHIFT (63 - 51)
+#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
+#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
+#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
+#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */
+#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */
+#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */
#define LPCR_MER (1ull << (63 - 52))
+#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */
#define LPCR_TC (1ull << (63 - 54))
+#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */
#define LPCR_LPES0 (1ull << (63 - 60))
#define LPCR_LPES1 (1ull << (63 - 61))
#define LPCR_RMI (1ull << (63 - 62))
+#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
#define LPCR_HDICE (1ull << (63 - 63))
#define msr_sf ((env->msr >> MSR_SF) & 1)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 2791f29..c09255d 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1062,6 +1062,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
break;
+ case POWERPC_MMU_3_00: /* P9 */
+ lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
+ break;
default:
;
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 84bf125..be35cbd 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
lpcr->default_value &= ~LPCR_RMLS;
lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
- /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
- * bit 47 and 48 which are reserved on P7. Here we set them all, which
- * will work as expected for both implementations
- */
- lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* By default we choose legacy mode and switch to new hash or radix
+ * when a register process table hcall is made. So disable process
+ * tables and guest translation shootdown by default
+ */
+ lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
+ lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
+ LPCR_OEE;
+ break;
+ default:
+ /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
+ * bit 47 and 48 which are reserved on P7. Here we set them all, which
+ * will work as expected for both implementations
+ */
+ lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
+ }
/* We should be followed by a CPU reset but update the active value
* just in case...
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (28 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9 David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function David Gibson
` (14 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Suraj Jitindar Singh, David Gibson
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-hash64.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c09255d..76669ed 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -652,7 +652,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@@ -670,7 +678,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (29 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 32/43] machine: move possible_cpus to MachineState David Gibson
` (13 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Thomas Huth <thuth@redhat.com>
hw_error() is for CPU related errors only (it prints out a
register dump and calls abort()), so we should not use it
if we just failed to load the bios image. Apart from that,
realize() functions should not exit directly but always set
the errp with error_setg() in case of errors instead.
Additionally, move some code around and delete the bios memory
subregion again in case of such an error, so that we leave a
clean state when returning to the caller.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/prep.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 5580293..260a119 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -309,7 +309,6 @@ static void raven_realize(PCIDevice *d, Error **errp)
memory_region_set_readonly(&s->bios, true);
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
&s->bios);
- vmstate_register_ram_global(&s->bios);
if (s->bios_name) {
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
if (filename) {
@@ -328,12 +327,15 @@ static void raven_realize(PCIDevice *d, Error **errp)
}
}
}
+ g_free(filename);
if (bios_size < 0 || bios_size > BIOS_SIZE) {
- /* FIXME should error_setg() */
- hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
+ memory_region_del_subregion(get_system_memory(), &s->bios);
+ error_setg(errp, "Could not load bios image '%s'", s->bios_name);
+ return;
}
- g_free(filename);
}
+
+ vmstate_register_ram_global(&s->bios);
}
static const VMStateDescription vmstate_raven = {
@@ -361,7 +363,6 @@ static void raven_class_init(ObjectClass *klass, void *data)
/*
* Reason: PCI-facing part of the host bridge, not usable without
* the host-facing part, which can't be device_add'ed, yet.
- * Reason: realize() method uses hw_error().
*/
dc->cannot_instantiate_with_device_add_yet = true;
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 32/43] machine: move possible_cpus to MachineState
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (30 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 33/43] pc: move pcms->possible_cpus init out of pc_cpus_init() David Gibson
` (12 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
so that it would be possible to reuse it with
spapr/virt-aarch64 targets.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i386/pc.c | 57 ++++++++++++++++++++++++++--------------------------
include/hw/boards.h | 1 +
include/hw/i386/pc.h | 1 -
3 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 60b0946..04c6e59 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -707,7 +707,8 @@ static void pc_build_smbios(PCMachineState *pcms)
size_t smbios_tables_len, smbios_anchor_len;
struct smbios_phys_mem_area *mem_array;
unsigned i, array_count;
- X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
+ MachineState *ms = MACHINE(pcms);
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
/* tell smbios about cpuid version and features */
smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
@@ -1111,7 +1112,7 @@ static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
void pc_hot_add_cpu(const int64_t id, Error **errp)
{
ObjectClass *oc;
- PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
+ MachineState *ms = MACHINE(qdev_get_machine());
int64_t apic_id = x86_cpu_apic_id_from_index(id);
Error *local_err = NULL;
@@ -1127,8 +1128,8 @@ void pc_hot_add_cpu(const int64_t id, Error **errp)
return;
}
- assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */
- oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu));
+ assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */
+ oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu));
pc_new_cpu(object_class_get_name(oc), apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
@@ -1178,11 +1179,11 @@ void pc_cpus_init(PCMachineState *pcms)
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
*/
pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
- pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
- sizeof(CPUArchId) * max_cpus);
+ machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+ sizeof(CPUArchId) * max_cpus);
for (i = 0; i < max_cpus; i++) {
- pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
- pcms->possible_cpus->len++;
+ machine->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
+ machine->possible_cpus->len++;
if (i < smp_cpus) {
pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), &error_fatal);
}
@@ -1191,7 +1192,8 @@ void pc_cpus_init(PCMachineState *pcms)
static void pc_build_feature_control_file(PCMachineState *pcms)
{
- X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu);
+ MachineState *ms = MACHINE(pcms);
+ X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
CPUX86State *env = &cpu->env;
uint32_t unused, ecx, edx;
uint64_t feature_control_bits = 0;
@@ -1787,21 +1789,20 @@ static int pc_apic_cmp(const void *a, const void *b)
}
/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
- * in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no
+ * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
* entry corresponding to CPU's apic_id returns NULL.
*/
-static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu,
- int *idx)
+static CPUArchId *pc_find_cpu_slot(MachineState *ms, CPUState *cpu, int *idx)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchId apic_id, *found_cpu;
apic_id.arch_id = cc->get_arch_id(CPU(cpu));
- found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus,
- pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus),
+ found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
+ ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
pc_apic_cmp);
if (found_cpu && idx) {
- *idx = found_cpu - pcms->possible_cpus->cpus;
+ *idx = found_cpu - ms->possible_cpus->cpus;
}
return found_cpu;
}
@@ -1831,7 +1832,7 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
}
- found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
+ found_cpu = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), NULL);
found_cpu->cpu = CPU(dev);
out:
error_propagate(errp, local_err);
@@ -1844,7 +1845,7 @@ static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
Error *local_err = NULL;
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
- pc_find_cpu_slot(pcms, CPU(dev), &idx);
+ pc_find_cpu_slot(MACHINE(pcms), CPU(dev), &idx);
assert(idx != -1);
if (idx == 0) {
error_setg(&local_err, "Boot CPU is unpluggable");
@@ -1878,7 +1879,7 @@ static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
goto out;
}
- found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL);
+ found_cpu = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), NULL);
found_cpu->cpu = NULL;
object_unparent(OBJECT(dev));
@@ -1936,13 +1937,15 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
}
- cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx);
+ cpu_slot = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), &idx);
if (!cpu_slot) {
+ MachineState *ms = MACHINE(pcms);
+
x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
- pcms->possible_cpus->len - 1);
+ ms->possible_cpus->len - 1);
return;
}
@@ -2253,9 +2256,8 @@ static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine)
{
- PCMachineState *pcms = PC_MACHINE(machine);
- assert(pcms->possible_cpus);
- return pcms->possible_cpus;
+ assert(machine->possible_cpus);
+ return machine->possible_cpus;
}
static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
@@ -2263,19 +2265,18 @@ static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
int i;
CPUState *cpu;
HotpluggableCPUList *head = NULL;
- PCMachineState *pcms = PC_MACHINE(machine);
const char *cpu_type;
- cpu = pcms->possible_cpus->cpus[0].cpu;
+ cpu = machine->possible_cpus->cpus[0].cpu;
assert(cpu); /* BSP is always present */
cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu)));
- for (i = 0; i < pcms->possible_cpus->len; i++) {
+ for (i = 0; i < machine->possible_cpus->len; i++) {
X86CPUTopoInfo topo;
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
- const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id;
+ const uint32_t apic_id = machine->possible_cpus->cpus[i].arch_id;
x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo);
@@ -2289,7 +2290,7 @@ static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
cpu_props->thread_id = topo.smt_id;
cpu_item->props = cpu_props;
- cpu = pcms->possible_cpus->cpus[i].cpu;
+ cpu = machine->possible_cpus->cpus[i].cpu;
if (cpu) {
cpu_item->has_qom_path = true;
cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
diff --git a/include/hw/boards.h b/include/hw/boards.h
index ac891a8..64e8c07 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -178,6 +178,7 @@ struct MachineState {
char *initrd_filename;
const char *cpu_model;
AccelState *accelerator;
+ CPUArchIdList *possible_cpus;
};
#define DEFINE_MACHINE(namestr, machine_initfn) \
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 079e8d9..d1f4554 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -73,7 +73,6 @@ struct PCMachineState {
/* CPU and apic information: */
bool apic_xrupt_override;
unsigned apic_id_limit;
- CPUArchIdList *possible_cpus;
uint16_t boot_cpus;
/* NUMA information: */
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 33/43] pc: move pcms->possible_cpus init out of pc_cpus_init()
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (31 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 32/43] machine: move possible_cpus to MachineState David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 34/43] pc: calculate topology only once when possible_cpus is initialised David Gibson
` (11 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
possible_cpus could be initialized earlier then cpu objects,
i.e. when -smp is parsed so move init code to possible_cpu_arch_ids()
interface func and do initialization on the first call.
it should help later with making -numa cpu/-smp parsing a machine state
properties.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i386/pc.c | 35 ++++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 04c6e59..a187748 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1144,7 +1144,9 @@ void pc_cpus_init(PCMachineState *pcms)
ObjectClass *oc;
const char *typename;
gchar **model_pieces;
+ const CPUArchIdList *possible_cpus;
MachineState *machine = MACHINE(pcms);
+ MachineClass *mc = MACHINE_GET_CLASS(pcms);
/* init CPUs */
if (machine->cpu_model == NULL) {
@@ -1179,14 +1181,9 @@ void pc_cpus_init(PCMachineState *pcms)
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
*/
pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
- machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
- sizeof(CPUArchId) * max_cpus);
- for (i = 0; i < max_cpus; i++) {
- machine->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
- machine->possible_cpus->len++;
- if (i < smp_cpus) {
- pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), &error_fatal);
- }
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
+ for (i = 0; i < smp_cpus; i++) {
+ pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
@@ -2254,10 +2251,26 @@ static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index)
return topo.pkg_id;
}
-static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine)
+static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
{
- assert(machine->possible_cpus);
- return machine->possible_cpus;
+ int i;
+
+ if (ms->possible_cpus) {
+ /*
+ * make sure that max_cpus hasn't changed since the first use, i.e.
+ * -smp hasn't been parsed after it
+ */
+ assert(ms->possible_cpus->len == max_cpus);
+ return ms->possible_cpus;
+ }
+
+ ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+ sizeof(CPUArchId) * max_cpus);
+ ms->possible_cpus->len = max_cpus;
+ for (i = 0; i < ms->possible_cpus->len; i++) {
+ ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
+ }
+ return ms->possible_cpus;
}
static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 34/43] pc: calculate topology only once when possible_cpus is initialised
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (32 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 33/43] pc: move pcms->possible_cpus init out of pc_cpus_init() David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object David Gibson
` (10 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Fill in CpuInstanceProperties once at board init time and
just copy them whenever query_hotpluggable_cpus() is called.
It will keep topology info always available without need
to recalculate it every time it's needed.
Considering it has NUMA node id, it will be used to keep
NUMA node to cpu mapping instead of numa_info[i].node_cpu
bitmasks.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i386/pc.c | 24 ++++++++++++------------
include/hw/boards.h | 2 ++
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a187748..50ba977 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2268,7 +2268,17 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
for (i = 0; i < ms->possible_cpus->len; i++) {
+ X86CPUTopoInfo topo;
+
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
+ x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+ smp_cores, smp_threads, &topo);
+ ms->possible_cpus->cpus[i].props.has_socket_id = true;
+ ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
+ ms->possible_cpus->cpus[i].props.has_core_id = true;
+ ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
+ ms->possible_cpus->cpus[i].props.has_thread_id = true;
+ ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
}
return ms->possible_cpus;
}
@@ -2285,23 +2295,13 @@ static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu)));
for (i = 0; i < machine->possible_cpus->len; i++) {
- X86CPUTopoInfo topo;
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
- CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
- const uint32_t apic_id = machine->possible_cpus->cpus[i].arch_id;
-
- x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo);
cpu_item->type = g_strdup(cpu_type);
cpu_item->vcpus_count = 1;
- cpu_props->has_socket_id = true;
- cpu_props->socket_id = topo.pkg_id;
- cpu_props->has_core_id = true;
- cpu_props->core_id = topo.core_id;
- cpu_props->has_thread_id = true;
- cpu_props->thread_id = topo.smt_id;
- cpu_item->props = cpu_props;
+ cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
+ sizeof(*cpu_item->props));
cpu = machine->possible_cpus->cpus[i].cpu;
if (cpu) {
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 64e8c07..4023b38 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -46,9 +46,11 @@ void machine_register_compat_props(MachineState *machine);
* CPUArchId:
* @arch_id - architecture-dependent CPU ID of present or possible CPU
* @cpu - pointer to corresponding CPU object if it's present on NULL otherwise
+ * @props - CPU object properties, initialized by board
*/
typedef struct {
uint64_t arch_id;
+ CpuInstanceProperties props;
struct CPUState *cpu;
} CPUArchId;
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (33 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 34/43] pc: calculate topology only once when possible_cpus is initialised David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 36/43] change CPUArchId.cpu type to Object* David Gibson
` (9 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i386/pc.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 50ba977..3475174 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1789,12 +1789,11 @@ static int pc_apic_cmp(const void *a, const void *b)
* in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
* entry corresponding to CPU's apic_id returns NULL.
*/
-static CPUArchId *pc_find_cpu_slot(MachineState *ms, CPUState *cpu, int *idx)
+static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchId apic_id, *found_cpu;
- apic_id.arch_id = cc->get_arch_id(CPU(cpu));
+ apic_id.arch_id = id;
found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
pc_apic_cmp);
@@ -1810,6 +1809,7 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
CPUArchId *found_cpu;
HotplugHandlerClass *hhc;
Error *local_err = NULL;
+ X86CPU *cpu = X86_CPU(dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
if (pcms->acpi_dev) {
@@ -1829,7 +1829,7 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
}
- found_cpu = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), NULL);
+ found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
found_cpu->cpu = CPU(dev);
out:
error_propagate(errp, local_err);
@@ -1840,9 +1840,10 @@ static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
int idx = -1;
HotplugHandlerClass *hhc;
Error *local_err = NULL;
+ X86CPU *cpu = X86_CPU(dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
- pc_find_cpu_slot(MACHINE(pcms), CPU(dev), &idx);
+ pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
assert(idx != -1);
if (idx == 0) {
error_setg(&local_err, "Boot CPU is unpluggable");
@@ -1867,6 +1868,7 @@ static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
CPUArchId *found_cpu;
HotplugHandlerClass *hhc;
Error *local_err = NULL;
+ X86CPU *cpu = X86_CPU(dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
@@ -1876,7 +1878,7 @@ static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
goto out;
}
- found_cpu = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), NULL);
+ found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
found_cpu->cpu = NULL;
object_unparent(OBJECT(dev));
@@ -1934,7 +1936,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
}
- cpu_slot = pc_find_cpu_slot(MACHINE(pcms), CPU(dev), &idx);
+ cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 36/43] change CPUArchId.cpu type to Object*
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (34 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 37/43] spapr: reuse machine->possible_cpus instead of cores[] David Gibson
` (8 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
so it could be reused for SPAPR cores as well
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/acpi/cpu.c | 2 +-
hw/i386/pc.c | 8 ++++----
include/hw/boards.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 6017ca0..8c719d3 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -198,7 +198,7 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
state->dev_count = id_list->len;
state->devs = g_new0(typeof(*state->devs), state->dev_count);
for (i = 0; i < id_list->len; i++) {
- state->devs[i].cpu = id_list->cpus[i].cpu;
+ state->devs[i].cpu = CPU(id_list->cpus[i].cpu);
state->devs[i].arch_id = id_list->cpus[i].arch_id;
}
memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state,
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3475174..138022d 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1830,7 +1830,7 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev,
}
found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
- found_cpu->cpu = CPU(dev);
+ found_cpu->cpu = OBJECT(dev);
out:
error_propagate(errp, local_err);
}
@@ -2288,13 +2288,13 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
{
int i;
- CPUState *cpu;
+ Object *cpu;
HotpluggableCPUList *head = NULL;
const char *cpu_type;
cpu = machine->possible_cpus->cpus[0].cpu;
assert(cpu); /* BSP is always present */
- cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu)));
+ cpu_type = object_get_typename(cpu);
for (i = 0; i < machine->possible_cpus->len; i++) {
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
@@ -2308,7 +2308,7 @@ static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
cpu = machine->possible_cpus->cpus[i].cpu;
if (cpu) {
cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
+ cpu_item->qom_path = object_get_canonical_path(cpu);
}
list_item->value = cpu_item;
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 4023b38..60209df 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -51,7 +51,7 @@ void machine_register_compat_props(MachineState *machine);
typedef struct {
uint64_t arch_id;
CpuInstanceProperties props;
- struct CPUState *cpu;
+ Object *cpu;
} CPUArchId;
/**
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (35 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 36/43] change CPUArchId.cpu type to Object* David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 11:05 ` [Qemu-devel] [PATCH " Igor Mammedov
2017-02-22 6:33 ` [Qemu-devel] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks David Gibson
` (7 subsequent siblings)
44 siblings, 1 reply; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Replace SPAPR specific cores[] array with generic
machine->possible_cpus and store core objects there.
It makes cores bookkeeping similar to x86 cpus and
will allow to unify similar code.
It would allow to replace cpu_index based NUMA node
mapping with iproperty based one (for -device created
cores) since possible_cpus carries board defined
topology/layout.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 129 ++++++++++++++++++++++++++++++++++---------------
include/hw/ppc/spapr.h | 1 -
2 files changed, 90 insertions(+), 40 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 37cb338..a0aa69e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1751,13 +1751,28 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
}
}
+/* find cpu slot in machine->possible_cpus by core_id */
+static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
+{
+ int index = id / smp_threads;
+
+ if (index >= ms->possible_cpus->len) {
+ return NULL;
+ }
+ if (idx) {
+ *idx = index;
+ }
+ return &ms->possible_cpus->cpus[index];
+}
+
static void spapr_init_cpus(sPAPRMachineState *spapr)
{
MachineState *machine = MACHINE(spapr);
MachineClass *mc = MACHINE_GET_CLASS(machine);
char *type = spapr_get_cpu_core_type(machine->cpu_model);
int smt = kvmppc_smt_threads();
- int spapr_max_cores, spapr_cores;
+ const CPUArchIdList *possible_cpus;
+ int boot_cores_nr = smp_cpus / smp_threads;
int i;
if (!type) {
@@ -1765,6 +1780,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
exit(1);
}
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
if (mc->query_hotpluggable_cpus) {
if (smp_cpus % smp_threads) {
error_report("smp_cpus (%u) must be multiple of threads (%u)",
@@ -1776,21 +1792,15 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
max_cpus, smp_threads);
exit(1);
}
-
- spapr_max_cores = max_cpus / smp_threads;
- spapr_cores = smp_cpus / smp_threads;
} else {
if (max_cpus != smp_cpus) {
error_report("This machine version does not support CPU hotplug");
exit(1);
}
-
- spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
- spapr_cores = spapr_max_cores;
+ boot_cores_nr = possible_cpus->len;
}
- spapr->cores = g_new0(Object *, spapr_max_cores);
- for (i = 0; i < spapr_max_cores; i++) {
+ for (i = 0; i < possible_cpus->len; i++) {
int core_id = i * smp_threads;
if (mc->query_hotpluggable_cpus) {
@@ -1802,7 +1812,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
qemu_register_reset(spapr_drc_reset, drc);
}
- if (i < spapr_cores) {
+ if (i < boot_cores_nr) {
Object *core = object_new(type);
int nr_threads = smp_threads;
@@ -2491,10 +2501,11 @@ void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ MachineState *ms = MACHINE(qdev_get_machine());
CPUCore *cc = CPU_CORE(dev);
+ CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
- spapr->cores[cc->core_id / smp_threads] = NULL;
+ core_slot->cpu = NULL;
object_unparent(OBJECT(dev));
}
@@ -2510,19 +2521,24 @@ static
void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- CPUCore *cc = CPU_CORE(dev);
- int smt = kvmppc_smt_threads();
- int index = cc->core_id / smp_threads;
- sPAPRDRConnector *drc =
- spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
+ int index;
+ sPAPRDRConnector *drc;
sPAPRDRConnectorClass *drck;
Error *local_err = NULL;
+ CPUCore *cc = CPU_CORE(dev);
+ int smt = kvmppc_smt_threads();
+ if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
+ error_setg(errp, "Unable to find CPU core with core-id: %d",
+ cc->core_id);
+ return;
+ }
if (index == 0) {
error_setg(errp, "Boot CPU core may not be unplugged");
return;
}
+ drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
g_assert(drc);
drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
@@ -2547,11 +2563,17 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error *local_err = NULL;
void *fdt = NULL;
int fdt_offset = 0;
- int index = cc->core_id / smp_threads;
int smt = kvmppc_smt_threads();
+ CPUArchId *core_slot;
+ int index;
+ core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
+ if (!core_slot) {
+ error_setg(errp, "Unable to find CPU core with core-id: %d",
+ cc->core_id);
+ return;
+ }
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
- spapr->cores[index] = OBJECT(dev);
g_assert(drc || !mc->query_hotpluggable_cpus);
@@ -2568,7 +2590,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
if (local_err) {
g_free(fdt);
- spapr->cores[index] = NULL;
error_propagate(errp, local_err);
return;
}
@@ -2590,6 +2611,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
}
}
+ core_slot->cpu = OBJECT(dev);
}
static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -2597,13 +2619,12 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
{
MachineState *machine = MACHINE(OBJECT(hotplug_dev));
MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
- sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
- int spapr_max_cores = max_cpus / smp_threads;
- int index;
Error *local_err = NULL;
CPUCore *cc = CPU_CORE(dev);
char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
const char *type = object_get_typename(OBJECT(dev));
+ CPUArchId *core_slot;
+ int index;
if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
error_setg(&local_err, "CPU hotplug not supported for this machine");
@@ -2620,13 +2641,13 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
goto out;
}
- index = cc->core_id / smp_threads;
- if (index < 0 || index >= spapr_max_cores) {
+ core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
+ if (!core_slot) {
error_setg(&local_err, "core id %d out of range", cc->core_id);
goto out;
}
- if (spapr->cores[index]) {
+ if (core_slot->cpu) {
error_setg(&local_err, "core %d already populated", cc->core_id);
goto out;
}
@@ -2758,29 +2779,58 @@ static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
return cpu_index / smp_threads / smp_cores;
}
+static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
+{
+ int i;
+ int spapr_max_cores = max_cpus / smp_threads;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (!mc->query_hotpluggable_cpus) {
+ spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
+ }
+ if (machine->possible_cpus) {
+ assert(machine->possible_cpus->len == spapr_max_cores);
+ return machine->possible_cpus;
+ }
+
+ machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+ sizeof(CPUArchId) * spapr_max_cores);
+ machine->possible_cpus->len = spapr_max_cores;
+ for (i = 0; i < machine->possible_cpus->len; i++) {
+ int core_id = i * smp_threads;
+
+ machine->possible_cpus->cpus[i].arch_id = core_id;
+ machine->possible_cpus->cpus[i].props.has_core_id = true;
+ machine->possible_cpus->cpus[i].props.core_id = core_id;
+ /* TODO: add 'has_node/node' here to describe
+ to which node core belongs */
+ }
+ return machine->possible_cpus;
+}
+
static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
{
int i;
+ Object *cpu;
HotpluggableCPUList *head = NULL;
- sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
- int spapr_max_cores = max_cpus / smp_threads;
+ const char *cpu_type;
- for (i = 0; i < spapr_max_cores; i++) {
+ cpu = machine->possible_cpus->cpus[0].cpu;
+ assert(cpu); /* Boot cpu is always present */
+ cpu_type = object_get_typename(cpu);
+ for (i = 0; i < machine->possible_cpus->len; i++) {
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
- CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
- cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
- cpu_item->vcpus_count = smp_threads;
- cpu_props->has_core_id = true;
- cpu_props->core_id = i * smp_threads;
- /* TODO: add 'has_node/node' here to describe
- to which node core belongs */
+ cpu_item->type = g_strdup(cpu_type);
+ cpu_item->vcpus_count = smp_threads; // TODO: ??? generalize
+ cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
+ sizeof(*cpu_item->props));
- cpu_item->props = cpu_props;
- if (spapr->cores[i]) {
+ cpu = machine->possible_cpus->cpus[i].cpu;
+ if (cpu) {
cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
+ cpu_item->qom_path = object_get_canonical_path(cpu);
}
list_item->value = cpu_item;
list_item->next = head;
@@ -2872,6 +2922,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
hc->plug = spapr_machine_device_plug;
hc->unplug = spapr_machine_device_unplug;
mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
+ mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
hc->unplug_request = spapr_machine_device_unplug_request;
smc->dr_lmb_enabled = true;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index a2d8964..f9b17d8 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -94,7 +94,6 @@ struct sPAPRMachineState {
/*< public >*/
char *kvm_type;
MemoryHotplugState hotplug_memory;
- Object **cores;
};
#define H_SUCCESS 0
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (36 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 37/43] spapr: reuse machine->possible_cpus instead of cores[] David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 11:07 ` [Qemu-devel] [PATCH " Igor Mammedov
2017-02-22 6:33 ` [Qemu-devel] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag David Gibson
` (6 subsequent siblings)
44 siblings, 1 reply; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
All callbacks FOO_query_hotpluggable_cpus() are practically
the same except of setting vcpus_count to different values.
Convert them to a generic machine_query_hotpluggable_cpus()
callback by moving vcpus_count initialization to per machine
specific callback possible_cpu_arch_ids().
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/core/machine.c | 31 +++++++++++++++++++++++++++++++
hw/i386/pc.c | 36 ++----------------------------------
hw/ppc/spapr.c | 34 ++--------------------------------
include/hw/boards.h | 3 +++
4 files changed, 38 insertions(+), 66 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index b0fd91f..0699750 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -357,6 +357,37 @@ static void machine_init_notify(Notifier *notifier, void *data)
foreach_dynamic_sysbus_device(error_on_sysbus_device, NULL);
}
+HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
+{
+ int i;
+ Object *cpu;
+ HotpluggableCPUList *head = NULL;
+ const char *cpu_type;
+
+ cpu = machine->possible_cpus->cpus[0].cpu;
+ assert(cpu); /* Boot cpu is always present */
+ cpu_type = object_get_typename(cpu);
+ for (i = 0; i < machine->possible_cpus->len; i++) {
+ HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
+ HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
+
+ cpu_item->type = g_strdup(cpu_type);
+ cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
+ cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
+ sizeof(*cpu_item->props));
+
+ cpu = machine->possible_cpus->cpus[i].cpu;
+ if (cpu) {
+ cpu_item->has_qom_path = true;
+ cpu_item->qom_path = object_get_canonical_path(cpu);
+ }
+ list_item->value = cpu_item;
+ list_item->next = head;
+ head = list_item;
+ }
+ return head;
+}
+
static void machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 138022d..f96cfc6 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2272,6 +2272,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
for (i = 0; i < ms->possible_cpus->len; i++) {
X86CPUTopoInfo topo;
+ ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
smp_cores, smp_threads, &topo);
@@ -2285,39 +2286,6 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
return ms->possible_cpus;
}
-static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
-{
- int i;
- Object *cpu;
- HotpluggableCPUList *head = NULL;
- const char *cpu_type;
-
- cpu = machine->possible_cpus->cpus[0].cpu;
- assert(cpu); /* BSP is always present */
- cpu_type = object_get_typename(cpu);
-
- for (i = 0; i < machine->possible_cpus->len; i++) {
- HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
- HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
-
- cpu_item->type = g_strdup(cpu_type);
- cpu_item->vcpus_count = 1;
- cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
- sizeof(*cpu_item->props));
-
- cpu = machine->possible_cpus->cpus[i].cpu;
- if (cpu) {
- cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(cpu);
- }
-
- list_item->value = cpu_item;
- list_item->next = head;
- head = list_item;
- }
- return head;
-}
-
static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
{
/* cpu index isn't used */
@@ -2358,7 +2326,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->get_hotplug_handler = pc_get_hotpug_handler;
mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
- mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus;
+ mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
mc->default_boot_order = "cad";
mc->hot_add_cpu = pc_hot_add_cpu;
mc->block_default_type = IF_IDE;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a0aa69e..49768eb 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2799,6 +2799,7 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
for (i = 0; i < machine->possible_cpus->len; i++) {
int core_id = i * smp_threads;
+ machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
machine->possible_cpus->cpus[i].arch_id = core_id;
machine->possible_cpus->cpus[i].props.has_core_id = true;
machine->possible_cpus->cpus[i].props.core_id = core_id;
@@ -2808,37 +2809,6 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
return machine->possible_cpus;
}
-static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
-{
- int i;
- Object *cpu;
- HotpluggableCPUList *head = NULL;
- const char *cpu_type;
-
- cpu = machine->possible_cpus->cpus[0].cpu;
- assert(cpu); /* Boot cpu is always present */
- cpu_type = object_get_typename(cpu);
- for (i = 0; i < machine->possible_cpus->len; i++) {
- HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
- HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
-
- cpu_item->type = g_strdup(cpu_type);
- cpu_item->vcpus_count = smp_threads; // TODO: ??? generalize
- cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
- sizeof(*cpu_item->props));
-
- cpu = machine->possible_cpus->cpus[i].cpu;
- if (cpu) {
- cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(cpu);
- }
- list_item->value = cpu_item;
- list_item->next = head;
- head = list_item;
- }
- return head;
-}
-
static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
uint64_t *buid, hwaddr *pio,
hwaddr *mmio32, hwaddr *mmio64,
@@ -2927,7 +2897,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->dr_lmb_enabled = true;
smc->tcg_default_cpu = "POWER8";
- mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
+ mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 60209df..9040dbb 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -41,15 +41,18 @@ int machine_phandle_start(MachineState *machine);
bool machine_dump_guest_core(MachineState *machine);
bool machine_mem_merge(MachineState *machine);
void machine_register_compat_props(MachineState *machine);
+HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine);
/**
* CPUArchId:
* @arch_id - architecture-dependent CPU ID of present or possible CPU
* @cpu - pointer to corresponding CPU object if it's present on NULL otherwise
* @props - CPU object properties, initialized by board
+ * #vcpus_count - number of threads provided by @cpu object
*/
typedef struct {
uint64_t arch_id;
+ int64_t vcpus_count;
CpuInstanceProperties props;
Object *cpu;
} CPUArchId;
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (37 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 40/43] hw/net/spapr_llan: 6 byte mac address device tree entry David Gibson
` (5 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Generic helper machine_query_hotpluggable_cpus() replaced
target specific query_hotpluggable_cpus() callbacks so
there is no need in it anymore. However inon NULL callback
value is used to detect/report hotpluggable cpus support,
therefore it can be removed completely.
Replace it with MachineClass.has_hotpluggable_cpus boolean
which is sufficient for the task.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/i386/pc.c | 4 ++--
hw/ppc/spapr.c | 20 ++++++++++----------
include/hw/boards.h | 8 +++-----
monitor.c | 4 ++--
vl.c | 2 +-
5 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f96cfc6..d24388e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1955,7 +1955,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
}
/* if 'address' properties socket-id/core-id/thread-id are not set, set them
- * so that query_hotpluggable_cpus would show correct values
+ * so that machine_query_hotpluggable_cpus would show correct values
*/
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
@@ -2326,7 +2326,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->get_hotplug_handler = pc_get_hotpug_handler;
mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
- mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
+ mc->has_hotpluggable_cpus = true;
mc->default_boot_order = "cad";
mc->hot_add_cpu = pc_hot_add_cpu;
mc->block_default_type = IF_IDE;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 49768eb..6f37288 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -958,7 +958,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,
_FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
}
- if (mc->query_hotpluggable_cpus) {
+ if (mc->has_hotpluggable_cpus) {
int offset = fdt_path_offset(fdt, "/cpus");
ret = spapr_drc_populate_dt(fdt, offset, NULL,
SPAPR_DR_CONNECTOR_TYPE_CPU);
@@ -1781,7 +1781,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
}
possible_cpus = mc->possible_cpu_arch_ids(machine);
- if (mc->query_hotpluggable_cpus) {
+ if (mc->has_hotpluggable_cpus) {
if (smp_cpus % smp_threads) {
error_report("smp_cpus (%u) must be multiple of threads (%u)",
smp_cpus, smp_threads);
@@ -1803,7 +1803,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
for (i = 0; i < possible_cpus->len; i++) {
int core_id = i * smp_threads;
- if (mc->query_hotpluggable_cpus) {
+ if (mc->has_hotpluggable_cpus) {
sPAPRDRConnector *drc =
spapr_dr_connector_new(OBJECT(spapr),
SPAPR_DR_CONNECTOR_TYPE_CPU,
@@ -2575,7 +2575,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
}
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
- g_assert(drc || !mc->query_hotpluggable_cpus);
+ g_assert(drc || !mc->has_hotpluggable_cpus);
/*
* Setup CPU DT entries only for hotplugged CPUs. For boot time or
@@ -2626,7 +2626,7 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
CPUArchId *core_slot;
int index;
- if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
+ if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
error_setg(&local_err, "CPU hotplug not supported for this machine");
goto out;
}
@@ -2719,7 +2719,7 @@ static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
error_setg(errp, "Memory hot unplug not supported for this guest");
}
} else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
- if (!mc->query_hotpluggable_cpus) {
+ if (!mc->has_hotpluggable_cpus) {
error_setg(errp, "CPU hot unplug not supported on this machine");
return;
}
@@ -2746,7 +2746,7 @@ static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
error_setg(errp, "Memory hot unplug not supported for this guest");
}
} else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
- if (!mc->query_hotpluggable_cpus) {
+ if (!mc->has_hotpluggable_cpus) {
error_setg(errp, "CPU hot unplug not supported on this machine");
return;
}
@@ -2785,7 +2785,7 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
int spapr_max_cores = max_cpus / smp_threads;
MachineClass *mc = MACHINE_GET_CLASS(machine);
- if (!mc->query_hotpluggable_cpus) {
+ if (!mc->has_hotpluggable_cpus) {
spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
}
if (machine->possible_cpus) {
@@ -2897,7 +2897,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->dr_lmb_enabled = true;
smc->tcg_default_cpu = "POWER8";
- mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
+ mc->has_hotpluggable_cpus = true;
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
@@ -3097,7 +3097,7 @@ static void spapr_machine_2_6_instance_options(MachineState *machine)
static void spapr_machine_2_6_class_options(MachineClass *mc)
{
spapr_machine_2_7_class_options(mc);
- mc->query_hotpluggable_cpus = NULL;
+ mc->has_hotpluggable_cpus = false;
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 9040dbb..269d0ba 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -87,10 +87,8 @@ typedef struct {
* Returns an array of @CPUArchId architecture-dependent CPU IDs
* which includes CPU IDs for present and possible to hotplug CPUs.
* Caller is responsible for freeing returned list.
- * @query_hotpluggable_cpus:
- * Returns a @HotpluggableCPUList, which describes CPUs objects which
- * could be added with -device/device_add.
- * Caller is responsible for freeing returned list.
+ * @has_hotpluggable_cpus:
+ * If true, board supports CPUs creation with -device/device_add.
* @minimum_page_bits:
* If non-zero, the board promises never to create a CPU with a page size
* smaller than this, so QEMU can use a more efficient larger page
@@ -136,12 +134,12 @@ struct MachineClass {
bool option_rom_has_mr;
bool rom_file_has_mr;
int minimum_page_bits;
+ bool has_hotpluggable_cpus;
HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
DeviceState *dev);
unsigned (*cpu_index_to_socket_id)(unsigned cpu_index);
const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
- HotpluggableCPUList *(*query_hotpluggable_cpus)(MachineState *machine);
};
/**
diff --git a/monitor.c b/monitor.c
index 3cd72a9..18bf2f8e 100644
--- a/monitor.c
+++ b/monitor.c
@@ -4155,10 +4155,10 @@ HotpluggableCPUList *qmp_query_hotpluggable_cpus(Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
MachineClass *mc = MACHINE_GET_CLASS(ms);
- if (!mc->query_hotpluggable_cpus) {
+ if (!mc->has_hotpluggable_cpus) {
error_setg(errp, QERR_FEATURE_DISABLED, "query-hotpluggable-cpus");
return NULL;
}
- return mc->query_hotpluggable_cpus(ms);
+ return machine_query_hotpluggable_cpus(ms);
}
diff --git a/vl.c b/vl.c
index b5d0a19..904e34b 100644
--- a/vl.c
+++ b/vl.c
@@ -1492,7 +1492,7 @@ MachineInfoList *qmp_query_machines(Error **errp)
info->name = g_strdup(mc->name);
info->cpu_max = !mc->max_cpus ? 1 : mc->max_cpus;
- info->hotpluggable_cpus = !!mc->query_hotpluggable_cpus;
+ info->hotpluggable_cpus = mc->has_hotpluggable_cpus;
entry = g_malloc0(sizeof(*entry));
entry->value = info;
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 40/43] hw/net/spapr_llan: 6 byte mac address device tree entry
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (38 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 41/43] target-ppc: fix Book-E TLB matching David Gibson
` (4 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Sam Bobroff, David Gibson
From: Sam Bobroff <sam.bobroff@au1.ibm.com>
The spapr-vlan device in QEMU has always presented it's MAC address in
the device tree as an 8 byte value, even though PAPR requires it to be
6 bytes. This is because, at the time, AIX required the value to be 8
bytes. However, modern versions of AIX support the (correct) 6
byte value so they no longer require the workaround.
It would be neatest to always provide a 6 byte value but that would
cause a problem with old Linux kernel ibmveth drivers, so the old 8
byte value is still presented when necessary.
Since commit 13f85203e (3.10, May 2013) the driver has been able to
handle 6 or 8 byte addresses so versions after that don't need to be
considered specially.
Drivers from kernels before that can also handle either type of
address, but not always:
* If the first byte's lowest bits are 10, the address must be 6 bytes.
* Otherwise, the address must be 8 bytes.
(The two bits in question are significant in a MAC address: they
indicate a locally-administered unicast address.)
So to maintain compatibility the old 8 byte value is presented when
the lowest two bits of the first byte are not 10.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/net/spapr_llan.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c
index 058908d..d239e4b 100644
--- a/hw/net/spapr_llan.c
+++ b/hw/net/spapr_llan.c
@@ -385,18 +385,24 @@ static int spapr_vlan_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
int ret;
/* Some old phyp versions give the mac address in an 8-byte
- * property. The kernel driver has an insane workaround for this;
+ * property. The kernel driver (before 3.10) has an insane workaround;
* rather than doing the obvious thing and checking the property
* length, it checks whether the first byte has 0b10 in the low
* bits. If a correct 6-byte property has a different first byte
* the kernel will get the wrong mac address, overrunning its
* buffer in the process (read only, thank goodness).
*
- * Here we workaround the kernel workaround by always supplying an
- * 8-byte property, with the mac address in the last six bytes */
- memcpy(&padded_mac[2], &vdev->nicconf.macaddr, ETH_ALEN);
- ret = fdt_setprop(fdt, node_off, "local-mac-address",
- padded_mac, sizeof(padded_mac));
+ * Here we return a 6-byte address unless that would break a pre-3.10
+ * driver. In that case we return a padded 8-byte address to allow the old
+ * workaround to succeed. */
+ if ((vdev->nicconf.macaddr.a[0] & 0x3) == 0x2) {
+ ret = fdt_setprop(fdt, node_off, "local-mac-address",
+ &vdev->nicconf.macaddr, ETH_ALEN);
+ } else {
+ memcpy(&padded_mac[2], &vdev->nicconf.macaddr, ETH_ALEN);
+ ret = fdt_setprop(fdt, node_off, "local-mac-address",
+ padded_mac, sizeof(padded_mac));
+ }
if (ret < 0) {
return ret;
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 41/43] target-ppc: fix Book-E TLB matching
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (39 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 40/43] hw/net/spapr_llan: 6 byte mac address device tree entry David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 42/43] hw/ppc/spapr: Check for valid page size when hot plugging memory David Gibson
` (3 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
Alex Zuepke, David Gibson
From: Alex Zuepke <azu@sysgo.de>
The Book-E TLB matching process should bail out early when a TLB
entry matches, but the access permissions are wrong. The CPU
will then raise a DSI error instead of a Data TLB error, as
described for TLB matching in Freescale and IBM documents.
Signed-off-by: Alex Zuepke <azu@sysgo.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 172a305..eb2d482 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -825,7 +825,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
access_type, i);
- if (!ret) {
+ if (ret != -1) {
break;
}
}
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 42/43] hw/ppc/spapr: Check for valid page size when hot plugging memory
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (40 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 41/43] target-ppc: fix Book-E TLB matching David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 43/43] hw/ppc/ppc405_uc.c: Avoid integer overflows David Gibson
` (2 subsequent siblings)
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Thomas Huth <thuth@redhat.com>
On POWER, the valid page sizes that the guest can use are bound
to the CPU and not to the memory region. QEMU already has some
fancy logic to find out the right maximum memory size to tell
it to the guest during boot (see getrampagesize() in the file
target/ppc/kvm.c for more information).
However, once we're booted and the guest is using huge pages
already, it is currently still possible to hot-plug memory regions
that does not support huge pages - which of course does not work
on POWER, since the guest thinks that it is possible to use huge
pages everywhere. The KVM_RUN ioctl will then abort with -EFAULT,
QEMU spills out a not very helpful error message together with
a register dump and the user is annoyed that the VM unexpectedly
died.
To avoid this situation, we should check the page size of hot-plugged
DIMMs to see whether it is possible to use it in the current VM.
If it does not fit, we can print out a better error message and
refuse to add it, so that the VM does not die unexpectely and the
user has a second chance to plug a DIMM with a matching memory
backend instead.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1419466
Signed-off-by: Thomas Huth <thuth@redhat.com>
[dwg: Fix a build error on 32-bit builds with KVM]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 8 ++++++++
target/ppc/kvm.c | 32 ++++++++++++++++++++++++++++----
target/ppc/kvm_ppc.h | 7 +++++++
3 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 6f37288..5904e64 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2367,6 +2367,7 @@ static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
uint64_t align = memory_region_get_alignment(mr);
uint64_t size = memory_region_size(mr);
uint64_t addr;
+ char *mem_dev;
if (size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(&local_err, "Hotplugged memory size must be a multiple of "
@@ -2374,6 +2375,13 @@ static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
goto out;
}
+ mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
+ if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
+ error_setg(&local_err, "Memory backend has bad page size. "
+ "Use 'memory-backend-file' with correct mem-path.");
+ goto out;
+ }
+
pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
if (local_err) {
goto out;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 663d2e7..52bbea5 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -438,12 +438,13 @@ static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift)
return (1ul << shift) <= rampgsize;
}
+static long max_cpu_page_size;
+
static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
{
static struct kvm_ppc_smmu_info smmu_info;
static bool has_smmu_info;
CPUPPCState *env = &cpu->env;
- long rampagesize;
int iq, ik, jq, jk;
bool has_64k_pages = false;
@@ -458,7 +459,9 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
has_smmu_info = true;
}
- rampagesize = getrampagesize();
+ if (!max_cpu_page_size) {
+ max_cpu_page_size = getrampagesize();
+ }
/* Convert to QEMU form */
memset(&env->sps, 0, sizeof(env->sps));
@@ -478,14 +481,14 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
- if (!kvm_valid_page_size(smmu_info.flags, rampagesize,
+ if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
ksps->page_shift)) {
continue;
}
qsps->page_shift = ksps->page_shift;
qsps->slb_enc = ksps->slb_enc;
for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) {
- if (!kvm_valid_page_size(smmu_info.flags, rampagesize,
+ if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
ksps->enc[jk].page_shift)) {
continue;
}
@@ -510,12 +513,33 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
env->mmu_model &= ~POWERPC_MMU_64K;
}
}
+
+bool kvmppc_is_mem_backend_page_size_ok(char *obj_path)
+{
+ Object *mem_obj = object_resolve_path(obj_path, NULL);
+ char *mempath = object_property_get_str(mem_obj, "mem-path", NULL);
+ long pagesize;
+
+ if (mempath) {
+ pagesize = gethugepagesize(mempath);
+ } else {
+ pagesize = getpagesize();
+ }
+
+ return pagesize >= max_cpu_page_size;
+}
+
#else /* defined (TARGET_PPC64) */
static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu)
{
}
+bool kvmppc_is_mem_backend_page_size_ok(char *obj_path)
+{
+ return true;
+}
+
#endif /* !defined (TARGET_PPC64) */
unsigned long kvm_arch_vcpu_id(CPUState *cpu)
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index 151c00b..8da2ee4 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -60,6 +60,8 @@ int kvmppc_enable_hwrng(void);
int kvmppc_put_books_sregs(PowerPCCPU *cpu);
PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void);
+bool kvmppc_is_mem_backend_page_size_ok(char *obj_path);
+
#else
static inline uint32_t kvmppc_get_tbfreq(void)
@@ -192,6 +194,11 @@ static inline uint64_t kvmppc_rma_size(uint64_t current_size,
return ram_size;
}
+static inline bool kvmppc_is_mem_backend_page_size_ok(char *obj_path)
+{
+ return true;
+}
+
#endif /* !CONFIG_USER_ONLY */
static inline bool kvmppc_has_cap_epr(void)
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 43/43] hw/ppc/ppc405_uc.c: Avoid integer overflows
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (41 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 42/43] hw/ppc/spapr: Check for valid page size when hot plugging memory David Gibson
@ 2017-02-22 6:33 ` David Gibson
2017-02-22 7:29 ` [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 no-reply
2017-02-24 12:47 ` Peter Maydell
44 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2017-02-22 6:33 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, thuth, lvivier, qemu-devel, qemu-ppc, mdroth, imammedo,
David Gibson
From: Peter Maydell <peter.maydell@linaro.org>
When performing clock calculations, the ppc405_uc code
has several places where it multiplies together two
32-bit variables and assigns the result to a 64-bit
variable. This doesn't quite do what is intended because
C will compute a 32-bit multiply result. Add casts to
ensure we don't truncate the result.
(Spotted by Coverity, CID 1005504, 1005505.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc405_uc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6d3fc2..d5df94a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1881,7 +1881,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
M = D0 * D1 * D2;
- VCO_out = cpc->sysclk * M;
+ VCO_out = (uint64_t)cpc->sysclk * M;
if (VCO_out < 400000000 || VCO_out > 800000000) {
/* PLL cannot lock */
cpc->pllmr &= ~0x80000000;
@@ -1892,7 +1892,7 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
/* Bypass PLL */
bypass_pll:
M = D0;
- PLL_out = cpc->sysclk * M;
+ PLL_out = (uint64_t)cpc->sysclk * M;
}
CPU_clk = PLL_out;
if (cpc->cr1 & 0x00800000)
@@ -2242,7 +2242,7 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
#ifdef DEBUG_CLOCKS_LL
printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
#endif
- VCO_out = cpc->sysclk * M * D;
+ VCO_out = (uint64_t)cpc->sysclk * M * D;
if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
/* Error - unlock the PLL */
printf("VCO out of range %" PRIu64 "\n", VCO_out);
--
2.9.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (42 preceding siblings ...)
2017-02-22 6:33 ` [Qemu-devel] [PULL 43/43] hw/ppc/ppc405_uc.c: Avoid integer overflows David Gibson
@ 2017-02-22 7:29 ` no-reply
2017-02-24 12:47 ` Peter Maydell
44 siblings, 0 replies; 52+ messages in thread
From: no-reply @ 2017-02-22 7:29 UTC (permalink / raw)
To: david
Cc: famz, peter.maydell, lvivier, thuth, qemu-devel, mdroth, agraf,
qemu-ppc, imammedo
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222
Message-id: 20170222063348.32176-1-david@gibson.dropbear.id.au
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20170222063348.32176-1-david@gibson.dropbear.id.au -> patchew/20170222063348.32176-1-david@gibson.dropbear.id.au
Switched to a new branch 'test'
62d6f06 hw/ppc/ppc405_uc.c: Avoid integer overflows
ec98e40 hw/ppc/spapr: Check for valid page size when hot plugging memory
10a38a7 target-ppc: fix Book-E TLB matching
1f52e11 hw/net/spapr_llan: 6 byte mac address device tree entry
80ad17a machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag
7bd7baf machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
d340fb4 spapr: reuse machine->possible_cpus instead of cores[]
67a1cc8 change CPUArchId.cpu type to Object*
fb052cc pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object
4152831 pc: calculate topology only once when possible_cpus is initialised
23a237d pc: move pcms->possible_cpus init out of pc_cpus_init()
d15edca machine: move possible_cpus to MachineState
1bf84e1 hw/pci-host/prep: Do not use hw_error() in realize function
fa8a3dd target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
a7b4f90 target/ppc/POWER9: Adapt LPCR handling for POWER9
2be712b target/ppc/POWER9: Add ISAv3.00 MMU definition
746707a target/ppc: Fix LPCR DPFD mask define
aa25681 target-ppc: Add xscvqpudz and xscvqpuwz instructions
5716d68 target-ppc: Implement round to odd variants of quad FP instructions
d105058 softfloat: Add float128_to_uint32_round_to_zero()
c1ac9ad softfloat: Add float128_to_uint64_round_to_zero()
b4735f4 softfloat: Add round-to-odd rounding mode
42ce5b8 spapr: replace debug printf with trace points
c4ce322 ppc4xx: replace debug printf with trace points
b477c51 mac99: replace debug printf with trace points
27c4372 target-ppc, tcg: fix usermode segfault with pthread_create()
dc64bab target-ppc: add wait instruction
0dc563d target-ppc: add slbsync implementation
ca87bf1 target-ppc: add slbieg instruction
fee213a target-ppc: generate exception for copy/paste
b2fe78d target-ppc: implement store atomic instruction
ece9f14 target-ppc: implement load atomic instruction
0c8feed spapr: fix off-by-one error in spapr_ovec_populate_dt()
2d57efc target-ppc: Add xsmaxjdp and xsminjdp instructions
de589f4 target-ppc: Add xsmaxcdp and xsmincdp instructions
c1d37ae hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings
ed94562 ppc: implement xssubqp instruction
f79e29f ppc: implement xssqrtqp instruction
836021e ppc: implement xsrqpxp instruction
981bb34 ppc: implement xsrqpi[x] instruction
d11e917 spapr: make cpu core unplug follow expected hotunplug call flow
98cbd73 spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c
bcfc8b5 spapr: cpu core: separate child threads destruction from machine state operations
=== OUTPUT BEGIN ===
Checking PATCH 1/43: spapr: cpu core: separate child threads destruction from machine state operations...
Checking PATCH 2/43: spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c...
Checking PATCH 3/43: spapr: make cpu core unplug follow expected hotunplug call flow...
Checking PATCH 4/43: ppc: implement xsrqpi[x] instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#125: FILE: target/ppc/translate/vsx-ops.inc.c:106:
+#define GEN_VSX_Z23FORM_300(name, opc2, opc3, opc4, inval) \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x0, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x00, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x08, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
+GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x18, opc4 | 0x1, inval)
total: 1 errors, 0 warnings, 102 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/43: ppc: implement xsrqpxp instruction...
Checking PATCH 6/43: ppc: implement xssqrtqp instruction...
Checking PATCH 7/43: ppc: implement xssubqp instruction...
Checking PATCH 8/43: hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings...
Checking PATCH 9/43: target-ppc: Add xsmaxcdp and xsmincdp instructions...
Checking PATCH 10/43: target-ppc: Add xsmaxjdp and xsminjdp instructions...
Checking PATCH 11/43: spapr: fix off-by-one error in spapr_ovec_populate_dt()...
Checking PATCH 12/43: target-ppc: implement load atomic instruction...
Checking PATCH 13/43: target-ppc: implement store atomic instruction...
Checking PATCH 14/43: target-ppc: generate exception for copy/paste...
Checking PATCH 15/43: target-ppc: add slbieg instruction...
Checking PATCH 16/43: target-ppc: add slbsync implementation...
Checking PATCH 17/43: target-ppc: add wait instruction...
Checking PATCH 18/43: target-ppc, tcg: fix usermode segfault with pthread_create()...
Checking PATCH 19/43: mac99: replace debug printf with trace points...
Checking PATCH 20/43: ppc4xx: replace debug printf with trace points...
Checking PATCH 21/43: spapr: replace debug printf with trace points...
Checking PATCH 22/43: softfloat: Add round-to-odd rounding mode...
Checking PATCH 23/43: softfloat: Add float128_to_uint64_round_to_zero()...
Checking PATCH 24/43: softfloat: Add float128_to_uint32_round_to_zero()...
Checking PATCH 25/43: target-ppc: Implement round to odd variants of quad FP instructions...
Checking PATCH 26/43: target-ppc: Add xscvqpudz and xscvqpuwz instructions...
Checking PATCH 27/43: target/ppc: Fix LPCR DPFD mask define...
Checking PATCH 28/43: target/ppc/POWER9: Add ISAv3.00 MMU definition...
Checking PATCH 29/43: target/ppc/POWER9: Adapt LPCR handling for POWER9...
Checking PATCH 30/43: target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv...
Checking PATCH 31/43: hw/pci-host/prep: Do not use hw_error() in realize function...
Checking PATCH 32/43: machine: move possible_cpus to MachineState...
Checking PATCH 33/43: pc: move pcms->possible_cpus init out of pc_cpus_init()...
Checking PATCH 34/43: pc: calculate topology only once when possible_cpus is initialised...
Checking PATCH 35/43: pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object...
Checking PATCH 36/43: change CPUArchId.cpu type to Object*...
Checking PATCH 37/43: spapr: reuse machine->possible_cpus instead of cores[]...
ERROR: do not use C99 // comments
#266: FILE: hw/ppc/spapr.c:2826:
+ cpu_item->vcpus_count = smp_threads; // TODO: ??? generalize
total: 1 errors, 0 warnings, 258 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 38/43: machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks...
Checking PATCH 39/43: machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag...
Checking PATCH 40/43: hw/net/spapr_llan: 6 byte mac address device tree entry...
Checking PATCH 41/43: target-ppc: fix Book-E TLB matching...
Checking PATCH 42/43: hw/ppc/spapr: Check for valid page size when hot plugging memory...
Checking PATCH 43/43: hw/ppc/ppc405_uc.c: Avoid integer overflows...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCH 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-22 6:33 ` [Qemu-devel] [PULL 37/43] spapr: reuse machine->possible_cpus instead of cores[] David Gibson
@ 2017-02-22 11:05 ` Igor Mammedov
2017-02-24 13:03 ` David Gibson
0 siblings, 1 reply; 52+ messages in thread
From: Igor Mammedov @ 2017-02-22 11:05 UTC (permalink / raw)
To: qemu-devel
Cc: agraf, thuth, lvivier, qemu-ppc, mdroth, David Gibson, peter.maydell
Replace SPAPR specific cores[] array with generic
machine->possible_cpus and store core objects there.
It makes cores bookkeeping similar to x86 cpus and
will allow to unify similar code.
It would allow to replace cpu_index based NUMA node
mapping with property based one (for -device created
cores) since possible_cpus carries board defined
topology/layout.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
v3:
- drop "// TODO" comment as todo is completed in next patch anyway
fixes checkpatch error wrt // comment
v2:
- remove extra ';' at the end of expression (David Gibson)
---
include/hw/ppc/spapr.h | 1 -
hw/ppc/spapr.c | 127 ++++++++++++++++++++++++++++++++++---------------
2 files changed, 89 insertions(+), 39 deletions(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index a2d8964..f9b17d8 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -94,7 +94,6 @@ struct sPAPRMachineState {
/*< public >*/
char *kvm_type;
MemoryHotplugState hotplug_memory;
- Object **cores;
};
#define H_SUCCESS 0
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 37cb338..735f53d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1751,13 +1751,28 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
}
}
+/* find cpu slot in machine->possible_cpus by core_id */
+static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
+{
+ int index = id / smp_threads;
+
+ if (index >= ms->possible_cpus->len) {
+ return NULL;
+ }
+ if (idx) {
+ *idx = index;
+ }
+ return &ms->possible_cpus->cpus[index];
+}
+
static void spapr_init_cpus(sPAPRMachineState *spapr)
{
MachineState *machine = MACHINE(spapr);
MachineClass *mc = MACHINE_GET_CLASS(machine);
char *type = spapr_get_cpu_core_type(machine->cpu_model);
int smt = kvmppc_smt_threads();
- int spapr_max_cores, spapr_cores;
+ const CPUArchIdList *possible_cpus;
+ int boot_cores_nr = smp_cpus / smp_threads;
int i;
if (!type) {
@@ -1765,6 +1780,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
exit(1);
}
+ possible_cpus = mc->possible_cpu_arch_ids(machine);
if (mc->query_hotpluggable_cpus) {
if (smp_cpus % smp_threads) {
error_report("smp_cpus (%u) must be multiple of threads (%u)",
@@ -1776,21 +1792,15 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
max_cpus, smp_threads);
exit(1);
}
-
- spapr_max_cores = max_cpus / smp_threads;
- spapr_cores = smp_cpus / smp_threads;
} else {
if (max_cpus != smp_cpus) {
error_report("This machine version does not support CPU hotplug");
exit(1);
}
-
- spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
- spapr_cores = spapr_max_cores;
+ boot_cores_nr = possible_cpus->len;
}
- spapr->cores = g_new0(Object *, spapr_max_cores);
- for (i = 0; i < spapr_max_cores; i++) {
+ for (i = 0; i < possible_cpus->len; i++) {
int core_id = i * smp_threads;
if (mc->query_hotpluggable_cpus) {
@@ -1802,7 +1812,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
qemu_register_reset(spapr_drc_reset, drc);
}
- if (i < spapr_cores) {
+ if (i < boot_cores_nr) {
Object *core = object_new(type);
int nr_threads = smp_threads;
@@ -2491,10 +2501,11 @@ void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ MachineState *ms = MACHINE(qdev_get_machine());
CPUCore *cc = CPU_CORE(dev);
+ CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
- spapr->cores[cc->core_id / smp_threads] = NULL;
+ core_slot->cpu = NULL;
object_unparent(OBJECT(dev));
}
@@ -2510,19 +2521,24 @@ static
void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- CPUCore *cc = CPU_CORE(dev);
- int smt = kvmppc_smt_threads();
- int index = cc->core_id / smp_threads;
- sPAPRDRConnector *drc =
- spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
+ int index;
+ sPAPRDRConnector *drc;
sPAPRDRConnectorClass *drck;
Error *local_err = NULL;
+ CPUCore *cc = CPU_CORE(dev);
+ int smt = kvmppc_smt_threads();
+ if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
+ error_setg(errp, "Unable to find CPU core with core-id: %d",
+ cc->core_id);
+ return;
+ }
if (index == 0) {
error_setg(errp, "Boot CPU core may not be unplugged");
return;
}
+ drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
g_assert(drc);
drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
@@ -2547,11 +2563,17 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error *local_err = NULL;
void *fdt = NULL;
int fdt_offset = 0;
- int index = cc->core_id / smp_threads;
int smt = kvmppc_smt_threads();
+ CPUArchId *core_slot;
+ int index;
+ core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
+ if (!core_slot) {
+ error_setg(errp, "Unable to find CPU core with core-id: %d",
+ cc->core_id);
+ return;
+ }
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
- spapr->cores[index] = OBJECT(dev);
g_assert(drc || !mc->query_hotpluggable_cpus);
@@ -2568,7 +2590,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
if (local_err) {
g_free(fdt);
- spapr->cores[index] = NULL;
error_propagate(errp, local_err);
return;
}
@@ -2590,6 +2611,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
}
}
+ core_slot->cpu = OBJECT(dev);
}
static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -2597,13 +2619,12 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
{
MachineState *machine = MACHINE(OBJECT(hotplug_dev));
MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
- sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
- int spapr_max_cores = max_cpus / smp_threads;
- int index;
Error *local_err = NULL;
CPUCore *cc = CPU_CORE(dev);
char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
const char *type = object_get_typename(OBJECT(dev));
+ CPUArchId *core_slot;
+ int index;
if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
error_setg(&local_err, "CPU hotplug not supported for this machine");
@@ -2620,13 +2641,13 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
goto out;
}
- index = cc->core_id / smp_threads;
- if (index < 0 || index >= spapr_max_cores) {
+ core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
+ if (!core_slot) {
error_setg(&local_err, "core id %d out of range", cc->core_id);
goto out;
}
- if (spapr->cores[index]) {
+ if (core_slot->cpu) {
error_setg(&local_err, "core %d already populated", cc->core_id);
goto out;
}
@@ -2758,29 +2779,58 @@ static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
return cpu_index / smp_threads / smp_cores;
}
+static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
+{
+ int i;
+ int spapr_max_cores = max_cpus / smp_threads;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (!mc->query_hotpluggable_cpus) {
+ spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
+ }
+ if (machine->possible_cpus) {
+ assert(machine->possible_cpus->len == spapr_max_cores);
+ return machine->possible_cpus;
+ }
+
+ machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+ sizeof(CPUArchId) * spapr_max_cores);
+ machine->possible_cpus->len = spapr_max_cores;
+ for (i = 0; i < machine->possible_cpus->len; i++) {
+ int core_id = i * smp_threads;
+
+ machine->possible_cpus->cpus[i].arch_id = core_id;
+ machine->possible_cpus->cpus[i].props.has_core_id = true;
+ machine->possible_cpus->cpus[i].props.core_id = core_id;
+ /* TODO: add 'has_node/node' here to describe
+ to which node core belongs */
+ }
+ return machine->possible_cpus;
+}
+
static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
{
int i;
+ Object *cpu;
HotpluggableCPUList *head = NULL;
- sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
- int spapr_max_cores = max_cpus / smp_threads;
+ const char *cpu_type;
- for (i = 0; i < spapr_max_cores; i++) {
+ cpu = machine->possible_cpus->cpus[0].cpu;
+ assert(cpu); /* Boot cpu is always present */
+ cpu_type = object_get_typename(cpu);
+ for (i = 0; i < machine->possible_cpus->len; i++) {
HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
- CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
- cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
+ cpu_item->type = g_strdup(cpu_type);
cpu_item->vcpus_count = smp_threads;
- cpu_props->has_core_id = true;
- cpu_props->core_id = i * smp_threads;
- /* TODO: add 'has_node/node' here to describe
- to which node core belongs */
+ cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
+ sizeof(*cpu_item->props));
- cpu_item->props = cpu_props;
- if (spapr->cores[i]) {
+ cpu = machine->possible_cpus->cpus[i].cpu;
+ if (cpu) {
cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
+ cpu_item->qom_path = object_get_canonical_path(cpu);
}
list_item->value = cpu_item;
list_item->next = head;
@@ -2872,6 +2922,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
hc->plug = spapr_machine_device_plug;
hc->unplug = spapr_machine_device_unplug;
mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
+ mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
hc->unplug_request = spapr_machine_device_unplug_request;
smc->dr_lmb_enabled = true;
--
2.7.4
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PATCH 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
2017-02-22 6:33 ` [Qemu-devel] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks David Gibson
@ 2017-02-22 11:07 ` Igor Mammedov
0 siblings, 0 replies; 52+ messages in thread
From: Igor Mammedov @ 2017-02-22 11:07 UTC (permalink / raw)
To: qemu-devel
Cc: agraf, thuth, lvivier, qemu-ppc, mdroth, David Gibson, peter.maydell
All callbacks FOO_query_hotpluggable_cpus() are practically
the same except of setting vcpus_count to different values.
Convert them to a generic machine_query_hotpluggable_cpus()
callback by moving vcpus_count initialization to per machine
specific callback possible_cpu_arch_ids().
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
v2:
- fix rebase conflict due to dropping comment in previous
patch
---
include/hw/boards.h | 3 +++
hw/core/machine.c | 31 +++++++++++++++++++++++++++++++
hw/i386/pc.c | 36 ++----------------------------------
hw/ppc/spapr.c | 34 ++--------------------------------
4 files changed, 38 insertions(+), 66 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 60209df..9040dbb 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -41,15 +41,18 @@ int machine_phandle_start(MachineState *machine);
bool machine_dump_guest_core(MachineState *machine);
bool machine_mem_merge(MachineState *machine);
void machine_register_compat_props(MachineState *machine);
+HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine);
/**
* CPUArchId:
* @arch_id - architecture-dependent CPU ID of present or possible CPU
* @cpu - pointer to corresponding CPU object if it's present on NULL otherwise
* @props - CPU object properties, initialized by board
+ * #vcpus_count - number of threads provided by @cpu object
*/
typedef struct {
uint64_t arch_id;
+ int64_t vcpus_count;
CpuInstanceProperties props;
Object *cpu;
} CPUArchId;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index b0fd91f..0699750 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -357,6 +357,37 @@ static void machine_init_notify(Notifier *notifier, void *data)
foreach_dynamic_sysbus_device(error_on_sysbus_device, NULL);
}
+HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
+{
+ int i;
+ Object *cpu;
+ HotpluggableCPUList *head = NULL;
+ const char *cpu_type;
+
+ cpu = machine->possible_cpus->cpus[0].cpu;
+ assert(cpu); /* Boot cpu is always present */
+ cpu_type = object_get_typename(cpu);
+ for (i = 0; i < machine->possible_cpus->len; i++) {
+ HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
+ HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
+
+ cpu_item->type = g_strdup(cpu_type);
+ cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
+ cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
+ sizeof(*cpu_item->props));
+
+ cpu = machine->possible_cpus->cpus[i].cpu;
+ if (cpu) {
+ cpu_item->has_qom_path = true;
+ cpu_item->qom_path = object_get_canonical_path(cpu);
+ }
+ list_item->value = cpu_item;
+ list_item->next = head;
+ head = list_item;
+ }
+ return head;
+}
+
static void machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index afaae15..548628f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2266,6 +2266,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
for (i = 0; i < ms->possible_cpus->len; i++) {
X86CPUTopoInfo topo;
+ ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
smp_cores, smp_threads, &topo);
@@ -2279,39 +2280,6 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
return ms->possible_cpus;
}
-static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine)
-{
- int i;
- Object *cpu;
- HotpluggableCPUList *head = NULL;
- const char *cpu_type;
-
- cpu = machine->possible_cpus->cpus[0].cpu;
- assert(cpu); /* BSP is always present */
- cpu_type = object_get_typename(cpu);
-
- for (i = 0; i < machine->possible_cpus->len; i++) {
- HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
- HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
-
- cpu_item->type = g_strdup(cpu_type);
- cpu_item->vcpus_count = 1;
- cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
- sizeof(*cpu_item->props));
-
- cpu = machine->possible_cpus->cpus[i].cpu;
- if (cpu) {
- cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(cpu);
- }
-
- list_item->value = cpu_item;
- list_item->next = head;
- head = list_item;
- }
- return head;
-}
-
static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
{
/* cpu index isn't used */
@@ -2352,7 +2320,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->get_hotplug_handler = pc_get_hotpug_handler;
mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id;
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
- mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus;
+ mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
mc->default_boot_order = "cad";
mc->hot_add_cpu = pc_hot_add_cpu;
mc->max_cpus = 255;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 735f53d..49768eb 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2799,6 +2799,7 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
for (i = 0; i < machine->possible_cpus->len; i++) {
int core_id = i * smp_threads;
+ machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
machine->possible_cpus->cpus[i].arch_id = core_id;
machine->possible_cpus->cpus[i].props.has_core_id = true;
machine->possible_cpus->cpus[i].props.core_id = core_id;
@@ -2808,37 +2809,6 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
return machine->possible_cpus;
}
-static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
-{
- int i;
- Object *cpu;
- HotpluggableCPUList *head = NULL;
- const char *cpu_type;
-
- cpu = machine->possible_cpus->cpus[0].cpu;
- assert(cpu); /* Boot cpu is always present */
- cpu_type = object_get_typename(cpu);
- for (i = 0; i < machine->possible_cpus->len; i++) {
- HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
- HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
-
- cpu_item->type = g_strdup(cpu_type);
- cpu_item->vcpus_count = smp_threads;
- cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
- sizeof(*cpu_item->props));
-
- cpu = machine->possible_cpus->cpus[i].cpu;
- if (cpu) {
- cpu_item->has_qom_path = true;
- cpu_item->qom_path = object_get_canonical_path(cpu);
- }
- list_item->value = cpu_item;
- list_item->next = head;
- head = list_item;
- }
- return head;
-}
-
static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
uint64_t *buid, hwaddr *pio,
hwaddr *mmio32, hwaddr *mmio64,
@@ -2927,7 +2897,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->dr_lmb_enabled = true;
smc->tcg_default_cpu = "POWER8";
- mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
+ mc->query_hotpluggable_cpus = machine_query_hotpluggable_cpus;
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
--
2.7.4
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
` (43 preceding siblings ...)
2017-02-22 7:29 ` [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 no-reply
@ 2017-02-24 12:47 ` Peter Maydell
44 siblings, 0 replies; 52+ messages in thread
From: Peter Maydell @ 2017-02-24 12:47 UTC (permalink / raw)
To: David Gibson
Cc: Alexander Graf, Thomas Huth, Laurent Vivier, QEMU Developers,
qemu-ppc, Michael Roth, Igor Mammedov
On 22 February 2017 at 06:33, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit 796b288f7be875045670f963ce99991b3c8e96ac:
>
> Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging (2017-02-21 15:48:22 +0000)
>
> are available in the git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170222
>
> for you to fetch changes up to fb6971c110387cf597b58c411658e3d15cc6c6fb:
>
> hw/ppc/ppc405_uc.c: Avoid integer overflows (2017-02-22 14:28:53 +1100)
>
> NOTE: This pull request hasn't passed the full set of tests I usually
> run, because there seem to be problems with those on current master
> anyway: some of "make check" seems to wedge, and a number of travis
> builds timed out. AFAICT this series doesn't cause any failures that
> aren't already present in upstream.
>
> ----------------------------------------------------------------
> ppc patch queue for 2017-02-22
>
> This pull request has:
> * Yet more POWER9 instruction implementations
> * Some extensions to the softfloat code which are necesssary for
> some of those instructions
> * Some preliminary patches in preparation for POWER9 softmmu
> implementation
> * Igor Mammedov's cleanups to unify hotplug cpu handling across
> architectures
> * Assorted bugfixes
>
> The softfloat and cpu hotplug changes aren't entirely ppc specific (in
> fact the hotplug stuff contains some pc specific patches). However
> they're included here because ppc is one of the main beneficiaries,
> and the series depend on some ppc specific patches.
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-22 11:05 ` [Qemu-devel] [PATCH " Igor Mammedov
@ 2017-02-24 13:03 ` David Gibson
2017-02-24 13:29 ` Igor Mammedov
0 siblings, 1 reply; 52+ messages in thread
From: David Gibson @ 2017-02-24 13:03 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, agraf, thuth, lvivier, qemu-ppc, mdroth, peter.maydell
[-- Attachment #1: Type: text/plain, Size: 12541 bytes --]
On Wed, Feb 22, 2017 at 12:05:55PM +0100, Igor Mammedov wrote:
> Replace SPAPR specific cores[] array with generic
> machine->possible_cpus and store core objects there.
> It makes cores bookkeeping similar to x86 cpus and
> will allow to unify similar code.
> It would allow to replace cpu_index based NUMA node
> mapping with property based one (for -device created
> cores) since possible_cpus carries board defined
> topology/layout.
>
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> Acked-by: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Sorry Igor, Peter has applied the original version. Can you resend
these updates as deltas against the applied versions of the patches.
> ---
> v3:
> - drop "// TODO" comment as todo is completed in next patch anyway
> fixes checkpatch error wrt // comment
> v2:
> - remove extra ';' at the end of expression (David Gibson)
> ---
> include/hw/ppc/spapr.h | 1 -
> hw/ppc/spapr.c | 127 ++++++++++++++++++++++++++++++++++---------------
> 2 files changed, 89 insertions(+), 39 deletions(-)
>
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index a2d8964..f9b17d8 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -94,7 +94,6 @@ struct sPAPRMachineState {
> /*< public >*/
> char *kvm_type;
> MemoryHotplugState hotplug_memory;
> - Object **cores;
> };
>
> #define H_SUCCESS 0
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 37cb338..735f53d 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1751,13 +1751,28 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
> }
> }
>
> +/* find cpu slot in machine->possible_cpus by core_id */
> +static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
> +{
> + int index = id / smp_threads;
> +
> + if (index >= ms->possible_cpus->len) {
> + return NULL;
> + }
> + if (idx) {
> + *idx = index;
> + }
> + return &ms->possible_cpus->cpus[index];
> +}
> +
> static void spapr_init_cpus(sPAPRMachineState *spapr)
> {
> MachineState *machine = MACHINE(spapr);
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> char *type = spapr_get_cpu_core_type(machine->cpu_model);
> int smt = kvmppc_smt_threads();
> - int spapr_max_cores, spapr_cores;
> + const CPUArchIdList *possible_cpus;
> + int boot_cores_nr = smp_cpus / smp_threads;
> int i;
>
> if (!type) {
> @@ -1765,6 +1780,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
> exit(1);
> }
>
> + possible_cpus = mc->possible_cpu_arch_ids(machine);
> if (mc->query_hotpluggable_cpus) {
> if (smp_cpus % smp_threads) {
> error_report("smp_cpus (%u) must be multiple of threads (%u)",
> @@ -1776,21 +1792,15 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
> max_cpus, smp_threads);
> exit(1);
> }
> -
> - spapr_max_cores = max_cpus / smp_threads;
> - spapr_cores = smp_cpus / smp_threads;
> } else {
> if (max_cpus != smp_cpus) {
> error_report("This machine version does not support CPU hotplug");
> exit(1);
> }
> -
> - spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
> - spapr_cores = spapr_max_cores;
> + boot_cores_nr = possible_cpus->len;
> }
>
> - spapr->cores = g_new0(Object *, spapr_max_cores);
> - for (i = 0; i < spapr_max_cores; i++) {
> + for (i = 0; i < possible_cpus->len; i++) {
> int core_id = i * smp_threads;
>
> if (mc->query_hotpluggable_cpus) {
> @@ -1802,7 +1812,7 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)
> qemu_register_reset(spapr_drc_reset, drc);
> }
>
> - if (i < spapr_cores) {
> + if (i < boot_cores_nr) {
> Object *core = object_new(type);
> int nr_threads = smp_threads;
>
> @@ -2491,10 +2501,11 @@ void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
> static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
> Error **errp)
> {
> - sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
> + MachineState *ms = MACHINE(qdev_get_machine());
> CPUCore *cc = CPU_CORE(dev);
> + CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
>
> - spapr->cores[cc->core_id / smp_threads] = NULL;
> + core_slot->cpu = NULL;
> object_unparent(OBJECT(dev));
> }
>
> @@ -2510,19 +2521,24 @@ static
> void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
> Error **errp)
> {
> - CPUCore *cc = CPU_CORE(dev);
> - int smt = kvmppc_smt_threads();
> - int index = cc->core_id / smp_threads;
> - sPAPRDRConnector *drc =
> - spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
> + int index;
> + sPAPRDRConnector *drc;
> sPAPRDRConnectorClass *drck;
> Error *local_err = NULL;
> + CPUCore *cc = CPU_CORE(dev);
> + int smt = kvmppc_smt_threads();
>
> + if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
> + error_setg(errp, "Unable to find CPU core with core-id: %d",
> + cc->core_id);
> + return;
> + }
> if (index == 0) {
> error_setg(errp, "Boot CPU core may not be unplugged");
> return;
> }
>
> + drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
> g_assert(drc);
>
> drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
> @@ -2547,11 +2563,17 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> Error *local_err = NULL;
> void *fdt = NULL;
> int fdt_offset = 0;
> - int index = cc->core_id / smp_threads;
> int smt = kvmppc_smt_threads();
> + CPUArchId *core_slot;
> + int index;
>
> + core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
> + if (!core_slot) {
> + error_setg(errp, "Unable to find CPU core with core-id: %d",
> + cc->core_id);
> + return;
> + }
> drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
> - spapr->cores[index] = OBJECT(dev);
>
> g_assert(drc || !mc->query_hotpluggable_cpus);
>
> @@ -2568,7 +2590,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
> if (local_err) {
> g_free(fdt);
> - spapr->cores[index] = NULL;
> error_propagate(errp, local_err);
> return;
> }
> @@ -2590,6 +2611,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
> }
> }
> + core_slot->cpu = OBJECT(dev);
> }
>
> static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> @@ -2597,13 +2619,12 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> {
> MachineState *machine = MACHINE(OBJECT(hotplug_dev));
> MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
> - sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
> - int spapr_max_cores = max_cpus / smp_threads;
> - int index;
> Error *local_err = NULL;
> CPUCore *cc = CPU_CORE(dev);
> char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
> const char *type = object_get_typename(OBJECT(dev));
> + CPUArchId *core_slot;
> + int index;
>
> if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
> error_setg(&local_err, "CPU hotplug not supported for this machine");
> @@ -2620,13 +2641,13 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
> goto out;
> }
>
> - index = cc->core_id / smp_threads;
> - if (index < 0 || index >= spapr_max_cores) {
> + core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
> + if (!core_slot) {
> error_setg(&local_err, "core id %d out of range", cc->core_id);
> goto out;
> }
>
> - if (spapr->cores[index]) {
> + if (core_slot->cpu) {
> error_setg(&local_err, "core %d already populated", cc->core_id);
> goto out;
> }
> @@ -2758,29 +2779,58 @@ static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
> return cpu_index / smp_threads / smp_cores;
> }
>
> +static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
> +{
> + int i;
> + int spapr_max_cores = max_cpus / smp_threads;
> + MachineClass *mc = MACHINE_GET_CLASS(machine);
> +
> + if (!mc->query_hotpluggable_cpus) {
> + spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
> + }
> + if (machine->possible_cpus) {
> + assert(machine->possible_cpus->len == spapr_max_cores);
> + return machine->possible_cpus;
> + }
> +
> + machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
> + sizeof(CPUArchId) * spapr_max_cores);
> + machine->possible_cpus->len = spapr_max_cores;
> + for (i = 0; i < machine->possible_cpus->len; i++) {
> + int core_id = i * smp_threads;
> +
> + machine->possible_cpus->cpus[i].arch_id = core_id;
> + machine->possible_cpus->cpus[i].props.has_core_id = true;
> + machine->possible_cpus->cpus[i].props.core_id = core_id;
> + /* TODO: add 'has_node/node' here to describe
> + to which node core belongs */
> + }
> + return machine->possible_cpus;
> +}
> +
> static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
> {
> int i;
> + Object *cpu;
> HotpluggableCPUList *head = NULL;
> - sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
> - int spapr_max_cores = max_cpus / smp_threads;
> + const char *cpu_type;
>
> - for (i = 0; i < spapr_max_cores; i++) {
> + cpu = machine->possible_cpus->cpus[0].cpu;
> + assert(cpu); /* Boot cpu is always present */
> + cpu_type = object_get_typename(cpu);
> + for (i = 0; i < machine->possible_cpus->len; i++) {
> HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
> HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
> - CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
>
> - cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
> + cpu_item->type = g_strdup(cpu_type);
> cpu_item->vcpus_count = smp_threads;
> - cpu_props->has_core_id = true;
> - cpu_props->core_id = i * smp_threads;
> - /* TODO: add 'has_node/node' here to describe
> - to which node core belongs */
> + cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
> + sizeof(*cpu_item->props));
>
> - cpu_item->props = cpu_props;
> - if (spapr->cores[i]) {
> + cpu = machine->possible_cpus->cpus[i].cpu;
> + if (cpu) {
> cpu_item->has_qom_path = true;
> - cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
> + cpu_item->qom_path = object_get_canonical_path(cpu);
> }
> list_item->value = cpu_item;
> list_item->next = head;
> @@ -2872,6 +2922,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
> hc->plug = spapr_machine_device_plug;
> hc->unplug = spapr_machine_device_unplug;
> mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
> + mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
> hc->unplug_request = spapr_machine_device_unplug_request;
>
> smc->dr_lmb_enabled = true;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-24 13:03 ` David Gibson
@ 2017-02-24 13:29 ` Igor Mammedov
2017-02-26 22:46 ` David Gibson
0 siblings, 1 reply; 52+ messages in thread
From: Igor Mammedov @ 2017-02-24 13:29 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, agraf, thuth, lvivier, qemu-ppc, mdroth, peter.maydell
On Sat, 25 Feb 2017 00:03:57 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Wed, Feb 22, 2017 at 12:05:55PM +0100, Igor Mammedov wrote:
> > Replace SPAPR specific cores[] array with generic
> > machine->possible_cpus and store core objects there.
> > It makes cores bookkeeping similar to x86 cpus and
> > will allow to unify similar code.
> > It would allow to replace cpu_index based NUMA node
> > mapping with property based one (for -device created
> > cores) since possible_cpus carries board defined
> > topology/layout.
> >
> > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> > Acked-by: David Gibson <david@gibson.dropbear.id.au>
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>
> Sorry Igor, Peter has applied the original version. Can you resend
> these updates as deltas against the applied versions of the patches.
>
> > ---
> > v3:
> > - drop "// TODO" comment as todo is completed in next patch anyway
> > fixes checkpatch error wrt // comment
there is no need for patches on top as the next applied patch
38/43 removed c++ style comment as part of removed
spapr_query_hotpluggable_cpus().
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-24 13:29 ` Igor Mammedov
@ 2017-02-26 22:46 ` David Gibson
2017-02-27 12:41 ` Igor Mammedov
0 siblings, 1 reply; 52+ messages in thread
From: David Gibson @ 2017-02-26 22:46 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, agraf, thuth, lvivier, qemu-ppc, mdroth, peter.maydell
[-- Attachment #1: Type: text/plain, Size: 1560 bytes --]
On Fri, Feb 24, 2017 at 02:29:21PM +0100, Igor Mammedov wrote:
> On Sat, 25 Feb 2017 00:03:57 +1100
> David Gibson <david@gibson.dropbear.id.au> wrote:
>
> > On Wed, Feb 22, 2017 at 12:05:55PM +0100, Igor Mammedov wrote:
> > > Replace SPAPR specific cores[] array with generic
> > > machine->possible_cpus and store core objects there.
> > > It makes cores bookkeeping similar to x86 cpus and
> > > will allow to unify similar code.
> > > It would allow to replace cpu_index based NUMA node
> > > mapping with property based one (for -device created
> > > cores) since possible_cpus carries board defined
> > > topology/layout.
> > >
> > > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> > > Acked-by: David Gibson <david@gibson.dropbear.id.au>
> > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >
> > Sorry Igor, Peter has applied the original version. Can you resend
> > these updates as deltas against the applied versions of the patches.
> >
> > > ---
> > > v3:
> > > - drop "// TODO" comment as todo is completed in next patch anyway
> > > fixes checkpatch error wrt // comment
> there is no need for patches on top as the next applied patch
> 38/43 removed c++ style comment as part of removed
> spapr_query_hotpluggable_cpus().
Ok, good to hear. What about the other update patch you posted?
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PATCH 37/43] spapr: reuse machine->possible_cpus instead of cores[]
2017-02-26 22:46 ` David Gibson
@ 2017-02-27 12:41 ` Igor Mammedov
0 siblings, 0 replies; 52+ messages in thread
From: Igor Mammedov @ 2017-02-27 12:41 UTC (permalink / raw)
To: David Gibson
Cc: qemu-devel, agraf, thuth, lvivier, qemu-ppc, mdroth, peter.maydell
On Mon, 27 Feb 2017 09:46:43 +1100
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Fri, Feb 24, 2017 at 02:29:21PM +0100, Igor Mammedov wrote:
> > On Sat, 25 Feb 2017 00:03:57 +1100
> > David Gibson <david@gibson.dropbear.id.au> wrote:
> >
> > > On Wed, Feb 22, 2017 at 12:05:55PM +0100, Igor Mammedov wrote:
> > > > Replace SPAPR specific cores[] array with generic
> > > > machine->possible_cpus and store core objects there.
> > > > It makes cores bookkeeping similar to x86 cpus and
> > > > will allow to unify similar code.
> > > > It would allow to replace cpu_index based NUMA node
> > > > mapping with property based one (for -device created
> > > > cores) since possible_cpus carries board defined
> > > > topology/layout.
> > > >
> > > > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> > > > Acked-by: David Gibson <david@gibson.dropbear.id.au>
> > > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > >
> > > Sorry Igor, Peter has applied the original version. Can you resend
> > > these updates as deltas against the applied versions of the patches.
> > >
> > > > ---
> > > > v3:
> > > > - drop "// TODO" comment as todo is completed in next patch anyway
> > > > fixes checkpatch error wrt // comment
> > there is no need for patches on top as the next applied patch
> > 38/43 removed c++ style comment as part of removed
> > spapr_query_hotpluggable_cpus().
>
> Ok, good to hear. What about the other update patch you posted?
that was posted as addition to this patch to fix merge conflict
due to removal of TODO comment here, so ignore it as well.
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2017-02-27 12:42 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-22 6:33 [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 04/43] ppc: implement xsrqpi[x] instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 05/43] ppc: implement xsrqpxp instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 06/43] ppc: implement xssqrtqp instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 07/43] ppc: implement xssubqp instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 08/43] hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt() David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 12/43] target-ppc: implement load atomic instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 13/43] target-ppc: implement store " David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 14/43] target-ppc: generate exception for copy/paste David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 15/43] target-ppc: add slbieg instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 16/43] target-ppc: add slbsync implementation David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 17/43] target-ppc: add wait instruction David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 18/43] target-ppc, tcg: fix usermode segfault with pthread_create() David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 19/43] mac99: replace debug printf with trace points David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 20/43] ppc4xx: " David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 21/43] spapr: " David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 22/43] softfloat: Add round-to-odd rounding mode David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero() David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero() David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 25/43] target-ppc: Implement round to odd variants of quad FP instructions David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 29/43] target/ppc/POWER9: Adapt LPCR handling for POWER9 David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 32/43] machine: move possible_cpus to MachineState David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 33/43] pc: move pcms->possible_cpus init out of pc_cpus_init() David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 34/43] pc: calculate topology only once when possible_cpus is initialised David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 36/43] change CPUArchId.cpu type to Object* David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 37/43] spapr: reuse machine->possible_cpus instead of cores[] David Gibson
2017-02-22 11:05 ` [Qemu-devel] [PATCH " Igor Mammedov
2017-02-24 13:03 ` David Gibson
2017-02-24 13:29 ` Igor Mammedov
2017-02-26 22:46 ` David Gibson
2017-02-27 12:41 ` Igor Mammedov
2017-02-22 6:33 ` [Qemu-devel] [PULL 38/43] machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks David Gibson
2017-02-22 11:07 ` [Qemu-devel] [PATCH " Igor Mammedov
2017-02-22 6:33 ` [Qemu-devel] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 40/43] hw/net/spapr_llan: 6 byte mac address device tree entry David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 41/43] target-ppc: fix Book-E TLB matching David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 42/43] hw/ppc/spapr: Check for valid page size when hot plugging memory David Gibson
2017-02-22 6:33 ` [Qemu-devel] [PULL 43/43] hw/ppc/ppc405_uc.c: Avoid integer overflows David Gibson
2017-02-22 7:29 ` [Qemu-devel] [PULL 00/43] ppc-for-2.9 queue 20170222 no-reply
2017-02-24 12:47 ` Peter Maydell
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