* [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table
@ 2017-02-23 17:35 ville.syrjala
2017-02-23 17:35 ` [PATCH 2/3] drm/i915: Refactor translate_signal_level() ville.syrjala
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: ville.syrjala @ 2017-02-23 17:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the code to select the correct trasnslation table into DP,
eDP and FDI specific helpers. This reduces the clutter in
intel_prepare_dp_ddi_buffers(), and we'll have other uses for some
of these new helper functions later on.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 126 +++++++++++++++++++++++----------------
1 file changed, 73 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd6fedd229a0..5e4b0172810d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -468,6 +468,59 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
return hdmi_level;
}
+static const struct ddi_buf_trans *
+intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
+ int *n_entries)
+{
+ if (IS_KABYLAKE(dev_priv)) {
+ return kbl_get_buf_trans_dp(dev_priv, n_entries);
+ } else if (IS_SKYLAKE(dev_priv)) {
+ return skl_get_buf_trans_dp(dev_priv, n_entries);
+ } else if (IS_BROADWELL(dev_priv)) {
+ *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
+ return bdw_ddi_translations_dp;
+ } else if (IS_HASWELL(dev_priv)) {
+ *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
+ return hsw_ddi_translations_dp;
+ }
+
+ *n_entries = 0;
+ return NULL;
+}
+
+static const struct ddi_buf_trans *
+intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
+ int *n_entries)
+{
+ if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
+ return skl_get_buf_trans_edp(dev_priv, n_entries);
+ } else if (IS_BROADWELL(dev_priv)) {
+ return bdw_get_buf_trans_edp(dev_priv, n_entries);
+ } else if (IS_HASWELL(dev_priv)) {
+ *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
+ return hsw_ddi_translations_dp;
+ }
+
+ *n_entries = 0;
+ return NULL;
+}
+
+static const struct ddi_buf_trans *
+intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
+ int *n_entries)
+{
+ if (IS_BROADWELL(dev_priv)) {
+ *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
+ return hsw_ddi_translations_fdi;
+ } else if (IS_HASWELL(dev_priv)) {
+ *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
+ return hsw_ddi_translations_fdi;
+ }
+
+ *n_entries = 0;
+ return NULL;
+}
+
/*
* Starting with Haswell, DDI port buffers must be programmed with correct
* values in advance. This function programs the correct values for
@@ -477,45 +530,29 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 iboost_bit = 0;
- int i, n_dp_entries, n_edp_entries, size;
+ int i, n_entries;
enum port port = intel_ddi_get_encoder_port(encoder);
- const struct ddi_buf_trans *ddi_translations_fdi;
- const struct ddi_buf_trans *ddi_translations_dp;
- const struct ddi_buf_trans *ddi_translations_edp;
const struct ddi_buf_trans *ddi_translations;
if (IS_GEN9_LP(dev_priv))
return;
- if (IS_KABYLAKE(dev_priv)) {
- ddi_translations_fdi = NULL;
- ddi_translations_dp =
- kbl_get_buf_trans_dp(dev_priv, &n_dp_entries);
- ddi_translations_edp =
- skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
- } else if (IS_SKYLAKE(dev_priv)) {
- ddi_translations_fdi = NULL;
- ddi_translations_dp =
- skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
- ddi_translations_edp =
- skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
- } else if (IS_BROADWELL(dev_priv)) {
- ddi_translations_fdi = bdw_ddi_translations_fdi;
- ddi_translations_dp = bdw_ddi_translations_dp;
- ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
- n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
- } else if (IS_HASWELL(dev_priv)) {
- ddi_translations_fdi = hsw_ddi_translations_fdi;
- ddi_translations_dp = hsw_ddi_translations_dp;
- ddi_translations_edp = hsw_ddi_translations_dp;
- n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
- } else {
- WARN(1, "ddi translation table missing\n");
- ddi_translations_edp = bdw_ddi_translations_dp;
- ddi_translations_fdi = bdw_ddi_translations_fdi;
- ddi_translations_dp = bdw_ddi_translations_dp;
- n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
- n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
+ switch (encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
+ &n_entries);
+ break;
+ case INTEL_OUTPUT_DP:
+ ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
+ &n_entries);
+ break;
+ case INTEL_OUTPUT_ANALOG:
+ ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
+ &n_entries);
+ break;
+ default:
+ MISSING_CASE(encoder->type);
+ return;
}
if (IS_GEN9_BC(dev_priv)) {
@@ -525,28 +562,11 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
port != PORT_A && port != PORT_E &&
- n_edp_entries > 9))
- n_edp_entries = 9;
- }
-
- switch (encoder->type) {
- case INTEL_OUTPUT_EDP:
- ddi_translations = ddi_translations_edp;
- size = n_edp_entries;
- break;
- case INTEL_OUTPUT_DP:
- ddi_translations = ddi_translations_dp;
- size = n_dp_entries;
- break;
- case INTEL_OUTPUT_ANALOG:
- ddi_translations = ddi_translations_fdi;
- size = n_dp_entries;
- break;
- default:
- BUG();
+ n_entries > 9))
+ n_entries = 9;
}
- for (i = 0; i < size; i++) {
+ for (i = 0; i < n_entries; i++) {
I915_WRITE(DDI_BUF_TRANS_LO(port, i),
ddi_translations[i].trans1 | iboost_bit);
I915_WRITE(DDI_BUF_TRANS_HI(port, i),
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 2/3] drm/i915: Refactor translate_signal_level()
2017-02-23 17:35 [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table ville.syrjala
@ 2017-02-23 17:35 ` ville.syrjala
2017-02-23 17:43 ` David Weinehall
2017-02-23 17:35 ` [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max() ville.syrjala
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: ville.syrjala @ 2017-02-23 17:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert the big switch statement in translate_signal_level() into a neat
table. The table also serves as documentation for the translation
tables. We'll also have other uses for this table later on.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++--------------------------
1 file changed, 21 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5e4b0172810d..6f8e57f127e5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -34,6 +34,19 @@ struct ddi_buf_trans {
u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
};
+static const u8 index_to_dp_signal_levels[] = {
+ [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
+ [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
+ [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
+ [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
+ [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
+ [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
+ [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
+ [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
+ [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
+ [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
+};
+
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
* them for both DP and FDI transports, allowing those ports to
* automatically adapt to HDMI connections as well
@@ -1604,48 +1617,17 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
static uint32_t translate_signal_level(int signal_levels)
{
- uint32_t level;
-
- switch (signal_levels) {
- default:
- DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
- signal_levels);
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- level = 0;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- level = 1;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
- level = 2;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
- level = 3;
- break;
-
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- level = 4;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- level = 5;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
- level = 6;
- break;
-
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- level = 7;
- break;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
- level = 8;
- break;
+ int i;
- case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
- level = 9;
- break;
+ for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
+ if (index_to_dp_signal_levels[i] == signal_levels)
+ return i;
}
- return level;
+ WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
+ signal_levels);
+
+ return 0;
}
uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] drm/i915: Refactor translate_signal_level()
2017-02-23 17:35 ` [PATCH 2/3] drm/i915: Refactor translate_signal_level() ville.syrjala
@ 2017-02-23 17:43 ` David Weinehall
2017-02-23 17:47 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: David Weinehall @ 2017-02-23 17:43 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Feb 23, 2017 at 07:35:06PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Convert the big switch statement in translate_signal_level() into a neat
> table. The table also serves as documentation for the translation
> tables. We'll also have other uses for this table later on.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++--------------------------
> 1 file changed, 21 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 5e4b0172810d..6f8e57f127e5 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -34,6 +34,19 @@ struct ddi_buf_trans {
> u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
> };
>
> +static const u8 index_to_dp_signal_levels[] = {
> + [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> + [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> + [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
> + [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
> + [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> + [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> + [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
> + [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> + [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> + [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> +};
> +
> /* HDMI/DVI modes ignore everything but the last 2 items. So we share
> * them for both DP and FDI transports, allowing those ports to
> * automatically adapt to HDMI connections as well
> @@ -1604,48 +1617,17 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
>
> static uint32_t translate_signal_level(int signal_levels)
> {
> - uint32_t level;
> -
> - switch (signal_levels) {
> - default:
> - DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
> - signal_levels);
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - level = 0;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - level = 1;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> - level = 2;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
> - level = 3;
> - break;
> -
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - level = 4;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - level = 5;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> - level = 6;
> - break;
> -
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - level = 7;
> - break;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - level = 8;
> - break;
> + int i;
>
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - level = 9;
> - break;
> + for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
Superfluous space between < and ARRAY_SIZE.
> + if (index_to_dp_signal_levels[i] == signal_levels)
> + return i;
> }
>
> - return level;
> + WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
> + signal_levels);
> +
> + return 0;
> }
>
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> --
> 2.10.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] drm/i915: Refactor translate_signal_level()
2017-02-23 17:43 ` David Weinehall
@ 2017-02-23 17:47 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2017-02-23 17:47 UTC (permalink / raw)
To: intel-gfx
On Thu, Feb 23, 2017 at 07:43:52PM +0200, David Weinehall wrote:
> On Thu, Feb 23, 2017 at 07:35:06PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Convert the big switch statement in translate_signal_level() into a neat
> > table. The table also serves as documentation for the translation
> > tables. We'll also have other uses for this table later on.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++--------------------------
> > 1 file changed, 21 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 5e4b0172810d..6f8e57f127e5 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -34,6 +34,19 @@ struct ddi_buf_trans {
> > u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
> > };
> >
> > +static const u8 index_to_dp_signal_levels[] = {
> > + [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> > + [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> > + [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
> > + [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
> > + [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> > + [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> > + [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
> > + [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> > + [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
> > + [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
> > +};
> > +
> > /* HDMI/DVI modes ignore everything but the last 2 items. So we share
> > * them for both DP and FDI transports, allowing those ports to
> > * automatically adapt to HDMI connections as well
> > @@ -1604,48 +1617,17 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> >
> > static uint32_t translate_signal_level(int signal_levels)
> > {
> > - uint32_t level;
> > -
> > - switch (signal_levels) {
> > - default:
> > - DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
> > - signal_levels);
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> > - level = 0;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> > - level = 1;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> > - level = 2;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
> > - level = 3;
> > - break;
> > -
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> > - level = 4;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> > - level = 5;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> > - level = 6;
> > - break;
> > -
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> > - level = 7;
> > - break;
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> > - level = 8;
> > - break;
> > + int i;
> >
> > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> > - level = 9;
> > - break;
> > + for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
>
> Superfluous space between < and ARRAY_SIZE.
Ack.
>
> > + if (index_to_dp_signal_levels[i] == signal_levels)
> > + return i;
> > }
> >
> > - return level;
> > + WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
> > + signal_levels);
> > +
> > + return 0;
> > }
> >
> > uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> > --
> > 2.10.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max()
2017-02-23 17:35 [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table ville.syrjala
2017-02-23 17:35 ` [PATCH 2/3] drm/i915: Refactor translate_signal_level() ville.syrjala
@ 2017-02-23 17:35 ` ville.syrjala
2017-02-23 17:44 ` David Weinehall
2017-02-23 17:49 ` [PATCH v2 " ville.syrjala
2017-02-23 17:49 ` [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table David Weinehall
2017-02-23 19:52 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Refactor code to select the DDI buf translation table (rev2) Patchwork
3 siblings, 2 replies; 11+ messages in thread
From: ville.syrjala @ 2017-02-23 17:35 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rather than sprinkling ideas of how big the DDI buf translation tables
are somewhere in intel_dp.c, let's concentrate it all in intel_ddi.c
where the actual tables are defined. To that end we introduce
intel_ddi_dp_voltage_max() which will actually look at the proper
translation table to determine what is the maximum voltage swing level
supported.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 5 ++---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6f8e57f127e5..0c3665f9e4f4 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1615,6 +1615,24 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
ddi_translations[level].deemphasis);
}
+u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ int n_entries;
+
+ if (encoder->type == INTEL_OUTPUT_EDP)
+ intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
+ else
+ intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
+
+ if (WARN_ON(n_entries < 1))
+ n_entries = 1;
+ if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
+ n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
+
+ return index_to_dp_signal_levels[n_entries - 1];
+}
+
static uint32_t translate_signal_level(int signal_levels)
{
int i;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 024798a9c016..e72c92a08c81 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3098,9 +3098,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
if (IS_GEN9_LP(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_GEN(dev_priv) >= 9) {
- if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
- return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
- return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ return intel_ddi_dp_voltage_max(encoder);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev_priv) && port == PORT_A)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3c8aaca947d3..e9a90dcd15df 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1233,6 +1233,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
+u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+
unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
unsigned int height,
uint32_t pixel_format,
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max()
2017-02-23 17:35 ` [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max() ville.syrjala
@ 2017-02-23 17:44 ` David Weinehall
2017-02-23 17:47 ` Ville Syrjälä
2017-02-23 17:49 ` [PATCH v2 " ville.syrjala
1 sibling, 1 reply; 11+ messages in thread
From: David Weinehall @ 2017-02-23 17:44 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Feb 23, 2017 at 07:35:07PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rather than sprinkling ideas of how big the DDI buf translation tables
> are somewhere in intel_dp.c, let's concentrate it all in intel_ddi.c
> where the actual tables are defined. To that end we introduce
> intel_ddi_dp_voltage_max() which will actually look at the proper
> translation table to determine what is the maximum voltage swing level
> supported.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 5 ++---
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6f8e57f127e5..0c3665f9e4f4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1615,6 +1615,24 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> ddi_translations[level].deemphasis);
> }
>
> +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + int n_entries;
> +
> + if (encoder->type == INTEL_OUTPUT_EDP)
> + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> + else
> + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> +
> + if (WARN_ON(n_entries < 1))
> + n_entries = 1;
> + if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
> + n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
> +
> + return index_to_dp_signal_levels[n_entries - 1];
> +}
> +
> static uint32_t translate_signal_level(int signal_levels)
> {
> int i;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 024798a9c016..e72c92a08c81 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3098,9 +3098,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> if (IS_GEN9_LP(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_GEN(dev_priv) >= 9) {
> - if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> - return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + return intel_ddi_dp_voltage_max(encoder);
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev_priv) && port == PORT_A)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3c8aaca947d3..e9a90dcd15df 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1233,6 +1233,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> +
> unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
> unsigned int height,
> uint32_t pixel_format,
> --
> 2.10.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max()
2017-02-23 17:44 ` David Weinehall
@ 2017-02-23 17:47 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2017-02-23 17:47 UTC (permalink / raw)
To: intel-gfx
On Thu, Feb 23, 2017 at 07:44:48PM +0200, David Weinehall wrote:
> On Thu, Feb 23, 2017 at 07:35:07PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rather than sprinkling ideas of how big the DDI buf translation tables
> > are somewhere in intel_dp.c, let's concentrate it all in intel_ddi.c
> > where the actual tables are defined. To that end we introduce
> > intel_ddi_dp_voltage_max() which will actually look at the proper
> > translation table to determine what is the maximum voltage swing level
> > supported.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++
> > drivers/gpu/drm/i915/intel_dp.c | 5 ++---
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 22 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6f8e57f127e5..0c3665f9e4f4 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1615,6 +1615,24 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
> > ddi_translations[level].deemphasis);
> > }
> >
> > +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + int n_entries;
> > +
> > + if (encoder->type == INTEL_OUTPUT_EDP)
> > + intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
> > + else
> > + intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
> > +
> > + if (WARN_ON(n_entries < 1))
> > + n_entries = 1;
> > + if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
> > + n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
> > +
> > + return index_to_dp_signal_levels[n_entries - 1];
I just realized myself that this needs to mask out the preemphasis bits.
I'll fire off a v2.
> > +}
> > +
> > static uint32_t translate_signal_level(int signal_levels)
> > {
> > int i;
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 024798a9c016..e72c92a08c81 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3098,9 +3098,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> > if (IS_GEN9_LP(dev_priv))
> > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > else if (INTEL_GEN(dev_priv) >= 9) {
> > - if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> > - return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > - return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> > + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > + return intel_ddi_dp_voltage_max(encoder);
> > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > else if (IS_GEN7(dev_priv) && port == PORT_A)
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 3c8aaca947d3..e9a90dcd15df 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1233,6 +1233,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config);
> > void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> > uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> > +u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> > +
> > unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
> > unsigned int height,
> > uint32_t pixel_format,
> > --
> > 2.10.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max()
2017-02-23 17:35 ` [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max() ville.syrjala
2017-02-23 17:44 ` David Weinehall
@ 2017-02-23 17:49 ` ville.syrjala
1 sibling, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2017-02-23 17:49 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rather than sprinkling ideas of how big the DDI buf translation tables
are somewhere in intel_dp.c, let's concentrate it all in intel_ddi.c
where the actual tables are defined. To that end we introduce
intel_ddi_dp_voltage_max() which will actually look at the proper
translation table to determine what is the maximum voltage swing level
supported.
v2: Mask out the preemphasis bits from the return value of
intel_ddi_dp_voltage_max()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 5 ++---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7694f4fcce4e..e2947b7f5079 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1615,6 +1615,25 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
ddi_translations[level].deemphasis);
}
+u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ int n_entries;
+
+ if (encoder->type == INTEL_OUTPUT_EDP)
+ intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
+ else
+ intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
+
+ if (WARN_ON(n_entries < 1))
+ n_entries = 1;
+ if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
+ n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
+
+ return index_to_dp_signal_levels[n_entries - 1] &
+ DP_TRAIN_VOLTAGE_SWING_MASK;
+}
+
static uint32_t translate_signal_level(int signal_levels)
{
int i;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 024798a9c016..e72c92a08c81 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3098,9 +3098,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
if (IS_GEN9_LP(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_GEN(dev_priv) >= 9) {
- if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
- return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
- return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ return intel_ddi_dp_voltage_max(encoder);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev_priv) && port == PORT_A)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3c8aaca947d3..e9a90dcd15df 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1233,6 +1233,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
+u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+
unsigned int intel_fb_align_height(struct drm_i915_private *dev_priv,
unsigned int height,
uint32_t pixel_format,
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table
2017-02-23 17:35 [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table ville.syrjala
2017-02-23 17:35 ` [PATCH 2/3] drm/i915: Refactor translate_signal_level() ville.syrjala
2017-02-23 17:35 ` [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max() ville.syrjala
@ 2017-02-23 17:49 ` David Weinehall
2017-02-24 12:49 ` Ville Syrjälä
2017-02-23 19:52 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Refactor code to select the DDI buf translation table (rev2) Patchwork
3 siblings, 1 reply; 11+ messages in thread
From: David Weinehall @ 2017-02-23 17:49 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, Feb 23, 2017 at 07:35:05PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the code to select the correct trasnslation table into DP,
translations, superfluous space before DP
> eDP and FDI specific helpers. This reduces the clutter in
> intel_prepare_dp_ddi_buffers(), and we'll have other uses for some
> of these new helper functions later on.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 126 +++++++++++++++++++++++----------------
> 1 file changed, 73 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cd6fedd229a0..5e4b0172810d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -468,6 +468,59 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> return hdmi_level;
> }
>
> +static const struct ddi_buf_trans *
> +intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> + int *n_entries)
> +{
> + if (IS_KABYLAKE(dev_priv)) {
> + return kbl_get_buf_trans_dp(dev_priv, n_entries);
> + } else if (IS_SKYLAKE(dev_priv)) {
> + return skl_get_buf_trans_dp(dev_priv, n_entries);
> + } else if (IS_BROADWELL(dev_priv)) {
> + *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> + return bdw_ddi_translations_dp;
> + } else if (IS_HASWELL(dev_priv)) {
> + *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> + return hsw_ddi_translations_dp;
> + }
> +
> + *n_entries = 0;
> + return NULL;
> +}
> +
> +static const struct ddi_buf_trans *
> +intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> + int *n_entries)
> +{
> + if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
> + return skl_get_buf_trans_edp(dev_priv, n_entries);
> + } else if (IS_BROADWELL(dev_priv)) {
> + return bdw_get_buf_trans_edp(dev_priv, n_entries);
> + } else if (IS_HASWELL(dev_priv)) {
> + *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> + return hsw_ddi_translations_dp;
> + }
> +
> + *n_entries = 0;
> + return NULL;
> +}
> +
> +static const struct ddi_buf_trans *
> +intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
> + int *n_entries)
> +{
> + if (IS_BROADWELL(dev_priv)) {
> + *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
> + return hsw_ddi_translations_fdi;
> + } else if (IS_HASWELL(dev_priv)) {
> + *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
> + return hsw_ddi_translations_fdi;
> + }
> +
> + *n_entries = 0;
> + return NULL;
> +}
> +
> /*
> * Starting with Haswell, DDI port buffers must be programmed with correct
> * values in advance. This function programs the correct values for
> @@ -477,45 +530,29 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 iboost_bit = 0;
> - int i, n_dp_entries, n_edp_entries, size;
> + int i, n_entries;
> enum port port = intel_ddi_get_encoder_port(encoder);
> - const struct ddi_buf_trans *ddi_translations_fdi;
> - const struct ddi_buf_trans *ddi_translations_dp;
> - const struct ddi_buf_trans *ddi_translations_edp;
> const struct ddi_buf_trans *ddi_translations;
>
> if (IS_GEN9_LP(dev_priv))
> return;
>
> - if (IS_KABYLAKE(dev_priv)) {
> - ddi_translations_fdi = NULL;
> - ddi_translations_dp =
> - kbl_get_buf_trans_dp(dev_priv, &n_dp_entries);
> - ddi_translations_edp =
> - skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
> - } else if (IS_SKYLAKE(dev_priv)) {
> - ddi_translations_fdi = NULL;
> - ddi_translations_dp =
> - skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
> - ddi_translations_edp =
> - skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
> - } else if (IS_BROADWELL(dev_priv)) {
> - ddi_translations_fdi = bdw_ddi_translations_fdi;
> - ddi_translations_dp = bdw_ddi_translations_dp;
> - ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
> - n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> - } else if (IS_HASWELL(dev_priv)) {
> - ddi_translations_fdi = hsw_ddi_translations_fdi;
> - ddi_translations_dp = hsw_ddi_translations_dp;
> - ddi_translations_edp = hsw_ddi_translations_dp;
> - n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> - } else {
> - WARN(1, "ddi translation table missing\n");
> - ddi_translations_edp = bdw_ddi_translations_dp;
> - ddi_translations_fdi = bdw_ddi_translations_fdi;
> - ddi_translations_dp = bdw_ddi_translations_dp;
> - n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
> - n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> + switch (encoder->type) {
> + case INTEL_OUTPUT_EDP:
> + ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
> + &n_entries);
> + break;
> + case INTEL_OUTPUT_DP:
> + ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
> + &n_entries);
> + break;
> + case INTEL_OUTPUT_ANALOG:
> + ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
> + &n_entries);
> + break;
> + default:
> + MISSING_CASE(encoder->type);
> + return;
> }
>
> if (IS_GEN9_BC(dev_priv)) {
> @@ -525,28 +562,11 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
>
> if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
> port != PORT_A && port != PORT_E &&
> - n_edp_entries > 9))
> - n_edp_entries = 9;
> - }
> -
> - switch (encoder->type) {
> - case INTEL_OUTPUT_EDP:
> - ddi_translations = ddi_translations_edp;
> - size = n_edp_entries;
> - break;
> - case INTEL_OUTPUT_DP:
> - ddi_translations = ddi_translations_dp;
> - size = n_dp_entries;
> - break;
> - case INTEL_OUTPUT_ANALOG:
> - ddi_translations = ddi_translations_fdi;
> - size = n_dp_entries;
> - break;
> - default:
> - BUG();
> + n_entries > 9))
> + n_entries = 9;
> }
>
> - for (i = 0; i < size; i++) {
> + for (i = 0; i < n_entries; i++) {
> I915_WRITE(DDI_BUF_TRANS_LO(port, i),
> ddi_translations[i].trans1 | iboost_bit);
> I915_WRITE(DDI_BUF_TRANS_HI(port, i),
> --
> 2.10.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table
2017-02-23 17:49 ` [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table David Weinehall
@ 2017-02-24 12:49 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2017-02-24 12:49 UTC (permalink / raw)
To: intel-gfx
On Thu, Feb 23, 2017 at 07:49:21PM +0200, David Weinehall wrote:
> On Thu, Feb 23, 2017 at 07:35:05PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Split the code to select the correct trasnslation table into DP,
>
> translations, superfluous space before DP
Fixed. And series pushed to dinq. Thanks for the review.
>
> > eDP and FDI specific helpers. This reduces the clutter in
> > intel_prepare_dp_ddi_buffers(), and we'll have other uses for some
> > of these new helper functions later on.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 126 +++++++++++++++++++++++----------------
> > 1 file changed, 73 insertions(+), 53 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index cd6fedd229a0..5e4b0172810d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -468,6 +468,59 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> > return hdmi_level;
> > }
> >
> > +static const struct ddi_buf_trans *
> > +intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
> > + int *n_entries)
> > +{
> > + if (IS_KABYLAKE(dev_priv)) {
> > + return kbl_get_buf_trans_dp(dev_priv, n_entries);
> > + } else if (IS_SKYLAKE(dev_priv)) {
> > + return skl_get_buf_trans_dp(dev_priv, n_entries);
> > + } else if (IS_BROADWELL(dev_priv)) {
> > + *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> > + return bdw_ddi_translations_dp;
> > + } else if (IS_HASWELL(dev_priv)) {
> > + *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> > + return hsw_ddi_translations_dp;
> > + }
> > +
> > + *n_entries = 0;
> > + return NULL;
> > +}
> > +
> > +static const struct ddi_buf_trans *
> > +intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
> > + int *n_entries)
> > +{
> > + if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
> > + return skl_get_buf_trans_edp(dev_priv, n_entries);
> > + } else if (IS_BROADWELL(dev_priv)) {
> > + return bdw_get_buf_trans_edp(dev_priv, n_entries);
> > + } else if (IS_HASWELL(dev_priv)) {
> > + *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> > + return hsw_ddi_translations_dp;
> > + }
> > +
> > + *n_entries = 0;
> > + return NULL;
> > +}
> > +
> > +static const struct ddi_buf_trans *
> > +intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
> > + int *n_entries)
> > +{
> > + if (IS_BROADWELL(dev_priv)) {
> > + *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
> > + return hsw_ddi_translations_fdi;
> > + } else if (IS_HASWELL(dev_priv)) {
> > + *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
> > + return hsw_ddi_translations_fdi;
> > + }
> > +
> > + *n_entries = 0;
> > + return NULL;
> > +}
> > +
> > /*
> > * Starting with Haswell, DDI port buffers must be programmed with correct
> > * values in advance. This function programs the correct values for
> > @@ -477,45 +530,29 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > u32 iboost_bit = 0;
> > - int i, n_dp_entries, n_edp_entries, size;
> > + int i, n_entries;
> > enum port port = intel_ddi_get_encoder_port(encoder);
> > - const struct ddi_buf_trans *ddi_translations_fdi;
> > - const struct ddi_buf_trans *ddi_translations_dp;
> > - const struct ddi_buf_trans *ddi_translations_edp;
> > const struct ddi_buf_trans *ddi_translations;
> >
> > if (IS_GEN9_LP(dev_priv))
> > return;
> >
> > - if (IS_KABYLAKE(dev_priv)) {
> > - ddi_translations_fdi = NULL;
> > - ddi_translations_dp =
> > - kbl_get_buf_trans_dp(dev_priv, &n_dp_entries);
> > - ddi_translations_edp =
> > - skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
> > - } else if (IS_SKYLAKE(dev_priv)) {
> > - ddi_translations_fdi = NULL;
> > - ddi_translations_dp =
> > - skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
> > - ddi_translations_edp =
> > - skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
> > - } else if (IS_BROADWELL(dev_priv)) {
> > - ddi_translations_fdi = bdw_ddi_translations_fdi;
> > - ddi_translations_dp = bdw_ddi_translations_dp;
> > - ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries);
> > - n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> > - } else if (IS_HASWELL(dev_priv)) {
> > - ddi_translations_fdi = hsw_ddi_translations_fdi;
> > - ddi_translations_dp = hsw_ddi_translations_dp;
> > - ddi_translations_edp = hsw_ddi_translations_dp;
> > - n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
> > - } else {
> > - WARN(1, "ddi translation table missing\n");
> > - ddi_translations_edp = bdw_ddi_translations_dp;
> > - ddi_translations_fdi = bdw_ddi_translations_fdi;
> > - ddi_translations_dp = bdw_ddi_translations_dp;
> > - n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
> > - n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> > + switch (encoder->type) {
> > + case INTEL_OUTPUT_EDP:
> > + ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
> > + &n_entries);
> > + break;
> > + case INTEL_OUTPUT_DP:
> > + ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
> > + &n_entries);
> > + break;
> > + case INTEL_OUTPUT_ANALOG:
> > + ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
> > + &n_entries);
> > + break;
> > + default:
> > + MISSING_CASE(encoder->type);
> > + return;
> > }
> >
> > if (IS_GEN9_BC(dev_priv)) {
> > @@ -525,28 +562,11 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
> >
> > if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
> > port != PORT_A && port != PORT_E &&
> > - n_edp_entries > 9))
> > - n_edp_entries = 9;
> > - }
> > -
> > - switch (encoder->type) {
> > - case INTEL_OUTPUT_EDP:
> > - ddi_translations = ddi_translations_edp;
> > - size = n_edp_entries;
> > - break;
> > - case INTEL_OUTPUT_DP:
> > - ddi_translations = ddi_translations_dp;
> > - size = n_dp_entries;
> > - break;
> > - case INTEL_OUTPUT_ANALOG:
> > - ddi_translations = ddi_translations_fdi;
> > - size = n_dp_entries;
> > - break;
> > - default:
> > - BUG();
> > + n_entries > 9))
> > + n_entries = 9;
> > }
> >
> > - for (i = 0; i < size; i++) {
> > + for (i = 0; i < n_entries; i++) {
> > I915_WRITE(DDI_BUF_TRANS_LO(port, i),
> > ddi_translations[i].trans1 | iboost_bit);
> > I915_WRITE(DDI_BUF_TRANS_HI(port, i),
> > --
> > 2.10.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Refactor code to select the DDI buf translation table (rev2)
2017-02-23 17:35 [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table ville.syrjala
` (2 preceding siblings ...)
2017-02-23 17:49 ` [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table David Weinehall
@ 2017-02-23 19:52 ` Patchwork
3 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2017-02-23 19:52 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Refactor code to select the DDI buf translation table (rev2)
URL : https://patchwork.freedesktop.org/series/20165/
State : success
== Summary ==
Series 20165v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20165/revisions/2/mbox/
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:108 pass:95 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29
5b28284e2cdc5f3154225255e081f1f2050820bb drm-tip: 2017y-02m-23d-18h-49m-02s UTC integration manifest
3aa34eb8 drm/i915: Introduce intel_ddi_dp_voltage_max()
953f040 drm/i915: Refactor translate_signal_level()
03444d66 drm/i915: Refactor code to select the DDI buf translation table
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3953/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-02-24 12:49 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-23 17:35 [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table ville.syrjala
2017-02-23 17:35 ` [PATCH 2/3] drm/i915: Refactor translate_signal_level() ville.syrjala
2017-02-23 17:43 ` David Weinehall
2017-02-23 17:47 ` Ville Syrjälä
2017-02-23 17:35 ` [PATCH 3/3] drm/i915: Introduce intel_ddi_dp_voltage_max() ville.syrjala
2017-02-23 17:44 ` David Weinehall
2017-02-23 17:47 ` Ville Syrjälä
2017-02-23 17:49 ` [PATCH v2 " ville.syrjala
2017-02-23 17:49 ` [PATCH 1/3] drm/i915: Refactor code to select the DDI buf translation table David Weinehall
2017-02-24 12:49 ` Ville Syrjälä
2017-02-23 19:52 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Refactor code to select the DDI buf translation table (rev2) Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.