[Qemu-devel] [Bug 1668103] Re: Possible off-by-one error in priority handling of hw/PL190.c

[Thomas Huth <1668103@bugs.launchpad.net>]

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** Changed in: qemu
       Status: Fix Committed => In Progress

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Title:
  Possible off-by-one error in priority handling of hw/PL190.c

Status in QEMU:
  In Progress

Bug description:
  I have a problem when reading back VECTADDR in my proprietary OS's
  interrupt handler.

  Example client code:

   1) Write INTENCLEAR to clear all interrupt enable bits
   2) Set all 16 vector control registers to zero
   3) Set vector address #2 to value 2
   4) Set vector control #2 to 0x21 (vector_interrupt_enable(0x20) | vector_interrupt_source(0x1) )
   5) Enable interrupt 1 by writing 0x2 to INTENABLE
   6) In interrupt handler: read VECTADDR [should read 0x2 (active IRQs vector address as set in step 3), reads 0x0 (active vector address index 3 instead of index 2)]

  Problem:

  So, for me, the block commented with /* Read vector address at the
  start of an ISR...  */ in hw/pl190.c has an off by-one error and does
  not return the vector address of the pending interrupt, but of the
  next one in the list of priorities (i.e. vector address 3).

  Solution:

  In pl190_update_vectors(), also set the priority bit for the current
  priority (1<<i) interrupt (if enabled) in s->prio_mask[i] in addition
  to those of higher priority enabled interrupts. This will cause the
  loop in the read handling of VECTADDR to terminate an iteration
  earlier and will deliver the correct interrupt priority as iteration
  variable i subsequently used for addressing.

  I'll try to provide a patch for this.

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