* [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf
@ 2017-02-22 16:36 Robert Bragg
2017-02-22 16:36 ` [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM Robert Bragg
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
This extends i915 perf to support periodic sampling of OA metrics for BDW, CHV,
SKL and BXT.
I've recently been working through a number of issues that were uncovered once
I started adapting the gen7 IGT tests. Some further issues were also noticed by
others using INTEL_performance_query in Mesa. So compared to earlier Gen8+ OA
series sent out a few notable updates are:
* Implements tail race handling like we have for gen 7
* On SKL we disable automatic reports for slice/unslice clock ratio changes
because the hardware can generate so many redundant reports (no ratio change)
that buffer overflows can start to become a problem and userspace ends up
doing an unreasonable amount of work to keep up.
* WaDisableDopClockGating:bdw is no longer handled in i915_perf.c
* Flex EU register updates within the register state context were using
incorrect offsets before.
* The generated per-gen config initialization code wasn't initializing the
flex eu register state.
* While filtering for a single context we weren't forwarding userspace the
reports it needed to bookend around context switches so that it can discount
the progress of the counters associated with other contexts.
* Even opening a stream for single context filtered OA metrics requires
dev.i915.perf_stream_paranoid == 0 since we can no longer reliably hide the
progress of system-wide metrics, now that filtering is done based on tagging
reports with an ID instead of physically clock gating the OA unit off for
other contests.
In case anyone wants to take a look at the IGT tests so far they can be found
here:
https://github.com/rib/intel-gpu-tools/commits/wip/rib/i915-perf-tests
I should probably write a few additional tests specific to changes made for
gen8+, but I've at least adapted the existing tests for gen7.
I can only say I've tested on Skylake recently, so although we can hopefully
review these patches with an eye towards upstreaming, they do still need some
broader testing across more hardware.
Considering the large number of configs for Gen 8 and 9, and how unsure I am
about the maturity of all the various configs I do have some doubt about
whether we should upstream them all together if someone hasn't looked at the
unique counters for each set against a relevant workload to see that the
numbers look plausible (so ignoring the common A counters). On the other hand
being optimistic means we can make more sets available faster and even makes it
more likely they will be tested across a broader range of workloads. We can
add replacement configs if needs be or even stop advertising configs
considering how they are advertised to userspace dynamically.
Note: these patches are based on the patches I sent out to update the tail
pointer race workaround for Haswell in i915 perf.
Regards,
- Robert
Robert Bragg (6):
drm/i915: expose _SLICE_MASK GETPARM
drm/i915: expose _SUBSLICE_MASK GETPARM
drm/i915: Add uncore mmio api for per-context registers
drm/i915: Add 'render basic' Gen8+ OA unit configs
drm/i915: Add OA unit support for Gen 8+
drm/i915: Add more OA configs for BDW, CHV, SKL + BXT
drivers/gpu/drm/i915/Makefile | 8 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +
drivers/gpu/drm/i915/i915_drv.h | 20 +
drivers/gpu/drm/i915/i915_gem_context.h | 1 +
drivers/gpu/drm/i915/i915_oa_bdw.c | 4954 +++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_bdw.h | 38 +
drivers/gpu/drm/i915/i915_oa_bxt.c | 2541 ++++++++++++++++
drivers/gpu/drm/i915/i915_oa_bxt.h | 38 +
drivers/gpu/drm/i915/i915_oa_chv.c | 2730 +++++++++++++++++
drivers/gpu/drm/i915/i915_oa_chv.h | 38 +
drivers/gpu/drm/i915/i915_oa_sklgt2.c | 3303 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt2.h | 38 +
drivers/gpu/drm/i915/i915_oa_sklgt3.c | 2856 ++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt3.h | 38 +
drivers/gpu/drm/i915/i915_oa_sklgt4.c | 2910 ++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt4.h | 38 +
drivers/gpu/drm/i915/i915_perf.c | 1067 ++++++-
drivers/gpu/drm/i915/i915_reg.h | 12 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +
drivers/gpu/drm/i915/intel_uncore.c | 73 +
include/uapi/drm/i915_drm.h | 21 +-
21 files changed, 20667 insertions(+), 71 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.h
--
2.11.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-02-22 16:36 ` [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM Robert Bragg
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
Enables userspace to determine the number of slices enabled and also
know what specific slices are enabled. This information is required, for
example, to be able to analyse some OA counter reports where the counter
configuration depends on the HW slice configuration.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b76e8f7ac174..d391768f301b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -359,6 +359,11 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_SLICE_MASK:
+ value = INTEL_INFO(dev_priv)->sseu.slice_mask;
+ if (!value)
+ return -ENODEV;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3554495bef13..f47fb7f26f36 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_SLICE_MASK 45 /* XXX: rebase before landing */
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
* priorities and the driver will attempt to execute batches in priority order.
--
2.11.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
2017-02-22 16:36 ` [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-02-22 16:36 ` [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers Robert Bragg
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
Assuming a uniform mask across all slices, this enables userspace to
determine the specific sub slices enabled. This information is required,
for example, to be able to analyse some OA counter reports where the
counter configuration depends on the HW sub slice configuration.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d391768f301b..a497537b42d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -364,6 +364,11 @@ static int i915_getparam(struct drm_device *dev, void *data,
if (!value)
return -ENODEV;
break;
+ case I915_PARAM_SUBSLICE_MASK:
+ value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
+ if (!value)
+ return -ENODEV;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f47fb7f26f36..e0599e729e68 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -393,6 +393,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
#define I915_PARAM_SLICE_MASK 45 /* XXX: rebase before landing */
+#define I915_PARAM_SUBSLICE_MASK 46
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
* priorities and the driver will attempt to execute batches in priority order.
--
2.11.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
2017-02-22 16:36 ` [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM Robert Bragg
2017-02-22 16:36 ` [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-02-23 15:35 ` Chris Wilson
2017-02-22 16:36 ` [PATCH 4/6] drm/i915: Add 'render basic' Gen8+ OA unit configs Robert Bragg
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
Since the exponent for periodic OA counter sampling is maintained in a
per-context register while we want to treat it as if it were global
state we need to be able to safely issue an mmio write to a per-context
register and affect any currently running context.
We have to take some extra care in this case and this adds a utility
api to encapsulate what's required.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_uncore.c | 73 +++++++++++++++++++++++++++++++++++++
3 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 105b97bd34d7..c8d03a2e89cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -718,6 +718,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
i915_reg_t reg, unsigned int op);
struct intel_uncore_funcs {
+ int (*wait_for_rcs_busy)(struct drm_i915_private *dev_priv);
void (*force_wake_get)(struct drm_i915_private *dev_priv,
enum forcewake_domains domains);
void (*force_wake_put)(struct drm_i915_private *dev_priv,
@@ -751,6 +752,7 @@ struct intel_uncore {
struct intel_uncore_funcs funcs;
+ atomic_t hold_rcs_busy_count;
unsigned fifo_count;
enum forcewake_domains fw_domains;
@@ -3139,6 +3141,8 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
{
return dev_priv->vgpu.active;
}
+int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv);
+void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv);
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 141a5c1e3895..94d40e82edc1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2313,6 +2313,9 @@ enum skl_disp_power_wells {
#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
+#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
+#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
+
/* Fuse readout registers for GT */
#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
#define CHV_FGT_DISABLE_SS0 (1 << 10)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 441c51fd9746..06bfe5f89ac5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1274,6 +1274,16 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->uncore.fw_domains == 0);
}
+static int gen8_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ return wait_for((I915_READ(GEN6_RCS_PWR_FSM) & 0x3f) == 0x30, 50);
+}
+
+static int gen9_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ return wait_for((I915_READ(GEN9_RCS_FE_FSM2) & 0x3f) == 0x30, 50);
+}
+
#define ASSIGN_FW_DOMAINS_TABLE(d) \
{ \
dev_priv->uncore.fw_domains_table = \
@@ -1305,6 +1315,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
dev_priv->uncore.funcs.mmio_writel =
gen9_decoupled_write32;
}
+ dev_priv->uncore.funcs.wait_for_rcs_busy =
+ gen9_wait_for_rcs_busy;
break;
case 8:
if (IS_CHERRYVIEW(dev_priv)) {
@@ -1316,6 +1328,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
ASSIGN_WRITE_MMIO_VFUNCS(gen8);
ASSIGN_READ_MMIO_VFUNCS(gen6);
}
+ dev_priv->uncore.funcs.wait_for_rcs_busy =
+ gen8_wait_for_rcs_busy;
break;
case 7:
case 6:
@@ -1858,6 +1872,65 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
return fw_domains;
}
+static int hold_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ int ret = 0;
+
+ if (atomic_inc_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
+ I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+
+ ret = dev_priv->uncore.funcs.wait_for_rcs_busy(dev_priv);
+ }
+
+ return ret;
+}
+
+static void release_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ if (!atomic_dec_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
+ I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+ }
+}
+
+/*
+ * From Broadwell PRM, 3D-Media-GPGPU -> Register State Context
+ *
+ * MMIO reads or writes to any of the registers listed in the
+ * “Register State Context image” subsections through HOST/IA
+ * MMIO interface for debug purposes must follow the steps below:
+ *
+ * - SW should set the Force Wakeup bit to prevent GT from entering C6.
+ * - Write 0x2050[31:0] = 0x00010001 (disable sequence).
+ * - Disable IDLE messaging in CS (Write 0x2050[31:0] = 0x00010001).
+ * - BDW: Poll/Wait for register bits of 0x22AC[6:0] turn to 0x30 value.
+ * - SKL+: Poll/Wait for register bits of 0x22A4[6:0] turn to 0x30 value.
+ * - Read/Write to desired MMIO registers.
+ * - Enable IDLE messaging in CS (Write 0x2050[31:0] = 0x00010000).
+ * - Force Wakeup bit should be reset to enable C6 entry.
+ */
+int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv)
+{
+ int ret = 0;
+
+ BUG_ON(dev_priv->info.gen < 8);
+
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_RENDER);
+
+ ret = hold_rcs_busy(dev_priv);
+ if (ret)
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
+
+ return ret;
+}
+
+void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv)
+{
+ release_rcs_busy(dev_priv);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/intel_uncore.c"
#endif
--
2.11.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/6] drm/i915: Add 'render basic' Gen8+ OA unit configs
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
` (2 preceding siblings ...)
2017-02-22 16:36 ` [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-02-22 16:36 ` [PATCH 5/6] drm/i915: Add OA unit support for Gen 8+ Robert Bragg
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/Makefile | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_oa_bdw.c | 371 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_bdw.h | 38 ++++
drivers/gpu/drm/i915/i915_oa_bxt.c | 322 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_bxt.h | 38 ++++
drivers/gpu/drm/i915/i915_oa_chv.c | 214 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_chv.h | 38 ++++
drivers/gpu/drm/i915/i915_oa_sklgt2.c | 228 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt2.h | 38 ++++
drivers/gpu/drm/i915/i915_oa_sklgt3.c | 236 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt3.h | 38 ++++
drivers/gpu/drm/i915/i915_oa_sklgt4.c | 247 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_sklgt4.h | 38 ++++
14 files changed, 1855 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b1b580337c7a..65a31450a392 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -127,7 +127,13 @@ i915-y += i915_vgpu.o
# perf code
i915-y += i915_perf.o \
- i915_oa_hsw.o
+ i915_oa_hsw.o \
+ i915_oa_bdw.o \
+ i915_oa_chv.o \
+ i915_oa_sklgt2.o \
+ i915_oa_sklgt3.o \
+ i915_oa_sklgt4.o \
+ i915_oa_bxt.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c8d03a2e89cc..d5e084b46023 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2437,6 +2437,8 @@ struct drm_i915_private {
int mux_regs_len;
const struct i915_oa_reg *b_counter_regs;
int b_counter_regs_len;
+ const struct i915_oa_reg *flex_regs;
+ int flex_regs_len;
struct {
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c
new file mode 100644
index 000000000000..d5d608ff2a36
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.c
@@ -0,0 +1,371 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_bdw.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_bdw = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
+ { _MMIO(0x9888), 0x143f000f },
+ { _MMIO(0x9888), 0x14110014 },
+ { _MMIO(0x9888), 0x14310014 },
+ { _MMIO(0x9888), 0x14bf000f },
+ { _MMIO(0x9888), 0x13837be0 },
+ { _MMIO(0x9888), 0x3b800060 },
+ { _MMIO(0x9888), 0x3d800005 },
+ { _MMIO(0x9888), 0x005c4000 },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x003d8000 },
+ { _MMIO(0x9888), 0x183d0800 },
+ { _MMIO(0x9888), 0x0a3f0023 },
+ { _MMIO(0x9888), 0x103f0000 },
+ { _MMIO(0x9888), 0x00584000 },
+ { _MMIO(0x9888), 0x08584000 },
+ { _MMIO(0x9888), 0x0a5a4000 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x0e5b8000 },
+ { _MMIO(0x9888), 0x185b2400 },
+ { _MMIO(0x9888), 0x0a1d4000 },
+ { _MMIO(0x9888), 0x0c1f0800 },
+ { _MMIO(0x9888), 0x0e1faa00 },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18380001 },
+ { _MMIO(0x9888), 0x00392000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a391000 },
+ { _MMIO(0x9888), 0x00104000 },
+ { _MMIO(0x9888), 0x08104000 },
+ { _MMIO(0x9888), 0x00110030 },
+ { _MMIO(0x9888), 0x08110031 },
+ { _MMIO(0x9888), 0x10110000 },
+ { _MMIO(0x9888), 0x00134000 },
+ { _MMIO(0x9888), 0x16130020 },
+ { _MMIO(0x9888), 0x06308000 },
+ { _MMIO(0x9888), 0x08308000 },
+ { _MMIO(0x9888), 0x06311800 },
+ { _MMIO(0x9888), 0x08311880 },
+ { _MMIO(0x9888), 0x10310000 },
+ { _MMIO(0x9888), 0x0e334000 },
+ { _MMIO(0x9888), 0x16330080 },
+ { _MMIO(0x9888), 0x0abf1180 },
+ { _MMIO(0x9888), 0x10bf0000 },
+ { _MMIO(0x9888), 0x0ada8000 },
+ { _MMIO(0x9888), 0x0a9d8000 },
+ { _MMIO(0x9888), 0x109f0002 },
+ { _MMIO(0x9888), 0x0ab94000 },
+ { _MMIO(0x9888), 0x0d888000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8a00a0 },
+ { _MMIO(0x9888), 0x238b0020 },
+ { _MMIO(0x9888), 0x258b2550 },
+ { _MMIO(0x9888), 0x198c1000 },
+ { _MMIO(0x9888), 0x0b8d8000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x0d831021 },
+ { _MMIO(0x9888), 0x0f83572f },
+ { _MMIO(0x9888), 0x01835680 },
+ { _MMIO(0x9888), 0x038315ac },
+ { _MMIO(0x9888), 0x0583002a },
+ { _MMIO(0x9888), 0x11830000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830001 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x05844000 },
+ { _MMIO(0x9888), 0x1b80c137 },
+ { _MMIO(0x9888), 0x1d80c147 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x17808000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x15804000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801110 },
+ { _MMIO(0x9888), 0x4f800331 },
+ { _MMIO(0x9888), 0x43800802 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45801465 },
+ { _MMIO(0x9888), 0x53801111 },
+ { _MMIO(0x9888), 0x478014a5 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f8014a5 },
+ { _MMIO(0x9888), 0x41800005 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
+ { _MMIO(0x9888), 0x143f000f },
+ { _MMIO(0x9888), 0x14bf000f },
+ { _MMIO(0x9888), 0x14910014 },
+ { _MMIO(0x9888), 0x14b10014 },
+ { _MMIO(0x9888), 0x13837be0 },
+ { _MMIO(0x9888), 0x3b800060 },
+ { _MMIO(0x9888), 0x3d800005 },
+ { _MMIO(0x9888), 0x0a3f0023 },
+ { _MMIO(0x9888), 0x103f0000 },
+ { _MMIO(0x9888), 0x0a5a4000 },
+ { _MMIO(0x9888), 0x0a1d4000 },
+ { _MMIO(0x9888), 0x0e1f8000 },
+ { _MMIO(0x9888), 0x0a391000 },
+ { _MMIO(0x9888), 0x00dc4000 },
+ { _MMIO(0x9888), 0x06dc8000 },
+ { _MMIO(0x9888), 0x08dcc000 },
+ { _MMIO(0x9888), 0x00bd8000 },
+ { _MMIO(0x9888), 0x18bd0800 },
+ { _MMIO(0x9888), 0x0abf1180 },
+ { _MMIO(0x9888), 0x10bf0000 },
+ { _MMIO(0x9888), 0x00d84000 },
+ { _MMIO(0x9888), 0x08d84000 },
+ { _MMIO(0x9888), 0x0ada8000 },
+ { _MMIO(0x9888), 0x00db4000 },
+ { _MMIO(0x9888), 0x0edb8000 },
+ { _MMIO(0x9888), 0x18db2400 },
+ { _MMIO(0x9888), 0x0a9d8000 },
+ { _MMIO(0x9888), 0x0c9f0800 },
+ { _MMIO(0x9888), 0x0e9f2a00 },
+ { _MMIO(0x9888), 0x109f0002 },
+ { _MMIO(0x9888), 0x00b84000 },
+ { _MMIO(0x9888), 0x0eb84000 },
+ { _MMIO(0x9888), 0x16b84000 },
+ { _MMIO(0x9888), 0x18b80001 },
+ { _MMIO(0x9888), 0x00b92000 },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab94000 },
+ { _MMIO(0x9888), 0x00904000 },
+ { _MMIO(0x9888), 0x08904000 },
+ { _MMIO(0x9888), 0x00910030 },
+ { _MMIO(0x9888), 0x08910031 },
+ { _MMIO(0x9888), 0x10910000 },
+ { _MMIO(0x9888), 0x00934000 },
+ { _MMIO(0x9888), 0x16930020 },
+ { _MMIO(0x9888), 0x06b08000 },
+ { _MMIO(0x9888), 0x08b08000 },
+ { _MMIO(0x9888), 0x06b11800 },
+ { _MMIO(0x9888), 0x08b11880 },
+ { _MMIO(0x9888), 0x10b10000 },
+ { _MMIO(0x9888), 0x0eb34000 },
+ { _MMIO(0x9888), 0x16b30080 },
+ { _MMIO(0x9888), 0x01888000 },
+ { _MMIO(0x9888), 0x0d88b800 },
+ { _MMIO(0x9888), 0x1b8a0080 },
+ { _MMIO(0x9888), 0x238b0040 },
+ { _MMIO(0x9888), 0x258b26a0 },
+ { _MMIO(0x9888), 0x018c4000 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c1100 },
+ { _MMIO(0x9888), 0x018d2000 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8d8000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x0d831021 },
+ { _MMIO(0x9888), 0x0f83572f },
+ { _MMIO(0x9888), 0x01835680 },
+ { _MMIO(0x9888), 0x038315ac },
+ { _MMIO(0x9888), 0x0583002a },
+ { _MMIO(0x9888), 0x11830000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830001 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x05844000 },
+ { _MMIO(0x9888), 0x1b80c137 },
+ { _MMIO(0x9888), 0x1d80c147 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x17808000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x15804000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d805550 },
+ { _MMIO(0x9888), 0x4f800335 },
+ { _MMIO(0x9888), 0x43800802 },
+ { _MMIO(0x9888), 0x51800400 },
+ { _MMIO(0x9888), 0x458004a1 },
+ { _MMIO(0x9888), 0x53805555 },
+ { _MMIO(0x9888), 0x47800421 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800421 },
+ { _MMIO(0x9888), 0x41800841 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_render_basic_1_0_slices_0x01);
+ return mux_config_render_basic_1_0_slices_0x01;
+ } else if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
+ *len = ARRAY_SIZE(mux_config_render_basic_1_1_slices_0x02);
+ return mux_config_render_basic_1_1_slices_0x02;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h
new file mode 100644
index 000000000000..ea6969aaf91a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_BDW_H__
+#define __I915_OA_BDW_H__
+
+extern int i915_oa_n_builtin_metric_sets_bdw;
+
+extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c
new file mode 100644
index 000000000000..6d78cdb7a73d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_bxt.c
@@ -0,0 +1,322 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_bxt.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_bxt = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic_0_0_sku_gte_0x03[] = {
+ { _MMIO(0x9888), 0x166c00f0 },
+ { _MMIO(0x9888), 0x12120280 },
+ { _MMIO(0x9888), 0x12320280 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900c00 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x002d1000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x0a2d1000 },
+ { _MMIO(0x9888), 0x0c2e0800 },
+ { _MMIO(0x9888), 0x0e2e5900 },
+ { _MMIO(0x9888), 0x0a4c8000 },
+ { _MMIO(0x9888), 0x0c4c8000 },
+ { _MMIO(0x9888), 0x0e4c4000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e2000 },
+ { _MMIO(0x9888), 0x1c4f0010 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1a0fcc00 },
+ { _MMIO(0x9888), 0x1c0f0002 },
+ { _MMIO(0x9888), 0x1c2c0040 },
+ { _MMIO(0x9888), 0x00101000 },
+ { _MMIO(0x9888), 0x04101000 },
+ { _MMIO(0x9888), 0x00114000 },
+ { _MMIO(0x9888), 0x08114000 },
+ { _MMIO(0x9888), 0x00120020 },
+ { _MMIO(0x9888), 0x08120021 },
+ { _MMIO(0x9888), 0x00141000 },
+ { _MMIO(0x9888), 0x08141000 },
+ { _MMIO(0x9888), 0x02308000 },
+ { _MMIO(0x9888), 0x04302000 },
+ { _MMIO(0x9888), 0x06318000 },
+ { _MMIO(0x9888), 0x08318000 },
+ { _MMIO(0x9888), 0x06320800 },
+ { _MMIO(0x9888), 0x08320840 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x06344000 },
+ { _MMIO(0x9888), 0x08344000 },
+ { _MMIO(0x9888), 0x0d931831 },
+ { _MMIO(0x9888), 0x0f939f3f },
+ { _MMIO(0x9888), 0x01939e80 },
+ { _MMIO(0x9888), 0x03931dbc },
+ { _MMIO(0x9888), 0x0593003a },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1993002a },
+ { _MMIO(0x9888), 0x07930000 },
+ { _MMIO(0x9888), 0x09930000 },
+ { _MMIO(0x9888), 0x1d900177 },
+ { _MMIO(0x9888), 0x1f900178 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25904000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x53901110 },
+ { _MMIO(0x9888), 0x43900423 },
+ { _MMIO(0x9888), 0x55900111 },
+ { _MMIO(0x9888), 0x47900c02 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900020 },
+ { _MMIO(0x9888), 0x59901111 },
+ { _MMIO(0x9888), 0x4b900421 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x45900821 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic_0_0_sku_lt_0x03[] = {
+ { _MMIO(0x9888), 0x166c00f0 },
+ { _MMIO(0x9888), 0x12120280 },
+ { _MMIO(0x9888), 0x12320280 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900c00 },
+ { _MMIO(0x9888), 0x419000a0 },
+ { _MMIO(0x9888), 0x002d1000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x0a2d1000 },
+ { _MMIO(0x9888), 0x0c2e0800 },
+ { _MMIO(0x9888), 0x0e2e5900 },
+ { _MMIO(0x9888), 0x0a4c8000 },
+ { _MMIO(0x9888), 0x0c4c8000 },
+ { _MMIO(0x9888), 0x0e4c4000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e2000 },
+ { _MMIO(0x9888), 0x1c4f0010 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1a0fcc00 },
+ { _MMIO(0x9888), 0x1c0f0002 },
+ { _MMIO(0x9888), 0x1c2c0040 },
+ { _MMIO(0x9888), 0x00101000 },
+ { _MMIO(0x9888), 0x04101000 },
+ { _MMIO(0x9888), 0x00114000 },
+ { _MMIO(0x9888), 0x08114000 },
+ { _MMIO(0x9888), 0x00120020 },
+ { _MMIO(0x9888), 0x08120021 },
+ { _MMIO(0x9888), 0x00141000 },
+ { _MMIO(0x9888), 0x08141000 },
+ { _MMIO(0x9888), 0x02308000 },
+ { _MMIO(0x9888), 0x04302000 },
+ { _MMIO(0x9888), 0x06318000 },
+ { _MMIO(0x9888), 0x08318000 },
+ { _MMIO(0x9888), 0x06320800 },
+ { _MMIO(0x9888), 0x08320840 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x06344000 },
+ { _MMIO(0x9888), 0x08344000 },
+ { _MMIO(0x9888), 0x0d931831 },
+ { _MMIO(0x9888), 0x0f939f3f },
+ { _MMIO(0x9888), 0x01939e80 },
+ { _MMIO(0x9888), 0x03931dbc },
+ { _MMIO(0x9888), 0x0593003a },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1993002a },
+ { _MMIO(0x9888), 0x07930000 },
+ { _MMIO(0x9888), 0x09930000 },
+ { _MMIO(0x9888), 0x1d900177 },
+ { _MMIO(0x9888), 0x1f900187 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25904000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x53901110 },
+ { _MMIO(0x9888), 0x43900423 },
+ { _MMIO(0x9888), 0x55900111 },
+ { _MMIO(0x9888), 0x47900c02 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900020 },
+ { _MMIO(0x9888), 0x59901111 },
+ { _MMIO(0x9888), 0x4b900421 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x45900821 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (dev_priv->drm.pdev->revision >= 0x03) {
+ *len = ARRAY_SIZE(mux_config_render_basic_0_0_sku_gte_0x03);
+ return mux_config_render_basic_0_0_sku_gte_0x03;
+ } else if (dev_priv->drm.pdev->revision < 0x03) {
+ *len = ARRAY_SIZE(mux_config_render_basic_0_0_sku_lt_0x03);
+ return mux_config_render_basic_0_0_sku_lt_0x03;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.h b/drivers/gpu/drm/i915/i915_oa_bxt.h
new file mode 100644
index 000000000000..9e86662c891d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_bxt.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_BXT_H__
+#define __I915_OA_BXT_H__
+
+extern int i915_oa_n_builtin_metric_sets_bxt;
+
+extern int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c
new file mode 100644
index 000000000000..3f06e0e1c3f2
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_chv.c
@@ -0,0 +1,214 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_chv.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_chv = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x59800000 },
+ { _MMIO(0x9888), 0x59800001 },
+ { _MMIO(0x9888), 0x2c110014 },
+ { _MMIO(0x9888), 0x2e110000 },
+ { _MMIO(0x9888), 0x2c310014 },
+ { _MMIO(0x9888), 0x2e310000 },
+ { _MMIO(0x9888), 0x2b8303df },
+ { _MMIO(0x9888), 0x358002c0 },
+ { _MMIO(0x9888), 0x00580888 },
+ { _MMIO(0x9888), 0x00190555 },
+ { _MMIO(0x9888), 0x00380444 },
+ { _MMIO(0x9888), 0x003a0666 },
+ { _MMIO(0x9888), 0x00100111 },
+ { _MMIO(0x9888), 0x06110030 },
+ { _MMIO(0x9888), 0x0a110031 },
+ { _MMIO(0x9888), 0x0e110046 },
+ { _MMIO(0x9888), 0x04110000 },
+ { _MMIO(0x9888), 0x00110000 },
+ { _MMIO(0x9888), 0x00130111 },
+ { _MMIO(0x9888), 0x00300444 },
+ { _MMIO(0x9888), 0x08310030 },
+ { _MMIO(0x9888), 0x0c310031 },
+ { _MMIO(0x9888), 0x10310046 },
+ { _MMIO(0x9888), 0x04310000 },
+ { _MMIO(0x9888), 0x00310000 },
+ { _MMIO(0x9888), 0x00330444 },
+ { _MMIO(0x9888), 0x018b0fff },
+ { _MMIO(0x9888), 0x01855000 },
+ { _MMIO(0x9888), 0x03850555 },
+ { _MMIO(0x9888), 0x13830021 },
+ { _MMIO(0x9888), 0x15830020 },
+ { _MMIO(0x9888), 0x1783002f },
+ { _MMIO(0x9888), 0x1983002e },
+ { _MMIO(0x9888), 0x1b83002d },
+ { _MMIO(0x9888), 0x1d83002c },
+ { _MMIO(0x9888), 0x1f83002b },
+ { _MMIO(0x9888), 0x2183002a },
+ { _MMIO(0x9888), 0x05830000 },
+ { _MMIO(0x9888), 0x01840555 },
+ { _MMIO(0x9888), 0x23800071 },
+ { _MMIO(0x9888), 0x25800072 },
+ { _MMIO(0x9888), 0x05800000 },
+ { _MMIO(0x9888), 0x01805000 },
+ { _MMIO(0x9888), 0x03800555 },
+ { _MMIO(0x9888), 0x01865000 },
+ { _MMIO(0x9888), 0x03860555 },
+ { _MMIO(0x9888), 0x01875000 },
+ { _MMIO(0x9888), 0x03870555 },
+ { _MMIO(0x9888), 0x418000aa },
+ { _MMIO(0x9888), 0x4380000a },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x47800000 },
+ { _MMIO(0x9888), 0x498000c8 },
+ { _MMIO(0x9888), 0x4b8000c8 },
+ { _MMIO(0x9888), 0x4d8000c8 },
+ { _MMIO(0x9888), 0x4f80014a },
+ { _MMIO(0x9888), 0x5180014a },
+ { _MMIO(0x9888), 0x5380014a },
+ { _MMIO(0x9888), 0x5580014a },
+ { _MMIO(0x9888), 0x578001ce },
+ { _MMIO(0x9888), 0x59800000 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_basic);
+ return mux_config_render_basic;
+}
+
+int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_chv.h b/drivers/gpu/drm/i915/i915_oa_chv.h
new file mode 100644
index 000000000000..e494200ff04f
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_chv.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_CHV_H__
+#define __I915_OA_CHV_H__
+
+extern int i915_oa_n_builtin_metric_sets_chv;
+
+extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
new file mode 100644
index 000000000000..e50842f2b939
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
@@ -0,0 +1,228 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_sklgt2.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_sklgt2 = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic_1_1_sku_gte_0x02[] = {
+ { _MMIO(0x9888), 0x166c01e0 },
+ { _MMIO(0x9888), 0x12170280 },
+ { _MMIO(0x9888), 0x12370280 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x1a4e0080 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x0a1b4000 },
+ { _MMIO(0x9888), 0x1c1c0001 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x042f1000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c8400 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0d2000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f6600 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x162c2200 },
+ { _MMIO(0x9888), 0x062d8000 },
+ { _MMIO(0x9888), 0x082d8000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x08133000 },
+ { _MMIO(0x9888), 0x00170020 },
+ { _MMIO(0x9888), 0x08170021 },
+ { _MMIO(0x9888), 0x10170000 },
+ { _MMIO(0x9888), 0x0633c000 },
+ { _MMIO(0x9888), 0x0833c000 },
+ { _MMIO(0x9888), 0x06370800 },
+ { _MMIO(0x9888), 0x08370840 },
+ { _MMIO(0x9888), 0x10370000 },
+ { _MMIO(0x9888), 0x0d933031 },
+ { _MMIO(0x9888), 0x0f933e3f },
+ { _MMIO(0x9888), 0x01933d00 },
+ { _MMIO(0x9888), 0x0393073c },
+ { _MMIO(0x9888), 0x0593000e },
+ { _MMIO(0x9888), 0x1d930000 },
+ { _MMIO(0x9888), 0x19930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190001f },
+ { _MMIO(0x9888), 0x51904400 },
+ { _MMIO(0x9888), 0x41900020 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c21 },
+ { _MMIO(0x9888), 0x47900061 },
+ { _MMIO(0x9888), 0x57904440 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900004 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53904444 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (dev_priv->drm.pdev->revision >= 0x02) {
+ *len = ARRAY_SIZE(mux_config_render_basic_1_1_sku_gte_0x02);
+ return mux_config_render_basic_1_1_sku_gte_0x02;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "f519e481-24d2-4d42-87c9-3fdd12c00202",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.h b/drivers/gpu/drm/i915/i915_oa_sklgt2.h
new file mode 100644
index 000000000000..e99b03f1bf9e
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_SKLGT2_H__
+#define __I915_OA_SKLGT2_H__
+
+extern int i915_oa_n_builtin_metric_sets_sklgt2;
+
+extern int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
new file mode 100644
index 000000000000..0f508fed71e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
@@ -0,0 +1,236 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_sklgt3.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_sklgt3 = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x166c01e0 },
+ { _MMIO(0x9888), 0x12170280 },
+ { _MMIO(0x9888), 0x12370280 },
+ { _MMIO(0x9888), 0x16ec01e0 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x1a4e0380 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x0a1b4000 },
+ { _MMIO(0x9888), 0x1c1c0001 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x042f1000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c8400 },
+ { _MMIO(0x9888), 0x0c4c0002 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f6600 },
+ { _MMIO(0x9888), 0x100f0001 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x162ca200 },
+ { _MMIO(0x9888), 0x062d8000 },
+ { _MMIO(0x9888), 0x082d8000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x08133000 },
+ { _MMIO(0x9888), 0x00170020 },
+ { _MMIO(0x9888), 0x08170021 },
+ { _MMIO(0x9888), 0x10170000 },
+ { _MMIO(0x9888), 0x0633c000 },
+ { _MMIO(0x9888), 0x0833c000 },
+ { _MMIO(0x9888), 0x06370800 },
+ { _MMIO(0x9888), 0x08370840 },
+ { _MMIO(0x9888), 0x10370000 },
+ { _MMIO(0x9888), 0x1ace0200 },
+ { _MMIO(0x9888), 0x0aec5300 },
+ { _MMIO(0x9888), 0x10ec0000 },
+ { _MMIO(0x9888), 0x1cec0000 },
+ { _MMIO(0x9888), 0x0a9b8000 },
+ { _MMIO(0x9888), 0x1c9c0002 },
+ { _MMIO(0x9888), 0x0ccc0002 },
+ { _MMIO(0x9888), 0x0a8d8000 },
+ { _MMIO(0x9888), 0x108f0001 },
+ { _MMIO(0x9888), 0x16ac8000 },
+ { _MMIO(0x9888), 0x0d933031 },
+ { _MMIO(0x9888), 0x0f933e3f },
+ { _MMIO(0x9888), 0x01933d00 },
+ { _MMIO(0x9888), 0x0393073c },
+ { _MMIO(0x9888), 0x0593000e },
+ { _MMIO(0x9888), 0x1d930000 },
+ { _MMIO(0x9888), 0x19930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190003f },
+ { _MMIO(0x9888), 0x51907710 },
+ { _MMIO(0x9888), 0x419020a0 },
+ { _MMIO(0x9888), 0x55901515 },
+ { _MMIO(0x9888), 0x45900529 },
+ { _MMIO(0x9888), 0x47901025 },
+ { _MMIO(0x9888), 0x57907770 },
+ { _MMIO(0x9888), 0x49902100 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900108 },
+ { _MMIO(0x9888), 0x59900007 },
+ { _MMIO(0x9888), 0x43902108 },
+ { _MMIO(0x9888), 0x53907777 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_basic);
+ return mux_config_render_basic;
+}
+
+int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "4616d450-2393-4836-8146-53c5ed84d359",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.h b/drivers/gpu/drm/i915/i915_oa_sklgt3.h
new file mode 100644
index 000000000000..ff7ec3206bf2
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_SKLGT3_H__
+#define __I915_OA_SKLGT3_H__
+
+extern int i915_oa_n_builtin_metric_sets_sklgt3;
+
+extern int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
new file mode 100644
index 000000000000..eb78f1ea659f
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
@@ -0,0 +1,247 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_sklgt4.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+};
+
+int i915_oa_n_builtin_metric_sets_sklgt4 = 1;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x166c01e0 },
+ { _MMIO(0x9888), 0x12170280 },
+ { _MMIO(0x9888), 0x12370280 },
+ { _MMIO(0x9888), 0x16ec01e0 },
+ { _MMIO(0x9888), 0x176c01e0 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x1a4e03b0 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x0a1b4000 },
+ { _MMIO(0x9888), 0x1c1c0001 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x042f1000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4ca400 },
+ { _MMIO(0x9888), 0x0c4c0002 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f5600 },
+ { _MMIO(0x9888), 0x100f0001 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x062d8000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x08133000 },
+ { _MMIO(0x9888), 0x00170020 },
+ { _MMIO(0x9888), 0x08170021 },
+ { _MMIO(0x9888), 0x10170000 },
+ { _MMIO(0x9888), 0x0633c000 },
+ { _MMIO(0x9888), 0x06370800 },
+ { _MMIO(0x9888), 0x10370000 },
+ { _MMIO(0x9888), 0x1ace0230 },
+ { _MMIO(0x9888), 0x0aec5300 },
+ { _MMIO(0x9888), 0x10ec0000 },
+ { _MMIO(0x9888), 0x1cec0000 },
+ { _MMIO(0x9888), 0x0a9b8000 },
+ { _MMIO(0x9888), 0x1c9c0002 },
+ { _MMIO(0x9888), 0x0acc2000 },
+ { _MMIO(0x9888), 0x0ccc0002 },
+ { _MMIO(0x9888), 0x088d8000 },
+ { _MMIO(0x9888), 0x0a8d8000 },
+ { _MMIO(0x9888), 0x0e8f1000 },
+ { _MMIO(0x9888), 0x108f0001 },
+ { _MMIO(0x9888), 0x16ac8800 },
+ { _MMIO(0x9888), 0x1b4e0020 },
+ { _MMIO(0x9888), 0x096c5300 },
+ { _MMIO(0x9888), 0x116c0000 },
+ { _MMIO(0x9888), 0x1d6c0000 },
+ { _MMIO(0x9888), 0x091b8000 },
+ { _MMIO(0x9888), 0x1b1c8000 },
+ { _MMIO(0x9888), 0x0b4c2000 },
+ { _MMIO(0x9888), 0x090d8000 },
+ { _MMIO(0x9888), 0x0f0f1000 },
+ { _MMIO(0x9888), 0x172c0800 },
+ { _MMIO(0x9888), 0x0d933031 },
+ { _MMIO(0x9888), 0x0f933e3f },
+ { _MMIO(0x9888), 0x01933d00 },
+ { _MMIO(0x9888), 0x0393073c },
+ { _MMIO(0x9888), 0x0593000e },
+ { _MMIO(0x9888), 0x1d930000 },
+ { _MMIO(0x9888), 0x19930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190003f },
+ { _MMIO(0x9888), 0x5190ff30 },
+ { _MMIO(0x9888), 0x41900060 },
+ { _MMIO(0x9888), 0x55903033 },
+ { _MMIO(0x9888), 0x45901421 },
+ { _MMIO(0x9888), 0x47900803 },
+ { _MMIO(0x9888), 0x5790fff1 },
+ { _MMIO(0x9888), 0x49900001 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x5990000f },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x5390ffff },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_basic);
+ return mux_config_render_basic;
+}
+
+int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "bad77c24-cc64-480d-99bf-e7b740713800",
+ .attrs = attrs_render_basic,
+};
+
+int
+i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+
+ return 0;
+
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.h b/drivers/gpu/drm/i915/i915_oa_sklgt4.h
new file mode 100644
index 000000000000..4faa8c4579cd
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_SKLGT4_H__
+#define __I915_OA_SKLGT4_H__
+
+extern int i915_oa_n_builtin_metric_sets_sklgt4;
+
+extern int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv);
+
+#endif
--
2.11.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/6] drm/i915: Add OA unit support for Gen 8+
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
` (3 preceding siblings ...)
2017-02-22 16:36 ` [PATCH 4/6] drm/i915: Add 'render basic' Gen8+ OA unit configs Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-02-22 16:36 ` [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT Robert Bragg
2017-02-22 19:22 ` ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to manage synchronous state changes from the cpu while
there's no guarantee of what context (if any) is currently actively
running on the gpu.
The periodic sampling frequency which can be particularly useful for
system-wide analysis (as opposed to command stream synchronised
MI_REPORT_PERF_COUNT commands) is perhaps the most surprising state to
have become per-context save and restored (while the OABUFFER
destination is still a shared, system-wide resource).
This support for gen8+ takes care to consider a number of timing
challenges involved in synchronously updating per-context state
primarily by programming all config state from the cpu and updating all
current and saved contexts synchronously while the OA unit is still
disabled.
The driver intentionally avoids depending on command streamer
programming to update OA state considering the lack of synchronization
between the automatic loading of OACTXCONTROL state (that includes the
periodic sampling state and enable state) on context restore and the
parsing of any general purpose BB the driver can control. I.e. this
implementation is careful to avoid the possibility of a context restore
temporarily enabling any out-of-date periodic sampling state. In
addition to the risk of transiently-out-of-date state being loaded
automatically; there are also internal HW latencies involved in the
loading of MUX configurations which would be difficult to account for
from the command streamer (and we only want to enable the unit when once
the MUX configuration is complete).
Since the Gen8+ OA unit design no longer supports clock gating the unit
off for a single given context (which effectively stopped any progress
of counters while any other context was running) and instead supports
tagging OA reports with a context ID for filtering on the CPU, it means
we can no longer hide the system-wide progress of counters from a
non-privileged application only interested in metrics for its own
context. Although we could theoretically try and subtract the progress
of other contexts before forwarding reports via read() we aren't in a
position to filter reports captured via MI_REPORT_PERF_COUNT commands.
As a result, for Gen8+, we always require the
dev.i915.perf_stream_paranoid to be unset for any access to OA metrics
if not root.
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/i915_drv.h | 14 +
drivers/gpu/drm/i915/i915_gem_context.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1067 +++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 9 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +
include/uapi/drm/i915_drm.h | 19 +-
6 files changed, 1044 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5e084b46023..b6d617e308af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2443,6 +2443,7 @@ struct drm_i915_private {
struct {
struct i915_vma *vma;
u8 *vaddr;
+ u32 last_ctx_id;
int format;
int format_size;
@@ -2512,6 +2513,14 @@ struct drm_i915_private {
} oa_buffer;
u32 gen7_latched_oastatus1;
+ u32 ctx_oactxctrl_off;
+ u32 ctx_flexeu0_off;
+
+ /* The RPT_ID/reason field for Gen8+ includes a bit
+ * to determine if the CTX ID in the report is valid
+ * but the specific bit differs between Gen 8 and 9
+ */
+ u32 gen8_valid_ctx_bit;
struct i915_oa_ops ops;
const struct i915_oa_format *oa_formats;
@@ -2823,6 +2832,8 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
INTEL_DEVID(dev_priv) == 0x5915 || \
INTEL_DEVID(dev_priv) == 0x591E)
+#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
@@ -3566,6 +3577,9 @@ i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
+void i915_oa_update_reg_state(struct intel_engine_cs *engine,
+ struct i915_gem_context *ctx,
+ uint32_t *reg_state);
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index 0ac750b90f3d..32c7921faeb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -153,6 +153,7 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
bool initialised;
+ atomic_t oa_state_dirty;
} engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a901bcd80263..d1591e2ed735 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -196,6 +196,12 @@
#include "i915_drv.h"
#include "i915_oa_hsw.h"
+#include "i915_oa_bdw.h"
+#include "i915_oa_chv.h"
+#include "i915_oa_sklgt2.h"
+#include "i915_oa_sklgt3.h"
+#include "i915_oa_sklgt4.h"
+#include "i915_oa_bxt.h"
/* HW requires this to be a power of two, between 128k and 16M, though driver
* is currently generally designed assuming the largest 16M size is used such
@@ -272,6 +278,13 @@ static u32 i915_perf_stream_paranoid = true;
#define INVALID_CTX_ID 0xffffffff
+/* On Gen8+ automatically triggered OA reports include a 'reason' field... */
+#define OAREPORT_REASON_MASK 0x3f
+#define OAREPORT_REASON_SHIFT 19
+#define OAREPORT_REASON_TIMER (1<<0)
+#define OAREPORT_REASON_CTX_SWITCH (1<<3)
+#define OAREPORT_REASON_CLK_RATIO (1<<5)
+
/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
*
@@ -303,6 +316,13 @@ static struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_C4_B8] = { 7, 64 },
};
+static struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
+ [I915_OA_FORMAT_A12] = { 0, 64 },
+ [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
+ [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+ [I915_OA_FORMAT_C4_B8] = { 7, 64 },
+};
+
#define SAMPLE_OA_REPORT (1<<0)
/**
@@ -333,6 +353,122 @@ struct perf_open_properties {
};
/**
+ * gen8_oa_buffer_check_unlocked - check for data and update tail ptr state
+ * @dev_priv: i915 device instance
+ *
+ * This is either called via fops (for blocking reads in user ctx) or the poll
+ * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
+ * if there is data available for userspace to read.
+ *
+ * This function is central to providing a workaround for the OA unit tail
+ * pointer having a race with respect to what data is visible to the CPU.
+ * It is responsible for reading tail pointers from the hardware and giving
+ * the pointers time to 'age' before they are made available for reading.
+ * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
+ *
+ * Besides returning true when there is data available to read() this function
+ * also has the side effect of updating the oa_buffer.tails[], .aging_timestamp
+ * and .aged_tail_idx state used for reading.
+ *
+ * Note: It's safe to read OA config state here unlocked, assuming that this is
+ * only called while the stream is enabled, while the global OA configuration
+ * can't be modified.
+ *
+ * Returns: %true if the OA buffer contains data, else %false
+ */
+static bool gen8_oa_buffer_check_unlocked(struct drm_i915_private *dev_priv)
+{
+ int report_size = dev_priv->perf.oa.oa_buffer.format_size;
+ unsigned long flags;
+ unsigned int aged_idx;
+ u32 head, hw_tail, aged_tail, aging_tail;
+ u64 now;
+
+ /* We have to consider the (unlikely) possibility that read() errors
+ * could result in an OA buffer reset which might reset the head,
+ * tails[] and aged_tail state.
+ */
+ spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ /* NB: The head we observe here might effectively be a little out of
+ * date (between head and tails[aged_idx].offset if there is currently
+ * a read() in progress.
+ */
+ head = dev_priv->perf.oa.oa_buffer.head;
+
+ aged_idx = dev_priv->perf.oa.oa_buffer.aged_tail_idx;
+ aged_tail = dev_priv->perf.oa.oa_buffer.tails[aged_idx].offset;
+ aging_tail = dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset;
+
+ hw_tail = I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
+
+ /* The tail pointer increases in 64 byte increments,
+ * not in report_size steps...
+ */
+ hw_tail &= ~(report_size - 1);
+
+ now = ktime_get_mono_fast_ns();
+
+ /* Update the aged tail
+ *
+ * Flip the tail pointer available for read()s once the aging tail is
+ * old enough to trust that the corresponding data will be visible to
+ * the CPU...
+ *
+ * Do this before updating the aging pointer in case we may be able to
+ * immediately start aging a new pointer too (if new data has become
+ * available) without needing to wait for a later hrtimer callback.
+ */
+ if (aging_tail != INVALID_TAIL_PTR &&
+ ((now - dev_priv->perf.oa.oa_buffer.aging_timestamp) >
+ OA_TAIL_MARGIN_NSEC)) {
+
+ aged_idx ^= 1;
+ dev_priv->perf.oa.oa_buffer.aged_tail_idx = aged_idx;
+
+ aged_tail = aging_tail;
+
+ /* Mark that we need a new pointer to start aging... */
+ dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset = INVALID_TAIL_PTR;
+ aging_tail = INVALID_TAIL_PTR;
+ }
+
+ /* Update the aging tail
+ *
+ * We throttle aging tail updates until we have a new tail that
+ * represents >= one report more data than is already available for
+ * reading. This ensures there will be enough data for a successful
+ * read once this new pointer has aged and ensures we will give the new
+ * pointer time to age.
+ */
+ if (aging_tail == INVALID_TAIL_PTR &&
+ (aged_tail == INVALID_TAIL_PTR ||
+ OA_TAKEN(hw_tail, aged_tail) >= report_size)) {
+ struct i915_vma *vma = dev_priv->perf.oa.oa_buffer.vma;
+ u32 gtt_offset = i915_ggtt_offset(vma);
+
+ /* Be paranoid and do a bounds check on the pointer read back
+ * from hardware, just in case some spurious hardware condition
+ * could put the tail out of bounds...
+ */
+ if (hw_tail >= gtt_offset &&
+ hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
+ dev_priv->perf.oa.oa_buffer.tails[!aged_idx].offset =
+ aging_tail = hw_tail;
+ dev_priv->perf.oa.oa_buffer.aging_timestamp = now;
+ } else {
+ DRM_ERROR("Ignoring spurious out of range OA buffer tail pointer = %u\n",
+ hw_tail);
+ }
+ }
+
+ spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ return aged_tail == INVALID_TAIL_PTR ?
+ false : OA_TAKEN(aged_tail, head) >= report_size;
+}
+
+/**
* gen7_oa_buffer_check_unlocked - check for data and update tail ptr state
* @dev_priv: i915 device instance
*
@@ -530,7 +666,284 @@ static int append_oa_sample(struct i915_perf_stream *stream,
(*offset) += header.size;
- return 0;
+ return 0;
+}
+
+/**
+ * Copies all buffered OA reports into userspace read() buffer.
+ * @stream: An i915-perf stream opened for OA metrics
+ * @buf: destination buffer given by userspace
+ * @count: the number of bytes userspace wants to read
+ * @offset: (inout): the current position for writing into @buf
+ *
+ * Notably any error condition resulting in a short read (-%ENOSPC or
+ * -%EFAULT) will be returned even though one or more records may
+ * have been successfully copied. In this case it's up to the caller
+ * to decide if the error should be squashed before returning to
+ * userspace.
+ *
+ * Note: reports are consumed from the head, and appended to the
+ * tail, so the tail chases the head?... If you think that's mad
+ * and back-to-front you're not alone, but this follows the
+ * Gen PRM naming convention.
+ *
+ * Returns: 0 on success, negative error code on failure.
+ */
+static int gen8_append_oa_reports(struct i915_perf_stream *stream,
+ char __user *buf,
+ size_t count,
+ size_t *offset)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ int report_size = dev_priv->perf.oa.oa_buffer.format_size;
+ u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
+ u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
+ u32 mask = (OA_BUFFER_SIZE - 1);
+ size_t start_offset = *offset;
+ unsigned long flags;
+ unsigned int aged_tail_idx;
+ u32 head, tail;
+ u32 taken;
+ int ret = 0;
+
+ if (WARN_ON(!stream->enabled))
+ return -EIO;
+
+ spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ head = dev_priv->perf.oa.oa_buffer.head;
+ aged_tail_idx = dev_priv->perf.oa.oa_buffer.aged_tail_idx;
+ tail = dev_priv->perf.oa.oa_buffer.tails[aged_tail_idx].offset;
+
+ spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ /* An invalid tail pointer here means we're still waiting for the poll
+ * hrtimer callback to give us a pointer
+ */
+ if (tail == INVALID_TAIL_PTR)
+ return -EAGAIN;
+
+ /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
+ * while indexing relative to oa_buf_base.
+ */
+ head -= gtt_offset;
+ tail -= gtt_offset;
+
+ /* An out of bounds or misaligned head or tail pointer implies a driver
+ * bug since we validate + align the tail pointers we read from the
+ * hardware and we are in full control of the head pointer which should
+ * only be incremented by multiples of the report size (notably also
+ * all a power of two).
+ */
+ if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
+ tail > OA_BUFFER_SIZE || tail % report_size,
+ "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
+ head, tail))
+ return -EIO;
+
+
+ for (/* none */;
+ (taken = OA_TAKEN(tail, head));
+ head = (head + report_size) & mask) {
+ u8 *report = oa_buf_base + head;
+ u32 *report32 = (void *)report;
+ u32 ctx_id;
+ u32 reason;
+
+ /* All the report sizes factor neatly into the buffer
+ * size so we never expect to see a report split
+ * between the beginning and end of the buffer.
+ *
+ * Given the initial alignment check a misalignment
+ * here would imply a driver bug that would result
+ * in an overrun.
+ */
+ if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
+ DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
+ break;
+ }
+
+ /* The reason field includes flags identifying what
+ * triggered this specific report (mostly timer
+ * triggered or e.g. due to a context switch).
+ *
+ * This field is never expected to be zero so we can
+ * check that the report isn't invalid before copying
+ * it to userspace...
+ */
+ reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
+ OAREPORT_REASON_MASK);
+ if (reason == 0) {
+ if (printk_ratelimit())
+ DRM_NOTE("Skipping spurious, invalid OA report\n");
+ continue;
+ }
+
+ /* XXX: Just keep the lower 21 bits for now since I'm not
+ * entirely sure if the HW touches any of the higher bits in
+ * this field
+ */
+ ctx_id = report32[2] & 0x1fffff;
+
+ /* Squash whatever is in the CTX_ID field if it's
+ * marked as invalid to be sure we avoid
+ * false-positive, single-context filtering below...
+ */
+ if (!(report32[0] & dev_priv->perf.oa.gen8_valid_ctx_bit))
+ ctx_id = report32[2] = INVALID_CTX_ID;
+
+ /* NB: For Gen 8 the OA unit no longer supports clock gating
+ * off for a specific context and the kernel can't securely
+ * stop the counters from updating as system-wide / global
+ * values.
+ *
+ * Automatic reports now include a context ID so reports can be
+ * filtered on the cpu but it's not worth trying to
+ * automatically subtract/hide counter progress for other
+ * contexts while filtering since we can't stop userspace
+ * issuing MI_REPORT_PERF_COUNT commands which would still
+ * provide a side-band view of the real values.
+ *
+ * To allow userspace (such as Mesa/GL_INTEL_performance_query)
+ * to normalize counters for a single filtered context then it
+ * needs be forwarded bookend context-switch reports so that it
+ * can track switches in between MI_REPORT_PERF_COUNT commands
+ * and can itself subtract/ignore the progress of counters
+ * associated with other contexts. Note that the hardware
+ * automatically triggers reports when switching to a new
+ * context which are tagged with the ID of the newly active
+ * context. To avoid the complexity (and likely fragility) of
+ * reading ahead while parsing reports to try and minimize
+ * forwarding redundant context switch reports (i.e. between
+ * other, unrelated contexts) we simply elect to forward them
+ * all.
+ *
+ * We don't rely solely on the reason field to identify context
+ * switches since it's not-uncommon for periodic samples to
+ * identify a switch before any 'context switch' report.
+ */
+ if (!dev_priv->perf.oa.exclusive_stream->ctx ||
+ dev_priv->perf.oa.specific_ctx_id == ctx_id ||
+ (dev_priv->perf.oa.oa_buffer.last_ctx_id ==
+ dev_priv->perf.oa.specific_ctx_id) ||
+ reason & OAREPORT_REASON_CTX_SWITCH) {
+
+ /* While filtering for a single context we avoid
+ * leaking the IDs of other contexts.
+ */
+ if (dev_priv->perf.oa.exclusive_stream->ctx &&
+ dev_priv->perf.oa.specific_ctx_id != ctx_id) {
+ report32[2] = INVALID_CTX_ID;
+ }
+
+ ret = append_oa_sample(stream, buf, count, offset,
+ report);
+ if (ret)
+ break;
+
+ dev_priv->perf.oa.oa_buffer.last_ctx_id = ctx_id;
+ }
+
+ /* The above reason field sanity check is based on
+ * the assumption that the OA buffer is initially
+ * zeroed and we reset the field after copying so the
+ * check is still meaningful once old reports start
+ * being overwritten.
+ */
+ report32[0] = 0;
+ }
+
+ if (start_offset != *offset) {
+ spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ /* We removed the gtt_offset for the copy loop above, indexing
+ * relative to oa_buf_base so put back here...
+ */
+ head += gtt_offset;
+
+ I915_WRITE(GEN8_OAHEADPTR, head & GEN8_OAHEADPTR_MASK);
+ dev_priv->perf.oa.oa_buffer.head = head;
+
+ spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+ }
+
+ return ret;
+}
+
+/**
+ * gen8_oa_read - copy status records then buffered OA reports
+ * @stream: An i915-perf stream opened for OA metrics
+ * @buf: destination buffer given by userspace
+ * @count: the number of bytes userspace wants to read
+ * @offset: (inout): the current position for writing into @buf
+ *
+ * Checks OA unit status registers and if necessary appends corresponding
+ * status records for userspace (such as for a buffer full condition) and then
+ * initiate appending any buffered OA reports.
+ *
+ * Updates @offset according to the number of bytes successfully copied into
+ * the userspace buffer.
+ *
+ * NB: some data may be successfully copied to the userspace buffer
+ * even if an error is returned, and this is reflected in the
+ * updated @read_state.
+ *
+ * Returns: zero on success or a negative error code
+ */
+static int gen8_oa_read(struct i915_perf_stream *stream,
+ char __user *buf,
+ size_t count,
+ size_t *offset)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ u32 oastatus;
+ int ret;
+
+ if (WARN_ON(!dev_priv->perf.oa.oa_buffer.vaddr))
+ return -EIO;
+
+ oastatus = I915_READ(GEN8_OASTATUS);
+
+ /* We treat OABUFFER_OVERFLOW as a significant error:
+ *
+ * Although theoretically we could handle this more gracefully
+ * sometimes, some Gens don't correctly suppress certain
+ * automatically triggered reports in this condition and so we
+ * have to assume that old reports are now being trampled
+ * over.
+ *
+ * Considering how we don't currently give userspace control
+ * over the OA buffer size and always configure a large 16MB
+ * buffer, then a buffer overflow does anyway likely indicate
+ * that something has gone quite badly wrong.
+ */
+ if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
+ ret = append_oa_status(stream, buf, count, offset,
+ DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
+ if (ret)
+ return ret;
+
+ DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
+ dev_priv->perf.oa.period_exponent);
+
+ dev_priv->perf.oa.ops.oa_disable(dev_priv);
+ dev_priv->perf.oa.ops.oa_enable(dev_priv);
+
+ /* Note: .oa_enable() is expected to re-init the oabuffer
+ * and reset GEN8_OASTATUS for us */
+ oastatus = I915_READ(GEN8_OASTATUS);
+ }
+
+ if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
+ ret = append_oa_status(stream, buf, count, offset,
+ DRM_I915_PERF_RECORD_OA_REPORT_LOST);
+ if (ret == 0) {
+ I915_WRITE(GEN8_OASTATUS,
+ oastatus & ~GEN8_OASTATUS_REPORT_LOST);
+ }
+ }
+
+ return gen8_append_oa_reports(stream, buf, count, offset);
}
/**
@@ -733,7 +1146,8 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
if (ret)
return ret;
- DRM_DEBUG("OA buffer overflow: force restart\n");
+ DRM_DEBUG("OA buffer overflow (exponent = %d): force restart\n",
+ dev_priv->perf.oa.period_exponent);
dev_priv->perf.oa.ops.oa_disable(dev_priv);
dev_priv->perf.oa.ops.oa_enable(dev_priv);
@@ -833,33 +1247,37 @@ static int i915_oa_read(struct i915_perf_stream *stream,
static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
- struct intel_engine_cs *engine = dev_priv->engine[RCS];
- int ret;
- ret = i915_mutex_lock_interruptible(&dev_priv->drm);
- if (ret)
- return ret;
+ if (i915.enable_execlists)
+ dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id;
+ else {
+ struct intel_engine_cs *engine = dev_priv->engine[RCS];
+ int ret;
- /* As the ID is the gtt offset of the context's vma we pin
- * the vma to ensure the ID remains fixed.
- *
- * NB: implied RCS engine...
- */
- ret = engine->context_pin(engine, stream->ctx);
- if (ret)
- goto unlock;
+ ret = i915_mutex_lock_interruptible(&dev_priv->drm);
+ if (ret)
+ return ret;
- /* Explicitly track the ID (instead of calling i915_ggtt_offset()
- * on the fly) considering the difference with gen8+ and
- * execlists
- */
- dev_priv->perf.oa.specific_ctx_id =
- i915_ggtt_offset(stream->ctx->engine[engine->id].state);
+ /* As the ID is the gtt offset of the context's vma we pin
+ * the vma to ensure the ID remains fixed.
+ */
+ ret = engine->context_pin(engine, stream->ctx);
+ if (ret) {
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ return ret;
+ }
-unlock:
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ /* Explicitly track the ID (instead of calling
+ * i915_ggtt_offset() on the fly) considering the difference
+ * with gen8+ and execlists
+ */
+ dev_priv->perf.oa.specific_ctx_id =
+ i915_ggtt_offset(stream->ctx->engine[engine->id].state);
- return ret;
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ }
+
+ return 0;
}
/**
@@ -874,12 +1292,16 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
struct drm_i915_private *dev_priv = stream->dev_priv;
struct intel_engine_cs *engine = dev_priv->engine[RCS];
- mutex_lock(&dev_priv->drm.struct_mutex);
+ if (i915.enable_execlists) {
+ dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
+ } else {
+ mutex_lock(&dev_priv->drm.struct_mutex);
- dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
- engine->context_unpin(engine, stream->ctx);
+ dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
+ engine->context_unpin(engine, stream->ctx);
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ }
}
static void
@@ -964,6 +1386,56 @@ static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.pollin = false;
}
+static void gen8_init_oa_buffer(struct drm_i915_private *dev_priv)
+{
+ u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+ I915_WRITE(GEN8_OASTATUS, 0);
+ I915_WRITE(GEN8_OAHEADPTR, gtt_offset);
+ dev_priv->perf.oa.oa_buffer.head = gtt_offset;
+
+ I915_WRITE(GEN8_OABUFFER_UDW, 0);
+
+ /* PRM says:
+ *
+ * "This MMIO must be set before the OATAILPTR
+ * register and after the OAHEADPTR register. This is
+ * to enable proper functionality of the overflow
+ * bit."
+ */
+ I915_WRITE(GEN8_OABUFFER, gtt_offset |
+ OABUFFER_SIZE_16M | OA_MEM_SELECT_GGTT);
+ I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
+
+ /* Mark that we need updated tail pointers to read from... */
+ dev_priv->perf.oa.oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
+ dev_priv->perf.oa.oa_buffer.tails[1].offset = INVALID_TAIL_PTR;
+
+ spin_unlock_irqrestore(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
+
+
+ /* NB: although the OA buffer will initially be allocated
+ * zeroed via shmfs (and so this memset is redundant when
+ * first allocating), we may re-init the OA buffer, either
+ * when re-enabling a stream or in error/reset paths.
+ *
+ * The reason we clear the buffer for each re-init is for the
+ * sanity check in gen8_append_oa_reports() that looks at the
+ * reason field to make sure it's non-zero which relies on
+ * the assumption that new reports are being written to zeroed
+ * memory...
+ */
+ memset(dev_priv->perf.oa.oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
+
+ /* Maybe make ->pollin per-stream state if we support multiple
+ * concurrent streams in the future.
+ */
+ dev_priv->perf.oa.pollin = false;
+}
+
static int alloc_oa_buffer(struct drm_i915_private *dev_priv)
{
struct drm_i915_gem_object *bo;
@@ -1108,6 +1580,260 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv)
~GT_NOA_ENABLE));
}
+/* Manages updating the per-context aspects of the OA stream
+ * configuration across all contexts.
+ *
+ * The awkward consideration here is that OACTXCONTROL controls the
+ * exponent for periodic sampling which is primarily used for system
+ * wide profiling where we'd like a consistent sampling period even in
+ * the face of context switches.
+ *
+ * Our approach of updating the register state context (as opposed to
+ * say using a workaround batch buffer) ensures that the hardware
+ * won't automatically reload an out-of-date timer exponent even
+ * transiently before a WA BB could be parsed.
+ */
+static int configure_all_contexts(struct drm_i915_private *dev_priv)
+{
+ struct i915_gem_context *ctx;
+ int ret;
+
+ ret = i915_mutex_lock_interruptible(&dev_priv->drm);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(ctx, &dev_priv->context_list, link) {
+ int i;
+
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
+ /* The actual update of the register state context
+ * will happen the next time this logical ring
+ * is submitted. (See i915_oa_update_reg_state()
+ * which hooks into execlists_update_context())
+ */
+ atomic_set(&ctx->engine[i].oa_state_dirty, true);
+ }
+ }
+
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
+ /* Now update the current context.
+ *
+ * Note: Using MMIO to update per-context registers requires
+ * some extra care...
+ */
+ ret = intel_uncore_begin_ctx_mmio(dev_priv);
+ if (ret) {
+ DRM_ERROR("Failed to bring RCS out of idle to update current ctx OA state");
+ return ret;
+ }
+
+ I915_WRITE(GEN8_OACTXCONTROL, ((dev_priv->perf.oa.period_exponent <<
+ GEN8_OA_TIMER_PERIOD_SHIFT) |
+ (dev_priv->perf.oa.periodic ?
+ GEN8_OA_TIMER_ENABLE : 0) |
+ GEN8_OA_COUNTER_RESUME));
+
+ config_oa_regs(dev_priv, dev_priv->perf.oa.flex_regs,
+ dev_priv->perf.oa.flex_regs_len);
+
+ intel_uncore_end_ctx_mmio(dev_priv);
+
+ return 0;
+}
+
+static int bdw_enable_metric_set(struct drm_i915_private *dev_priv)
+{
+ int ret = i915_oa_select_metric_set_bdw(dev_priv);
+
+ if (ret)
+ return ret;
+
+ I915_WRITE(GDT_CHICKEN_BITS, 0xA0);
+ config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_len);
+ I915_WRITE(GDT_CHICKEN_BITS, 0x80);
+
+ /* It takes a fairly long time for a new MUX configuration to
+ * be be applied after these register writes. This delay
+ * duration is take from Haswell (derived empirically based on
+ * the render_basic config) but hopefully it covers the
+ * maximum configuration latency on BDW too...
+ */
+ usleep_range(15000, 20000);
+
+ config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
+ dev_priv->perf.oa.b_counter_regs_len);
+
+ configure_all_contexts(dev_priv);
+
+ return 0;
+}
+
+static void bdw_disable_metric_set(struct drm_i915_private *dev_priv)
+{
+ /* NOP */
+}
+
+static int chv_enable_metric_set(struct drm_i915_private *dev_priv)
+{
+ int ret = i915_oa_select_metric_set_chv(dev_priv);
+
+ if (ret)
+ return ret;
+
+ I915_WRITE(GDT_CHICKEN_BITS, 0xA0);
+ config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_len);
+ I915_WRITE(GDT_CHICKEN_BITS, 0x80);
+
+ /* It takes a fairly long time for a new MUX configuration to
+ * be be applied after these register writes. This delay
+ * duration is take from Haswell (derived empirically based on
+ * the render_basic config) but hopefully it covers the
+ * maximum configuration latency on CHV too...
+ */
+ usleep_range(15000, 20000);
+
+ config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
+ dev_priv->perf.oa.b_counter_regs_len);
+
+ configure_all_contexts(dev_priv);
+
+ return 0;
+}
+
+static void chv_disable_metric_set(struct drm_i915_private *dev_priv)
+{
+ /* NOP */
+}
+
+static int skl_enable_metric_set(struct drm_i915_private *dev_priv)
+{
+ if (IS_SKL_GT2(dev_priv)) {
+ int ret = i915_oa_select_metric_set_sklgt2(dev_priv);
+ if (ret)
+ return ret;
+ } else if (IS_SKL_GT3(dev_priv)) {
+ int ret = i915_oa_select_metric_set_sklgt3(dev_priv);
+ if (ret)
+ return ret;
+ } else if (IS_SKL_GT4(dev_priv)) {
+ int ret = i915_oa_select_metric_set_sklgt4(dev_priv);
+ if (ret)
+ return ret;
+ } else
+ return -ENOTSUPP;
+
+ /* We disable slice/unslice clock ratio change reports on SKL since
+ * they are too noisy. The HW generates a lot redundant reports where
+ * the ratio hasn't really changed causing a lot of redundant work to
+ * processes and increasing the chances we'll hit buffer overruns.
+ *
+ * Although we don't currently use the 'disable overrun' OABUFFER
+ * feature it's worth noting that clock ratio reports have to be
+ * disabled before considering to use that feature since the HW doesn't
+ * correctly block these reports.
+ *
+ * Currently none of the high-level metrics we have depend on knowing
+ * this ratio to normalize.
+ *
+ * Note: This register is not power context saved and restored, but
+ * that's OK considering that we disable RC6 while the OA unit is
+ * enabled.
+ *
+ * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
+ * be read back from automatically triggered reports, as part of the
+ * RPT_ID field.
+ */
+ I915_WRITE(GEN8_OA_DEBUG,
+ _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
+ GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
+
+ I915_WRITE(GDT_CHICKEN_BITS, 0xA0);
+ config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_len);
+ I915_WRITE(GDT_CHICKEN_BITS, 0x80);
+
+ /* It takes a fairly long time for a new MUX configuration to
+ * be be applied after these register writes. This delay
+ * duration is take from Haswell (derived empirically based on
+ * the render_basic config) but hopefully it covers the
+ * maximum configuration latency on CHV too...
+ */
+ usleep_range(15000, 20000);
+
+ config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
+ dev_priv->perf.oa.b_counter_regs_len);
+
+ configure_all_contexts(dev_priv);
+
+ return 0;
+}
+
+static void skl_disable_metric_set(struct drm_i915_private *dev_priv)
+{
+ /* NOP */
+}
+
+static int bxt_enable_metric_set(struct drm_i915_private *dev_priv)
+{
+ int ret = i915_oa_select_metric_set_bxt(dev_priv);
+
+ if (ret)
+ return ret;
+
+ /* We disable slice/unslice clock ratio change reports on SKL since
+ * they are too noisy. The HW generates a lot redundant reports where
+ * the ratio hasn't really changed causing a lot of redundant work to
+ * processes and increasing the chances we'll hit buffer overruns.
+ *
+ * Although we don't currently use the 'disable overrun' OABUFFER
+ * feature it's worth noting that clock ratio reports have to be
+ * disabled before considering to use that feature since the HW doesn't
+ * correctly block these reports.
+ *
+ * Currently none of the high-level metrics we have depend on knowing
+ * this ratio to normalize.
+ *
+ * Note: This register is not power context saved and restored, but
+ * that's OK considering that we disable RC6 while the OA unit is
+ * enabled.
+ *
+ * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
+ * be read back from automatically triggered reports, as part of the
+ * RPT_ID field.
+ */
+ I915_WRITE(GEN8_OA_DEBUG,
+ _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
+ GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
+
+ I915_WRITE(GDT_CHICKEN_BITS, 0xA0);
+ config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_len);
+ I915_WRITE(GDT_CHICKEN_BITS, 0x80);
+
+ /* It takes a fairly long time for a new MUX configuration to
+ * be be applied after these register writes. This delay
+ * duration is take from Haswell (derived empirically based on
+ * the render_basic config) but hopefully it covers the
+ * maximum configuration latency on CHV too...
+ */
+ usleep_range(15000, 20000);
+
+ config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs,
+ dev_priv->perf.oa.b_counter_regs_len);
+
+ configure_all_contexts(dev_priv);
+
+ return 0;
+}
+
+static void bxt_disable_metric_set(struct drm_i915_private *dev_priv)
+{
+ /* NOP */
+}
+
static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv)
{
assert_spin_locked(&dev_priv->perf.hook_lock);
@@ -1152,6 +1878,29 @@ static void gen7_oa_enable(struct drm_i915_private *dev_priv)
spin_unlock_irqrestore(&dev_priv->perf.hook_lock, flags);
}
+static void gen8_oa_enable(struct drm_i915_private *dev_priv)
+{
+ u32 report_format = dev_priv->perf.oa.oa_buffer.format;
+
+ /* Reset buf pointers so we don't forward reports from before now.
+ *
+ * Think carefully if considering trying to avoid this, since it
+ * also ensures status flags and the buffer itself are cleared
+ * in error paths, and we have checks for invalid reports based
+ * on the assumption that certain fields are written to zeroed
+ * memory which this helps maintains.
+ */
+ gen8_init_oa_buffer(dev_priv);
+
+ /* Note: we don't rely on the hardware to perform single context
+ * filtering and instead filter on the cpu based on the context-id
+ * field of reports
+ */
+ I915_WRITE(GEN8_OACONTROL, (report_format <<
+ GEN8_OA_REPORT_FORMAT_SHIFT) |
+ GEN8_OA_COUNTER_ENABLE);
+}
+
/**
* i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
* @stream: An i915 perf stream opened for OA metrics
@@ -1178,6 +1927,11 @@ static void gen7_oa_disable(struct drm_i915_private *dev_priv)
I915_WRITE(GEN7_OACONTROL, 0);
}
+static void gen8_oa_disable(struct drm_i915_private *dev_priv)
+{
+ I915_WRITE(GEN8_OACONTROL, 0);
+}
+
/**
* i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
* @stream: An i915 perf stream opened for OA metrics
@@ -1336,6 +2090,74 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return ret;
}
+static void gen8_update_reg_state_unlocked(struct intel_engine_cs *engine,
+ struct i915_gem_context *ctx,
+ uint32_t *reg_state)
+{
+ struct drm_i915_private *dev_priv = ctx->i915;
+ const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs;
+ int n_flex_regs = dev_priv->perf.oa.flex_regs_len;
+ int ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_off;
+ int ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_off;
+ int i;
+
+ if (!atomic_read(&ctx->engine[engine->id].oa_state_dirty))
+ return;
+
+ reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL);
+ reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent <<
+ GEN8_OA_TIMER_PERIOD_SHIFT) |
+ (dev_priv->perf.oa.periodic ?
+ GEN8_OA_TIMER_ENABLE : 0) |
+ GEN8_OA_COUNTER_RESUME;
+
+ for (i = 0; i < n_flex_regs; i++) {
+ uint32_t offset = i915_mmio_reg_offset(flex_regs[i].addr);
+
+ /* Map from mmio address to register state context
+ * offset...
+ */
+
+ offset -= i915_mmio_reg_offset(EU_PERF_CNTL0);
+
+ /* Flex EU mmio registers are separated by 256 bytes */
+ offset /= 256;
+
+ /* This offset is in dwords not bytes */
+ offset *= 2;
+
+ /* EU_PERF_CNTL0 offset in register state context... */
+ offset += ctx_flexeu0;
+
+ reg_state[offset] = i915_mmio_reg_offset(flex_regs[i].addr);
+ reg_state[offset+1] = flex_regs[i].value;
+ }
+
+ atomic_set(&ctx->engine[engine->id].oa_state_dirty, false);
+}
+
+void i915_oa_update_reg_state(struct intel_engine_cs *engine,
+ struct i915_gem_context *ctx,
+ uint32_t *reg_state)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ if (!dev_priv->perf.initialized)
+ return;
+
+ /* XXX: We don't take a lock here and this may run async with
+ * respect to stream methods. Notably we don't want to block
+ * context switches by long i915 perf read() operations.
+ *
+ * It's expect to always be safe to read the dev_priv->perf
+ * state needed here, and expected to be benign to redundantly
+ * update the state if the OA unit has been disabled since
+ * oa_state_dirty was last set.
+ */
+
+ gen8_update_reg_state_unlocked(engine, ctx, reg_state);
+}
+
/**
* i915_perf_read_locked - &i915_perf_stream_ops->read with error normalisation
* @stream: An i915 perf stream
@@ -1750,6 +2572,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
struct i915_gem_context *specific_ctx = NULL;
struct i915_perf_stream *stream = NULL;
unsigned long f_flags = 0;
+ bool privileged_op = true;
int stream_fd;
int ret;
@@ -1767,12 +2590,28 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
}
}
+ /* On Haswell the OA unit supports clock gating off for a specific
+ * context and in this mode there's no visibility of metrics for the
+ * rest of the system, which we consider acceptable for a
+ * non-privileged client.
+ *
+ * For Gen8+ the OA unit no longer supports clock gating off for a
+ * specific context and the kernel can't securely stop the counters
+ * from updating as system-wide / global values. Even though we can
+ * filter reports based on the included context ID we can't block
+ * clients from seeing the raw / global counter values via
+ * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
+ * enable the OA unit by default.
+ */
+ if (IS_HASWELL(dev_priv) && specific_ctx)
+ privileged_op = false;
+
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a dev.i915.perf_stream_paranoid sysctl option
* to determine if it's ok to access system wide OA counters
* without CAP_SYS_ADMIN privileges.
*/
- if (!specific_ctx &&
+ if (privileged_op &&
i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
DRM_DEBUG("Insufficient privileges to open system-wide i915 perf stream\n");
ret = -EACCES;
@@ -2039,9 +2878,6 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data,
*/
void i915_perf_register(struct drm_i915_private *dev_priv)
{
- if (!IS_HASWELL(dev_priv))
- return;
-
if (!dev_priv->perf.initialized)
return;
@@ -2057,11 +2893,38 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
goto exit;
- if (i915_perf_register_sysfs_hsw(dev_priv)) {
- kobject_put(dev_priv->perf.metrics_kobj);
- dev_priv->perf.metrics_kobj = NULL;
+ if (IS_HASWELL(dev_priv)) {
+ if (i915_perf_register_sysfs_hsw(dev_priv))
+ goto sysfs_error;
+ } else if (IS_BROADWELL(dev_priv)) {
+ if (i915_perf_register_sysfs_bdw(dev_priv))
+ goto sysfs_error;
+ } else if (IS_CHERRYVIEW(dev_priv)) {
+ if (i915_perf_register_sysfs_chv(dev_priv))
+ goto sysfs_error;
+ } else if (IS_SKYLAKE(dev_priv)) {
+ if (IS_SKL_GT2(dev_priv)) {
+ if (i915_perf_register_sysfs_sklgt2(dev_priv))
+ goto sysfs_error;
+ } else if (IS_SKL_GT3(dev_priv)) {
+ if (i915_perf_register_sysfs_sklgt3(dev_priv))
+ goto sysfs_error;
+ } else if (IS_SKL_GT4(dev_priv)) {
+ if (i915_perf_register_sysfs_sklgt4(dev_priv))
+ goto sysfs_error;
+ } else
+ goto sysfs_error;
+ } else if (IS_BROXTON(dev_priv)) {
+ if (i915_perf_register_sysfs_bxt(dev_priv))
+ goto sysfs_error;
}
+ goto exit;
+
+sysfs_error:
+ kobject_put(dev_priv->perf.metrics_kobj);
+ dev_priv->perf.metrics_kobj = NULL;
+
exit:
mutex_unlock(&dev_priv->perf.lock);
}
@@ -2077,13 +2940,24 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
*/
void i915_perf_unregister(struct drm_i915_private *dev_priv)
{
- if (!IS_HASWELL(dev_priv))
- return;
-
if (!dev_priv->perf.metrics_kobj)
return;
- i915_perf_unregister_sysfs_hsw(dev_priv);
+ if (IS_HASWELL(dev_priv))
+ i915_perf_unregister_sysfs_hsw(dev_priv);
+ else if (IS_BROADWELL(dev_priv))
+ i915_perf_unregister_sysfs_bdw(dev_priv);
+ else if (IS_CHERRYVIEW(dev_priv))
+ i915_perf_unregister_sysfs_chv(dev_priv);
+ else if (IS_SKYLAKE(dev_priv)) {
+ if (IS_SKL_GT2(dev_priv))
+ i915_perf_unregister_sysfs_sklgt2(dev_priv);
+ else if (IS_SKL_GT3(dev_priv))
+ i915_perf_unregister_sysfs_sklgt3(dev_priv);
+ else if (IS_SKL_GT4(dev_priv))
+ i915_perf_unregister_sysfs_sklgt4(dev_priv);
+ } else if (IS_BROXTON(dev_priv))
+ i915_perf_unregister_sysfs_bxt(dev_priv);
kobject_put(dev_priv->perf.metrics_kobj);
dev_priv->perf.metrics_kobj = NULL;
@@ -2142,36 +3016,102 @@ static struct ctl_table dev_root[] = {
*/
void i915_perf_init(struct drm_i915_private *dev_priv)
{
- if (!IS_HASWELL(dev_priv))
- return;
-
- hrtimer_init(&dev_priv->perf.oa.poll_check_timer,
- CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb;
- init_waitqueue_head(&dev_priv->perf.oa.poll_wq);
+ dev_priv->perf.oa.n_builtin_sets = 0;
+
+ if (IS_HASWELL(dev_priv)) {
+ dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer;
+ dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set;
+ dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set;
+ dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable;
+ dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable;
+ dev_priv->perf.oa.ops.read = gen7_oa_read;
+ dev_priv->perf.oa.ops.oa_buffer_check =
+ gen7_oa_buffer_check_unlocked;
+
+ dev_priv->perf.oa.oa_formats = hsw_oa_formats;
+
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_hsw;
+ } else if (i915.enable_execlists) {
+ if (IS_BROADWELL(dev_priv)) {
+ dev_priv->perf.oa.ops.enable_metric_set =
+ bdw_enable_metric_set;
+ dev_priv->perf.oa.ops.disable_metric_set =
+ bdw_disable_metric_set;
+ dev_priv->perf.oa.ctx_oactxctrl_off = 0x120;
+ dev_priv->perf.oa.ctx_flexeu0_off = 0x2ce;
+ dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_bdw;
+ } else if (IS_CHERRYVIEW(dev_priv)) {
+ dev_priv->perf.oa.ops.enable_metric_set =
+ chv_enable_metric_set;
+ dev_priv->perf.oa.ops.disable_metric_set =
+ chv_disable_metric_set;
+ dev_priv->perf.oa.ctx_oactxctrl_off = 0x120;
+ dev_priv->perf.oa.ctx_flexeu0_off = 0x2ce;
+ dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_chv;
+ } else if (IS_SKYLAKE(dev_priv)) {
+ dev_priv->perf.oa.ops.enable_metric_set =
+ skl_enable_metric_set;
+ dev_priv->perf.oa.ops.disable_metric_set =
+ skl_disable_metric_set;
+ dev_priv->perf.oa.ctx_oactxctrl_off = 0x128;
+ dev_priv->perf.oa.ctx_flexeu0_off = 0x3de;
+ dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
+
+
+ if (IS_SKL_GT2(dev_priv)) {
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_sklgt2;
+ } else if (IS_SKL_GT3(dev_priv)) {
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_sklgt3;
+ } else if (IS_SKL_GT4(dev_priv)) {
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_sklgt4;
+ }
+ } else if (IS_BROXTON(dev_priv)) {
+ dev_priv->perf.oa.ops.enable_metric_set =
+ bxt_enable_metric_set;
+ dev_priv->perf.oa.ops.disable_metric_set =
+ bxt_disable_metric_set;
+ dev_priv->perf.oa.ctx_oactxctrl_off = 0x128;
+ dev_priv->perf.oa.ctx_flexeu0_off = 0x3de;
+ dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_bxt;
+ }
- INIT_LIST_HEAD(&dev_priv->perf.streams);
- mutex_init(&dev_priv->perf.lock);
- spin_lock_init(&dev_priv->perf.hook_lock);
- spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
+ if (dev_priv->perf.oa.n_builtin_sets) {
+ dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer;
+ dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable;
+ dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable;
+ dev_priv->perf.oa.ops.read = gen8_oa_read;
+ dev_priv->perf.oa.ops.oa_buffer_check =
+ gen8_oa_buffer_check_unlocked;
- dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer;
- dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set;
- dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set;
- dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable;
- dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable;
- dev_priv->perf.oa.ops.read = gen7_oa_read;
- dev_priv->perf.oa.ops.oa_buffer_check =
- gen7_oa_buffer_check_unlocked;
+ dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats;
+ }
+ }
- dev_priv->perf.oa.oa_formats = hsw_oa_formats;
+ if (dev_priv->perf.oa.n_builtin_sets) {
+ hrtimer_init(&dev_priv->perf.oa.poll_check_timer,
+ CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb;
+ init_waitqueue_head(&dev_priv->perf.oa.poll_wq);
- dev_priv->perf.oa.n_builtin_sets =
- i915_oa_n_builtin_metric_sets_hsw;
+ INIT_LIST_HEAD(&dev_priv->perf.streams);
+ mutex_init(&dev_priv->perf.lock);
+ spin_lock_init(&dev_priv->perf.hook_lock);
+ spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
- dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
+ dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
- dev_priv->perf.initialized = true;
+ dev_priv->perf.initialized = true;
+ }
}
/**
@@ -2186,5 +3126,6 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
unregister_sysctl_table(dev_priv->perf.sysctl_header);
memset(&dev_priv->perf.oa.ops, 0, sizeof(dev_priv->perf.oa.ops));
+
dev_priv->perf.initialized = false;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d40e82edc1..f60554410711 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -639,6 +639,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_OACTXID _MMIO(0x2364)
+#define GEN8_OA_DEBUG _MMIO(0x2B04)
+#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5)
+#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6)
+#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2)
+#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1)
+
#define GEN8_OACONTROL _MMIO(0x2B00)
#define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
@@ -660,6 +666,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
#define GEN7_OABUFFER_RESUME (1<<0)
+#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
#define GEN8_OABUFFER _MMIO(0x2b14)
#define GEN7_OASTATUS1 _MMIO(0x2364)
@@ -678,7 +685,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_OASTATUS_REPORT_LOST (1<<0)
#define GEN8_OAHEADPTR _MMIO(0x2B0C)
+#define GEN8_OAHEADPTR_MASK 0xffffffc0
#define GEN8_OATAILPTR _MMIO(0x2B10)
+#define GEN8_OATAILPTR_MASK 0xffffffc0
#define OABUFFER_SIZE_128K (0<<3)
#define OABUFFER_SIZE_256K (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 39329d40da46..197e22c9cd39 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -336,6 +336,8 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
execlists_update_context_pdps(ppgtt, reg_state);
+ i915_oa_update_reg_state(rq->engine, rq->ctx, reg_state);
+
return ce->lrc_desc;
}
@@ -1898,6 +1900,8 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
make_rpcs(dev_priv));
}
+
+ i915_oa_update_reg_state(engine, ctx, regs);
}
static int
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e0599e729e68..03b833849919 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1295,13 +1295,18 @@ struct drm_i915_gem_context_param {
};
enum drm_i915_oa_format {
- I915_OA_FORMAT_A13 = 1,
- I915_OA_FORMAT_A29,
- I915_OA_FORMAT_A13_B8_C8,
- I915_OA_FORMAT_B4_C8,
- I915_OA_FORMAT_A45_B8_C8,
- I915_OA_FORMAT_B4_C8_A16,
- I915_OA_FORMAT_C4_B8,
+ I915_OA_FORMAT_A13 = 1, /* HSW only */
+ I915_OA_FORMAT_A29, /* HSW only */
+ I915_OA_FORMAT_A13_B8_C8, /* HSW only */
+ I915_OA_FORMAT_B4_C8, /* HSW only */
+ I915_OA_FORMAT_A45_B8_C8, /* HSW only */
+ I915_OA_FORMAT_B4_C8_A16, /* HSW only */
+ I915_OA_FORMAT_C4_B8, /* HSW+ */
+
+ /* Gen8+ */
+ I915_OA_FORMAT_A12,
+ I915_OA_FORMAT_A12_B8_C8,
+ I915_OA_FORMAT_A32u40_A4u32_B8_C8,
I915_OA_FORMAT_MAX /* non-ABI */
};
--
2.11.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
` (4 preceding siblings ...)
2017-02-22 16:36 ` [PATCH 5/6] drm/i915: Add OA unit support for Gen 8+ Robert Bragg
@ 2017-02-22 16:36 ` Robert Bragg
2017-03-01 13:00 ` Matthew Auld
2017-02-22 19:22 ` ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf Patchwork
6 siblings, 1 reply; 12+ messages in thread
From: Robert Bragg @ 2017-02-22 16:36 UTC (permalink / raw)
To: intel-gfx
These are auto generated from an XML description of metric sets,
currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gputop-data -f Makefile.xml
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
drivers/gpu/drm/i915/i915_oa_bdw.c | 4731 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_oa_bxt.c | 2483 ++++++++++++++++-
drivers/gpu/drm/i915/i915_oa_chv.c | 2600 +++++++++++++++++-
drivers/gpu/drm/i915/i915_oa_sklgt2.c | 3093 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_oa_sklgt3.c | 2638 +++++++++++++++++-
drivers/gpu/drm/i915/i915_oa_sklgt4.c | 2681 ++++++++++++++++++-
6 files changed, 17951 insertions(+), 275 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c
index d5d608ff2a36..12a9316fcada 100644
--- a/drivers/gpu/drm/i915/i915_oa_bdw.c
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.c
@@ -31,15 +31,37 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_DATA_PORT_READS_COALESCING,
+ METRIC_SET_ID_DATA_PORT_WRITES_COALESCING,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_L3_4,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER_1,
+ METRIC_SET_ID_SAMPLER_2,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_bdw = 1;
+int i915_oa_n_builtin_metric_sets_bdw = 22;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_render_basic[] = {
@@ -57,6 +79,7 @@ static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
{ _MMIO(0x9888), 0x14110014 },
{ _MMIO(0x9888), 0x14310014 },
{ _MMIO(0x9888), 0x14bf000f },
+ { _MMIO(0x9888), 0x118a0317 },
{ _MMIO(0x9888), 0x13837be0 },
{ _MMIO(0x9888), 0x3b800060 },
{ _MMIO(0x9888), 0x3d800005 },
@@ -105,11 +128,15 @@ static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
{ _MMIO(0x9888), 0x109f0002 },
{ _MMIO(0x9888), 0x0ab94000 },
{ _MMIO(0x9888), 0x0d888000 },
+ { _MMIO(0x9888), 0x038a0380 },
+ { _MMIO(0x9888), 0x058a000e },
{ _MMIO(0x9888), 0x018a8000 },
{ _MMIO(0x9888), 0x0f8a8000 },
{ _MMIO(0x9888), 0x198a8000 },
{ _MMIO(0x9888), 0x1b8a00a0 },
- { _MMIO(0x9888), 0x238b0020 },
+ { _MMIO(0x9888), 0x078a0000 },
+ { _MMIO(0x9888), 0x098a0000 },
+ { _MMIO(0x9888), 0x238b2820 },
{ _MMIO(0x9888), 0x258b2550 },
{ _MMIO(0x9888), 0x198c1000 },
{ _MMIO(0x9888), 0x0b8d8000 },
@@ -119,13 +146,13 @@ static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
{ _MMIO(0x9888), 0x0d831021 },
{ _MMIO(0x9888), 0x0f83572f },
{ _MMIO(0x9888), 0x01835680 },
- { _MMIO(0x9888), 0x038315ac },
- { _MMIO(0x9888), 0x0583002a },
+ { _MMIO(0x9888), 0x0383002c },
{ _MMIO(0x9888), 0x11830000 },
{ _MMIO(0x9888), 0x19835400 },
{ _MMIO(0x9888), 0x1b830001 },
- { _MMIO(0x9888), 0x07830000 },
- { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x05830000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0184c000 },
{ _MMIO(0x9888), 0x07848000 },
{ _MMIO(0x9888), 0x0984c000 },
@@ -143,7 +170,6 @@ static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x15804000 },
- { _MMIO(0xd24), 0x00000000 },
{ _MMIO(0x9888), 0x4d801110 },
{ _MMIO(0x9888), 0x4f800331 },
{ _MMIO(0x9888), 0x43800802 },
@@ -152,8 +178,8 @@ static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
{ _MMIO(0x9888), 0x53801111 },
{ _MMIO(0x9888), 0x478014a5 },
{ _MMIO(0x9888), 0x31800000 },
- { _MMIO(0x9888), 0x3f8014a5 },
- { _MMIO(0x9888), 0x41800005 },
+ { _MMIO(0x9888), 0x3f800ca5 },
+ { _MMIO(0x9888), 0x41800003 },
};
static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
@@ -161,6 +187,7 @@ static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
{ _MMIO(0x9888), 0x14bf000f },
{ _MMIO(0x9888), 0x14910014 },
{ _MMIO(0x9888), 0x14b10014 },
+ { _MMIO(0x9888), 0x118a0317 },
{ _MMIO(0x9888), 0x13837be0 },
{ _MMIO(0x9888), 0x3b800060 },
{ _MMIO(0x9888), 0x3d800005 },
@@ -211,8 +238,12 @@ static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
{ _MMIO(0x9888), 0x16b30080 },
{ _MMIO(0x9888), 0x01888000 },
{ _MMIO(0x9888), 0x0d88b800 },
+ { _MMIO(0x9888), 0x038a0380 },
+ { _MMIO(0x9888), 0x058a000e },
{ _MMIO(0x9888), 0x1b8a0080 },
- { _MMIO(0x9888), 0x238b0040 },
+ { _MMIO(0x9888), 0x078a0000 },
+ { _MMIO(0x9888), 0x098a0000 },
+ { _MMIO(0x9888), 0x238b2840 },
{ _MMIO(0x9888), 0x258b26a0 },
{ _MMIO(0x9888), 0x018c4000 },
{ _MMIO(0x9888), 0x0f8c4000 },
@@ -228,13 +259,13 @@ static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
{ _MMIO(0x9888), 0x0d831021 },
{ _MMIO(0x9888), 0x0f83572f },
{ _MMIO(0x9888), 0x01835680 },
- { _MMIO(0x9888), 0x038315ac },
- { _MMIO(0x9888), 0x0583002a },
+ { _MMIO(0x9888), 0x0383002c },
{ _MMIO(0x9888), 0x11830000 },
{ _MMIO(0x9888), 0x19835400 },
{ _MMIO(0x9888), 0x1b830001 },
- { _MMIO(0x9888), 0x07830000 },
- { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x05830000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0184c000 },
{ _MMIO(0x9888), 0x07848000 },
{ _MMIO(0x9888), 0x0984c000 },
@@ -252,17 +283,16 @@ static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x15804000 },
- { _MMIO(0xd24), 0x00000000 },
- { _MMIO(0x9888), 0x4d805550 },
- { _MMIO(0x9888), 0x4f800335 },
+ { _MMIO(0x9888), 0x4d801550 },
+ { _MMIO(0x9888), 0x4f800331 },
{ _MMIO(0x9888), 0x43800802 },
{ _MMIO(0x9888), 0x51800400 },
{ _MMIO(0x9888), 0x458004a1 },
{ _MMIO(0x9888), 0x53805555 },
{ _MMIO(0x9888), 0x47800421 },
{ _MMIO(0x9888), 0x31800000 },
- { _MMIO(0x9888), 0x3f800421 },
- { _MMIO(0x9888), 0x41800841 },
+ { _MMIO(0x9888), 0x3f801421 },
+ { _MMIO(0x9888), 0x41800845 },
};
static const struct i915_oa_reg *
@@ -281,82 +311,4593 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return NULL;
}
-int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01[] = {
+ { _MMIO(0x9888), 0x105c00e0 },
+ { _MMIO(0x9888), 0x105800e0 },
+ { _MMIO(0x9888), 0x103800e0 },
+ { _MMIO(0x9888), 0x3580001a },
+ { _MMIO(0x9888), 0x3b800060 },
+ { _MMIO(0x9888), 0x3d800005 },
+ { _MMIO(0x9888), 0x065c2100 },
+ { _MMIO(0x9888), 0x0a5c0041 },
+ { _MMIO(0x9888), 0x0c5c6600 },
+ { _MMIO(0x9888), 0x005c6580 },
+ { _MMIO(0x9888), 0x085c8000 },
+ { _MMIO(0x9888), 0x0e5c8000 },
+ { _MMIO(0x9888), 0x00580042 },
+ { _MMIO(0x9888), 0x08582080 },
+ { _MMIO(0x9888), 0x0c58004c },
+ { _MMIO(0x9888), 0x0e582580 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x185b1000 },
+ { _MMIO(0x9888), 0x1a5b0104 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faa00 },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x08380042 },
+ { _MMIO(0x9888), 0x0a382080 },
+ { _MMIO(0x9888), 0x0e38404c },
+ { _MMIO(0x9888), 0x0238404b },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x16380000 },
+ { _MMIO(0x9888), 0x18381145 },
+ { _MMIO(0x9888), 0x04380000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x02392000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x238b02a0 },
+ { _MMIO(0x9888), 0x258b5550 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x1f850a80 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x03844000 },
+ { _MMIO(0x9888), 0x17808137 },
+ { _MMIO(0x9888), 0x1980c147 },
+ { _MMIO(0x9888), 0x1b80c0e5 },
+ { _MMIO(0x9888), 0x1d80c0e3 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x13804000 },
+ { _MMIO(0x9888), 0x15800000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801000 },
+ { _MMIO(0x9888), 0x4f800111 },
+ { _MMIO(0x9888), 0x43800062 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800062 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800062 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f801062 },
+ { _MMIO(0x9888), 0x41801084 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic_1_2_slices_0x02[] = {
+ { _MMIO(0x9888), 0x10dc00e0 },
+ { _MMIO(0x9888), 0x10d800e0 },
+ { _MMIO(0x9888), 0x10b800e0 },
+ { _MMIO(0x9888), 0x3580001a },
+ { _MMIO(0x9888), 0x3b800060 },
+ { _MMIO(0x9888), 0x3d800005 },
+ { _MMIO(0x9888), 0x06dc2100 },
+ { _MMIO(0x9888), 0x0adc0041 },
+ { _MMIO(0x9888), 0x0cdc6600 },
+ { _MMIO(0x9888), 0x00dc6580 },
+ { _MMIO(0x9888), 0x08dc8000 },
+ { _MMIO(0x9888), 0x0edc8000 },
+ { _MMIO(0x9888), 0x00d80042 },
+ { _MMIO(0x9888), 0x08d82080 },
+ { _MMIO(0x9888), 0x0cd8004c },
+ { _MMIO(0x9888), 0x0ed82580 },
+ { _MMIO(0x9888), 0x00db4000 },
+ { _MMIO(0x9888), 0x18db1000 },
+ { _MMIO(0x9888), 0x1adb0104 },
+ { _MMIO(0x9888), 0x0c9fa800 },
+ { _MMIO(0x9888), 0x0e9faa00 },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x08b80042 },
+ { _MMIO(0x9888), 0x0ab82080 },
+ { _MMIO(0x9888), 0x0eb8404c },
+ { _MMIO(0x9888), 0x02b8404b },
+ { _MMIO(0x9888), 0x00b84000 },
+ { _MMIO(0x9888), 0x16b80000 },
+ { _MMIO(0x9888), 0x18b81145 },
+ { _MMIO(0x9888), 0x04b80000 },
+ { _MMIO(0x9888), 0x00b9a000 },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x02b92000 },
+ { _MMIO(0x9888), 0x01888000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x238b0540 },
+ { _MMIO(0x9888), 0x258baaa0 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x018c4000 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x018da000 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038d2000 },
+ { _MMIO(0x9888), 0x1f850a80 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x03844000 },
+ { _MMIO(0x9888), 0x17808137 },
+ { _MMIO(0x9888), 0x1980c147 },
+ { _MMIO(0x9888), 0x1b80c0e5 },
+ { _MMIO(0x9888), 0x1d80c0e3 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x13804000 },
+ { _MMIO(0x9888), 0x15800000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d805000 },
+ { _MMIO(0x9888), 0x4f800555 },
+ { _MMIO(0x9888), 0x43800062 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800062 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800062 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800062 },
+ { _MMIO(0x9888), 0x41800000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- dev_priv->perf.oa.mux_regs = NULL;
- dev_priv->perf.oa.mux_regs_len = 0;
- dev_priv->perf.oa.b_counter_regs = NULL;
- dev_priv->perf.oa.b_counter_regs_len = 0;
- dev_priv->perf.oa.flex_regs = NULL;
- dev_priv->perf.oa.flex_regs_len = 0;
+ if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01);
+ return mux_config_compute_basic_1_0_slices_0x01;
+ } else if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) {
+ *len = ARRAY_SIZE(mux_config_compute_basic_1_2_slices_0x02);
+ return mux_config_compute_basic_1_2_slices_0x02;
+ }
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
- dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
- &dev_priv->perf.oa.mux_regs_len);
- if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+ *len = 0;
+ return NULL;
+}
- /* EINVAL because *_register_sysfs already checked this
- * and so it wouldn't have been advertised so userspace and
- * so shouldn't have been requested
- */
- return -EINVAL;
- }
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
- dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
- dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
- dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
- dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0a1e0000 },
+ { _MMIO(0x9888), 0x0c1f000f },
+ { _MMIO(0x9888), 0x10176800 },
+ { _MMIO(0x9888), 0x1191001f },
+ { _MMIO(0x9888), 0x0b880320 },
+ { _MMIO(0x9888), 0x01890c40 },
+ { _MMIO(0x9888), 0x118a1c00 },
+ { _MMIO(0x9888), 0x118d7c00 },
+ { _MMIO(0x9888), 0x118e0020 },
+ { _MMIO(0x9888), 0x118f4c00 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x13900001 },
+ { _MMIO(0x9888), 0x065c4000 },
+ { _MMIO(0x9888), 0x0c3d8000 },
+ { _MMIO(0x9888), 0x06584000 },
+ { _MMIO(0x9888), 0x0c5b4000 },
+ { _MMIO(0x9888), 0x081e0040 },
+ { _MMIO(0x9888), 0x0e1e0000 },
+ { _MMIO(0x9888), 0x021f5400 },
+ { _MMIO(0x9888), 0x001f0000 },
+ { _MMIO(0x9888), 0x101f0010 },
+ { _MMIO(0x9888), 0x0e1f0080 },
+ { _MMIO(0x9888), 0x0c384000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0c13c000 },
+ { _MMIO(0x9888), 0x06164000 },
+ { _MMIO(0x9888), 0x06170012 },
+ { _MMIO(0x9888), 0x00170000 },
+ { _MMIO(0x9888), 0x01910005 },
+ { _MMIO(0x9888), 0x07880002 },
+ { _MMIO(0x9888), 0x01880c00 },
+ { _MMIO(0x9888), 0x0f880000 },
+ { _MMIO(0x9888), 0x0d880000 },
+ { _MMIO(0x9888), 0x05880000 },
+ { _MMIO(0x9888), 0x09890032 },
+ { _MMIO(0x9888), 0x078a0800 },
+ { _MMIO(0x9888), 0x0f8a0a00 },
+ { _MMIO(0x9888), 0x198a4000 },
+ { _MMIO(0x9888), 0x1b8a2000 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x038a4000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x238b54c0 },
+ { _MMIO(0x9888), 0x258baa55 },
+ { _MMIO(0x9888), 0x278b0019 },
+ { _MMIO(0x9888), 0x198c0100 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x0f8d0015 },
+ { _MMIO(0x9888), 0x018d1000 },
+ { _MMIO(0x9888), 0x098d8000 },
+ { _MMIO(0x9888), 0x0b8df000 },
+ { _MMIO(0x9888), 0x0d8d3000 },
+ { _MMIO(0x9888), 0x038de000 },
+ { _MMIO(0x9888), 0x058d3000 },
+ { _MMIO(0x9888), 0x0d8e0004 },
+ { _MMIO(0x9888), 0x058e000c },
+ { _MMIO(0x9888), 0x098e0000 },
+ { _MMIO(0x9888), 0x078e0000 },
+ { _MMIO(0x9888), 0x038e0000 },
+ { _MMIO(0x9888), 0x0b8f0020 },
+ { _MMIO(0x9888), 0x198f0c00 },
+ { _MMIO(0x9888), 0x078f8000 },
+ { _MMIO(0x9888), 0x098f4000 },
+ { _MMIO(0x9888), 0x0b900980 },
+ { _MMIO(0x9888), 0x03900d80 },
+ { _MMIO(0x9888), 0x01900000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801111 },
+ { _MMIO(0x9888), 0x3d800800 },
+ { _MMIO(0x9888), 0x4f801011 },
+ { _MMIO(0x9888), 0x43800443 },
+ { _MMIO(0x9888), 0x51801111 },
+ { _MMIO(0x9888), 0x45800422 },
+ { _MMIO(0x9888), 0x53801111 },
+ { _MMIO(0x9888), 0x47800c60 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800422 },
+ { _MMIO(0x9888), 0x41800021 },
+};
- return 0;
- default:
- return -ENODEV;
- }
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile);
+ return mux_config_render_pipe_profile;
}
-static ssize_t
-show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x198b0343 },
+ { _MMIO(0x9888), 0x13845800 },
+ { _MMIO(0x9888), 0x15840018 },
+ { _MMIO(0x9888), 0x3580001a },
+ { _MMIO(0x9888), 0x038b6300 },
+ { _MMIO(0x9888), 0x058b6b62 },
+ { _MMIO(0x9888), 0x078b006a },
+ { _MMIO(0x9888), 0x118b0000 },
+ { _MMIO(0x9888), 0x238b0000 },
+ { _MMIO(0x9888), 0x258b0000 },
+ { _MMIO(0x9888), 0x1f85a080 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385000a },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x01840018 },
+ { _MMIO(0x9888), 0x07844c80 },
+ { _MMIO(0x9888), 0x09840d9a },
+ { _MMIO(0x9888), 0x0b840e9c },
+ { _MMIO(0x9888), 0x0d840f9e },
+ { _MMIO(0x9888), 0x0f840010 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x03848000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x2f8000e5 },
+ { _MMIO(0x9888), 0x138080e3 },
+ { _MMIO(0x9888), 0x1580c0e1 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x11804000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f804000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3d800800 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800842 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800842 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801042 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800084 },
+ { _MMIO(0x9888), 0x41800000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+ *len = ARRAY_SIZE(mux_config_memory_reads);
+ return mux_config_memory_reads;
}
-static struct device_attribute dev_attr_render_basic_id = {
- .attr = { .name = "id", .mode = 0444 },
- .show = show_render_basic_id,
- .store = NULL,
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
};
-static struct attribute *attrs_render_basic[] = {
- &dev_attr_render_basic_id.attr,
- NULL,
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
};
-static struct attribute_group group_render_basic = {
- .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
- .attrs = attrs_render_basic,
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x198b0343 },
+ { _MMIO(0x9888), 0x13845400 },
+ { _MMIO(0x9888), 0x3580001a },
+ { _MMIO(0x9888), 0x3d800805 },
+ { _MMIO(0x9888), 0x038b6300 },
+ { _MMIO(0x9888), 0x058b6b62 },
+ { _MMIO(0x9888), 0x078b006a },
+ { _MMIO(0x9888), 0x118b0000 },
+ { _MMIO(0x9888), 0x238b0000 },
+ { _MMIO(0x9888), 0x258b0000 },
+ { _MMIO(0x9888), 0x1f85a080 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x23850002 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x01840010 },
+ { _MMIO(0x9888), 0x07844880 },
+ { _MMIO(0x9888), 0x09840992 },
+ { _MMIO(0x9888), 0x0b840a94 },
+ { _MMIO(0x9888), 0x0d840b96 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x03848000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x2d800147 },
+ { _MMIO(0x9888), 0x2f8000e5 },
+ { _MMIO(0x9888), 0x138080e3 },
+ { _MMIO(0x9888), 0x1580c0e1 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x11804000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f800000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800842 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800842 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801082 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800084 },
+ { _MMIO(0x9888), 0x41800000 },
};
-int
-i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv)
+static const struct i915_oa_reg *
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- int mux_len;
- int ret = 0;
+ *len = ARRAY_SIZE(mux_config_memory_writes);
+ return mux_config_memory_writes;
+}
- if (get_render_basic_mux_config(dev_priv, &mux_len)) {
- ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
- if (ret)
- goto error_render_basic;
- }
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
- return 0;
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_0_subslices_0x01[] = {
+ { _MMIO(0x9888), 0x143d0160 },
+ { _MMIO(0x9888), 0x163d2800 },
+ { _MMIO(0x9888), 0x183d0120 },
+ { _MMIO(0x9888), 0x105800e0 },
+ { _MMIO(0x9888), 0x005cc000 },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5cc000 },
+ { _MMIO(0x9888), 0x0e5cc000 },
+ { _MMIO(0x9888), 0x025cc000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x003d0011 },
+ { _MMIO(0x9888), 0x063d0900 },
+ { _MMIO(0x9888), 0x083d0a13 },
+ { _MMIO(0x9888), 0x0a3d0b15 },
+ { _MMIO(0x9888), 0x0c3d2317 },
+ { _MMIO(0x9888), 0x043d21b7 },
+ { _MMIO(0x9888), 0x103d0000 },
+ { _MMIO(0x9888), 0x0e3d0000 },
+ { _MMIO(0x9888), 0x1a3d0000 },
+ { _MMIO(0x9888), 0x0e5825c1 },
+ { _MMIO(0x9888), 0x00586100 },
+ { _MMIO(0x9888), 0x0258204c },
+ { _MMIO(0x9888), 0x06588000 },
+ { _MMIO(0x9888), 0x0858c000 },
+ { _MMIO(0x9888), 0x0a58c000 },
+ { _MMIO(0x9888), 0x0c58c000 },
+ { _MMIO(0x9888), 0x0458c000 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x185b5400 },
+ { _MMIO(0x9888), 0x1a5b0155 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faa2a },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18381555 },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x06384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x238b2aa0 },
+ { _MMIO(0x9888), 0x258b5551 },
+ { _MMIO(0x9888), 0x278b0015 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_1_subslices_0x08[] = {
+ { _MMIO(0x9888), 0x14bd0160 },
+ { _MMIO(0x9888), 0x16bd2800 },
+ { _MMIO(0x9888), 0x18bd0120 },
+ { _MMIO(0x9888), 0x10d800e0 },
+ { _MMIO(0x9888), 0x00dcc000 },
+ { _MMIO(0x9888), 0x06dc8000 },
+ { _MMIO(0x9888), 0x08dcc000 },
+ { _MMIO(0x9888), 0x0adcc000 },
+ { _MMIO(0x9888), 0x0cdcc000 },
+ { _MMIO(0x9888), 0x0edcc000 },
+ { _MMIO(0x9888), 0x02dcc000 },
+ { _MMIO(0x9888), 0x04dcc000 },
+ { _MMIO(0x9888), 0x00bd0011 },
+ { _MMIO(0x9888), 0x06bd0900 },
+ { _MMIO(0x9888), 0x08bd0a13 },
+ { _MMIO(0x9888), 0x0abd0b15 },
+ { _MMIO(0x9888), 0x0cbd2317 },
+ { _MMIO(0x9888), 0x04bd21b7 },
+ { _MMIO(0x9888), 0x10bd0000 },
+ { _MMIO(0x9888), 0x0ebd0000 },
+ { _MMIO(0x9888), 0x1abd0000 },
+ { _MMIO(0x9888), 0x0ed825c1 },
+ { _MMIO(0x9888), 0x00d86100 },
+ { _MMIO(0x9888), 0x02d8204c },
+ { _MMIO(0x9888), 0x06d88000 },
+ { _MMIO(0x9888), 0x08d8c000 },
+ { _MMIO(0x9888), 0x0ad8c000 },
+ { _MMIO(0x9888), 0x0cd8c000 },
+ { _MMIO(0x9888), 0x04d8c000 },
+ { _MMIO(0x9888), 0x00db4000 },
+ { _MMIO(0x9888), 0x0edb4000 },
+ { _MMIO(0x9888), 0x18db5400 },
+ { _MMIO(0x9888), 0x1adb0155 },
+ { _MMIO(0x9888), 0x02db4000 },
+ { _MMIO(0x9888), 0x04db4000 },
+ { _MMIO(0x9888), 0x06db4000 },
+ { _MMIO(0x9888), 0x08db4000 },
+ { _MMIO(0x9888), 0x0adb4000 },
+ { _MMIO(0x9888), 0x0c9fa800 },
+ { _MMIO(0x9888), 0x0e9faa2a },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x00b84000 },
+ { _MMIO(0x9888), 0x0eb84000 },
+ { _MMIO(0x9888), 0x16b84000 },
+ { _MMIO(0x9888), 0x18b81555 },
+ { _MMIO(0x9888), 0x02b84000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab84000 },
+ { _MMIO(0x9888), 0x00b9a000 },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x01888000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x238b5540 },
+ { _MMIO(0x9888), 0x258baaa2 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x018c4000 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x018da000 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_2_subslices_0x02[] = {
+ { _MMIO(0x9888), 0x105c00e0 },
+ { _MMIO(0x9888), 0x145b0160 },
+ { _MMIO(0x9888), 0x165b2800 },
+ { _MMIO(0x9888), 0x185b0120 },
+ { _MMIO(0x9888), 0x0e5c25c1 },
+ { _MMIO(0x9888), 0x005c6100 },
+ { _MMIO(0x9888), 0x025c204c },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5cc000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x005b0011 },
+ { _MMIO(0x9888), 0x065b0900 },
+ { _MMIO(0x9888), 0x085b0a13 },
+ { _MMIO(0x9888), 0x0a5b0b15 },
+ { _MMIO(0x9888), 0x0c5b2317 },
+ { _MMIO(0x9888), 0x045b21b7 },
+ { _MMIO(0x9888), 0x105b0000 },
+ { _MMIO(0x9888), 0x0e5b0000 },
+ { _MMIO(0x9888), 0x1a5b0000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faa2a },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18381555 },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x06384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x238b2aa0 },
+ { _MMIO(0x9888), 0x258b5551 },
+ { _MMIO(0x9888), 0x278b0015 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_3_subslices_0x10[] = {
+ { _MMIO(0x9888), 0x10dc00e0 },
+ { _MMIO(0x9888), 0x14db0160 },
+ { _MMIO(0x9888), 0x16db2800 },
+ { _MMIO(0x9888), 0x18db0120 },
+ { _MMIO(0x9888), 0x0edc25c1 },
+ { _MMIO(0x9888), 0x00dc6100 },
+ { _MMIO(0x9888), 0x02dc204c },
+ { _MMIO(0x9888), 0x06dc8000 },
+ { _MMIO(0x9888), 0x08dcc000 },
+ { _MMIO(0x9888), 0x0adcc000 },
+ { _MMIO(0x9888), 0x0cdcc000 },
+ { _MMIO(0x9888), 0x04dcc000 },
+ { _MMIO(0x9888), 0x00db0011 },
+ { _MMIO(0x9888), 0x06db0900 },
+ { _MMIO(0x9888), 0x08db0a13 },
+ { _MMIO(0x9888), 0x0adb0b15 },
+ { _MMIO(0x9888), 0x0cdb2317 },
+ { _MMIO(0x9888), 0x04db21b7 },
+ { _MMIO(0x9888), 0x10db0000 },
+ { _MMIO(0x9888), 0x0edb0000 },
+ { _MMIO(0x9888), 0x1adb0000 },
+ { _MMIO(0x9888), 0x0c9fa800 },
+ { _MMIO(0x9888), 0x0e9faa2a },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x00b84000 },
+ { _MMIO(0x9888), 0x0eb84000 },
+ { _MMIO(0x9888), 0x16b84000 },
+ { _MMIO(0x9888), 0x18b81555 },
+ { _MMIO(0x9888), 0x02b84000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab84000 },
+ { _MMIO(0x9888), 0x00b9a000 },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x01888000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x238b5540 },
+ { _MMIO(0x9888), 0x258baaa2 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x018c4000 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x018da000 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_4_subslices_0x04[] = {
+ { _MMIO(0x9888), 0x103800e0 },
+ { _MMIO(0x9888), 0x143a0160 },
+ { _MMIO(0x9888), 0x163a2800 },
+ { _MMIO(0x9888), 0x183a0120 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faa2a },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x0e38a5c1 },
+ { _MMIO(0x9888), 0x0038a100 },
+ { _MMIO(0x9888), 0x0238204c },
+ { _MMIO(0x9888), 0x16388000 },
+ { _MMIO(0x9888), 0x183802aa },
+ { _MMIO(0x9888), 0x04380000 },
+ { _MMIO(0x9888), 0x06380000 },
+ { _MMIO(0x9888), 0x08388000 },
+ { _MMIO(0x9888), 0x0a388000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x003a0011 },
+ { _MMIO(0x9888), 0x063a0900 },
+ { _MMIO(0x9888), 0x083a0a13 },
+ { _MMIO(0x9888), 0x0a3a0b15 },
+ { _MMIO(0x9888), 0x0c3a2317 },
+ { _MMIO(0x9888), 0x043a21b7 },
+ { _MMIO(0x9888), 0x103a0000 },
+ { _MMIO(0x9888), 0x0e3a0000 },
+ { _MMIO(0x9888), 0x1a3a0000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x238b2aa0 },
+ { _MMIO(0x9888), 0x258b5551 },
+ { _MMIO(0x9888), 0x278b0015 },
+};
+static const struct i915_oa_reg mux_config_compute_extended_1_5_subslices_0x20[] = {
+ { _MMIO(0x9888), 0x10b800e0 },
+ { _MMIO(0x9888), 0x14ba0160 },
+ { _MMIO(0x9888), 0x16ba2800 },
+ { _MMIO(0x9888), 0x18ba0120 },
+ { _MMIO(0x9888), 0x0c9fa800 },
+ { _MMIO(0x9888), 0x0e9faa2a },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x0eb8a5c1 },
+ { _MMIO(0x9888), 0x00b8a100 },
+ { _MMIO(0x9888), 0x02b8204c },
+ { _MMIO(0x9888), 0x16b88000 },
+ { _MMIO(0x9888), 0x18b802aa },
+ { _MMIO(0x9888), 0x04b80000 },
+ { _MMIO(0x9888), 0x06b80000 },
+ { _MMIO(0x9888), 0x08b88000 },
+ { _MMIO(0x9888), 0x0ab88000 },
+ { _MMIO(0x9888), 0x00b9a000 },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x00ba0011 },
+ { _MMIO(0x9888), 0x06ba0900 },
+ { _MMIO(0x9888), 0x08ba0a13 },
+ { _MMIO(0x9888), 0x0aba0b15 },
+ { _MMIO(0x9888), 0x0cba2317 },
+ { _MMIO(0x9888), 0x04ba21b7 },
+ { _MMIO(0x9888), 0x10ba0000 },
+ { _MMIO(0x9888), 0x0eba0000 },
+ { _MMIO(0x9888), 0x1aba0000 },
+ { _MMIO(0x9888), 0x01888000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x238b5540 },
+ { _MMIO(0x9888), 0x258baaa2 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x018c4000 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x018da000 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaa2 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x17808000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3d800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800000 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800420 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800421 },
+ { _MMIO(0x9888), 0x41800000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01);
+ return mux_config_compute_extended_1_0_subslices_0x01;
+ } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_1_subslices_0x08);
+ return mux_config_compute_extended_1_1_subslices_0x08;
+ } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_2_subslices_0x02);
+ return mux_config_compute_extended_1_2_subslices_0x02;
+ } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_3_subslices_0x10);
+ return mux_config_compute_extended_1_3_subslices_0x10;
+ } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_4_subslices_0x04);
+ return mux_config_compute_extended_1_4_subslices_0x04;
+ } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_5_subslices_0x20);
+ return mux_config_compute_extended_1_5_subslices_0x20;
+ *len = ARRAY_SIZE(mux_config_compute_extended);
+ return mux_config_compute_extended;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x143f00b3 },
+ { _MMIO(0x9888), 0x14bf00b3 },
+ { _MMIO(0x9888), 0x138303c0 },
+ { _MMIO(0x9888), 0x3b800060 },
+ { _MMIO(0x9888), 0x3d800805 },
+ { _MMIO(0x9888), 0x003f0029 },
+ { _MMIO(0x9888), 0x063f1400 },
+ { _MMIO(0x9888), 0x083f1225 },
+ { _MMIO(0x9888), 0x0e3f1327 },
+ { _MMIO(0x9888), 0x103f0000 },
+ { _MMIO(0x9888), 0x005a4000 },
+ { _MMIO(0x9888), 0x065a8000 },
+ { _MMIO(0x9888), 0x085ac000 },
+ { _MMIO(0x9888), 0x0e5ac000 },
+ { _MMIO(0x9888), 0x001d4000 },
+ { _MMIO(0x9888), 0x061d8000 },
+ { _MMIO(0x9888), 0x081dc000 },
+ { _MMIO(0x9888), 0x0e1dc000 },
+ { _MMIO(0x9888), 0x0c1f0800 },
+ { _MMIO(0x9888), 0x0e1f2a00 },
+ { _MMIO(0x9888), 0x101f0280 },
+ { _MMIO(0x9888), 0x00391000 },
+ { _MMIO(0x9888), 0x06394000 },
+ { _MMIO(0x9888), 0x08395000 },
+ { _MMIO(0x9888), 0x0e395000 },
+ { _MMIO(0x9888), 0x0abf1429 },
+ { _MMIO(0x9888), 0x0cbf1225 },
+ { _MMIO(0x9888), 0x00bf1380 },
+ { _MMIO(0x9888), 0x02bf0026 },
+ { _MMIO(0x9888), 0x10bf0000 },
+ { _MMIO(0x9888), 0x0adac000 },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x00da8000 },
+ { _MMIO(0x9888), 0x02da4000 },
+ { _MMIO(0x9888), 0x0a9dc000 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x009d8000 },
+ { _MMIO(0x9888), 0x029d4000 },
+ { _MMIO(0x9888), 0x0e9f8000 },
+ { _MMIO(0x9888), 0x109f002a },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0ab95000 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x00b94000 },
+ { _MMIO(0x9888), 0x02b91000 },
+ { _MMIO(0x9888), 0x0d88c000 },
+ { _MMIO(0x9888), 0x0f880003 },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8a8020 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x238b0520 },
+ { _MMIO(0x9888), 0x258ba950 },
+ { _MMIO(0x9888), 0x278b0016 },
+ { _MMIO(0x9888), 0x198c5400 },
+ { _MMIO(0x9888), 0x1b8c0001 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038d2000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x03835180 },
+ { _MMIO(0x9888), 0x05834022 },
+ { _MMIO(0x9888), 0x11830000 },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x05844000 },
+ { _MMIO(0x9888), 0x1b80c137 },
+ { _MMIO(0x9888), 0x1d80c147 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x17808000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x15804000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801000 },
+ { _MMIO(0x9888), 0x4f800111 },
+ { _MMIO(0x9888), 0x43800842 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800840 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800800 },
+ { _MMIO(0x9888), 0x418014a2 },
+};
+
+static const struct i915_oa_reg *
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_l3_cache);
+ return mux_config_compute_l3_cache;
+}
+
+static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0xba98ba98 },
+ { _MMIO(0x2748), 0xba98ba98 },
+ { _MMIO(0x2744), 0x00003377 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fff2 },
+ { _MMIO(0x2774), 0x00007ff0 },
+ { _MMIO(0x2778), 0x0007ffe2 },
+ { _MMIO(0x277c), 0x00007ff0 },
+ { _MMIO(0x2780), 0x0007ffc2 },
+ { _MMIO(0x2784), 0x00007ff0 },
+ { _MMIO(0x2788), 0x0007ff82 },
+ { _MMIO(0x278c), 0x00007ff0 },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000bfef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000bfdf },
+ { _MMIO(0x27a0), 0x0007fffa },
+ { _MMIO(0x27a4), 0x0000bfbf },
+ { _MMIO(0x27a8), 0x0007fffa },
+ { _MMIO(0x27ac), 0x0000bf7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_data_port_reads_coalescing_1_0_subslices_0x01[] = {
+ { _MMIO(0x9888), 0x103d0005 },
+ { _MMIO(0x9888), 0x163d240b },
+ { _MMIO(0x9888), 0x1058022f },
+ { _MMIO(0x9888), 0x185b5520 },
+ { _MMIO(0x9888), 0x198b0003 },
+ { _MMIO(0x9888), 0x005cc000 },
+ { _MMIO(0x9888), 0x065cc000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5cc000 },
+ { _MMIO(0x9888), 0x0e5cc000 },
+ { _MMIO(0x9888), 0x025c4000 },
+ { _MMIO(0x9888), 0x045c8000 },
+ { _MMIO(0x9888), 0x003d0000 },
+ { _MMIO(0x9888), 0x063d00b0 },
+ { _MMIO(0x9888), 0x083d0182 },
+ { _MMIO(0x9888), 0x0a3d10a0 },
+ { _MMIO(0x9888), 0x0c3d11a2 },
+ { _MMIO(0x9888), 0x0e3d0000 },
+ { _MMIO(0x9888), 0x183d0000 },
+ { _MMIO(0x9888), 0x1a3d0000 },
+ { _MMIO(0x9888), 0x0e582242 },
+ { _MMIO(0x9888), 0x00586700 },
+ { _MMIO(0x9888), 0x0258004f },
+ { _MMIO(0x9888), 0x0658c000 },
+ { _MMIO(0x9888), 0x0858c000 },
+ { _MMIO(0x9888), 0x0a58c000 },
+ { _MMIO(0x9888), 0x0c58c000 },
+ { _MMIO(0x9888), 0x045b6300 },
+ { _MMIO(0x9888), 0x105b0000 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x1a5b0155 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x0a5b0000 },
+ { _MMIO(0x9888), 0x0c5b4000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faaa0 },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18381555 },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c384000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x0639a000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x02392000 },
+ { _MMIO(0x9888), 0x04398000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x038b6300 },
+ { _MMIO(0x9888), 0x058b0062 },
+ { _MMIO(0x9888), 0x118b0000 },
+ { _MMIO(0x9888), 0x238b02a0 },
+ { _MMIO(0x9888), 0x258b5555 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801000 },
+ { _MMIO(0x9888), 0x3d800000 },
+ { _MMIO(0x9888), 0x4f800001 },
+ { _MMIO(0x9888), 0x43800000 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800420 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800421 },
+ { _MMIO(0x9888), 0x41800041 },
+};
+
+static const struct i915_oa_reg *
+get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_data_port_reads_coalescing_1_0_subslices_0x01);
+ return mux_config_data_port_reads_coalescing_1_0_subslices_0x01;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0xba98ba98 },
+ { _MMIO(0x2748), 0xba98ba98 },
+ { _MMIO(0x2744), 0x00003377 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ff72 },
+ { _MMIO(0x2774), 0x0000bfd0 },
+ { _MMIO(0x2778), 0x0007ff62 },
+ { _MMIO(0x277c), 0x0000bfd0 },
+ { _MMIO(0x2780), 0x0007ff42 },
+ { _MMIO(0x2784), 0x0000bfd0 },
+ { _MMIO(0x2788), 0x0007ff02 },
+ { _MMIO(0x278c), 0x0000bfd0 },
+ { _MMIO(0x2790), 0x0005fff2 },
+ { _MMIO(0x2794), 0x0000bfd0 },
+ { _MMIO(0x2798), 0x0005ffe2 },
+ { _MMIO(0x279c), 0x0000bfd0 },
+ { _MMIO(0x27a0), 0x0005ffc2 },
+ { _MMIO(0x27a4), 0x0000bfd0 },
+ { _MMIO(0x27a8), 0x0005ff82 },
+ { _MMIO(0x27ac), 0x0000bfd0 },
+};
+
+static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_data_port_writes_coalescing_1_0_subslices_0x01[] = {
+ { _MMIO(0x9888), 0x103d0005 },
+ { _MMIO(0x9888), 0x143d0120 },
+ { _MMIO(0x9888), 0x163d2400 },
+ { _MMIO(0x9888), 0x1058022f },
+ { _MMIO(0x9888), 0x105b0000 },
+ { _MMIO(0x9888), 0x198b0003 },
+ { _MMIO(0x9888), 0x005cc000 },
+ { _MMIO(0x9888), 0x065cc000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0e5cc000 },
+ { _MMIO(0x9888), 0x025c4000 },
+ { _MMIO(0x9888), 0x045c8000 },
+ { _MMIO(0x9888), 0x003d0000 },
+ { _MMIO(0x9888), 0x063d0094 },
+ { _MMIO(0x9888), 0x083d0182 },
+ { _MMIO(0x9888), 0x0a3d1814 },
+ { _MMIO(0x9888), 0x0e3d0000 },
+ { _MMIO(0x9888), 0x183d0000 },
+ { _MMIO(0x9888), 0x1a3d0000 },
+ { _MMIO(0x9888), 0x0c3d0000 },
+ { _MMIO(0x9888), 0x0e582242 },
+ { _MMIO(0x9888), 0x00586700 },
+ { _MMIO(0x9888), 0x0258004f },
+ { _MMIO(0x9888), 0x0658c000 },
+ { _MMIO(0x9888), 0x0858c000 },
+ { _MMIO(0x9888), 0x0a58c000 },
+ { _MMIO(0x9888), 0x045b6a80 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x185b5400 },
+ { _MMIO(0x9888), 0x1a5b0141 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x0a5b0000 },
+ { _MMIO(0x9888), 0x0c5b4000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1faaa0 },
+ { _MMIO(0x9888), 0x101f0282 },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18381415 },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c384000 },
+ { _MMIO(0x9888), 0x0039a000 },
+ { _MMIO(0x9888), 0x0639a000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x02392000 },
+ { _MMIO(0x9888), 0x04398000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8a82a0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x038b6300 },
+ { _MMIO(0x9888), 0x058b0062 },
+ { _MMIO(0x9888), 0x118b0000 },
+ { _MMIO(0x9888), 0x238b02a0 },
+ { _MMIO(0x9888), 0x258b1555 },
+ { _MMIO(0x9888), 0x278b0014 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x21852aaa },
+ { _MMIO(0x9888), 0x23850028 },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830141 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0xd24), 0x00000000 },
+ { _MMIO(0x9888), 0x4d801000 },
+ { _MMIO(0x9888), 0x3d800000 },
+ { _MMIO(0x9888), 0x4f800001 },
+ { _MMIO(0x9888), 0x43800000 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800420 },
+ { _MMIO(0x9888), 0x3f800421 },
+ { _MMIO(0x9888), 0x41800041 },
+};
+
+static const struct i915_oa_reg *
+get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_data_port_writes_coalescing_1_0_subslices_0x01);
+ return mux_config_data_port_writes_coalescing_1_0_subslices_0x01;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fff7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x105c0232 },
+ { _MMIO(0x9888), 0x10580232 },
+ { _MMIO(0x9888), 0x10380232 },
+ { _MMIO(0x9888), 0x10dc0232 },
+ { _MMIO(0x9888), 0x10d80232 },
+ { _MMIO(0x9888), 0x10b80232 },
+ { _MMIO(0x9888), 0x118e4400 },
+ { _MMIO(0x9888), 0x025c6080 },
+ { _MMIO(0x9888), 0x045c004b },
+ { _MMIO(0x9888), 0x005c8000 },
+ { _MMIO(0x9888), 0x00582080 },
+ { _MMIO(0x9888), 0x0258004b },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x04386080 },
+ { _MMIO(0x9888), 0x0638404b },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a380000 },
+ { _MMIO(0x9888), 0x0c380000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0cdc25c1 },
+ { _MMIO(0x9888), 0x0adcc000 },
+ { _MMIO(0x9888), 0x0ad825c1 },
+ { _MMIO(0x9888), 0x18db4000 },
+ { _MMIO(0x9888), 0x1adb0001 },
+ { _MMIO(0x9888), 0x0e9f8000 },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x0eb825c1 },
+ { _MMIO(0x9888), 0x18b80154 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x0d88c000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258baa05 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c5400 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x098dc000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x098e05c0 },
+ { _MMIO(0x9888), 0x058e0000 },
+ { _MMIO(0x9888), 0x198f0020 },
+ { _MMIO(0x9888), 0x2185aa0a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x19835000 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x19808000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x51800040 },
+ { _MMIO(0x9888), 0x43800400 },
+ { _MMIO(0x9888), 0x45800800 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800c62 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f801042 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x418014a4 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x10bf03da },
+ { _MMIO(0x9888), 0x14bf0001 },
+ { _MMIO(0x9888), 0x12980340 },
+ { _MMIO(0x9888), 0x12990340 },
+ { _MMIO(0x9888), 0x0cbf1187 },
+ { _MMIO(0x9888), 0x0ebf1205 },
+ { _MMIO(0x9888), 0x00bf0500 },
+ { _MMIO(0x9888), 0x02bf042b },
+ { _MMIO(0x9888), 0x04bf002c },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x00da8000 },
+ { _MMIO(0x9888), 0x02dac000 },
+ { _MMIO(0x9888), 0x04da4000 },
+ { _MMIO(0x9888), 0x04983400 },
+ { _MMIO(0x9888), 0x10980000 },
+ { _MMIO(0x9888), 0x06990034 },
+ { _MMIO(0x9888), 0x10990000 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x009d8000 },
+ { _MMIO(0x9888), 0x029dc000 },
+ { _MMIO(0x9888), 0x049d4000 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00ba },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x00b94000 },
+ { _MMIO(0x9888), 0x02b95000 },
+ { _MMIO(0x9888), 0x04b91000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0cba4000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x258b800a },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x47800000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800060 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_1);
+ return mux_config_l3_1;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x103f03da },
+ { _MMIO(0x9888), 0x143f0001 },
+ { _MMIO(0x9888), 0x12180340 },
+ { _MMIO(0x9888), 0x12190340 },
+ { _MMIO(0x9888), 0x0c3f1187 },
+ { _MMIO(0x9888), 0x0e3f1205 },
+ { _MMIO(0x9888), 0x003f0500 },
+ { _MMIO(0x9888), 0x023f042b },
+ { _MMIO(0x9888), 0x043f002c },
+ { _MMIO(0x9888), 0x0c5ac000 },
+ { _MMIO(0x9888), 0x0e5ac000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x04183400 },
+ { _MMIO(0x9888), 0x10180000 },
+ { _MMIO(0x9888), 0x06190034 },
+ { _MMIO(0x9888), 0x10190000 },
+ { _MMIO(0x9888), 0x0c1dc000 },
+ { _MMIO(0x9888), 0x0e1dc000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x101f02a8 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00ba },
+ { _MMIO(0x9888), 0x0c388000 },
+ { _MMIO(0x9888), 0x0c395000 },
+ { _MMIO(0x9888), 0x0e395000 },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04391000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0c3a4000 },
+ { _MMIO(0x9888), 0x1b8aa800 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258b4005 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x47800000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800060 },
+};
+
+static const struct i915_oa_reg *
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_2);
+ return mux_config_l3_2;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x121b0340 },
+ { _MMIO(0x9888), 0x103f0274 },
+ { _MMIO(0x9888), 0x123f0000 },
+ { _MMIO(0x9888), 0x129b0340 },
+ { _MMIO(0x9888), 0x10bf0274 },
+ { _MMIO(0x9888), 0x12bf0000 },
+ { _MMIO(0x9888), 0x041b3400 },
+ { _MMIO(0x9888), 0x101b0000 },
+ { _MMIO(0x9888), 0x045c8000 },
+ { _MMIO(0x9888), 0x0a3d4000 },
+ { _MMIO(0x9888), 0x003f0080 },
+ { _MMIO(0x9888), 0x023f0793 },
+ { _MMIO(0x9888), 0x043f0014 },
+ { _MMIO(0x9888), 0x04588000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f002a },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04399000 },
+ { _MMIO(0x9888), 0x069b0034 },
+ { _MMIO(0x9888), 0x109b0000 },
+ { _MMIO(0x9888), 0x06dc4000 },
+ { _MMIO(0x9888), 0x0cbd4000 },
+ { _MMIO(0x9888), 0x0cbf0981 },
+ { _MMIO(0x9888), 0x0ebf0a0f },
+ { _MMIO(0x9888), 0x06d84000 },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x0cdb4000 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0e9f0080 },
+ { _MMIO(0x9888), 0x0cb84000 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x258b8009 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800c00 },
+ { _MMIO(0x9888), 0x47800c63 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f8014a5 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800045 },
+};
+
+static const struct i915_oa_reg *
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_3);
+ return mux_config_l3_3;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_4[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_4[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_4[] = {
+ { _MMIO(0x9888), 0x121a0340 },
+ { _MMIO(0x9888), 0x103f0017 },
+ { _MMIO(0x9888), 0x123f0020 },
+ { _MMIO(0x9888), 0x129a0340 },
+ { _MMIO(0x9888), 0x10bf0017 },
+ { _MMIO(0x9888), 0x12bf0020 },
+ { _MMIO(0x9888), 0x041a3400 },
+ { _MMIO(0x9888), 0x101a0000 },
+ { _MMIO(0x9888), 0x043b8000 },
+ { _MMIO(0x9888), 0x0a3e0010 },
+ { _MMIO(0x9888), 0x003f0200 },
+ { _MMIO(0x9888), 0x023f0113 },
+ { _MMIO(0x9888), 0x043f0014 },
+ { _MMIO(0x9888), 0x02592000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x0a1c8000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x0a1e8000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f001a },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04391000 },
+ { _MMIO(0x9888), 0x069a0034 },
+ { _MMIO(0x9888), 0x109a0000 },
+ { _MMIO(0x9888), 0x06bb4000 },
+ { _MMIO(0x9888), 0x0abe0040 },
+ { _MMIO(0x9888), 0x0cbf0984 },
+ { _MMIO(0x9888), 0x0ebf0a02 },
+ { _MMIO(0x9888), 0x02d94000 },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x0c9c0400 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x0c9e0400 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0e9f0040 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x258b8009 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800800 },
+ { _MMIO(0x9888), 0x47800842 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f801084 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800044 },
+};
+
+static const struct i915_oa_reg *
+get_l3_4_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_4);
+ return mux_config_l3_4;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00006000 },
+ { _MMIO(0x2774), 0x0000f3ff },
+ { _MMIO(0x2778), 0x00001800 },
+ { _MMIO(0x277c), 0x0000fcff },
+ { _MMIO(0x2780), 0x00000600 },
+ { _MMIO(0x2784), 0x0000ff3f },
+ { _MMIO(0x2788), 0x00000180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000060 },
+ { _MMIO(0x2794), 0x0000fff3 },
+ { _MMIO(0x2798), 0x00000018 },
+ { _MMIO(0x279c), 0x0000fffc },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x143b000e },
+ { _MMIO(0x9888), 0x043c55c0 },
+ { _MMIO(0x9888), 0x0a1e0280 },
+ { _MMIO(0x9888), 0x0c1e0408 },
+ { _MMIO(0x9888), 0x10390000 },
+ { _MMIO(0x9888), 0x12397a1f },
+ { _MMIO(0x9888), 0x14bb000e },
+ { _MMIO(0x9888), 0x04bc5000 },
+ { _MMIO(0x9888), 0x0a9e0296 },
+ { _MMIO(0x9888), 0x0c9e0008 },
+ { _MMIO(0x9888), 0x10b90000 },
+ { _MMIO(0x9888), 0x12b97a1f },
+ { _MMIO(0x9888), 0x063b0042 },
+ { _MMIO(0x9888), 0x103b0000 },
+ { _MMIO(0x9888), 0x083c0000 },
+ { _MMIO(0x9888), 0x0a3e0040 },
+ { _MMIO(0x9888), 0x043f8000 },
+ { _MMIO(0x9888), 0x02594000 },
+ { _MMIO(0x9888), 0x045a8000 },
+ { _MMIO(0x9888), 0x0c1c0400 },
+ { _MMIO(0x9888), 0x041d8000 },
+ { _MMIO(0x9888), 0x081e02c0 },
+ { _MMIO(0x9888), 0x0e1e0000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1f0260 },
+ { _MMIO(0x9888), 0x101f0014 },
+ { _MMIO(0x9888), 0x003905e0 },
+ { _MMIO(0x9888), 0x06390bc0 },
+ { _MMIO(0x9888), 0x02390018 },
+ { _MMIO(0x9888), 0x04394000 },
+ { _MMIO(0x9888), 0x04bb0042 },
+ { _MMIO(0x9888), 0x10bb0000 },
+ { _MMIO(0x9888), 0x02bc05c0 },
+ { _MMIO(0x9888), 0x08bc0000 },
+ { _MMIO(0x9888), 0x0abe0004 },
+ { _MMIO(0x9888), 0x02bf8000 },
+ { _MMIO(0x9888), 0x02d91000 },
+ { _MMIO(0x9888), 0x02da8000 },
+ { _MMIO(0x9888), 0x089c8000 },
+ { _MMIO(0x9888), 0x029d8000 },
+ { _MMIO(0x9888), 0x089e8000 },
+ { _MMIO(0x9888), 0x0e9e0000 },
+ { _MMIO(0x9888), 0x0e9fa806 },
+ { _MMIO(0x9888), 0x109f0142 },
+ { _MMIO(0x9888), 0x08b90617 },
+ { _MMIO(0x9888), 0x0ab90be0 },
+ { _MMIO(0x9888), 0x02b94000 },
+ { _MMIO(0x9888), 0x0d88f000 },
+ { _MMIO(0x9888), 0x0f88000c },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x1b8a2800 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x238b52a0 },
+ { _MMIO(0x9888), 0x258b6a95 },
+ { _MMIO(0x9888), 0x278b0029 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c1500 },
+ { _MMIO(0x9888), 0x1b8c0014 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038d8000 },
+ { _MMIO(0x9888), 0x058d2000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4d800444 },
+ { _MMIO(0x9888), 0x3d800000 },
+ { _MMIO(0x9888), 0x4f804000 },
+ { _MMIO(0x9888), 0x43801080 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800084 },
+ { _MMIO(0x9888), 0x53800044 },
+ { _MMIO(0x9888), 0x47801080 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x41800840 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler_1[] = {
+ { _MMIO(0x9888), 0x18921400 },
+ { _MMIO(0x9888), 0x149500ab },
+ { _MMIO(0x9888), 0x18b21400 },
+ { _MMIO(0x9888), 0x14b500ab },
+ { _MMIO(0x9888), 0x18d21400 },
+ { _MMIO(0x9888), 0x14d500ab },
+ { _MMIO(0x9888), 0x0cdc8000 },
+ { _MMIO(0x9888), 0x0edc4000 },
+ { _MMIO(0x9888), 0x02dcc000 },
+ { _MMIO(0x9888), 0x04dcc000 },
+ { _MMIO(0x9888), 0x1abd00a0 },
+ { _MMIO(0x9888), 0x0abd8000 },
+ { _MMIO(0x9888), 0x0cd88000 },
+ { _MMIO(0x9888), 0x0ed84000 },
+ { _MMIO(0x9888), 0x04d88000 },
+ { _MMIO(0x9888), 0x1adb0050 },
+ { _MMIO(0x9888), 0x04db8000 },
+ { _MMIO(0x9888), 0x06db8000 },
+ { _MMIO(0x9888), 0x08db8000 },
+ { _MMIO(0x9888), 0x0adb4000 },
+ { _MMIO(0x9888), 0x109f02a0 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00aa },
+ { _MMIO(0x9888), 0x18b82500 },
+ { _MMIO(0x9888), 0x02b88000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab84000 },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x0cb98000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x00b98000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x1aba0200 },
+ { _MMIO(0x9888), 0x02ba8000 },
+ { _MMIO(0x9888), 0x0cba8000 },
+ { _MMIO(0x9888), 0x04908000 },
+ { _MMIO(0x9888), 0x04918000 },
+ { _MMIO(0x9888), 0x04927300 },
+ { _MMIO(0x9888), 0x10920000 },
+ { _MMIO(0x9888), 0x1893000a },
+ { _MMIO(0x9888), 0x0a934000 },
+ { _MMIO(0x9888), 0x0a946000 },
+ { _MMIO(0x9888), 0x0c959000 },
+ { _MMIO(0x9888), 0x0e950098 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x04b04000 },
+ { _MMIO(0x9888), 0x04b14000 },
+ { _MMIO(0x9888), 0x04b20073 },
+ { _MMIO(0x9888), 0x10b20000 },
+ { _MMIO(0x9888), 0x04b38000 },
+ { _MMIO(0x9888), 0x06b38000 },
+ { _MMIO(0x9888), 0x08b34000 },
+ { _MMIO(0x9888), 0x04b4c000 },
+ { _MMIO(0x9888), 0x02b59890 },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x06d04000 },
+ { _MMIO(0x9888), 0x06d14000 },
+ { _MMIO(0x9888), 0x06d20073 },
+ { _MMIO(0x9888), 0x10d20000 },
+ { _MMIO(0x9888), 0x18d30020 },
+ { _MMIO(0x9888), 0x02d38000 },
+ { _MMIO(0x9888), 0x0cd34000 },
+ { _MMIO(0x9888), 0x0ad48000 },
+ { _MMIO(0x9888), 0x04d42000 },
+ { _MMIO(0x9888), 0x0ed59000 },
+ { _MMIO(0x9888), 0x00d59800 },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x0f88000e },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x258b000a },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8d8000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x2185000a },
+ { _MMIO(0x9888), 0x1b830150 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d848000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d808000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801021 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800c64 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800c02 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler_1);
+ return mux_config_sampler_1;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler_2[] = {
+ { _MMIO(0x9888), 0x18121400 },
+ { _MMIO(0x9888), 0x141500ab },
+ { _MMIO(0x9888), 0x18321400 },
+ { _MMIO(0x9888), 0x143500ab },
+ { _MMIO(0x9888), 0x18521400 },
+ { _MMIO(0x9888), 0x145500ab },
+ { _MMIO(0x9888), 0x0c5c8000 },
+ { _MMIO(0x9888), 0x0e5c4000 },
+ { _MMIO(0x9888), 0x025cc000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x1a3d00a0 },
+ { _MMIO(0x9888), 0x0a3d8000 },
+ { _MMIO(0x9888), 0x0c588000 },
+ { _MMIO(0x9888), 0x0e584000 },
+ { _MMIO(0x9888), 0x04588000 },
+ { _MMIO(0x9888), 0x1a5b0050 },
+ { _MMIO(0x9888), 0x045b8000 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b8000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x101f02a0 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x18382500 },
+ { _MMIO(0x9888), 0x02388000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x06384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c388000 },
+ { _MMIO(0x9888), 0x0c398000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x1a3a0200 },
+ { _MMIO(0x9888), 0x023a8000 },
+ { _MMIO(0x9888), 0x0c3a8000 },
+ { _MMIO(0x9888), 0x04108000 },
+ { _MMIO(0x9888), 0x04118000 },
+ { _MMIO(0x9888), 0x04127300 },
+ { _MMIO(0x9888), 0x10120000 },
+ { _MMIO(0x9888), 0x1813000a },
+ { _MMIO(0x9888), 0x0a134000 },
+ { _MMIO(0x9888), 0x0a146000 },
+ { _MMIO(0x9888), 0x0c159000 },
+ { _MMIO(0x9888), 0x0e150098 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04304000 },
+ { _MMIO(0x9888), 0x04314000 },
+ { _MMIO(0x9888), 0x04320073 },
+ { _MMIO(0x9888), 0x10320000 },
+ { _MMIO(0x9888), 0x04338000 },
+ { _MMIO(0x9888), 0x06338000 },
+ { _MMIO(0x9888), 0x08334000 },
+ { _MMIO(0x9888), 0x0434c000 },
+ { _MMIO(0x9888), 0x02359890 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x06504000 },
+ { _MMIO(0x9888), 0x06514000 },
+ { _MMIO(0x9888), 0x06520073 },
+ { _MMIO(0x9888), 0x10520000 },
+ { _MMIO(0x9888), 0x18530020 },
+ { _MMIO(0x9888), 0x02538000 },
+ { _MMIO(0x9888), 0x0c534000 },
+ { _MMIO(0x9888), 0x0a548000 },
+ { _MMIO(0x9888), 0x04542000 },
+ { _MMIO(0x9888), 0x0e559000 },
+ { _MMIO(0x9888), 0x00559800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x1b8aa000 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x258b0005 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x2185000a },
+ { _MMIO(0x9888), 0x1b830150 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d848000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d808000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801021 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800c64 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800c02 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler_2);
+ return mux_config_sampler_2;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x0000fe7f },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000ffbf },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fff7 },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fff9 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x16154d60 },
+ { _MMIO(0x9888), 0x16352e60 },
+ { _MMIO(0x9888), 0x16554d60 },
+ { _MMIO(0x9888), 0x16950000 },
+ { _MMIO(0x9888), 0x16b50000 },
+ { _MMIO(0x9888), 0x16d50000 },
+ { _MMIO(0x9888), 0x005c8000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x065c4000 },
+ { _MMIO(0x9888), 0x083d8000 },
+ { _MMIO(0x9888), 0x0a3d8000 },
+ { _MMIO(0x9888), 0x0458c000 },
+ { _MMIO(0x9888), 0x025b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04388000 },
+ { _MMIO(0x9888), 0x06388000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c384000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x043a8000 },
+ { _MMIO(0x9888), 0x063a8000 },
+ { _MMIO(0x9888), 0x08138000 },
+ { _MMIO(0x9888), 0x0a138000 },
+ { _MMIO(0x9888), 0x06143000 },
+ { _MMIO(0x9888), 0x0415cfc7 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x02338000 },
+ { _MMIO(0x9888), 0x0c338000 },
+ { _MMIO(0x9888), 0x04342000 },
+ { _MMIO(0x9888), 0x06344000 },
+ { _MMIO(0x9888), 0x0035c700 },
+ { _MMIO(0x9888), 0x063500cf },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04538000 },
+ { _MMIO(0x9888), 0x06538000 },
+ { _MMIO(0x9888), 0x0454c000 },
+ { _MMIO(0x9888), 0x0255cfc7 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06dc8000 },
+ { _MMIO(0x9888), 0x08dc4000 },
+ { _MMIO(0x9888), 0x0cdcc000 },
+ { _MMIO(0x9888), 0x0edcc000 },
+ { _MMIO(0x9888), 0x1abd00a8 },
+ { _MMIO(0x9888), 0x0cd8c000 },
+ { _MMIO(0x9888), 0x0ed84000 },
+ { _MMIO(0x9888), 0x0edb8000 },
+ { _MMIO(0x9888), 0x18db0800 },
+ { _MMIO(0x9888), 0x1adb0254 },
+ { _MMIO(0x9888), 0x0e9faa00 },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x0eb84000 },
+ { _MMIO(0x9888), 0x16b84000 },
+ { _MMIO(0x9888), 0x18b8156a },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x18baa000 },
+ { _MMIO(0x9888), 0x1aba0002 },
+ { _MMIO(0x9888), 0x16934000 },
+ { _MMIO(0x9888), 0x1893000a },
+ { _MMIO(0x9888), 0x0a947000 },
+ { _MMIO(0x9888), 0x0c95c5c1 },
+ { _MMIO(0x9888), 0x0e9500c3 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x0eb38000 },
+ { _MMIO(0x9888), 0x16b30040 },
+ { _MMIO(0x9888), 0x18b30020 },
+ { _MMIO(0x9888), 0x06b48000 },
+ { _MMIO(0x9888), 0x08b41000 },
+ { _MMIO(0x9888), 0x0ab48000 },
+ { _MMIO(0x9888), 0x06b5c500 },
+ { _MMIO(0x9888), 0x08b500c3 },
+ { _MMIO(0x9888), 0x0eb5c100 },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x16d31500 },
+ { _MMIO(0x9888), 0x08d4e000 },
+ { _MMIO(0x9888), 0x08d5c100 },
+ { _MMIO(0x9888), 0x0ad5c3c5 },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258baaa5 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800c42 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800063 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800800 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f8014a4 },
+ { _MMIO(0x9888), 0x41801042 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x0000fe7f },
+ { _MMIO(0x2780), 0x00000000 },
+ { _MMIO(0x2784), 0x0000ff9f },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000ffe7 },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fffb },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000fffd },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x16150000 },
+ { _MMIO(0x9888), 0x16350000 },
+ { _MMIO(0x9888), 0x16550000 },
+ { _MMIO(0x9888), 0x16952e60 },
+ { _MMIO(0x9888), 0x16b54d60 },
+ { _MMIO(0x9888), 0x16d52e60 },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5c4000 },
+ { _MMIO(0x9888), 0x0e3d8000 },
+ { _MMIO(0x9888), 0x183da000 },
+ { _MMIO(0x9888), 0x06588000 },
+ { _MMIO(0x9888), 0x08588000 },
+ { _MMIO(0x9888), 0x0a584000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x185b5800 },
+ { _MMIO(0x9888), 0x1a5b000a },
+ { _MMIO(0x9888), 0x0e1faa00 },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18382a55 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x1a3a02a0 },
+ { _MMIO(0x9888), 0x0e138000 },
+ { _MMIO(0x9888), 0x16130500 },
+ { _MMIO(0x9888), 0x06148000 },
+ { _MMIO(0x9888), 0x08146000 },
+ { _MMIO(0x9888), 0x0615c100 },
+ { _MMIO(0x9888), 0x0815c500 },
+ { _MMIO(0x9888), 0x0a1500c3 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x16335040 },
+ { _MMIO(0x9888), 0x08349000 },
+ { _MMIO(0x9888), 0x0a341000 },
+ { _MMIO(0x9888), 0x083500c1 },
+ { _MMIO(0x9888), 0x0a35c500 },
+ { _MMIO(0x9888), 0x0c3500c3 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x1853002a },
+ { _MMIO(0x9888), 0x0a54e000 },
+ { _MMIO(0x9888), 0x0c55c500 },
+ { _MMIO(0x9888), 0x0e55c1c3 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x00dc8000 },
+ { _MMIO(0x9888), 0x02dcc000 },
+ { _MMIO(0x9888), 0x04dc4000 },
+ { _MMIO(0x9888), 0x04bd8000 },
+ { _MMIO(0x9888), 0x06bd8000 },
+ { _MMIO(0x9888), 0x02d8c000 },
+ { _MMIO(0x9888), 0x02db8000 },
+ { _MMIO(0x9888), 0x04db4000 },
+ { _MMIO(0x9888), 0x06db4000 },
+ { _MMIO(0x9888), 0x08db8000 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00aa },
+ { _MMIO(0x9888), 0x02b84000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab88000 },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x00b98000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0aba8000 },
+ { _MMIO(0x9888), 0x0cba8000 },
+ { _MMIO(0x9888), 0x04938000 },
+ { _MMIO(0x9888), 0x06938000 },
+ { _MMIO(0x9888), 0x0494c000 },
+ { _MMIO(0x9888), 0x0295cfc7 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x02b38000 },
+ { _MMIO(0x9888), 0x08b38000 },
+ { _MMIO(0x9888), 0x04b42000 },
+ { _MMIO(0x9888), 0x06b41000 },
+ { _MMIO(0x9888), 0x00b5c700 },
+ { _MMIO(0x9888), 0x04b500cf },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x0ad38000 },
+ { _MMIO(0x9888), 0x0cd38000 },
+ { _MMIO(0x9888), 0x06d46000 },
+ { _MMIO(0x9888), 0x04d5c700 },
+ { _MMIO(0x9888), 0x06d500cf },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x258b555a },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800882 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45801082 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x478014a5 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800002 },
+ { _MMIO(0x9888), 0x41800c62 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+ { _MMIO(0xe458), 0x00001000 },
+ { _MMIO(0xe558), 0x00003002 },
+ { _MMIO(0xe658), 0x00005004 },
+ { _MMIO(0xe758), 0x00011010 },
+ { _MMIO(0xe45c), 0x00050012 },
+ { _MMIO(0xe55c), 0x00052051 },
+ { _MMIO(0xe65c), 0x00000008 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x161503e0 },
+ { _MMIO(0x9888), 0x163503e0 },
+ { _MMIO(0x9888), 0x165503e0 },
+ { _MMIO(0x9888), 0x169503e0 },
+ { _MMIO(0x9888), 0x16b503e0 },
+ { _MMIO(0x9888), 0x16d503e0 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x083d8000 },
+ { _MMIO(0x9888), 0x04584000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5b8000 },
+ { _MMIO(0x9888), 0x0e1f00a8 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c388000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0c3a8000 },
+ { _MMIO(0x9888), 0x08138000 },
+ { _MMIO(0x9888), 0x06141000 },
+ { _MMIO(0x9888), 0x041500c3 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x0a338000 },
+ { _MMIO(0x9888), 0x06342000 },
+ { _MMIO(0x9888), 0x0435c300 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x0c538000 },
+ { _MMIO(0x9888), 0x06544000 },
+ { _MMIO(0x9888), 0x065500c3 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x00dc8000 },
+ { _MMIO(0x9888), 0x02dc4000 },
+ { _MMIO(0x9888), 0x02bd8000 },
+ { _MMIO(0x9888), 0x00d88000 },
+ { _MMIO(0x9888), 0x02db4000 },
+ { _MMIO(0x9888), 0x04db8000 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f0002 },
+ { _MMIO(0x9888), 0x02b84000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b88000 },
+ { _MMIO(0x9888), 0x00b98000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x06ba8000 },
+ { _MMIO(0x9888), 0x02938000 },
+ { _MMIO(0x9888), 0x04942000 },
+ { _MMIO(0x9888), 0x0095c300 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x04b38000 },
+ { _MMIO(0x9888), 0x04b44000 },
+ { _MMIO(0x9888), 0x02b500c3 },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x06d38000 },
+ { _MMIO(0x9888), 0x04d48000 },
+ { _MMIO(0x9888), 0x02d5c300 },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x238b3500 },
+ { _MMIO(0x9888), 0x258b0005 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x2185000a },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800c40 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41801482 },
+ { _MMIO(0x9888), 0x31800000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extra);
+ return mux_config_compute_extra;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x14100812 },
+ { _MMIO(0x9888), 0x14125800 },
+ { _MMIO(0x9888), 0x161200c0 },
+ { _MMIO(0x9888), 0x14300812 },
+ { _MMIO(0x9888), 0x14325800 },
+ { _MMIO(0x9888), 0x163200c0 },
+ { _MMIO(0x9888), 0x005c4000 },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5cc000 },
+ { _MMIO(0x9888), 0x003d8000 },
+ { _MMIO(0x9888), 0x0e3d8000 },
+ { _MMIO(0x9888), 0x183d2800 },
+ { _MMIO(0x9888), 0x00584000 },
+ { _MMIO(0x9888), 0x06588000 },
+ { _MMIO(0x9888), 0x0858c000 },
+ { _MMIO(0x9888), 0x005b4000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x185b9400 },
+ { _MMIO(0x9888), 0x1a5b002a },
+ { _MMIO(0x9888), 0x0c1f0800 },
+ { _MMIO(0x9888), 0x0e1faa00 },
+ { _MMIO(0x9888), 0x101f002a },
+ { _MMIO(0x9888), 0x00384000 },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18380155 },
+ { _MMIO(0x9888), 0x00392000 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x00100047 },
+ { _MMIO(0x9888), 0x06101a80 },
+ { _MMIO(0x9888), 0x10100000 },
+ { _MMIO(0x9888), 0x0810c000 },
+ { _MMIO(0x9888), 0x0811c000 },
+ { _MMIO(0x9888), 0x08126151 },
+ { _MMIO(0x9888), 0x10120000 },
+ { _MMIO(0x9888), 0x00134000 },
+ { _MMIO(0x9888), 0x0e134000 },
+ { _MMIO(0x9888), 0x161300a0 },
+ { _MMIO(0x9888), 0x0a301ac7 },
+ { _MMIO(0x9888), 0x10300000 },
+ { _MMIO(0x9888), 0x0c30c000 },
+ { _MMIO(0x9888), 0x0c31c000 },
+ { _MMIO(0x9888), 0x0c326151 },
+ { _MMIO(0x9888), 0x10320000 },
+ { _MMIO(0x9888), 0x16332a00 },
+ { _MMIO(0x9888), 0x18330001 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8a2aa0 },
+ { _MMIO(0x9888), 0x238b0020 },
+ { _MMIO(0x9888), 0x258b5550 },
+ { _MMIO(0x9888), 0x278b0001 },
+ { _MMIO(0x9888), 0x1f850080 },
+ { _MMIO(0x9888), 0x2185aaa0 },
+ { _MMIO(0x9888), 0x23850002 },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830015 },
+ { _MMIO(0x9888), 0x01844000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x11804000 },
+ { _MMIO(0x9888), 0x17808000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3d800800 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800002 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800884 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800002 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+};
+
+static const struct i915_oa_reg *
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_vme_pipe);
+ return mux_config_vme_pipe;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x198b0000 },
+ { _MMIO(0x9888), 0x078b0066 },
+ { _MMIO(0x9888), 0x118b0000 },
+ { _MMIO(0x9888), 0x258b0000 },
+ { _MMIO(0x9888), 0x21850008 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800000 },
+ { _MMIO(0x9888), 0x31800000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
+int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_reads_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_reads;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_reads);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_reads;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_DATA_PORT_READS_COALESCING:
+ dev_priv->perf.oa.mux_regs =
+ get_data_port_reads_coalescing_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_data_port_reads_coalescing;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_data_port_reads_coalescing);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_data_port_reads_coalescing;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing);
+
+ return 0;
+ case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING:
+ dev_priv->perf.oa.mux_regs =
+ get_data_port_writes_coalescing_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_data_port_writes_coalescing;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_data_port_writes_coalescing);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_data_port_writes_coalescing;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_L3_4:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_4_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_4;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_4);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_4;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_4);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER_1:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler_1);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER_2:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler_2);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
+ .attrs = attrs_render_basic,
+};
+
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "35fbc9b2-a891-40a6-a38d-022bb7057552",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "233d0544-fff7-4281-8291-e02f222aff72",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "27a364dc-8225-4ecb-b607-d6f1925598d9",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING);
+}
+
+static struct device_attribute dev_attr_data_port_reads_coalescing_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_data_port_reads_coalescing_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_data_port_reads_coalescing[] = {
+ &dev_attr_data_port_reads_coalescing_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_data_port_reads_coalescing = {
+ .name = "857fc630-2f09-4804-85f1-084adfadd5ab",
+ .attrs = attrs_data_port_reads_coalescing,
+};
+
+static ssize_t
+show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING);
+}
+
+static struct device_attribute dev_attr_data_port_writes_coalescing_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_data_port_writes_coalescing_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_data_port_writes_coalescing[] = {
+ &dev_attr_data_port_writes_coalescing_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_data_port_writes_coalescing = {
+ .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20",
+ .attrs = attrs_data_port_writes_coalescing,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
+}
+
+static struct device_attribute dev_attr_l3_4_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_4_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_4[] = {
+ &dev_attr_l3_4_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_4 = {
+ .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
+ .attrs = attrs_l3_4,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
+}
+
+static struct device_attribute dev_attr_sampler_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler_1[] = {
+ &dev_attr_sampler_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler_1 = {
+ .name = "71148d78-baf5-474f-878a-e23158d0265d",
+ .attrs = attrs_sampler_1,
+};
+
+static ssize_t
+show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
+}
+
+static struct device_attribute dev_attr_sampler_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler_2[] = {
+ &dev_attr_sampler_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler_2 = {
+ .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
+ .attrs = attrs_sampler_2,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e",
+ .attrs = attrs_test_oa,
+};
+
+int
+i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_data_port_reads_coalescing_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
+ if (ret)
+ goto error_data_port_reads_coalescing;
+ }
+ if (get_data_port_writes_coalescing_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
+ if (ret)
+ goto error_data_port_writes_coalescing;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_l3_4_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+ if (ret)
+ goto error_l3_4;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+ if (ret)
+ goto error_sampler_1;
+ }
+ if (get_sampler_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+ if (ret)
+ goto error_sampler_2;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
+
+ return 0;
+
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+error_sampler_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+error_sampler_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+error_l3_4:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
+error_data_port_writes_coalescing:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
+error_data_port_reads_coalescing:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -368,4 +4909,46 @@ i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_data_port_reads_coalescing_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing);
+ if (get_data_port_writes_coalescing_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_l3_4_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+ if (get_sampler_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c
index 6d78cdb7a73d..c8d7e4ede2ac 100644
--- a/drivers/gpu/drm/i915/i915_oa_bxt.c
+++ b/drivers/gpu/drm/i915/i915_oa_bxt.c
@@ -31,15 +31,30 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_bxt = 1;
+int i915_oa_n_builtin_metric_sets_bxt = 15;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_render_basic[] = {
@@ -56,9 +71,10 @@ static const struct i915_oa_reg mux_config_render_basic_0_0_sku_gte_0x03[] = {
{ _MMIO(0x9888), 0x166c00f0 },
{ _MMIO(0x9888), 0x12120280 },
{ _MMIO(0x9888), 0x12320280 },
+ { _MMIO(0x9888), 0x11930317 },
{ _MMIO(0x9888), 0x159303df },
{ _MMIO(0x9888), 0x3f900c00 },
- { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x419000a0 },
{ _MMIO(0x9888), 0x002d1000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x082d5000 },
@@ -98,14 +114,13 @@ static const struct i915_oa_reg mux_config_render_basic_0_0_sku_gte_0x03[] = {
{ _MMIO(0x9888), 0x0d931831 },
{ _MMIO(0x9888), 0x0f939f3f },
{ _MMIO(0x9888), 0x01939e80 },
- { _MMIO(0x9888), 0x03931dbc },
- { _MMIO(0x9888), 0x0593003a },
- { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x039303bc },
+ { _MMIO(0x9888), 0x0593000e },
{ _MMIO(0x9888), 0x1993002a },
{ _MMIO(0x9888), 0x07930000 },
{ _MMIO(0x9888), 0x09930000 },
{ _MMIO(0x9888), 0x1d900177 },
- { _MMIO(0x9888), 0x1f900178 },
+ { _MMIO(0x9888), 0x1f900187 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
@@ -134,180 +149,2356 @@ static const struct i915_oa_reg mux_config_render_basic_0_0_sku_gte_0x03[] = {
{ _MMIO(0x9888), 0x45900821 },
};
-static const struct i915_oa_reg mux_config_render_basic_0_0_sku_lt_0x03[] = {
- { _MMIO(0x9888), 0x166c00f0 },
- { _MMIO(0x9888), 0x12120280 },
- { _MMIO(0x9888), 0x12320280 },
- { _MMIO(0x9888), 0x159303df },
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (dev_priv->drm.pdev->revision >= 0x03) {
+ *len = ARRAY_SIZE(mux_config_render_basic_0_0_sku_gte_0x03);
+ return mux_config_render_basic_0_0_sku_gte_0x03;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x39900340 },
{ _MMIO(0x9888), 0x3f900c00 },
- { _MMIO(0x9888), 0x419000a0 },
- { _MMIO(0x9888), 0x002d1000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x002d5000 },
{ _MMIO(0x9888), 0x062d4000 },
- { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x082d4000 },
{ _MMIO(0x9888), 0x0a2d1000 },
- { _MMIO(0x9888), 0x0c2e0800 },
- { _MMIO(0x9888), 0x0e2e5900 },
+ { _MMIO(0x9888), 0x0c2d5000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x0c2e1400 },
+ { _MMIO(0x9888), 0x0e2e5100 },
+ { _MMIO(0x9888), 0x102e0114 },
+ { _MMIO(0x9888), 0x044cc000 },
{ _MMIO(0x9888), 0x0a4c8000 },
{ _MMIO(0x9888), 0x0c4c8000 },
{ _MMIO(0x9888), 0x0e4c4000 },
+ { _MMIO(0x9888), 0x104c8000 },
+ { _MMIO(0x9888), 0x124c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x004ea000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e2000 },
- { _MMIO(0x9888), 0x1c4f0010 },
- { _MMIO(0x9888), 0x0a6c0053 },
- { _MMIO(0x9888), 0x106c0000 },
- { _MMIO(0x9888), 0x1c6c0000 },
- { _MMIO(0x9888), 0x1a0fcc00 },
- { _MMIO(0x9888), 0x1c0f0002 },
- { _MMIO(0x9888), 0x1c2c0040 },
- { _MMIO(0x9888), 0x00101000 },
- { _MMIO(0x9888), 0x04101000 },
- { _MMIO(0x9888), 0x00114000 },
- { _MMIO(0x9888), 0x08114000 },
- { _MMIO(0x9888), 0x00120020 },
- { _MMIO(0x9888), 0x08120021 },
- { _MMIO(0x9888), 0x00141000 },
- { _MMIO(0x9888), 0x08141000 },
- { _MMIO(0x9888), 0x02308000 },
- { _MMIO(0x9888), 0x04302000 },
- { _MMIO(0x9888), 0x06318000 },
- { _MMIO(0x9888), 0x08318000 },
- { _MMIO(0x9888), 0x06320800 },
- { _MMIO(0x9888), 0x08320840 },
- { _MMIO(0x9888), 0x00320000 },
- { _MMIO(0x9888), 0x06344000 },
- { _MMIO(0x9888), 0x08344000 },
- { _MMIO(0x9888), 0x0d931831 },
- { _MMIO(0x9888), 0x0f939f3f },
- { _MMIO(0x9888), 0x01939e80 },
- { _MMIO(0x9888), 0x03931dbc },
- { _MMIO(0x9888), 0x0593003a },
- { _MMIO(0x9888), 0x11930000 },
- { _MMIO(0x9888), 0x1993002a },
- { _MMIO(0x9888), 0x07930000 },
- { _MMIO(0x9888), 0x09930000 },
- { _MMIO(0x9888), 0x1d900177 },
- { _MMIO(0x9888), 0x1f900187 },
+ { _MMIO(0x9888), 0x0c4ea000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x004f6b42 },
+ { _MMIO(0x9888), 0x064f6200 },
+ { _MMIO(0x9888), 0x084f4100 },
+ { _MMIO(0x9888), 0x0a4f0061 },
+ { _MMIO(0x9888), 0x0c4f6c4c },
+ { _MMIO(0x9888), 0x0e4f4b00 },
+ { _MMIO(0x9888), 0x1a4f0000 },
+ { _MMIO(0x9888), 0x1c4f0000 },
+ { _MMIO(0x9888), 0x180f5000 },
+ { _MMIO(0x9888), 0x1a0f8800 },
+ { _MMIO(0x9888), 0x1c0f08a2 },
+ { _MMIO(0x9888), 0x182c4000 },
+ { _MMIO(0x9888), 0x1c2c1451 },
+ { _MMIO(0x9888), 0x1e2c0001 },
+ { _MMIO(0x9888), 0x1a2c0010 },
+ { _MMIO(0x9888), 0x01938000 },
+ { _MMIO(0x9888), 0x0f938000 },
+ { _MMIO(0x9888), 0x19938a28 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x19900177 },
+ { _MMIO(0x9888), 0x1b900178 },
+ { _MMIO(0x9888), 0x1d900125 },
+ { _MMIO(0x9888), 0x1f900123 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
- { _MMIO(0x9888), 0x23904000 },
{ _MMIO(0x9888), 0x25904000 },
{ _MMIO(0x9888), 0x27904000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2d904000 },
- { _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
- { _MMIO(0x9888), 0x17904000 },
- { _MMIO(0x9888), 0x19904000 },
- { _MMIO(0x9888), 0x1b904000 },
- { _MMIO(0x9888), 0x53901110 },
- { _MMIO(0x9888), 0x43900423 },
+ { _MMIO(0x9888), 0x53901000 },
+ { _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x55900111 },
- { _MMIO(0x9888), 0x47900c02 },
+ { _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x57900000 },
- { _MMIO(0x9888), 0x49900020 },
- { _MMIO(0x9888), 0x59901111 },
- { _MMIO(0x9888), 0x4b900421 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
- { _MMIO(0x9888), 0x4d900001 },
- { _MMIO(0x9888), 0x45900821 },
+ { _MMIO(0x9888), 0x4d900000 },
+ { _MMIO(0x9888), 0x45900000 },
};
static const struct i915_oa_reg *
-get_render_basic_mux_config(struct drm_i915_private *dev_priv,
- int *len)
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- if (dev_priv->drm.pdev->revision >= 0x03) {
- *len = ARRAY_SIZE(mux_config_render_basic_0_0_sku_gte_0x03);
- return mux_config_render_basic_0_0_sku_gte_0x03;
- } else if (dev_priv->drm.pdev->revision < 0x03) {
- *len = ARRAY_SIZE(mux_config_render_basic_0_0_sku_lt_0x03);
- return mux_config_render_basic_0_0_sku_lt_0x03;
- }
-
- *len = 0;
- return NULL;
+ *len = ARRAY_SIZE(mux_config_compute_basic);
+ return mux_config_compute_basic;
}
-int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
-{
- dev_priv->perf.oa.mux_regs = NULL;
- dev_priv->perf.oa.mux_regs_len = 0;
- dev_priv->perf.oa.b_counter_regs = NULL;
- dev_priv->perf.oa.b_counter_regs_len = 0;
- dev_priv->perf.oa.flex_regs = NULL;
- dev_priv->perf.oa.flex_regs_len = 0;
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
- dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
- &dev_priv->perf.oa.mux_regs_len);
- if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
- /* EINVAL because *_register_sysfs already checked this
- * and so it wouldn't have been advertised so userspace and
- * so shouldn't have been requested
- */
- return -EINVAL;
- }
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0c2e001f },
+ { _MMIO(0x9888), 0x0a2f0000 },
+ { _MMIO(0x9888), 0x10186800 },
+ { _MMIO(0x9888), 0x11810019 },
+ { _MMIO(0x9888), 0x15810013 },
+ { _MMIO(0x9888), 0x13820020 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x17840000 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x21860000 },
+ { _MMIO(0x9888), 0x178703e0 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x022e5400 },
+ { _MMIO(0x9888), 0x002e0000 },
+ { _MMIO(0x9888), 0x0e2e0080 },
+ { _MMIO(0x9888), 0x082f0040 },
+ { _MMIO(0x9888), 0x002f0000 },
+ { _MMIO(0x9888), 0x06143000 },
+ { _MMIO(0x9888), 0x06174000 },
+ { _MMIO(0x9888), 0x06180012 },
+ { _MMIO(0x9888), 0x00180000 },
+ { _MMIO(0x9888), 0x0d804000 },
+ { _MMIO(0x9888), 0x0f804000 },
+ { _MMIO(0x9888), 0x05804000 },
+ { _MMIO(0x9888), 0x09810200 },
+ { _MMIO(0x9888), 0x0b810030 },
+ { _MMIO(0x9888), 0x03810003 },
+ { _MMIO(0x9888), 0x21819140 },
+ { _MMIO(0x9888), 0x23819050 },
+ { _MMIO(0x9888), 0x25810018 },
+ { _MMIO(0x9888), 0x0b820980 },
+ { _MMIO(0x9888), 0x03820d80 },
+ { _MMIO(0x9888), 0x11820000 },
+ { _MMIO(0x9888), 0x0182c000 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x09824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0d830004 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x0f831000 },
+ { _MMIO(0x9888), 0x01848072 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x07848000 },
+ { _MMIO(0x9888), 0x09844000 },
+ { _MMIO(0x9888), 0x0f848000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x09860092 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x01869100 },
+ { _MMIO(0x9888), 0x0f870065 },
+ { _MMIO(0x9888), 0x01870000 },
+ { _MMIO(0x9888), 0x19930800 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x1b952000 },
+ { _MMIO(0x9888), 0x1d955055 },
+ { _MMIO(0x9888), 0x1f951455 },
+ { _MMIO(0x9888), 0x0992a000 },
+ { _MMIO(0x9888), 0x0f928000 },
+ { _MMIO(0x9888), 0x1192a800 },
+ { _MMIO(0x9888), 0x1392028a },
+ { _MMIO(0x9888), 0x0b92a000 },
+ { _MMIO(0x9888), 0x0d922000 },
+ { _MMIO(0x9888), 0x13908000 },
+ { _MMIO(0x9888), 0x21908000 },
+ { _MMIO(0x9888), 0x23908000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27908000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900c01 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900863 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900061 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900000 },
+ { _MMIO(0x9888), 0x45900c22 },
+};
- dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
- dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile);
+ return mux_config_render_pipe_profile;
+}
- dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
- dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
- return 0;
- default:
- return -ENODEV;
- }
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x19800343 },
+ { _MMIO(0x9888), 0x39900340 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x41900003 },
+ { _MMIO(0x9888), 0x03803180 },
+ { _MMIO(0x9888), 0x058035e2 },
+ { _MMIO(0x9888), 0x0780006a },
+ { _MMIO(0x9888), 0x11800000 },
+ { _MMIO(0x9888), 0x2181a000 },
+ { _MMIO(0x9888), 0x2381000a },
+ { _MMIO(0x9888), 0x1d950550 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d92a000 },
+ { _MMIO(0x9888), 0x0f922000 },
+ { _MMIO(0x9888), 0x13900170 },
+ { _MMIO(0x9888), 0x21900171 },
+ { _MMIO(0x9888), 0x23900172 },
+ { _MMIO(0x9888), 0x25900173 },
+ { _MMIO(0x9888), 0x27900174 },
+ { _MMIO(0x9888), 0x29900175 },
+ { _MMIO(0x9888), 0x2b900176 },
+ { _MMIO(0x9888), 0x2d900177 },
+ { _MMIO(0x9888), 0x2f90017f },
+ { _MMIO(0x9888), 0x31900125 },
+ { _MMIO(0x9888), 0x15900123 },
+ { _MMIO(0x9888), 0x17900121 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43901084 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47901080 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49901084 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b901084 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900004 },
+ { _MMIO(0x9888), 0x45900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_memory_reads);
+ return mux_config_memory_reads;
}
-static ssize_t
-show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x19800343 },
+ { _MMIO(0x9888), 0x39900340 },
+ { _MMIO(0x9888), 0x3f900000 },
+ { _MMIO(0x9888), 0x41900080 },
+ { _MMIO(0x9888), 0x03803180 },
+ { _MMIO(0x9888), 0x058035e2 },
+ { _MMIO(0x9888), 0x0780006a },
+ { _MMIO(0x9888), 0x11800000 },
+ { _MMIO(0x9888), 0x2181a000 },
+ { _MMIO(0x9888), 0x2381000a },
+ { _MMIO(0x9888), 0x1d950550 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d92a000 },
+ { _MMIO(0x9888), 0x0f922000 },
+ { _MMIO(0x9888), 0x13900180 },
+ { _MMIO(0x9888), 0x21900181 },
+ { _MMIO(0x9888), 0x23900182 },
+ { _MMIO(0x9888), 0x25900183 },
+ { _MMIO(0x9888), 0x27900184 },
+ { _MMIO(0x9888), 0x29900185 },
+ { _MMIO(0x9888), 0x2b900186 },
+ { _MMIO(0x9888), 0x2d900187 },
+ { _MMIO(0x9888), 0x2f900170 },
+ { _MMIO(0x9888), 0x31900125 },
+ { _MMIO(0x9888), 0x15900123 },
+ { _MMIO(0x9888), 0x17900121 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43901084 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47901080 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49901084 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b901084 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900004 },
+ { _MMIO(0x9888), 0x45900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+ *len = ARRAY_SIZE(mux_config_memory_writes);
+ return mux_config_memory_writes;
}
-static struct device_attribute dev_attr_render_basic_id = {
- .attr = { .name = "id", .mode = 0444 },
- .show = show_render_basic_id,
- .store = NULL,
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
};
-static struct attribute *attrs_render_basic[] = {
- &dev_attr_render_basic_id.attr,
- NULL,
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
};
-static struct attribute_group group_render_basic = {
- .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
- .attrs = attrs_render_basic,
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x141c0160 },
+ { _MMIO(0x9888), 0x161c0015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x002d5000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x0a2d5000 },
+ { _MMIO(0x9888), 0x0c2d5000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x0c2e5400 },
+ { _MMIO(0x9888), 0x0e2e5515 },
+ { _MMIO(0x9888), 0x102e0155 },
+ { _MMIO(0x9888), 0x044cc000 },
+ { _MMIO(0x9888), 0x0a4c8000 },
+ { _MMIO(0x9888), 0x0c4cc000 },
+ { _MMIO(0x9888), 0x0e4cc000 },
+ { _MMIO(0x9888), 0x104c8000 },
+ { _MMIO(0x9888), 0x124c8000 },
+ { _MMIO(0x9888), 0x144c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x064cc000 },
+ { _MMIO(0x9888), 0x084cc000 },
+ { _MMIO(0x9888), 0x004ea000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084ea000 },
+ { _MMIO(0x9888), 0x0a4ea000 },
+ { _MMIO(0x9888), 0x0c4ea000 },
+ { _MMIO(0x9888), 0x0e4ea000 },
+ { _MMIO(0x9888), 0x024ea000 },
+ { _MMIO(0x9888), 0x044ea000 },
+ { _MMIO(0x9888), 0x0e4f4b41 },
+ { _MMIO(0x9888), 0x004f4200 },
+ { _MMIO(0x9888), 0x024f404c },
+ { _MMIO(0x9888), 0x1c4f0000 },
+ { _MMIO(0x9888), 0x1a4f0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0a1bc000 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x001c0031 },
+ { _MMIO(0x9888), 0x061c1900 },
+ { _MMIO(0x9888), 0x081c1a33 },
+ { _MMIO(0x9888), 0x0a1c1b35 },
+ { _MMIO(0x9888), 0x0c1c3337 },
+ { _MMIO(0x9888), 0x041c31c7 },
+ { _MMIO(0x9888), 0x180f5000 },
+ { _MMIO(0x9888), 0x1a0fa8aa },
+ { _MMIO(0x9888), 0x1c0f0aaa },
+ { _MMIO(0x9888), 0x182c8000 },
+ { _MMIO(0x9888), 0x1c2c6aaa },
+ { _MMIO(0x9888), 0x1e2c0001 },
+ { _MMIO(0x9888), 0x1a2c2950 },
+ { _MMIO(0x9888), 0x01938000 },
+ { _MMIO(0x9888), 0x0f938000 },
+ { _MMIO(0x9888), 0x1993aaaa },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25904000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29904000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900420 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900400 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x45900001 },
};
-int
-i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
+static const struct i915_oa_reg *
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
{
- int mux_len;
- int ret = 0;
+ *len = ARRAY_SIZE(mux_config_compute_extended);
+ return mux_config_compute_extended;
+}
- if (get_render_basic_mux_config(dev_priv, &mux_len)) {
- ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
- if (ret)
- goto error_render_basic;
- }
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
- return 0;
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c03b0 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f900c00 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x002d1000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x0c2e0400 },
+ { _MMIO(0x9888), 0x0e2e1500 },
+ { _MMIO(0x9888), 0x102e0140 },
+ { _MMIO(0x9888), 0x044c4000 },
+ { _MMIO(0x9888), 0x0a4c8000 },
+ { _MMIO(0x9888), 0x0c4cc000 },
+ { _MMIO(0x9888), 0x144c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x004e2000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084ea000 },
+ { _MMIO(0x9888), 0x0e4ea000 },
+ { _MMIO(0x9888), 0x1a4f4001 },
+ { _MMIO(0x9888), 0x1c4f5005 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x180f1000 },
+ { _MMIO(0x9888), 0x1a0fa800 },
+ { _MMIO(0x9888), 0x1c0f0a00 },
+ { _MMIO(0x9888), 0x182c4000 },
+ { _MMIO(0x9888), 0x1c2c4015 },
+ { _MMIO(0x9888), 0x1e2c0001 },
+ { _MMIO(0x9888), 0x03931980 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x01938000 },
+ { _MMIO(0x9888), 0x0f938000 },
+ { _MMIO(0x9888), 0x1993a00a },
+ { _MMIO(0x9888), 0x07930000 },
+ { _MMIO(0x9888), 0x09930000 },
+ { _MMIO(0x9888), 0x1d900177 },
+ { _MMIO(0x9888), 0x1f900178 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x53901000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x55900111 },
+ { _MMIO(0x9888), 0x47900001 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x4d900000 },
+ { _MMIO(0x9888), 0x45900400 },
+};
+
+static const struct i915_oa_reg *
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_l3_cache);
+ return mux_config_compute_l3_cache;
+}
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x022d4000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x0e2e0055 },
+ { _MMIO(0x9888), 0x064c8000 },
+ { _MMIO(0x9888), 0x084cc000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044ea000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x024f6100 },
+ { _MMIO(0x9888), 0x044f416b },
+ { _MMIO(0x9888), 0x064f004b },
+ { _MMIO(0x9888), 0x1a4f0000 },
+ { _MMIO(0x9888), 0x1a0f02a8 },
+ { _MMIO(0x9888), 0x1a2c5500 },
+ { _MMIO(0x9888), 0x0f808000 },
+ { _MMIO(0x9888), 0x25810020 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x1f951000 },
+ { _MMIO(0x9888), 0x13920200 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4d900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1_0_0_sku_gte_0x03[] = {
+ { _MMIO(0x9888), 0x12643400 },
+ { _MMIO(0x9888), 0x12653400 },
+ { _MMIO(0x9888), 0x106c6800 },
+ { _MMIO(0x9888), 0x126c001e },
+ { _MMIO(0x9888), 0x166c0010 },
+ { _MMIO(0x9888), 0x0c2d5000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x002d4000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x102e0154 },
+ { _MMIO(0x9888), 0x0c2e5000 },
+ { _MMIO(0x9888), 0x0e2e0055 },
+ { _MMIO(0x9888), 0x104c8000 },
+ { _MMIO(0x9888), 0x124c8000 },
+ { _MMIO(0x9888), 0x144c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x044c8000 },
+ { _MMIO(0x9888), 0x064cc000 },
+ { _MMIO(0x9888), 0x084cc000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x0c4ea000 },
+ { _MMIO(0x9888), 0x0e4ea000 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x024ea000 },
+ { _MMIO(0x9888), 0x044ea000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x1c4f5500 },
+ { _MMIO(0x9888), 0x1a4f1554 },
+ { _MMIO(0x9888), 0x0a640024 },
+ { _MMIO(0x9888), 0x10640000 },
+ { _MMIO(0x9888), 0x04640000 },
+ { _MMIO(0x9888), 0x0c650024 },
+ { _MMIO(0x9888), 0x10650000 },
+ { _MMIO(0x9888), 0x06650000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1a6c0900 },
+ { _MMIO(0x9888), 0x1c0f0aa0 },
+ { _MMIO(0x9888), 0x180f4000 },
+ { _MMIO(0x9888), 0x1a0f02aa },
+ { _MMIO(0x9888), 0x1c2c5400 },
+ { _MMIO(0x9888), 0x1e2c0001 },
+ { _MMIO(0x9888), 0x1a2c5550 },
+ { _MMIO(0x9888), 0x1993aa00 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900421 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900420 },
+ { _MMIO(0x9888), 0x45900021 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1_0_0_sku_lt_0x03[] = {
+ { _MMIO(0x9888), 0x14640340 },
+ { _MMIO(0x9888), 0x14650340 },
+ { _MMIO(0x9888), 0x106c6800 },
+ { _MMIO(0x9888), 0x126c001e },
+ { _MMIO(0x9888), 0x166c0010 },
+ { _MMIO(0x9888), 0x0c2d5000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x002d4000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x102e0154 },
+ { _MMIO(0x9888), 0x0c2e5000 },
+ { _MMIO(0x9888), 0x0e2e0055 },
+ { _MMIO(0x9888), 0x104c8000 },
+ { _MMIO(0x9888), 0x124c8000 },
+ { _MMIO(0x9888), 0x144c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x044c8000 },
+ { _MMIO(0x9888), 0x064cc000 },
+ { _MMIO(0x9888), 0x084cc000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x0c4ea000 },
+ { _MMIO(0x9888), 0x0e4ea000 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x024ea000 },
+ { _MMIO(0x9888), 0x044ea000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x1c4f5500 },
+ { _MMIO(0x9888), 0x1a4f1554 },
+ { _MMIO(0x9888), 0x04642400 },
+ { _MMIO(0x9888), 0x22640000 },
+ { _MMIO(0x9888), 0x1a640000 },
+ { _MMIO(0x9888), 0x06650024 },
+ { _MMIO(0x9888), 0x22650000 },
+ { _MMIO(0x9888), 0x1c650000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1a6c0900 },
+ { _MMIO(0x9888), 0x1c0f0aa0 },
+ { _MMIO(0x9888), 0x180f4000 },
+ { _MMIO(0x9888), 0x1a0f02aa },
+ { _MMIO(0x9888), 0x1c2c5400 },
+ { _MMIO(0x9888), 0x1e2c0001 },
+ { _MMIO(0x9888), 0x1a2c5550 },
+ { _MMIO(0x9888), 0x1993aa00 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900421 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900420 },
+ { _MMIO(0x9888), 0x45900021 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (dev_priv->drm.pdev->revision >= 0x03) {
+ *len = ARRAY_SIZE(mux_config_l3_1_0_0_sku_gte_0x03);
+ return mux_config_l3_1_0_0_sku_gte_0x03;
+ } else if (dev_priv->drm.pdev->revision < 0x03) {
+ *len = ARRAY_SIZE(mux_config_l3_1_0_0_sku_lt_0x03);
+ return mux_config_l3_1_0_0_sku_lt_0x03;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102d7800 },
+ { _MMIO(0x9888), 0x122d79e0 },
+ { _MMIO(0x9888), 0x0c2f0004 },
+ { _MMIO(0x9888), 0x100e3800 },
+ { _MMIO(0x9888), 0x180f0005 },
+ { _MMIO(0x9888), 0x002d0940 },
+ { _MMIO(0x9888), 0x022d802f },
+ { _MMIO(0x9888), 0x042d4013 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x0e2e0050 },
+ { _MMIO(0x9888), 0x022f0010 },
+ { _MMIO(0x9888), 0x002f0000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x040e0480 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x060f0027 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x1a0f0040 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x439014a0 },
+ { _MMIO(0x9888), 0x459000a4 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x121300a0 },
+ { _MMIO(0x9888), 0x141600ab },
+ { _MMIO(0x9888), 0x123300a0 },
+ { _MMIO(0x9888), 0x143600ab },
+ { _MMIO(0x9888), 0x125300a0 },
+ { _MMIO(0x9888), 0x145600ab },
+ { _MMIO(0x9888), 0x0c2d4000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x002d4000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x102e01a0 },
+ { _MMIO(0x9888), 0x0c2e5000 },
+ { _MMIO(0x9888), 0x0e2e0065 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x044c8000 },
+ { _MMIO(0x9888), 0x064cc000 },
+ { _MMIO(0x9888), 0x084c4000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x024ea000 },
+ { _MMIO(0x9888), 0x044e2000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x1c0f0800 },
+ { _MMIO(0x9888), 0x180f4000 },
+ { _MMIO(0x9888), 0x1a0f023f },
+ { _MMIO(0x9888), 0x1e2c0003 },
+ { _MMIO(0x9888), 0x1a2cc030 },
+ { _MMIO(0x9888), 0x04132180 },
+ { _MMIO(0x9888), 0x02130000 },
+ { _MMIO(0x9888), 0x0c148000 },
+ { _MMIO(0x9888), 0x0e142000 },
+ { _MMIO(0x9888), 0x04148000 },
+ { _MMIO(0x9888), 0x1e150140 },
+ { _MMIO(0x9888), 0x1c150040 },
+ { _MMIO(0x9888), 0x0c163000 },
+ { _MMIO(0x9888), 0x0e160068 },
+ { _MMIO(0x9888), 0x10160000 },
+ { _MMIO(0x9888), 0x18160000 },
+ { _MMIO(0x9888), 0x0a164000 },
+ { _MMIO(0x9888), 0x04330043 },
+ { _MMIO(0x9888), 0x02330000 },
+ { _MMIO(0x9888), 0x0234a000 },
+ { _MMIO(0x9888), 0x04342000 },
+ { _MMIO(0x9888), 0x1c350015 },
+ { _MMIO(0x9888), 0x02363460 },
+ { _MMIO(0x9888), 0x10360000 },
+ { _MMIO(0x9888), 0x04360000 },
+ { _MMIO(0x9888), 0x06360000 },
+ { _MMIO(0x9888), 0x08364000 },
+ { _MMIO(0x9888), 0x06530043 },
+ { _MMIO(0x9888), 0x02530000 },
+ { _MMIO(0x9888), 0x0e548000 },
+ { _MMIO(0x9888), 0x00548000 },
+ { _MMIO(0x9888), 0x06542000 },
+ { _MMIO(0x9888), 0x1e550400 },
+ { _MMIO(0x9888), 0x1a552000 },
+ { _MMIO(0x9888), 0x1c550100 },
+ { _MMIO(0x9888), 0x0e563000 },
+ { _MMIO(0x9888), 0x00563400 },
+ { _MMIO(0x9888), 0x10560000 },
+ { _MMIO(0x9888), 0x18560000 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x0c564000 },
+ { _MMIO(0x9888), 0x1993a800 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b9014a0 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900001 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900820 },
+ { _MMIO(0x9888), 0x45901022 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler);
+ return mux_config_sampler;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x141a0000 },
+ { _MMIO(0x9888), 0x143a0000 },
+ { _MMIO(0x9888), 0x145a0000 },
+ { _MMIO(0x9888), 0x0c2d4000 },
+ { _MMIO(0x9888), 0x0e2d5000 },
+ { _MMIO(0x9888), 0x002d4000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x102e0150 },
+ { _MMIO(0x9888), 0x0c2e5000 },
+ { _MMIO(0x9888), 0x0e2e006a },
+ { _MMIO(0x9888), 0x124c8000 },
+ { _MMIO(0x9888), 0x144c8000 },
+ { _MMIO(0x9888), 0x164c2000 },
+ { _MMIO(0x9888), 0x044c8000 },
+ { _MMIO(0x9888), 0x064c4000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x0e4ea000 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x024e2000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x1c0f0bc0 },
+ { _MMIO(0x9888), 0x180f4000 },
+ { _MMIO(0x9888), 0x1a0f0302 },
+ { _MMIO(0x9888), 0x1e2c0003 },
+ { _MMIO(0x9888), 0x1a2c00f0 },
+ { _MMIO(0x9888), 0x021a3080 },
+ { _MMIO(0x9888), 0x041a31e5 },
+ { _MMIO(0x9888), 0x02148000 },
+ { _MMIO(0x9888), 0x0414a000 },
+ { _MMIO(0x9888), 0x1c150054 },
+ { _MMIO(0x9888), 0x06168000 },
+ { _MMIO(0x9888), 0x08168000 },
+ { _MMIO(0x9888), 0x0a168000 },
+ { _MMIO(0x9888), 0x0c3a3280 },
+ { _MMIO(0x9888), 0x0e3a0063 },
+ { _MMIO(0x9888), 0x063a0061 },
+ { _MMIO(0x9888), 0x023a0000 },
+ { _MMIO(0x9888), 0x0c348000 },
+ { _MMIO(0x9888), 0x0e342000 },
+ { _MMIO(0x9888), 0x06342000 },
+ { _MMIO(0x9888), 0x1e350140 },
+ { _MMIO(0x9888), 0x1c350100 },
+ { _MMIO(0x9888), 0x18360028 },
+ { _MMIO(0x9888), 0x0c368000 },
+ { _MMIO(0x9888), 0x0e5a3080 },
+ { _MMIO(0x9888), 0x005a3280 },
+ { _MMIO(0x9888), 0x025a0063 },
+ { _MMIO(0x9888), 0x0e548000 },
+ { _MMIO(0x9888), 0x00548000 },
+ { _MMIO(0x9888), 0x02542000 },
+ { _MMIO(0x9888), 0x1e550400 },
+ { _MMIO(0x9888), 0x1a552000 },
+ { _MMIO(0x9888), 0x1c550001 },
+ { _MMIO(0x9888), 0x18560080 },
+ { _MMIO(0x9888), 0x02568000 },
+ { _MMIO(0x9888), 0x04568000 },
+ { _MMIO(0x9888), 0x1993a800 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x2d904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4d900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x45901084 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900001 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x141a026b },
+ { _MMIO(0x9888), 0x143a0173 },
+ { _MMIO(0x9888), 0x145a026b },
+ { _MMIO(0x9888), 0x002d4000 },
+ { _MMIO(0x9888), 0x022d5000 },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x0c2e5000 },
+ { _MMIO(0x9888), 0x0e2e0069 },
+ { _MMIO(0x9888), 0x044c8000 },
+ { _MMIO(0x9888), 0x064cc000 },
+ { _MMIO(0x9888), 0x0a4c4000 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x024ea000 },
+ { _MMIO(0x9888), 0x064e2000 },
+ { _MMIO(0x9888), 0x180f6000 },
+ { _MMIO(0x9888), 0x1a0f030a },
+ { _MMIO(0x9888), 0x1a2c03c0 },
+ { _MMIO(0x9888), 0x041a37e7 },
+ { _MMIO(0x9888), 0x021a0000 },
+ { _MMIO(0x9888), 0x0414a000 },
+ { _MMIO(0x9888), 0x1c150050 },
+ { _MMIO(0x9888), 0x08168000 },
+ { _MMIO(0x9888), 0x0a168000 },
+ { _MMIO(0x9888), 0x003a3380 },
+ { _MMIO(0x9888), 0x063a006f },
+ { _MMIO(0x9888), 0x023a0000 },
+ { _MMIO(0x9888), 0x00348000 },
+ { _MMIO(0x9888), 0x06342000 },
+ { _MMIO(0x9888), 0x1a352000 },
+ { _MMIO(0x9888), 0x1c350100 },
+ { _MMIO(0x9888), 0x02368000 },
+ { _MMIO(0x9888), 0x0c368000 },
+ { _MMIO(0x9888), 0x025a37e7 },
+ { _MMIO(0x9888), 0x0254a000 },
+ { _MMIO(0x9888), 0x1c550005 },
+ { _MMIO(0x9888), 0x04568000 },
+ { _MMIO(0x9888), 0x06568000 },
+ { _MMIO(0x9888), 0x03938000 },
+ { _MMIO(0x9888), 0x05938000 },
+ { _MMIO(0x9888), 0x07938000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17904000 },
+ { _MMIO(0x9888), 0x19904000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900020 },
+ { _MMIO(0x9888), 0x45901080 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+ { _MMIO(0xe458), 0x00001000 },
+ { _MMIO(0xe558), 0x00003002 },
+ { _MMIO(0xe658), 0x00005004 },
+ { _MMIO(0xe758), 0x00011010 },
+ { _MMIO(0xe45c), 0x00050012 },
+ { _MMIO(0xe55c), 0x00052051 },
+ { _MMIO(0xe65c), 0x00000008 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x141a001f },
+ { _MMIO(0x9888), 0x143a001f },
+ { _MMIO(0x9888), 0x145a001f },
+ { _MMIO(0x9888), 0x042d5000 },
+ { _MMIO(0x9888), 0x062d1000 },
+ { _MMIO(0x9888), 0x0e2e0094 },
+ { _MMIO(0x9888), 0x084cc000 },
+ { _MMIO(0x9888), 0x044ea000 },
+ { _MMIO(0x9888), 0x1a0f00e0 },
+ { _MMIO(0x9888), 0x1a2c0c00 },
+ { _MMIO(0x9888), 0x061a0063 },
+ { _MMIO(0x9888), 0x021a0000 },
+ { _MMIO(0x9888), 0x06142000 },
+ { _MMIO(0x9888), 0x1c150100 },
+ { _MMIO(0x9888), 0x0c168000 },
+ { _MMIO(0x9888), 0x043a3180 },
+ { _MMIO(0x9888), 0x023a0000 },
+ { _MMIO(0x9888), 0x04348000 },
+ { _MMIO(0x9888), 0x1c350040 },
+ { _MMIO(0x9888), 0x0a368000 },
+ { _MMIO(0x9888), 0x045a0063 },
+ { _MMIO(0x9888), 0x025a0000 },
+ { _MMIO(0x9888), 0x04542000 },
+ { _MMIO(0x9888), 0x1c550010 },
+ { _MMIO(0x9888), 0x08568000 },
+ { _MMIO(0x9888), 0x09938000 },
+ { _MMIO(0x9888), 0x0b938000 },
+ { _MMIO(0x9888), 0x0d938000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1d904000 },
+ { _MMIO(0x9888), 0x1f904000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900004 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extra);
+ return mux_config_compute_extra;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x19800000 },
+ { _MMIO(0x9888), 0x07800063 },
+ { _MMIO(0x9888), 0x11800000 },
+ { _MMIO(0x9888), 0x23810008 },
+ { _MMIO(0x9888), 0x1d950400 },
+ { _MMIO(0x9888), 0x0f922000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
+int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_reads_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_reads;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_reads);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_reads;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a",
+ .attrs = attrs_render_basic,
+};
+
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "012d72cf-82a9-4d25-8ddf-74076fd30797",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "ce416533-e49e-4211-80af-ec513590a914",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "398e2452-18d7-42d0-b241-e4d0a9148ada",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "00ad5a41-7eab-4f7a-9103-49d411c67219",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "8364e2a8-af63-40af-b0d5-42969a255654",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "d260f03f-b34d-4b49-a44e-436819117332",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "5ee72f5c-092f-421e-8b70-225f7c3e9612",
+ .attrs = attrs_test_oa,
+};
+
+int
+i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
+{
+ int mux_len;
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
+
+ return 0;
+
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -319,4 +2510,32 @@ i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c
index 3f06e0e1c3f2..f651e2ffc870 100644
--- a/drivers/gpu/drm/i915/i915_oa_chv.c
+++ b/drivers/gpu/drm/i915/i915_oa_chv.c
@@ -31,11 +31,25 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_L3_4,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER_1,
+ METRIC_SET_ID_SAMPLER_2,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_chv = 1;
+int i915_oa_n_builtin_metric_sets_chv = 14;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
@@ -55,15 +69,24 @@ static const struct i915_oa_reg flex_eu_config_render_basic[] = {
static const struct i915_oa_reg mux_config_render_basic[] = {
{ _MMIO(0x9888), 0x59800000 },
{ _MMIO(0x9888), 0x59800001 },
+ { _MMIO(0x9888), 0x285a0006 },
{ _MMIO(0x9888), 0x2c110014 },
{ _MMIO(0x9888), 0x2e110000 },
{ _MMIO(0x9888), 0x2c310014 },
{ _MMIO(0x9888), 0x2e310000 },
{ _MMIO(0x9888), 0x2b8303df },
- { _MMIO(0x9888), 0x358002c0 },
+ { _MMIO(0x9888), 0x3580024f },
{ _MMIO(0x9888), 0x00580888 },
+ { _MMIO(0x9888), 0x1e5a0015 },
+ { _MMIO(0x9888), 0x205a0014 },
+ { _MMIO(0x9888), 0x045a0000 },
+ { _MMIO(0x9888), 0x025a0000 },
+ { _MMIO(0x9888), 0x02180500 },
{ _MMIO(0x9888), 0x00190555 },
+ { _MMIO(0x9888), 0x021d0500 },
+ { _MMIO(0x9888), 0x021f0a00 },
{ _MMIO(0x9888), 0x00380444 },
+ { _MMIO(0x9888), 0x02390500 },
{ _MMIO(0x9888), 0x003a0666 },
{ _MMIO(0x9888), 0x00100111 },
{ _MMIO(0x9888), 0x06110030 },
@@ -79,67 +102,2119 @@ static const struct i915_oa_reg mux_config_render_basic[] = {
{ _MMIO(0x9888), 0x04310000 },
{ _MMIO(0x9888), 0x00310000 },
{ _MMIO(0x9888), 0x00330444 },
+ { _MMIO(0x9888), 0x038a0a00 },
{ _MMIO(0x9888), 0x018b0fff },
+ { _MMIO(0x9888), 0x038b0a00 },
{ _MMIO(0x9888), 0x01855000 },
- { _MMIO(0x9888), 0x03850555 },
+ { _MMIO(0x9888), 0x03850055 },
{ _MMIO(0x9888), 0x13830021 },
{ _MMIO(0x9888), 0x15830020 },
{ _MMIO(0x9888), 0x1783002f },
{ _MMIO(0x9888), 0x1983002e },
{ _MMIO(0x9888), 0x1b83002d },
{ _MMIO(0x9888), 0x1d83002c },
- { _MMIO(0x9888), 0x1f83002b },
- { _MMIO(0x9888), 0x2183002a },
{ _MMIO(0x9888), 0x05830000 },
{ _MMIO(0x9888), 0x01840555 },
- { _MMIO(0x9888), 0x23800071 },
- { _MMIO(0x9888), 0x25800072 },
+ { _MMIO(0x9888), 0x03840500 },
+ { _MMIO(0x9888), 0x23800074 },
+ { _MMIO(0x9888), 0x2580007d },
{ _MMIO(0x9888), 0x05800000 },
{ _MMIO(0x9888), 0x01805000 },
- { _MMIO(0x9888), 0x03800555 },
+ { _MMIO(0x9888), 0x03800055 },
{ _MMIO(0x9888), 0x01865000 },
- { _MMIO(0x9888), 0x03860555 },
+ { _MMIO(0x9888), 0x03860055 },
{ _MMIO(0x9888), 0x01875000 },
- { _MMIO(0x9888), 0x03870555 },
+ { _MMIO(0x9888), 0x03870055 },
{ _MMIO(0x9888), 0x418000aa },
{ _MMIO(0x9888), 0x4380000a },
{ _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x4780000a },
+ { _MMIO(0x9888), 0x49800000 },
+ { _MMIO(0x9888), 0x4b800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x55800000 },
+ { _MMIO(0x9888), 0x57800000 },
+ { _MMIO(0x9888), 0x59800000 },
+};
+
+static const struct i915_oa_reg *
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_basic);
+ return mux_config_render_basic;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x59800000 },
+ { _MMIO(0x9888), 0x59800001 },
+ { _MMIO(0x9888), 0x2e5800e0 },
+ { _MMIO(0x9888), 0x2e3800e0 },
+ { _MMIO(0x9888), 0x3580024f },
+ { _MMIO(0x9888), 0x3d800140 },
+ { _MMIO(0x9888), 0x08580042 },
+ { _MMIO(0x9888), 0x0c580040 },
+ { _MMIO(0x9888), 0x1058004c },
+ { _MMIO(0x9888), 0x1458004b },
+ { _MMIO(0x9888), 0x04580000 },
+ { _MMIO(0x9888), 0x00580000 },
+ { _MMIO(0x9888), 0x00195555 },
+ { _MMIO(0x9888), 0x06380042 },
+ { _MMIO(0x9888), 0x0a380040 },
+ { _MMIO(0x9888), 0x0e38004c },
+ { _MMIO(0x9888), 0x1238004b },
+ { _MMIO(0x9888), 0x04380000 },
+ { _MMIO(0x9888), 0x00384444 },
+ { _MMIO(0x9888), 0x003a5555 },
+ { _MMIO(0x9888), 0x018bffff },
+ { _MMIO(0x9888), 0x01845555 },
+ { _MMIO(0x9888), 0x17800074 },
+ { _MMIO(0x9888), 0x1980007d },
+ { _MMIO(0x9888), 0x1b80007c },
+ { _MMIO(0x9888), 0x1d8000b6 },
+ { _MMIO(0x9888), 0x1f8000b7 },
+ { _MMIO(0x9888), 0x05800000 },
+ { _MMIO(0x9888), 0x03800000 },
+ { _MMIO(0x9888), 0x418000aa },
+ { _MMIO(0x9888), 0x438000aa },
+ { _MMIO(0x9888), 0x45800000 },
{ _MMIO(0x9888), 0x47800000 },
- { _MMIO(0x9888), 0x498000c8 },
- { _MMIO(0x9888), 0x4b8000c8 },
- { _MMIO(0x9888), 0x4d8000c8 },
- { _MMIO(0x9888), 0x4f80014a },
- { _MMIO(0x9888), 0x5180014a },
- { _MMIO(0x9888), 0x5380014a },
- { _MMIO(0x9888), 0x5580014a },
- { _MMIO(0x9888), 0x578001ce },
+ { _MMIO(0x9888), 0x4980012a },
+ { _MMIO(0x9888), 0x4b80012a },
+ { _MMIO(0x9888), 0x4d80012a },
+ { _MMIO(0x9888), 0x4f80012a },
+ { _MMIO(0x9888), 0x518001ce },
+ { _MMIO(0x9888), 0x538001ce },
+ { _MMIO(0x9888), 0x5580000e },
+ { _MMIO(0x9888), 0x59800000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_basic);
+ return mux_config_compute_basic;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
{ _MMIO(0x9888), 0x59800000 },
+ { _MMIO(0x9888), 0x59800001 },
+ { _MMIO(0x9888), 0x261e0000 },
+ { _MMIO(0x9888), 0x281f000f },
+ { _MMIO(0x9888), 0x2817001a },
+ { _MMIO(0x9888), 0x2791001f },
+ { _MMIO(0x9888), 0x27880019 },
+ { _MMIO(0x9888), 0x2d890000 },
+ { _MMIO(0x9888), 0x278a0007 },
+ { _MMIO(0x9888), 0x298d001f },
+ { _MMIO(0x9888), 0x278e0020 },
+ { _MMIO(0x9888), 0x2b8f0012 },
+ { _MMIO(0x9888), 0x29900000 },
+ { _MMIO(0x9888), 0x00184000 },
+ { _MMIO(0x9888), 0x02181000 },
+ { _MMIO(0x9888), 0x02194000 },
+ { _MMIO(0x9888), 0x141e0002 },
+ { _MMIO(0x9888), 0x041e0000 },
+ { _MMIO(0x9888), 0x001e0000 },
+ { _MMIO(0x9888), 0x221f0015 },
+ { _MMIO(0x9888), 0x041f0000 },
+ { _MMIO(0x9888), 0x001f4000 },
+ { _MMIO(0x9888), 0x021f0000 },
+ { _MMIO(0x9888), 0x023a8000 },
+ { _MMIO(0x9888), 0x0213c000 },
+ { _MMIO(0x9888), 0x02164000 },
+ { _MMIO(0x9888), 0x24170012 },
+ { _MMIO(0x9888), 0x04170000 },
+ { _MMIO(0x9888), 0x07910005 },
+ { _MMIO(0x9888), 0x05910000 },
+ { _MMIO(0x9888), 0x01911500 },
+ { _MMIO(0x9888), 0x03910501 },
+ { _MMIO(0x9888), 0x0d880002 },
+ { _MMIO(0x9888), 0x1d880003 },
+ { _MMIO(0x9888), 0x05880000 },
+ { _MMIO(0x9888), 0x0b890032 },
+ { _MMIO(0x9888), 0x1b890031 },
+ { _MMIO(0x9888), 0x05890000 },
+ { _MMIO(0x9888), 0x01890040 },
+ { _MMIO(0x9888), 0x03890040 },
+ { _MMIO(0x9888), 0x098a0000 },
+ { _MMIO(0x9888), 0x198a0004 },
+ { _MMIO(0x9888), 0x058a0000 },
+ { _MMIO(0x9888), 0x018a8050 },
+ { _MMIO(0x9888), 0x038a2050 },
+ { _MMIO(0x9888), 0x018b95a9 },
+ { _MMIO(0x9888), 0x038be5a9 },
+ { _MMIO(0x9888), 0x018c1500 },
+ { _MMIO(0x9888), 0x038c0501 },
+ { _MMIO(0x9888), 0x178d0015 },
+ { _MMIO(0x9888), 0x058d0000 },
+ { _MMIO(0x9888), 0x138e0004 },
+ { _MMIO(0x9888), 0x218e000c },
+ { _MMIO(0x9888), 0x058e0000 },
+ { _MMIO(0x9888), 0x018e0500 },
+ { _MMIO(0x9888), 0x038e0101 },
+ { _MMIO(0x9888), 0x0f8f0027 },
+ { _MMIO(0x9888), 0x058f0000 },
+ { _MMIO(0x9888), 0x018f0000 },
+ { _MMIO(0x9888), 0x038f0001 },
+ { _MMIO(0x9888), 0x11900013 },
+ { _MMIO(0x9888), 0x1f900017 },
+ { _MMIO(0x9888), 0x05900000 },
+ { _MMIO(0x9888), 0x01900100 },
+ { _MMIO(0x9888), 0x03900001 },
+ { _MMIO(0x9888), 0x01845555 },
+ { _MMIO(0x9888), 0x03845555 },
+ { _MMIO(0x9888), 0x418000aa },
+ { _MMIO(0x9888), 0x438000aa },
+ { _MMIO(0x9888), 0x458000aa },
+ { _MMIO(0x9888), 0x478000aa },
+ { _MMIO(0x9888), 0x4980018c },
+ { _MMIO(0x9888), 0x4b80014b },
+ { _MMIO(0x9888), 0x4d800128 },
+ { _MMIO(0x9888), 0x4f80012a },
+ { _MMIO(0x9888), 0x51800187 },
+ { _MMIO(0x9888), 0x5380014b },
+ { _MMIO(0x9888), 0x55800149 },
+ { _MMIO(0x9888), 0x5780010a },
+ { _MMIO(0x9888), 0x59800000 },
+};
+
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile);
+ return mux_config_render_pipe_profile;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fff7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x105c0232 },
+ { _MMIO(0x9888), 0x10580232 },
+ { _MMIO(0x9888), 0x10380232 },
+ { _MMIO(0x9888), 0x10dc0232 },
+ { _MMIO(0x9888), 0x10d80232 },
+ { _MMIO(0x9888), 0x10b80232 },
+ { _MMIO(0x9888), 0x118e4400 },
+ { _MMIO(0x9888), 0x025c6080 },
+ { _MMIO(0x9888), 0x045c004b },
+ { _MMIO(0x9888), 0x005c8000 },
+ { _MMIO(0x9888), 0x00582080 },
+ { _MMIO(0x9888), 0x0258004b },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x04386080 },
+ { _MMIO(0x9888), 0x0638404b },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a380000 },
+ { _MMIO(0x9888), 0x0c380000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0cdc25c1 },
+ { _MMIO(0x9888), 0x0adcc000 },
+ { _MMIO(0x9888), 0x0ad825c1 },
+ { _MMIO(0x9888), 0x18db4000 },
+ { _MMIO(0x9888), 0x1adb0001 },
+ { _MMIO(0x9888), 0x0e9f8000 },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x0eb825c1 },
+ { _MMIO(0x9888), 0x18b80154 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x0d88c000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258baa05 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c5400 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x098dc000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x098e05c0 },
+ { _MMIO(0x9888), 0x058e0000 },
+ { _MMIO(0x9888), 0x198f0020 },
+ { _MMIO(0x9888), 0x2185aa0a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x19835000 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x19808000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x51800040 },
+ { _MMIO(0x9888), 0x43800400 },
+ { _MMIO(0x9888), 0x45800800 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800c62 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f801042 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x418014a4 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x10bf03da },
+ { _MMIO(0x9888), 0x14bf0001 },
+ { _MMIO(0x9888), 0x12980340 },
+ { _MMIO(0x9888), 0x12990340 },
+ { _MMIO(0x9888), 0x0cbf1187 },
+ { _MMIO(0x9888), 0x0ebf1205 },
+ { _MMIO(0x9888), 0x00bf0500 },
+ { _MMIO(0x9888), 0x02bf042b },
+ { _MMIO(0x9888), 0x04bf002c },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x00da8000 },
+ { _MMIO(0x9888), 0x02dac000 },
+ { _MMIO(0x9888), 0x04da4000 },
+ { _MMIO(0x9888), 0x04983400 },
+ { _MMIO(0x9888), 0x10980000 },
+ { _MMIO(0x9888), 0x06990034 },
+ { _MMIO(0x9888), 0x10990000 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x009d8000 },
+ { _MMIO(0x9888), 0x029dc000 },
+ { _MMIO(0x9888), 0x049d4000 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00ba },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x00b94000 },
+ { _MMIO(0x9888), 0x02b95000 },
+ { _MMIO(0x9888), 0x04b91000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0cba4000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x258b800a },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x47800000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800060 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_1);
+ return mux_config_l3_1;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x103f03da },
+ { _MMIO(0x9888), 0x143f0001 },
+ { _MMIO(0x9888), 0x12180340 },
+ { _MMIO(0x9888), 0x12190340 },
+ { _MMIO(0x9888), 0x0c3f1187 },
+ { _MMIO(0x9888), 0x0e3f1205 },
+ { _MMIO(0x9888), 0x003f0500 },
+ { _MMIO(0x9888), 0x023f042b },
+ { _MMIO(0x9888), 0x043f002c },
+ { _MMIO(0x9888), 0x0c5ac000 },
+ { _MMIO(0x9888), 0x0e5ac000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x04183400 },
+ { _MMIO(0x9888), 0x10180000 },
+ { _MMIO(0x9888), 0x06190034 },
+ { _MMIO(0x9888), 0x10190000 },
+ { _MMIO(0x9888), 0x0c1dc000 },
+ { _MMIO(0x9888), 0x0e1dc000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x101f02a8 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00ba },
+ { _MMIO(0x9888), 0x0c388000 },
+ { _MMIO(0x9888), 0x0c395000 },
+ { _MMIO(0x9888), 0x0e395000 },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04391000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x0c3a4000 },
+ { _MMIO(0x9888), 0x1b8aa800 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258b4005 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800000 },
+ { _MMIO(0x9888), 0x47800000 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800060 },
+};
+
+static const struct i915_oa_reg *
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_2);
+ return mux_config_l3_2;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x121b0340 },
+ { _MMIO(0x9888), 0x103f0274 },
+ { _MMIO(0x9888), 0x123f0000 },
+ { _MMIO(0x9888), 0x129b0340 },
+ { _MMIO(0x9888), 0x10bf0274 },
+ { _MMIO(0x9888), 0x12bf0000 },
+ { _MMIO(0x9888), 0x041b3400 },
+ { _MMIO(0x9888), 0x101b0000 },
+ { _MMIO(0x9888), 0x045c8000 },
+ { _MMIO(0x9888), 0x0a3d4000 },
+ { _MMIO(0x9888), 0x003f0080 },
+ { _MMIO(0x9888), 0x023f0793 },
+ { _MMIO(0x9888), 0x043f0014 },
+ { _MMIO(0x9888), 0x04588000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f002a },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04399000 },
+ { _MMIO(0x9888), 0x069b0034 },
+ { _MMIO(0x9888), 0x109b0000 },
+ { _MMIO(0x9888), 0x06dc4000 },
+ { _MMIO(0x9888), 0x0cbd4000 },
+ { _MMIO(0x9888), 0x0cbf0981 },
+ { _MMIO(0x9888), 0x0ebf0a0f },
+ { _MMIO(0x9888), 0x06d84000 },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x0cdb4000 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0e9f0080 },
+ { _MMIO(0x9888), 0x0cb84000 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x258b8009 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800c00 },
+ { _MMIO(0x9888), 0x47800c63 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f8014a5 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800045 },
+};
+
+static const struct i915_oa_reg *
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_3);
+ return mux_config_l3_3;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_4[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_4[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_4[] = {
+ { _MMIO(0x9888), 0x121a0340 },
+ { _MMIO(0x9888), 0x103f0017 },
+ { _MMIO(0x9888), 0x123f0020 },
+ { _MMIO(0x9888), 0x129a0340 },
+ { _MMIO(0x9888), 0x10bf0017 },
+ { _MMIO(0x9888), 0x12bf0020 },
+ { _MMIO(0x9888), 0x041a3400 },
+ { _MMIO(0x9888), 0x101a0000 },
+ { _MMIO(0x9888), 0x043b8000 },
+ { _MMIO(0x9888), 0x0a3e0010 },
+ { _MMIO(0x9888), 0x003f0200 },
+ { _MMIO(0x9888), 0x023f0113 },
+ { _MMIO(0x9888), 0x043f0014 },
+ { _MMIO(0x9888), 0x02592000 },
+ { _MMIO(0x9888), 0x005a8000 },
+ { _MMIO(0x9888), 0x025ac000 },
+ { _MMIO(0x9888), 0x045a4000 },
+ { _MMIO(0x9888), 0x0a1c8000 },
+ { _MMIO(0x9888), 0x001d8000 },
+ { _MMIO(0x9888), 0x021dc000 },
+ { _MMIO(0x9888), 0x041d4000 },
+ { _MMIO(0x9888), 0x0a1e8000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f001a },
+ { _MMIO(0x9888), 0x00394000 },
+ { _MMIO(0x9888), 0x02395000 },
+ { _MMIO(0x9888), 0x04391000 },
+ { _MMIO(0x9888), 0x069a0034 },
+ { _MMIO(0x9888), 0x109a0000 },
+ { _MMIO(0x9888), 0x06bb4000 },
+ { _MMIO(0x9888), 0x0abe0040 },
+ { _MMIO(0x9888), 0x0cbf0984 },
+ { _MMIO(0x9888), 0x0ebf0a02 },
+ { _MMIO(0x9888), 0x02d94000 },
+ { _MMIO(0x9888), 0x0cdac000 },
+ { _MMIO(0x9888), 0x0edac000 },
+ { _MMIO(0x9888), 0x0c9c0400 },
+ { _MMIO(0x9888), 0x0c9dc000 },
+ { _MMIO(0x9888), 0x0e9dc000 },
+ { _MMIO(0x9888), 0x0c9e0400 },
+ { _MMIO(0x9888), 0x109f02a8 },
+ { _MMIO(0x9888), 0x0e9f0040 },
+ { _MMIO(0x9888), 0x0cb95000 },
+ { _MMIO(0x9888), 0x0eb95000 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x258b8009 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x198c4000 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185800a },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x1b830154 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x45800800 },
+ { _MMIO(0x9888), 0x47800842 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f801084 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800044 },
+};
+
+static const struct i915_oa_reg *
+get_l3_4_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_4);
+ return mux_config_l3_4;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00006000 },
+ { _MMIO(0x2774), 0x0000f3ff },
+ { _MMIO(0x2778), 0x00001800 },
+ { _MMIO(0x277c), 0x0000fcff },
+ { _MMIO(0x2780), 0x00000600 },
+ { _MMIO(0x2784), 0x0000ff3f },
+ { _MMIO(0x2788), 0x00000180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000060 },
+ { _MMIO(0x2794), 0x0000fff3 },
+ { _MMIO(0x2798), 0x00000018 },
+ { _MMIO(0x279c), 0x0000fffc },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
};
-static const struct i915_oa_reg *
-get_render_basic_mux_config(struct drm_i915_private *dev_priv,
- int *len)
-{
- *len = ARRAY_SIZE(mux_config_render_basic);
- return mux_config_render_basic;
-}
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x143b000e },
+ { _MMIO(0x9888), 0x043c55c0 },
+ { _MMIO(0x9888), 0x0a1e0280 },
+ { _MMIO(0x9888), 0x0c1e0408 },
+ { _MMIO(0x9888), 0x10390000 },
+ { _MMIO(0x9888), 0x12397a1f },
+ { _MMIO(0x9888), 0x14bb000e },
+ { _MMIO(0x9888), 0x04bc5000 },
+ { _MMIO(0x9888), 0x0a9e0296 },
+ { _MMIO(0x9888), 0x0c9e0008 },
+ { _MMIO(0x9888), 0x10b90000 },
+ { _MMIO(0x9888), 0x12b97a1f },
+ { _MMIO(0x9888), 0x063b0042 },
+ { _MMIO(0x9888), 0x103b0000 },
+ { _MMIO(0x9888), 0x083c0000 },
+ { _MMIO(0x9888), 0x0a3e0040 },
+ { _MMIO(0x9888), 0x043f8000 },
+ { _MMIO(0x9888), 0x02594000 },
+ { _MMIO(0x9888), 0x045a8000 },
+ { _MMIO(0x9888), 0x0c1c0400 },
+ { _MMIO(0x9888), 0x041d8000 },
+ { _MMIO(0x9888), 0x081e02c0 },
+ { _MMIO(0x9888), 0x0e1e0000 },
+ { _MMIO(0x9888), 0x0c1fa800 },
+ { _MMIO(0x9888), 0x0e1f0260 },
+ { _MMIO(0x9888), 0x101f0014 },
+ { _MMIO(0x9888), 0x003905e0 },
+ { _MMIO(0x9888), 0x06390bc0 },
+ { _MMIO(0x9888), 0x02390018 },
+ { _MMIO(0x9888), 0x04394000 },
+ { _MMIO(0x9888), 0x04bb0042 },
+ { _MMIO(0x9888), 0x10bb0000 },
+ { _MMIO(0x9888), 0x02bc05c0 },
+ { _MMIO(0x9888), 0x08bc0000 },
+ { _MMIO(0x9888), 0x0abe0004 },
+ { _MMIO(0x9888), 0x02bf8000 },
+ { _MMIO(0x9888), 0x02d91000 },
+ { _MMIO(0x9888), 0x02da8000 },
+ { _MMIO(0x9888), 0x089c8000 },
+ { _MMIO(0x9888), 0x029d8000 },
+ { _MMIO(0x9888), 0x089e8000 },
+ { _MMIO(0x9888), 0x0e9e0000 },
+ { _MMIO(0x9888), 0x0e9fa806 },
+ { _MMIO(0x9888), 0x109f0142 },
+ { _MMIO(0x9888), 0x08b90617 },
+ { _MMIO(0x9888), 0x0ab90be0 },
+ { _MMIO(0x9888), 0x02b94000 },
+ { _MMIO(0x9888), 0x0d88f000 },
+ { _MMIO(0x9888), 0x0f88000c },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x018a8000 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x1b8a2800 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x238b52a0 },
+ { _MMIO(0x9888), 0x258b6a95 },
+ { _MMIO(0x9888), 0x278b0029 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c1500 },
+ { _MMIO(0x9888), 0x1b8c0014 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x038d8000 },
+ { _MMIO(0x9888), 0x058d2000 },
+ { _MMIO(0x9888), 0x1f85aa80 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x01834000 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0184c000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1180c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4d800444 },
+ { _MMIO(0x9888), 0x3d800000 },
+ { _MMIO(0x9888), 0x4f804000 },
+ { _MMIO(0x9888), 0x43801080 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800084 },
+ { _MMIO(0x9888), 0x53800044 },
+ { _MMIO(0x9888), 0x47801080 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x3f800000 },
+ { _MMIO(0x9888), 0x41800840 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler_1[] = {
+ { _MMIO(0x9888), 0x18921400 },
+ { _MMIO(0x9888), 0x149500ab },
+ { _MMIO(0x9888), 0x18b21400 },
+ { _MMIO(0x9888), 0x14b500ab },
+ { _MMIO(0x9888), 0x18d21400 },
+ { _MMIO(0x9888), 0x14d500ab },
+ { _MMIO(0x9888), 0x0cdc8000 },
+ { _MMIO(0x9888), 0x0edc4000 },
+ { _MMIO(0x9888), 0x02dcc000 },
+ { _MMIO(0x9888), 0x04dcc000 },
+ { _MMIO(0x9888), 0x1abd00a0 },
+ { _MMIO(0x9888), 0x0abd8000 },
+ { _MMIO(0x9888), 0x0cd88000 },
+ { _MMIO(0x9888), 0x0ed84000 },
+ { _MMIO(0x9888), 0x04d88000 },
+ { _MMIO(0x9888), 0x1adb0050 },
+ { _MMIO(0x9888), 0x04db8000 },
+ { _MMIO(0x9888), 0x06db8000 },
+ { _MMIO(0x9888), 0x08db8000 },
+ { _MMIO(0x9888), 0x0adb4000 },
+ { _MMIO(0x9888), 0x109f02a0 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00aa },
+ { _MMIO(0x9888), 0x18b82500 },
+ { _MMIO(0x9888), 0x02b88000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab84000 },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x0cb98000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x00b98000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x1aba0200 },
+ { _MMIO(0x9888), 0x02ba8000 },
+ { _MMIO(0x9888), 0x0cba8000 },
+ { _MMIO(0x9888), 0x04908000 },
+ { _MMIO(0x9888), 0x04918000 },
+ { _MMIO(0x9888), 0x04927300 },
+ { _MMIO(0x9888), 0x10920000 },
+ { _MMIO(0x9888), 0x1893000a },
+ { _MMIO(0x9888), 0x0a934000 },
+ { _MMIO(0x9888), 0x0a946000 },
+ { _MMIO(0x9888), 0x0c959000 },
+ { _MMIO(0x9888), 0x0e950098 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x04b04000 },
+ { _MMIO(0x9888), 0x04b14000 },
+ { _MMIO(0x9888), 0x04b20073 },
+ { _MMIO(0x9888), 0x10b20000 },
+ { _MMIO(0x9888), 0x04b38000 },
+ { _MMIO(0x9888), 0x06b38000 },
+ { _MMIO(0x9888), 0x08b34000 },
+ { _MMIO(0x9888), 0x04b4c000 },
+ { _MMIO(0x9888), 0x02b59890 },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x06d04000 },
+ { _MMIO(0x9888), 0x06d14000 },
+ { _MMIO(0x9888), 0x06d20073 },
+ { _MMIO(0x9888), 0x10d20000 },
+ { _MMIO(0x9888), 0x18d30020 },
+ { _MMIO(0x9888), 0x02d38000 },
+ { _MMIO(0x9888), 0x0cd34000 },
+ { _MMIO(0x9888), 0x0ad48000 },
+ { _MMIO(0x9888), 0x04d42000 },
+ { _MMIO(0x9888), 0x0ed59000 },
+ { _MMIO(0x9888), 0x00d59800 },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x0f88000e },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x258b000a },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x0d8d8000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x2185000a },
+ { _MMIO(0x9888), 0x1b830150 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d848000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d808000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801021 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800c64 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800c02 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler_1);
+ return mux_config_sampler_1;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler_2[] = {
+ { _MMIO(0x9888), 0x18121400 },
+ { _MMIO(0x9888), 0x141500ab },
+ { _MMIO(0x9888), 0x18321400 },
+ { _MMIO(0x9888), 0x143500ab },
+ { _MMIO(0x9888), 0x18521400 },
+ { _MMIO(0x9888), 0x145500ab },
+ { _MMIO(0x9888), 0x0c5c8000 },
+ { _MMIO(0x9888), 0x0e5c4000 },
+ { _MMIO(0x9888), 0x025cc000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x1a3d00a0 },
+ { _MMIO(0x9888), 0x0a3d8000 },
+ { _MMIO(0x9888), 0x0c588000 },
+ { _MMIO(0x9888), 0x0e584000 },
+ { _MMIO(0x9888), 0x04588000 },
+ { _MMIO(0x9888), 0x1a5b0050 },
+ { _MMIO(0x9888), 0x045b8000 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b8000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x101f02a0 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x18382500 },
+ { _MMIO(0x9888), 0x02388000 },
+ { _MMIO(0x9888), 0x04384000 },
+ { _MMIO(0x9888), 0x06384000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c388000 },
+ { _MMIO(0x9888), 0x0c398000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x1a3a0200 },
+ { _MMIO(0x9888), 0x023a8000 },
+ { _MMIO(0x9888), 0x0c3a8000 },
+ { _MMIO(0x9888), 0x04108000 },
+ { _MMIO(0x9888), 0x04118000 },
+ { _MMIO(0x9888), 0x04127300 },
+ { _MMIO(0x9888), 0x10120000 },
+ { _MMIO(0x9888), 0x1813000a },
+ { _MMIO(0x9888), 0x0a134000 },
+ { _MMIO(0x9888), 0x0a146000 },
+ { _MMIO(0x9888), 0x0c159000 },
+ { _MMIO(0x9888), 0x0e150098 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04304000 },
+ { _MMIO(0x9888), 0x04314000 },
+ { _MMIO(0x9888), 0x04320073 },
+ { _MMIO(0x9888), 0x10320000 },
+ { _MMIO(0x9888), 0x04338000 },
+ { _MMIO(0x9888), 0x06338000 },
+ { _MMIO(0x9888), 0x08334000 },
+ { _MMIO(0x9888), 0x0434c000 },
+ { _MMIO(0x9888), 0x02359890 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x06504000 },
+ { _MMIO(0x9888), 0x06514000 },
+ { _MMIO(0x9888), 0x06520073 },
+ { _MMIO(0x9888), 0x10520000 },
+ { _MMIO(0x9888), 0x18530020 },
+ { _MMIO(0x9888), 0x02538000 },
+ { _MMIO(0x9888), 0x0c534000 },
+ { _MMIO(0x9888), 0x0a548000 },
+ { _MMIO(0x9888), 0x04542000 },
+ { _MMIO(0x9888), 0x0e559000 },
+ { _MMIO(0x9888), 0x00559800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x1b8aa000 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x258b0005 },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x2185000a },
+ { _MMIO(0x9888), 0x1b830150 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0d848000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x07844000 },
+ { _MMIO(0x9888), 0x1d808000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x17804000 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47801021 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800c64 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x41800c02 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler_2);
+ return mux_config_sampler_2;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x0000fe7f },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000ffbf },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fff7 },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fff9 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x16154d60 },
+ { _MMIO(0x9888), 0x16352e60 },
+ { _MMIO(0x9888), 0x16554d60 },
+ { _MMIO(0x9888), 0x16950000 },
+ { _MMIO(0x9888), 0x16b50000 },
+ { _MMIO(0x9888), 0x16d50000 },
+ { _MMIO(0x9888), 0x005c8000 },
+ { _MMIO(0x9888), 0x045cc000 },
+ { _MMIO(0x9888), 0x065c4000 },
+ { _MMIO(0x9888), 0x083d8000 },
+ { _MMIO(0x9888), 0x0a3d8000 },
+ { _MMIO(0x9888), 0x0458c000 },
+ { _MMIO(0x9888), 0x025b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0c1fa000 },
+ { _MMIO(0x9888), 0x0e1f00aa },
+ { _MMIO(0x9888), 0x02384000 },
+ { _MMIO(0x9888), 0x04388000 },
+ { _MMIO(0x9888), 0x06388000 },
+ { _MMIO(0x9888), 0x08384000 },
+ { _MMIO(0x9888), 0x0a384000 },
+ { _MMIO(0x9888), 0x0c384000 },
+ { _MMIO(0x9888), 0x00398000 },
+ { _MMIO(0x9888), 0x0239a000 },
+ { _MMIO(0x9888), 0x0439a000 },
+ { _MMIO(0x9888), 0x06392000 },
+ { _MMIO(0x9888), 0x043a8000 },
+ { _MMIO(0x9888), 0x063a8000 },
+ { _MMIO(0x9888), 0x08138000 },
+ { _MMIO(0x9888), 0x0a138000 },
+ { _MMIO(0x9888), 0x06143000 },
+ { _MMIO(0x9888), 0x0415cfc7 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x02338000 },
+ { _MMIO(0x9888), 0x0c338000 },
+ { _MMIO(0x9888), 0x04342000 },
+ { _MMIO(0x9888), 0x06344000 },
+ { _MMIO(0x9888), 0x0035c700 },
+ { _MMIO(0x9888), 0x063500cf },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04538000 },
+ { _MMIO(0x9888), 0x06538000 },
+ { _MMIO(0x9888), 0x0454c000 },
+ { _MMIO(0x9888), 0x0255cfc7 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06dc8000 },
+ { _MMIO(0x9888), 0x08dc4000 },
+ { _MMIO(0x9888), 0x0cdcc000 },
+ { _MMIO(0x9888), 0x0edcc000 },
+ { _MMIO(0x9888), 0x1abd00a8 },
+ { _MMIO(0x9888), 0x0cd8c000 },
+ { _MMIO(0x9888), 0x0ed84000 },
+ { _MMIO(0x9888), 0x0edb8000 },
+ { _MMIO(0x9888), 0x18db0800 },
+ { _MMIO(0x9888), 0x1adb0254 },
+ { _MMIO(0x9888), 0x0e9faa00 },
+ { _MMIO(0x9888), 0x109f02aa },
+ { _MMIO(0x9888), 0x0eb84000 },
+ { _MMIO(0x9888), 0x16b84000 },
+ { _MMIO(0x9888), 0x18b8156a },
+ { _MMIO(0x9888), 0x06b98000 },
+ { _MMIO(0x9888), 0x08b9a000 },
+ { _MMIO(0x9888), 0x0ab9a000 },
+ { _MMIO(0x9888), 0x0cb9a000 },
+ { _MMIO(0x9888), 0x0eb9a000 },
+ { _MMIO(0x9888), 0x18baa000 },
+ { _MMIO(0x9888), 0x1aba0002 },
+ { _MMIO(0x9888), 0x16934000 },
+ { _MMIO(0x9888), 0x1893000a },
+ { _MMIO(0x9888), 0x0a947000 },
+ { _MMIO(0x9888), 0x0c95c5c1 },
+ { _MMIO(0x9888), 0x0e9500c3 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x0eb38000 },
+ { _MMIO(0x9888), 0x16b30040 },
+ { _MMIO(0x9888), 0x18b30020 },
+ { _MMIO(0x9888), 0x06b48000 },
+ { _MMIO(0x9888), 0x08b41000 },
+ { _MMIO(0x9888), 0x0ab48000 },
+ { _MMIO(0x9888), 0x06b5c500 },
+ { _MMIO(0x9888), 0x08b500c3 },
+ { _MMIO(0x9888), 0x0eb5c100 },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x16d31500 },
+ { _MMIO(0x9888), 0x08d4e000 },
+ { _MMIO(0x9888), 0x08d5c100 },
+ { _MMIO(0x9888), 0x0ad5c3c5 },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x0d88f800 },
+ { _MMIO(0x9888), 0x0f88000f },
+ { _MMIO(0x9888), 0x038a8000 },
+ { _MMIO(0x9888), 0x058a8000 },
+ { _MMIO(0x9888), 0x078a8000 },
+ { _MMIO(0x9888), 0x098a8000 },
+ { _MMIO(0x9888), 0x0b8a8000 },
+ { _MMIO(0x9888), 0x0d8a8000 },
+ { _MMIO(0x9888), 0x258baaa5 },
+ { _MMIO(0x9888), 0x278b002a },
+ { _MMIO(0x9888), 0x238b2a80 },
+ { _MMIO(0x9888), 0x0f8c4000 },
+ { _MMIO(0x9888), 0x178c2000 },
+ { _MMIO(0x9888), 0x198c5500 },
+ { _MMIO(0x9888), 0x1b8c0015 },
+ { _MMIO(0x9888), 0x078d8000 },
+ { _MMIO(0x9888), 0x098da000 },
+ { _MMIO(0x9888), 0x0b8da000 },
+ { _MMIO(0x9888), 0x0d8da000 },
+ { _MMIO(0x9888), 0x0f8da000 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800c42 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45800063 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x47800800 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f8014a4 },
+ { _MMIO(0x9888), 0x41801042 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x0000fe7f },
+ { _MMIO(0x2780), 0x00000000 },
+ { _MMIO(0x2784), 0x0000ff9f },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000ffe7 },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fffb },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000fffd },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x16150000 },
+ { _MMIO(0x9888), 0x16350000 },
+ { _MMIO(0x9888), 0x16550000 },
+ { _MMIO(0x9888), 0x16952e60 },
+ { _MMIO(0x9888), 0x16b54d60 },
+ { _MMIO(0x9888), 0x16d52e60 },
+ { _MMIO(0x9888), 0x065c8000 },
+ { _MMIO(0x9888), 0x085cc000 },
+ { _MMIO(0x9888), 0x0a5cc000 },
+ { _MMIO(0x9888), 0x0c5c4000 },
+ { _MMIO(0x9888), 0x0e3d8000 },
+ { _MMIO(0x9888), 0x183da000 },
+ { _MMIO(0x9888), 0x06588000 },
+ { _MMIO(0x9888), 0x08588000 },
+ { _MMIO(0x9888), 0x0a584000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x185b5800 },
+ { _MMIO(0x9888), 0x1a5b000a },
+ { _MMIO(0x9888), 0x0e1faa00 },
+ { _MMIO(0x9888), 0x101f02aa },
+ { _MMIO(0x9888), 0x0e384000 },
+ { _MMIO(0x9888), 0x16384000 },
+ { _MMIO(0x9888), 0x18382a55 },
+ { _MMIO(0x9888), 0x06398000 },
+ { _MMIO(0x9888), 0x0839a000 },
+ { _MMIO(0x9888), 0x0a39a000 },
+ { _MMIO(0x9888), 0x0c39a000 },
+ { _MMIO(0x9888), 0x0e39a000 },
+ { _MMIO(0x9888), 0x1a3a02a0 },
+ { _MMIO(0x9888), 0x0e138000 },
+ { _MMIO(0x9888), 0x16130500 },
+ { _MMIO(0x9888), 0x06148000 },
+ { _MMIO(0x9888), 0x08146000 },
+ { _MMIO(0x9888), 0x0615c100 },
+ { _MMIO(0x9888), 0x0815c500 },
+ { _MMIO(0x9888), 0x0a1500c3 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x16335040 },
+ { _MMIO(0x9888), 0x08349000 },
+ { _MMIO(0x9888), 0x0a341000 },
+ { _MMIO(0x9888), 0x083500c1 },
+ { _MMIO(0x9888), 0x0a35c500 },
+ { _MMIO(0x9888), 0x0c3500c3 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x1853002a },
+ { _MMIO(0x9888), 0x0a54e000 },
+ { _MMIO(0x9888), 0x0c55c500 },
+ { _MMIO(0x9888), 0x0e55c1c3 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x00dc8000 },
+ { _MMIO(0x9888), 0x02dcc000 },
+ { _MMIO(0x9888), 0x04dc4000 },
+ { _MMIO(0x9888), 0x04bd8000 },
+ { _MMIO(0x9888), 0x06bd8000 },
+ { _MMIO(0x9888), 0x02d8c000 },
+ { _MMIO(0x9888), 0x02db8000 },
+ { _MMIO(0x9888), 0x04db4000 },
+ { _MMIO(0x9888), 0x06db4000 },
+ { _MMIO(0x9888), 0x08db8000 },
+ { _MMIO(0x9888), 0x0c9fa000 },
+ { _MMIO(0x9888), 0x0e9f00aa },
+ { _MMIO(0x9888), 0x02b84000 },
+ { _MMIO(0x9888), 0x04b84000 },
+ { _MMIO(0x9888), 0x06b84000 },
+ { _MMIO(0x9888), 0x08b84000 },
+ { _MMIO(0x9888), 0x0ab88000 },
+ { _MMIO(0x9888), 0x0cb88000 },
+ { _MMIO(0x9888), 0x00b98000 },
+ { _MMIO(0x9888), 0x02b9a000 },
+ { _MMIO(0x9888), 0x04b9a000 },
+ { _MMIO(0x9888), 0x06b92000 },
+ { _MMIO(0x9888), 0x0aba8000 },
+ { _MMIO(0x9888), 0x0cba8000 },
+ { _MMIO(0x9888), 0x04938000 },
+ { _MMIO(0x9888), 0x06938000 },
+ { _MMIO(0x9888), 0x0494c000 },
+ { _MMIO(0x9888), 0x0295cfc7 },
+ { _MMIO(0x9888), 0x10950000 },
+ { _MMIO(0x9888), 0x02b38000 },
+ { _MMIO(0x9888), 0x08b38000 },
+ { _MMIO(0x9888), 0x04b42000 },
+ { _MMIO(0x9888), 0x06b41000 },
+ { _MMIO(0x9888), 0x00b5c700 },
+ { _MMIO(0x9888), 0x04b500cf },
+ { _MMIO(0x9888), 0x10b50000 },
+ { _MMIO(0x9888), 0x0ad38000 },
+ { _MMIO(0x9888), 0x0cd38000 },
+ { _MMIO(0x9888), 0x06d46000 },
+ { _MMIO(0x9888), 0x04d5c700 },
+ { _MMIO(0x9888), 0x06d500cf },
+ { _MMIO(0x9888), 0x10d50000 },
+ { _MMIO(0x9888), 0x03888000 },
+ { _MMIO(0x9888), 0x05888000 },
+ { _MMIO(0x9888), 0x07888000 },
+ { _MMIO(0x9888), 0x09888000 },
+ { _MMIO(0x9888), 0x0b888000 },
+ { _MMIO(0x9888), 0x0d880400 },
+ { _MMIO(0x9888), 0x0f8a8000 },
+ { _MMIO(0x9888), 0x198a8000 },
+ { _MMIO(0x9888), 0x1b8aaaa0 },
+ { _MMIO(0x9888), 0x1d8a0002 },
+ { _MMIO(0x9888), 0x258b555a },
+ { _MMIO(0x9888), 0x278b0015 },
+ { _MMIO(0x9888), 0x238b5500 },
+ { _MMIO(0x9888), 0x038c4000 },
+ { _MMIO(0x9888), 0x058c4000 },
+ { _MMIO(0x9888), 0x078c4000 },
+ { _MMIO(0x9888), 0x098c4000 },
+ { _MMIO(0x9888), 0x0b8c4000 },
+ { _MMIO(0x9888), 0x0d8c4000 },
+ { _MMIO(0x9888), 0x018d8000 },
+ { _MMIO(0x9888), 0x038da000 },
+ { _MMIO(0x9888), 0x058da000 },
+ { _MMIO(0x9888), 0x078d2000 },
+ { _MMIO(0x9888), 0x2185aaaa },
+ { _MMIO(0x9888), 0x2385002a },
+ { _MMIO(0x9888), 0x1f85aa00 },
+ { _MMIO(0x9888), 0x0f834000 },
+ { _MMIO(0x9888), 0x19835400 },
+ { _MMIO(0x9888), 0x1b830155 },
+ { _MMIO(0x9888), 0x03834000 },
+ { _MMIO(0x9888), 0x05834000 },
+ { _MMIO(0x9888), 0x07834000 },
+ { _MMIO(0x9888), 0x09834000 },
+ { _MMIO(0x9888), 0x0b834000 },
+ { _MMIO(0x9888), 0x0d834000 },
+ { _MMIO(0x9888), 0x0784c000 },
+ { _MMIO(0x9888), 0x0984c000 },
+ { _MMIO(0x9888), 0x0b84c000 },
+ { _MMIO(0x9888), 0x0d84c000 },
+ { _MMIO(0x9888), 0x0f84c000 },
+ { _MMIO(0x9888), 0x01848000 },
+ { _MMIO(0x9888), 0x0384c000 },
+ { _MMIO(0x9888), 0x0584c000 },
+ { _MMIO(0x9888), 0x1780c000 },
+ { _MMIO(0x9888), 0x1980c000 },
+ { _MMIO(0x9888), 0x1b80c000 },
+ { _MMIO(0x9888), 0x1d80c000 },
+ { _MMIO(0x9888), 0x1f80c000 },
+ { _MMIO(0x9888), 0x11808000 },
+ { _MMIO(0x9888), 0x1380c000 },
+ { _MMIO(0x9888), 0x1580c000 },
+ { _MMIO(0x9888), 0x4f800000 },
+ { _MMIO(0x9888), 0x43800882 },
+ { _MMIO(0x9888), 0x51800000 },
+ { _MMIO(0x9888), 0x45801082 },
+ { _MMIO(0x9888), 0x53800000 },
+ { _MMIO(0x9888), 0x478014a5 },
+ { _MMIO(0x9888), 0x21800000 },
+ { _MMIO(0x9888), 0x31800000 },
+ { _MMIO(0x9888), 0x4d800000 },
+ { _MMIO(0x9888), 0x3f800002 },
+ { _MMIO(0x9888), 0x41800c62 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x59800000 },
+ { _MMIO(0x9888), 0x59800001 },
+ { _MMIO(0x9888), 0x338b0000 },
+ { _MMIO(0x9888), 0x258b0066 },
+ { _MMIO(0x9888), 0x058b0000 },
+ { _MMIO(0x9888), 0x038b0000 },
+ { _MMIO(0x9888), 0x03844000 },
+ { _MMIO(0x9888), 0x47800080 },
+ { _MMIO(0x9888), 0x57800000 },
+ { _MMIO(0x1823a4), 0x00000000 },
+ { _MMIO(0x9888), 0x59800000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
+int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.mux_regs = NULL;
+ dev_priv->perf.oa.mux_regs_len = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_L3_4:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_4_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_4;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_4);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_4;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_4);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER_1:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler_1);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER_2:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler_2);
-int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
-{
- dev_priv->perf.oa.mux_regs = NULL;
- dev_priv->perf.oa.mux_regs_len = 0;
- dev_priv->perf.oa.b_counter_regs = NULL;
- dev_priv->perf.oa.b_counter_regs_len = 0;
- dev_priv->perf.oa.flex_regs = NULL;
- dev_priv->perf.oa.flex_regs_len = 0;
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
- &dev_priv->perf.oa.mux_regs_len);
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised so userspace and
@@ -149,14 +2224,39 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
}
dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
+ b_counter_config_tdl_2;
dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+ ARRAY_SIZE(b_counter_config_tdl_2);
dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
+ flex_eu_config_tdl_2;
dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
@@ -186,6 +2286,292 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic,
};
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "f522a89c-ecd1-4522-8331-3383c54af5f5",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
+}
+
+static struct device_attribute dev_attr_l3_4_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_4_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_4[] = {
+ &dev_attr_l3_4_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_4 = {
+ .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
+ .attrs = attrs_l3_4,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
+}
+
+static struct device_attribute dev_attr_sampler_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler_1[] = {
+ &dev_attr_sampler_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler_1 = {
+ .name = "71148d78-baf5-474f-878a-e23158d0265d",
+ .attrs = attrs_sampler_1,
+};
+
+static ssize_t
+show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
+}
+
+static struct device_attribute dev_attr_sampler_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler_2[] = {
+ &dev_attr_sampler_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler_2 = {
+ .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
+ .attrs = attrs_sampler_2,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "4a534b07-cba3-414d-8d60-874830e883aa",
+ .attrs = attrs_test_oa,
+};
+
int
i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
{
@@ -197,9 +2583,113 @@ i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
if (ret)
goto error_render_basic;
}
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_l3_4_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+ if (ret)
+ goto error_l3_4;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+ if (ret)
+ goto error_sampler_1;
+ }
+ if (get_sampler_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+ if (ret)
+ goto error_sampler_2;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
return 0;
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+error_sampler_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+error_sampler_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+error_l3_4:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -211,4 +2701,30 @@ i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_l3_4_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
+ if (get_sampler_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
index e50842f2b939..bc3a8b259b3f 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c
@@ -31,9 +31,26 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_sklgt2 = 1;
+int i915_oa_n_builtin_metric_sets_sklgt2 = 18;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
@@ -138,6 +155,2095 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return NULL;
}
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901403 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8200 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x004f0db2 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f1880 },
+ { _MMIO(0x9888), 0x0a4f0011 },
+ { _MMIO(0x9888), 0x0c4f0e3c },
+ { _MMIO(0x9888), 0x0e4f1d80 },
+ { _MMIO(0x9888), 0x086c0002 },
+ { _MMIO(0x9888), 0x0a6c0100 },
+ { _MMIO(0x9888), 0x0e6c000c },
+ { _MMIO(0x9888), 0x026c000b },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x081b4000 },
+ { _MMIO(0x9888), 0x0a1b8000 },
+ { _MMIO(0x9888), 0x0e1b4000 },
+ { _MMIO(0x9888), 0x021b4000 },
+ { _MMIO(0x9888), 0x1a1c4000 },
+ { _MMIO(0x9888), 0x1c1c0012 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x005bc000 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b8000 },
+ { _MMIO(0x9888), 0x0a5b4000 },
+ { _MMIO(0x9888), 0x0c5bc000 },
+ { _MMIO(0x9888), 0x0e5b8000 },
+ { _MMIO(0x9888), 0x105c8000 },
+ { _MMIO(0x9888), 0x1a5ca000 },
+ { _MMIO(0x9888), 0x1c5c002d },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x0a4c0800 },
+ { _MMIO(0x9888), 0x0c4c0082 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002cc000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cbe00 },
+ { _MMIO(0x9888), 0x182c00ef },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900167 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0xd28), 0x00000000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900840 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900842 },
+ { _MMIO(0x9888), 0x47900840 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900840 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900040 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900840 },
+ { _MMIO(0x9888), 0x53901111 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901403 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x1a4e0820 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f0032 },
+ { _MMIO(0x9888), 0x0a4f1810 },
+ { _MMIO(0x9888), 0x0c4f0e00 },
+ { _MMIO(0x9888), 0x0e4f003c },
+ { _MMIO(0x9888), 0x004f0d80 },
+ { _MMIO(0x9888), 0x024f003b },
+ { _MMIO(0x9888), 0x006c0002 },
+ { _MMIO(0x9888), 0x086c0000 },
+ { _MMIO(0x9888), 0x0c6c000c },
+ { _MMIO(0x9888), 0x0e6c0b00 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x081b8000 },
+ { _MMIO(0x9888), 0x0c1b4000 },
+ { _MMIO(0x9888), 0x0e1b8000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1c8000 },
+ { _MMIO(0x9888), 0x1c1c0024 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5bc000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x1a5c6000 },
+ { _MMIO(0x9888), 0x1c5c001b },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2000 },
+ { _MMIO(0x9888), 0x0c4c0208 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cfb00 },
+ { _MMIO(0x9888), 0x182c00be },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900167 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900842 },
+ { _MMIO(0x9888), 0x47900802 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900802 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53901111 },
+};
+
+static const struct i915_oa_reg *
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
+ (dev_priv->drm.pdev->revision < 0x02)) {
+ *len = ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02);
+ return mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02;
+ } else if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
+ (dev_priv->drm.pdev->revision >= 0x02)) {
+ *len = ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02);
+ return mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile_1_0_sku_lt_0x02[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x15968000 },
+ { _MMIO(0x9888), 0x17968000 },
+ { _MMIO(0x9888), 0x0f96c000 },
+ { _MMIO(0x9888), 0x1f950011 },
+ { _MMIO(0x9888), 0x1d950014 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x0b978000 },
+ { _MMIO(0x9888), 0x0f974000 },
+ { _MMIO(0x9888), 0x11974000 },
+ { _MMIO(0x9888), 0x13978000 },
+ { _MMIO(0x9888), 0x09974000 },
+ { _MMIO(0xd28), 0x00000000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x419010a0 },
+ { _MMIO(0x9888), 0x55904000 },
+ { _MMIO(0x9888), 0x45901000 },
+ { _MMIO(0x9888), 0x47900084 },
+ { _MMIO(0x9888), 0x57904400 },
+ { _MMIO(0x9888), 0x499000a5 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900081 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x439014a4 },
+ { _MMIO(0x9888), 0x53900400 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile_1_0_sku_gte_0x02[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x1b931001 },
+ { _MMIO(0x9888), 0x1d930001 },
+ { _MMIO(0x9888), 0x19934000 },
+ { _MMIO(0x9888), 0x1b958000 },
+ { _MMIO(0x9888), 0x1d950094 },
+ { _MMIO(0x9888), 0x19958000 },
+ { _MMIO(0x9888), 0x05e5a000 },
+ { _MMIO(0x9888), 0x01e5c000 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x419010a0 },
+ { _MMIO(0x9888), 0x55904000 },
+ { _MMIO(0x9888), 0x45901000 },
+ { _MMIO(0x9888), 0x47900084 },
+ { _MMIO(0x9888), 0x57904400 },
+ { _MMIO(0x9888), 0x499000a5 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900081 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x439014a4 },
+ { _MMIO(0x9888), 0x53900400 },
+};
+
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (dev_priv->drm.pdev->revision < 0x02) {
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile_1_0_sku_lt_0x02);
+ return mux_config_render_pipe_profile_1_0_sku_lt_0x02;
+ } else if (dev_priv->drm.pdev->revision >= 0x02) {
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile_1_0_sku_gte_0x02);
+ return mux_config_render_pipe_profile_1_0_sku_gte_0x02;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x13946000 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x0f968000 },
+ { _MMIO(0x9888), 0x1196c000 },
+ { _MMIO(0x9888), 0x13964000 },
+ { _MMIO(0x9888), 0x11938000 },
+ { _MMIO(0x9888), 0x1b93fe00 },
+ { _MMIO(0x9888), 0x01940010 },
+ { _MMIO(0x9888), 0x07941100 },
+ { _MMIO(0x9888), 0x09941312 },
+ { _MMIO(0x9888), 0x0b941514 },
+ { _MMIO(0x9888), 0x0d941716 },
+ { _MMIO(0x9888), 0x11940000 },
+ { _MMIO(0x9888), 0x19940000 },
+ { _MMIO(0x9888), 0x1b940000 },
+ { _MMIO(0x9888), 0x1d940000 },
+ { _MMIO(0x9888), 0x1b954000 },
+ { _MMIO(0x9888), 0x1d95a550 },
+ { _MMIO(0x9888), 0x1f9502aa },
+ { _MMIO(0x9888), 0x2f900157 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13908000 },
+ { _MMIO(0x9888), 0x21908000 },
+ { _MMIO(0x9888), 0x23908000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27908000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0xd28), 0x00000000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads_1_0_sku_lt_0x05_and_sku_gte_0x02[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x13946000 },
+ { _MMIO(0x9888), 0x15940016 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x19930800 },
+ { _MMIO(0x9888), 0x1b93aa55 },
+ { _MMIO(0x9888), 0x1d9300aa },
+ { _MMIO(0x9888), 0x01940010 },
+ { _MMIO(0x9888), 0x07941100 },
+ { _MMIO(0x9888), 0x09941312 },
+ { _MMIO(0x9888), 0x0b941514 },
+ { _MMIO(0x9888), 0x0d941716 },
+ { _MMIO(0x9888), 0x0f940018 },
+ { _MMIO(0x9888), 0x1b940000 },
+ { _MMIO(0x9888), 0x11940000 },
+ { _MMIO(0x9888), 0x01e58000 },
+ { _MMIO(0x9888), 0x03e57000 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13908000 },
+ { _MMIO(0x9888), 0x21908000 },
+ { _MMIO(0x9888), 0x23908000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27908000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c20 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900421 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900421 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900061 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads_1_0_sku_gte_0x05[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900064 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900150 },
+ { _MMIO(0x9888), 0x21900151 },
+ { _MMIO(0x9888), 0x23900152 },
+ { _MMIO(0x9888), 0x25900153 },
+ { _MMIO(0x9888), 0x27900154 },
+ { _MMIO(0x9888), 0x29900155 },
+ { _MMIO(0x9888), 0x2b900156 },
+ { _MMIO(0x9888), 0x2d900157 },
+ { _MMIO(0x9888), 0x2f90015f },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
+ (dev_priv->drm.pdev->revision < 0x02)) {
+ *len = ARRAY_SIZE(mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02);
+ return mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02;
+ } else if ((dev_priv->drm.pdev->revision < 0x05) &&
+ (dev_priv->drm.pdev->revision >= 0x02)) {
+ *len = ARRAY_SIZE(mux_config_memory_reads_1_0_sku_lt_0x05_and_sku_gte_0x02);
+ return mux_config_memory_reads_1_0_sku_lt_0x05_and_sku_gte_0x02;
+ } else if (dev_priv->drm.pdev->revision >= 0x05) {
+ *len = ARRAY_SIZE(mux_config_memory_reads_1_0_sku_gte_0x05);
+ return mux_config_memory_reads_1_0_sku_gte_0x05;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x13945400 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901400 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x0f968000 },
+ { _MMIO(0x9888), 0x1196c000 },
+ { _MMIO(0x9888), 0x13964000 },
+ { _MMIO(0x9888), 0x11938000 },
+ { _MMIO(0x9888), 0x1b93fe00 },
+ { _MMIO(0x9888), 0x01940010 },
+ { _MMIO(0x9888), 0x07941100 },
+ { _MMIO(0x9888), 0x09941312 },
+ { _MMIO(0x9888), 0x0b941514 },
+ { _MMIO(0x9888), 0x0d941716 },
+ { _MMIO(0x9888), 0x11940000 },
+ { _MMIO(0x9888), 0x19940000 },
+ { _MMIO(0x9888), 0x1b940000 },
+ { _MMIO(0x9888), 0x1d940000 },
+ { _MMIO(0x9888), 0x1b954000 },
+ { _MMIO(0x9888), 0x1d95a550 },
+ { _MMIO(0x9888), 0x1f9502aa },
+ { _MMIO(0x9888), 0x2f900167 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13908000 },
+ { _MMIO(0x9888), 0x21908000 },
+ { _MMIO(0x9888), 0x23908000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27908000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0xd28), 0x00000000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes_1_0_sku_lt_0x05_and_sku_gte_0x02[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x13945400 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901400 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x19930800 },
+ { _MMIO(0x9888), 0x1b93aa55 },
+ { _MMIO(0x9888), 0x1d93002a },
+ { _MMIO(0x9888), 0x01940010 },
+ { _MMIO(0x9888), 0x07941100 },
+ { _MMIO(0x9888), 0x09941312 },
+ { _MMIO(0x9888), 0x0b941514 },
+ { _MMIO(0x9888), 0x0d941716 },
+ { _MMIO(0x9888), 0x1b940000 },
+ { _MMIO(0x9888), 0x11940000 },
+ { _MMIO(0x9888), 0x01e58000 },
+ { _MMIO(0x9888), 0x03e57000 },
+ { _MMIO(0x9888), 0x2f900167 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x13908000 },
+ { _MMIO(0x9888), 0x21908000 },
+ { _MMIO(0x9888), 0x23908000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27908000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c20 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900421 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900421 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes_1_0_sku_gte_0x05[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900160 },
+ { _MMIO(0x9888), 0x21900161 },
+ { _MMIO(0x9888), 0x23900162 },
+ { _MMIO(0x9888), 0x25900163 },
+ { _MMIO(0x9888), 0x27900164 },
+ { _MMIO(0x9888), 0x29900165 },
+ { _MMIO(0x9888), 0x2b900166 },
+ { _MMIO(0x9888), 0x2d900167 },
+ { _MMIO(0x9888), 0x2f900150 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) &&
+ (dev_priv->drm.pdev->revision < 0x02)) {
+ *len = ARRAY_SIZE(mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02);
+ return mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02;
+ } else if ((dev_priv->drm.pdev->revision < 0x05) &&
+ (dev_priv->drm.pdev->revision >= 0x02)) {
+ *len = ARRAY_SIZE(mux_config_memory_writes_1_0_sku_lt_0x05_and_sku_gte_0x02);
+ return mux_config_memory_writes_1_0_sku_lt_0x05_and_sku_gte_0x02;
+ } else if (dev_priv->drm.pdev->revision >= 0x05) {
+ *len = ARRAY_SIZE(mux_config_memory_writes_1_0_sku_gte_0x05);
+ return mux_config_memory_writes_1_0_sku_gte_0x05;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended_1_0_subslices_0x01[] = {
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x141c8160 },
+ { _MMIO(0x9888), 0x161c8015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4eaaa0 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0e6c0b01 },
+ { _MMIO(0x9888), 0x006c0200 },
+ { _MMIO(0x9888), 0x026c000c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x001c0041 },
+ { _MMIO(0x9888), 0x061c4200 },
+ { _MMIO(0x9888), 0x081c4443 },
+ { _MMIO(0x9888), 0x0a1c4645 },
+ { _MMIO(0x9888), 0x0c1c7647 },
+ { _MMIO(0x9888), 0x041c7357 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x101c0000 },
+ { _MMIO(0x9888), 0x1a1c0000 },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4caa2a },
+ { _MMIO(0x9888), 0x0c4c02aa },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5515 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0xd28), 0x00000000 },
+ { _MMIO(0x9888), 0x11907fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900802 },
+ { _MMIO(0x9888), 0x47900842 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900842 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900800 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
+ *len = ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01);
+ return mux_config_compute_extended_1_0_subslices_0x01;
+ }
+
+ *len = 0;
+ return NULL;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c0760 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f901403 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8020 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1ce000 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2a00 },
+ { _MMIO(0x9888), 0x0c4c0280 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f1500 },
+ { _MMIO(0x9888), 0x100f0140 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x182c00a0 },
+ { _MMIO(0x9888), 0x03933300 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900167 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190030f },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900042 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x53901111 },
+ { _MMIO(0x9888), 0x43900420 },
+};
+
+static const struct i915_oa_reg *
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_l3_cache);
+ return mux_config_compute_l3_cache;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x106c0232 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x004f1880 },
+ { _MMIO(0x9888), 0x024f08bb },
+ { _MMIO(0x9888), 0x044f001b },
+ { _MMIO(0x9888), 0x046c0100 },
+ { _MMIO(0x9888), 0x066c000b },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x041b8000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025bc000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x165c8000 },
+ { _MMIO(0x9888), 0x185c8000 },
+ { _MMIO(0x9888), 0x0a4c00a0 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x062cc000 },
+ { _MMIO(0x9888), 0x082cc000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x1d950080 },
+ { _MMIO(0x9888), 0x13928000 },
+ { _MMIO(0x9888), 0x0f988000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b9000a0 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x126c7b40 },
+ { _MMIO(0x9888), 0x166c0020 },
+ { _MMIO(0x9888), 0x0a603444 },
+ { _MMIO(0x9888), 0x0a613400 },
+ { _MMIO(0x9888), 0x1a4ea800 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0800 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x1c1c003c },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x10600000 },
+ { _MMIO(0x9888), 0x04600000 },
+ { _MMIO(0x9888), 0x0c610044 },
+ { _MMIO(0x9888), 0x10610000 },
+ { _MMIO(0x9888), 0x06610000 },
+ { _MMIO(0x9888), 0x0c4c02a8 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0154 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190ffc0 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900021 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900400 },
+ { _MMIO(0x9888), 0x43900421 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_1);
+ return mux_config_l3_1;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x126c02e0 },
+ { _MMIO(0x9888), 0x146c0001 },
+ { _MMIO(0x9888), 0x0a623400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x026c3324 },
+ { _MMIO(0x9888), 0x046c3422 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x06614000 },
+ { _MMIO(0x9888), 0x0c620044 },
+ { _MMIO(0x9888), 0x10620000 },
+ { _MMIO(0x9888), 0x06620000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_2);
+ return mux_config_l3_2;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x126c4e80 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x0a633400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x026c3321 },
+ { _MMIO(0x9888), 0x046c342f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c2000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x06604000 },
+ { _MMIO(0x9888), 0x0c630044 },
+ { _MMIO(0x9888), 0x10630000 },
+ { _MMIO(0x9888), 0x06630000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c00aa },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_3);
+ return mux_config_l3_3;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102f3800 },
+ { _MMIO(0x9888), 0x144d0500 },
+ { _MMIO(0x9888), 0x120d03c0 },
+ { _MMIO(0x9888), 0x140d03cf },
+ { _MMIO(0x9888), 0x0c0f0004 },
+ { _MMIO(0x9888), 0x0c4e4000 },
+ { _MMIO(0x9888), 0x042f0480 },
+ { _MMIO(0x9888), 0x082f0000 },
+ { _MMIO(0x9888), 0x022f0000 },
+ { _MMIO(0x9888), 0x0a4c0090 },
+ { _MMIO(0x9888), 0x064d0027 },
+ { _MMIO(0x9888), 0x004d0000 },
+ { _MMIO(0x9888), 0x000d0d40 },
+ { _MMIO(0x9888), 0x020d803f },
+ { _MMIO(0x9888), 0x040d8023 },
+ { _MMIO(0x9888), 0x100d0000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020f0010 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x0e0f0050 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x43901485 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x14152c00 },
+ { _MMIO(0x9888), 0x16150005 },
+ { _MMIO(0x9888), 0x121600a0 },
+ { _MMIO(0x9888), 0x14352c00 },
+ { _MMIO(0x9888), 0x16350005 },
+ { _MMIO(0x9888), 0x123600a0 },
+ { _MMIO(0x9888), 0x14552c00 },
+ { _MMIO(0x9888), 0x16550005 },
+ { _MMIO(0x9888), 0x125600a0 },
+ { _MMIO(0x9888), 0x062f6000 },
+ { _MMIO(0x9888), 0x022f2000 },
+ { _MMIO(0x9888), 0x0c4c0050 },
+ { _MMIO(0x9888), 0x0a4c0010 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0350 },
+ { _MMIO(0x9888), 0x0c0fb000 },
+ { _MMIO(0x9888), 0x0e0f00da },
+ { _MMIO(0x9888), 0x182c0028 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x022dc000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x0c138000 },
+ { _MMIO(0x9888), 0x0e132000 },
+ { _MMIO(0x9888), 0x0413c000 },
+ { _MMIO(0x9888), 0x1c140018 },
+ { _MMIO(0x9888), 0x0c157000 },
+ { _MMIO(0x9888), 0x0e150078 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04162180 },
+ { _MMIO(0x9888), 0x02160000 },
+ { _MMIO(0x9888), 0x04174000 },
+ { _MMIO(0x9888), 0x0233a000 },
+ { _MMIO(0x9888), 0x04333000 },
+ { _MMIO(0x9888), 0x14348000 },
+ { _MMIO(0x9888), 0x16348000 },
+ { _MMIO(0x9888), 0x02357870 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04360043 },
+ { _MMIO(0x9888), 0x02360000 },
+ { _MMIO(0x9888), 0x04371000 },
+ { _MMIO(0x9888), 0x0e538000 },
+ { _MMIO(0x9888), 0x00538000 },
+ { _MMIO(0x9888), 0x06533000 },
+ { _MMIO(0x9888), 0x1c540020 },
+ { _MMIO(0x9888), 0x12548000 },
+ { _MMIO(0x9888), 0x0e557000 },
+ { _MMIO(0x9888), 0x00557800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06560043 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x06571000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900060 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900060 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler);
+ return mux_config_sampler;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x12120000 },
+ { _MMIO(0x9888), 0x12320000 },
+ { _MMIO(0x9888), 0x12520000 },
+ { _MMIO(0x9888), 0x002f8000 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0015 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f03a0 },
+ { _MMIO(0x9888), 0x0c0ff000 },
+ { _MMIO(0x9888), 0x0e0f0095 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x02108000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x02118000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x02121880 },
+ { _MMIO(0x9888), 0x041219b5 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x02134000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x0c308000 },
+ { _MMIO(0x9888), 0x0e304000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x0c318000 },
+ { _MMIO(0x9888), 0x0e314000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x0c321a80 },
+ { _MMIO(0x9888), 0x0e320033 },
+ { _MMIO(0x9888), 0x06320031 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x0c334000 },
+ { _MMIO(0x9888), 0x0e331000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0e508000 },
+ { _MMIO(0x9888), 0x00508000 },
+ { _MMIO(0x9888), 0x02504000 },
+ { _MMIO(0x9888), 0x0e518000 },
+ { _MMIO(0x9888), 0x00518000 },
+ { _MMIO(0x9888), 0x02514000 },
+ { _MMIO(0x9888), 0x0e521880 },
+ { _MMIO(0x9888), 0x00521a80 },
+ { _MMIO(0x9888), 0x02520033 },
+ { _MMIO(0x9888), 0x0e534000 },
+ { _MMIO(0x9888), 0x00534000 },
+ { _MMIO(0x9888), 0x02531000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900062 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x12124d60 },
+ { _MMIO(0x9888), 0x12322e60 },
+ { _MMIO(0x9888), 0x12524d60 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0014 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0fe000 },
+ { _MMIO(0x9888), 0x0e0f0097 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x002d8000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x04121fb7 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x00308000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x00318000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x00321b80 },
+ { _MMIO(0x9888), 0x0632003f },
+ { _MMIO(0x9888), 0x00334000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0250c000 },
+ { _MMIO(0x9888), 0x0251c000 },
+ { _MMIO(0x9888), 0x02521fb7 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x02535000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900063 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+ { _MMIO(0xe458), 0x00001000 },
+ { _MMIO(0xe558), 0x00003002 },
+ { _MMIO(0xe658), 0x00005004 },
+ { _MMIO(0xe758), 0x00011010 },
+ { _MMIO(0xe45c), 0x00050012 },
+ { _MMIO(0xe55c), 0x00052051 },
+ { _MMIO(0xe65c), 0x00000008 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x121203e0 },
+ { _MMIO(0x9888), 0x123203e0 },
+ { _MMIO(0x9888), 0x125203e0 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0e0f006c },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x042d8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06114000 },
+ { _MMIO(0x9888), 0x06120033 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x04308000 },
+ { _MMIO(0x9888), 0x04318000 },
+ { _MMIO(0x9888), 0x04321980 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x04334000 },
+ { _MMIO(0x9888), 0x04504000 },
+ { _MMIO(0x9888), 0x04514000 },
+ { _MMIO(0x9888), 0x04520033 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x04531000 },
+ { _MMIO(0x9888), 0x1190e000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900c00 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extra);
+ return mux_config_compute_extra;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x141a5800 },
+ { _MMIO(0x9888), 0x161a00c0 },
+ { _MMIO(0x9888), 0x12180240 },
+ { _MMIO(0x9888), 0x14180002 },
+ { _MMIO(0x9888), 0x143a5800 },
+ { _MMIO(0x9888), 0x163a00c0 },
+ { _MMIO(0x9888), 0x12380240 },
+ { _MMIO(0x9888), 0x14380002 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x022f8000 },
+ { _MMIO(0x9888), 0x042f3000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c1500 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f9500 },
+ { _MMIO(0x9888), 0x100f002a },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x0a2dc000 },
+ { _MMIO(0x9888), 0x0c2dc000 },
+ { _MMIO(0x9888), 0x04193000 },
+ { _MMIO(0x9888), 0x081a28c1 },
+ { _MMIO(0x9888), 0x001a0000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x0613c000 },
+ { _MMIO(0x9888), 0x0813f000 },
+ { _MMIO(0x9888), 0x00172000 },
+ { _MMIO(0x9888), 0x06178000 },
+ { _MMIO(0x9888), 0x0817a000 },
+ { _MMIO(0x9888), 0x00180037 },
+ { _MMIO(0x9888), 0x06180940 },
+ { _MMIO(0x9888), 0x08180000 },
+ { _MMIO(0x9888), 0x02180000 },
+ { _MMIO(0x9888), 0x04183000 },
+ { _MMIO(0x9888), 0x06393000 },
+ { _MMIO(0x9888), 0x0c3a28c1 },
+ { _MMIO(0x9888), 0x003a0000 },
+ { _MMIO(0x9888), 0x0a33f000 },
+ { _MMIO(0x9888), 0x0c33f000 },
+ { _MMIO(0x9888), 0x0a37a000 },
+ { _MMIO(0x9888), 0x0c37a000 },
+ { _MMIO(0x9888), 0x0a380977 },
+ { _MMIO(0x9888), 0x08380000 },
+ { _MMIO(0x9888), 0x04380000 },
+ { _MMIO(0x9888), 0x06383000 },
+ { _MMIO(0x9888), 0x119000ff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900800 },
+ { _MMIO(0x9888), 0x47901000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900844 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_vme_pipe);
+ return mux_config_vme_pipe;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x11810000 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x03e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.mux_regs = NULL;
@@ -147,13 +2253,88 @@ int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0;
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
+ get_memory_reads_mux_config(dev_priv,
&dev_priv->perf.oa.mux_regs_len);
if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised so userspace and
@@ -163,14 +2344,364 @@ int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
}
dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
+ b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+ ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
+ flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
@@ -200,6 +2731,380 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic,
};
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "fe47b29d-ae51-423e-bff4-27d965a95b60",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "9bc436dd-6130-4add-affc-283eb6eaa864",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "2ea0da8f-3527-4669-9d9d-13099a7435bf",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "d97d16af-028b-4cd1-a672-6210cb5513dd",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "9fb22842-e708-43f7-9752-e0e41670c39e",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "5378e2a1-4248-4188-a4ae-da25a794c603",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "1988315f-0a26-44df-acb0-df7ec86b1456",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "97875e21-6624-4aee-9191-682feb3eae21",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "41a24047-7484-4ead-ae37-de907e5ff2b2",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "95910492-943f-44bd-9461-390240f243fd",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1",
+ .attrs = attrs_test_oa,
+};
+
int
i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv)
{
@@ -211,9 +3116,145 @@ i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv)
if (ret)
goto error_render_basic;
}
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
return 0;
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -225,4 +3266,38 @@ i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
index 0f508fed71e9..e16dea7dbace 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c
@@ -31,9 +31,26 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_sklgt3 = 1;
+int i915_oa_n_builtin_metric_sets_sklgt3 = 18;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
@@ -146,6 +163,1640 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return mux_config_render_basic;
}
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x1a4e0820 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f0032 },
+ { _MMIO(0x9888), 0x0a4f1891 },
+ { _MMIO(0x9888), 0x0c4f0e00 },
+ { _MMIO(0x9888), 0x0e4f003c },
+ { _MMIO(0x9888), 0x004f0d80 },
+ { _MMIO(0x9888), 0x024f003b },
+ { _MMIO(0x9888), 0x006c0002 },
+ { _MMIO(0x9888), 0x086c0100 },
+ { _MMIO(0x9888), 0x0c6c000c },
+ { _MMIO(0x9888), 0x0e6c0b00 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x081b8000 },
+ { _MMIO(0x9888), 0x0c1b4000 },
+ { _MMIO(0x9888), 0x0e1b8000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1c8000 },
+ { _MMIO(0x9888), 0x1c1c0024 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5bc000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x1a5c6000 },
+ { _MMIO(0x9888), 0x1c5c001b },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2000 },
+ { _MMIO(0x9888), 0x0c4c0208 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cfb00 },
+ { _MMIO(0x9888), 0x182c00be },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900158 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900863 },
+ { _MMIO(0x9888), 0x47900802 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900802 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900c62 },
+ { _MMIO(0x9888), 0x53903333 },
+};
+
+static const struct i915_oa_reg *
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_basic);
+ return mux_config_compute_basic;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x1b931001 },
+ { _MMIO(0x9888), 0x1d930001 },
+ { _MMIO(0x9888), 0x19934000 },
+ { _MMIO(0x9888), 0x1b958000 },
+ { _MMIO(0x9888), 0x1d950094 },
+ { _MMIO(0x9888), 0x19958000 },
+ { _MMIO(0x9888), 0x09e58000 },
+ { _MMIO(0x9888), 0x0be58000 },
+ { _MMIO(0x9888), 0x03e5c000 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51901150 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x55905111 },
+ { _MMIO(0x9888), 0x45901400 },
+ { _MMIO(0x9888), 0x479004a5 },
+ { _MMIO(0x9888), 0x57903455 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b9000a0 },
+ { _MMIO(0x9888), 0x59900001 },
+ { _MMIO(0x9888), 0x43900005 },
+ { _MMIO(0x9888), 0x53900455 },
+};
+
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile);
+ return mux_config_render_pipe_profile;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900064 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900150 },
+ { _MMIO(0x9888), 0x21900151 },
+ { _MMIO(0x9888), 0x23900152 },
+ { _MMIO(0x9888), 0x25900153 },
+ { _MMIO(0x9888), 0x27900154 },
+ { _MMIO(0x9888), 0x29900155 },
+ { _MMIO(0x9888), 0x2b900156 },
+ { _MMIO(0x9888), 0x2d900157 },
+ { _MMIO(0x9888), 0x2f90015f },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_memory_reads);
+ return mux_config_memory_reads;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900160 },
+ { _MMIO(0x9888), 0x21900161 },
+ { _MMIO(0x9888), 0x23900162 },
+ { _MMIO(0x9888), 0x25900163 },
+ { _MMIO(0x9888), 0x27900164 },
+ { _MMIO(0x9888), 0x29900165 },
+ { _MMIO(0x9888), 0x2b900166 },
+ { _MMIO(0x9888), 0x2d900167 },
+ { _MMIO(0x9888), 0x2f900150 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_memory_writes);
+ return mux_config_memory_writes;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x141c8160 },
+ { _MMIO(0x9888), 0x161c8015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4eaaa0 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0e6c0b01 },
+ { _MMIO(0x9888), 0x006c0200 },
+ { _MMIO(0x9888), 0x026c000c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x001c0041 },
+ { _MMIO(0x9888), 0x061c4200 },
+ { _MMIO(0x9888), 0x081c4443 },
+ { _MMIO(0x9888), 0x0a1c4645 },
+ { _MMIO(0x9888), 0x0c1c7647 },
+ { _MMIO(0x9888), 0x041c7357 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x101c0000 },
+ { _MMIO(0x9888), 0x1a1c0000 },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4caa2a },
+ { _MMIO(0x9888), 0x0c4c02aa },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5515 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x11907fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900802 },
+ { _MMIO(0x9888), 0x47900842 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900842 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900800 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extended);
+ return mux_config_compute_extended;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c0760 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8020 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1ce000 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2a00 },
+ { _MMIO(0x9888), 0x0c4c0280 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f1500 },
+ { _MMIO(0x9888), 0x100f0140 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x182c00a0 },
+ { _MMIO(0x9888), 0x03933300 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190030f },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900063 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x53903333 },
+ { _MMIO(0x9888), 0x43900840 },
+};
+
+static const struct i915_oa_reg *
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_l3_cache);
+ return mux_config_compute_l3_cache;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x106c0232 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x004f1880 },
+ { _MMIO(0x9888), 0x024f08bb },
+ { _MMIO(0x9888), 0x044f001b },
+ { _MMIO(0x9888), 0x046c0100 },
+ { _MMIO(0x9888), 0x066c000b },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x041b8000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025bc000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x165c8000 },
+ { _MMIO(0x9888), 0x185c8000 },
+ { _MMIO(0x9888), 0x0a4c00a0 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x062cc000 },
+ { _MMIO(0x9888), 0x082cc000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x1d950080 },
+ { _MMIO(0x9888), 0x13928000 },
+ { _MMIO(0x9888), 0x0f988000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900005 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x126c7b40 },
+ { _MMIO(0x9888), 0x166c0020 },
+ { _MMIO(0x9888), 0x0a603444 },
+ { _MMIO(0x9888), 0x0a613400 },
+ { _MMIO(0x9888), 0x1a4ea800 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0800 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x1c1c003c },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x10600000 },
+ { _MMIO(0x9888), 0x04600000 },
+ { _MMIO(0x9888), 0x0c610044 },
+ { _MMIO(0x9888), 0x10610000 },
+ { _MMIO(0x9888), 0x06610000 },
+ { _MMIO(0x9888), 0x0c4c02a8 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0154 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190ffc0 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900021 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900400 },
+ { _MMIO(0x9888), 0x43900421 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_1);
+ return mux_config_l3_1;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x126c02e0 },
+ { _MMIO(0x9888), 0x146c0001 },
+ { _MMIO(0x9888), 0x0a623400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x026c3324 },
+ { _MMIO(0x9888), 0x046c3422 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x06614000 },
+ { _MMIO(0x9888), 0x0c620044 },
+ { _MMIO(0x9888), 0x10620000 },
+ { _MMIO(0x9888), 0x06620000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_2);
+ return mux_config_l3_2;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x126c4e80 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x0a633400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x026c3321 },
+ { _MMIO(0x9888), 0x046c342f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c2000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x06604000 },
+ { _MMIO(0x9888), 0x0c630044 },
+ { _MMIO(0x9888), 0x10630000 },
+ { _MMIO(0x9888), 0x06630000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c00aa },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_3);
+ return mux_config_l3_3;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102f3800 },
+ { _MMIO(0x9888), 0x144d0500 },
+ { _MMIO(0x9888), 0x120d03c0 },
+ { _MMIO(0x9888), 0x140d03cf },
+ { _MMIO(0x9888), 0x0c0f0004 },
+ { _MMIO(0x9888), 0x0c4e4000 },
+ { _MMIO(0x9888), 0x042f0480 },
+ { _MMIO(0x9888), 0x082f0000 },
+ { _MMIO(0x9888), 0x022f0000 },
+ { _MMIO(0x9888), 0x0a4c0090 },
+ { _MMIO(0x9888), 0x064d0027 },
+ { _MMIO(0x9888), 0x004d0000 },
+ { _MMIO(0x9888), 0x000d0d40 },
+ { _MMIO(0x9888), 0x020d803f },
+ { _MMIO(0x9888), 0x040d8023 },
+ { _MMIO(0x9888), 0x100d0000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020f0010 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x0e0f0050 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x43901485 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x14152c00 },
+ { _MMIO(0x9888), 0x16150005 },
+ { _MMIO(0x9888), 0x121600a0 },
+ { _MMIO(0x9888), 0x14352c00 },
+ { _MMIO(0x9888), 0x16350005 },
+ { _MMIO(0x9888), 0x123600a0 },
+ { _MMIO(0x9888), 0x14552c00 },
+ { _MMIO(0x9888), 0x16550005 },
+ { _MMIO(0x9888), 0x125600a0 },
+ { _MMIO(0x9888), 0x062f6000 },
+ { _MMIO(0x9888), 0x022f2000 },
+ { _MMIO(0x9888), 0x0c4c0050 },
+ { _MMIO(0x9888), 0x0a4c0010 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0350 },
+ { _MMIO(0x9888), 0x0c0fb000 },
+ { _MMIO(0x9888), 0x0e0f00da },
+ { _MMIO(0x9888), 0x182c0028 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x022dc000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x0c138000 },
+ { _MMIO(0x9888), 0x0e132000 },
+ { _MMIO(0x9888), 0x0413c000 },
+ { _MMIO(0x9888), 0x1c140018 },
+ { _MMIO(0x9888), 0x0c157000 },
+ { _MMIO(0x9888), 0x0e150078 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04162180 },
+ { _MMIO(0x9888), 0x02160000 },
+ { _MMIO(0x9888), 0x04174000 },
+ { _MMIO(0x9888), 0x0233a000 },
+ { _MMIO(0x9888), 0x04333000 },
+ { _MMIO(0x9888), 0x14348000 },
+ { _MMIO(0x9888), 0x16348000 },
+ { _MMIO(0x9888), 0x02357870 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04360043 },
+ { _MMIO(0x9888), 0x02360000 },
+ { _MMIO(0x9888), 0x04371000 },
+ { _MMIO(0x9888), 0x0e538000 },
+ { _MMIO(0x9888), 0x00538000 },
+ { _MMIO(0x9888), 0x06533000 },
+ { _MMIO(0x9888), 0x1c540020 },
+ { _MMIO(0x9888), 0x12548000 },
+ { _MMIO(0x9888), 0x0e557000 },
+ { _MMIO(0x9888), 0x00557800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06560043 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x06571000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900060 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900060 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler);
+ return mux_config_sampler;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x12120000 },
+ { _MMIO(0x9888), 0x12320000 },
+ { _MMIO(0x9888), 0x12520000 },
+ { _MMIO(0x9888), 0x002f8000 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0015 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f03a0 },
+ { _MMIO(0x9888), 0x0c0ff000 },
+ { _MMIO(0x9888), 0x0e0f0095 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x02108000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x02118000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x02121880 },
+ { _MMIO(0x9888), 0x041219b5 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x02134000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x0c308000 },
+ { _MMIO(0x9888), 0x0e304000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x0c318000 },
+ { _MMIO(0x9888), 0x0e314000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x0c321a80 },
+ { _MMIO(0x9888), 0x0e320033 },
+ { _MMIO(0x9888), 0x06320031 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x0c334000 },
+ { _MMIO(0x9888), 0x0e331000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0e508000 },
+ { _MMIO(0x9888), 0x00508000 },
+ { _MMIO(0x9888), 0x02504000 },
+ { _MMIO(0x9888), 0x0e518000 },
+ { _MMIO(0x9888), 0x00518000 },
+ { _MMIO(0x9888), 0x02514000 },
+ { _MMIO(0x9888), 0x0e521880 },
+ { _MMIO(0x9888), 0x00521a80 },
+ { _MMIO(0x9888), 0x02520033 },
+ { _MMIO(0x9888), 0x0e534000 },
+ { _MMIO(0x9888), 0x00534000 },
+ { _MMIO(0x9888), 0x02531000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900062 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x12124d60 },
+ { _MMIO(0x9888), 0x12322e60 },
+ { _MMIO(0x9888), 0x12524d60 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0014 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0fe000 },
+ { _MMIO(0x9888), 0x0e0f0097 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x002d8000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x04121fb7 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x00308000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x00318000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x00321b80 },
+ { _MMIO(0x9888), 0x0632003f },
+ { _MMIO(0x9888), 0x00334000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0250c000 },
+ { _MMIO(0x9888), 0x0251c000 },
+ { _MMIO(0x9888), 0x02521fb7 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x02535000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900063 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x121203e0 },
+ { _MMIO(0x9888), 0x123203e0 },
+ { _MMIO(0x9888), 0x125203e0 },
+ { _MMIO(0x9888), 0x129203e0 },
+ { _MMIO(0x9888), 0x12b203e0 },
+ { _MMIO(0x9888), 0x12d203e0 },
+ { _MMIO(0x9888), 0x024ec000 },
+ { _MMIO(0x9888), 0x044ec000 },
+ { _MMIO(0x9888), 0x064ec000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c0042 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f006d },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x042d8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06114000 },
+ { _MMIO(0x9888), 0x06120033 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x04308000 },
+ { _MMIO(0x9888), 0x04318000 },
+ { _MMIO(0x9888), 0x04321980 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x04334000 },
+ { _MMIO(0x9888), 0x04504000 },
+ { _MMIO(0x9888), 0x04514000 },
+ { _MMIO(0x9888), 0x04520033 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x04531000 },
+ { _MMIO(0x9888), 0x00af8000 },
+ { _MMIO(0x9888), 0x0acc0001 },
+ { _MMIO(0x9888), 0x008d8000 },
+ { _MMIO(0x9888), 0x028da000 },
+ { _MMIO(0x9888), 0x0c8fb000 },
+ { _MMIO(0x9888), 0x0e8f0001 },
+ { _MMIO(0x9888), 0x06ac8000 },
+ { _MMIO(0x9888), 0x02ad4000 },
+ { _MMIO(0x9888), 0x02908000 },
+ { _MMIO(0x9888), 0x02918000 },
+ { _MMIO(0x9888), 0x02921980 },
+ { _MMIO(0x9888), 0x00920000 },
+ { _MMIO(0x9888), 0x02934000 },
+ { _MMIO(0x9888), 0x02b04000 },
+ { _MMIO(0x9888), 0x02b14000 },
+ { _MMIO(0x9888), 0x02b20033 },
+ { _MMIO(0x9888), 0x00b20000 },
+ { _MMIO(0x9888), 0x02b31000 },
+ { _MMIO(0x9888), 0x00d08000 },
+ { _MMIO(0x9888), 0x00d18000 },
+ { _MMIO(0x9888), 0x00d21980 },
+ { _MMIO(0x9888), 0x00d34000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900402 },
+ { _MMIO(0x9888), 0x53901550 },
+ { _MMIO(0x9888), 0x45900080 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extra);
+ return mux_config_compute_extra;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x141a5800 },
+ { _MMIO(0x9888), 0x161a00c0 },
+ { _MMIO(0x9888), 0x12180240 },
+ { _MMIO(0x9888), 0x14180002 },
+ { _MMIO(0x9888), 0x149a5800 },
+ { _MMIO(0x9888), 0x169a00c0 },
+ { _MMIO(0x9888), 0x12980240 },
+ { _MMIO(0x9888), 0x14980002 },
+ { _MMIO(0x9888), 0x1a4e3fc0 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x022f8000 },
+ { _MMIO(0x9888), 0x042f3000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c9500 },
+ { _MMIO(0x9888), 0x0c4c002a },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0015 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c000a },
+ { _MMIO(0x9888), 0x04193000 },
+ { _MMIO(0x9888), 0x081a28c1 },
+ { _MMIO(0x9888), 0x001a0000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x0613c000 },
+ { _MMIO(0x9888), 0x0813f000 },
+ { _MMIO(0x9888), 0x00172000 },
+ { _MMIO(0x9888), 0x06178000 },
+ { _MMIO(0x9888), 0x0817a000 },
+ { _MMIO(0x9888), 0x00180037 },
+ { _MMIO(0x9888), 0x06180940 },
+ { _MMIO(0x9888), 0x08180000 },
+ { _MMIO(0x9888), 0x02180000 },
+ { _MMIO(0x9888), 0x04183000 },
+ { _MMIO(0x9888), 0x04afc000 },
+ { _MMIO(0x9888), 0x06af3000 },
+ { _MMIO(0x9888), 0x0acc4000 },
+ { _MMIO(0x9888), 0x0ccc0015 },
+ { _MMIO(0x9888), 0x0a8da000 },
+ { _MMIO(0x9888), 0x0c8da000 },
+ { _MMIO(0x9888), 0x0e8f4000 },
+ { _MMIO(0x9888), 0x108f0015 },
+ { _MMIO(0x9888), 0x16aca000 },
+ { _MMIO(0x9888), 0x18ac000a },
+ { _MMIO(0x9888), 0x06993000 },
+ { _MMIO(0x9888), 0x0c9a28c1 },
+ { _MMIO(0x9888), 0x009a0000 },
+ { _MMIO(0x9888), 0x0a93f000 },
+ { _MMIO(0x9888), 0x0c93f000 },
+ { _MMIO(0x9888), 0x0a97a000 },
+ { _MMIO(0x9888), 0x0c97a000 },
+ { _MMIO(0x9888), 0x0a980977 },
+ { _MMIO(0x9888), 0x08980000 },
+ { _MMIO(0x9888), 0x04980000 },
+ { _MMIO(0x9888), 0x06983000 },
+ { _MMIO(0x9888), 0x119000ff },
+ { _MMIO(0x9888), 0x51900050 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900115 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x47900884 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900002 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_vme_pipe);
+ return mux_config_vme_pipe;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x11810000 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.mux_regs = NULL;
@@ -155,13 +1806,88 @@ int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0;
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
+ get_memory_reads_mux_config(dev_priv,
&dev_priv->perf.oa.mux_regs_len);
if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised so userspace and
@@ -171,14 +1897,364 @@ int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
}
dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
+ b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+ ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
+ flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
@@ -208,6 +2284,380 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic,
};
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "055f256d-4052-467c-8dec-6064a4806433",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "753972d4-87cd-4460-824d-754463ac5054",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "27076eeb-49f3-4fed-8423-c66506005c63",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "8071b409-c39a-4674-94d7-32962ecfb512",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "1988315f-0a26-44df-acb0-df7ec86b1456",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "97875e21-6624-4aee-9191-682feb3eae21",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "cfae9232-6ffc-42cc-a703-9790016925f0",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "882fa433-1f4a-4a67-a962-c741888fe5f5",
+ .attrs = attrs_test_oa,
+};
+
int
i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv)
{
@@ -219,9 +2669,145 @@ i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv)
if (ret)
goto error_render_basic;
}
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
return 0;
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -233,4 +2819,38 @@ i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
index eb78f1ea659f..c512afb2d8d9 100644
--- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c
+++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c
@@ -31,9 +31,26 @@
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
};
-int i915_oa_n_builtin_metric_sets_sklgt4 = 1;
+int i915_oa_n_builtin_metric_sets_sklgt4 = 18;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
@@ -157,6 +174,1683 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return mux_config_render_basic;
}
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x1a4e0820 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f0032 },
+ { _MMIO(0x9888), 0x0a4f1891 },
+ { _MMIO(0x9888), 0x0c4f0e00 },
+ { _MMIO(0x9888), 0x0e4f003c },
+ { _MMIO(0x9888), 0x004f0d80 },
+ { _MMIO(0x9888), 0x024f003b },
+ { _MMIO(0x9888), 0x006c0002 },
+ { _MMIO(0x9888), 0x086c0100 },
+ { _MMIO(0x9888), 0x0c6c000c },
+ { _MMIO(0x9888), 0x0e6c0b00 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x081b8000 },
+ { _MMIO(0x9888), 0x0c1b4000 },
+ { _MMIO(0x9888), 0x0e1b8000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1c8000 },
+ { _MMIO(0x9888), 0x1c1c0024 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5bc000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x1a5c6000 },
+ { _MMIO(0x9888), 0x1c5c001b },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2000 },
+ { _MMIO(0x9888), 0x0c4c0208 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cfb00 },
+ { _MMIO(0x9888), 0x182c00be },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900158 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900821 },
+ { _MMIO(0x9888), 0x47900802 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900802 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900422 },
+ { _MMIO(0x9888), 0x53905555 },
+};
+
+static const struct i915_oa_reg *
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_basic);
+ return mux_config_compute_basic;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x1b931001 },
+ { _MMIO(0x9888), 0x1d930001 },
+ { _MMIO(0x9888), 0x19934000 },
+ { _MMIO(0x9888), 0x1b958000 },
+ { _MMIO(0x9888), 0x1d950094 },
+ { _MMIO(0x9888), 0x19958000 },
+ { _MMIO(0x9888), 0x09e58000 },
+ { _MMIO(0x9888), 0x0be58000 },
+ { _MMIO(0x9888), 0x03e5c000 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51901110 },
+ { _MMIO(0x9888), 0x41900440 },
+ { _MMIO(0x9888), 0x55901111 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900c21 },
+ { _MMIO(0x9888), 0x57901411 },
+ { _MMIO(0x9888), 0x49900042 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900024 },
+ { _MMIO(0x9888), 0x59900001 },
+ { _MMIO(0x9888), 0x43900841 },
+ { _MMIO(0x9888), 0x53900411 },
+};
+
+static const struct i915_oa_reg *
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_render_pipe_profile);
+ return mux_config_render_pipe_profile;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900064 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900150 },
+ { _MMIO(0x9888), 0x21900151 },
+ { _MMIO(0x9888), 0x23900152 },
+ { _MMIO(0x9888), 0x25900153 },
+ { _MMIO(0x9888), 0x27900154 },
+ { _MMIO(0x9888), 0x29900155 },
+ { _MMIO(0x9888), 0x2b900156 },
+ { _MMIO(0x9888), 0x2d900157 },
+ { _MMIO(0x9888), 0x2f90015f },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_memory_reads);
+ return mux_config_memory_reads;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900160 },
+ { _MMIO(0x9888), 0x21900161 },
+ { _MMIO(0x9888), 0x23900162 },
+ { _MMIO(0x9888), 0x25900163 },
+ { _MMIO(0x9888), 0x27900164 },
+ { _MMIO(0x9888), 0x29900165 },
+ { _MMIO(0x9888), 0x2b900166 },
+ { _MMIO(0x9888), 0x2d900167 },
+ { _MMIO(0x9888), 0x2f900150 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_memory_writes);
+ return mux_config_memory_writes;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x141c8160 },
+ { _MMIO(0x9888), 0x161c8015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4eaaa0 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0e6c0b01 },
+ { _MMIO(0x9888), 0x006c0200 },
+ { _MMIO(0x9888), 0x026c000c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x001c0041 },
+ { _MMIO(0x9888), 0x061c4200 },
+ { _MMIO(0x9888), 0x081c4443 },
+ { _MMIO(0x9888), 0x0a1c4645 },
+ { _MMIO(0x9888), 0x0c1c7647 },
+ { _MMIO(0x9888), 0x041c7357 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x101c0000 },
+ { _MMIO(0x9888), 0x1a1c0000 },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4caa2a },
+ { _MMIO(0x9888), 0x0c4c02aa },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5515 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x11907fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900802 },
+ { _MMIO(0x9888), 0x47900842 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900842 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900800 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extended);
+ return mux_config_compute_extended;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c0760 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8020 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1ce000 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2a00 },
+ { _MMIO(0x9888), 0x0c4c0280 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f1500 },
+ { _MMIO(0x9888), 0x100f0140 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x182c00a0 },
+ { _MMIO(0x9888), 0x03933300 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190030f },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900021 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x53905555 },
+ { _MMIO(0x9888), 0x43900000 },
+};
+
+static const struct i915_oa_reg *
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_l3_cache);
+ return mux_config_compute_l3_cache;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x106c0232 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x004f1880 },
+ { _MMIO(0x9888), 0x024f08bb },
+ { _MMIO(0x9888), 0x044f001b },
+ { _MMIO(0x9888), 0x046c0100 },
+ { _MMIO(0x9888), 0x066c000b },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x041b8000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025bc000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x165c8000 },
+ { _MMIO(0x9888), 0x185c8000 },
+ { _MMIO(0x9888), 0x0a4c00a0 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x062cc000 },
+ { _MMIO(0x9888), 0x082cc000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x1d950080 },
+ { _MMIO(0x9888), 0x13928000 },
+ { _MMIO(0x9888), 0x0f988000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900001 },
+ { _MMIO(0x9888), 0x4b900040 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_hdc_and_sf);
+ return mux_config_hdc_and_sf;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x126c7b40 },
+ { _MMIO(0x9888), 0x166c0020 },
+ { _MMIO(0x9888), 0x0a603444 },
+ { _MMIO(0x9888), 0x0a613400 },
+ { _MMIO(0x9888), 0x1a4ea800 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0800 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x1c1c003c },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x10600000 },
+ { _MMIO(0x9888), 0x04600000 },
+ { _MMIO(0x9888), 0x0c610044 },
+ { _MMIO(0x9888), 0x10610000 },
+ { _MMIO(0x9888), 0x06610000 },
+ { _MMIO(0x9888), 0x0c4c02a8 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0154 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190ffc0 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900021 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900400 },
+ { _MMIO(0x9888), 0x43900421 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_1);
+ return mux_config_l3_1;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x126c02e0 },
+ { _MMIO(0x9888), 0x146c0001 },
+ { _MMIO(0x9888), 0x0a623400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x026c3324 },
+ { _MMIO(0x9888), 0x046c3422 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x06614000 },
+ { _MMIO(0x9888), 0x0c620044 },
+ { _MMIO(0x9888), 0x10620000 },
+ { _MMIO(0x9888), 0x06620000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_2);
+ return mux_config_l3_2;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x126c4e80 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x0a633400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x026c3321 },
+ { _MMIO(0x9888), 0x046c342f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c2000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x06604000 },
+ { _MMIO(0x9888), 0x0c630044 },
+ { _MMIO(0x9888), 0x10630000 },
+ { _MMIO(0x9888), 0x06630000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c00aa },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_l3_3);
+ return mux_config_l3_3;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102f3800 },
+ { _MMIO(0x9888), 0x144d0500 },
+ { _MMIO(0x9888), 0x120d03c0 },
+ { _MMIO(0x9888), 0x140d03cf },
+ { _MMIO(0x9888), 0x0c0f0004 },
+ { _MMIO(0x9888), 0x0c4e4000 },
+ { _MMIO(0x9888), 0x042f0480 },
+ { _MMIO(0x9888), 0x082f0000 },
+ { _MMIO(0x9888), 0x022f0000 },
+ { _MMIO(0x9888), 0x0a4c0090 },
+ { _MMIO(0x9888), 0x064d0027 },
+ { _MMIO(0x9888), 0x004d0000 },
+ { _MMIO(0x9888), 0x000d0d40 },
+ { _MMIO(0x9888), 0x020d803f },
+ { _MMIO(0x9888), 0x040d8023 },
+ { _MMIO(0x9888), 0x100d0000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020f0010 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x0e0f0050 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x43901485 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ return mux_config_rasterizer_and_pixel_backend;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x14152c00 },
+ { _MMIO(0x9888), 0x16150005 },
+ { _MMIO(0x9888), 0x121600a0 },
+ { _MMIO(0x9888), 0x14352c00 },
+ { _MMIO(0x9888), 0x16350005 },
+ { _MMIO(0x9888), 0x123600a0 },
+ { _MMIO(0x9888), 0x14552c00 },
+ { _MMIO(0x9888), 0x16550005 },
+ { _MMIO(0x9888), 0x125600a0 },
+ { _MMIO(0x9888), 0x062f6000 },
+ { _MMIO(0x9888), 0x022f2000 },
+ { _MMIO(0x9888), 0x0c4c0050 },
+ { _MMIO(0x9888), 0x0a4c0010 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0350 },
+ { _MMIO(0x9888), 0x0c0fb000 },
+ { _MMIO(0x9888), 0x0e0f00da },
+ { _MMIO(0x9888), 0x182c0028 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x022dc000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x0c138000 },
+ { _MMIO(0x9888), 0x0e132000 },
+ { _MMIO(0x9888), 0x0413c000 },
+ { _MMIO(0x9888), 0x1c140018 },
+ { _MMIO(0x9888), 0x0c157000 },
+ { _MMIO(0x9888), 0x0e150078 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04162180 },
+ { _MMIO(0x9888), 0x02160000 },
+ { _MMIO(0x9888), 0x04174000 },
+ { _MMIO(0x9888), 0x0233a000 },
+ { _MMIO(0x9888), 0x04333000 },
+ { _MMIO(0x9888), 0x14348000 },
+ { _MMIO(0x9888), 0x16348000 },
+ { _MMIO(0x9888), 0x02357870 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04360043 },
+ { _MMIO(0x9888), 0x02360000 },
+ { _MMIO(0x9888), 0x04371000 },
+ { _MMIO(0x9888), 0x0e538000 },
+ { _MMIO(0x9888), 0x00538000 },
+ { _MMIO(0x9888), 0x06533000 },
+ { _MMIO(0x9888), 0x1c540020 },
+ { _MMIO(0x9888), 0x12548000 },
+ { _MMIO(0x9888), 0x0e557000 },
+ { _MMIO(0x9888), 0x00557800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06560043 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x06571000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900060 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900060 },
+};
+
+static const struct i915_oa_reg *
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_sampler);
+ return mux_config_sampler;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x12120000 },
+ { _MMIO(0x9888), 0x12320000 },
+ { _MMIO(0x9888), 0x12520000 },
+ { _MMIO(0x9888), 0x002f8000 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0015 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f03a0 },
+ { _MMIO(0x9888), 0x0c0ff000 },
+ { _MMIO(0x9888), 0x0e0f0095 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x02108000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x02118000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x02121880 },
+ { _MMIO(0x9888), 0x041219b5 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x02134000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x0c308000 },
+ { _MMIO(0x9888), 0x0e304000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x0c318000 },
+ { _MMIO(0x9888), 0x0e314000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x0c321a80 },
+ { _MMIO(0x9888), 0x0e320033 },
+ { _MMIO(0x9888), 0x06320031 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x0c334000 },
+ { _MMIO(0x9888), 0x0e331000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0e508000 },
+ { _MMIO(0x9888), 0x00508000 },
+ { _MMIO(0x9888), 0x02504000 },
+ { _MMIO(0x9888), 0x0e518000 },
+ { _MMIO(0x9888), 0x00518000 },
+ { _MMIO(0x9888), 0x02514000 },
+ { _MMIO(0x9888), 0x0e521880 },
+ { _MMIO(0x9888), 0x00521a80 },
+ { _MMIO(0x9888), 0x02520033 },
+ { _MMIO(0x9888), 0x0e534000 },
+ { _MMIO(0x9888), 0x00534000 },
+ { _MMIO(0x9888), 0x02531000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900062 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_1);
+ return mux_config_tdl_1;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x12124d60 },
+ { _MMIO(0x9888), 0x12322e60 },
+ { _MMIO(0x9888), 0x12524d60 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0014 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0fe000 },
+ { _MMIO(0x9888), 0x0e0f0097 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x002d8000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x04121fb7 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x00308000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x00318000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x00321b80 },
+ { _MMIO(0x9888), 0x0632003f },
+ { _MMIO(0x9888), 0x00334000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0250c000 },
+ { _MMIO(0x9888), 0x0251c000 },
+ { _MMIO(0x9888), 0x02521fb7 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x02535000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900063 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_tdl_2);
+ return mux_config_tdl_2;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x121203e0 },
+ { _MMIO(0x9888), 0x123203e0 },
+ { _MMIO(0x9888), 0x125203e0 },
+ { _MMIO(0x9888), 0x129203e0 },
+ { _MMIO(0x9888), 0x12b203e0 },
+ { _MMIO(0x9888), 0x12d203e0 },
+ { _MMIO(0x9888), 0x131203e0 },
+ { _MMIO(0x9888), 0x133203e0 },
+ { _MMIO(0x9888), 0x135203e0 },
+ { _MMIO(0x9888), 0x1a4ef000 },
+ { _MMIO(0x9888), 0x1c4e0003 },
+ { _MMIO(0x9888), 0x024ec000 },
+ { _MMIO(0x9888), 0x044ec000 },
+ { _MMIO(0x9888), 0x064ec000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0c4c02a0 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c0042 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0150 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f006d },
+ { _MMIO(0x9888), 0x182c00a8 },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x042d8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06114000 },
+ { _MMIO(0x9888), 0x06120033 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x04308000 },
+ { _MMIO(0x9888), 0x04318000 },
+ { _MMIO(0x9888), 0x04321980 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x04334000 },
+ { _MMIO(0x9888), 0x04504000 },
+ { _MMIO(0x9888), 0x04514000 },
+ { _MMIO(0x9888), 0x04520033 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x04531000 },
+ { _MMIO(0x9888), 0x1acef000 },
+ { _MMIO(0x9888), 0x1cce0003 },
+ { _MMIO(0x9888), 0x00af8000 },
+ { _MMIO(0x9888), 0x0ccc02a0 },
+ { _MMIO(0x9888), 0x0acc0001 },
+ { _MMIO(0x9888), 0x0c8d8000 },
+ { _MMIO(0x9888), 0x0e8da000 },
+ { _MMIO(0x9888), 0x008d8000 },
+ { _MMIO(0x9888), 0x028da000 },
+ { _MMIO(0x9888), 0x108f0150 },
+ { _MMIO(0x9888), 0x0c8fb000 },
+ { _MMIO(0x9888), 0x0e8f0001 },
+ { _MMIO(0x9888), 0x18ac00a8 },
+ { _MMIO(0x9888), 0x06ac8000 },
+ { _MMIO(0x9888), 0x02ad4000 },
+ { _MMIO(0x9888), 0x02908000 },
+ { _MMIO(0x9888), 0x02918000 },
+ { _MMIO(0x9888), 0x02921980 },
+ { _MMIO(0x9888), 0x00920000 },
+ { _MMIO(0x9888), 0x02934000 },
+ { _MMIO(0x9888), 0x02b04000 },
+ { _MMIO(0x9888), 0x02b14000 },
+ { _MMIO(0x9888), 0x02b20033 },
+ { _MMIO(0x9888), 0x00b20000 },
+ { _MMIO(0x9888), 0x02b31000 },
+ { _MMIO(0x9888), 0x00d08000 },
+ { _MMIO(0x9888), 0x00d18000 },
+ { _MMIO(0x9888), 0x00d21980 },
+ { _MMIO(0x9888), 0x00d34000 },
+ { _MMIO(0x9888), 0x072f8000 },
+ { _MMIO(0x9888), 0x0d4c0100 },
+ { _MMIO(0x9888), 0x0d0d8000 },
+ { _MMIO(0x9888), 0x0f0da000 },
+ { _MMIO(0x9888), 0x110f01b0 },
+ { _MMIO(0x9888), 0x192c0080 },
+ { _MMIO(0x9888), 0x0f2d4000 },
+ { _MMIO(0x9888), 0x0f108000 },
+ { _MMIO(0x9888), 0x0f118000 },
+ { _MMIO(0x9888), 0x0f121980 },
+ { _MMIO(0x9888), 0x01120000 },
+ { _MMIO(0x9888), 0x0f134000 },
+ { _MMIO(0x9888), 0x0f304000 },
+ { _MMIO(0x9888), 0x0f314000 },
+ { _MMIO(0x9888), 0x0f320033 },
+ { _MMIO(0x9888), 0x01320000 },
+ { _MMIO(0x9888), 0x0f331000 },
+ { _MMIO(0x9888), 0x0d508000 },
+ { _MMIO(0x9888), 0x0d518000 },
+ { _MMIO(0x9888), 0x0d521980 },
+ { _MMIO(0x9888), 0x01520000 },
+ { _MMIO(0x9888), 0x0d534000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51901100 },
+ { _MMIO(0x9888), 0x41901000 },
+ { _MMIO(0x9888), 0x43901423 },
+ { _MMIO(0x9888), 0x53903331 },
+ { _MMIO(0x9888), 0x45900044 },
+};
+
+static const struct i915_oa_reg *
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_compute_extra);
+ return mux_config_compute_extra;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x141a5800 },
+ { _MMIO(0x9888), 0x161a00c0 },
+ { _MMIO(0x9888), 0x12180240 },
+ { _MMIO(0x9888), 0x14180002 },
+ { _MMIO(0x9888), 0x149a5800 },
+ { _MMIO(0x9888), 0x169a00c0 },
+ { _MMIO(0x9888), 0x12980240 },
+ { _MMIO(0x9888), 0x14980002 },
+ { _MMIO(0x9888), 0x1a4e3fc0 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x022f8000 },
+ { _MMIO(0x9888), 0x042f3000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c9500 },
+ { _MMIO(0x9888), 0x0c4c002a },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0015 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c000a },
+ { _MMIO(0x9888), 0x04193000 },
+ { _MMIO(0x9888), 0x081a28c1 },
+ { _MMIO(0x9888), 0x001a0000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x0613c000 },
+ { _MMIO(0x9888), 0x0813f000 },
+ { _MMIO(0x9888), 0x00172000 },
+ { _MMIO(0x9888), 0x06178000 },
+ { _MMIO(0x9888), 0x0817a000 },
+ { _MMIO(0x9888), 0x00180037 },
+ { _MMIO(0x9888), 0x06180940 },
+ { _MMIO(0x9888), 0x08180000 },
+ { _MMIO(0x9888), 0x02180000 },
+ { _MMIO(0x9888), 0x04183000 },
+ { _MMIO(0x9888), 0x04afc000 },
+ { _MMIO(0x9888), 0x06af3000 },
+ { _MMIO(0x9888), 0x0acc4000 },
+ { _MMIO(0x9888), 0x0ccc0015 },
+ { _MMIO(0x9888), 0x0a8da000 },
+ { _MMIO(0x9888), 0x0c8da000 },
+ { _MMIO(0x9888), 0x0e8f4000 },
+ { _MMIO(0x9888), 0x108f0015 },
+ { _MMIO(0x9888), 0x16aca000 },
+ { _MMIO(0x9888), 0x18ac000a },
+ { _MMIO(0x9888), 0x06993000 },
+ { _MMIO(0x9888), 0x0c9a28c1 },
+ { _MMIO(0x9888), 0x009a0000 },
+ { _MMIO(0x9888), 0x0a93f000 },
+ { _MMIO(0x9888), 0x0c93f000 },
+ { _MMIO(0x9888), 0x0a97a000 },
+ { _MMIO(0x9888), 0x0c97a000 },
+ { _MMIO(0x9888), 0x0a980977 },
+ { _MMIO(0x9888), 0x08980000 },
+ { _MMIO(0x9888), 0x04980000 },
+ { _MMIO(0x9888), 0x06983000 },
+ { _MMIO(0x9888), 0x119000ff },
+ { _MMIO(0x9888), 0x51900010 },
+ { _MMIO(0x9888), 0x41900060 },
+ { _MMIO(0x9888), 0x55900111 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900821 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900002 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_vme_pipe);
+ return mux_config_vme_pipe;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x11810000 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static const struct i915_oa_reg *
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ int *len)
+{
+ *len = ARRAY_SIZE(mux_config_test_oa);
+ return mux_config_test_oa;
+}
+
int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.mux_regs = NULL;
@@ -166,13 +1860,88 @@ int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0;
- switch (dev_priv->perf.oa.metrics_set) {
- case METRIC_SET_ID_RENDER_BASIC:
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.mux_regs =
- get_render_basic_mux_config(dev_priv,
+ get_memory_reads_mux_config(dev_priv,
&dev_priv->perf.oa.mux_regs_len);
if (!dev_priv->perf.oa.mux_regs) {
- DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised so userspace and
@@ -182,14 +1951,364 @@ int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
}
dev_priv->perf.oa.b_counter_regs =
- b_counter_config_render_basic;
+ b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
- ARRAY_SIZE(b_counter_config_render_basic);
+ ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
- flex_eu_config_render_basic;
+ flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
- ARRAY_SIZE(flex_eu_config_render_basic);
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.mux_regs =
+ get_sampler_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ &dev_priv->perf.oa.mux_regs_len);
+ if (!dev_priv->perf.oa.mux_regs) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised so userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
@@ -219,6 +2338,380 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic,
};
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "7277228f-e7f3-4743-945a-6a2049d11377",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "463c668c-3f60-49b6-8f85-d995b635b3b2",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "055f256d-4052-467c-8dec-6064a4806433",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "753972d4-87cd-4460-824d-754463ac5054",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "1988315f-0a26-44df-acb0-df7ec86b1456",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "97875e21-6624-4aee-9191-682feb3eae21",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "882fa433-1f4a-4a67-a962-c741888fe5f5",
+ .attrs = attrs_test_oa,
+};
+
int
i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv)
{
@@ -230,9 +2723,145 @@ i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv)
if (ret)
goto error_render_basic;
}
+ if (get_compute_basic_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, &mux_len)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
return 0;
+error_test_oa:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic:
return ret;
}
@@ -244,4 +2873,38 @@ i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, &mux_len))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, &mux_len))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
}
--
2.11.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
` (5 preceding siblings ...)
2017-02-22 16:36 ` [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT Robert Bragg
@ 2017-02-22 19:22 ` Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2017-02-22 19:22 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
== Series Details ==
Series: Enable OA unit for Gen 8 and 9 in i915 perf
URL : https://patchwork.freedesktop.org/series/20084/
State : success
== Summary ==
Series 20084v1 Enable OA unit for Gen 8 and 9 in i915 perf
https://patchwork.freedesktop.org/api/1.0/series/20084/revisions/1/mbox/
fi-bdw-5557u total:253 pass:242 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:253 pass:214 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:253 pass:234 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:253 pass:226 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:253 pass:222 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:253 pass:203 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-skl-6260u total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:253 pass:236 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:253 pass:231 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:253 pass:225 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:253 pass:224 dwarn:0 dfail:0 fail:0 skip:29
bf89ec45d0822835b03910371ac0baf46c4efa2d drm-tip: 2017y-02m-22d-14h-30m-04s UTC integration manifest
733c1e5 drm/i915: Add 'render basic' Gen8+ OA unit configs
73646a7 drm/i915: Add uncore mmio api for per-context registers
26c9eb3 drm/i915: expose _SUBSLICE_MASK GETPARM
b035818 drm/i915: expose _SLICE_MASK GETPARM
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3935/
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers
2017-02-22 16:36 ` [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers Robert Bragg
@ 2017-02-23 15:35 ` Chris Wilson
2017-03-23 16:43 ` Robert Bragg
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2017-02-23 15:35 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
On Wed, Feb 22, 2017 at 04:36:31PM +0000, Robert Bragg wrote:
> Since the exponent for periodic OA counter sampling is maintained in a
> per-context register while we want to treat it as if it were global
> state we need to be able to safely issue an mmio write to a per-context
> register and affect any currently running context.
>
> We have to take some extra care in this case and this adds a utility
> api to encapsulate what's required.
Been waying up the pros/cons of having this in uncore. It doesn't
attempt to be generic nor replace the existing instance, so atm I think
it might be better as local to i915_perf.
> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_uncore.c | 73 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 105b97bd34d7..c8d03a2e89cc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -718,6 +718,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
> i915_reg_t reg, unsigned int op);
>
> struct intel_uncore_funcs {
> + int (*wait_for_rcs_busy)(struct drm_i915_private *dev_priv);
> void (*force_wake_get)(struct drm_i915_private *dev_priv,
> enum forcewake_domains domains);
> void (*force_wake_put)(struct drm_i915_private *dev_priv,
> @@ -751,6 +752,7 @@ struct intel_uncore {
>
> struct intel_uncore_funcs funcs;
>
> + atomic_t hold_rcs_busy_count;
> unsigned fifo_count;
>
> enum forcewake_domains fw_domains;
> @@ -3139,6 +3141,8 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
> {
> return dev_priv->vgpu.active;
> }
> +int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv);
> +void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv);
>
> void
> i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 141a5c1e3895..94d40e82edc1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2313,6 +2313,9 @@ enum skl_disp_power_wells {
> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
>
> +#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
> +#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
> +
> /* Fuse readout registers for GT */
> #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
> #define CHV_FGT_DISABLE_SS0 (1 << 10)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 441c51fd9746..06bfe5f89ac5 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1274,6 +1274,16 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> WARN_ON(dev_priv->uncore.fw_domains == 0);
> }
>
> +static int gen8_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
> +{
> + return wait_for((I915_READ(GEN6_RCS_PWR_FSM) & 0x3f) == 0x30, 50);
> +}
> +
> +static int gen9_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
> +{
> + return wait_for((I915_READ(GEN9_RCS_FE_FSM2) & 0x3f) == 0x30, 50);
> +}
> +
> #define ASSIGN_FW_DOMAINS_TABLE(d) \
> { \
> dev_priv->uncore.fw_domains_table = \
> @@ -1305,6 +1315,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> dev_priv->uncore.funcs.mmio_writel =
> gen9_decoupled_write32;
> }
> + dev_priv->uncore.funcs.wait_for_rcs_busy =
> + gen9_wait_for_rcs_busy;
> break;
> case 8:
> if (IS_CHERRYVIEW(dev_priv)) {
> @@ -1316,6 +1328,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> ASSIGN_WRITE_MMIO_VFUNCS(gen8);
> ASSIGN_READ_MMIO_VFUNCS(gen6);
> }
> + dev_priv->uncore.funcs.wait_for_rcs_busy =
> + gen8_wait_for_rcs_busy;
> break;
> case 7:
> case 6:
> @@ -1858,6 +1872,65 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
> return fw_domains;
> }
>
> +static int hold_rcs_busy(struct drm_i915_private *dev_priv)
> +{
> + int ret = 0;
> +
> + if (atomic_inc_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
> + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> + _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
> +
> + ret = dev_priv->uncore.funcs.wait_for_rcs_busy(dev_priv);
> + }
> +
> + return ret;
> +}
> +
> +static void release_rcs_busy(struct drm_i915_private *dev_priv)
> +{
> + if (!atomic_dec_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
> + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
> + _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
> + }
atomic_inc_and_test is correct, but atomic_dec_and_test is backwards.
Besides if you just extend the irq spinlock slightly, you get:
+int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv)
+{
+ unsigned long flags;
+ i915_reg_t reg;
+ int ret;
+
+ if (INTEL_GEN(dev_priv) < 8)
+ return 0;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+ __intel_uncore_forcewake_get(dev_priv, FORCEWAKE_RENDER);
+
+ if (!dev_priv->uncore.rcs_hold_count++)
+ I915_WRITE_FW(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+
+ if (INTEL_GEN(dev_priv) == 8)
+ reg = GEN6_RCS_PWR_FSM;
+ else
+ reg = GEN9_RCS_FE_FSM2;
+
+ ret = wait_for_atomic((__raw_i915_read32(dev_priv, reg) & 0x3f) == 0x30,
+ 50);
+ if (ret)
+ __intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+
+ return ret;
+}
+
+void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv)
+{
+ unsigned long flags;
+
+ if (INTEL_GEN(dev_priv) < 8)
+ return;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
+ if (!--dev_priv->uncore.rcs_hold_count)
+ I915_WRITE_FW(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+ __intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+}
Note as well you need to think about serialising the wakeup, not just
the hold count.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT
2017-02-22 16:36 ` [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT Robert Bragg
@ 2017-03-01 13:00 ` Matthew Auld
2017-03-20 16:34 ` Robert Bragg
0 siblings, 1 reply; 12+ messages in thread
From: Matthew Auld @ 2017-03-01 13:00 UTC (permalink / raw)
To: Robert Bragg; +Cc: intel-gfx
On 02/22, Robert Bragg wrote:
> These are auto generated from an XML description of metric sets,
> currently maintained in gputop, ref:
>
> https://github.com/rib/gputop
> > gputop-data/oa-*.xml
> > scripts/i915-perf-kernelgen.py
>
> $ make -C gputop-data -f Makefile.xml
>
> Signed-off-by: Robert Bragg <robert@sixbynine.org>
> ---
<SNIP>
> +
> +static const struct i915_oa_reg *
> +get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
> + int *len)
> +{
> + if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01);
> + return mux_config_compute_extended_1_0_subslices_0x01;
> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_1_subslices_0x08);
> + return mux_config_compute_extended_1_1_subslices_0x08;
> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_2_subslices_0x02);
> + return mux_config_compute_extended_1_2_subslices_0x02;
> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_3_subslices_0x10);
> + return mux_config_compute_extended_1_3_subslices_0x10;
> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_4_subslices_0x04);
> + return mux_config_compute_extended_1_4_subslices_0x04;
> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) {
> + *len = ARRAY_SIZE(mux_config_compute_extended_1_5_subslices_0x20);
> + return mux_config_compute_extended_1_5_subslices_0x20;
> + *len = ARRAY_SIZE(mux_config_compute_extended);
> + return mux_config_compute_extended;
It looks like your script doesn't properly handle the unconditional mux
config here.
<SNIP>
> +
> +static const struct i915_oa_reg *
> +get_test_oa_mux_config(struct drm_i915_private *dev_priv,
> + int *len)
> +{
> + *len = ARRAY_SIZE(mux_config_test_oa);
> + return mux_config_test_oa;
> +}
> +
> +int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
> +{
> + dev_priv->perf.oa.mux_regs = NULL;
> + dev_priv->perf.oa.mux_regs_len = 0;
> + dev_priv->perf.oa.b_counter_regs = NULL;
> + dev_priv->perf.oa.b_counter_regs_len = 0;
> + dev_priv->perf.oa.flex_regs = NULL;
> + dev_priv->perf.oa.flex_regs_len = 0;
> +
> + switch (dev_priv->perf.oa.metrics_set) {
> + case METRIC_SET_ID_RENDER_BASIC:
> + dev_priv->perf.oa.mux_regs =
> + get_render_basic_mux_config(dev_priv,
> + &dev_priv->perf.oa.mux_regs_len);
> + if (!dev_priv->perf.oa.mux_regs) {
> + DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
Your script also needs to output a newline for DRM_DEBUG_DRIVER.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT
2017-03-01 13:00 ` Matthew Auld
@ 2017-03-20 16:34 ` Robert Bragg
0 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-03-20 16:34 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
On Wed, Mar 1, 2017 at 1:00 PM, Matthew Auld
<matthew.william.auld@gmail.com> wrote:
> On 02/22, Robert Bragg wrote:
>> These are auto generated from an XML description of metric sets,
>> currently maintained in gputop, ref:
>>
>> https://github.com/rib/gputop
>> > gputop-data/oa-*.xml
>> > scripts/i915-perf-kernelgen.py
>>
>> $ make -C gputop-data -f Makefile.xml
>>
>> Signed-off-by: Robert Bragg <robert@sixbynine.org>
>> ---
>
> <SNIP>
>
>> +
>> +static const struct i915_oa_reg *
>> +get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
>> + int *len)
>> +{
>> + if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01);
>> + return mux_config_compute_extended_1_0_subslices_0x01;
>> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_1_subslices_0x08);
>> + return mux_config_compute_extended_1_1_subslices_0x08;
>> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_2_subslices_0x02);
>> + return mux_config_compute_extended_1_2_subslices_0x02;
>> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_3_subslices_0x10);
>> + return mux_config_compute_extended_1_3_subslices_0x10;
>> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_4_subslices_0x04);
>> + return mux_config_compute_extended_1_4_subslices_0x04;
>> + } else if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) {
>> + *len = ARRAY_SIZE(mux_config_compute_extended_1_5_subslices_0x20);
>> + return mux_config_compute_extended_1_5_subslices_0x20;
>> + *len = ARRAY_SIZE(mux_config_compute_extended);
>> + return mux_config_compute_extended;
> It looks like your script doesn't properly handle the unconditional mux
> config here.
Very well spotted!
This is a pretty ambiguous case and I'm not entirely sure what the
right thing to do here is and have asked the folks that came up with
the original OA config for their feedback. I *think* in this case it's
supposed to combine both as if the unconditional config were logically
concatenated at the end of all the conditional configs.
Locally I've at least updated the i915-perf-kernelgen.py script to
print a loud warning out for this so I could double check in case
there were other similar cases I'd missed - this BDW config seems to
be the only one with this ambiguity though. This makes me think that I
should update the mdapi-xml-convert.py script to just hide this
special case from our oa-*.xml file by explicitly concatenating with
the conditional configs if that's appropriate - then we don't need to
support multiple NOA configs in the i915 perf implementation. The
scripts can then have strict assertions that this doesn't change in
the future.
>
> <SNIP>
>
>> +
>> +static const struct i915_oa_reg *
>> +get_test_oa_mux_config(struct drm_i915_private *dev_priv,
>> + int *len)
>> +{
>> + *len = ARRAY_SIZE(mux_config_test_oa);
>> + return mux_config_test_oa;
>> +}
>> +
>> +int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
>> +{
>> + dev_priv->perf.oa.mux_regs = NULL;
>> + dev_priv->perf.oa.mux_regs_len = 0;
>> + dev_priv->perf.oa.b_counter_regs = NULL;
>> + dev_priv->perf.oa.b_counter_regs_len = 0;
>> + dev_priv->perf.oa.flex_regs = NULL;
>> + dev_priv->perf.oa.flex_regs_len = 0;
>> +
>> + switch (dev_priv->perf.oa.metrics_set) {
>> + case METRIC_SET_ID_RENDER_BASIC:
>> + dev_priv->perf.oa.mux_regs =
>> + get_render_basic_mux_config(dev_priv,
>> + &dev_priv->perf.oa.mux_regs_len);
>> + if (!dev_priv->perf.oa.mux_regs) {
>> + DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
> Your script also needs to output a newline for DRM_DEBUG_DRIVER.
Ah yep, fixed locally thanks,
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers
2017-02-23 15:35 ` Chris Wilson
@ 2017-03-23 16:43 ` Robert Bragg
0 siblings, 0 replies; 12+ messages in thread
From: Robert Bragg @ 2017-03-23 16:43 UTC (permalink / raw)
To: Chris Wilson, Robert Bragg, Intel Graphics Development
On Thu, Feb 23, 2017 at 3:35 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Wed, Feb 22, 2017 at 04:36:31PM +0000, Robert Bragg wrote:
>> Since the exponent for periodic OA counter sampling is maintained in a
>> per-context register while we want to treat it as if it were global
>> state we need to be able to safely issue an mmio write to a per-context
>> register and affect any currently running context.
>>
>> We have to take some extra care in this case and this adds a utility
>> api to encapsulate what's required.
>
> Been waying up the pros/cons of having this in uncore. It doesn't
> attempt to be generic nor replace the existing instance, so atm I think
> it might be better as local to i915_perf.
Thanks. Can you maybe clarify for me what "the existing instance"
that's not replaced is in this context?
>
>> Signed-off-by: Robert Bragg <robert@sixbynine.org>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 4 ++
>> drivers/gpu/drm/i915/i915_reg.h | 3 ++
>> drivers/gpu/drm/i915/intel_uncore.c | 73 +++++++++++++++++++++++++++++++++++++
>> 3 files changed, 80 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 105b97bd34d7..c8d03a2e89cc 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -718,6 +718,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>> i915_reg_t reg, unsigned int op);
>>
>> struct intel_uncore_funcs {
>> + int (*wait_for_rcs_busy)(struct drm_i915_private *dev_priv);
>> void (*force_wake_get)(struct drm_i915_private *dev_priv,
>> enum forcewake_domains domains);
>> void (*force_wake_put)(struct drm_i915_private *dev_priv,
>> @@ -751,6 +752,7 @@ struct intel_uncore {
>>
>> struct intel_uncore_funcs funcs;
>>
>> + atomic_t hold_rcs_busy_count;
>> unsigned fifo_count;
>>
>> enum forcewake_domains fw_domains;
>> @@ -3139,6 +3141,8 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
>> {
>> return dev_priv->vgpu.active;
>> }
>> +int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv);
>> +void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv);
>>
>> void
>> i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 141a5c1e3895..94d40e82edc1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2313,6 +2313,9 @@ enum skl_disp_power_wells {
>> #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
>> #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
>>
>> +#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
>> +#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
>> +
>> /* Fuse readout registers for GT */
>> #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
>> #define CHV_FGT_DISABLE_SS0 (1 << 10)
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 441c51fd9746..06bfe5f89ac5 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -1274,6 +1274,16 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>> WARN_ON(dev_priv->uncore.fw_domains == 0);
>> }
>>
>> +static int gen8_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
>> +{
>> + return wait_for((I915_READ(GEN6_RCS_PWR_FSM) & 0x3f) == 0x30, 50);
>> +}
>> +
>> +static int gen9_wait_for_rcs_busy(struct drm_i915_private *dev_priv)
>> +{
>> + return wait_for((I915_READ(GEN9_RCS_FE_FSM2) & 0x3f) == 0x30, 50);
>> +}
>> +
>> #define ASSIGN_FW_DOMAINS_TABLE(d) \
>> { \
>> dev_priv->uncore.fw_domains_table = \
>> @@ -1305,6 +1315,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
>> dev_priv->uncore.funcs.mmio_writel =
>> gen9_decoupled_write32;
>> }
>> + dev_priv->uncore.funcs.wait_for_rcs_busy =
>> + gen9_wait_for_rcs_busy;
>> break;
>> case 8:
>> if (IS_CHERRYVIEW(dev_priv)) {
>> @@ -1316,6 +1328,8 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
>> ASSIGN_WRITE_MMIO_VFUNCS(gen8);
>> ASSIGN_READ_MMIO_VFUNCS(gen6);
>> }
>> + dev_priv->uncore.funcs.wait_for_rcs_busy =
>> + gen8_wait_for_rcs_busy;
>> break;
>> case 7:
>> case 6:
>> @@ -1858,6 +1872,65 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>> return fw_domains;
>> }
>>
>> +static int hold_rcs_busy(struct drm_i915_private *dev_priv)
>> +{
>> + int ret = 0;
>> +
>> + if (atomic_inc_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
>> + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
>> + _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>> +
>> + ret = dev_priv->uncore.funcs.wait_for_rcs_busy(dev_priv);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void release_rcs_busy(struct drm_i915_private *dev_priv)
>> +{
>> + if (!atomic_dec_and_test(&dev_priv->uncore.hold_rcs_busy_count)) {
>> + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
>> + _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
>> + }
>
> atomic_inc_and_test is correct, but atomic_dec_and_test is backwards.
Hmm, it's not the mirror and the first is wrong too, sorry I clearly
didn't verify this - though I vaguely recall explicitly testing the
behaviour of the wait_for_rcs_busy at some point in the past :-/
atomic_inc_and_test() is equivalent to (atomic_inc_return(v) == 0) and
atomic_inc_return() evaluates to the post-increment value. The
intention here is to only explicitly wait when the rcs_busy_count
changes from zero to one, but the first atomic_inc_and_test will fail
for that transition and then pass for each subsequent nested
hold_rcs_busy(). The second atomic_dec_and_test() check would have
been ok without that misplaced negation :-/
Adding some printk debugging to this implementation as is and then
nesting hold/release_rcs_busy() calls like:
hold_rcs_busy();
hold_rcs_busy();
release_rcs_busy();
release_rcs_busy();
I got this incorrect output:
[ 205.747836] Skipping redundant wake up for per-ctx mmio
[ 205.747840] Skipping redundant wake up for per-ctx mmio
[ 205.747844] Explicitly relinquishing wake up hold for per-ctx mmio
[ 205.747845] Not relinquishing hold for per-ctx mmio yet
Looking at this again, I think I now prefer avoiding these _and_test
macros() and instead having something like:
+if (atomic_dec_return(&dev_priv->uncore.hold_rcs_busy_count) == 0) {
I believe this fixes the ref counting control flow here:
+static int hold_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ int ret = 0;
+
+ /* Only explicitly enact a hold if it's not already being held */
+ if (atomic_inc_return(&dev_priv->uncore.hold_rcs_busy_count) == 1) {
+ I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+
+ /* If waiting didn't succeed, decrement counter to allow retries */
+ ret = dev_priv->uncore.funcs.wait_for_rcs_busy(dev_priv);
+ if (ret)
+ atomic_dec(&dev_priv->uncore.hold_rcs_busy_count);
+ }
+
+ return ret;
+}
+
+static void release_rcs_busy(struct drm_i915_private *dev_priv)
+{
+ /* Only drop the hold if nothing else needs it */
+ if (atomic_dec_return(&dev_priv->uncore.hold_rcs_busy_count) == 0) {
+ I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+ }
+}
With the same kind of prink debugging with nested calls, I double
checked I got the expected output of:
[ 68.375183] Explicitly waiting for wake up for per-ctx mmio
[ 68.375190] Skipping redundant wake up for per-ctx mmio
[ 68.375196] Not relinquishing hold for per-ctx mmio yet
[ 68.375197] Explicitly relinquishing wake up hold for per-ctx mmio
> Besides if you just extend the irq spinlock slightly, you get:
>
> +int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv)
> +{
> + unsigned long flags;
> + i915_reg_t reg;
> + int ret;
> +
> + if (INTEL_GEN(dev_priv) < 8)
> + return 0;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> + __intel_uncore_forcewake_get(dev_priv, FORCEWAKE_RENDER);
> +
> + if (!dev_priv->uncore.rcs_hold_count++)
> + I915_WRITE_FW(GEN6_RC_SLEEP_PSMI_CONTROL,
> + _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
> +
> + if (INTEL_GEN(dev_priv) == 8)
> + reg = GEN6_RCS_PWR_FSM;
> + else
> + reg = GEN9_RCS_FE_FSM2;
> +
> + ret = wait_for_atomic((__raw_i915_read32(dev_priv, reg) & 0x3f) == 0x30,
> + 50);
> + if (ret)
> + __intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> +
> + return ret;
> +}
Thanks for writing this out.
With regards to your earlier comment about not being general/replacing
the existing instance, would the same still apply to something along
these lines - or you'd still suggest something along these lines would
live in i915_perf.c?
I have a couple of concerns about this atm:
I don't really know what kind of worst case latencies to expect while
waiting for the _FSM status, which makes me wonder about the
repercussions of taking the uncore.lock and updating the
implementation to be able to run in atomic context. I'd be a little
worried an OA configuration ioctl might end up blocking something much
more important.
For i915_perf.c we currently only ever need to set these while in
process context.
Another issue with my previous code, carried over here is not dropping
the rcs_hold_count if the wait_for fails.
> +
> +void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv)
> +{
> + unsigned long flags;
> +
> + if (INTEL_GEN(dev_priv) < 8)
> + return;
> +
> + spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> +
> + if (!--dev_priv->uncore.rcs_hold_count)
> + I915_WRITE_FW(GEN6_RC_SLEEP_PSMI_CONTROL,
> + _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
> + __intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
> +
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> +}
>
> Note as well you need to think about serialising the wakeup, not just
> the hold count.
Hmm, right, if there were an overlapping _begin_ctx_mmio it could
quite possibly return (before the wake up completes) with no error
just because something else initiated a begin_ctx_mmio.
I think at this point, if I just put something specific to i915 perf
into i915_perf.c then the requirements become so much simpler.
Considering i915 perf is currently the only drm/i915 code needing to
do this, then in this case we also only ever need to do this from
process context from a single non-reentrant ioctl.
Thanks for looking at this,
- Robert
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-03-23 16:44 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-22 16:36 [PATCH 0/6] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
2017-02-22 16:36 ` [PATCH 1/6] drm/i915: expose _SLICE_MASK GETPARM Robert Bragg
2017-02-22 16:36 ` [PATCH 2/6] drm/i915: expose _SUBSLICE_MASK GETPARM Robert Bragg
2017-02-22 16:36 ` [PATCH 3/6] drm/i915: Add uncore mmio api for per-context registers Robert Bragg
2017-02-23 15:35 ` Chris Wilson
2017-03-23 16:43 ` Robert Bragg
2017-02-22 16:36 ` [PATCH 4/6] drm/i915: Add 'render basic' Gen8+ OA unit configs Robert Bragg
2017-02-22 16:36 ` [PATCH 5/6] drm/i915: Add OA unit support for Gen 8+ Robert Bragg
2017-02-22 16:36 ` [PATCH 6/6] drm/i915: Add more OA configs for BDW, CHV, SKL + BXT Robert Bragg
2017-03-01 13:00 ` Matthew Auld
2017-03-20 16:34 ` Robert Bragg
2017-02-22 19:22 ` ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf Patchwork
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