[PATCH 00/27] DC Patches Mar 8, 2017

[PATCH 00/27] DC Patches Mar 8, 2017

[Harry Wentland]

* Use atomic helpers for commit, suspend/resume, and gamma
* Whole bunch of fixes
* Updated scaler calculations

Amy Zhang (1):
  drm/amd/display: Simplify some DMCU waits

Andrey Grodzovsky (4):
  drm/amd/display: Refactor atomic commit implementation. (v2)
  drm/amd/display: Refactor headless to use atomic commit.
  drm/amd/display: Remove page_fleep_needed function.
  drm/amd/display: Switch to DRM helpers in s3.

Charlene Liu (6):
  drm/amd/display: freesync pipe split :VTotal_Min_Mask for Hflip/lock.
  drm/amd/display: extended the programming sequence to VFlip as well
  drm/amd/display: sometime VtotalMin less than VTotal (rounding issue)
  drm/amd/display: refclock from bios firmwareInfoTable
  drm/amd/display: move refclk from dc to resource_pool
  drm/amd/display: TPS4 logic typo fix

Dmytro Laktyushkin (4):
  drm/amd/display: add init calculation to scaler params
  drm/amd/display: fix hsplit viewport calculation for rotated/mirrored
    usecases
  drm/amd/display: fix viewport adjustment on rotated surface
  drm/amd/display: fix incorrect vp adjustment

Harry Wentland (4):
  drm/amd/display: Use amdgpu mode funcs statically
  drm/amd/display: Use atomic helpers for gamma
  drm/amd/display: Remove unused define from amdgpu_dm_types
  drm/amd/display: We don't support interlace and doublescan

Jordan Lazare (1):
  drm/amd/display: Less log spam

Leon Elazar (2):
  drm/amd/display: Adding FastUpdate functionality
  drm/amd/display: Memory leak fix during disable

Tony Cheng (2):
  drm/amd/display: clean up and simply locking logic
  drm/amd/display: remove independent lock as we have no use case today

Yongqiang Sun (2):
  drm/amd/display: After program backend, also program front end regs.
  drm/amd/display: Do not copy bottom pipe when map resource.

Zeyu Fan (1):
  drm/amd/display: Refactor on dc_sink structure.

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 223 ++-----
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |   5 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 639 ++++++++-------------
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h    |  12 +-
 drivers/gpu/drm/amd/display/dc/basics/logger.c     |   4 +-
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 213 ++++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |   9 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 391 ++++++++++---
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c      |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |   2 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |  17 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c     |   4 +-
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |  17 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c    |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h    |   1 -
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c      |  46 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c     |  37 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     |  16 +-
 .../drm/amd/display/dc/dce/dce_stream_encoder.c    |   4 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |   1 +
 drivers/gpu/drm/amd/display/dc/inc/core_dc.h       |   4 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |  11 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  21 +-
 drivers/gpu/drm/amd/display/dc/inc/resource.h      |   4 +-
 .../drm/amd/display/include/hw_sequencer_types.h   |   1 +
 drivers/gpu/drm/amd/display/include/logger_types.h |   1 +
 .../drm/amd/display/modules/freesync/freesync.c    |  12 +-
 30 files changed, 862 insertions(+), 847 deletions(-)

-- 
2.10.2

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[PATCH 01/27] drm/amd/display: Use amdgpu mode funcs statically

[Harry Wentland]

No need to assign them dynamically. This is much more readable.

Change-Id: I2d8a356e8d916800c4553c4e9b19ce42f7f1c391
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 29d1900bc650..fe5bf0472c23 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -28,6 +28,7 @@
 
 #include "vid.h"
 #include "amdgpu.h"
+#include "amdgpu_display.h"
 #include "atom.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_types.h"
@@ -721,6 +722,8 @@ const struct amdgpu_ip_block_version dm_ip_block =
 
 /* TODO: it is temporary non-const, should fixed later */
 static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
+	.fb_create = amdgpu_user_framebuffer_create,
+	.output_poll_changed = amdgpu_output_poll_changed,
 	.atomic_check = amdgpu_dm_atomic_check,
 	.atomic_commit = amdgpu_dm_atomic_commit
 };
@@ -1094,11 +1097,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 
 	adev->mode_info.mode_config_initialized = true;
 
-	amdgpu_dm_mode_funcs.fb_create =
-		amdgpu_mode_funcs.fb_create;
-	amdgpu_dm_mode_funcs.output_poll_changed =
-		amdgpu_mode_funcs.output_poll_changed;
-
 	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
 
 	adev->ddev->mode_config.max_width = 16384;
-- 
2.10.2

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[PATCH 02/27] drm/amd/display: Use atomic helpers for gamma

[Harry Wentland]

We were using set_properties and gamma in a weird way.
This change aligns the properties with other drivers
and allows us to remove a private gamma flag and reuse
atomic helpers for most of this.

Change-Id: Ic74b692ee6c6d3e4fd938c6226e65b54075ff983
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 89 +++++-----------------
 1 file changed, 21 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index d0b855abd665..d25116888348 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -61,7 +61,6 @@ struct dm_connector_state {
 #define to_dm_connector_state(x)\
 	container_of((x), struct dm_connector_state, base)
 
-#define AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET 1
 
 void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 {
@@ -551,23 +550,18 @@ static void fill_gamma_from_crtc(
 {
 	int i;
 	struct dc_gamma *gamma;
-	uint16_t *red, *green, *blue;
-	int end = (crtc->gamma_size > NUM_OF_RAW_GAMMA_RAMP_RGB_256) ?
-			NUM_OF_RAW_GAMMA_RAMP_RGB_256 : crtc->gamma_size;
-
-	red = crtc->gamma_store;
-	green = red + crtc->gamma_size;
-	blue = green + crtc->gamma_size;
+	struct drm_crtc_state *state = crtc->state;
+	struct drm_color_lut *lut = (struct drm_color_lut *) state->gamma_lut->data;
 
 	gamma = dc_create_gamma();
 
 	if (gamma == NULL)
 		return;
 
-	for (i = 0; i < end; i++) {
-		gamma->red[i] = (unsigned short) red[i];
-		gamma->green[i] = (unsigned short) green[i];
-		gamma->blue[i] = (unsigned short) blue[i];
+	for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
+		gamma->red[i] = lut[i].red;
+		gamma->green[i] = lut[i].green;
+		gamma->blue[i] = lut[i].blue;
 	}
 
 	dc_surface->gamma_correction = gamma;
@@ -601,8 +595,7 @@ static void fill_plane_attributes(
 	surface->in_transfer_func = input_tf;
 
 	/* In case of gamma set, update gamma value */
-	if (crtc->mode.private_flags &
-		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
+	if (state->crtc->state->gamma_lut) {
 		fill_gamma_from_crtc(crtc, surface);
 	}
 }
@@ -719,12 +712,6 @@ static void dm_dc_surface_commit(
 			dc_surface,
 			crtc->primary->state,
 			true);
-	if (crtc->mode.private_flags &
-		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-		/* reset trigger of gamma */
-		crtc->mode.private_flags &=
-			~AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-	}
 
 	dc_surfaces[0] = dc_surface;
 
@@ -1049,50 +1036,6 @@ void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
 	kfree(crtc);
 }
 
-static int amdgpu_dm_atomic_crtc_gamma_set(
-		struct drm_crtc *crtc,
-		u16 *red,
-		u16 *green,
-		u16 *blue,
-		uint32_t size)
-{
-	struct drm_device *dev = crtc->dev;
-	struct drm_property *prop = dev->mode_config.prop_crtc_id;
-
-	crtc->state->mode.private_flags |= AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET;
-
-	return drm_atomic_helper_crtc_set_property(crtc, prop, 0);
-}
-
-static int dm_crtc_funcs_atomic_set_property(
-	struct drm_crtc *crtc,
-	struct drm_crtc_state *crtc_state,
-	struct drm_property *property,
-	uint64_t val)
-{
-	struct drm_plane_state *plane_state;
-
-	crtc_state->planes_changed = true;
-
-	/*
-	 * Bit of magic done here. We need to ensure
-	 * that planes get update after mode is set.
-	 * So, we need to add primary plane to state,
-	 * and this way atomic_update would be called
-	 * for it
-	 */
-	plane_state =
-		drm_atomic_get_plane_state(
-			crtc_state->state,
-			crtc->primary);
-
-	if (!plane_state)
-		return -EINVAL;
-
-	return 0;
-}
-
-
 static int amdgpu_atomic_helper_page_flip(struct drm_crtc *crtc,
 				struct drm_framebuffer *fb,
 				struct drm_pending_vblank_event *event,
@@ -1178,12 +1121,12 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 	.cursor_set = dm_crtc_cursor_set,
 	.cursor_move = dm_crtc_cursor_move,
 	.destroy = amdgpu_dm_crtc_destroy,
-	.gamma_set = amdgpu_dm_atomic_crtc_gamma_set,
+	.gamma_set = drm_atomic_helper_legacy_gamma_set,
 	.set_config = drm_atomic_helper_set_config,
+	.set_property = drm_atomic_helper_crtc_set_property,
 	.page_flip = amdgpu_atomic_helper_page_flip,
 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
-	.atomic_set_property = dm_crtc_funcs_atomic_set_property
 };
 
 static enum drm_connector_status
@@ -2753,8 +2696,7 @@ int amdgpu_dm_atomic_commit(
 		struct dm_connector_state *dm_state = NULL;
 		enum dm_commit_action action;
 
-		if (!fb || !crtc || !crtc->state->planes_changed ||
-			!crtc->state->active)
+		if (!fb || !crtc || !crtc->state->active)
 			continue;
 
 		action = get_dm_commit_action(crtc->state);
@@ -3188,6 +3130,17 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			}
 			break;
 		}
+
+		/*
+		 * TODO revisit when removing commit action
+		 * and looking at atomic flags directly
+		 */
+
+		/* commit needs planes right now (for gamma, eg.) */
+		/* TODO rework commit to chack crtc for gamma change */
+		ret = drm_atomic_add_affected_planes(state, crtc);
+		if (ret)
+			return ret;
 	}
 
 	for (i = 0; i < set_count; i++) {
-- 
2.10.2

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[PATCH 03/27] drm/amd/display: Remove unused define from amdgpu_dm_types

[Harry Wentland]

Change-Id: Idfd0d0d6e537eddbc75378ba394b0f36bd89dd50
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 6ed1480a8bc3..4faa1659f7f9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -59,11 +59,6 @@ int amdgpu_dm_atomic_commit(
 int amdgpu_dm_atomic_check(struct drm_device *dev,
 				struct drm_atomic_state *state);
 
-int dm_create_validation_set_for_stream(
-	struct drm_connector *connector,
-	struct drm_display_mode *mode,
-	struct dc_validation_set *val_set);
-
 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
 struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
 	struct drm_connector *connector);
-- 
2.10.2

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[PATCH 04/27] drm/amd/display: freesync pipe split :VTotal_Min_Mask for Hflip/lock.

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: Icb5d285ed455e7081f88cd09df3845c08f7ceb20
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 40 +++++++++++++++-------
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c     | 21 +++++++-----
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 15 ++------
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  | 20 ++++++++---
 .../drm/amd/display/include/hw_sequencer_types.h   |  1 +
 5 files changed, 59 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 852932aec436..66a5b2745501 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1178,6 +1178,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 	enum surface_update_type update_type;
 	const struct dc_stream_status *stream_status;
+	unsigned int lock_mask = 0;
 
 	stream_status = dc_stream_get_status(dc_stream);
 	ASSERT(stream_status);
@@ -1315,21 +1316,38 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+			if (pipe_ctx->surface != surface)
+				continue;
+			/*lock all the MCPP if blnd is enable for DRR*/
+			if ((update_type == UPDATE_TYPE_FAST &&
+					(dc_stream->freesync_ctx.enabled == true &&
+							surface_count != context->res_ctx.pool->pipe_count)) &&
+					!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
+				lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR;
+				core_dc->hwss.pipe_control_lock(
+						core_dc,
+						pipe_ctx,
+						lock_mask,
+						true);
+				}
+			}
+		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 			struct pipe_ctx *cur_pipe_ctx;
 			bool is_new_pipe_surface = true;
 
 			if (pipe_ctx->surface != surface)
 				continue;
-
 			if (update_type != UPDATE_TYPE_FAST &&
 				!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-				core_dc->hwss.pipe_control_lock(
-						core_dc->hwseq,
-						pipe_ctx->pipe_idx,
-						PIPE_LOCK_CONTROL_GRAPHICS |
+				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
 						PIPE_LOCK_CONTROL_SCL |
 						PIPE_LOCK_CONTROL_BLENDER |
-						PIPE_LOCK_CONTROL_MODE,
+						PIPE_LOCK_CONTROL_MODE;
+				core_dc->hwss.pipe_control_lock(
+						core_dc,
+						pipe_ctx,
+						lock_mask,
 						true);
 			}
 
@@ -1371,7 +1389,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		}
 	}
 
-	if (update_type == UPDATE_TYPE_FAST)
+	if (update_type == UPDATE_TYPE_FAST && (lock_mask == 0))
 		return;
 
 	for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
@@ -1381,11 +1399,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 			if (updates[j].surface == &pipe_ctx->surface->public) {
 				if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 					core_dc->hwss.pipe_control_lock(
-							core_dc->hwseq,
-							pipe_ctx->pipe_idx,
-							PIPE_LOCK_CONTROL_GRAPHICS |
-							PIPE_LOCK_CONTROL_SCL |
-							PIPE_LOCK_CONTROL_BLENDER,
+							core_dc,
+							pipe_ctx,
+							lock_mask,
 							false);
 				}
 				break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 8eb755620c48..1e1d60af8306 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -26,6 +26,7 @@
 #include "dce_hwseq.h"
 #include "reg_helper.h"
 #include "hw_sequencer.h"
+#include "core_dc.h"
 
 #define CTX \
 	hws->ctx
@@ -43,15 +44,17 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
 			DCFE_CLOCK_ENABLE, enable);
 }
 
-void dce_pipe_control_lock(struct dce_hwseq *hws,
-		unsigned int blnd_inst,
+void dce_pipe_control_lock(struct core_dc *dc,
+		struct pipe_ctx *pipe,
 		enum pipe_lock_control control_mask,
 		bool lock)
 {
 	uint32_t lock_val = lock ? 1 : 0;
-	uint32_t dcp_grph, scl, blnd, update_lock_mode;
-
-	uint32_t val = REG_GET_4(BLND_V_UPDATE_LOCK[blnd_inst],
+	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
+	struct dce_hwseq *hws = dc->hwseq;
+	if (control_mask & PIPE_LOCK_CONTROL_MPCC_ADDR)
+		return;
+	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
 			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
 			BLND_SCL_V_UPDATE_LOCK, &scl,
 			BLND_BLND_V_UPDATE_LOCK, &blnd,
@@ -70,19 +73,19 @@ void dce_pipe_control_lock(struct dce_hwseq *hws,
 		update_lock_mode = lock_val;
 
 
-	REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val,
+	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
 			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
 			BLND_SCL_V_UPDATE_LOCK, scl);
 
 	if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
-		REG_SET_2(BLND_V_UPDATE_LOCK[blnd_inst], val,
+		REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
 				BLND_BLND_V_UPDATE_LOCK, blnd,
 				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
 
 	if (hws->wa.blnd_crtc_trigger) {
 		if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
-			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]);
-			REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value);
+			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
+			REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 4af8d560a7ee..9ef618443255 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -212,17 +212,6 @@ struct dce_hwseq_mask {
 	HWSEQ_REG_FIED_LIST(uint32_t)
 };
 
-struct dce_hwseq_wa {
-	bool blnd_crtc_trigger;
-};
-
-struct dce_hwseq {
-	struct dc_context *ctx;
-	const struct dce_hwseq_registers *regs;
-	const struct dce_hwseq_shift *shifts;
-	const struct dce_hwseq_mask *masks;
-	struct dce_hwseq_wa wa;
-};
 
 enum blnd_mode {
 	BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
@@ -233,8 +222,8 @@ enum blnd_mode {
 void dce_enable_fe_clock(struct dce_hwseq *hwss,
 		unsigned int inst, bool enable);
 
-void dce_pipe_control_lock(struct dce_hwseq *hws,
-		unsigned int blnd_inst,
+void dce_pipe_control_lock(struct core_dc *dc,
+		struct pipe_ctx *pipe,
 		enum pipe_lock_control control_mask,
 		bool lock);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7b780c610631..a902de52107f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -38,10 +38,22 @@ enum pipe_lock_control {
 	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
 	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
 	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-	PIPE_LOCK_CONTROL_MODE = 1 << 3
+	PIPE_LOCK_CONTROL_MODE = 1 << 3,
+	PIPE_LOCK_CONTROL_MPCC_ADDR = 1 << 4
+};
+
+struct dce_hwseq_wa {
+	bool blnd_crtc_trigger;
+};
+
+struct dce_hwseq {
+	struct dc_context *ctx;
+	const struct dce_hwseq_registers *regs;
+	const struct dce_hwseq_shift *shifts;
+	const struct dce_hwseq_mask *masks;
+	struct dce_hwseq_wa wa;
 };
 
-struct dce_hwseq;
 
 struct hw_sequencer_funcs {
 
@@ -115,8 +127,8 @@ struct hw_sequencer_funcs {
 			struct dc_link_settings *link_settings);
 
 	void (*pipe_control_lock)(
-				struct dce_hwseq *hwseq,
-				unsigned int blnd_inst,
+				struct core_dc *dc,
+				struct pipe_ctx *pipe,
 				enum pipe_lock_control control_mask,
 				bool lock);
 
diff --git a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
index 6f0475c25566..065a91a7002f 100644
--- a/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
+++ b/drivers/gpu/drm/amd/display/include/hw_sequencer_types.h
@@ -38,6 +38,7 @@ struct drr_params {
 	/* defines the maximum possible vertical dimension of display timing
 	 * for CRTC as supported by the panel */
 	uint32_t vertical_total_max;
+    bool immediate_flip;
 };
 
 #endif
-- 
2.10.2

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[PATCH 05/27] drm/amd/display: We don't support interlace and doublescan

[Harry Wentland]

Don't tell DRM otherwise.

Change-Id: I6c01701b3be35cb5badf236459ee5d9a1ab8c309
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index d25116888348..0bf88d86e7a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2014,8 +2014,9 @@ void amdgpu_dm_connector_init_helper(
 
 	aconnector->connector_id = link_index;
 	aconnector->dc_link = link;
-	aconnector->base.interlace_allowed = true;
-	aconnector->base.doublescan_allowed = true;
+	aconnector->base.interlace_allowed = false;
+	aconnector->base.doublescan_allowed = false;
+	aconnector->base.stereo_allowed = false;
 	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
 	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
 
-- 
2.10.2

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[PATCH 06/27] drm/amd/display: extended the programming sequence to VFlip as well

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: Iccf6c436dc0807f4d5e0ce96ae1e64ed31c20a38
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 66a5b2745501..efe50fd2be78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1316,6 +1316,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+			struct pipe_ctx *cur_pipe_ctx;
+			bool is_new_pipe_surface = true;
+
 			if (pipe_ctx->surface != surface)
 				continue;
 			/*lock all the MCPP if blnd is enable for DRR*/
@@ -1324,26 +1327,16 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 							surface_count != context->res_ctx.pool->pipe_count)) &&
 					!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 				lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR;
-				core_dc->hwss.pipe_control_lock(
-						core_dc,
-						pipe_ctx,
-						lock_mask,
-						true);
-				}
 			}
-		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-			struct pipe_ctx *cur_pipe_ctx;
-			bool is_new_pipe_surface = true;
 
-			if (pipe_ctx->surface != surface)
-				continue;
 			if (update_type != UPDATE_TYPE_FAST &&
 				!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
 						PIPE_LOCK_CONTROL_SCL |
 						PIPE_LOCK_CONTROL_BLENDER |
 						PIPE_LOCK_CONTROL_MODE;
+			}
+			if (lock_mask != 0) {
 				core_dc->hwss.pipe_control_lock(
 						core_dc,
 						pipe_ctx,
@@ -1389,7 +1382,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		}
 	}
 
-	if (update_type == UPDATE_TYPE_FAST && (lock_mask == 0))
+	if ((update_type == UPDATE_TYPE_FAST) && lock_mask == 0)
 		return;
 
 	for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
-- 
2.10.2

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[PATCH 07/27] drm/amd/display: Refactor atomic commit implementation. (v2)

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Modify amdgpu_dm_atomic_comit to implement
atomic_comit_tail hook.
Unify Buffer objects allocation and dealocation
for surface updates and page flips.
Simplify wait for fences and target_vbank logic
for non blockiing commit.
Remove hacky update surface to page flip synchronization
we had and rely on atomic framework synchronization logic.

v2:
Add state->allow_modeset as indicator of page flip call.

Change-Id: I23a01d2744b9f75d4e534a95e586d64de47ca32c
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  58 +++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 343 ++++++++++-----------
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h    |   7 +-
 3 files changed, 203 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fe5bf0472c23..201c97e1485e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -155,7 +155,6 @@ static struct amdgpu_crtc *get_crtc_by_otg_inst(
 
 static void dm_pflip_high_irq(void *interrupt_params)
 {
-	struct amdgpu_flip_work *works;
 	struct amdgpu_crtc *amdgpu_crtc;
 	struct common_irq_params *irq_params = interrupt_params;
 	struct amdgpu_device *adev = irq_params->adev;
@@ -171,7 +170,6 @@ static void dm_pflip_high_irq(void *interrupt_params)
 	}
 
 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
-	works = amdgpu_crtc->pflip_works;
 
 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
@@ -183,22 +181,24 @@ static void dm_pflip_high_irq(void *interrupt_params)
 		return;
 	}
 
-	/* page flip completed. clean up */
-	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
-	amdgpu_crtc->pflip_works = NULL;
 
 	/* wakeup usersapce */
-	if (works->event)
-		drm_crtc_send_vblank_event(&amdgpu_crtc->base,
-					   works->event);
+	if (amdgpu_crtc->event
+			&& amdgpu_crtc->event->event.base.type
+			== DRM_EVENT_FLIP_COMPLETE) {
+		drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
+		/* page flip completed. clean up */
+		amdgpu_crtc->event = NULL;
+	} else
+		WARN_ON(1);
 
+	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
-	DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE, work: %p,\n",
-					__func__, amdgpu_crtc->crtc_id, amdgpu_crtc, works);
+	DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
+					__func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 
 	drm_crtc_vblank_put(&amdgpu_crtc->base);
-	schedule_work(&works->unpin_work);
 }
 
 static void dm_crtc_high_irq(void *interrupt_params)
@@ -725,7 +725,11 @@ static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 	.fb_create = amdgpu_user_framebuffer_create,
 	.output_poll_changed = amdgpu_output_poll_changed,
 	.atomic_check = amdgpu_dm_atomic_check,
-	.atomic_commit = amdgpu_dm_atomic_commit
+	.atomic_commit = drm_atomic_helper_commit
+};
+
+static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
+	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 };
 
 void amdgpu_dm_update_connector_after_detect(
@@ -1098,6 +1102,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 	adev->mode_info.mode_config_initialized = true;
 
 	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
+	adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
 
 	adev->ddev->mode_config.max_width = 16384;
 	adev->ddev->mode_config.max_height = 16384;
@@ -1351,6 +1356,14 @@ static void dm_page_flip(struct amdgpu_device *adev,
 	acrtc = adev->mode_info.crtcs[crtc_id];
 	stream = acrtc->stream;
 
+
+	if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
+		DRM_ERROR("flip queue: acrtc %d, already busy\n", acrtc->crtc_id);
+		/* In commit tail framework this cannot happen */
+		BUG_ON(0);
+	}
+
+
 	/*
 	 * Received a page flip call after the display has been reset.
 	 * Just return in this case. Everything should be clean-up on reset.
@@ -1365,15 +1378,28 @@ static void dm_page_flip(struct amdgpu_device *adev,
 	addr.address.grph.addr.high_part = upper_32_bits(crtc_base);
 	addr.flip_immediate = async;
 
+
+	if (acrtc->base.state->event &&
+	    acrtc->base.state->event->event.base.type ==
+			    DRM_EVENT_FLIP_COMPLETE) {
+		acrtc->event = acrtc->base.state->event;
+
+		/* Set the flip status */
+		acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
+
+		/* Mark this event as consumed */
+		acrtc->base.state->event = NULL;
+	}
+
+	dc_flip_surface_addrs(adev->dm.dc,
+			      dc_stream_get_status(stream)->surfaces,
+			      &addr, 1);
+
 	DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
 			 __func__,
 			 addr.address.grph.addr.high_part,
 			 addr.address.grph.addr.low_part);
 
-	dc_flip_surface_addrs(
-			adev->dm.dc,
-			dc_stream_get_status(stream)->surfaces,
-			&addr, 1);
 }
 
 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 0bf88d86e7a0..7e762aac07ac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -686,8 +686,18 @@ static void dm_dc_surface_commit(
 {
 	struct dc_surface *dc_surface;
 	const struct dc_surface *dc_surfaces[1];
-	const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 	const struct dc_stream *dc_stream = acrtc->stream;
+	unsigned long flags;
+
+	spin_lock_irqsave(&crtc->dev->event_lock, flags);
+	if (acrtc->pflip_status != AMDGPU_FLIP_NONE) {
+		DRM_ERROR("dm_dc_surface_commit: acrtc %d, already busy\n", acrtc->crtc_id);
+		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+		/* In comit tail framework this cannot happen */
+		BUG_ON(0);
+	}
+	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 
 	if (!dc_stream) {
 		dm_error(
@@ -1591,6 +1601,7 @@ static void clear_unrelated_fields(struct drm_plane_state *state)
 	state->fence = NULL;
 }
 
+/*TODO update because event is always present now */
 static bool page_flip_needed(
 	const struct drm_plane_state *new_state,
 	const struct drm_plane_state *old_state,
@@ -1646,11 +1657,13 @@ static bool page_flip_needed(
 	page_flip_required = memcmp(&old_state_tmp,
 				    &new_state_tmp,
 				    sizeof(old_state_tmp)) == 0 ? true:false;
+
 	if (new_state->crtc && page_flip_required == false) {
 		acrtc_new = to_amdgpu_crtc(new_state->crtc);
 		if (acrtc_new->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
 			page_flip_required = true;
 	}
+
 	return page_flip_required;
 }
 
@@ -1676,7 +1689,7 @@ static int dm_plane_helper_prepare_fb(
 	if (unlikely(r != 0))
 		return r;
 
-	r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
+	r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
 
 	amdgpu_bo_unreserve(rbo);
 
@@ -1685,6 +1698,7 @@ static int dm_plane_helper_prepare_fb(
 		return r;
 	}
 
+	amdgpu_bo_ref(rbo);
 	return 0;
 }
 
@@ -1708,7 +1722,10 @@ static void dm_plane_helper_cleanup_fb(
 	} else {
 		amdgpu_bo_unpin(rbo);
 		amdgpu_bo_unreserve(rbo);
+		amdgpu_bo_unref(&rbo);
 	}
+
+	afb->address = 0;
 }
 
 int dm_create_validation_set_for_connector(struct drm_connector *connector,
@@ -2306,51 +2323,6 @@ static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state)
 	}
 }
 
-
-typedef bool (*predicate)(struct amdgpu_crtc *acrtc);
-
-static void wait_while_pflip_status(struct amdgpu_device *adev,
-		struct amdgpu_crtc *acrtc, predicate f) {
-	int count = 0;
-	while (f(acrtc)) {
-		/* Spin Wait*/
-		msleep(1);
-		count++;
-		if (count == 1000) {
-			DRM_ERROR("%s - crtc:%d[%p], pflip_stat:%d, probable hang!\n",
-										__func__, acrtc->crtc_id,
-										acrtc,
-										acrtc->pflip_status);
-
-			/* we do not expect to hit this case except on Polaris with PHY PLL
-			 * 1. DP to HDMI passive dongle connected
-			 * 2. unplug (headless)
-			 * 3. plug in DP
-			 * 3a. on plug in, DP will try verify link by training, and training
-			 * would disable PHY PLL which HDMI rely on to drive TG
-			 * 3b. this will cause flip interrupt cannot be generated, and we
-			 * exit when timeout expired.  however we do not have code to clean
-			 * up flip, flip clean up will happen when the address is written
-			 * with the restore mode change
-			 */
-			WARN_ON(1);
-			break;
-		}
-	}
-
-	DRM_DEBUG_DRIVER("%s - Finished waiting for:%d msec, crtc:%d[%p], pflip_stat:%d \n",
-											__func__,
-											count,
-											acrtc->crtc_id,
-											acrtc,
-											acrtc->pflip_status);
-}
-
-static bool pflip_in_progress_predicate(struct amdgpu_crtc *acrtc)
-{
-	return acrtc->pflip_status != AMDGPU_FLIP_NONE;
-}
-
 static void manage_dm_interrupts(
 	struct amdgpu_device *adev,
 	struct amdgpu_crtc *acrtc,
@@ -2372,8 +2344,6 @@ static void manage_dm_interrupts(
 			&adev->pageflip_irq,
 			irq_type);
 	} else {
-		wait_while_pflip_status(adev, acrtc,
-				pflip_in_progress_predicate);
 
 		amdgpu_irq_put(
 			adev,
@@ -2383,12 +2353,6 @@ static void manage_dm_interrupts(
 	}
 }
 
-
-static bool pflip_pending_predicate(struct amdgpu_crtc *acrtc)
-{
-	return acrtc->pflip_status == AMDGPU_FLIP_PENDING;
-}
-
 static bool is_scaling_state_different(
 		const struct dm_connector_state *dm_state,
 		const struct dm_connector_state *old_dm_state)
@@ -2426,116 +2390,94 @@ static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc)
 	acrtc->enabled = false;
 }
 
-int amdgpu_dm_atomic_commit(
-	struct drm_device *dev,
-	struct drm_atomic_state *state,
-	bool nonblock)
+
+/*
+ * Executes flip
+ *
+ * Waits on all BO's fences and for proper vblank count
+ */
+static void amdgpu_dm_do_flip(
+				struct drm_crtc *crtc,
+				struct drm_framebuffer *fb,
+				uint32_t target)
 {
+	unsigned long flags;
+	uint32_t target_vblank;
+	int r, vpos, hpos;
+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
+	struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
+	struct amdgpu_device *adev = crtc->dev->dev_private;
+	bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
+
+
+	/*TODO This might fail and hence better not used, wait
+	 * explicitly on fences instead
+	 * and in general should be called for
+	 * blocking commit to as per framework helpers
+	 * */
+	r = amdgpu_bo_reserve(abo, true);
+	if (unlikely(r != 0)) {
+		DRM_ERROR("failed to reserve buffer before flip\n");
+		BUG_ON(0);
+	}
+
+	/* Wait for all fences on this FB */
+	WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
+								    MAX_SCHEDULE_TIMEOUT) < 0);
+
+	amdgpu_bo_unreserve(abo);
+
+	/* Wait for target vblank */
+	/* Wait until we're out of the vertical blank period before the one
+	 * targeted by the flip
+	 */
+	target_vblank = target - drm_crtc_vblank_count(crtc) +
+			amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
+
+	while ((acrtc->enabled &&
+		(amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
+					&vpos, &hpos, NULL, NULL,
+					&crtc->hwmode)
+		 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
+		(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
+		(int)(target_vblank -
+		  amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
+		usleep_range(1000, 1100);
+	}
+
+	/* Flip */
+	spin_lock_irqsave(&crtc->dev->event_lock, flags);
+	/* update crtc fb */
+	crtc->primary->fb = fb;
+
+	/* Do the flip (mmio) */
+	adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip);
+
+	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
+	DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
+						 acrtc->crtc_id);
+}
+
+void amdgpu_dm_atomic_commit_tail(
+	struct drm_atomic_state *state)
+{
+	struct drm_device *dev = state->dev;
 	struct amdgpu_device *adev = dev->dev_private;
 	struct amdgpu_display_manager *dm = &adev->dm;
 	struct drm_plane *plane;
-	struct drm_plane_state *new_plane_state;
 	struct drm_plane_state *old_plane_state;
 	uint32_t i;
-	int32_t ret = 0;
 	uint32_t commit_streams_count = 0;
 	uint32_t new_crtcs_count = 0;
-	uint32_t flip_crtcs_count = 0;
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *old_crtc_state;
 	const struct dc_stream *commit_streams[MAX_STREAMS];
 	struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
 	const struct dc_stream *new_stream;
-	struct drm_crtc *flip_crtcs[MAX_STREAMS];
-	struct amdgpu_flip_work *work[MAX_STREAMS] = {0};
-	struct amdgpu_bo *new_abo[MAX_STREAMS] = {0};
-
-	/* In this step all new fb would be pinned */
-
-	/*
-	 * TODO: Revisit when we support true asynchronous commit.
-	 * Right now we receive async commit only from pageflip, in which case
-	 * we should not pin/unpin the fb here, it should be done in
-	 * amdgpu_crtc_flip and from the vblank irq handler.
-	 */
-	if (!nonblock) {
-		ret = drm_atomic_helper_prepare_planes(dev, state);
-		if (ret)
-			return ret;
-	}
+	unsigned long flags;
+	bool wait_for_vblank = true;
 
-	/* Page flip if needed */
-	for_each_plane_in_state(state, plane, new_plane_state, i) {
-		struct drm_plane_state *old_plane_state = plane->state;
-		struct drm_crtc *crtc = new_plane_state->crtc;
-		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-		struct drm_framebuffer *fb = new_plane_state->fb;
-		struct drm_crtc_state *crtc_state;
-
-		if (!fb || !crtc)
-			continue;
-
-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
-
-		if (!crtc_state->planes_changed || !crtc_state->active)
-			continue;
-
-		if (page_flip_needed(
-				new_plane_state,
-				old_plane_state,
-				crtc_state->event,
-				false)) {
-			ret = amdgpu_crtc_prepare_flip(crtc,
-							fb,
-							crtc_state->event,
-							acrtc->flip_flags,
-							drm_crtc_vblank_count(crtc),
-							&work[flip_crtcs_count],
-							&new_abo[flip_crtcs_count]);
-
-			if (ret) {
-				/* According to atomic_commit hook API, EINVAL is not allowed */
-				if (unlikely(ret == -EINVAL))
-					ret = -ENOMEM;
-
-				DRM_ERROR("Atomic commit: Flip for  crtc id %d: [%p], "
-									"failed, errno = %d\n",
-									acrtc->crtc_id,
-									acrtc,
-									ret);
-				/* cleanup all flip configurations which
-				 * succeeded in this commit
-				 */
-				for (i = 0; i < flip_crtcs_count; i++)
-					amdgpu_crtc_cleanup_flip_ctx(
-							work[i],
-							new_abo[i]);
-
-				return ret;
-			}
-
-			flip_crtcs[flip_crtcs_count] = crtc;
-			flip_crtcs_count++;
-		}
-	}
-
-	/*
-	 * This is the point of no return - everything below never fails except
-	 * when the hw goes bonghits. Which means we can commit the new state on
-	 * the software side now.
-	 */
-
-	drm_atomic_helper_swap_state(state, true);
-
-	/*
-	 * From this point state become old state really. New state is
-	 * initialized to appropriate objects and could be accessed from there
-	 */
-
-	/*
-	 * there is no fences usage yet in state. We can skip the following line
-	 * wait_for_fences(dev, state);
-	 */
 
 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
 
@@ -2691,11 +2633,11 @@ int amdgpu_dm_atomic_commit(
 	for_each_plane_in_state(state, plane, old_plane_state, i) {
 		struct drm_plane_state *plane_state = plane->state;
 		struct drm_crtc *crtc = plane_state->crtc;
-		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 		struct drm_framebuffer *fb = plane_state->fb;
 		struct drm_connector *connector;
 		struct dm_connector_state *dm_state = NULL;
 		enum dm_commit_action action;
+		bool pflip_needed;
 
 		if (!fb || !crtc || !crtc->state->active)
 			continue;
@@ -2706,12 +2648,14 @@ int amdgpu_dm_atomic_commit(
 		 * 1. This commit is not a page flip.
 		 * 2. This commit is a page flip, and streams are created.
 		 */
-		if (!page_flip_needed(
+		pflip_needed = !state->allow_modeset &&
+				page_flip_needed(
 				plane_state,
 				old_plane_state,
-				crtc->state->event, true) ||
-				action == DM_COMMIT_ACTION_DPMS_ON ||
-				action == DM_COMMIT_ACTION_SET) {
+				crtc->state->event, true);
+		if (!pflip_needed ||
+		     action == DM_COMMIT_ACTION_DPMS_ON ||
+		     action == DM_COMMIT_ACTION_SET) {
 			list_for_each_entry(connector,
 				&dev->mode_config.connector_list, head)	{
 				if (connector->state->crtc == crtc) {
@@ -2738,14 +2682,6 @@ int amdgpu_dm_atomic_commit(
 			if (!dm_state)
 				continue;
 
-			/*
-			 * if flip is pending (ie, still waiting for fence to return
-			 * before address is submitted) here, we cannot commit_surface
-			 * as commit_surface will pre-maturely write out the future
-			 * address. wait until flip is submitted before proceeding.
-			 */
-			wait_while_pflip_status(adev, acrtc, pflip_pending_predicate);
-
 			dm_dc_surface_commit(dm->dc, crtc);
 		}
 	}
@@ -2765,43 +2701,77 @@ int amdgpu_dm_atomic_commit(
 
 	}
 
-	/* Do actual flip */
-	flip_crtcs_count = 0;
 	for_each_plane_in_state(state, plane, old_plane_state, i) {
 		struct drm_plane_state *plane_state = plane->state;
 		struct drm_crtc *crtc = plane_state->crtc;
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 		struct drm_framebuffer *fb = plane_state->fb;
+		bool pflip_needed;
 
 		if (!fb || !crtc || !crtc->state->planes_changed ||
 			!crtc->state->active)
 			continue;
-
-		if (page_flip_needed(
+		pflip_needed = !state->allow_modeset &&
+				page_flip_needed(
 				plane_state,
 				old_plane_state,
 				crtc->state->event,
-				false)) {
-				amdgpu_crtc_submit_flip(
-							crtc,
-						    fb,
-						    work[flip_crtcs_count],
-						    new_abo[i]);
-				 flip_crtcs_count++;
+				false);
+
+		if (pflip_needed) {
+			amdgpu_dm_do_flip(
+					crtc,
+					fb,
+					drm_crtc_vblank_count(crtc));
+
+			wait_for_vblank =
+					acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
+							false : true;
 			/*clean up the flags for next usage*/
 			acrtc->flip_flags = 0;
 		}
 	}
 
-	/* In this state all old framebuffers would be unpinned */
 
-	/* TODO: Revisit when we support true asynchronous commit.*/
-	if (!nonblock)
-		drm_atomic_helper_cleanup_planes(dev, state);
+	/*TODO mark consumed event on all crtc assigned event
+	 * in drm_atomic_helper_setup_commit just to signal completion
+	 */
+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
+	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
-	drm_atomic_state_free(state);
+		if (acrtc->base.state->event &&
+				acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
+			acrtc->event = acrtc->base.state->event;
+			acrtc->base.state->event = NULL;
+		}
+	}
+	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
-	return ret;
+	/* Signal HW programming completion */
+	drm_atomic_helper_commit_hw_done(state);
+
+	if (wait_for_vblank)
+		drm_atomic_helper_wait_for_vblanks(dev, state);
+
+	/*TODO send vblank event on all crtc assigned event
+	 * in drm_atomic_helper_setup_commit just to signal completion
+	 */
+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
+	for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+
+		if (acrtc->event &&
+			acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) {
+			drm_send_event_locked(dev, &acrtc->event->base);
+			acrtc->event = NULL;
+		}
+	}
+	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
+
+	/*TODO Is it to early if actual flip haven't happened yet ?*/
+	/* Release old FB */
+	drm_atomic_helper_cleanup_planes(dev, state);
 }
 /*
  * This functions handle all cases when set mode does not come upon hotplug.
@@ -3153,6 +3123,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			struct dm_connector_state *dm_state = NULL;
 			enum dm_commit_action action;
 			struct drm_crtc_state *crtc_state;
+			bool pflip_needed;
 
 
 			if (!fb || !crtc || crtc_set[i] != crtc ||
@@ -3166,10 +3137,12 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			 * 2. This commit is a page flip, and streams are created.
 			 */
 			crtc_state = drm_atomic_get_crtc_state(state, crtc);
-			if (!page_flip_needed(plane_state, old_plane_state,
-					crtc_state->event, true) ||
-					action == DM_COMMIT_ACTION_DPMS_ON ||
-					action == DM_COMMIT_ACTION_SET) {
+			pflip_needed = !state->allow_modeset &&
+					page_flip_needed(plane_state, old_plane_state,
+					crtc_state->event, true);
+			if (!pflip_needed ||
+				action == DM_COMMIT_ACTION_DPMS_ON ||
+				action == DM_COMMIT_ACTION_SET) {
 				struct dc_surface *surface;
 
 				list_for_each_entry(connector,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 4faa1659f7f9..1bbeb87dc9d0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -52,10 +52,9 @@ void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder);
 
 int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 
-int amdgpu_dm_atomic_commit(
-	struct drm_device *dev,
-	struct drm_atomic_state *state,
-	bool async);
+void amdgpu_dm_atomic_commit_tail(
+	struct drm_atomic_state *state);
+
 int amdgpu_dm_atomic_check(struct drm_device *dev,
 				struct drm_atomic_state *state);
 
-- 
2.10.2

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[PATCH 08/27] drm/amd/display: Refactor headless to use atomic commit.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Headless mode set needs to be synchronized against outstanding nonblocking
commits. This achieved by building atomic state and commiting it.

Change-Id: Ie5e778afb33dd5c303a169216a7bb8c2d857037e
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 140 +++++++++------------
 1 file changed, 61 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 7e762aac07ac..b87cdfcf8c63 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2773,6 +2773,65 @@ void amdgpu_dm_atomic_commit_tail(
 	/* Release old FB */
 	drm_atomic_helper_cleanup_planes(dev, state);
 }
+
+
+static int dm_force_atomic_commit(struct drm_connector *connector)
+{
+	int ret = 0;
+	struct drm_device *ddev = connector->dev;
+	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
+	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
+	struct drm_plane *plane = disconnected_acrtc->base.primary;
+	struct drm_connector_state *conn_state;
+	struct drm_crtc_state *crtc_state;
+	struct drm_plane_state *plane_state;
+
+	if (!state)
+		return -ENOMEM;
+
+	state->acquire_ctx = ddev->mode_config.acquire_ctx;
+
+	/* Construct an atomic state to restore previous display setting */
+
+	/*
+	 * Attach connectors to drm_atomic_state
+	 */
+	conn_state = drm_atomic_get_connector_state(state, connector);
+
+	ret = PTR_ERR_OR_ZERO(conn_state);
+	if (ret)
+		goto err;
+
+	/* Attach crtc to drm_atomic_state*/
+	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
+
+	ret = PTR_ERR_OR_ZERO(crtc_state);
+	if (ret)
+		goto err;
+
+	/* force a restore */
+	crtc_state->mode_changed = true;
+
+	/* Attach plane to drm_atomic_state */
+	plane_state = drm_atomic_get_plane_state(state, plane);
+
+	ret = PTR_ERR_OR_ZERO(plane_state);
+	if (ret)
+		goto err;
+
+
+	/* Call commit internally with the state we just constructed */
+	ret = drm_atomic_commit(state);
+	if (!ret)
+		return 0;
+
+err:
+	DRM_ERROR("Restoring old state failed with %i\n", ret);
+	drm_atomic_state_free(state);
+
+	return ret;
+}
+
 /*
  * This functions handle all cases when set mode does not come upon hotplug.
  * This include when the same display is unplugged then plugged back into the
@@ -2780,15 +2839,8 @@ void amdgpu_dm_atomic_commit_tail(
  */
 void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
 {
-	struct drm_crtc *crtc;
-	struct amdgpu_device *adev = dev->dev_private;
-	struct dc *dc = adev->dm.dc;
 	struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
 	struct amdgpu_crtc *disconnected_acrtc;
-	const struct dc_sink *sink;
-	const struct dc_stream *commit_streams[MAX_STREAMS];
-	const struct dc_stream *current_stream;
-	uint32_t commit_streams_count = 0;
 
 	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
 		return;
@@ -2798,83 +2850,13 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector
 	if (!disconnected_acrtc || !disconnected_acrtc->stream)
 		return;
 
-	sink = disconnected_acrtc->stream->sink;
-
 	/*
 	 * If the previous sink is not released and different from the current,
 	 * we deduce we are in a state where we can not rely on usermode call
 	 * to turn on the display, so we do it here
 	 */
-	if (sink != aconnector->dc_sink) {
-		struct dm_connector_state *dm_state =
-				to_dm_connector_state(aconnector->base.state);
-
-		struct dc_stream *new_stream =
-			create_stream_for_sink(
-				aconnector,
-				&disconnected_acrtc->base.state->mode,
-				dm_state);
-
-		DRM_INFO("Headless hotplug, restoring connector state\n");
-		/*
-		 * we evade vblanks and pflips on crtc that
-		 * should be changed
-		 */
-		manage_dm_interrupts(adev, disconnected_acrtc, false);
-		/* this is the update mode case */
-
-		current_stream = disconnected_acrtc->stream;
-
-		disconnected_acrtc->stream = new_stream;
-		disconnected_acrtc->enabled = true;
-		disconnected_acrtc->hw_mode = disconnected_acrtc->base.state->mode;
-
-		commit_streams_count = 0;
-
-		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-			struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-
-			if (acrtc->stream) {
-				commit_streams[commit_streams_count] = acrtc->stream;
-				++commit_streams_count;
-			}
-		}
-
-		/* DC is optimized not to do anything if 'streams' didn't change. */
-		if (!dc_commit_streams(dc, commit_streams,
-				commit_streams_count)) {
-			DRM_INFO("Failed to restore connector state!\n");
-			dc_stream_release(disconnected_acrtc->stream);
-			disconnected_acrtc->stream = current_stream;
-			manage_dm_interrupts(adev, disconnected_acrtc, true);
-			return;
-		}
-
-		if (adev->dm.freesync_module) {
-			mod_freesync_remove_stream(adev->dm.freesync_module,
-				current_stream);
-
-			mod_freesync_add_stream(adev->dm.freesync_module,
-						new_stream, &aconnector->caps);
-		}
-
-		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-			struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-
-			if (acrtc->stream != NULL) {
-				acrtc->otg_inst =
-					dc_stream_get_status(acrtc->stream)->primary_otg_inst;
-			}
-		}
-
-		dc_stream_release(current_stream);
-
-		dm_dc_surface_commit(dc, &disconnected_acrtc->base);
-
-		manage_dm_interrupts(adev, disconnected_acrtc, true);
-		dm_crtc_cursor_reset(&disconnected_acrtc->base);
-
-	}
+	if (disconnected_acrtc->stream->sink != aconnector->dc_sink)
+		dm_force_atomic_commit(&aconnector->base);
 }
 
 static uint32_t add_val_sets_surface(
-- 
2.10.2

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[PATCH 09/27] drm/amd/display: Remove page_fleep_needed function.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

This function makes a lot of assumptions to try and deduce
tha an atomic_commit came from FLIP ioctl. Those assumptions
are not explicit contract with DRM API and might lead to wrong
result as the code changes. Instead use drm_atomic_state.allow_modeset
flag which explicitly is set to false only in atomic flip
helper function, otherwise this flag is always true.
P.S When we get to do actual atomic IOCTL this will have to be revised
with the atomic call behavior.

Change-Id: I2c2c95daf015627a5f215fd8932a8a4fb4ba6d89
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 92 +---------------------
 1 file changed, 3 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index b87cdfcf8c63..d4f8f81d6edb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1593,80 +1593,6 @@ static const struct drm_plane_funcs dm_plane_funcs = {
 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state
 };
 
-static void clear_unrelated_fields(struct drm_plane_state *state)
-{
-	state->crtc = NULL;
-	state->fb = NULL;
-	state->state = NULL;
-	state->fence = NULL;
-}
-
-/*TODO update because event is always present now */
-static bool page_flip_needed(
-	const struct drm_plane_state *new_state,
-	const struct drm_plane_state *old_state,
-	struct drm_pending_vblank_event *event,
-	bool commit_surface_required)
-{
-	struct drm_plane_state old_state_tmp;
-	struct drm_plane_state new_state_tmp;
-
-	struct amdgpu_framebuffer *amdgpu_fb_old;
-	struct amdgpu_framebuffer *amdgpu_fb_new;
-	struct amdgpu_crtc *acrtc_new;
-
-	uint64_t old_tiling_flags;
-	uint64_t new_tiling_flags;
-
-	bool page_flip_required;
-
-	if (!old_state)
-		return false;
-
-	if (!old_state->fb)
-		return false;
-
-	if (!new_state)
-		return false;
-
-	if (!new_state->fb)
-		return false;
-
-	old_state_tmp = *old_state;
-	new_state_tmp = *new_state;
-
-	if (!event)
-		return false;
-
-	amdgpu_fb_old = to_amdgpu_framebuffer(old_state->fb);
-	amdgpu_fb_new = to_amdgpu_framebuffer(new_state->fb);
-
-	if (!get_fb_info(amdgpu_fb_old, &old_tiling_flags, NULL))
-		return false;
-
-	if (!get_fb_info(amdgpu_fb_new, &new_tiling_flags, NULL))
-		return false;
-
-	if (commit_surface_required == true &&
-	    old_tiling_flags != new_tiling_flags)
-		return false;
-
-	clear_unrelated_fields(&old_state_tmp);
-	clear_unrelated_fields(&new_state_tmp);
-
-	page_flip_required = memcmp(&old_state_tmp,
-				    &new_state_tmp,
-				    sizeof(old_state_tmp)) == 0 ? true:false;
-
-	if (new_state->crtc && page_flip_required == false) {
-		acrtc_new = to_amdgpu_crtc(new_state->crtc);
-		if (acrtc_new->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
-			page_flip_required = true;
-	}
-
-	return page_flip_required;
-}
-
 static int dm_plane_helper_prepare_fb(
 	struct drm_plane *plane,
 	struct drm_plane_state *new_state)
@@ -2648,11 +2574,7 @@ void amdgpu_dm_atomic_commit_tail(
 		 * 1. This commit is not a page flip.
 		 * 2. This commit is a page flip, and streams are created.
 		 */
-		pflip_needed = !state->allow_modeset &&
-				page_flip_needed(
-				plane_state,
-				old_plane_state,
-				crtc->state->event, true);
+		pflip_needed = !state->allow_modeset;
 		if (!pflip_needed ||
 		     action == DM_COMMIT_ACTION_DPMS_ON ||
 		     action == DM_COMMIT_ACTION_SET) {
@@ -2711,12 +2633,7 @@ void amdgpu_dm_atomic_commit_tail(
 		if (!fb || !crtc || !crtc->state->planes_changed ||
 			!crtc->state->active)
 			continue;
-		pflip_needed = !state->allow_modeset &&
-				page_flip_needed(
-				plane_state,
-				old_plane_state,
-				crtc->state->event,
-				false);
+		pflip_needed = !state->allow_modeset;
 
 		if (pflip_needed) {
 			amdgpu_dm_do_flip(
@@ -3098,7 +3015,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
 	for (i = 0; i < set_count; i++) {
 		for_each_plane_in_state(state, plane, plane_state, j) {
-			struct drm_plane_state *old_plane_state = plane->state;
 			struct drm_crtc *crtc = plane_state->crtc;
 			struct drm_framebuffer *fb = plane_state->fb;
 			struct drm_connector *connector;
@@ -3119,9 +3035,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 			 * 2. This commit is a page flip, and streams are created.
 			 */
 			crtc_state = drm_atomic_get_crtc_state(state, crtc);
-			pflip_needed = !state->allow_modeset &&
-					page_flip_needed(plane_state, old_plane_state,
-					crtc_state->event, true);
+			pflip_needed = !state->allow_modeset;
 			if (!pflip_needed ||
 				action == DM_COMMIT_ACTION_DPMS_ON ||
 				action == DM_COMMIT_ACTION_SET) {
-- 
2.10.2

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[PATCH 10/27] drm/amd/display: clean up and simply locking logic

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

always take update lock instead of using HW built in update lock trigger with write to primary_addr_lo.

we will be a little more inefficient with the extra registers write to lock, but this simplify code and make it always correct.

Will revisit locking optimization once update sequence mature

Change-Id: If576fc059da16fd4fe3587743ce907e9490ba2a8
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c          | 32 +++++++----------------
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c    |  3 +--
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h |  1 -
 3 files changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index efe50fd2be78..8f871924beb9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1321,22 +1321,22 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 			if (pipe_ctx->surface != surface)
 				continue;
-			/*lock all the MCPP if blnd is enable for DRR*/
-			if ((update_type == UPDATE_TYPE_FAST &&
-					(dc_stream->freesync_ctx.enabled == true &&
-							surface_count != context->res_ctx.pool->pipe_count)) &&
-					!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-				lock_mask = PIPE_LOCK_CONTROL_MPCC_ADDR;
+
+			if (update_type == UPDATE_TYPE_FULL) {
+				/* only apply for top pipe */
+				if (!pipe_ctx->top_pipe) {
+					core_dc->hwss.apply_ctx_for_surface(core_dc,
+							 surface, context);
+					context_timing_trace(dc, &context->res_ctx);
+				}
 			}
 
-			if (update_type != UPDATE_TYPE_FAST &&
-				!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
+			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
 						PIPE_LOCK_CONTROL_SCL |
 						PIPE_LOCK_CONTROL_BLENDER |
 						PIPE_LOCK_CONTROL_MODE;
-			}
-			if (lock_mask != 0) {
+
 				core_dc->hwss.pipe_control_lock(
 						core_dc,
 						pipe_ctx,
@@ -1344,15 +1344,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 						true);
 			}
 
-			if (update_type == UPDATE_TYPE_FULL) {
-				/* only apply for top pipe */
-				if (!pipe_ctx->top_pipe) {
-					core_dc->hwss.apply_ctx_for_surface(core_dc,
-							 surface, context);
-					context_timing_trace(dc, &context->res_ctx);
-				}
-			}
-
 			if (updates[i].flip_addr)
 				core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
 
@@ -1382,9 +1373,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		}
 	}
 
-	if ((update_type == UPDATE_TYPE_FAST) && lock_mask == 0)
-		return;
-
 	for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 1e1d60af8306..89a8274e12ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -52,8 +52,7 @@ void dce_pipe_control_lock(struct core_dc *dc,
 	uint32_t lock_val = lock ? 1 : 0;
 	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
 	struct dce_hwseq *hws = dc->hwseq;
-	if (control_mask & PIPE_LOCK_CONTROL_MPCC_ADDR)
-		return;
+
 	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
 			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
 			BLND_SCL_V_UPDATE_LOCK, &scl,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index a902de52107f..612910e720af 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -39,7 +39,6 @@ enum pipe_lock_control {
 	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
 	PIPE_LOCK_CONTROL_SCL = 1 << 2,
 	PIPE_LOCK_CONTROL_MODE = 1 << 3,
-	PIPE_LOCK_CONTROL_MPCC_ADDR = 1 << 4
 };
 
 struct dce_hwseq_wa {
-- 
2.10.2

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[PATCH 11/27] drm/amd/display: remove independent lock as we have no use case today

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: Id3561b3aaeef9086908b5f04c91c4604dba19c6b
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c          |  8 --------
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c    | 19 +++++--------------
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h    |  1 -
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h |  8 --------
 4 files changed, 5 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8f871924beb9..c34232c8c322 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1178,7 +1178,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 
 	enum surface_update_type update_type;
 	const struct dc_stream_status *stream_status;
-	unsigned int lock_mask = 0;
 
 	stream_status = dc_stream_get_status(dc_stream);
 	ASSERT(stream_status);
@@ -1332,15 +1331,9 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 			}
 
 			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |
-						PIPE_LOCK_CONTROL_SCL |
-						PIPE_LOCK_CONTROL_BLENDER |
-						PIPE_LOCK_CONTROL_MODE;
-
 				core_dc->hwss.pipe_control_lock(
 						core_dc,
 						pipe_ctx,
-						lock_mask,
 						true);
 			}
 
@@ -1382,7 +1375,6 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 					core_dc->hwss.pipe_control_lock(
 							core_dc,
 							pipe_ctx,
-							lock_mask,
 							false);
 				}
 				break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 89a8274e12ea..17cdd70a2c27 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -46,7 +46,6 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
 
 void dce_pipe_control_lock(struct core_dc *dc,
 		struct pipe_ctx *pipe,
-		enum pipe_lock_control control_mask,
 		bool lock)
 {
 	uint32_t lock_val = lock ? 1 : 0;
@@ -59,18 +58,10 @@ void dce_pipe_control_lock(struct core_dc *dc,
 			BLND_BLND_V_UPDATE_LOCK, &blnd,
 			BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
 
-	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
-		dcp_grph = lock_val;
-
-	if (control_mask & PIPE_LOCK_CONTROL_SCL)
-		scl = lock_val;
-
-	if (control_mask & PIPE_LOCK_CONTROL_BLENDER)
-		blnd = lock_val;
-
-	if (control_mask & PIPE_LOCK_CONTROL_MODE)
-		update_lock_mode = lock_val;
-
+	dcp_grph = lock_val;
+	scl = lock_val;
+	blnd = lock_val;
+	update_lock_mode = lock_val;
 
 	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
 			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
@@ -82,7 +73,7 @@ void dce_pipe_control_lock(struct core_dc *dc,
 				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
 
 	if (hws->wa.blnd_crtc_trigger) {
-		if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
+		if (!lock) {
 			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
 			REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 9ef618443255..70e0652be071 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -224,7 +224,6 @@ void dce_enable_fe_clock(struct dce_hwseq *hwss,
 
 void dce_pipe_control_lock(struct core_dc *dc,
 		struct pipe_ctx *pipe,
-		enum pipe_lock_control control_mask,
 		bool lock);
 
 void dce_set_blender_mode(struct dce_hwseq *hws,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 612910e720af..98a04cd46178 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -34,13 +34,6 @@ enum pipe_gating_control {
 	PIPE_GATING_CONTROL_INIT
 };
 
-enum pipe_lock_control {
-	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
-	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
-	PIPE_LOCK_CONTROL_SCL = 1 << 2,
-	PIPE_LOCK_CONTROL_MODE = 1 << 3,
-};
-
 struct dce_hwseq_wa {
 	bool blnd_crtc_trigger;
 };
@@ -128,7 +121,6 @@ struct hw_sequencer_funcs {
 	void (*pipe_control_lock)(
 				struct core_dc *dc,
 				struct pipe_ctx *pipe,
-				enum pipe_lock_control control_mask,
 				bool lock);
 
 	void (*set_displaymarks)(
-- 
2.10.2

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[PATCH 12/27] drm/amd/display: sometime VtotalMin less than VTotal (rounding issue)

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I1f8de5415aac149d85b73a28fb630c50696a9250
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 2026ef34b11b..7a0731e2dbb0 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -905,7 +905,6 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
 
 	for (stream_index = 0; stream_index < num_streams; stream_index++) {
-
 		map_index = map_index_from_stream(core_freesync,
 				streams[stream_index]);
 
@@ -913,11 +912,12 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
 
 		if (core_freesync->map[map_index].caps->supported) {
 			/* Update the field rate for new timing */
-			state->nominal_refresh_rate_in_micro_hz = 1000000 *
-				div64_u64(div64_u64((streams[stream_index]->
-				timing.pix_clk_khz * 1000),
-				streams[stream_index]->timing.v_total),
-				streams[stream_index]->timing.h_total);
+			unsigned long long temp;
+			temp = streams[stream_index]->timing.pix_clk_khz;
+			temp *= 1000ULL * 1000ULL * 1000ULL;
+			temp = div_u64(temp, streams[stream_index]->timing.h_total);
+			temp = div_u64(temp, streams[stream_index]->timing.v_total);
+			state->nominal_refresh_rate_in_micro_hz = (unsigned int) temp;
 
 			/* Update the stream */
 			update_stream(core_freesync, streams[stream_index]);
-- 
2.10.2

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[PATCH 13/27] drm/amd/display: Adding FastUpdate functionality

[Harry Wentland]

From: Leon Elazar <leon.elazar@amd.com>

Exposing DC Api dc_check_update_surfaces_for_stream
validation will return the answer which type of update is required,
so upper layers can is it safe to call the update API fro high IRQ yes/no.

Change-Id: I094592c5df4227ed2fea2ceb5de5b2604173fa20
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 149 ++++++++++++++++++++++++++-----
 drivers/gpu/drm/amd/display/dc/dc.h      |  12 +++
 2 files changed, 140 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c34232c8c322..27e31bd665ce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1110,42 +1110,149 @@ static bool is_surface_in_context(
 	return false;
 }
 
-enum surface_update_type {
-	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
-	UPDATE_TYPE_MED,  /* a lot of programming needed.  may need to alloc */
-	UPDATE_TYPE_FULL, /* may need to shuffle resources */
-};
+static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
+{
+	switch (format) {
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+		return 16;
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+		return 32;
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+		return 64;
+	default:
+		ASSERT_CRITICAL(false);
+		return -1;
+	}
+}
+
+static enum surface_update_type get_plane_info_update_type(
+		const struct dc_surface_update *u)
+{
+	struct dc_plane_info temp_plane_info = { { { { 0 } } } };
+
+	if (!u->plane_info)
+		return UPDATE_TYPE_FAST;
+
+	/* Copy all parameters that will cause a full update
+	 * from current surface, the rest of the parameters
+	 * from provided plane configuration.
+	 * Perform memory compare and special validation
+	 * for those that can cause fast/medium updates
+	 */
+
+	/* Full update parameters */
+	temp_plane_info.color_space = u->surface->color_space;
+	temp_plane_info.dcc = u->surface->dcc;
+	temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
+	temp_plane_info.plane_size = u->surface->plane_size;
+	temp_plane_info.rotation = u->surface->rotation;
+	temp_plane_info.stereo_format = u->surface->stereo_format;
+	temp_plane_info.tiling_info = u->surface->tiling_info;
+	temp_plane_info.visible = u->surface->visible;
+
+	/* Special Validation parameters */
+	temp_plane_info.format = u->plane_info->format;
+
+	if (memcmp(u->plane_info, &temp_plane_info,
+			sizeof(struct dc_plane_info)) != 0)
+		return UPDATE_TYPE_FULL;
+
+	if (pixel_format_to_bpp(u->plane_info->format) !=
+			pixel_format_to_bpp(u->surface->format)) {
+		return UPDATE_TYPE_FULL;
+	} else {
+		return UPDATE_TYPE_MED;
+	}
+}
+
+static enum surface_update_type  get_scaling_info_update_type(
+		const struct dc_surface_update *u)
+{
+	struct dc_scaling_info temp_scaling_info = { { 0 } };
+
+	if (!u->scaling_info)
+		return UPDATE_TYPE_FAST;
+
+	/* Copy all parameters that will cause a full update
+	 * from current surface, the rest of the parameters
+	 * from provided plane configuration.
+	 * Perform memory compare and special validation
+	 * for those that can cause fast/medium updates
+	 */
+
+	/* Full Update Parameters */
+	temp_scaling_info.dst_rect = u->surface->dst_rect;
+	temp_scaling_info.src_rect = u->surface->src_rect;
+	temp_scaling_info.scaling_quality = u->surface->scaling_quality;
+
+	/* Special validation required */
+	temp_scaling_info.clip_rect = u->scaling_info->clip_rect;
+
+	if (memcmp(u->scaling_info, &temp_scaling_info,
+			sizeof(struct dc_scaling_info)) != 0)
+		return UPDATE_TYPE_FULL;
+
+	/* Check Clip rectangles if not equal
+	 * difference is in offsets == > UPDATE_TYPE_FAST
+	 * difference is in dimensions == > UPDATE_TYPE_FULL
+	 */
+	if (memcmp(&u->scaling_info->clip_rect,
+			&u->surface->clip_rect, sizeof(struct rect)) != 0) {
+		if ((u->scaling_info->clip_rect.height ==
+			u->surface->clip_rect.height) &&
+			(u->scaling_info->clip_rect.width ==
+			u->surface->clip_rect.width)) {
+			return UPDATE_TYPE_FAST;
+		} else {
+			return UPDATE_TYPE_FULL;
+		}
+	}
+
+	return UPDATE_TYPE_FAST;
+}
 
 static enum surface_update_type det_surface_update(
 		const struct core_dc *dc,
 		const struct dc_surface_update *u)
 {
 	const struct validate_context *context = dc->current_context;
-
-	if (u->scaling_info || u->plane_info)
-		/* todo: not all scale and plane_info update need full update
-		 * ie. check if following is the same
-		 * scale ratio, view port, surface bpp etc
-		 */
-		return UPDATE_TYPE_FULL; /* may need bandwidth update */
+	enum surface_update_type type = UPDATE_TYPE_FAST;
+	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
 	if (!is_surface_in_context(context, u->surface))
 		return UPDATE_TYPE_FULL;
 
+	type = get_plane_info_update_type(u);
+	if (overall_type < type)
+		overall_type = type;
+
+	type = get_scaling_info_update_type(u);
+	if (overall_type < type)
+		overall_type = type;
+
 	if (u->in_transfer_func ||
 		u->out_transfer_func ||
-		u->hdr_static_metadata)
-		return UPDATE_TYPE_MED;
+		u->hdr_static_metadata) {
+		if (overall_type < UPDATE_TYPE_MED)
+			overall_type = UPDATE_TYPE_MED;
+	}
 
-	return UPDATE_TYPE_FAST;
+	return overall_type;
 }
 
-static enum surface_update_type check_update_surfaces_for_stream(
-		struct core_dc *dc,
+enum surface_update_type dc_check_update_surfaces_for_stream(
+		struct dc *dc,
 		struct dc_surface_update *updates,
 		int surface_count,
 		const struct dc_stream_status *stream_status)
 {
+	struct core_dc *core_dc = DC_TO_CORE(dc);
 	int i;
 	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
@@ -1154,7 +1261,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
 
 	for (i = 0 ; i < surface_count; i++) {
 		enum surface_update_type type =
-				det_surface_update(dc, &updates[i]);
+				det_surface_update(core_dc, &updates[i]);
 
 		if (type == UPDATE_TYPE_FULL)
 			return type;
@@ -1184,8 +1291,8 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 	if (!stream_status)
 		return; /* Cannot commit surface to stream that is not committed */
 
-	update_type = check_update_surfaces_for_stream(
-			core_dc, updates, surface_count, stream_status);
+	update_type = dc_check_update_surfaces_for_stream(
+			dc, updates, surface_count, stream_status);
 
 	if (update_type >= update_surface_trace_level)
 		update_surface_trace(dc, updates, surface_count);
@@ -1321,7 +1428,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 			if (pipe_ctx->surface != surface)
 				continue;
 
-			if (update_type == UPDATE_TYPE_FULL) {
+			if (update_type >= UPDATE_TYPE_MED) {
 				/* only apply for top pipe */
 				if (!pipe_ctx->top_pipe) {
 					core_dc->hwss.apply_ctx_for_surface(core_dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 2d84b18f48b0..69ae94bb209f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -379,6 +379,12 @@ bool dc_post_update_surfaces_to_stream(
 void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates,
 		int surface_count, const struct dc_stream *stream);
 
+enum surface_update_type {
+	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
+	UPDATE_TYPE_MED,  /* a lot of programming needed.  may need to alloc */
+	UPDATE_TYPE_FULL, /* may need to shuffle resources */
+};
+
 /*******************************************************************************
  * Stream Interfaces
  ******************************************************************************/
@@ -498,6 +504,12 @@ struct dc_stream_status {
 const struct dc_stream_status *dc_stream_get_status(
 	const struct dc_stream *dc_stream);
 
+enum surface_update_type dc_check_update_surfaces_for_stream(
+		struct dc *dc,
+		struct dc_surface_update *updates,
+		int surface_count,
+		const struct dc_stream_status *stream_status);
+
 /*******************************************************************************
  * Link Interfaces
  ******************************************************************************/
-- 
2.10.2

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[PATCH 14/27] drm/amd/display: Simplify some DMCU waits

[Harry Wentland]

From: Amy Zhang <Amy.Zhang@amd.com>

Change-Id: I3fbfab5a617bed56bb5013e820b0e37c507e0bfe
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h |  1 -
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c   | 46 +++++--------------------
 3 files changed, 9 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 3e3eefea3e82..ac1febafcaa4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -387,6 +387,7 @@ static void dce112_set_clock(
 					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
 
 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
+
 }
 
 static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 4ad6fe4c2841..020ab9d5434d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -45,7 +45,6 @@
 	CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 	CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
 
-
 #define CLK_REG_FIELD_LIST(type) \
 	type DPREFCLK_SRC_SEL; \
 	type DENTIST_DPREFCLK_WDIVIDER; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 44eeeeb888fe..da7f86b61de4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -57,19 +57,13 @@ bool dce_dmcu_load_iram(struct dmcu *dmcu,
 {
 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 	unsigned int count = 0;
-	uint32_t status;
 
 	/* Enable write access to IRAM */
 	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
 			IRAM_HOST_ACCESS_EN, 1,
 			IRAM_WR_ADDR_AUTO_INC, 1);
 
-	do {
-		dm_delay_in_microseconds(dmcu->ctx, 2);
-		REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &status);
-		count++;
-	} while
-	((status & dmcu_dce->dmcu_mask->DMCU_IRAM_MEM_PWR_STATE) && count < 10);
+	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 
 	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
 
@@ -88,21 +82,12 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
 {
 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
 
-	uint32_t count = 0;
 	uint32_t psrStateOffset = 0xf0;
-	uint32_t value = -1;
 
 	/* Enable write access to IRAM */
 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
 
-	while (REG(DCI_MEM_PWR_STATUS) && value != 0 && count++ < 10) {
-		dm_delay_in_microseconds(dmcu->ctx, 2);
-		REG_GET(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, &value);
-	}
-	while (REG(DMU_MEM_PWR_CNTL) && value != 0 && count++ < 10) {
-		dm_delay_in_microseconds(dmcu->ctx, 2);
-		REG_GET(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, &value);
-	}
+	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
 
 	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
 	REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
@@ -122,21 +107,13 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable)
 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 	unsigned int dmcu_wait_reg_ready_interval = 100;
 
-	unsigned int regValue;
-
 	unsigned int retryCount;
 	uint32_t psr_state = 0;
 
 	/* waitDMCUReadyForCmd */
-	do {
-		dm_delay_in_microseconds(dmcu->ctx,
-				dmcu_wait_reg_ready_interval);
-		regValue = REG_READ(MASTER_COMM_CNTL_REG);
-		dmcu_max_retry_on_wait_reg_ready--;
-	} while
-	/* expected value is 0, loop while not 0*/
-	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
-		dmcu_max_retry_on_wait_reg_ready > 0);
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+				dmcu_wait_reg_ready_interval,
+				dmcu_max_retry_on_wait_reg_ready);
 
 	/* setDMCUParam_Cmd */
 	if (enable)
@@ -170,7 +147,6 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu,
 
 	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
 	unsigned int dmcu_wait_reg_ready_interval = 100;
-	unsigned int regValue;
 
 	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
 	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
@@ -231,15 +207,9 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu,
 		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
 
 	/* waitDMCUReadyForCmd */
-	do {
-		dm_delay_in_microseconds(dmcu->ctx,
-				dmcu_wait_reg_ready_interval);
-		regValue = REG_READ(MASTER_COMM_CNTL_REG);
-		dmcu_max_retry_on_wait_reg_ready--;
-	} while
-	/* expected value is 0, loop while not 0*/
-	((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
-		dmcu_max_retry_on_wait_reg_ready > 0);
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+					dmcu_wait_reg_ready_interval,
+					dmcu_max_retry_on_wait_reg_ready);
 
 	/* setDMCUParam_PSRHostConfigData */
 	masterCmdData1.u32All = 0;
-- 
2.10.2

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[PATCH 15/27] drm/amd/display: refclock from bios firmwareInfoTable

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I7baef2a6e2629caf6639fab68536ac0ccecd9d86
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c              | 10 +++++++++-
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c       |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h             |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 17 ++++++-----------
 4 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 27e31bd665ce..302a10c86afb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -467,6 +467,8 @@ static bool construct(struct core_dc *dc,
 	else {
 		/* Create BIOS parser */
 		struct bp_init_data bp_init_data;
+		struct firmware_info fw_info = { { 0 } };
+
 		bp_init_data.ctx = dc_ctx;
 		bp_init_data.bios = init_params->asic_id.atombios_base_address;
 
@@ -479,7 +481,13 @@ static bool construct(struct core_dc *dc,
 		}
 
 		dc_ctx->created_bios = true;
-	}
+
+		if (dc_ctx->dc_bios->funcs->get_firmware_info(
+				dc_ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+				dc->ctx->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
+		} else
+			ASSERT_CRITICAL(false);
+		}
 
 	/* Create I2C AUX */
 	dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 4e1a933be021..365a19e5d11c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -237,7 +237,7 @@ bool dc_stream_set_cursor_position(
 			struct input_pixel_processor *ipp = pipe_ctx->ipp;
 			struct dc_cursor_mi_param param = {
 				.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
-				.ref_clk_khz = 48000,/*todo refclk*/
+				.ref_clk_khz = core_dc->ctx->ref_clock_inKhz,
 				.viewport_x_start = pipe_ctx->scl_data.viewport.x,
 				.viewport_width = pipe_ctx->scl_data.viewport.width,
 				.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 242dd7b3b6b1..c428a0249488 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -91,6 +91,7 @@ struct dc_context {
 	bool created_bios;
 	struct gpio_service *gpio_service;
 	struct i2caux *i2caux;
+	unsigned int ref_clock_inKhz;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index a2a2ecf8d077..1d6a9da45ba6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1230,17 +1230,12 @@ bool dce110_clk_src_construct(
 			goto unexpected_failure;
 		}
 
-		if (clk_src->ref_freq_khz == 48000) {
-			calc_pll_cs_init_data_hdmi.
-				min_override_input_pxl_clk_pll_freq_khz = 24000;
-			calc_pll_cs_init_data_hdmi.
-				max_override_input_pxl_clk_pll_freq_khz = 48000;
-		} else if (clk_src->ref_freq_khz == 100000) {
-			calc_pll_cs_init_data_hdmi.
-				min_override_input_pxl_clk_pll_freq_khz = 25000;
-			calc_pll_cs_init_data_hdmi.
-				max_override_input_pxl_clk_pll_freq_khz = 50000;
-		}
+
+		calc_pll_cs_init_data_hdmi.
+				min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
+		calc_pll_cs_init_data_hdmi.
+				max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
+
 
 		if (!calc_pll_max_vco_construct(
 				&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
-- 
2.10.2

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[PATCH 16/27] drm/amd/display: Memory leak fix during disable

[Harry Wentland]

From: Leon Elazar <leon.elazar@amd.com>

1.current_context memory wasn't released at
dc_post_update_surfaces_to_stream during context swap.

Change-Id: Iff814cf675856708daadfa540ef2b57d633139df
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 302a10c86afb..4fed2f25cd96 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1046,6 +1046,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 	core_dc->hwss.set_bandwidth(core_dc, context, true);
 
 	resource_validate_ctx_destruct(core_dc->current_context);
+	if (core_dc->current_context)
+		dm_free(core_dc->current_context);
+
 	core_dc->current_context = context;
 
 	return true;
-- 
2.10.2

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[PATCH 17/27] drm/amd/display: move refclk from dc to resource_pool

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: Ib84c5ff3887c4b096c8716279a7741b46350e433
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c          |  7 -------
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 25 ++++++++++++++++++-----
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c   |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h         |  1 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   |  1 +
 5 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4fed2f25cd96..f1ec27365f56 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -467,7 +467,6 @@ static bool construct(struct core_dc *dc,
 	else {
 		/* Create BIOS parser */
 		struct bp_init_data bp_init_data;
-		struct firmware_info fw_info = { { 0 } };
 
 		bp_init_data.ctx = dc_ctx;
 		bp_init_data.bios = init_params->asic_id.atombios_base_address;
@@ -481,12 +480,6 @@ static bool construct(struct core_dc *dc,
 		}
 
 		dc_ctx->created_bios = true;
-
-		if (dc_ctx->dc_bios->funcs->get_firmware_info(
-				dc_ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
-				dc->ctx->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
-		} else
-			ASSERT_CRITICAL(false);
 		}
 
 	/* Create I2C AUX */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 407ce60f253e..f1b1dae5399e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -31,6 +31,7 @@
 #include "opp.h"
 #include "timing_generator.h"
 #include "transform.h"
+#include "core_types.h"
 #include "set_mode_types.h"
 #include "virtual/virtual_stream_encoder.h"
 
@@ -77,25 +78,39 @@ struct resource_pool *dc_create_resource_pool(
 				enum dce_version dc_version,
 				struct hw_asic_id asic_id)
 {
+	struct resource_pool *res_pool = NULL;
 
 	switch (dc_version) {
 	case DCE_VERSION_8_0:
-		return dce80_create_resource_pool(
+		res_pool = dce80_create_resource_pool(
 			num_virtual_links, dc);
+		break;
 	case DCE_VERSION_10_0:
-		return dce100_create_resource_pool(
+		res_pool = dce100_create_resource_pool(
 				num_virtual_links, dc);
+		break;
 	case DCE_VERSION_11_0:
-		return dce110_create_resource_pool(
+		res_pool = dce110_create_resource_pool(
 			num_virtual_links, dc, asic_id);
+		break;
 	case DCE_VERSION_11_2:
-		return dce112_create_resource_pool(
+		res_pool = dce112_create_resource_pool(
 			num_virtual_links, dc);
+		break;
 	default:
 		break;
 	}
+	if (res_pool != NULL) {
+		struct firmware_info fw_info = { { 0 } };
+
+		if (dc->ctx->dc_bios->funcs->get_firmware_info(
+				dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+				res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
+			} else
+				ASSERT_CRITICAL(false);
+	}
 
-	return false;
+	return res_pool;
 }
 
 void dc_destroy_resource_pool(struct core_dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 365a19e5d11c..bafba1f13a1a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -237,7 +237,7 @@ bool dc_stream_set_cursor_position(
 			struct input_pixel_processor *ipp = pipe_ctx->ipp;
 			struct dc_cursor_mi_param param = {
 				.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
-				.ref_clk_khz = core_dc->ctx->ref_clock_inKhz,
+				.ref_clk_khz = res_ctx->pool->ref_clock_inKhz,
 				.viewport_x_start = pipe_ctx->scl_data.viewport.x,
 				.viewport_width = pipe_ctx->scl_data.viewport.width,
 				.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index c428a0249488..242dd7b3b6b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -91,7 +91,6 @@ struct dc_context {
 	bool created_bios;
 	struct gpio_service *gpio_service;
 	struct i2caux *i2caux;
-	unsigned int ref_clock_inKhz;
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index e8fe333c5918..b29fca9dfeff 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -239,6 +239,7 @@ struct resource_pool {
 	unsigned int pipe_count;
 	unsigned int underlay_pipe_index;
 	unsigned int stream_enc_count;
+	unsigned int ref_clock_inKhz;
 
 	/*
 	 * reserved clock source for DP
-- 
2.10.2

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[PATCH 18/27] drm/amd/display: TPS4 logic typo fix

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Change-Id: I334d4dfa6f5db2366457b1db9062f8ae6ec04e19
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index c250d8f6d011..5c6978eed8da 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -921,8 +921,8 @@ static inline bool perform_link_training_int(
 	 * If the upstream DPTX and downstream DPRX both support TPS4,
 	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
 	 */
-	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 &&
-		get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
+	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
+			get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
 		return status;
 
 	if (status &&
-- 
2.10.2

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[PATCH 19/27] drm/amd/display: After program backend, also program front end regs.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Issue:
In case of two 4K@60 + one non-4k monitor, when unplug non-4k monitor,
the remain two 4k monitor don't work properly.
Reason:
In that case, two 4k use two pipes and no split, when unplug happens,
those two monitor will use 4 pipes and split, but on that time, frontend
is not programed properly.
Solution:
After programed backend, front end should be programmed as per new pipe
setting.

Change-Id: Id8b7bd244241652132becb7eeb8e767813540e61
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f1ec27365f56..a39b9987b9d6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -806,7 +806,7 @@ bool dc_commit_streams(
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 	struct validate_context *context;
 	struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
-	int i, j, k;
+	int i, j;
 
 	if (false == streams_changed(core_dc, streams, stream_count))
 		return DC_OK;
@@ -862,18 +862,10 @@ bool dc_commit_streams(
 		const struct core_sink *sink = context->streams[i]->sink;
 
 		for (j = 0; j < context->stream_status[i].surface_count; j++) {
-			const struct dc_surface *dc_surface =
-					context->stream_status[i].surfaces[j];
-
-			for (k = 0; k < context->res_ctx.pool->pipe_count; k++) {
-				struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[k];
+			struct core_surface *surface =
+					DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 
-				if (dc_surface != &pipe->surface->public
-						|| !dc_surface->visible)
-					continue;
-
-				pipe->tg->funcs->set_blank(pipe->tg, false);
-			}
+			core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
 		}
 
 		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
-- 
2.10.2

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[PATCH 20/27] drm/amd/display: Do not copy bottom pipe when map resource.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: I30658257832be3865f3f3af0b471fd490fab4426
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f1b1dae5399e..c38f71e45381 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1134,6 +1134,9 @@ enum dc_status resource_map_pool_resources(
 			if (!are_stream_backends_same(old_pipe_ctx->stream, stream))
 				continue;
 
+			if (old_pipe_ctx->top_pipe)
+				continue;
+
 			pipe_ctx->stream = stream;
 			copy_pipe_ctx(old_pipe_ctx, pipe_ctx);
 
-- 
2.10.2

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[PATCH 21/27] drm/amd/display: Switch to DRM helpers in s3.

[Harry Wentland]

From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>

Change-Id: I50db672b5b1f2eed7933863a2e901466dcb636d0
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 157 ++--------------------
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   5 +
 drivers/gpu/drm/amd/display/dc/core/dc.c          |   8 +-
 drivers/gpu/drm/amd/display/dc/dc.h               |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/core_dc.h      |   4 -
 5 files changed, 21 insertions(+), 156 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 201c97e1485e..fa4eaf59765b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -457,28 +457,17 @@ static int dm_suspend(void *handle)
 	struct amdgpu_device *adev = handle;
 	struct amdgpu_display_manager *dm = &adev->dm;
 	int ret = 0;
-	struct drm_crtc *crtc;
 
 	s3_handle_mst(adev->ddev, true);
 
-	/* flash all pending vblank events and turn interrupt off
-	 * before disabling CRTCs. They will be enabled back in
-	 * dm_display_resume
-	 */
-	drm_modeset_lock_all(adev->ddev);
-	list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) {
-		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-		if (acrtc->stream)
-				drm_crtc_vblank_off(crtc);
-	}
-	drm_modeset_unlock_all(adev->ddev);
-
 	amdgpu_dm_irq_suspend(adev);
 
+	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
+
 	dc_set_power_state(
 		dm->dc,
-		DC_ACPI_CM_POWER_STATE_D3,
-		DC_VIDEO_POWER_SUSPEND);
+		DC_ACPI_CM_POWER_STATE_D3
+		);
 
 	return ret;
 }
@@ -510,120 +499,6 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
 	return NULL;
 }
 
-static int dm_display_resume(struct drm_device *ddev)
-{
-	int ret = 0;
-	struct drm_connector *connector;
-
-	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
-	struct drm_plane *plane;
-	struct drm_crtc *crtc;
-	struct amdgpu_connector *aconnector;
-	struct drm_connector_state *conn_state;
-
-	if (!state)
-		return ENOMEM;
-
-	state->acquire_ctx = ddev->mode_config.acquire_ctx;
-
-	/* Construct an atomic state to restore previous display setting */
-
-	/*
-	 * Attach connectors to drm_atomic_state
-	 * Should be done in the first place in order to make connectors
-	 * available in state during crtc state processing. It is used for
-	 * making decision if crtc should be disabled in case sink got
-	 * disconnected.
-	 *
-	 * Connectors state crtc with NULL dc_sink should be cleared, because it
-	 * will fail validation during commit
-	 */
-	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
-		aconnector = to_amdgpu_connector(connector);
-		conn_state = drm_atomic_get_connector_state(state, connector);
-
-		ret = PTR_ERR_OR_ZERO(conn_state);
-		if (ret)
-			goto err;
-	}
-
-	/* Attach crtcs to drm_atomic_state*/
-	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
-		struct drm_crtc_state *crtc_state =
-			drm_atomic_get_crtc_state(state, crtc);
-
-		ret = PTR_ERR_OR_ZERO(crtc_state);
-		if (ret)
-			goto err;
-
-		/* force a restore */
-		crtc_state->mode_changed = true;
-	}
-
-
-	/* Attach planes to drm_atomic_state */
-	list_for_each_entry(plane, &ddev->mode_config.plane_list, head) {
-
-		struct drm_crtc *crtc;
-		struct drm_gem_object *obj;
-		struct drm_framebuffer *fb;
-		struct amdgpu_framebuffer *afb;
-		struct amdgpu_bo *rbo;
-		int r;
-		struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane);
-
-		ret = PTR_ERR_OR_ZERO(plane_state);
-		if (ret)
-			goto err;
-
-		crtc = plane_state->crtc;
-		fb = plane_state->fb;
-
-		if (!crtc || !crtc->state || !crtc->state->active)
-			continue;
-
-		if (!fb) {
-			DRM_DEBUG_KMS("No FB bound\n");
-			return 0;
-		}
-
-		/*
-		 * Pin back the front buffers, cursor buffer was already pinned
-		 * back in amdgpu_resume_kms
-		 */
-
-		afb = to_amdgpu_framebuffer(fb);
-
-		obj = afb->obj;
-		rbo = gem_to_amdgpu_bo(obj);
-		r = amdgpu_bo_reserve(rbo, false);
-		if (unlikely(r != 0))
-		       return r;
-
-		r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
-
-		amdgpu_bo_unreserve(rbo);
-
-		if (unlikely(r != 0)) {
-			DRM_ERROR("Failed to pin framebuffer\n");
-			return r;
-		}
-
-	}
-
-
-	/* Call commit internally with the state we just constructed */
-	ret = drm_atomic_commit(state);
-	if (!ret)
-		return 0;
-
-err:
-	DRM_ERROR("Restoring old state failed with %i\n", ret);
-	drm_atomic_state_free(state);
-
-	return ret;
-}
-
 static int dm_resume(void *handle)
 {
 	struct amdgpu_device *adev = handle;
@@ -632,8 +507,8 @@ static int dm_resume(void *handle)
 	/* power on hardware */
 	dc_set_power_state(
 		dm->dc,
-		DC_ACPI_CM_POWER_STATE_D0,
-		DC_VIDEO_POWER_ON);
+		DC_ACPI_CM_POWER_STATE_D0
+		);
 
 	return 0;
 }
@@ -644,8 +519,10 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 	struct amdgpu_display_manager *dm = &adev->dm;
 	struct amdgpu_connector *aconnector;
 	struct drm_connector *connector;
-	int ret = 0;
 	struct drm_crtc *crtc;
+	struct drm_crtc_state *crtc_state;
+	int ret = 0;
+	int i;
 
 	/* program HPD filter */
 	dc_resume(dm->dc);
@@ -659,14 +536,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 	 */
 	amdgpu_dm_irq_resume_early(adev);
 
-	drm_modeset_lock_all(ddev);
-	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
-		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-		if (acrtc->stream)
-				drm_crtc_vblank_on(crtc);
-	}
-	drm_modeset_unlock_all(ddev);
-
 	/* Do detection*/
 	list_for_each_entry(connector,
 			&ddev->mode_config.connector_list, head) {
@@ -684,9 +553,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 		amdgpu_dm_update_connector_after_detect(aconnector);
 	}
 
-	drm_modeset_lock_all(ddev);
-	ret = dm_display_resume(ddev);
-	drm_modeset_unlock_all(ddev);
+	/* Force mode set in atomic comit */
+	for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i)
+			crtc_state->active_changed = true;
+
+	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
 	amdgpu_dm_irq_resume(adev);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index d6ebba012e15..ee69179636a1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -128,6 +128,11 @@ struct amdgpu_display_manager {
 	struct work_struct mst_hotplug_work;
 
 	struct mod_freesync *freesync_module;
+
+	/**
+	 * Caches device atomic state for suspend/resume
+	 */
+	struct drm_atomic_state *cached_state;
 };
 
 /* basic init/fini API */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a39b9987b9d6..edcb731a3aea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1589,21 +1589,15 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
 
 void dc_set_power_state(
 	struct dc *dc,
-	enum dc_acpi_cm_power_state power_state,
-	enum dc_video_power_state video_power_state)
+	enum dc_acpi_cm_power_state power_state)
 {
 	struct core_dc *core_dc = DC_TO_CORE(dc);
 
-	core_dc->previous_power_state = core_dc->current_power_state;
-	core_dc->current_power_state = video_power_state;
-
 	switch (power_state) {
 	case DC_ACPI_CM_POWER_STATE_D0:
 		core_dc->hwss.init_hw(core_dc);
 		break;
 	default:
-		/* NULL means "reset/release all DC streams" */
-		dc_commit_streams(dc, NULL, 0);
 
 		core_dc->hwss.power_down(core_dc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 69ae94bb209f..e2c2a0bf764d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -705,8 +705,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index(
 
 void dc_set_power_state(
 		struct dc *dc,
-		enum dc_acpi_cm_power_state power_state,
-		enum dc_video_power_state video_power_state);
+		enum dc_acpi_cm_power_state power_state);
 void dc_resume(const struct dc *dc);
 
 /*******************************************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index 7a6444dc2957..8d87f490dc1c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -26,10 +26,6 @@ struct core_dc {
 	struct validate_context *scratch_val_ctx;
 	struct resource_pool *res_pool;
 
-	/*Power State*/
-	enum dc_video_power_state previous_power_state;
-	enum dc_video_power_state current_power_state;
-
 	/* Display Engine Clock levels */
 	struct dm_pp_clock_levels sclk_lvls;
 
-- 
2.10.2

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[PATCH 22/27] drm/amd/display: Refactor on dc_sink structure.

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

Change-Id: I47456746d26307356b62379b1cf3c221e5935eb5
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c     | 9 ++++-----
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c     | 4 ++--
 drivers/gpu/drm/amd/display/dc/dc.h               | 2 ++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 2 --
 5 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d275fc88f71e..5ca72afe8f6f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -675,10 +675,6 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
 
 		sink_init_data.link = &link->public;
 		sink_init_data.sink_signal = sink_caps.signal;
-		sink_init_data.dongle_max_pix_clk =
-			sink_caps.max_hdmi_pixel_clock;
-		sink_init_data.converter_disable_audio =
-			converter_disable_audio;
 
 		dc_sink = dc_sink_create(&sink_init_data);
 		if (!dc_sink) {
@@ -686,6 +682,9 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
 			return false;
 		}
 
+		dc_sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
+		dc_sink->converter_disable_audio = converter_disable_audio;
+
 		sink = DC_SINK_TO_CORE(dc_sink);
 		link->public.local_sink = &sink->public;
 
@@ -1361,7 +1360,7 @@ enum dc_status dc_link_validate_mode_timing(
 		struct core_link *link,
 		const struct dc_crtc_timing *timing)
 {
-	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
+	uint32_t max_pix_clk = stream->sink->public.dongle_max_pix_clk;
 
 	/* A hack to avoid failing any modes for EDID override feature on
 	 * topology change such as lower quality cable for DP or different dongle
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c38f71e45381..326019407cb1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1193,7 +1193,7 @@ enum dc_status resource_map_pool_resources(
 			pipe_ctx->stream_enc);
 
 		/* TODO: Add check if ASIC support and EDID audio */
-		if (!stream->sink->converter_disable_audio &&
+		if (!stream->sink->public.converter_disable_audio &&
 			dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
 			stream->public.audio_info.mode_count) {
 			pipe_ctx->audio = find_first_free_audio(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
index 0a805ea1159a..8a204731301d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
@@ -60,8 +60,8 @@ static bool construct(struct sink *sink, const struct dc_sink_init_data *init_pa
 	sink->protected.public.sink_signal = init_params->sink_signal;
 	sink->protected.link = core_link;
 	sink->protected.ctx = core_link->ctx;
-	sink->protected.dongle_max_pix_clk = init_params->dongle_max_pix_clk;
-	sink->protected.converter_disable_audio =
+	sink->protected.public.dongle_max_pix_clk = init_params->dongle_max_pix_clk;
+	sink->protected.public.converter_disable_audio =
 			init_params->converter_disable_audio;
 
 	return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e2c2a0bf764d..c6c0cf500ae8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -653,6 +653,8 @@ struct dc_sink {
 	enum signal_type sink_signal;
 	struct dc_edid dc_edid; /* raw edid */
 	struct dc_edid_caps edid_caps; /* parse display caps */
+	uint32_t dongle_max_pix_clk;
+	bool converter_disable_audio;
 };
 
 void dc_sink_retain(const struct dc_sink *sink);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b29fca9dfeff..faec2292cc27 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -109,8 +109,6 @@ struct core_sink {
 	/* not used for now */
 	struct core_link *link;
 	struct dc_context *ctx;
-	uint32_t dongle_max_pix_clk;
-	bool converter_disable_audio;
 };
 
 /************ link *****************/
-- 
2.10.2

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[PATCH 23/27] drm/amd/display: add init calculation to scaler params

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: Ia77c018ff221edbe933d45a82964a45f5937151d
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |   5 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 245 ++++++++++++++++++---
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |  11 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h      |   4 +-
 5 files changed, 229 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index edcb731a3aea..b9ca9688f8a3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -971,8 +971,7 @@ bool dc_pre_update_surfaces_to_stream(
 					DC_SURFACE_TO_CORE(new_surfaces[i]))
 				continue;
 
-			resource_build_scaling_params(
-				new_surfaces[i], &context->res_ctx.pipe_ctx[j]);
+			resource_build_scaling_params(&context->res_ctx.pipe_ctx[j]);
 		}
 
 	if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
@@ -1364,7 +1363,7 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 				if (pipe_ctx->surface != surface)
 					continue;
 
-				resource_build_scaling_params(updates[i].surface, pipe_ctx);
+				resource_build_scaling_params(pipe_ctx);
 			}
 		}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 326019407cb1..d4b338fa4ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -401,15 +401,17 @@ static void rect_swap_helper(struct rect *rect)
 	rect->y = temp;
 }
 
-static void calculate_viewport(
-		const struct dc_surface *surface,
-		struct pipe_ctx *pipe_ctx)
+static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 {
+	const struct dc_surface *surface = &pipe_ctx->surface->public;
+	struct scaler_data *data = &pipe_ctx->scl_data;
 	struct rect stream_src = pipe_ctx->stream->public.src;
 	struct rect src = surface->src_rect;
 	struct rect dst = surface->dst_rect;
 	struct rect surface_clip = surface->clip_rect;
 	struct rect clip = {0};
+	int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
+			|| data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
 
 
 	if (surface->rotation == ROTATION_ANGLE_90 ||
@@ -442,27 +444,45 @@ static void calculate_viewport(
 	/* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio
 	 * num_pixels = clip.num_pix * scl_ratio
 	 */
-	pipe_ctx->scl_data.viewport.x = src.x + (clip.x - dst.x) *
+	data->viewport.x = src.x + (clip.x - dst.x) *
 			src.width / dst.width;
-	pipe_ctx->scl_data.viewport.width = clip.width *
+	data->viewport.width = clip.width *
 			src.width / dst.width;
 
-	pipe_ctx->scl_data.viewport.y = src.y + (clip.y - dst.y) *
+	data->viewport.y = src.y + (clip.y - dst.y) *
 			src.height / dst.height;
-	pipe_ctx->scl_data.viewport.height = clip.height *
+	data->viewport.height = clip.height *
 			src.height / dst.height;
 
-	/* Minimum viewport such that 420/422 chroma vp is non 0 */
-	if (pipe_ctx->scl_data.viewport.width < 2)
-		pipe_ctx->scl_data.viewport.width = 2;
-	if (pipe_ctx->scl_data.viewport.height < 2)
-		pipe_ctx->scl_data.viewport.height = 2;
+	/* Round down, compensate in init */
+	data->viewport_c.x = data->viewport.x / vpc_div;
+	data->viewport_c.y = data->viewport.y / vpc_div;
+	data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
+			dal_fixed31_32_half : dal_fixed31_32_zero;
+	data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
+			dal_fixed31_32_half : dal_fixed31_32_zero;
+	/* Round up, assume original video size always even dimensions */
+	data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
+	data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
+
+	/* Handle hsplit */
+	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
+		data->viewport.width /= 2;
+		data->viewport_c.width /= 2;
+		data->viewport.x +=  data->viewport.width;
+		data->viewport_c.x +=  data->viewport_c.width;
+		/* Floor primary pipe, ceil 2ndary pipe */
+		data->viewport.width += data->viewport.width % 2;
+		data->viewport_c.width += data->viewport_c.width % 2;
+	} else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
+		data->viewport.width /= 2;
+		data->viewport_c.width /= 2;
+	}
 }
 
-static void calculate_recout(
-		const struct dc_surface *surface,
-		struct pipe_ctx *pipe_ctx)
+static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
 {
+	const struct dc_surface *surface = &pipe_ctx->surface->public;
 	struct core_stream *stream = pipe_ctx->stream;
 	struct rect clip = surface->clip_rect;
 
@@ -493,12 +513,26 @@ static void calculate_recout(
 		pipe_ctx->scl_data.recout.height =
 			stream->public.dst.y + stream->public.dst.height
 						- pipe_ctx->scl_data.recout.y;
+
+	/* Handle hsplit */
+	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
+		pipe_ctx->scl_data.recout.width /= 2;
+		pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
+		/* Floor primary pipe, ceil 2ndary pipe */
+		pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
+	} else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
+		pipe_ctx->scl_data.recout.width /= 2;
+	}
+
+	recout_skip->width = pipe_ctx->scl_data.recout.x - stream->public.dst.x -
+			surface->dst_rect.x * stream->public.dst.width / stream->public.src.width;
+	recout_skip->height = pipe_ctx->scl_data.recout.y - stream->public.dst.y -
+			surface->dst_rect.y * stream->public.dst.height / stream->public.src.height;
 }
 
-static void calculate_scaling_ratios(
-		const struct dc_surface *surface,
-		struct pipe_ctx *pipe_ctx)
+static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 {
+	const struct dc_surface *surface = &pipe_ctx->surface->public;
 	struct core_stream *stream = pipe_ctx->stream;
 	const uint32_t in_w = stream->public.src.width;
 	const uint32_t in_h = stream->public.src.height;
@@ -525,31 +559,179 @@ static void calculate_scaling_ratios(
 	pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
 	pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
 
-	if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12) {
+	if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
+			|| pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
 		pipe_ctx->scl_data.ratios.horz_c.value /= 2;
 		pipe_ctx->scl_data.ratios.vert_c.value /= 2;
 	}
 }
 
-bool resource_build_scaling_params(
-	const struct dc_surface *surface,
-	struct pipe_ctx *pipe_ctx)
+static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
 {
-	bool res;
+	struct scaler_data *data = &pipe_ctx->scl_data;
+	struct rect src = pipe_ctx->surface->public.src_rect;
+	int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
+			|| data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+
+	/*
+	 * Init calculated according to formula:
+	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
+	 * 	init_bot = init + scaling_ratio
+	 * 	init_c = init + truncated_vp_c_offset(from calculate viewport)
+	 */
+	data->inits.h = dal_fixed31_32_div_int(
+			dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
+
+	data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
+			dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
+
+	data->inits.v = dal_fixed31_32_div_int(
+			dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
+
+	data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
+			dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
+
+
+	/* Adjust for viewport end clip-off */
+	if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
+		int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
+		int int_part = dal_fixed31_32_floor(data->inits.h);
+
+		data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
+	}
+	if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
+		int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
+		int int_part = dal_fixed31_32_floor(data->inits.v);
+
+		data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
+	}
+	if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
+		int vp_clip = (src.x + src.width) / vpc_div -
+				data->viewport_c.width - data->viewport_c.x;
+		int int_part = dal_fixed31_32_floor(data->inits.h_c);
+
+		data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
+	}
+	if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
+		int vp_clip = (src.y + src.height) / vpc_div -
+				data->viewport_c.height - data->viewport_c.y;
+		int int_part = dal_fixed31_32_floor(data->inits.v_c);
+
+		data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
+	}
+
+	/* Adjust for non-0 viewport offset */
+	if (data->viewport.x) {
+		int int_part;
+
+		data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
+				data->ratios.horz, recout_skip->width));
+		int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
+		if (int_part < data->taps.h_taps) {
+			int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
+						(data->taps.h_taps - int_part) : data->viewport.x;
+			data->viewport.x -= int_adj;
+			data->viewport.width += int_adj;
+			int_part += int_adj;
+		} else if (int_part > data->taps.h_taps) {
+			data->viewport.x += int_part - data->taps.h_taps;
+			data->viewport.width -= int_part - data->taps.h_taps;
+			int_part = data->taps.h_taps;
+		}
+		data->inits.h.value &= 0xffffffff;
+		data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
+	}
+
+	if (data->viewport_c.x) {
+		int int_part;
+
+		data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
+				data->ratios.horz_c, recout_skip->width));
+		int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
+		if (int_part < data->taps.h_taps_c) {
+			int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
+					(data->taps.h_taps_c - int_part) : data->viewport_c.x;
+			data->viewport_c.x -= int_adj;
+			data->viewport_c.width += int_adj;
+			int_part += int_adj;
+		} else if (int_part > data->taps.h_taps_c) {
+			data->viewport_c.x += int_part - data->taps.h_taps_c;
+			data->viewport_c.width -= int_part - data->taps.h_taps_c;
+			int_part = data->taps.h_taps_c;
+		}
+		data->inits.h_c.value &= 0xffffffff;
+		data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
+	}
+
+	if (data->viewport.y) {
+		int int_part;
+
+		data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
+				data->ratios.vert, recout_skip->height));
+		int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
+		if (int_part < data->taps.v_taps) {
+			int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
+						(data->taps.v_taps - int_part) : data->viewport.y;
+			data->viewport.y -= int_adj;
+			data->viewport.height += int_adj;
+			int_part += int_adj;
+		} else if (int_part > data->taps.v_taps) {
+			data->viewport.y += int_part - data->taps.v_taps;
+			data->viewport.height -= int_part - data->taps.v_taps;
+			int_part = data->taps.v_taps;
+		}
+		data->inits.v.value &= 0xffffffff;
+		data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
+	}
+
+	if (data->viewport_c.y) {
+		int int_part;
+
+		data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
+				data->ratios.vert_c, recout_skip->height));
+		int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
+		if (int_part < data->taps.v_taps_c) {
+			int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
+					(data->taps.v_taps_c - int_part) : data->viewport_c.y;
+			data->viewport_c.y -= int_adj;
+			data->viewport_c.height += int_adj;
+			int_part += int_adj;
+		} else if (int_part > data->taps.v_taps_c) {
+			data->viewport_c.y += int_part - data->taps.v_taps_c;
+			data->viewport_c.height -= int_part - data->taps.v_taps_c;
+			int_part = data->taps.v_taps_c;
+		}
+		data->inits.v_c.value &= 0xffffffff;
+		data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
+	}
+
+	/* Interlaced inits based on final vert inits */
+	data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
+	data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
+}
+
+bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+{
+	const struct dc_surface *surface = &pipe_ctx->surface->public;
 	struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
+	struct view recout_skip = { 0 };
+	bool res = false;
+
 	/* Important: scaling ratio calculation requires pixel format,
 	 * lb depth calculation requires recout and taps require scaling ratios.
+	 * Inits require viewport, taps, ratios and recout of split pipe
 	 */
-	pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(surface->format);
+	pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface(
+			pipe_ctx->surface->public.format);
+
+	calculate_scaling_ratios(pipe_ctx);
 
-	calculate_viewport(surface, pipe_ctx);
+	calculate_viewport(pipe_ctx);
 
 	if (pipe_ctx->scl_data.viewport.height < 16 || pipe_ctx->scl_data.viewport.width < 16)
 		return false;
 
-	calculate_scaling_ratios(surface, pipe_ctx);
-
-	calculate_recout(surface, pipe_ctx);
+	calculate_recout(pipe_ctx, &recout_skip);
 
 	/**
 	 * Setting line buffer pixel depth to 24bpp yields banding
@@ -572,6 +754,9 @@ bool resource_build_scaling_params(
 			pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
 	}
 
+	if (res)
+		calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
+
 	dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
 				"%s: Viewport:\nheight:%d width:%d x:%d "
 				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
@@ -599,9 +784,7 @@ enum dc_status resource_build_scaling_params_for_context(
 	for (i = 0; i < MAX_PIPES; i++) {
 		if (context->res_ctx.pipe_ctx[i].surface != NULL &&
 				context->res_ctx.pipe_ctx[i].stream != NULL)
-			if (!resource_build_scaling_params(
-				&context->res_ctx.pipe_ctx[i].surface->public,
-				&context->res_ctx.pipe_ctx[i]))
+			if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
 				return DC_FAIL_SCALING;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d9dcb37a4f65..041830e05b67 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -927,6 +927,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
 		color->color_b_cb = color_value;
 		break;
 	case PIXEL_FORMAT_420BPP12:
+	case PIXEL_FORMAT_420BPP15:
 		/* set boarder color to green */
 		color->color_g_y = color_value;
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 9c5cb0ee4243..8325a0a47179 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -147,13 +147,24 @@ struct line_buffer_params {
 	enum lb_pixel_depth depth;
 };
 
+struct scl_inits {
+	struct fixed31_32 h;
+	struct fixed31_32 h_c;
+	struct fixed31_32 v;
+	struct fixed31_32 v_bot;
+	struct fixed31_32 v_c;
+	struct fixed31_32 v_c_bot;
+};
+
 struct scaler_data {
 	int h_active;
 	int v_active;
 	struct scaling_taps taps;
 	struct rect viewport;
+	struct rect viewport_c;
 	struct rect recout;
 	struct scaling_ratios ratios;
+	struct scl_inits inits;
 	struct sharpness_adj sharpness;
 	enum pixel_format format;
 	struct line_buffer_params lb_params;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index d96c64bb0a70..eb9c96634578 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -82,9 +82,7 @@ enum dc_status resource_map_pool_resources(
 		const struct core_dc *dc,
 		struct validate_context *context);
 
-bool resource_build_scaling_params(
-		const struct dc_surface *surface,
-		struct pipe_ctx *pipe_ctx);
+bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
 
 enum dc_status resource_build_scaling_params_for_context(
 		const struct core_dc *dc,
-- 
2.10.2

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[PATCH 24/27] drm/amd/display: fix hsplit viewport calculation for rotated/mirrored usecases

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I603f1f04c9bbac3236dfd56b3587b6943e25acd1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 47 +++++++++++++++++------
 1 file changed, 36 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d4b338fa4ab9..e34b52e28e52 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -412,6 +412,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 	struct rect clip = {0};
 	int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
 			|| data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+	bool need_split = (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface)
+		|| (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface);
 
 
 	if (surface->rotation == ROTATION_ANGLE_90 ||
@@ -466,17 +468,40 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 	data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
 
 	/* Handle hsplit */
-	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
-		data->viewport.width /= 2;
-		data->viewport_c.width /= 2;
-		data->viewport.x +=  data->viewport.width;
-		data->viewport_c.x +=  data->viewport_c.width;
-		/* Floor primary pipe, ceil 2ndary pipe */
-		data->viewport.width += data->viewport.width % 2;
-		data->viewport_c.width += data->viewport_c.width % 2;
-	} else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
-		data->viewport.width /= 2;
-		data->viewport_c.width /= 2;
+	if (need_split && (surface->rotation == ROTATION_ANGLE_90 ||
+				surface->rotation == ROTATION_ANGLE_270)) {
+		bool lower_view = (surface->rotation == ROTATION_ANGLE_270) ^
+			(pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface);
+
+		if (lower_view) {
+			data->viewport.height /= 2;
+			data->viewport_c.height /= 2;
+			data->viewport.y +=  data->viewport.height;
+			data->viewport_c.y +=  data->viewport_c.height;
+			/* Ceil offset pipe */
+			data->viewport.height += data->viewport.height % 2;
+			data->viewport_c.height += data->viewport_c.height % 2;
+		} else {
+			data->viewport.height /= 2;
+			data->viewport_c.height /= 2;
+		}
+	} else if (need_split) {
+		bool right_view = (surface->rotation == ROTATION_ANGLE_180) ^
+			(pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) ^
+			surface->horizontal_mirror;
+
+		if (right_view) {
+			data->viewport.width /= 2;
+			data->viewport_c.width /= 2;
+			data->viewport.x +=  data->viewport.width;
+			data->viewport_c.x +=  data->viewport_c.width;
+			/* Ceil offset pipe */
+			data->viewport.width += data->viewport.width % 2;
+			data->viewport_c.width += data->viewport_c.width % 2;
+		} else {
+			data->viewport.width /= 2;
+			data->viewport_c.width /= 2;
+		}
 	}
 }
 
-- 
2.10.2

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[PATCH 25/27] drm/amd/display: fix viewport adjustment on rotated surface

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I1d7db6e097c5a0d307e4d08d70f52542afba0f93
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 133 +++++++++++-----------
 1 file changed, 69 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index e34b52e28e52..01f15052bebf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -404,57 +404,47 @@ static void rect_swap_helper(struct rect *rect)
 static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 {
 	const struct dc_surface *surface = &pipe_ctx->surface->public;
+	const struct dc_stream *stream = &pipe_ctx->stream->public;
 	struct scaler_data *data = &pipe_ctx->scl_data;
-	struct rect stream_src = pipe_ctx->stream->public.src;
-	struct rect src = surface->src_rect;
-	struct rect dst = surface->dst_rect;
-	struct rect surface_clip = surface->clip_rect;
-	struct rect clip = {0};
+	struct rect clip = { 0 };
 	int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
 			|| data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
-	bool need_split = (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface)
-		|| (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface);
-
-
-	if (surface->rotation == ROTATION_ANGLE_90 ||
-	    surface->rotation == ROTATION_ANGLE_270) {
-		rect_swap_helper(&src);
-		rect_swap_helper(&dst);
-		rect_swap_helper(&surface_clip);
-		rect_swap_helper(&stream_src);
-	}
+	bool pri_split = pipe_ctx->bottom_pipe &&
+			pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
+	bool sec_split = pipe_ctx->top_pipe &&
+			pipe_ctx->top_pipe->surface == pipe_ctx->surface;
 
 	/* The actual clip is an intersection between stream
 	 * source and surface clip
 	 */
-	clip.x = stream_src.x > surface_clip.x ?
-			stream_src.x : surface_clip.x;
+	clip.x = stream->src.x > surface->clip_rect.x ?
+			stream->src.x : surface->clip_rect.x;
 
-	clip.width = stream_src.x + stream_src.width <
-			surface_clip.x + surface_clip.width ?
-			stream_src.x + stream_src.width - clip.x :
-			surface_clip.x + surface_clip.width - clip.x ;
+	clip.width = stream->src.x + stream->src.width <
+			surface->clip_rect.x + surface->clip_rect.width ?
+			stream->src.x + stream->src.width - clip.x :
+			surface->clip_rect.x + surface->clip_rect.width - clip.x ;
 
-	clip.y = stream_src.y > surface_clip.y ?
-			stream_src.y : surface_clip.y;
+	clip.y = stream->src.y > surface->clip_rect.y ?
+			stream->src.y : surface->clip_rect.y;
 
-	clip.height = stream_src.y + stream_src.height <
-			surface_clip.y + surface_clip.height ?
-			stream_src.y + stream_src.height - clip.y :
-			surface_clip.y + surface_clip.height - clip.y ;
+	clip.height = stream->src.y + stream->src.height <
+			surface->clip_rect.y + surface->clip_rect.height ?
+			stream->src.y + stream->src.height - clip.y :
+			surface->clip_rect.y + surface->clip_rect.height - clip.y ;
 
-	/* offset = src.ofs + (clip.ofs - dst.ofs) * scl_ratio
+	/* offset = src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
 	 * num_pixels = clip.num_pix * scl_ratio
 	 */
-	data->viewport.x = src.x + (clip.x - dst.x) *
-			src.width / dst.width;
+	data->viewport.x = surface->src_rect.x + (clip.x - surface->dst_rect.x) *
+			surface->src_rect.width / surface->dst_rect.width;
 	data->viewport.width = clip.width *
-			src.width / dst.width;
+			surface->src_rect.width / surface->dst_rect.width;
 
-	data->viewport.y = src.y + (clip.y - dst.y) *
-			src.height / dst.height;
+	data->viewport.y = surface->src_rect.y + (clip.y - surface->dst_rect.y) *
+			surface->src_rect.height / surface->dst_rect.height;
 	data->viewport.height = clip.height *
-			src.height / dst.height;
+			surface->src_rect.height / surface->dst_rect.height;
 
 	/* Round down, compensate in init */
 	data->viewport_c.x = data->viewport.x / vpc_div;
@@ -468,27 +458,15 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 	data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
 
 	/* Handle hsplit */
-	if (need_split && (surface->rotation == ROTATION_ANGLE_90 ||
-				surface->rotation == ROTATION_ANGLE_270)) {
-		bool lower_view = (surface->rotation == ROTATION_ANGLE_270) ^
-			(pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface);
-
-		if (lower_view) {
-			data->viewport.height /= 2;
-			data->viewport_c.height /= 2;
-			data->viewport.y +=  data->viewport.height;
-			data->viewport_c.y +=  data->viewport_c.height;
-			/* Ceil offset pipe */
-			data->viewport.height += data->viewport.height % 2;
-			data->viewport_c.height += data->viewport_c.height % 2;
-		} else {
-			data->viewport.height /= 2;
-			data->viewport_c.height /= 2;
-		}
-	} else if (need_split) {
-		bool right_view = (surface->rotation == ROTATION_ANGLE_180) ^
-			(pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) ^
-			surface->horizontal_mirror;
+	if (pri_split || sec_split) {
+		/* HMirror XOR Secondary_pipe XOR Rotation_180 */
+		bool right_view = (sec_split != surface->horizontal_mirror) !=
+					(surface->rotation == ROTATION_ANGLE_180);
+
+		if (surface->rotation == ROTATION_ANGLE_90
+				|| surface->rotation == ROTATION_ANGLE_270)
+			/* Secondary_pipe XOR Rotation_270 */
+			right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split;
 
 		if (right_view) {
 			data->viewport.width /= 2;
@@ -503,6 +481,12 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
 			data->viewport_c.width /= 2;
 		}
 	}
+
+	if (surface->rotation == ROTATION_ANGLE_90 ||
+			surface->rotation == ROTATION_ANGLE_270) {
+		rect_swap_helper(&data->viewport_c);
+		rect_swap_helper(&data->viewport);
+	}
 }
 
 static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
@@ -559,10 +543,10 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 {
 	const struct dc_surface *surface = &pipe_ctx->surface->public;
 	struct core_stream *stream = pipe_ctx->stream;
-	const uint32_t in_w = stream->public.src.width;
-	const uint32_t in_h = stream->public.src.height;
-	const uint32_t out_w = stream->public.dst.width;
-	const uint32_t out_h = stream->public.dst.height;
+	const int in_w = stream->public.src.width;
+	const int in_h = stream->public.src.height;
+	const int out_w = stream->public.dst.width;
+	const int out_h = stream->public.dst.height;
 
 	pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction(
 					surface->src_rect.width,
@@ -598,6 +582,12 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
 	int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
 			|| data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
 
+	if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
+			pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
+		rect_swap_helper(&data->viewport_c);
+		rect_swap_helper(&data->viewport);
+	}
+
 	/*
 	 * Init calculated according to formula:
 	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
@@ -620,28 +610,36 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
 	/* Adjust for viewport end clip-off */
 	if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
 		int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
-		int int_part = dal_fixed31_32_floor(data->inits.h);
+		int int_part = dal_fixed31_32_floor(
+				dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
 
+		int_part = int_part > 0 ? int_part : 0;
 		data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
 	}
 	if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
 		int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
-		int int_part = dal_fixed31_32_floor(data->inits.v);
+		int int_part = dal_fixed31_32_floor(
+				dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
 
+		int_part = int_part > 0 ? int_part : 0;
 		data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
 	}
 	if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
 		int vp_clip = (src.x + src.width) / vpc_div -
 				data->viewport_c.width - data->viewport_c.x;
-		int int_part = dal_fixed31_32_floor(data->inits.h_c);
+		int int_part = dal_fixed31_32_floor(
+				dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
 
+		int_part = int_part > 0 ? int_part : 0;
 		data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
 	}
 	if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
 		int vp_clip = (src.y + src.height) / vpc_div -
 				data->viewport_c.height - data->viewport_c.y;
-		int int_part = dal_fixed31_32_floor(data->inits.v_c);
+		int int_part = dal_fixed31_32_floor(
+				dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
 
+		int_part = int_part > 0 ? int_part : 0;
 		data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
 	}
 
@@ -733,6 +731,12 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
 	/* Interlaced inits based on final vert inits */
 	data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
 	data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
+
+	if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
+			pipe_ctx->surface->public.rotation == ROTATION_ANGLE_270) {
+		rect_swap_helper(&data->viewport_c);
+		rect_swap_helper(&data->viewport);
+	}
 }
 
 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
@@ -780,6 +784,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 	}
 
 	if (res)
+		/* May need to re-check lb size after this in some obscure scenario */
 		calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
 
 	dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
-- 
2.10.2

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[PATCH 26/27] drm/amd/display: Less log spam

[Harry Wentland]

From: Jordan Lazare <Jordan.Lazare@amd.com>

Change-Id: I499099f788838c17c243d471887a9c56c1747105
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/basics/logger.c          | 4 +++-
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c       | 2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c          | 4 ++--
 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 4 ++--
 drivers/gpu/drm/amd/display/include/logger_types.h      | 1 +
 5 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index a5625a3badab..8f4497332bda 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -32,6 +32,7 @@
 static const struct dc_log_type_info log_type_info_tbl[] = {
 		{LOG_ERROR,                 "Error"},
 		{LOG_WARNING,               "Warning"},
+		{LOG_DEBUG,		    "Debug"},
 		{LOG_DC,                    "DC_Interface"},
 		{LOG_SURFACE,               "Surface"},
 		{LOG_HW_HOTPLUG,            "HW_Hotplug"},
@@ -80,12 +81,13 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
 		(1 << LOG_SYNC) | \
 		(1 << LOG_BANDWIDTH_VALIDATION) | \
 		(1 << LOG_MST) | \
-		(1 << LOG_BIOS) | \
 		(1 << LOG_DETECTION_EDID_PARSER) | \
 		(1 << LOG_DETECTION_DP_CAPS) | \
 		(1 << LOG_BACKLIGHT)) | \
 		(1 << LOG_I2C_AUX) | \
 		(1 << LOG_IF_TRACE) /* | \
+		(1 << LOG_DEBUG) | \
+		(1 << LOG_BIOS) | \
 		(1 << LOG_SURFACE) | \
 		(1 << LOG_SCALER) | \
 		(1 << LOG_DML) | \
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 656c39ac0256..50163a06a653 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -3299,7 +3299,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
 					    opm_object,
 					    &ext_display_connection_info_tbl) != BP_RESULT_OK) {
 
-		dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
+		dm_logger_write(bp->base.ctx->logger, LOG_WARNING,
 				"%s: Failed to read Connection Info Table", __func__);
 		return BP_RESULT_UNSUPPORTED;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 7f52e39ec92a..b94c1e5d85cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -773,8 +773,8 @@ void dce_aud_wall_dto_setup(
 			crtc_info->calculated_pixel_clock,
 			&clock_info);
 
-		dm_logger_write(audio->ctx->logger, LOG_HW_SET_MODE,\
-				"\n************************%s:Input::requested_pixel_clock = %d"\
+		dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
+				"\n%s:Input::requested_pixel_clock = %d"\
 				"calculated_pixel_clock =%d\n"\
 				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
 				crtc_info->requested_pixel_clock,\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index d6662fa2f4e1..f3e1a293351f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -1093,8 +1093,8 @@ static void dce110_se_setup_hdmi_audio(
 		crtc_info->requested_pixel_clock,
 		crtc_info->calculated_pixel_clock,
 		&audio_clock_info)) {
-		dm_logger_write(enc->ctx->logger, LOG_HW_SET_MODE,
-				"\n*********************%s:Input::requested_pixel_clock = %d"\
+		dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
+				"\n%s:Input::requested_pixel_clock = %d"\
 				"calculated_pixel_clock = %d \n", __func__,\
 				crtc_info->requested_pixel_clock,\
 				crtc_info->calculated_pixel_clock);
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index babd6523b105..832d17e1cc49 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -35,6 +35,7 @@ struct dal_logger;
 enum dc_log_type {
 	LOG_ERROR = 0,
 	LOG_WARNING,
+	LOG_DEBUG,
 	LOG_DC,
 	LOG_SURFACE,
 	LOG_HW_HOTPLUG,
-- 
2.10.2

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[PATCH 27/27] drm/amd/display: fix incorrect vp adjustment

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Viewport would be incorrectly adjusted when surface was used
for multiple displays

Change-Id: Iffd7e03973edc72f63d21aa83b0482f6013d2ecd
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 01f15052bebf..6119973c7f0a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -494,6 +494,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip
 	const struct dc_surface *surface = &pipe_ctx->surface->public;
 	struct core_stream *stream = pipe_ctx->stream;
 	struct rect clip = surface->clip_rect;
+	int recout_full_x, recout_full_y;
 
 	pipe_ctx->scl_data.recout.x = stream->public.dst.x;
 	if (stream->public.src.x < clip.x)
@@ -533,10 +534,21 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip
 		pipe_ctx->scl_data.recout.width /= 2;
 	}
 
-	recout_skip->width = pipe_ctx->scl_data.recout.x - stream->public.dst.x -
-			surface->dst_rect.x * stream->public.dst.width / stream->public.src.width;
-	recout_skip->height = pipe_ctx->scl_data.recout.y - stream->public.dst.y -
-			surface->dst_rect.y * stream->public.dst.height / stream->public.src.height;
+	/* Unclipped recout offset = stream dst offset + ((surf dst offset - stream src offset)
+	 * 				* 1/ stream scaling ratio) - (surf src offset * 1/ full scl
+	 * 				ratio)
+	 */
+	recout_full_x = stream->public.dst.x + (surface->dst_rect.x -  stream->public.src.x)
+					* stream->public.dst.width / stream->public.src.width -
+			surface->src_rect.x * surface->dst_rect.width / surface->src_rect.width
+					* stream->public.dst.width / stream->public.src.width;
+	recout_full_y = stream->public.dst.y + (surface->dst_rect.y -  stream->public.src.y)
+					* stream->public.dst.height / stream->public.src.height -
+			surface->src_rect.y * surface->dst_rect.height / surface->src_rect.height
+					* stream->public.dst.height / stream->public.src.height;
+
+	recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x;
+	recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y;
 }
 
 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
-- 
2.10.2

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