* [CI 1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
@ 2017-03-09 10:16 Chris Wilson
2017-03-09 10:16 ` [CI 2/2] HAX enable guc submission for CI Chris Wilson
2017-03-09 11:54 ` ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Patchwork
0 siblings, 2 replies; 4+ messages in thread
From: Chris Wilson @ 2017-03-09 10:16 UTC (permalink / raw)
To: intel-gfx
From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Driver needs to ensure that it doesn't mask the PM interrupts, which are
unmasked/needed by GuC firmware. For that, Driver maintains a bitmask of
interrupts to be kept unmasked, pm_intr_keep.
pm_intr_keep was determined across GuC load. GuC gets loaded in different
scenarios and it is not going to change the pm_intr_keep so this patch
moves its setup to intel_irq_init.
This patch fixes incorrect RPS masking leading to UP interrupts triggered
even when at cur_freq=max and inversly for Down interrupts.
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1488862355-9768-1-git-send-email-sagar.a.kamble@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 24 ++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_loader.c | 26 --------------------------
3 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index df95733cf112..22ac70374ac1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4301,6 +4301,30 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_INFO(dev_priv)->gen >= 8)
dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
+ /*
+ * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
+ * (unmasked) PM interrupts to the GuC. All other bits of this
+ * register *disable* generation of a specific interrupt.
+ *
+ * 'pm_intr_keep' indicates bits that are NOT to be set when
+ * writing to the PM interrupt mask register, i.e. interrupts
+ * that must not be disabled.
+ *
+ * If the GuC is handling these interrupts, then we must not let
+ * the PM code disable ANY interrupt that the GuC is expecting.
+ * So for each ENABLED (0) bit in this register, we must SET the
+ * bit in pm_intr_keep so that it's left enabled for the GuC.
+ * GuC needs ARAT expired interrupt unmasked hence it is set in
+ * pm_intr_keep.
+ *
+ * Here we CLEAR REDIRECT_TO_GUC bit in pm_intr_keep, which will
+ * result in the register bit being left SET!
+ */
+ if (HAS_GUC_SCHED(dev_priv)) {
+ dev_priv->rps.pm_intr_keep |= ARAT_EXPIRED_INTRMSK;
+ dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
+ }
+
if (IS_GEN2(dev_priv)) {
/* Gen2 doesn't have a hardware frame counter */
dev->max_vblank_count = 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc843f96576f..19d42e8813c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7453,7 +7453,8 @@ enum {
#define VLV_RCEDATA _MMIO(0xA0BC)
#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
#define GEN6_PMINTRMSK _MMIO(0xA168)
-#define GEN8_PMINTR_REDIRECT_TO_GUC (1<<31)
+#define GEN8_PMINTR_REDIRECT_TO_GUC (1<<31)
+#define ARAT_EXPIRED_INTRMSK (1<<9)
#define GEN8_MISC_CTRL0 _MMIO(0xA180)
#define VLV_PWRDWNUPCTL _MMIO(0xA294)
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 9885f760f2ef..64cdef479d1d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -114,7 +114,6 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
struct intel_engine_cs *engine;
enum intel_engine_id id;
int irqs;
- u32 tmp;
/* tell all command streamers to forward interrupts (but not vblank) to GuC */
irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
@@ -128,31 +127,6 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
I915_WRITE(GUC_WD_VECS_IER, ~irqs);
-
- /*
- * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
- * (unmasked) PM interrupts to the GuC. All other bits of this
- * register *disable* generation of a specific interrupt.
- *
- * 'pm_intr_keep' indicates bits that are NOT to be set when
- * writing to the PM interrupt mask register, i.e. interrupts
- * that must not be disabled.
- *
- * If the GuC is handling these interrupts, then we must not let
- * the PM code disable ANY interrupt that the GuC is expecting.
- * So for each ENABLED (0) bit in this register, we must SET the
- * bit in pm_intr_keep so that it's left enabled for the GuC.
- *
- * OTOH the REDIRECT_TO_GUC bit is initially SET in pm_intr_keep
- * (so interrupts go to the DISPLAY unit at first); but here we
- * need to CLEAR that bit, which will result in the register bit
- * being left SET!
- */
- tmp = I915_READ(GEN6_PMINTRMSK);
- if (tmp & GEN8_PMINTR_REDIRECT_TO_GUC) {
- dev_priv->rps.pm_intr_keep |= ~tmp;
- dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
- }
}
static u32 get_gttype(struct drm_i915_private *dev_priv)
--
2.11.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* [CI 2/2] HAX enable guc submission for CI
2017-03-09 10:16 [CI 1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Chris Wilson
@ 2017-03-09 10:16 ` Chris Wilson
2017-03-09 11:54 ` ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Patchwork
1 sibling, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2017-03-09 10:16 UTC (permalink / raw)
To: intel-gfx
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 2e9645e6555a..8fa96edddf9f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_loading = 0,
- .enable_guc_submission = 0,
+ .enable_guc_loading = 1,
+ .enable_guc_submission = 1,
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
2017-03-09 10:16 [CI 1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Chris Wilson
2017-03-09 10:16 ` [CI 2/2] HAX enable guc submission for CI Chris Wilson
@ 2017-03-09 11:54 ` Patchwork
2017-03-09 12:04 ` Chris Wilson
1 sibling, 1 reply; 4+ messages in thread
From: Patchwork @ 2017-03-09 11:54 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
URL : https://patchwork.freedesktop.org/series/20980/
State : failure
== Summary ==
Series 20980v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20980/revisions/1/mbox/
Test gem_ctx_create:
Subgroup basic-files:
incomplete -> PASS (fi-skl-6700hq)
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-wb:
pass -> INCOMPLETE (fi-skl-6770hq)
Test gem_ringfill:
Subgroup basic-default-hang:
pass -> INCOMPLETE (fi-bxt-j4205)
pass -> INCOMPLETE (fi-bxt-t5700)
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 466s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 602s
fi-bxt-j4205 total:146 pass:133 dwarn:0 dfail:0 fail:0 skip:12 time: 0s
fi-bxt-t5700 total:146 pass:132 dwarn:0 dfail:0 fail:0 skip:13 time: 0s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 505s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 506s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 437s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 440s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 443s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 506s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 484s
fi-kbl-7500u total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time: 468s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 500s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 568s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 486s
fi-skl-6770hq total:52 pass:50 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 553s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 422s
6fa1f12c25f9c8f71a704c0bae5e0f150e04dacd drm-tip: 2017y-03m-09d-10h-41m-48s UTC integration manifest
ebf3da2 HAX enable guc submission for CI
2b9d11b drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4110/
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
2017-03-09 11:54 ` ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Patchwork
@ 2017-03-09 12:04 ` Chris Wilson
0 siblings, 0 replies; 4+ messages in thread
From: Chris Wilson @ 2017-03-09 12:04 UTC (permalink / raw)
To: intel-gfx
On Thu, Mar 09, 2017 at 11:54:31AM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC
> URL : https://patchwork.freedesktop.org/series/20980/
> State : failure
>
> == Summary ==
>
> Series 20980v1 Series without cover letter
> https://patchwork.freedesktop.org/api/1.0/series/20980/revisions/1/mbox/
>
> Test gem_ctx_create:
> Subgroup basic-files:
> incomplete -> PASS (fi-skl-6700hq)
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-wb:
> pass -> INCOMPLETE (fi-skl-6770hq)
> Test gem_ringfill:
> Subgroup basic-default-hang:
> pass -> INCOMPLETE (fi-bxt-j4205)
> pass -> INCOMPLETE (fi-bxt-t5700)
Two "identical" uncaptured explosions in Broxton, no go.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-03-09 10:16 [CI 1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Chris Wilson
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2017-03-09 11:54 ` ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Initialize pm_intr_keep during intel_irq_init for GuC Patchwork
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