* [CI 1/2] drm/i915/guc: Fix request re-submission after reset
@ 2017-03-09 13:20 Tvrtko Ursulin
2017-03-09 13:20 ` [CI 2/2] HAX enable guc submission for CI Tvrtko Ursulin
2017-03-09 16:47 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset Patchwork
0 siblings, 2 replies; 5+ messages in thread
From: Tvrtko Ursulin @ 2017-03-09 13:20 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
In order to ensure no missed interrupts we must first re-direct
the interrupts to GuC, and only then re-submit the requests to
be replayed after a GPU reset. Otherwise context switch can fire
before GuC has been set up to receive it triggering more hangs.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 32 ++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 21 --------------------
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index beb38e30d0e9..41f2dd87b413 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -936,6 +936,26 @@ static void guc_reset_wq(struct i915_guc_client *client)
client->wq_tail = 0;
}
+static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int irqs;
+
+ /* tell all command streamers to forward interrupts (but not vblank) to GuC */
+ irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
+ for_each_engine(engine, dev_priv, id)
+ I915_WRITE(RING_MODE_GEN7(engine), irqs);
+
+ /* route USER_INTERRUPT to Host, all others are sent to GuC. */
+ irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+ GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
+ /* These three registers have the same bit definitions */
+ I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
+ I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
+ I915_WRITE(GUC_WD_VECS_IER, ~irqs);
+}
+
int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
@@ -953,13 +973,17 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
/* Take over from manual control of ELSP (execlists) */
for_each_engine(engine, dev_priv, id) {
- const int wqi_size = sizeof(struct guc_wq_item);
- struct drm_i915_gem_request *rq;
-
engine->submit_request = i915_guc_submit;
engine->schedule = NULL;
+ }
+
+ guc_interrupts_capture(dev_priv);
+
+ /* Replay the current set of previously submitted requests */
+ for_each_engine(engine, dev_priv, id) {
+ const int wqi_size = sizeof(struct guc_wq_item);
+ struct drm_i915_gem_request *rq;
- /* Replay the current set of previously submitted requests */
spin_lock_irq(&engine->timeline->lock);
list_for_each_entry(rq, &engine->timeline->requests, link) {
guc_client_update_wq_rsvd(client, wqi_size);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 64cdef479d1d..2e24712cf3ee 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -109,26 +109,6 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_WD_VECS_IER, 0);
}
-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- int irqs;
-
- /* tell all command streamers to forward interrupts (but not vblank) to GuC */
- irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
- for_each_engine(engine, dev_priv, id)
- I915_WRITE(RING_MODE_GEN7(engine), irqs);
-
- /* route USER_INTERRUPT to Host, all others are sent to GuC. */
- irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
- GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- /* These three registers have the same bit definitions */
- I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
- I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
- I915_WRITE(GUC_WD_VECS_IER, ~irqs);
-}
-
static u32 get_gttype(struct drm_i915_private *dev_priv)
{
/* XXX: GT type based on PCI device ID? field seems unused by fw */
@@ -503,7 +483,6 @@ int intel_guc_setup(struct drm_i915_private *dev_priv)
err = i915_guc_submission_enable(dev_priv);
if (err)
goto fail;
- guc_interrupts_capture(dev_priv);
}
DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
--
2.9.3
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [CI 2/2] HAX enable guc submission for CI
2017-03-09 13:20 [CI 1/2] drm/i915/guc: Fix request re-submission after reset Tvrtko Ursulin
@ 2017-03-09 13:20 ` Tvrtko Ursulin
2017-03-09 16:47 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset Patchwork
1 sibling, 0 replies; 5+ messages in thread
From: Tvrtko Ursulin @ 2017-03-09 13:20 UTC (permalink / raw)
To: Intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 2e9645e6555a..8fa96edddf9f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -56,8 +56,8 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_loading = 0,
- .enable_guc_submission = 0,
+ .enable_guc_loading = 1,
+ .enable_guc_submission = 1,
.guc_log_level = -1,
.enable_dp_mst = true,
.inject_load_failure = 0,
--
2.9.3
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
2017-03-09 13:20 [CI 1/2] drm/i915/guc: Fix request re-submission after reset Tvrtko Ursulin
2017-03-09 13:20 ` [CI 2/2] HAX enable guc submission for CI Tvrtko Ursulin
@ 2017-03-09 16:47 ` Patchwork
2017-03-09 20:55 ` Chris Wilson
1 sibling, 1 reply; 5+ messages in thread
From: Patchwork @ 2017-03-09 16:47 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
URL : https://patchwork.freedesktop.org/series/20991/
State : success
== Summary ==
Series 20991v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20991/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
incomplete -> PASS (fi-skl-6700k) fdo#100130
fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 474s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 598s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 523s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 576s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 504s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 503s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 437s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 436s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 445s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 492s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 497s
fi-kbl-7500u total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time: 464s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 493s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 584s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 484s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 536s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 552s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 421s
510c200742ced5a91d07e48220b669a3c9b30c0c drm-tip: 2017y-03m-09d-15h-21m-14s UTC integration manifest
938a1af HAX enable guc submission for CI
4c5011d drm/i915/guc: Fix request re-submission after reset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4117/
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
2017-03-09 16:47 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset Patchwork
@ 2017-03-09 20:55 ` Chris Wilson
2017-03-10 7:53 ` Tvrtko Ursulin
0 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2017-03-09 20:55 UTC (permalink / raw)
To: intel-gfx
On Thu, Mar 09, 2017 at 04:47:52PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
> URL : https://patchwork.freedesktop.org/series/20991/
> State : success
>
> == Summary ==
>
> Series 20991v1 Series without cover letter
> https://patchwork.freedesktop.org/api/1.0/series/20991/revisions/1/mbox/
>
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-uc:
> incomplete -> PASS (fi-skl-6700k) fdo#100130
Wait... Did that just fix the bxt fails! My hero! :)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
2017-03-09 20:55 ` Chris Wilson
@ 2017-03-10 7:53 ` Tvrtko Ursulin
0 siblings, 0 replies; 5+ messages in thread
From: Tvrtko Ursulin @ 2017-03-10 7:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Tvrtko Ursulin
On 09/03/2017 20:55, Chris Wilson wrote:
> On Thu, Mar 09, 2017 at 04:47:52PM -0000, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset
>> URL : https://patchwork.freedesktop.org/series/20991/
>> State : success
>>
>> == Summary ==
>>
>> Series 20991v1 Series without cover letter
>> https://patchwork.freedesktop.org/api/1.0/series/20991/revisions/1/mbox/
>>
>> Test gem_exec_flush:
>> Subgroup basic-batch-kernel-default-uc:
>> incomplete -> PASS (fi-skl-6700k) fdo#100130
>
> Wait... Did that just fix the bxt fails! My hero! :)
It was the team effort I think since you found it while testing the
scheduler support.
Pushed now, thanks for the review!
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-03-09 13:20 [CI 1/2] drm/i915/guc: Fix request re-submission after reset Tvrtko Ursulin
2017-03-09 13:20 ` [CI 2/2] HAX enable guc submission for CI Tvrtko Ursulin
2017-03-09 16:47 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/guc: Fix request re-submission after reset Patchwork
2017-03-09 20:55 ` Chris Wilson
2017-03-10 7:53 ` Tvrtko Ursulin
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