From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> To: Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Arnd Bergmann <arnd@arndb.de>, "H. Peter Anvin" <hpa@zytor.com> Cc: Andi Kleen <ak@linux.intel.com>, Dave Hansen <dave.hansen@intel.com>, Andy Lutomirski <luto@amacapital.net>, Michal Hocko <mhocko@suse.com>, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Subject: [PATCH 17/26] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL Date: Mon, 13 Mar 2017 08:50:11 +0300 [thread overview] Message-ID: <20170313055020.69655-18-kirill.shutemov@linux.intel.com> (raw) In-Reply-To: <20170313055020.69655-1-kirill.shutemov@linux.intel.com> Extends pagetable headers to support new paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> --- arch/x86/include/asm/pgtable_64.h | 11 +++++++++++ arch/x86/include/asm/pgtable_64_types.h | 20 +++++++++++++++++++ arch/x86/include/asm/pgtable_types.h | 10 +++++++++- arch/x86/mm/pgtable.c | 34 ++++++++++++++++++++++++++++++++- 4 files changed, 73 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 79396bfdc791..9991224f6238 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -35,6 +35,13 @@ extern void paging_init(void); #define pud_ERROR(e) \ pr_err("%s:%d: bad pud %p(%016lx)\n", \ __FILE__, __LINE__, &(e), pud_val(e)) + +#if CONFIG_PGTABLE_LEVELS >= 5 +#define p4d_ERROR(e) \ + pr_err("%s:%d: bad p4d %p(%016lx)\n", \ + __FILE__, __LINE__, &(e), p4d_val(e)) +#endif + #define pgd_ERROR(e) \ pr_err("%s:%d: bad pgd %p(%016lx)\n", \ __FILE__, __LINE__, &(e), pgd_val(e)) @@ -128,7 +135,11 @@ static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d) static inline void native_p4d_clear(p4d_t *p4d) { +#ifdef CONFIG_X86_5LEVEL + native_set_p4d(p4d, native_make_p4d(0)); +#else native_set_p4d(p4d, (p4d_t) { .pgd = native_make_pgd(0)}); +#endif } static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd) diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 00dc0c2b456e..7ae641fdbd07 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -23,12 +23,32 @@ typedef struct { pteval_t pte; } pte_t; #define SHARED_KERNEL_PMD 0 +#ifdef CONFIG_X86_5LEVEL + +/* + * PGDIR_SHIFT determines what a top-level page table entry can map + */ +#define PGDIR_SHIFT 48 +#define PTRS_PER_PGD 512 + +/* + * 4rd level page in 5-level paging case + */ +#define P4D_SHIFT 39 +#define PTRS_PER_P4D 512 +#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT) +#define P4D_MASK (~(P4D_SIZE - 1)) + +#else /* CONFIG_X86_5LEVEL */ + /* * PGDIR_SHIFT determines what a top-level page table entry can map */ #define PGDIR_SHIFT 39 #define PTRS_PER_PGD 512 +#endif /* CONFIG_X86_5LEVEL */ + /* * 3rd level page */ diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 4930afe9df0a..bf9638e1ee42 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -273,9 +273,17 @@ static inline pgdval_t pgd_flags(pgd_t pgd) } #if CONFIG_PGTABLE_LEVELS > 4 +typedef struct { p4dval_t p4d; } p4d_t; -#error FIXME +static inline p4d_t native_make_p4d(pudval_t val) +{ + return (p4d_t) { val }; +} +static inline p4dval_t native_p4d_val(p4d_t p4d) +{ + return p4d.p4d; +} #else #include <asm-generic/pgtable-nop4d.h> diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 38b6daf72deb..d26b066944a5 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -81,6 +81,14 @@ void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) paravirt_release_pud(__pa(pud) >> PAGE_SHIFT); tlb_remove_page(tlb, virt_to_page(pud)); } + +#if CONFIG_PGTABLE_LEVELS > 4 +void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) +{ + paravirt_release_p4d(__pa(p4d) >> PAGE_SHIFT); + tlb_remove_page(tlb, virt_to_page(p4d)); +} +#endif /* CONFIG_PGTABLE_LEVELS > 4 */ #endif /* CONFIG_PGTABLE_LEVELS > 3 */ #endif /* CONFIG_PGTABLE_LEVELS > 2 */ @@ -120,7 +128,7 @@ static void pgd_ctor(struct mm_struct *mm, pgd_t *pgd) references from swapper_pg_dir. */ if (CONFIG_PGTABLE_LEVELS == 2 || (CONFIG_PGTABLE_LEVELS == 3 && SHARED_KERNEL_PMD) || - CONFIG_PGTABLE_LEVELS == 4) { + CONFIG_PGTABLE_LEVELS >= 4) { clone_pgd_range(pgd + KERNEL_PGD_BOUNDARY, swapper_pg_dir + KERNEL_PGD_BOUNDARY, KERNEL_PGD_PTRS); @@ -582,6 +590,30 @@ void native_set_fixmap(enum fixed_addresses idx, phys_addr_t phys, } #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP +#ifdef CONFIG_X86_5LEVEL +/** + * p4d_set_huge - setup kernel P4D mapping + * + * No 512GB pages yet -- always return 0 + * + * Returns 1 on success and 0 on failure. + */ +int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) +{ + return 0; +} + +/** + * p4d_clear_huge - clear kernel P4D mapping when it is set + * + * No 512GB pages yet -- always return 0 + */ +int p4d_clear_huge(p4d_t *p4d) +{ + return 0; +} +#endif + /** * pud_set_huge - setup kernel PUD mapping * -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> To: Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Arnd Bergmann <arnd@arndb.de>, "H. Peter Anvin" <hpa@zytor.com> Cc: Andi Kleen <ak@linux.intel.com>, Dave Hansen <dave.hansen@intel.com>, Andy Lutomirski <luto@amacapital.net>, Michal Hocko <mhocko@suse.com>, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Subject: [PATCH 17/26] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL Date: Mon, 13 Mar 2017 08:50:11 +0300 [thread overview] Message-ID: <20170313055020.69655-18-kirill.shutemov@linux.intel.com> (raw) In-Reply-To: <20170313055020.69655-1-kirill.shutemov@linux.intel.com> Extends pagetable headers to support new paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> --- arch/x86/include/asm/pgtable_64.h | 11 +++++++++++ arch/x86/include/asm/pgtable_64_types.h | 20 +++++++++++++++++++ arch/x86/include/asm/pgtable_types.h | 10 +++++++++- arch/x86/mm/pgtable.c | 34 ++++++++++++++++++++++++++++++++- 4 files changed, 73 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 79396bfdc791..9991224f6238 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -35,6 +35,13 @@ extern void paging_init(void); #define pud_ERROR(e) \ pr_err("%s:%d: bad pud %p(%016lx)\n", \ __FILE__, __LINE__, &(e), pud_val(e)) + +#if CONFIG_PGTABLE_LEVELS >= 5 +#define p4d_ERROR(e) \ + pr_err("%s:%d: bad p4d %p(%016lx)\n", \ + __FILE__, __LINE__, &(e), p4d_val(e)) +#endif + #define pgd_ERROR(e) \ pr_err("%s:%d: bad pgd %p(%016lx)\n", \ __FILE__, __LINE__, &(e), pgd_val(e)) @@ -128,7 +135,11 @@ static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d) static inline void native_p4d_clear(p4d_t *p4d) { +#ifdef CONFIG_X86_5LEVEL + native_set_p4d(p4d, native_make_p4d(0)); +#else native_set_p4d(p4d, (p4d_t) { .pgd = native_make_pgd(0)}); +#endif } static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd) diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 00dc0c2b456e..7ae641fdbd07 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -23,12 +23,32 @@ typedef struct { pteval_t pte; } pte_t; #define SHARED_KERNEL_PMD 0 +#ifdef CONFIG_X86_5LEVEL + +/* + * PGDIR_SHIFT determines what a top-level page table entry can map + */ +#define PGDIR_SHIFT 48 +#define PTRS_PER_PGD 512 + +/* + * 4rd level page in 5-level paging case + */ +#define P4D_SHIFT 39 +#define PTRS_PER_P4D 512 +#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT) +#define P4D_MASK (~(P4D_SIZE - 1)) + +#else /* CONFIG_X86_5LEVEL */ + /* * PGDIR_SHIFT determines what a top-level page table entry can map */ #define PGDIR_SHIFT 39 #define PTRS_PER_PGD 512 +#endif /* CONFIG_X86_5LEVEL */ + /* * 3rd level page */ diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 4930afe9df0a..bf9638e1ee42 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -273,9 +273,17 @@ static inline pgdval_t pgd_flags(pgd_t pgd) } #if CONFIG_PGTABLE_LEVELS > 4 +typedef struct { p4dval_t p4d; } p4d_t; -#error FIXME +static inline p4d_t native_make_p4d(pudval_t val) +{ + return (p4d_t) { val }; +} +static inline p4dval_t native_p4d_val(p4d_t p4d) +{ + return p4d.p4d; +} #else #include <asm-generic/pgtable-nop4d.h> diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 38b6daf72deb..d26b066944a5 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -81,6 +81,14 @@ void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) paravirt_release_pud(__pa(pud) >> PAGE_SHIFT); tlb_remove_page(tlb, virt_to_page(pud)); } + +#if CONFIG_PGTABLE_LEVELS > 4 +void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) +{ + paravirt_release_p4d(__pa(p4d) >> PAGE_SHIFT); + tlb_remove_page(tlb, virt_to_page(p4d)); +} +#endif /* CONFIG_PGTABLE_LEVELS > 4 */ #endif /* CONFIG_PGTABLE_LEVELS > 3 */ #endif /* CONFIG_PGTABLE_LEVELS > 2 */ @@ -120,7 +128,7 @@ static void pgd_ctor(struct mm_struct *mm, pgd_t *pgd) references from swapper_pg_dir. */ if (CONFIG_PGTABLE_LEVELS == 2 || (CONFIG_PGTABLE_LEVELS == 3 && SHARED_KERNEL_PMD) || - CONFIG_PGTABLE_LEVELS == 4) { + CONFIG_PGTABLE_LEVELS >= 4) { clone_pgd_range(pgd + KERNEL_PGD_BOUNDARY, swapper_pg_dir + KERNEL_PGD_BOUNDARY, KERNEL_PGD_PTRS); @@ -582,6 +590,30 @@ void native_set_fixmap(enum fixed_addresses idx, phys_addr_t phys, } #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP +#ifdef CONFIG_X86_5LEVEL +/** + * p4d_set_huge - setup kernel P4D mapping + * + * No 512GB pages yet -- always return 0 + * + * Returns 1 on success and 0 on failure. + */ +int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) +{ + return 0; +} + +/** + * p4d_clear_huge - clear kernel P4D mapping when it is set + * + * No 512GB pages yet -- always return 0 + */ +int p4d_clear_huge(p4d_t *p4d) +{ + return 0; +} +#endif + /** * pud_set_huge - setup kernel PUD mapping * -- 2.11.0 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
next prev parent reply other threads:[~2017-03-13 5:54 UTC|newest] Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-13 5:49 [PATCH 00/26] x86: 5-level paging enabling for v4.12 Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` [PATCH 01/26] x86: basic changes into headers for 5-level paging Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` [PATCH 02/26] x86: trivial portion of 5-level paging conversion Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` [PATCH 03/26] x86/gup: add 5-level paging support Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` [PATCH 04/26] x86/ident_map: " Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:49 ` [PATCH 05/26] x86/mm: add support of p4d_t in vmalloc_fault() Kirill A. Shutemov 2017-03-13 5:49 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 06/26] x86/power: support p4d_t in hibernate code Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 07/26] x86/kexec: support p4d_t Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 08/26] x86/efi: handle p4d in EFI pagetables Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 09/26] x86/mm/pat: handle additional page table Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 10/26] x86/kasan: prepare clear_pgds() to switch to <asm-generic/pgtable-nop4d.h> Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 11/26] x86/xen: convert __xen_pgd_walk() and xen_cleanmfnmap() to support p4d Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 12/26] x86: convert the rest of the code to support p4d_t Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 13/26] x86: detect 5-level paging support Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 14/26] x86/asm: remove __VIRTUAL_MASK_SHIFT==47 assert Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 15/26] x86/mm: define virtual memory map for 5-level paging Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 16/26] x86/paravirt: make paravirt code support " Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov [this message] 2017-03-13 5:50 ` [PATCH 17/26] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 18/26] x86/dump_pagetables: support 5-level paging Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 19/26] x86/kasan: extend to " Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 7:25 ` Dmitry Vyukov 2017-03-13 7:25 ` Dmitry Vyukov 2017-03-13 5:50 ` [PATCH 20/26] x86/espfix: " Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 21/26] x86/mm: add support of additional page table level during early boot Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 7:18 ` Ingo Molnar 2017-03-13 7:18 ` Ingo Molnar 2017-04-05 11:36 ` Kirill A. Shutemov 2017-04-05 11:36 ` Kirill A. Shutemov 2017-04-05 15:32 ` Kirill A. Shutemov 2017-04-05 15:32 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 22/26] x86/mm: add sync_global_pgds() for configuration with 5-level paging Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 7:22 ` Ingo Molnar 2017-03-13 7:22 ` Ingo Molnar 2017-03-13 5:50 ` [PATCH 23/26] x86/mm: make kernel_physical_mapping_init() support " Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 24/26] x86/mm: add support for 5-level paging for KASLR Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 25/26] x86: enable 5-level paging support Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-13 5:50 ` [PATCH 26/26] x86/mm: allow to have userspace mappings above 47-bits Kirill A. Shutemov 2017-03-13 5:50 ` Kirill A. Shutemov 2017-03-17 17:53 ` Aneesh Kumar K.V 2017-03-17 17:53 ` Aneesh Kumar K.V 2017-03-17 17:53 ` Aneesh Kumar K.V 2017-03-17 17:53 ` Aneesh Kumar K.V 2017-03-17 17:57 ` Kirill A. Shutemov 2017-03-17 17:57 ` Kirill A. Shutemov 2017-03-19 8:24 ` Aneesh Kumar K.V 2017-03-19 8:24 ` Aneesh Kumar K.V 2017-03-19 8:26 ` Kirill A. Shutemov 2017-03-20 18:08 ` hpa 2017-03-20 18:08 ` hpa 2017-03-20 18:38 ` Matthew Wilcox 2017-03-20 18:38 ` Matthew Wilcox 2017-03-24 8:59 ` Kirill A. Shutemov 2017-03-24 8:59 ` Kirill A. Shutemov 2017-03-19 8:55 ` Aneesh Kumar K.V 2017-03-19 8:55 ` Aneesh Kumar K.V 2017-03-24 9:03 ` Kirill A. Shutemov 2017-03-24 9:03 ` Kirill A. Shutemov 2017-03-20 9:15 ` Michael Ellerman 2017-03-20 9:15 ` Michael Ellerman 2017-03-20 5:10 ` Aneesh Kumar K.V 2017-03-20 5:10 ` Aneesh Kumar K.V 2017-03-20 5:10 ` Aneesh Kumar K.V 2017-03-20 5:10 ` Aneesh Kumar K.V 2017-03-24 9:04 ` Kirill A. Shutemov 2017-03-24 9:04 ` Kirill A. Shutemov 2017-03-24 9:14 ` Aneesh Kumar K.V 2017-03-24 9:14 ` Aneesh Kumar K.V 2017-03-24 9:30 ` Kirill A. Shutemov 2017-03-24 9:30 ` Kirill A. Shutemov 2017-03-13 7:49 ` [PATCH 00/26] x86: 5-level paging enabling for v4.12 Ingo Molnar 2017-03-13 7:49 ` Ingo Molnar
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