From: Bjorn Helgaas <helgaas@kernel.org>
To: Mason <slash.tmp@free.fr>
Cc: linux-pci <linux-pci@vger.kernel.org>,
David Laight <david.laight@aculab.com>,
Robin Murphy <robin.murphy@arm.com>,
Thibaud Cornic <thibaud_cornic@sigmadesigns.com>,
Phuong Nguyen <phuong_nguyen@sigmadesigns.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
netdev <netdev@vger.kernel.org>,
Tim Harvey <tharvey@gateworks.com>, Arnd Bergmann <arnd@arndb.de>
Subject: Re: Legacy features in PCI Express devices
Date: Mon, 13 Mar 2017 13:55:04 -0500 [thread overview]
Message-ID: <20170313185504.GC8232@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <ef5c9778-fbae-9f4f-ac2e-29b8597537a5@free.fr>
On Mon, Mar 13, 2017 at 05:10:57PM +0100, Mason wrote:
> Hello,
>
> There are two revisions of our PCI Express controller.
>
> Rev 1 did not support the following features:
>
> 1) legacy PCI interrupt delivery (INTx signals)
> 2) I/O address space
>
> Internally, someone stated that such missing support would prevent
> some PCIe cards from working with our controller.
>
> Are there really modern PCIe cards that require 1) and/or 2)
> to function?
>From a spec point of view, all endpoints, including Legacy, PCI
Express, and Root Complex Integrated Endpoints, are "required to
support MSI or MSI-X or both if an interrupt resource is requested"
(PCIe r3.0, sec 1.3.2).
The same section says Legacy Endpoints are permitted to use I/O
Requests, but PCI Express and Root Complex Integrated Endpoints are
not. There's a little wiggle room in the I/O BAR description; I would
interpret it to mean the latter two varieties are permitted to have
I/O BARs, but they must make the resources described by those BARs
available via a memory BAR as well, so they can operate with I/O
address space.
But that's only in theory; David has already given examples of devices
that don't support MSI, and Greg hinted at new devices that might
require I/O space. I'm particularly curious about that last one,
because there are several host bridges that don't support I/O space at
all.
Bjorn
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Mason <slash.tmp@free.fr>
Cc: Arnd Bergmann <arnd@arndb.de>,
linux-pci <linux-pci@vger.kernel.org>,
Thibaud Cornic <thibaud_cornic@sigmadesigns.com>,
David Laight <david.laight@aculab.com>,
netdev <netdev@vger.kernel.org>,
Phuong Nguyen <phuong_nguyen@sigmadesigns.com>,
Robin Murphy <robin.murphy@arm.com>,
Tim Harvey <tharvey@gateworks.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: Legacy features in PCI Express devices
Date: Mon, 13 Mar 2017 13:55:04 -0500 [thread overview]
Message-ID: <20170313185504.GC8232@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <ef5c9778-fbae-9f4f-ac2e-29b8597537a5@free.fr>
On Mon, Mar 13, 2017 at 05:10:57PM +0100, Mason wrote:
> Hello,
>
> There are two revisions of our PCI Express controller.
>
> Rev 1 did not support the following features:
>
> 1) legacy PCI interrupt delivery (INTx signals)
> 2) I/O address space
>
> Internally, someone stated that such missing support would prevent
> some PCIe cards from working with our controller.
>
> Are there really modern PCIe cards that require 1) and/or 2)
> to function?
>From a spec point of view, all endpoints, including Legacy, PCI
Express, and Root Complex Integrated Endpoints, are "required to
support MSI or MSI-X or both if an interrupt resource is requested"
(PCIe r3.0, sec 1.3.2).
The same section says Legacy Endpoints are permitted to use I/O
Requests, but PCI Express and Root Complex Integrated Endpoints are
not. There's a little wiggle room in the I/O BAR description; I would
interpret it to mean the latter two varieties are permitted to have
I/O BARs, but they must make the resources described by those BARs
available via a memory BAR as well, so they can operate with I/O
address space.
But that's only in theory; David has already given examples of devices
that don't support MSI, and Greg hinted at new devices that might
require I/O space. I'm particularly curious about that last one,
because there are several host bridges that don't support I/O space at
all.
Bjorn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: helgaas@kernel.org (Bjorn Helgaas)
To: linux-arm-kernel@lists.infradead.org
Subject: Legacy features in PCI Express devices
Date: Mon, 13 Mar 2017 13:55:04 -0500 [thread overview]
Message-ID: <20170313185504.GC8232@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <ef5c9778-fbae-9f4f-ac2e-29b8597537a5@free.fr>
On Mon, Mar 13, 2017 at 05:10:57PM +0100, Mason wrote:
> Hello,
>
> There are two revisions of our PCI Express controller.
>
> Rev 1 did not support the following features:
>
> 1) legacy PCI interrupt delivery (INTx signals)
> 2) I/O address space
>
> Internally, someone stated that such missing support would prevent
> some PCIe cards from working with our controller.
>
> Are there really modern PCIe cards that require 1) and/or 2)
> to function?
>From a spec point of view, all endpoints, including Legacy, PCI
Express, and Root Complex Integrated Endpoints, are "required to
support MSI or MSI-X or both if an interrupt resource is requested"
(PCIe r3.0, sec 1.3.2).
The same section says Legacy Endpoints are permitted to use I/O
Requests, but PCI Express and Root Complex Integrated Endpoints are
not. There's a little wiggle room in the I/O BAR description; I would
interpret it to mean the latter two varieties are permitted to have
I/O BARs, but they must make the resources described by those BARs
available via a memory BAR as well, so they can operate with I/O
address space.
But that's only in theory; David has already given examples of devices
that don't support MSI, and Greg hinted at new devices that might
require I/O space. I'm particularly curious about that last one,
because there are several host bridges that don't support I/O space at
all.
Bjorn
next prev parent reply other threads:[~2017-03-13 18:55 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-13 16:10 Legacy features in PCI Express devices Mason
2017-03-13 16:10 ` Mason
2017-03-13 11:08 ` Greg
2017-03-13 11:08 ` Greg
2017-03-13 11:08 ` Greg
2017-03-13 17:12 ` Robin Murphy
2017-03-13 17:12 ` Robin Murphy
2017-03-13 17:39 ` Mason
2017-03-13 17:39 ` Mason
2017-03-13 17:55 ` Robin Murphy
2017-03-13 17:55 ` Robin Murphy
2017-03-13 17:24 ` David Daney
2017-03-13 17:24 ` David Daney
2017-03-13 18:55 ` Bjorn Helgaas [this message]
2017-03-13 18:55 ` Bjorn Helgaas
2017-03-13 18:55 ` Bjorn Helgaas
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