[PATCH 1/7] drm/i915: Move residency calculation into intel_pm.c

[PATCH 1/7] drm/i915: Move residency calculation into intel_pm.c

[Mika Kuoppala]

Plan is to make generic residency calculation utility
function for usage outside of sysfs. As a first step
move residency calculation into intel_pm.c

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  2 ++
 drivers/gpu/drm/i915/i915_sysfs.c | 27 +--------------------------
 drivers/gpu/drm/i915/intel_pm.c   | 31 +++++++++++++++++++++++++++++++
 3 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48ff648..4aee323 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3874,6 +3874,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
+u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
+			i915_reg_t reg);
 
 #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
 #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index af0ac9f..ab723e3 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -42,32 +42,7 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
 static u32 calc_residency(struct drm_i915_private *dev_priv,
 			  i915_reg_t reg)
 {
-	u64 raw_time; /* 32b value may overflow during fixed point math */
-	u64 units = 128ULL, div = 100000ULL;
-	u32 ret;
-
-	if (!intel_enable_rc6())
-		return 0;
-
-	intel_runtime_pm_get(dev_priv);
-
-	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		units = 1;
-		div = dev_priv->czclk_freq;
-
-		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
-			units <<= 8;
-	} else if (IS_GEN9_LP(dev_priv)) {
-		units = 1;
-		div = 1200;		/* 833.33ns */
-	}
-
-	raw_time = I915_READ(reg) * units;
-	ret = DIV_ROUND_UP_ULL(raw_time, div);
-
-	intel_runtime_pm_put(dev_priv);
-	return ret;
+	return intel_rc6_residency(dev_priv, reg);
 }
 
 static ssize_t
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2ca38ae..a4a2c23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8349,3 +8349,34 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	dev_priv->pm.suspended = false;
 	atomic_set(&dev_priv->pm.wakeref_count, 0);
 }
+
+u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
+			i915_reg_t reg)
+{
+	u64 raw_time; /* 32b value may overflow during fixed point math */
+	u64 units = 128ULL, div = 100000ULL;
+	u32 ret;
+
+	if (!intel_enable_rc6())
+		return 0;
+
+	intel_runtime_pm_get(dev_priv);
+
+	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+		units = 1;
+		div = dev_priv->czclk_freq;
+
+		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
+			units <<= 8;
+	} else if (IS_GEN9_LP(dev_priv)) {
+		units = 1;
+		div = 1200;		/* 833.33ns */
+	}
+
+	raw_time = I915_READ(reg) * units;
+	ret = DIV_ROUND_UP_ULL(raw_time, div);
+
+	intel_runtime_pm_put(dev_priv);
+	return ret;
+}
-- 
2.7.4

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[PATCH 2/7] drm/i915: Return residency as microseconds

[Mika Kuoppala]

Change the granularity from milliseconds to microseconds
when returning rc6 residencies. This is in preparation
for increased resolution on some platforms.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
 drivers/gpu/drm/i915/i915_sysfs.c |  2 +-
 drivers/gpu/drm/i915/intel_pm.c   | 12 ++++++------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4aee323..0023e21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3874,8 +3874,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
-u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
-			i915_reg_t reg);
+u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
+			   const i915_reg_t reg);
 
 #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
 #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ab723e3..a0b35a8 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -42,7 +42,7 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
 static u32 calc_residency(struct drm_i915_private *dev_priv,
 			  i915_reg_t reg)
 {
-	return intel_rc6_residency(dev_priv, reg);
+	return DIV_ROUND_UP(intel_rc6_residency_us(dev_priv, reg), 1000);
 }
 
 static ssize_t
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a4a2c23..da742a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8350,12 +8350,12 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	atomic_set(&dev_priv->pm.wakeref_count, 0);
 }
 
-u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
-			i915_reg_t reg)
+u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
+			   const i915_reg_t reg)
 {
 	u64 raw_time; /* 32b value may overflow during fixed point math */
-	u64 units = 128ULL, div = 100000ULL;
-	u32 ret;
+	u64 units = 128000ULL, div = 100000ULL;
+	u64 ret;
 
 	if (!intel_enable_rc6())
 		return 0;
@@ -8364,13 +8364,13 @@ u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
 
 	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		units = 1;
+		units = 1000;
 		div = dev_priv->czclk_freq;
 
 		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
 			units <<= 8;
 	} else if (IS_GEN9_LP(dev_priv)) {
-		units = 1;
+		units = 1000;
 		div = 1200;		/* 833.33ns */
 	}
 
-- 
2.7.4

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Re: [PATCH 2/7] drm/i915: Return residency as microseconds

[Chris Wilson]

On Tue, Mar 14, 2017 at 03:17:24PM +0200, Mika Kuoppala wrote:
> Change the granularity from milliseconds to microseconds
> when returning rc6 residencies. This is in preparation
> for increased resolution on some platforms.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 ++--
>  drivers/gpu/drm/i915/i915_sysfs.c |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c   | 12 ++++++------
>  3 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4aee323..0023e21 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3874,8 +3874,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> -u32 intel_rc6_residency(struct drm_i915_private *dev_priv,
> -			i915_reg_t reg);
> +u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> +			   const i915_reg_t reg);
>  
>  #define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
>  #define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index ab723e3..a0b35a8 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -42,7 +42,7 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
>  static u32 calc_residency(struct drm_i915_private *dev_priv,
>  			  i915_reg_t reg)
>  {
> -	return intel_rc6_residency(dev_priv, reg);
> +	return DIV_ROUND_UP(intel_rc6_residency_us(dev_priv, reg), 1000);

Is DIV_ROUND_UP() 64bit safe? I think this needs DIV_ROUND_UP_ULL()
-Chris

-- 
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[PATCH 3/7] drm/i915: Extend vlv/chv residency resolution

[Mika Kuoppala]

The high counter value bit can be used to get 8 bits more
of range out of the same residency counter registers.

Lets toggle this bit on and off on vlv/chv while reading the
counters to push the wrap from 13 seconds to 54 minutes.

Reported-by: Len Brown <len.brown@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 47 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index da742a9..7e7a8d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8350,6 +8350,44 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	atomic_set(&dev_priv->pm.wakeref_count, 0);
 }
 
+static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
+			     const i915_reg_t reg)
+{
+	u32 lower, upper, tmp, saved_ctl;
+
+	/* The register accessed do not need forcewake. We borrow
+	 * uncore lock to prevent concurrent access to range reg.
+	 */
+	spin_lock_irq(&dev_priv->uncore.lock);
+	saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL);
+
+	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
+		I915_WRITE_FW(VLV_COUNTER_CONTROL,
+			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
+
+	tmp = I915_READ_FW(reg);
+	do {
+		upper = tmp;
+
+		I915_WRITE_FW(VLV_COUNTER_CONTROL,
+			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
+		lower = I915_READ_FW(reg);
+
+		I915_WRITE_FW(VLV_COUNTER_CONTROL,
+			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
+
+		tmp = I915_READ_FW(reg);
+	} while (upper != tmp);
+
+	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
+		I915_WRITE_FW(VLV_COUNTER_CONTROL,
+			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
+
+	spin_unlock_irq(&dev_priv->uncore.lock);
+
+	return lower | (u64)upper << 8;
+}
+
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
 			   const i915_reg_t reg)
 {
@@ -8367,15 +8405,16 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
 		units = 1000;
 		div = dev_priv->czclk_freq;
 
-		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
-			units <<= 8;
+		raw_time = vlv_residency_raw(dev_priv, reg);
+		goto out;
 	} else if (IS_GEN9_LP(dev_priv)) {
 		units = 1000;
 		div = 1200;		/* 833.33ns */
 	}
 
-	raw_time = I915_READ(reg) * units;
-	ret = DIV_ROUND_UP_ULL(raw_time, div);
+	raw_time = I915_READ(reg);
+out:
+	ret = DIV_ROUND_UP_ULL(raw_time * units, div);
 
 	intel_runtime_pm_put(dev_priv);
 	return ret;
-- 
2.7.4

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Re: [PATCH 3/7] drm/i915: Extend vlv/chv residency resolution

[Chris Wilson]

On Tue, Mar 14, 2017 at 03:17:25PM +0200, Mika Kuoppala wrote:
> The high counter value bit can be used to get 8 bits more
> of range out of the same residency counter registers.

Please do note that it is internally a 40bit register with a 32bit
window (and a similar comment in code).

> Lets toggle this bit on and off on vlv/chv while reading the
> counters to push the wrap from 13 seconds to 54 minutes.
> 
> Reported-by: Len Brown <len.brown@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 47 +++++++++++++++++++++++++++++++++++++----
>  1 file changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index da742a9..7e7a8d9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8350,6 +8350,44 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
>  	atomic_set(&dev_priv->pm.wakeref_count, 0);
>  }
>  
> +static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
> +			     const i915_reg_t reg)
> +{
> +	u32 lower, upper, tmp, saved_ctl;
> +
> +	/* The register accessed do not need forcewake. We borrow
> +	 * uncore lock to prevent concurrent access to range reg.
> +	 */
> +	spin_lock_irq(&dev_priv->uncore.lock);
> +	saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL);
> +
> +	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
> +		I915_WRITE_FW(VLV_COUNTER_CONTROL,
> +			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> +
> +	tmp = I915_READ_FW(reg);

Do upper = READ;
> +	do {
> +		upper = tmp;
		tmp = upper;
> +
> +		I915_WRITE_FW(VLV_COUNTER_CONTROL,
> +			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> +		lower = I915_READ_FW(reg);
> +
> +		I915_WRITE_FW(VLV_COUNTER_CONTROL,
> +			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> +

Kill this newline, so both look equivalent (i.e. so that the write is
always coupled with the read).

> +		tmp = I915_READ_FW(reg);
		upper = READ

Then the lower/upper are clearly read together in the same loop, with
the wraparound condition checked.

> +	} while (upper != tmp);
> +
> +	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
> +		I915_WRITE_FW(VLV_COUNTER_CONTROL,
> +			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> +
> +	spin_unlock_irq(&dev_priv->uncore.lock);
> +
> +	return lower | (u64)upper << 8;
> +}
> +
>  u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
>  			   const i915_reg_t reg)
>  {
> @@ -8367,15 +8405,16 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
>  		units = 1000;
>  		div = dev_priv->czclk_freq;
>  
> -		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
> -			units <<= 8;
> +		raw_time = vlv_residency_raw(dev_priv, reg);
> +		goto out;
>  	} else if (IS_GEN9_LP(dev_priv)) {
>  		units = 1000;
>  		div = 1200;		/* 833.33ns */
>  	}
>  
> -	raw_time = I915_READ(reg) * units;
> -	ret = DIV_ROUND_UP_ULL(raw_time, div);
> +	raw_time = I915_READ(reg);
> +out:

Do we need the goto? just move this I915_READ into the branches?

> +	ret = DIV_ROUND_UP_ULL(raw_time * units, div);

-- 
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[PATCH 4/7] drm/i915: Convert debugfs to use generic residency calculator

[Mika Kuoppala]

Use intel_rc6_residency to get benefit for increased resolution
in byt/chv.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9db6b04..407a198 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1487,10 +1487,10 @@ static int vlv_drpc_info(struct seq_file *m)
 	seq_printf(m, "Media Power Well: %s\n",
 		   (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
 
-	seq_printf(m, "Render RC6 residency since boot: %u\n",
-		   I915_READ(VLV_GT_RENDER_RC6));
-	seq_printf(m, "Media RC6 residency since boot: %u\n",
-		   I915_READ(VLV_GT_MEDIA_RC6));
+	seq_printf(m, "Render RC6 residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, VLV_GT_RENDER_RC6));
+	seq_printf(m, "Media RC6 residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, VLV_GT_MEDIA_RC6));
 
 	return i915_forcewake_domains(m, NULL);
 }
@@ -1583,14 +1583,14 @@ static int gen6_drpc_info(struct seq_file *m)
 	}
 
 	/* Not exactly sure what this is */
-	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
-		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
-	seq_printf(m, "RC6 residency since boot: %u\n",
-		   I915_READ(GEN6_GT_GFX_RC6));
-	seq_printf(m, "RC6+ residency since boot: %u\n",
-		   I915_READ(GEN6_GT_GFX_RC6p));
-	seq_printf(m, "RC6++ residency since boot: %u\n",
-		   I915_READ(GEN6_GT_GFX_RC6pp));
+	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, GEN6_GT_GFX_RC6_LOCKED));
+	seq_printf(m, "RC6 residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, GEN6_GT_GFX_RC6));
+	seq_printf(m, "RC6+ residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, GEN6_GT_GFX_RC6p));
+	seq_printf(m, "RC6++ residency since boot: %llu us\n",
+		   intel_rc6_residency_us(dev_priv, GEN6_GT_GFX_RC6pp));
 
 	seq_printf(m, "RC6   voltage: %dmV\n",
 		   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
-- 
2.7.4

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Re: [PATCH 4/7] drm/i915: Convert debugfs to use generic residency calculator

[Chris Wilson]

On Tue, Mar 14, 2017 at 03:17:26PM +0200, Mika Kuoppala wrote:
> Use intel_rc6_residency to get benefit for increased resolution
> in byt/chv.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

I was thinking what's the point, but
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

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[PATCH 5/7] drm/i915: Use cpu clock to calculate rc0 residency

[Mika Kuoppala]

Avoid more costly punit access and use the local cpu clock.
The time diff between separate processor units is irrelevant in
our rc0 residency granularity so we can ignore it.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_irq.c | 10 ++++------
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0023e21..70e335c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1323,7 +1323,7 @@ struct vlv_s0ix_state {
 };
 
 struct intel_rps_ei {
-	u32 cz_clock;
+	u64 cpu_clock;
 	u32 render_c0;
 	u32 media_c0;
 };
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 31f0d7c..00e7875 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1076,7 +1076,7 @@ static void notify_ring(struct intel_engine_cs *engine)
 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 			struct intel_rps_ei *ei)
 {
-	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
+	ei->cpu_clock = local_clock();
 	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 }
@@ -1096,19 +1096,17 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 		return 0;
 
 	vlv_c0_read(dev_priv, &now);
-	if (now.cz_clock == 0)
-		return 0;
 
-	if (prev->cz_clock) {
+	if (prev->cpu_clock) {
 		u64 time, c0;
 		u32 render, media;
 		unsigned int mul;
 
-		mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
+		mul = 1000 * 1000 * 100; /* scale to threshold% */
 		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
 			mul <<= 8;
 
-		time = now.cz_clock - prev->cz_clock;
+		time = now.cpu_clock - prev->cpu_clock;
 		time *= dev_priv->czclk_freq;
 
 		/* Workload can be split between render + media,
-- 
2.7.4

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Re: [PATCH 5/7] drm/i915: Use cpu clock to calculate rc0 residency

[Chris Wilson]

On Tue, Mar 14, 2017 at 03:17:27PM +0200, Mika Kuoppala wrote:
> Avoid more costly punit access and use the local cpu clock.
> The time diff between separate processor units is irrelevant in
> our rc0 residency granularity so we can ignore it.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c | 10 ++++------
>  2 files changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0023e21..70e335c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1323,7 +1323,7 @@ struct vlv_s0ix_state {
>  };
>  
>  struct intel_rps_ei {
> -	u32 cz_clock;
> +	u64 cpu_clock;
>  	u32 render_c0;
>  	u32 media_c0;
>  };
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 31f0d7c..00e7875 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1076,7 +1076,7 @@ static void notify_ring(struct intel_engine_cs *engine)
>  static void vlv_c0_read(struct drm_i915_private *dev_priv,
>  			struct intel_rps_ei *ei)
>  {
> -	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
> +	ei->cpu_clock = local_clock();

local_clock() is specific to a single cpu.

ktime_t ktime_get().

ktime_to_ns(ktime_sub(now.cpu_clock, prev->cpu_clock));
-chris

-- 
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Re: [PATCH 5/7] drm/i915: Use cpu clock to calculate rc0 residency

[Ville Syrjälä]

On Tue, Mar 14, 2017 at 01:30:40PM +0000, Chris Wilson wrote:
> On Tue, Mar 14, 2017 at 03:17:27PM +0200, Mika Kuoppala wrote:
> > Avoid more costly punit access and use the local cpu clock.
> > The time diff between separate processor units is irrelevant in
> > our rc0 residency granularity so we can ignore it.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h |  2 +-
> >  drivers/gpu/drm/i915/i915_irq.c | 10 ++++------
> >  2 files changed, 5 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 0023e21..70e335c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1323,7 +1323,7 @@ struct vlv_s0ix_state {
> >  };
> >  
> >  struct intel_rps_ei {
> > -	u32 cz_clock;
> > +	u64 cpu_clock;
> >  	u32 render_c0;
> >  	u32 media_c0;
> >  };
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 31f0d7c..00e7875 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1076,7 +1076,7 @@ static void notify_ring(struct intel_engine_cs *engine)
> >  static void vlv_c0_read(struct drm_i915_private *dev_priv,
> >  			struct intel_rps_ei *ei)
> >  {
> > -	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
> > +	ei->cpu_clock = local_clock();
> 
> local_clock() is specific to a single cpu.
> 
> ktime_t ktime_get().

Perhaps _raw() so that ntp adjustment doesn't change things
over time? But I guess it shouldn't matter all that much
either way.

> 
> ktime_to_ns(ktime_sub(now.cpu_clock, prev->cpu_clock));

There's no ktime_ns_delta() it seems. There is ktime_us_delta()
and ktime_ms_delta() if you don't need ns resolution.

-- 
Ville Syrjälä
Intel OTC
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[PATCH 6/7] drm/i915: Use coarse grained residency counter with byt

[Mika Kuoppala]

Set byt rc residency counters high level as chv does by
default. We lose some accuracy on byt but we can do the calculation
without extra hw read on both platforms, as now they behave
identically in this respect.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 9 ++-------
 drivers/gpu/drm/i915/intel_pm.c | 9 +++------
 2 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 00e7875..5ec12cf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1100,14 +1100,9 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 	if (prev->cpu_clock) {
 		u64 time, c0;
 		u32 render, media;
-		unsigned int mul;
-
-		mul = 1000 * 1000 * 100; /* scale to threshold% */
-		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
-			mul <<= 8;
 
 		time = now.cpu_clock - prev->cpu_clock;
-		time *= dev_priv->czclk_freq;
+		time *= dev_priv->czclk_freq >> 8;
 
 		/* Workload can be split between render + media,
 		 * e.g. SwapBuffers being blitted in X after being rendered in
@@ -1117,7 +1112,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 		render = now.render_c0 - prev->render_c0;
 		media = now.media_c0 - prev->media_c0;
 		c0 = max(render, media);
-		c0 *= mul;
+		c0 *= 1000 * 1000 * 100; /* scale to threshold% */
 
 		if (c0 > time * dev_priv->rps.up_threshold)
 			events = GEN6_PM_RP_UP_THRESHOLD;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e7a8d9..f1a4234 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6392,7 +6392,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
 
 	/* allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,
-		   _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
+		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+				      VLV_MEDIA_RC0_COUNT_EN |
 				      VLV_RENDER_RC0_COUNT_EN |
 				      VLV_MEDIA_RC6_COUNT_EN |
 				      VLV_RENDER_RC6_COUNT_EN));
@@ -8361,7 +8362,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 	spin_lock_irq(&dev_priv->uncore.lock);
 	saved_ctl = I915_READ_FW(VLV_COUNTER_CONTROL);
 
-	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
+	if (WARN_ON(!(saved_ctl & VLV_COUNT_RANGE_HIGH)))
 		I915_WRITE_FW(VLV_COUNTER_CONTROL,
 			      _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
 
@@ -8379,10 +8380,6 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
 		tmp = I915_READ_FW(reg);
 	} while (upper != tmp);
 
-	if (!(saved_ctl & VLV_COUNT_RANGE_HIGH))
-		I915_WRITE_FW(VLV_COUNTER_CONTROL,
-			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
-
 	spin_unlock_irq(&dev_priv->uncore.lock);
 
 	return lower | (u64)upper << 8;
-- 
2.7.4

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[PATCH 7/7] drm/i915: Upclock on the first residency calculation

[Mika Kuoppala]

After ei reset, upclock as default if we don't have a previous
timestamp at hand. We might at sometimes waste one interval
of more power but also be more agile if we need to ramp up.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5ec12cf..aacb654 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1118,6 +1118,8 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 			events = GEN6_PM_RP_UP_THRESHOLD;
 		else if (c0 < time * dev_priv->rps.down_threshold)
 			events = GEN6_PM_RP_DOWN_THRESHOLD;
+	} else {
+		events = GEN6_PM_RP_UP_THRESHOLD;
 	}
 
 	dev_priv->rps.ei = now;
-- 
2.7.4

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Re: [PATCH 7/7] drm/i915: Upclock on the first residency calculation

[Chris Wilson]

On Tue, Mar 14, 2017 at 03:17:29PM +0200, Mika Kuoppala wrote:
> After ei reset, upclock as default if we don't have a previous
> timestamp at hand. We might at sometimes waste one interval
> of more power but also be more agile if we need to ramp up.

Why? There is nothing special about the first EI interval - it doesn't
correspond to GPU activity. We already start from rpe which is about 75%
of max on that platform. At the first sign that we are underperforming
we will overcompensate.
-Chris

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Re: [PATCH 7/7] drm/i915: Upclock on the first residency calculation

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> On Tue, Mar 14, 2017 at 03:17:29PM +0200, Mika Kuoppala wrote:
>> After ei reset, upclock as default if we don't have a previous
>> timestamp at hand. We might at sometimes waste one interval
>> of more power but also be more agile if we need to ramp up.
>
> Why? There is nothing special about the first EI interval - it doesn't
> correspond to GPU activity. We already start from rpe which is about 75%
> of max on that platform. At the first sign that we are underperforming
> we will overcompensate.

Then I have misunderstood the rampup and need to reread it. This patch
can be ignored.

-Mika

> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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✗ Fi.CI.BAT: warning for series starting with [1/7] drm/i915: Move residency calculation into intel_pm.c

[Patchwork]

== Series Details ==

Series: series starting with [1/7] drm/i915: Move residency calculation into intel_pm.c
URL   : https://patchwork.freedesktop.org/series/21217/
State : warning

== Summary ==

Series 21217v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21217/revisions/1/mbox/

Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> DMESG-WARN (fi-bsw-n3050)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2520m)
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-bsw-n3050) fdo#100113

fdo#100113 https://bugs.freedesktop.org/show_bug.cgi?id=100113

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 470s
fi-bsw-n3050     total:278  pass:237  dwarn:2   dfail:0   fail:0   skip:39  time: 573s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 539s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 560s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 504s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 500s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 435s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 436s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 449s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 520s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 498s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 479s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 482s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 605s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 483s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 512s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 545s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 411s

c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
f48c6b4 drm/i915: Upclock on the first residency calculation
e1fcfbc drm/i915: Use coarse grained residency counter with byt
0b956b1 drm/i915: Use cpu clock to calculate rc0 residency
e7dff5f drm/i915: Convert debugfs to use generic residency calculator
86cfc4e drm/i915: Extend vlv/chv residency resolution
65c1b89 drm/i915: Return residency as microseconds
ae4e79d drm/i915: Move residency calculation into intel_pm.c

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4163/
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