* [PATCH v5 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition @ 2017-03-12 10:03 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. JC. Jayachandran C (2): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 --------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 +++++++++++++++++++++ 8 files changed, 190 insertions(+), 181 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition @ 2017-03-12 10:03 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: linux-arm-kernel Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. JC. Jayachandran C (2): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 --------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 +++++++++++++++++++++ 8 files changed, 190 insertions(+), 181 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 ^ permalink raw reply [flat|nested] 34+ messages in thread
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* [PATCH v5 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation 2017-03-12 10:03 ` Jayachandran C @ 2017-03-12 10:03 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- [ v5: updated the commit message for clarity ] Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation @ 2017-03-12 10:03 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: linux-arm-kernel Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Acked-by: Rob Herring <robh@kernel.org> --- [ v5: updated the commit message for clarity ] Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-12 10:03 ` Jayachandran C @ 2017-03-12 10:03 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ 6 files changed, 181 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its@40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..57a6f75 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,33 @@ +/* + * dts file for Broadcom (BRCM) Vulcan Evaluation Platform + * + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..46afe3a --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,147 @@ +/* + * dtsi file for Broadcom (BRCM) Vulcan processor + * + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its@40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-12 10:03 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-12 10:03 UTC (permalink / raw) To: linux-arm-kernel Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ 6 files changed, 181 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim@broadcom.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu at 0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu at 1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu at 2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu at 3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller at 400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its at 40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial at 402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..57a6f75 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,33 @@ +/* + * dts file for Broadcom (BRCM) Vulcan Evaluation Platform + * + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..46afe3a --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,147 @@ +/* + * dtsi file for Broadcom (BRCM) Vulcan processor + * + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim@broadcom.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu at 2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu at 3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller at 400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its at 40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial at 402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
[parent not found: <1489313015-4783-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>]
* Re: [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-12 10:03 ` Jayachandran C @ 2017-03-13 12:04 ` Matthias Brugger -1 siblings, 0 replies; 34+ messages in thread From: Matthias Brugger @ 2017-03-13 12:04 UTC (permalink / raw) To: Jayachandran C, arm-DgEjT+Ai2ygdnm+yROfE0A Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Florian Fainelli, Arnd Bergmann, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On 12/03/17 11:03, Jayachandran C wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > --- > arch/arm64/boot/dts/broadcom/Makefile | 1 - > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- > arch/arm64/boot/dts/cavium/Makefile | 1 + > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ > 6 files changed, 181 insertions(+), 181 deletions(-) > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > index f1caece..bfa8f8e 100644 > --- a/arch/arm64/boot/dts/broadcom/Makefile > +++ b/arch/arm64/boot/dts/broadcom/Makefile > @@ -1,6 +1,5 @@ > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > deleted file mode 100644 > index 9ee8d3d..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > +++ /dev/null > @@ -1,33 +0,0 @@ > -/* > - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > - * > - * Copyright (c) 2013-2016 Broadcom > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -/dts-v1/; > - > -#include "vulcan.dtsi" > - > -/ { > - model = "Broadcom Vulcan Eval Platform"; > - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > - > - memory { > - device_type = "memory"; > - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > - }; > - > - aliases { > - serial0 = &uart0; > - }; > - > - chosen { > - stdout-path = "serial0:115200n8"; > - }; > -}; > diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > deleted file mode 100644 > index 34e11a9..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > +++ /dev/null > @@ -1,147 +0,0 @@ > -/* > - * dtsi file for Broadcom (BRCM) Vulcan processor > - * > - * Copyright (c) 2013-2016 Broadcom > - * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -#include <dt-bindings/interrupt-controller/arm-gic.h> > - > -/ { > - model = "Broadcom Vulcan"; > - compatible = "brcm,vulcan-soc"; > - interrupt-parent = <&gic>; > - #address-cells = <2>; > - #size-cells = <2>; > - > - /* just 4 cpus now, 128 needed in full config */ > - cpus { > - #address-cells = <0x2>; > - #size-cells = <0x0>; > - > - cpu@0 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x0>; > - enable-method = "psci"; > - }; > - > - cpu@1 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x1>; > - enable-method = "psci"; > - }; > - > - cpu@2 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x2>; > - enable-method = "psci"; > - }; > - > - cpu@3 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x3>; > - enable-method = "psci"; > - }; > - }; > - > - psci { > - compatible = "arm,psci-0.2"; > - method = "smc"; > - }; > - > - gic: interrupt-controller@400080000 { > - compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - interrupt-controller; > - #redistributor-regions = <1>; > - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > - > - gicits: gic-its@40010000 { > - compatible = "arm,gic-v3-its"; > - msi-controller; > - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > - }; > - }; > - > - timer { > - compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > - }; > - > - pmu { > - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > - }; > - > - clk125mhz: uart_clk125mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <125000000>; > - clock-output-names = "clk125mhz"; > - }; > - > - pci { > - compatible = "pci-host-ecam-generic"; > - device_type = "pci"; > - #interrupt-cells = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - > - /* ECAM at 0x3000_0000 - 0x4000_0000 */ > - reg = <0x0 0x30000000 0x0 0x10000000>; > - reg-names = "PCI ECAM"; > - > - /* > - * PCI ranges: > - * IO no supported > - * MEM 0x4000_0000 - 0x6000_0000 > - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > - */ > - ranges = > - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = > - /* addr pin ic icaddr icintr */ > - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > - msi-parent = <&gicits>; > - dma-coherent; > - }; > - > - soc { > - compatible = "simple-bus"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - > - uart0: serial@402020000 { > - compatible = "arm,pl011", "arm,primecell"; > - reg = <0x04 0x02020000 0x0 0x1000>; > - interrupt-parent = <&gic>; > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk125mhz>; > - clock-names = "apb_pclk"; > - }; > - }; > - > -}; > diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > index e34f89d..581b2c1 100644 > --- a/arch/arm64/boot/dts/cavium/Makefile > +++ b/arch/arm64/boot/dts/cavium/Makefile > @@ -1,4 +1,5 @@ > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > new file mode 100644 > index 0000000..57a6f75 > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > @@ -0,0 +1,33 @@ > +/* > + * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > + * > + * Copyright (c) 2013-2016 Broadcom > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +/dts-v1/; > + > +#include "thunder2-99xx.dtsi" > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > new file mode 100644 > index 0000000..46afe3a > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > @@ -0,0 +1,147 @@ > +/* > + * dtsi file for Broadcom (BRCM) Vulcan processor You might want to add Cavium CN99 here. Apart from that: Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * Copyright (c) 2013-2016 Broadcom > + * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + /* just 4 cpus now, 128 needed in full config */ > + cpus { > + #address-cells = <0x2>; > + #size-cells = <0x0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + gic: interrupt-controller@400080000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gicits: gic-its@40010000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pmu { > + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > + }; > + > + clk125mhz: uart_clk125mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk125mhz"; > + }; > + > + pci { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + /* ECAM at 0x3000_0000 - 0x4000_0000 */ > + reg = <0x0 0x30000000 0x0 0x10000000>; > + reg-names = "PCI ECAM"; > + > + /* > + * PCI ranges: > + * IO no supported > + * MEM 0x4000_0000 - 0x6000_0000 > + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > + */ > + ranges = > + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = > + /* addr pin ic icaddr icintr */ > + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + msi-parent = <&gicits>; > + dma-coherent; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + uart0: serial@402020000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x04 0x02020000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk125mhz>; > + clock-names = "apb_pclk"; > + }; > + }; > + > +}; > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-13 12:04 ` Matthias Brugger 0 siblings, 0 replies; 34+ messages in thread From: Matthias Brugger @ 2017-03-13 12:04 UTC (permalink / raw) To: linux-arm-kernel On 12/03/17 11:03, Jayachandran C wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > --- > arch/arm64/boot/dts/broadcom/Makefile | 1 - > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- > arch/arm64/boot/dts/cavium/Makefile | 1 + > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ > 6 files changed, 181 insertions(+), 181 deletions(-) > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > index f1caece..bfa8f8e 100644 > --- a/arch/arm64/boot/dts/broadcom/Makefile > +++ b/arch/arm64/boot/dts/broadcom/Makefile > @@ -1,6 +1,5 @@ > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > deleted file mode 100644 > index 9ee8d3d..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > +++ /dev/null > @@ -1,33 +0,0 @@ > -/* > - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > - * > - * Copyright (c) 2013-2016 Broadcom > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -/dts-v1/; > - > -#include "vulcan.dtsi" > - > -/ { > - model = "Broadcom Vulcan Eval Platform"; > - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > - > - memory { > - device_type = "memory"; > - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > - }; > - > - aliases { > - serial0 = &uart0; > - }; > - > - chosen { > - stdout-path = "serial0:115200n8"; > - }; > -}; > diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > deleted file mode 100644 > index 34e11a9..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > +++ /dev/null > @@ -1,147 +0,0 @@ > -/* > - * dtsi file for Broadcom (BRCM) Vulcan processor > - * > - * Copyright (c) 2013-2016 Broadcom > - * Author: Zi Shen Lim <zlim@broadcom.com> > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -#include <dt-bindings/interrupt-controller/arm-gic.h> > - > -/ { > - model = "Broadcom Vulcan"; > - compatible = "brcm,vulcan-soc"; > - interrupt-parent = <&gic>; > - #address-cells = <2>; > - #size-cells = <2>; > - > - /* just 4 cpus now, 128 needed in full config */ > - cpus { > - #address-cells = <0x2>; > - #size-cells = <0x0>; > - > - cpu at 0 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x0>; > - enable-method = "psci"; > - }; > - > - cpu at 1 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x1>; > - enable-method = "psci"; > - }; > - > - cpu at 2 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x2>; > - enable-method = "psci"; > - }; > - > - cpu at 3 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x3>; > - enable-method = "psci"; > - }; > - }; > - > - psci { > - compatible = "arm,psci-0.2"; > - method = "smc"; > - }; > - > - gic: interrupt-controller at 400080000 { > - compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - interrupt-controller; > - #redistributor-regions = <1>; > - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > - > - gicits: gic-its at 40010000 { > - compatible = "arm,gic-v3-its"; > - msi-controller; > - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > - }; > - }; > - > - timer { > - compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > - }; > - > - pmu { > - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > - }; > - > - clk125mhz: uart_clk125mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <125000000>; > - clock-output-names = "clk125mhz"; > - }; > - > - pci { > - compatible = "pci-host-ecam-generic"; > - device_type = "pci"; > - #interrupt-cells = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - > - /* ECAM at 0x3000_0000 - 0x4000_0000 */ > - reg = <0x0 0x30000000 0x0 0x10000000>; > - reg-names = "PCI ECAM"; > - > - /* > - * PCI ranges: > - * IO no supported > - * MEM 0x4000_0000 - 0x6000_0000 > - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > - */ > - ranges = > - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = > - /* addr pin ic icaddr icintr */ > - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > - msi-parent = <&gicits>; > - dma-coherent; > - }; > - > - soc { > - compatible = "simple-bus"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - > - uart0: serial at 402020000 { > - compatible = "arm,pl011", "arm,primecell"; > - reg = <0x04 0x02020000 0x0 0x1000>; > - interrupt-parent = <&gic>; > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk125mhz>; > - clock-names = "apb_pclk"; > - }; > - }; > - > -}; > diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > index e34f89d..581b2c1 100644 > --- a/arch/arm64/boot/dts/cavium/Makefile > +++ b/arch/arm64/boot/dts/cavium/Makefile > @@ -1,4 +1,5 @@ > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > new file mode 100644 > index 0000000..57a6f75 > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > @@ -0,0 +1,33 @@ > +/* > + * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > + * > + * Copyright (c) 2013-2016 Broadcom > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +/dts-v1/; > + > +#include "thunder2-99xx.dtsi" > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > new file mode 100644 > index 0000000..46afe3a > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > @@ -0,0 +1,147 @@ > +/* > + * dtsi file for Broadcom (BRCM) Vulcan processor You might want to add Cavium CN99 here. Apart from that: Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > + * > + * Copyright (c) 2013-2016 Broadcom > + * Author: Zi Shen Lim <zlim@broadcom.com> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + /* just 4 cpus now, 128 needed in full config */ > + cpus { > + #address-cells = <0x2>; > + #size-cells = <0x0>; > + > + cpu at 0 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu at 1 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + cpu at 2 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + cpu at 3 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + gic: interrupt-controller at 400080000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gicits: gic-its at 40010000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pmu { > + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > + }; > + > + clk125mhz: uart_clk125mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk125mhz"; > + }; > + > + pci { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + /* ECAM at 0x3000_0000 - 0x4000_0000 */ > + reg = <0x0 0x30000000 0x0 0x10000000>; > + reg-names = "PCI ECAM"; > + > + /* > + * PCI ranges: > + * IO no supported > + * MEM 0x4000_0000 - 0x6000_0000 > + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > + */ > + ranges = > + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = > + /* addr pin ic icaddr icintr */ > + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + msi-parent = <&gicits>; > + dma-coherent; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + uart0: serial at 402020000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x04 0x02020000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk125mhz>; > + clock-names = "apb_pclk"; > + }; > + }; > + > +}; > ^ permalink raw reply [flat|nested] 34+ messages in thread
[parent not found: <24cdda5a-beb8-4cfe-e1b8-5faa2474c063-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-13 12:04 ` Matthias Brugger @ 2017-03-13 13:52 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-13 13:52 UTC (permalink / raw) To: Matthias Brugger Cc: arm-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Florian Fainelli, Arnd Bergmann, Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Mon, Mar 13, 2017 at 01:04:42PM +0100, Matthias Brugger wrote: > > > On 12/03/17 11:03, Jayachandran C wrote: > >Move and update device tree files as part of transition from Broadcom > >Vulcan to Cavium ThunderX2. > > > >The changes are to: > > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > > update cpu cores to be "cavium,thunder2", and update SoC to be > > "cavium,thunderx2-cn9900" > > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > > and update board name string > > * Update dts/broadcom/Makefile not to build vulcan dtbs > > * Update dts/cavium/Makefile to build thunder2 dtbs > > > >No changes to the dts contents except the updated "compatible" and > >"model" properties. > > > >Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > >--- > > arch/arm64/boot/dts/broadcom/Makefile | 1 - > > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- > > arch/arm64/boot/dts/cavium/Makefile | 1 + > > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ > > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ > > 6 files changed, 181 insertions(+), 181 deletions(-) > > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > > >diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > >index f1caece..bfa8f8e 100644 > >--- a/arch/arm64/boot/dts/broadcom/Makefile > >+++ b/arch/arm64/boot/dts/broadcom/Makefile > >@@ -1,6 +1,5 @@ > > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > >-dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > > > always := $(dtb-y) > > subdir-y := $(dts-dirs) > >diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > >deleted file mode 100644 > >index 9ee8d3d..0000000 > >--- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > >+++ /dev/null > >@@ -1,33 +0,0 @@ > >-/* > >- * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > >- * > >- * Copyright (c) 2013-2016 Broadcom > >- * > >- * This program is free software; you can redistribute it and/or > >- * modify it under the terms of the GNU General Public License as > >- * published by the Free Software Foundation; either version 2 of > >- * the License, or (at your option) any later version. > >- */ > >- > >-/dts-v1/; > >- > >-#include "vulcan.dtsi" > >- > >-/ { > >- model = "Broadcom Vulcan Eval Platform"; > >- compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > >- > >- memory { > >- device_type = "memory"; > >- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > >- <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > >- }; > >- > >- aliases { > >- serial0 = &uart0; > >- }; > >- > >- chosen { > >- stdout-path = "serial0:115200n8"; > >- }; > >-}; > >diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > >deleted file mode 100644 > >index 34e11a9..0000000 > >--- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > >+++ /dev/null > >@@ -1,147 +0,0 @@ > >-/* > >- * dtsi file for Broadcom (BRCM) Vulcan processor > >- * > >- * Copyright (c) 2013-2016 Broadcom > >- * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > >- * > >- * This program is free software; you can redistribute it and/or > >- * modify it under the terms of the GNU General Public License as > >- * published by the Free Software Foundation; either version 2 of > >- * the License, or (at your option) any later version. > >- */ > >- > >-#include <dt-bindings/interrupt-controller/arm-gic.h> > >- > >-/ { > >- model = "Broadcom Vulcan"; > >- compatible = "brcm,vulcan-soc"; > >- interrupt-parent = <&gic>; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- > >- /* just 4 cpus now, 128 needed in full config */ > >- cpus { > >- #address-cells = <0x2>; > >- #size-cells = <0x0>; > >- > >- cpu@0 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x0>; > >- enable-method = "psci"; > >- }; > >- > >- cpu@1 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x1>; > >- enable-method = "psci"; > >- }; > >- > >- cpu@2 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x2>; > >- enable-method = "psci"; > >- }; > >- > >- cpu@3 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x3>; > >- enable-method = "psci"; > >- }; > >- }; > >- > >- psci { > >- compatible = "arm,psci-0.2"; > >- method = "smc"; > >- }; > >- > >- gic: interrupt-controller@400080000 { > >- compatible = "arm,gic-v3"; > >- #interrupt-cells = <3>; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- ranges; > >- interrupt-controller; > >- #redistributor-regions = <1>; > >- reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > >- <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > >- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > >- > >- gicits: gic-its@40010000 { > >- compatible = "arm,gic-v3-its"; > >- msi-controller; > >- reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > >- }; > >- }; > >- > >- timer { > >- compatible = "arm,armv8-timer"; > >- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > >- }; > >- > >- pmu { > >- compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > >- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > >- }; > >- > >- clk125mhz: uart_clk125mhz { > >- compatible = "fixed-clock"; > >- #clock-cells = <0>; > >- clock-frequency = <125000000>; > >- clock-output-names = "clk125mhz"; > >- }; > >- > >- pci { > >- compatible = "pci-host-ecam-generic"; > >- device_type = "pci"; > >- #interrupt-cells = <1>; > >- #address-cells = <3>; > >- #size-cells = <2>; > >- > >- /* ECAM at 0x3000_0000 - 0x4000_0000 */ > >- reg = <0x0 0x30000000 0x0 0x10000000>; > >- reg-names = "PCI ECAM"; > >- > >- /* > >- * PCI ranges: > >- * IO no supported > >- * MEM 0x4000_0000 - 0x6000_0000 > >- * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > >- */ > >- ranges = > >- <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > >- 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > >- interrupt-map-mask = <0 0 0 7>; > >- interrupt-map = > >- /* addr pin ic icaddr icintr */ > >- <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > >- msi-parent = <&gicits>; > >- dma-coherent; > >- }; > >- > >- soc { > >- compatible = "simple-bus"; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- ranges; > >- > >- uart0: serial@402020000 { > >- compatible = "arm,pl011", "arm,primecell"; > >- reg = <0x04 0x02020000 0x0 0x1000>; > >- interrupt-parent = <&gic>; > >- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > >- clocks = <&clk125mhz>; > >- clock-names = "apb_pclk"; > >- }; > >- }; > >- > >-}; > >diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > >index e34f89d..581b2c1 100644 > >--- a/arch/arm64/boot/dts/cavium/Makefile > >+++ b/arch/arm64/boot/dts/cavium/Makefile > >@@ -1,4 +1,5 @@ > > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > >+dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > > > always := $(dtb-y) > > subdir-y := $(dts-dirs) > >diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > >new file mode 100644 > >index 0000000..57a6f75 > >--- /dev/null > >+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > >@@ -0,0 +1,33 @@ > >+/* > >+ * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > >+ * > >+ * Copyright (c) 2013-2016 Broadcom > >+ * > >+ * This program is free software; you can redistribute it and/or > >+ * modify it under the terms of the GNU General Public License as > >+ * published by the Free Software Foundation; either version 2 of > >+ * the License, or (at your option) any later version. > >+ */ > >+ > >+/dts-v1/; > >+ > >+#include "thunder2-99xx.dtsi" > >+ > >+/ { > >+ model = "Cavium ThunderX2 CN99XX"; > >+ compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > >+ > >+ memory { > >+ device_type = "memory"; > >+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > >+ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > >+ }; > >+ > >+ aliases { > >+ serial0 = &uart0; > >+ }; > >+ > >+ chosen { > >+ stdout-path = "serial0:115200n8"; > >+ }; > >+}; > >diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > >new file mode 100644 > >index 0000000..46afe3a > >--- /dev/null > >+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > >@@ -0,0 +1,147 @@ > >+/* > >+ * dtsi file for Broadcom (BRCM) Vulcan processor > > You might want to add Cavium CN99 here. > > Apart from that: > Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> I seems to have missed this in both the dts and the dtsi files. Looking thru the file again, I think it might be worth adding a copyright line as well. Thanks for the reivew, will post v6. JC. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-13 13:52 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-13 13:52 UTC (permalink / raw) To: linux-arm-kernel On Mon, Mar 13, 2017 at 01:04:42PM +0100, Matthias Brugger wrote: > > > On 12/03/17 11:03, Jayachandran C wrote: > >Move and update device tree files as part of transition from Broadcom > >Vulcan to Cavium ThunderX2. > > > >The changes are to: > > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > > update cpu cores to be "cavium,thunder2", and update SoC to be > > "cavium,thunderx2-cn9900" > > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > > and update board name string > > * Update dts/broadcom/Makefile not to build vulcan dtbs > > * Update dts/cavium/Makefile to build thunder2 dtbs > > > >No changes to the dts contents except the updated "compatible" and > >"model" properties. > > > >Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > >--- > > arch/arm64/boot/dts/broadcom/Makefile | 1 - > > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------------- > > arch/arm64/boot/dts/cavium/Makefile | 1 + > > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 33 ++++++ > > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 147 ++++++++++++++++++++++++++ > > 6 files changed, 181 insertions(+), 181 deletions(-) > > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > > >diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > >index f1caece..bfa8f8e 100644 > >--- a/arch/arm64/boot/dts/broadcom/Makefile > >+++ b/arch/arm64/boot/dts/broadcom/Makefile > >@@ -1,6 +1,5 @@ > > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > >-dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > > > always := $(dtb-y) > > subdir-y := $(dts-dirs) > >diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > >deleted file mode 100644 > >index 9ee8d3d..0000000 > >--- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > >+++ /dev/null > >@@ -1,33 +0,0 @@ > >-/* > >- * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > >- * > >- * Copyright (c) 2013-2016 Broadcom > >- * > >- * This program is free software; you can redistribute it and/or > >- * modify it under the terms of the GNU General Public License as > >- * published by the Free Software Foundation; either version 2 of > >- * the License, or (at your option) any later version. > >- */ > >- > >-/dts-v1/; > >- > >-#include "vulcan.dtsi" > >- > >-/ { > >- model = "Broadcom Vulcan Eval Platform"; > >- compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > >- > >- memory { > >- device_type = "memory"; > >- reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > >- <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > >- }; > >- > >- aliases { > >- serial0 = &uart0; > >- }; > >- > >- chosen { > >- stdout-path = "serial0:115200n8"; > >- }; > >-}; > >diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > >deleted file mode 100644 > >index 34e11a9..0000000 > >--- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > >+++ /dev/null > >@@ -1,147 +0,0 @@ > >-/* > >- * dtsi file for Broadcom (BRCM) Vulcan processor > >- * > >- * Copyright (c) 2013-2016 Broadcom > >- * Author: Zi Shen Lim <zlim@broadcom.com> > >- * > >- * This program is free software; you can redistribute it and/or > >- * modify it under the terms of the GNU General Public License as > >- * published by the Free Software Foundation; either version 2 of > >- * the License, or (at your option) any later version. > >- */ > >- > >-#include <dt-bindings/interrupt-controller/arm-gic.h> > >- > >-/ { > >- model = "Broadcom Vulcan"; > >- compatible = "brcm,vulcan-soc"; > >- interrupt-parent = <&gic>; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- > >- /* just 4 cpus now, 128 needed in full config */ > >- cpus { > >- #address-cells = <0x2>; > >- #size-cells = <0x0>; > >- > >- cpu at 0 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x0>; > >- enable-method = "psci"; > >- }; > >- > >- cpu at 1 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x1>; > >- enable-method = "psci"; > >- }; > >- > >- cpu at 2 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x2>; > >- enable-method = "psci"; > >- }; > >- > >- cpu at 3 { > >- device_type = "cpu"; > >- compatible = "brcm,vulcan", "arm,armv8"; > >- reg = <0x0 0x3>; > >- enable-method = "psci"; > >- }; > >- }; > >- > >- psci { > >- compatible = "arm,psci-0.2"; > >- method = "smc"; > >- }; > >- > >- gic: interrupt-controller at 400080000 { > >- compatible = "arm,gic-v3"; > >- #interrupt-cells = <3>; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- ranges; > >- interrupt-controller; > >- #redistributor-regions = <1>; > >- reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > >- <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > >- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > >- > >- gicits: gic-its at 40010000 { > >- compatible = "arm,gic-v3-its"; > >- msi-controller; > >- reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > >- }; > >- }; > >- > >- timer { > >- compatible = "arm,armv8-timer"; > >- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > >- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > >- }; > >- > >- pmu { > >- compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > >- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > >- }; > >- > >- clk125mhz: uart_clk125mhz { > >- compatible = "fixed-clock"; > >- #clock-cells = <0>; > >- clock-frequency = <125000000>; > >- clock-output-names = "clk125mhz"; > >- }; > >- > >- pci { > >- compatible = "pci-host-ecam-generic"; > >- device_type = "pci"; > >- #interrupt-cells = <1>; > >- #address-cells = <3>; > >- #size-cells = <2>; > >- > >- /* ECAM at 0x3000_0000 - 0x4000_0000 */ > >- reg = <0x0 0x30000000 0x0 0x10000000>; > >- reg-names = "PCI ECAM"; > >- > >- /* > >- * PCI ranges: > >- * IO no supported > >- * MEM 0x4000_0000 - 0x6000_0000 > >- * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > >- */ > >- ranges = > >- <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > >- 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > >- interrupt-map-mask = <0 0 0 7>; > >- interrupt-map = > >- /* addr pin ic icaddr icintr */ > >- <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > >- 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > >- msi-parent = <&gicits>; > >- dma-coherent; > >- }; > >- > >- soc { > >- compatible = "simple-bus"; > >- #address-cells = <2>; > >- #size-cells = <2>; > >- ranges; > >- > >- uart0: serial at 402020000 { > >- compatible = "arm,pl011", "arm,primecell"; > >- reg = <0x04 0x02020000 0x0 0x1000>; > >- interrupt-parent = <&gic>; > >- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > >- clocks = <&clk125mhz>; > >- clock-names = "apb_pclk"; > >- }; > >- }; > >- > >-}; > >diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > >index e34f89d..581b2c1 100644 > >--- a/arch/arm64/boot/dts/cavium/Makefile > >+++ b/arch/arm64/boot/dts/cavium/Makefile > >@@ -1,4 +1,5 @@ > > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > >+dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > > > always := $(dtb-y) > > subdir-y := $(dts-dirs) > >diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > >new file mode 100644 > >index 0000000..57a6f75 > >--- /dev/null > >+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > >@@ -0,0 +1,33 @@ > >+/* > >+ * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > >+ * > >+ * Copyright (c) 2013-2016 Broadcom > >+ * > >+ * This program is free software; you can redistribute it and/or > >+ * modify it under the terms of the GNU General Public License as > >+ * published by the Free Software Foundation; either version 2 of > >+ * the License, or (at your option) any later version. > >+ */ > >+ > >+/dts-v1/; > >+ > >+#include "thunder2-99xx.dtsi" > >+ > >+/ { > >+ model = "Cavium ThunderX2 CN99XX"; > >+ compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > >+ > >+ memory { > >+ device_type = "memory"; > >+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > >+ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > >+ }; > >+ > >+ aliases { > >+ serial0 = &uart0; > >+ }; > >+ > >+ chosen { > >+ stdout-path = "serial0:115200n8"; > >+ }; > >+}; > >diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > >new file mode 100644 > >index 0000000..46afe3a > >--- /dev/null > >+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > >@@ -0,0 +1,147 @@ > >+/* > >+ * dtsi file for Broadcom (BRCM) Vulcan processor > > You might want to add Cavium CN99 here. > > Apart from that: > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> I seems to have missed this in both the dts and the dtsi files. Looking thru the file again, I think it might be worth adding a copyright line as well. Thanks for the reivew, will post v6. JC. ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition 2017-03-12 10:03 ` Jayachandran C @ 2017-03-14 12:47 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. v5->v6 Updated version addressing comment from Matthias, and adding his Reviewed-by tag. (https://www.spinics.net/lists/arm-kernel/msg568157.html) JC. Jayachandran C (2): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 +++++++++++++++++++++ 8 files changed, 192 insertions(+), 181 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition @ 2017-03-14 12:47 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: linux-arm-kernel Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. v5->v6 Updated version addressing comment from Matthias, and adding his Reviewed-by tag. (https://www.spinics.net/lists/arm-kernel/msg568157.html) JC. Jayachandran C (2): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 +++++++++++++++++++++ 8 files changed, 192 insertions(+), 181 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 ^ permalink raw reply [flat|nested] 34+ messages in thread
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* [PATCH v6 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation 2017-03-14 12:47 ` Jayachandran C @ 2017-03-14 12:47 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation @ 2017-03-14 12:47 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: linux-arm-kernel Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-14 12:47 ` Jayachandran C @ 2017-03-14 12:47 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ 6 files changed, 183 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its@40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..6c6fb86 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,34 @@ +/* + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..4220fbd --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,148 @@ +/* + * dtsi file for Cavium ThunderX2 CN99XX processor + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its@40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-14 12:47 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-14 12:47 UTC (permalink / raw) To: linux-arm-kernel Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ 6 files changed, 183 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim@broadcom.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu at 0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu at 1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu at 2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu at 3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller at 400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its at 40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial at 402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..6c6fb86 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,34 @@ +/* + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..4220fbd --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,148 @@ +/* + * dtsi file for Cavium ThunderX2 CN99XX processor + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim@broadcom.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu at 2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu at 3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller at 400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its at 40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial at 402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
[parent not found: <1489495634-2920-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>]
* Re: [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-14 12:47 ` Jayachandran C @ 2017-03-14 18:16 ` Florian Fainelli -1 siblings, 0 replies; 34+ messages in thread From: Florian Fainelli @ 2017-03-14 18:16 UTC (permalink / raw) To: Jayachandran C, arm-DgEjT+Ai2ygdnm+yROfE0A Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Matthias Brugger On 03/14/2017 05:47 AM, Jayachandran C wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Can you also change the relevant entry in the MAINTAINERS file: BROADCOM VULCAN ARM64 SOC M: Jayachandran C. <c.jayachandran-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> M: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/broadcom/vulcan* With that fixed: Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > arch/arm64/boot/dts/broadcom/Makefile | 1 - > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- > arch/arm64/boot/dts/cavium/Makefile | 1 + > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ > 6 files changed, 183 insertions(+), 181 deletions(-) > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > index f1caece..bfa8f8e 100644 > --- a/arch/arm64/boot/dts/broadcom/Makefile > +++ b/arch/arm64/boot/dts/broadcom/Makefile > @@ -1,6 +1,5 @@ > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > deleted file mode 100644 > index 9ee8d3d..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > +++ /dev/null > @@ -1,33 +0,0 @@ > -/* > - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > - * > - * Copyright (c) 2013-2016 Broadcom > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -/dts-v1/; > - > -#include "vulcan.dtsi" > - > -/ { > - model = "Broadcom Vulcan Eval Platform"; > - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > - > - memory { > - device_type = "memory"; > - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > - }; > - > - aliases { > - serial0 = &uart0; > - }; > - > - chosen { > - stdout-path = "serial0:115200n8"; > - }; > -}; > diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > deleted file mode 100644 > index 34e11a9..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > +++ /dev/null > @@ -1,147 +0,0 @@ > -/* > - * dtsi file for Broadcom (BRCM) Vulcan processor > - * > - * Copyright (c) 2013-2016 Broadcom > - * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -#include <dt-bindings/interrupt-controller/arm-gic.h> > - > -/ { > - model = "Broadcom Vulcan"; > - compatible = "brcm,vulcan-soc"; > - interrupt-parent = <&gic>; > - #address-cells = <2>; > - #size-cells = <2>; > - > - /* just 4 cpus now, 128 needed in full config */ > - cpus { > - #address-cells = <0x2>; > - #size-cells = <0x0>; > - > - cpu@0 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x0>; > - enable-method = "psci"; > - }; > - > - cpu@1 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x1>; > - enable-method = "psci"; > - }; > - > - cpu@2 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x2>; > - enable-method = "psci"; > - }; > - > - cpu@3 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x3>; > - enable-method = "psci"; > - }; > - }; > - > - psci { > - compatible = "arm,psci-0.2"; > - method = "smc"; > - }; > - > - gic: interrupt-controller@400080000 { > - compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - interrupt-controller; > - #redistributor-regions = <1>; > - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > - > - gicits: gic-its@40010000 { > - compatible = "arm,gic-v3-its"; > - msi-controller; > - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > - }; > - }; > - > - timer { > - compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > - }; > - > - pmu { > - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > - }; > - > - clk125mhz: uart_clk125mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <125000000>; > - clock-output-names = "clk125mhz"; > - }; > - > - pci { > - compatible = "pci-host-ecam-generic"; > - device_type = "pci"; > - #interrupt-cells = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - > - /* ECAM at 0x3000_0000 - 0x4000_0000 */ > - reg = <0x0 0x30000000 0x0 0x10000000>; > - reg-names = "PCI ECAM"; > - > - /* > - * PCI ranges: > - * IO no supported > - * MEM 0x4000_0000 - 0x6000_0000 > - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > - */ > - ranges = > - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = > - /* addr pin ic icaddr icintr */ > - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > - msi-parent = <&gicits>; > - dma-coherent; > - }; > - > - soc { > - compatible = "simple-bus"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - > - uart0: serial@402020000 { > - compatible = "arm,pl011", "arm,primecell"; > - reg = <0x04 0x02020000 0x0 0x1000>; > - interrupt-parent = <&gic>; > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk125mhz>; > - clock-names = "apb_pclk"; > - }; > - }; > - > -}; > diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > index e34f89d..581b2c1 100644 > --- a/arch/arm64/boot/dts/cavium/Makefile > +++ b/arch/arm64/boot/dts/cavium/Makefile > @@ -1,4 +1,5 @@ > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > new file mode 100644 > index 0000000..6c6fb86 > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > @@ -0,0 +1,34 @@ > +/* > + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform > + * > + * Copyright (c) 2017 Cavium Inc. > + * Copyright (c) 2013-2016 Broadcom > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +/dts-v1/; > + > +#include "thunder2-99xx.dtsi" > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > new file mode 100644 > index 0000000..4220fbd > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > @@ -0,0 +1,148 @@ > +/* > + * dtsi file for Cavium ThunderX2 CN99XX processor > + * > + * Copyright (c) 2017 Cavium Inc. > + * Copyright (c) 2013-2016 Broadcom > + * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + /* just 4 cpus now, 128 needed in full config */ > + cpus { > + #address-cells = <0x2>; > + #size-cells = <0x0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + gic: interrupt-controller@400080000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gicits: gic-its@40010000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pmu { > + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > + }; > + > + clk125mhz: uart_clk125mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk125mhz"; > + }; > + > + pci { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + /* ECAM at 0x3000_0000 - 0x4000_0000 */ > + reg = <0x0 0x30000000 0x0 0x10000000>; > + reg-names = "PCI ECAM"; > + > + /* > + * PCI ranges: > + * IO no supported > + * MEM 0x4000_0000 - 0x6000_0000 > + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > + */ > + ranges = > + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = > + /* addr pin ic icaddr icintr */ > + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + msi-parent = <&gicits>; > + dma-coherent; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + uart0: serial@402020000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x04 0x02020000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk125mhz>; > + clock-names = "apb_pclk"; > + }; > + }; > + > +}; > -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-14 18:16 ` Florian Fainelli 0 siblings, 0 replies; 34+ messages in thread From: Florian Fainelli @ 2017-03-14 18:16 UTC (permalink / raw) To: linux-arm-kernel On 03/14/2017 05:47 AM, Jayachandran C wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Can you also change the relevant entry in the MAINTAINERS file: BROADCOM VULCAN ARM64 SOC M: Jayachandran C. <c.jayachandran@gmail.com> M: bcm-kernel-feedback-list at broadcom.com L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/broadcom/vulcan* With that fixed: Acked-by: Florian Fainelli <f.fainelli@gmail.com> > --- > arch/arm64/boot/dts/broadcom/Makefile | 1 - > arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ > arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- > arch/arm64/boot/dts/cavium/Makefile | 1 + > arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ > arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ > 6 files changed, 183 insertions(+), 181 deletions(-) > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts > delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts > create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > > diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile > index f1caece..bfa8f8e 100644 > --- a/arch/arm64/boot/dts/broadcom/Makefile > +++ b/arch/arm64/boot/dts/broadcom/Makefile > @@ -1,6 +1,5 @@ > dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb > dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb > -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > deleted file mode 100644 > index 9ee8d3d..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts > +++ /dev/null > @@ -1,33 +0,0 @@ > -/* > - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform > - * > - * Copyright (c) 2013-2016 Broadcom > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -/dts-v1/; > - > -#include "vulcan.dtsi" > - > -/ { > - model = "Broadcom Vulcan Eval Platform"; > - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; > - > - memory { > - device_type = "memory"; > - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > - }; > - > - aliases { > - serial0 = &uart0; > - }; > - > - chosen { > - stdout-path = "serial0:115200n8"; > - }; > -}; > diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi > deleted file mode 100644 > index 34e11a9..0000000 > --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi > +++ /dev/null > @@ -1,147 +0,0 @@ > -/* > - * dtsi file for Broadcom (BRCM) Vulcan processor > - * > - * Copyright (c) 2013-2016 Broadcom > - * Author: Zi Shen Lim <zlim@broadcom.com> > - * > - * This program is free software; you can redistribute it and/or > - * modify it under the terms of the GNU General Public License as > - * published by the Free Software Foundation; either version 2 of > - * the License, or (at your option) any later version. > - */ > - > -#include <dt-bindings/interrupt-controller/arm-gic.h> > - > -/ { > - model = "Broadcom Vulcan"; > - compatible = "brcm,vulcan-soc"; > - interrupt-parent = <&gic>; > - #address-cells = <2>; > - #size-cells = <2>; > - > - /* just 4 cpus now, 128 needed in full config */ > - cpus { > - #address-cells = <0x2>; > - #size-cells = <0x0>; > - > - cpu at 0 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x0>; > - enable-method = "psci"; > - }; > - > - cpu at 1 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x1>; > - enable-method = "psci"; > - }; > - > - cpu at 2 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x2>; > - enable-method = "psci"; > - }; > - > - cpu at 3 { > - device_type = "cpu"; > - compatible = "brcm,vulcan", "arm,armv8"; > - reg = <0x0 0x3>; > - enable-method = "psci"; > - }; > - }; > - > - psci { > - compatible = "arm,psci-0.2"; > - method = "smc"; > - }; > - > - gic: interrupt-controller at 400080000 { > - compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - interrupt-controller; > - #redistributor-regions = <1>; > - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > - > - gicits: gic-its at 40010000 { > - compatible = "arm,gic-v3-its"; > - msi-controller; > - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > - }; > - }; > - > - timer { > - compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > - }; > - > - pmu { > - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > - }; > - > - clk125mhz: uart_clk125mhz { > - compatible = "fixed-clock"; > - #clock-cells = <0>; > - clock-frequency = <125000000>; > - clock-output-names = "clk125mhz"; > - }; > - > - pci { > - compatible = "pci-host-ecam-generic"; > - device_type = "pci"; > - #interrupt-cells = <1>; > - #address-cells = <3>; > - #size-cells = <2>; > - > - /* ECAM at 0x3000_0000 - 0x4000_0000 */ > - reg = <0x0 0x30000000 0x0 0x10000000>; > - reg-names = "PCI ECAM"; > - > - /* > - * PCI ranges: > - * IO no supported > - * MEM 0x4000_0000 - 0x6000_0000 > - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > - */ > - ranges = > - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > - interrupt-map-mask = <0 0 0 7>; > - interrupt-map = > - /* addr pin ic icaddr icintr */ > - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > - msi-parent = <&gicits>; > - dma-coherent; > - }; > - > - soc { > - compatible = "simple-bus"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - > - uart0: serial at 402020000 { > - compatible = "arm,pl011", "arm,primecell"; > - reg = <0x04 0x02020000 0x0 0x1000>; > - interrupt-parent = <&gic>; > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&clk125mhz>; > - clock-names = "apb_pclk"; > - }; > - }; > - > -}; > diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile > index e34f89d..581b2c1 100644 > --- a/arch/arm64/boot/dts/cavium/Makefile > +++ b/arch/arm64/boot/dts/cavium/Makefile > @@ -1,4 +1,5 @@ > dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb > +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb > > always := $(dtb-y) > subdir-y := $(dts-dirs) > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > new file mode 100644 > index 0000000..6c6fb86 > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts > @@ -0,0 +1,34 @@ > +/* > + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform > + * > + * Copyright (c) 2017 Cavium Inc. > + * Copyright (c) 2013-2016 Broadcom > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +/dts-v1/; > + > +#include "thunder2-99xx.dtsi" > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + > + memory { > + device_type = "memory"; > + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ > + }; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > new file mode 100644 > index 0000000..4220fbd > --- /dev/null > +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi > @@ -0,0 +1,148 @@ > +/* > + * dtsi file for Cavium ThunderX2 CN99XX processor > + * > + * Copyright (c) 2017 Cavium Inc. > + * Copyright (c) 2013-2016 Broadcom > + * Author: Zi Shen Lim <zlim@broadcom.com> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + model = "Cavium ThunderX2 CN99XX"; > + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + /* just 4 cpus now, 128 needed in full config */ > + cpus { > + #address-cells = <0x2>; > + #size-cells = <0x0>; > + > + cpu at 0 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu at 1 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + > + cpu at 2 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + > + cpu at 3 { > + device_type = "cpu"; > + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; > + reg = <0x0 0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + gic: interrupt-controller at 400080000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ > + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gicits: gic-its at 40010000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + pmu { > + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ > + }; > + > + clk125mhz: uart_clk125mhz { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk125mhz"; > + }; > + > + pci { > + compatible = "pci-host-ecam-generic"; > + device_type = "pci"; > + #interrupt-cells = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + /* ECAM at 0x3000_0000 - 0x4000_0000 */ > + reg = <0x0 0x30000000 0x0 0x10000000>; > + reg-names = "PCI ECAM"; > + > + /* > + * PCI ranges: > + * IO no supported > + * MEM 0x4000_0000 - 0x6000_0000 > + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 > + */ > + ranges = > + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 > + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = > + /* addr pin ic icaddr icintr */ > + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH > + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + msi-parent = <&gicits>; > + dma-coherent; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + uart0: serial at 402020000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x04 0x02020000 0x0 0x1000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk125mhz>; > + clock-names = "apb_pclk"; > + }; > + }; > + > +}; > -- Florian ^ permalink raw reply [flat|nested] 34+ messages in thread
[parent not found: <8262c276-c39c-17b6-dcb6-d087d68d3df5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-14 18:16 ` Florian Fainelli @ 2017-03-15 8:15 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 8:15 UTC (permalink / raw) To: Florian Fainelli Cc: arm-DgEjT+Ai2ygdnm+yROfE0A, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Matthias Brugger On Tue, Mar 14, 2017 at 11:16:47AM -0700, Florian Fainelli wrote: > On 03/14/2017 05:47 AM, Jayachandran C wrote: > > Move and update device tree files as part of transition from Broadcom > > Vulcan to Cavium ThunderX2. > > > > The changes are to: > > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > > update cpu cores to be "cavium,thunder2", and update SoC to be > > "cavium,thunderx2-cn9900" > > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > > and update board name string > > * Update dts/broadcom/Makefile not to build vulcan dtbs > > * Update dts/cavium/Makefile to build thunder2 dtbs > > > > No changes to the dts contents except the updated "compatible" and > > "model" properties. > > > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > > Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > > Can you also change the relevant entry in the MAINTAINERS file: > > BROADCOM VULCAN ARM64 SOC > M: Jayachandran C. <c.jayachandran-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > M: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org > L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) > S: Maintained > F: arch/arm64/boot/dts/broadcom/vulcan* I was planning to remove this entry in the later patchset that removes ARCH_VULCAN. But, as you suggest, it makes more sense to do that now. I will post an updated patchset with a new patch to update the entry. > With that fixed: > > Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Thanks, JC. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-15 8:15 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 8:15 UTC (permalink / raw) To: linux-arm-kernel On Tue, Mar 14, 2017 at 11:16:47AM -0700, Florian Fainelli wrote: > On 03/14/2017 05:47 AM, Jayachandran C wrote: > > Move and update device tree files as part of transition from Broadcom > > Vulcan to Cavium ThunderX2. > > > > The changes are to: > > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > > update cpu cores to be "cavium,thunder2", and update SoC to be > > "cavium,thunderx2-cn9900" > > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > > and update board name string > > * Update dts/broadcom/Makefile not to build vulcan dtbs > > * Update dts/cavium/Makefile to build thunder2 dtbs > > > > No changes to the dts contents except the updated "compatible" and > > "model" properties. > > > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > > Can you also change the relevant entry in the MAINTAINERS file: > > BROADCOM VULCAN ARM64 SOC > M: Jayachandran C. <c.jayachandran@gmail.com> > M: bcm-kernel-feedback-list at broadcom.com > L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: arch/arm64/boot/dts/broadcom/vulcan* I was planning to remove this entry in the later patchset that removes ARCH_VULCAN. But, as you suggest, it makes more sense to do that now. I will post an updated patchset with a new patch to update the entry. > With that fixed: > > Acked-by: Florian Fainelli <f.fainelli@gmail.com> Thanks, JC. ^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-14 12:47 ` Jayachandran C @ 2017-03-31 9:44 ` Arnd Bergmann -1 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-31 9:44 UTC (permalink / raw) To: Jayachandran C Cc: arm-soc, Linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Florian Fainelli, Matthias Brugger On Tue, Mar 14, 2017 at 1:47 PM, Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Applied to next/dt64. The contents are fine, but I'd recommend using 'git format-patch -M' when creating a submission for easier review, in case you do another patch with a rename in the future. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-31 9:44 ` Arnd Bergmann 0 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-31 9:44 UTC (permalink / raw) To: linux-arm-kernel On Tue, Mar 14, 2017 at 1:47 PM, Jayachandran C <jnair@caviumnetworks.com> wrote: > Move and update device tree files as part of transition from Broadcom > Vulcan to Cavium ThunderX2. > > The changes are to: > * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, > update cpu cores to be "cavium,thunder2", and update SoC to be > "cavium,thunderx2-cn9900" > * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi > and update board name string > * Update dts/broadcom/Makefile not to build vulcan dtbs > * Update dts/cavium/Makefile to build thunder2 dtbs > > No changes to the dts contents except the updated "compatible" and > "model" properties. > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Applied to next/dt64. The contents are fine, but I'd recommend using 'git format-patch -M' when creating a submission for easier review, in case you do another patch with a rename in the future. Arnd ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 0/3] ARCH_VULCAN to ARCH_THUNDER2 transition 2017-03-14 12:47 ` Jayachandran C @ 2017-03-15 20:10 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:10 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger One more update on this patchset, hopefully the final one. Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. I have now added a third patch to update the maintainer info v6->v7 Add a new patch to update the MAINTAINERS file (suggested by Florian) Add Acked-by from Florian. v5->v6 Updated version addressing comment from Matthias, and adding his Reviewed-by tag. (https://www.spinics.net/lists/arm-kernel/msg568157.html) JC. Jayachandran C (3): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + MAINTAINERS | 9 +- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 +++++++++++++++++++++ 9 files changed, 193 insertions(+), 189 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 0/3] ARCH_VULCAN to ARCH_THUNDER2 transition @ 2017-03-15 20:10 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:10 UTC (permalink / raw) To: linux-arm-kernel One more update on this patchset, hopefully the final one. Here are the updated versions of two patches of the series that did not get into 4.11. The patches are move the device trees to their new location and to document the new cpu and core names. I have now added a third patch to update the maintainer info v6->v7 Add a new patch to update the MAINTAINERS file (suggested by Florian) Add Acked-by from Florian. v5->v6 Updated version addressing comment from Matthias, and adding his Reviewed-by tag. (https://www.spinics.net/lists/arm-kernel/msg568157.html) JC. Jayachandran C (3): dt-bindings: arm64 ARCH_THUNDER2 platform documentation arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 .../devicetree/bindings/arm/cavium-thunder2.txt | 8 ++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + MAINTAINERS | 9 +- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ----- arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 -------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 +++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 +++++++++++++++++++++ 9 files changed, 193 insertions(+), 189 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi -- 2.7.4 ^ permalink raw reply [flat|nested] 34+ messages in thread
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* [PATCH v6 1/3] dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation 2017-03-15 20:10 ` Jayachandran C @ 2017-03-15 20:11 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 1/3] dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation @ 2017-03-15 20:11 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: linux-arm-kernel Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This SoC will use "cavium,thunderx2-cn9900" as the compatible property. Also add a documentation entry for the "cavium,thunder2" cpu core present in these SoCs. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 8 ++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 2 files changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cavium-thunder2.txt diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt new file mode 100644 index 0000000..dc5dd65 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt @@ -0,0 +1,8 @@ +Cavium ThunderX2 CN99XX platform tree bindings +---------------------------------------------- + +Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + +These SoC uses the "cavium,thunder2" core which will be compatible +with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 698ad1f0..1030f5f 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -170,6 +170,7 @@ nodes to be present and contain the properties described below. "brcm,brahma-b15" "brcm,vulcan" "cavium,thunder" + "cavium,thunder2" "faraday,fa526" "intel,sa110" "intel,sa1100" -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
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* Re: [PATCH v6 1/3] dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation 2017-03-15 20:11 ` Jayachandran C @ 2017-03-31 9:40 ` Arnd Bergmann -1 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-31 9:40 UTC (permalink / raw) To: Jayachandran C Cc: arm-soc, Linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Florian Fainelli, Matthias Brugger On Wed, Mar 15, 2017 at 9:11 PM, Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote: > Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This > SoC will use "cavium,thunderx2-cn9900" as the compatible property. > > Also add a documentation entry for the "cavium,thunder2" cpu core > present in these SoCs. > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Applied on next/dt64, thanks! Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 1/3] dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation @ 2017-03-31 9:40 ` Arnd Bergmann 0 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-31 9:40 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 15, 2017 at 9:11 PM, Jayachandran C <jnair@caviumnetworks.com> wrote: > Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This > SoC will use "cavium,thunderx2-cn9900" as the compatible property. > > Also add a documentation entry for the "cavium,thunder2" cpu core > present in these SoCs. > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > Acked-by: Rob Herring <robh@kernel.org> Applied on next/dt64, thanks! Arnd ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 2/3] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 2017-03-15 20:10 ` Jayachandran C @ 2017-03-15 20:11 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> Reviewed-by: Matthias Brugger <matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ 6 files changed, 183 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its@40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..6c6fb86 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,34 @@ +/* + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..4220fbd --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,148 @@ +/* + * dtsi file for Cavium ThunderX2 CN99XX processor + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its@40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 2/3] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 @ 2017-03-15 20:11 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: linux-arm-kernel Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> --- arch/arm64/boot/dts/broadcom/Makefile | 1 - arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 ------ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 147 ------------------------- arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 34 ++++++ arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 148 ++++++++++++++++++++++++++ 6 files changed, 183 insertions(+), 181 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts delete mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts create mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index f1caece..bfa8f8e 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,6 +1,5 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb -dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts deleted file mode 100644 index 9ee8d3d..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * dts file for Broadcom (BRCM) Vulcan Evaluation Platform - * - * Copyright (c) 2013-2016 Broadcom - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -/dts-v1/; - -#include "vulcan.dtsi" - -/ { - model = "Broadcom Vulcan Eval Platform"; - compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi deleted file mode 100644 index 34e11a9..0000000 --- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi +++ /dev/null @@ -1,147 +0,0 @@ -/* - * dtsi file for Broadcom (BRCM) Vulcan processor - * - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim <zlim@broadcom.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Broadcom Vulcan"; - compatible = "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu at 0 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu at 1 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu at 2 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu at 3 { - device_type = "cpu"; - compatible = "brcm,vulcan", "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller at 400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gicits: gic-its at 40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pci { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial at 402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index e34f89d..581b2c1 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts new file mode 100644 index 0000000..6c6fb86 --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -0,0 +1,34 @@ +/* + * dts file for Cavium ThunderX2 CN99XX Evaluation Platform + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "thunder2-99xx.dtsi" + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi new file mode 100644 index 0000000..4220fbd --- /dev/null +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -0,0 +1,148 @@ +/* + * dtsi file for Cavium ThunderX2 CN99XX processor + * + * Copyright (c) 2017 Cavium Inc. + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim <zlim@broadcom.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Cavium ThunderX2 CN99XX"; + compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu at 2 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu at 3 { + device_type = "cpu"; + compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller at 400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gicits: gic-its at 40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu { + compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* + * PCI ranges: + * IO no supported + * MEM 0x4000_0000 - 0x6000_0000 + * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 + */ + ranges = + <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 + 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial at 402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 2017-03-15 20:10 ` Jayachandran C @ 2017-03-15 20:11 ` Jayachandran C -1 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: arm-DgEjT+Ai2ygdnm+yROfE0A Cc: Jayachandran C, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Arnd Bergmann, Florian Fainelli, Matthias Brugger Now that the dts files are moved to the new location, we can remove the Broadcom Vulcan entry in the MAINTAINERS. Also fix up the Cavium ThunderX2 entry with the correct pattern for the new names. Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> --- MAINTAINERS | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c776906..81a1f2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2838,13 +2838,6 @@ L: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org S: Supported F: drivers/net/ethernet/broadcom/bcmsysport.* -BROADCOM VULCAN ARM64 SOC -M: Jayachandran C. <c.jayachandran-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> -M: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org -L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) -S: Maintained -F: arch/arm64/boot/dts/broadcom/vulcan* - BROADCOM NETXTREME-E ROCE DRIVER M: Selvin Xavier <selvin.xavier-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> M: Devesh Sharma <devesh.sharma-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> @@ -3030,7 +3023,7 @@ CAVIUM THUNDERX2 ARM64 SOC M: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers) S: Maintained -F: arch/arm64/boot/dts/cavium/thunder-99xx* +F: arch/arm64/boot/dts/cavium/thunder2-99xx* F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt CAVIUM I2C DRIVER -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 @ 2017-03-15 20:11 ` Jayachandran C 0 siblings, 0 replies; 34+ messages in thread From: Jayachandran C @ 2017-03-15 20:11 UTC (permalink / raw) To: linux-arm-kernel Now that the dts files are moved to the new location, we can remove the Broadcom Vulcan entry in the MAINTAINERS. Also fix up the Cavium ThunderX2 entry with the correct pattern for the new names. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> --- MAINTAINERS | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c776906..81a1f2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2838,13 +2838,6 @@ L: netdev at vger.kernel.org S: Supported F: drivers/net/ethernet/broadcom/bcmsysport.* -BROADCOM VULCAN ARM64 SOC -M: Jayachandran C. <c.jayachandran@gmail.com> -M: bcm-kernel-feedback-list at broadcom.com -L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm64/boot/dts/broadcom/vulcan* - BROADCOM NETXTREME-E ROCE DRIVER M: Selvin Xavier <selvin.xavier@broadcom.com> M: Devesh Sharma <devesh.sharma@broadcom.com> @@ -3030,7 +3023,7 @@ CAVIUM THUNDERX2 ARM64 SOC M: Jayachandran C <jnair@caviumnetworks.com> L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm64/boot/dts/cavium/thunder-99xx* +F: arch/arm64/boot/dts/cavium/thunder2-99xx* F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt CAVIUM I2C DRIVER -- 2.7.4 ^ permalink raw reply related [flat|nested] 34+ messages in thread
[parent not found: <1489608662-4434-4-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>]
* Re: [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 2017-03-15 20:11 ` Jayachandran C @ 2017-03-30 15:40 ` Arnd Bergmann -1 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-30 15:40 UTC (permalink / raw) To: Jayachandran C Cc: arm-soc, Linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Florian Fainelli, Matthias Brugger On Wed, Mar 15, 2017 at 9:11 PM, Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> wrote: > Now that the dts files are moved to the new location, we can remove > the Broadcom Vulcan entry in the MAINTAINERS. > > Also fix up the Cavium ThunderX2 entry with the correct pattern for > the new names. > > Signed-off-by: Jayachandran C <jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> > --- Applied to next/arm64, thanks! Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 @ 2017-03-30 15:40 ` Arnd Bergmann 0 siblings, 0 replies; 34+ messages in thread From: Arnd Bergmann @ 2017-03-30 15:40 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 15, 2017 at 9:11 PM, Jayachandran C <jnair@caviumnetworks.com> wrote: > Now that the dts files are moved to the new location, we can remove > the Broadcom Vulcan entry in the MAINTAINERS. > > Also fix up the Cavium ThunderX2 entry with the correct pattern for > the new names. > > Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> > --- Applied to next/arm64, thanks! Arnd ^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2017-03-31 9:44 UTC | newest]
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2017-03-12 10:03 [PATCH v5 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition Jayachandran C
2017-03-12 10:03 ` Jayachandran C
[not found] ` <1489313015-4783-1-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-12 10:03 ` [PATCH v5 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation Jayachandran C
2017-03-12 10:03 ` Jayachandran C
2017-03-12 10:03 ` [PATCH v5 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 Jayachandran C
2017-03-12 10:03 ` Jayachandran C
[not found] ` <1489313015-4783-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-13 12:04 ` Matthias Brugger
2017-03-13 12:04 ` Matthias Brugger
[not found] ` <24cdda5a-beb8-4cfe-e1b8-5faa2474c063-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-13 13:52 ` Jayachandran C
2017-03-13 13:52 ` Jayachandran C
2017-03-14 12:47 ` [PATCH v6 0/2] ARCH_VULCAN to ARCH_THUNDER2 transition Jayachandran C
2017-03-14 12:47 ` Jayachandran C
[not found] ` <1489495634-2920-1-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-14 12:47 ` [PATCH v6 1/2] dt-bindings: arm64 ARCH_THUNDER2 platform documentation Jayachandran C
2017-03-14 12:47 ` Jayachandran C
2017-03-14 12:47 ` [PATCH v6 2/2] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 Jayachandran C
2017-03-14 12:47 ` Jayachandran C
[not found] ` <1489495634-2920-3-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-14 18:16 ` Florian Fainelli
2017-03-14 18:16 ` Florian Fainelli
[not found] ` <8262c276-c39c-17b6-dcb6-d087d68d3df5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-15 8:15 ` Jayachandran C
2017-03-15 8:15 ` Jayachandran C
2017-03-31 9:44 ` Arnd Bergmann
2017-03-31 9:44 ` Arnd Bergmann
2017-03-15 20:10 ` [PATCH v6 0/3] ARCH_VULCAN to ARCH_THUNDER2 transition Jayachandran C
2017-03-15 20:10 ` Jayachandran C
[not found] ` <1489608662-4434-1-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-15 20:11 ` [PATCH v6 1/3] dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation Jayachandran C
2017-03-15 20:11 ` Jayachandran C
[not found] ` <1489608662-4434-2-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-31 9:40 ` Arnd Bergmann
2017-03-31 9:40 ` Arnd Bergmann
2017-03-15 20:11 ` [PATCH v6 2/3] arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2 Jayachandran C
2017-03-15 20:11 ` Jayachandran C
2017-03-15 20:11 ` [PATCH v6 3/3] MAINTAINERS: Broadcom Vulcan is now Cavium ThunderX2 Jayachandran C
2017-03-15 20:11 ` Jayachandran C
[not found] ` <1489608662-4434-4-git-send-email-jnair-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
2017-03-30 15:40 ` Arnd Bergmann
2017-03-30 15:40 ` Arnd Bergmann
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