* ✗ Fi.CI.BAT: failure for drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
@ 2017-03-15 8:32 ` Patchwork
2017-03-15 8:46 ` Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-03-15 8:32 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
URL : https://patchwork.freedesktop.org/series/19666/
State : failure
== Summary ==
Series 19666v4 drm: Add DPCD definitions for DP 1.4 DSC feature
https://patchwork.freedesktop.org/api/1.0/series/19666/revisions/4/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-wb:
pass -> INCOMPLETE (fi-skl-6770hq)
Subgroup basic-uc-pro-default:
pass -> INCOMPLETE (fi-skl-6700hq) fdo#100130
Subgroup basic-uc-ro-default:
pass -> INCOMPLETE (fi-skl-6260u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2520m)
fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 455s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 579s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 543s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 558s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 500s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 502s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 448s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 497s
fi-skl-6260u total:55 pass:53 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-skl-6700hq total:53 pass:45 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-skl-6770hq total:52 pass:50 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 551s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 418s
c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
88ee5288 drm: Add DPCD definitions for DP 1.4 DSC feature
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4171/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
2017-03-15 8:32 ` ✗ Fi.CI.BAT: failure for drm: Add DPCD definitions for DP 1.4 DSC feature (rev4) Patchwork
@ 2017-03-15 8:46 ` Patchwork
2017-03-15 8:49 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-03-15 8:46 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
URL : https://patchwork.freedesktop.org/series/19666/
State : failure
== Summary ==
Series 19666v4 drm: Add DPCD definitions for DP 1.4 DSC feature
https://patchwork.freedesktop.org/api/1.0/series/19666/revisions/4/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-wb:
pass -> INCOMPLETE (fi-skl-6770hq)
Subgroup basic-uc-pro-default:
pass -> INCOMPLETE (fi-skl-6700hq) fdo#100130
Subgroup basic-uc-ro-default:
pass -> INCOMPLETE (fi-skl-6260u) fdo#100130
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2520m)
fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 455s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 579s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 543s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 558s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 500s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 502s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 448s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 497s
fi-skl-6260u total:55 pass:53 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-skl-6700hq total:53 pass:45 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-skl-6770hq total:52 pass:50 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 551s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 418s
c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
88ee5288 drm: Add DPCD definitions for DP 1.4 DSC feature
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4171/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
2017-03-15 8:32 ` ✗ Fi.CI.BAT: failure for drm: Add DPCD definitions for DP 1.4 DSC feature (rev4) Patchwork
2017-03-15 8:46 ` Patchwork
@ 2017-03-15 8:49 ` Patchwork
2017-03-16 13:47 ` [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Ander Conselvan De Oliveira
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-03-15 8:49 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 DSC feature (rev4)
URL : https://patchwork.freedesktop.org/series/19666/
State : success
== Summary ==
Series 19666v4 drm: Add DPCD definitions for DP 1.4 DSC feature
https://patchwork.freedesktop.org/api/1.0/series/19666/revisions/4/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-wb:
pass -> INCOMPLETE (fi-skl-6770hq) fdo#100130
Subgroup basic-uc-pro-default:
pass -> INCOMPLETE (fi-skl-6700hq) fdo#100130
Subgroup basic-uc-ro-default:
pass -> INCOMPLETE (fi-skl-6260u) fdo#100130
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2520m)
fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 455s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 579s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 543s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 558s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 500s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 502s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 448s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 497s
fi-skl-6260u total:55 pass:53 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-skl-6700hq total:53 pass:45 dwarn:0 dfail:0 fail:0 skip:7 time: 0s
fi-skl-6770hq total:52 pass:50 dwarn:0 dfail:0 fail:0 skip:1 time: 0s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 551s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 418s
c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
88ee5288 drm: Add DPCD definitions for DP 1.4 DSC feature
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4171/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
` (2 preceding siblings ...)
2017-03-15 8:49 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2017-03-16 13:47 ` Ander Conselvan De Oliveira
2017-04-03 22:35 ` Manasi Navare
2017-04-03 22:51 ` [PATCH v4] " Manasi Navare
2017-04-03 23:04 ` ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 DSC feature (rev5) Patchwork
5 siblings, 1 reply; 10+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-03-16 13:47 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Paulo Zanoni, dri-devel
On Tue, 2017-03-14 at 13:01 -0700, Manasi Navare wrote:
> From: "Navare, Manasi D" <manasi.d.navare@intel.com>
>
> Display stream compression is supported on DP 1.4 DP
> devices. This patch adds the corersponding DPCD
> register definitions for DSC.
>
> v3:
> * Add some SHIFTS and MASKS for uniformity (Jani Nikula)
> v2:
> * Rebased on drm-tip
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> ---
> include/drm/drm_dp_helper.h | 105 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 105 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c0bd0d7..e1fb04f 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -179,6 +179,111 @@
>
> #define DP_GUID 0x030 /* 1.2 */
>
> +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
> +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_REV 0x061
> +# define DP_DSC_MAJOR_MASK (0xf << 0)
> +# define DP_DSC_MINOR_MASK (0xf << 4)
> +# define DP_DSC_MAJOR_SHIFT 0
> +# define DP_DSC_MINOR_SHIFT 4
> +
> +#define DP_DSC_RC_BUF_BLK_SIZE 0x062
> +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
> +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> +
> +#define DP_DSC_RC_BUF_SIZE 0x063
> +
> +#define DP_DSC_SLICE_CAP_1 0x064
> +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
> +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
> +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
> +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
> +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
> +
> +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
> +
> +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
> +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
> +
> +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
> +# define DP_DSC_RGB (1 << 0)
> +# define DP_DSC_YCbCr444 (1 << 1)
> +# define DP_DSC_YCbCr422_Simple (1 << 2)
> +# define DP_DSC_YCbCr422_Native (1 << 3)
> +# define DP_DSC_YCbCr420_Native (1 << 4)
> +
> +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
> +# define DP_DSC_8_BPC (1 << 1)
> +# define DP_DSC_10_BPC (1 << 2)
> +# define DP_DSC_12_BPC (1 << 3)
> +
> +#define DP_DSC_PEAK_THROUGHPUT 0x06B
> +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
> +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
> +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
> +
> +#define DP_DSC_MAX_SLICE_WIDTH 0x06C
> +
> +#define DP_DSC_SLICE_CAP_2 0x06D
> +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
> +
> +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
> +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
> +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
> +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
> +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
> +# define DP_DSC_BITS_PER_PIXEL_1 0x4
> +
Maybe add the DSC enable dpcd too (0x160)?
Ander
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature
2017-03-16 13:47 ` [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Ander Conselvan De Oliveira
@ 2017-04-03 22:35 ` Manasi Navare
0 siblings, 0 replies; 10+ messages in thread
From: Manasi Navare @ 2017-04-03 22:35 UTC (permalink / raw)
To: Ander Conselvan De Oliveira; +Cc: intel-gfx, Paulo Zanoni, dri-devel
On Thu, Mar 16, 2017 at 03:47:46PM +0200, Ander Conselvan De Oliveira wrote:
> On Tue, 2017-03-14 at 13:01 -0700, Manasi Navare wrote:
> > From: "Navare, Manasi D" <manasi.d.navare@intel.com>
> >
> > Display stream compression is supported on DP 1.4 DP
> > devices. This patch adds the corersponding DPCD
> > register definitions for DSC.
> >
> > v3:
> > * Add some SHIFTS and MASKS for uniformity (Jani Nikula)
> > v2:
> > * Rebased on drm-tip
> >
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: dri-devel@lists.freedesktop.org
> > ---
> > include/drm/drm_dp_helper.h | 105 ++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 105 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index c0bd0d7..e1fb04f 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -179,6 +179,111 @@
> >
> > #define DP_GUID 0x030 /* 1.2 */
> >
> > +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
> > +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
> > +
> > +#define DP_DSC_REV 0x061
> > +# define DP_DSC_MAJOR_MASK (0xf << 0)
> > +# define DP_DSC_MINOR_MASK (0xf << 4)
> > +# define DP_DSC_MAJOR_SHIFT 0
> > +# define DP_DSC_MINOR_SHIFT 4
> > +
> > +#define DP_DSC_RC_BUF_BLK_SIZE 0x062
> > +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
> > +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> > +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> > +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> > +
> > +#define DP_DSC_RC_BUF_SIZE 0x063
> > +
> > +#define DP_DSC_SLICE_CAP_1 0x064
> > +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
> > +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
> > +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
> > +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
> > +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
> > +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
> > +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
> > +
> > +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
> > +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
> > +
> > +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
> > +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> > +
> > +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
> > +
> > +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
> > +
> > +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
> > +# define DP_DSC_RGB (1 << 0)
> > +# define DP_DSC_YCbCr444 (1 << 1)
> > +# define DP_DSC_YCbCr422_Simple (1 << 2)
> > +# define DP_DSC_YCbCr422_Native (1 << 3)
> > +# define DP_DSC_YCbCr420_Native (1 << 4)
> > +
> > +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
> > +# define DP_DSC_8_BPC (1 << 1)
> > +# define DP_DSC_10_BPC (1 << 2)
> > +# define DP_DSC_12_BPC (1 << 3)
> > +
> > +#define DP_DSC_PEAK_THROUGHPUT 0x06B
> > +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
> > +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
> > +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
> > +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
> > +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
> > +
> > +#define DP_DSC_MAX_SLICE_WIDTH 0x06C
> > +
> > +#define DP_DSC_SLICE_CAP_2 0x06D
> > +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
> > +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
> > +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
> > +
> > +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
> > +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
> > +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
> > +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
> > +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
> > +# define DP_DSC_BITS_PER_PIXEL_1 0x4
> > +
>
> Maybe add the DSC enable dpcd too (0x160)?
>
> Ander
>
Thanks for catching this. I missed it because after
0x06F it says end of DSC register set. I will add this and
submit a new revision.
Regards
Manasi
>
> > #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> > # define DP_PSR_IS_SUPPORTED 1
> > # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4] drm: Add DPCD definitions for DP 1.4 DSC feature
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
` (3 preceding siblings ...)
2017-03-16 13:47 ` [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Ander Conselvan De Oliveira
@ 2017-04-03 22:51 ` Manasi Navare
2017-04-06 21:37 ` Manasi Navare
2017-04-20 14:47 ` Jani Nikula
2017-04-03 23:04 ` ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 DSC feature (rev5) Patchwork
5 siblings, 2 replies; 10+ messages in thread
From: Manasi Navare @ 2017-04-03 22:51 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Paulo Zanoni
From: "Navare, Manasi D" <manasi.d.navare@intel.com>
Display stream compression is supported on DP 1.4 DP
devices. This patch adds the corersponding DPCD
register definitions for DSC.
v4:
* Add DSC Enable DPCD register def (Ander)
v3:
* Add some SHIFTS and MASKS for uniformity (Jani Nikula)
v2:
* Rebased on drm-tip
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: dri-devel@lists.freedesktop.org
---
include/drm/drm_dp_helper.h | 107 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c0bd0d7..f6258ed 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -179,6 +179,111 @@
#define DP_GUID 0x030 /* 1.2 */
+#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
+# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
+
+#define DP_DSC_REV 0x061
+# define DP_DSC_MAJOR_MASK (0xf << 0)
+# define DP_DSC_MINOR_MASK (0xf << 4)
+# define DP_DSC_MAJOR_SHIFT 0
+# define DP_DSC_MINOR_SHIFT 4
+
+#define DP_DSC_RC_BUF_BLK_SIZE 0x062
+# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
+# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
+# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
+# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
+
+#define DP_DSC_RC_BUF_SIZE 0x063
+
+#define DP_DSC_SLICE_CAP_1 0x064
+# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
+# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
+# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
+# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
+# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
+# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
+# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
+
+#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
+# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
+# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
+# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
+# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
+# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
+# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
+# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
+# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
+# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
+# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
+
+#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
+# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
+
+#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
+
+#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
+
+#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
+# define DP_DSC_RGB (1 << 0)
+# define DP_DSC_YCbCr444 (1 << 1)
+# define DP_DSC_YCbCr422_Simple (1 << 2)
+# define DP_DSC_YCbCr422_Native (1 << 3)
+# define DP_DSC_YCbCr420_Native (1 << 4)
+
+#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
+# define DP_DSC_8_BPC (1 << 1)
+# define DP_DSC_10_BPC (1 << 2)
+# define DP_DSC_12_BPC (1 << 3)
+
+#define DP_DSC_PEAK_THROUGHPUT 0x06B
+# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
+# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
+# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
+# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
+# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
+# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
+
+#define DP_DSC_MAX_SLICE_WIDTH 0x06C
+
+#define DP_DSC_SLICE_CAP_2 0x06D
+# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
+# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
+# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
+
+#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
+# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
+# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
+# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
+# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
+# define DP_DSC_BITS_PER_PIXEL_1 0x4
+
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
# define DP_PSR_IS_SUPPORTED 1
# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
@@ -339,6 +444,8 @@
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
+#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
--
2.1.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4] drm: Add DPCD definitions for DP 1.4 DSC feature
2017-04-03 22:51 ` [PATCH v4] " Manasi Navare
@ 2017-04-06 21:37 ` Manasi Navare
2017-04-20 14:47 ` Jani Nikula
1 sibling, 0 replies; 10+ messages in thread
From: Manasi Navare @ 2017-04-06 21:37 UTC (permalink / raw)
To: intel-gfx, ander.conselvan.de.oliveira; +Cc: dri-devel, Paulo Zanoni
Hi Ander,
Could you take a look at this?
Manasi
On Mon, Apr 03, 2017 at 03:51:10PM -0700, Manasi Navare wrote:
> From: "Navare, Manasi D" <manasi.d.navare@intel.com>
>
> Display stream compression is supported on DP 1.4 DP
> devices. This patch adds the corersponding DPCD
> register definitions for DSC.
>
> v4:
> * Add DSC Enable DPCD register def (Ander)
> v3:
> * Add some SHIFTS and MASKS for uniformity (Jani Nikula)
> v2:
> * Rebased on drm-tip
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> ---
> include/drm/drm_dp_helper.h | 107 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c0bd0d7..f6258ed 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -179,6 +179,111 @@
>
> #define DP_GUID 0x030 /* 1.2 */
>
> +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
> +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_REV 0x061
> +# define DP_DSC_MAJOR_MASK (0xf << 0)
> +# define DP_DSC_MINOR_MASK (0xf << 4)
> +# define DP_DSC_MAJOR_SHIFT 0
> +# define DP_DSC_MINOR_SHIFT 4
> +
> +#define DP_DSC_RC_BUF_BLK_SIZE 0x062
> +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
> +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> +
> +#define DP_DSC_RC_BUF_SIZE 0x063
> +
> +#define DP_DSC_SLICE_CAP_1 0x064
> +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
> +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
> +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
> +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
> +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
> +
> +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
> +
> +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
> +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
> +
> +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
> +# define DP_DSC_RGB (1 << 0)
> +# define DP_DSC_YCbCr444 (1 << 1)
> +# define DP_DSC_YCbCr422_Simple (1 << 2)
> +# define DP_DSC_YCbCr422_Native (1 << 3)
> +# define DP_DSC_YCbCr420_Native (1 << 4)
> +
> +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
> +# define DP_DSC_8_BPC (1 << 1)
> +# define DP_DSC_10_BPC (1 << 2)
> +# define DP_DSC_12_BPC (1 << 3)
> +
> +#define DP_DSC_PEAK_THROUGHPUT 0x06B
> +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
> +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
> +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
> +
> +#define DP_DSC_MAX_SLICE_WIDTH 0x06C
> +
> +#define DP_DSC_SLICE_CAP_2 0x06D
> +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
> +
> +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
> +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
> +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
> +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
> +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
> +# define DP_DSC_BITS_PER_PIXEL_1 0x4
> +
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
> @@ -339,6 +444,8 @@
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
> +#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
> --
> 2.1.4
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4] drm: Add DPCD definitions for DP 1.4 DSC feature
2017-04-03 22:51 ` [PATCH v4] " Manasi Navare
2017-04-06 21:37 ` Manasi Navare
@ 2017-04-20 14:47 ` Jani Nikula
1 sibling, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2017-04-20 14:47 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Paulo Zanoni, dri-devel
On Tue, 04 Apr 2017, Manasi Navare <manasi.d.navare@intel.com> wrote:
> From: "Navare, Manasi D" <manasi.d.navare@intel.com>
>
> Display stream compression is supported on DP 1.4 DP
> devices. This patch adds the corersponding DPCD
> register definitions for DSC.
>
> v4:
> * Add DSC Enable DPCD register def (Ander)
> v3:
> * Add some SHIFTS and MASKS for uniformity (Jani Nikula)
> v2:
> * Rebased on drm-tip
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: dri-devel@lists.freedesktop.org
Pushed to drm-misc-next, thanks for the patch.
BR,
Jani.
> ---
> include/drm/drm_dp_helper.h | 107 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c0bd0d7..f6258ed 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -179,6 +179,111 @@
>
> #define DP_GUID 0x030 /* 1.2 */
>
> +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
> +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_REV 0x061
> +# define DP_DSC_MAJOR_MASK (0xf << 0)
> +# define DP_DSC_MINOR_MASK (0xf << 4)
> +# define DP_DSC_MAJOR_SHIFT 0
> +# define DP_DSC_MINOR_SHIFT 4
> +
> +#define DP_DSC_RC_BUF_BLK_SIZE 0x062
> +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
> +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
> +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
> +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
> +
> +#define DP_DSC_RC_BUF_SIZE 0x063
> +
> +#define DP_DSC_SLICE_CAP_1 0x064
> +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
> +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
> +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
> +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
> +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
> +
> +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
> +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
> +
> +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
> +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
> +
> +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
> +
> +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
> +# define DP_DSC_RGB (1 << 0)
> +# define DP_DSC_YCbCr444 (1 << 1)
> +# define DP_DSC_YCbCr422_Simple (1 << 2)
> +# define DP_DSC_YCbCr422_Native (1 << 3)
> +# define DP_DSC_YCbCr420_Native (1 << 4)
> +
> +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
> +# define DP_DSC_8_BPC (1 << 1)
> +# define DP_DSC_10_BPC (1 << 2)
> +# define DP_DSC_12_BPC (1 << 3)
> +
> +#define DP_DSC_PEAK_THROUGHPUT 0x06B
> +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
> +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
> +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
> +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
> +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
> +
> +#define DP_DSC_MAX_SLICE_WIDTH 0x06C
> +
> +#define DP_DSC_SLICE_CAP_2 0x06D
> +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
> +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
> +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
> +
> +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
> +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
> +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
> +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
> +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
> +# define DP_DSC_BITS_PER_PIXEL_1 0x4
> +
> #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
> # define DP_PSR_IS_SUPPORTED 1
> # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
> @@ -339,6 +444,8 @@
> #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
> # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
>
> +#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> +
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE (1 << 0)
> # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm: Add DPCD definitions for DP 1.4 DSC feature (rev5)
2017-03-14 20:01 [PATCH v3] drm: Add DPCD definitions for DP 1.4 DSC feature Manasi Navare
` (4 preceding siblings ...)
2017-04-03 22:51 ` [PATCH v4] " Manasi Navare
@ 2017-04-03 23:04 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-04-03 23:04 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm: Add DPCD definitions for DP 1.4 DSC feature (rev5)
URL : https://patchwork.freedesktop.org/series/19666/
State : success
== Summary ==
Series 19666v5 drm: Add DPCD definitions for DP 1.4 DSC feature
https://patchwork.freedesktop.org/api/1.0/series/19666/revisions/5/mbox/
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 430s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time: 425s
fi-bsw-n3050 total:278 pass:239 dwarn:0 dfail:0 fail:0 skip:39 time: 583s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 508s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 551s
fi-byt-j1900 total:278 pass:251 dwarn:0 dfail:0 fail:0 skip:27 time: 487s
fi-byt-n2820 total:278 pass:247 dwarn:0 dfail:0 fail:0 skip:31 time: 494s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 402s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 405s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 422s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 485s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 477s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 456s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time: 566s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 457s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 570s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 456s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 491s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time: 432s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 533s
fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time: 406s
5bc82ec7f62322a91ecf48fa966e68c876637fcd drm-tip: 2017y-04m-03d-16h-44m-48s UTC integration manifest
fd63abe drm: Add DPCD definitions for DP 1.4 DSC feature
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4386/
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^ permalink raw reply [flat|nested] 10+ messages in thread