Re: [PATCH v4 1/7] coresight: bindings for CPU debug module

From: Leo Yan <leo.yan@linaro.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, Guodong Xu <guodong.xu@linaro.org>,
	Suzuki.Poulose@arm.com, Catalin Marinas <catalin.marinas@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	sudeep.holla@arm.com, Will Deacon <will.deacon@arm.com>,
	linux-kernel@vger.kernel.org, Wei Xu <xuwei5@hisilicon.com>,
	linux-clk@vger.kernel.org, David Brown <david.brown@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	John Stultz <john.stultz@linaro.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Andy Gross <andy.gross@linaro.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v4 1/7] coresight: bindings for CPU debug module
Date: Mon, 20 Mar 2017 19:49:53 +0800	[thread overview]
Message-ID: <20170320114953.GA19581@leoy-linaro> (raw)
In-Reply-To: <20170317161335.GB20435@linaro.org>

Hi Mathieu,

On Fri, Mar 17, 2017 at 10:13:35AM -0600, Mathieu Poirier wrote:

[...]

> > +- compatible : should be
> > +	     * "arm,coresight-cpu-debug"; supplemented with "arm,primecell"
> > +	       since this driver is using the AMBA bus interface.
> 
> This description needs to be refactored - see my comment from an earlier post
> for more details.

I have refined this description according to your suggestion:
http://archive.armlinux.org.uk/lurker/message/20170301.154550.f55a09d5.en.html

Am I missing anthing for this?

> > +- reg : physical base address and length of the register set.
> > +
> > +- clocks : the clock associated to this component.
> > +
> > +- clock-names : the name of the clock referenced by the code. Since we are
> > +                using the AMBA framework, the name of the clock providing
> > +		the interconnect should be "apb_pclk" and the clock is
> > +		mandatory. The interface between the debug logic and the
> > +		processor core is clocked by the internal CPU clock, so it
> > +		is enabled with CPU clock by default.
> > +
> > +- cpu : the cpu phandle the debug module is affined to. When omitted
> > +	the module is considered to belong to CPU0.
> > +
> > +Optional properties:
> 
> s/properties/property
> 
> > +
> > +- power-domains: a phandle to power domain node for debug module. We can
> > +		 use "nohlt" to ensure CPU power domain is enabled.
> 
> The "power-domains" property is to take care of the debug power domain.  The
> "nohlt" is to make sure registers in the CPU power domain are accessible - both
> are independent from one another.  As such the description for this binding
> shoudl be:
> 
> "a phandle to the debug power domain".

Will fix for upper two comments.

Thanks,
Leo Yan