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* [PATCH] kvm/svm: Setup MCG_CAP on AMD properly
@ 2017-03-26 21:51 Borislav Petkov
  2017-03-28  8:17 ` Paolo Bonzini
  0 siblings, 1 reply; 2+ messages in thread
From: Borislav Petkov @ 2017-03-26 21:51 UTC (permalink / raw)
  To: KVM; +Cc: LKML, Joerg Roedel, Paolo Bonzini, Radim Krčmář

From: Borislav Petkov <bp@suse.de>

MCG_CAP[63:9] bits are reserved on AMD. However, on an AMD guest, this
MSR returns 0x100010a. More specifically, bit 24 is set, which is simply
wrong. That bit is MCG_SER_P and is present only on Intel. Thus, clean
up the reserved bits in order not to confuse guests.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
---
 arch/x86/kvm/svm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index c02b9af2056a..aba6100ebb8d 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -5251,6 +5251,12 @@ static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
 	avic_handle_ldr_update(vcpu);
 }
 
+static void svm_setup_mce(struct kvm_vcpu *vcpu)
+{
+	/* [63:9] are reserved. */
+	vcpu->arch.mcg_cap &= 0x1ff;
+}
+
 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
 	.cpu_has_kvm_support = has_svm,
 	.disabled_by_bios = is_disabled,
@@ -5362,6 +5368,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
 	.pmu_ops = &amd_pmu_ops,
 	.deliver_posted_interrupt = svm_deliver_avic_intr,
 	.update_pi_irte = svm_update_pi_irte,
+	.setup_mce = svm_setup_mce,
 };
 
 static int __init svm_init(void)
-- 
2.11.0

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] kvm/svm: Setup MCG_CAP on AMD properly
  2017-03-26 21:51 [PATCH] kvm/svm: Setup MCG_CAP on AMD properly Borislav Petkov
@ 2017-03-28  8:17 ` Paolo Bonzini
  0 siblings, 0 replies; 2+ messages in thread
From: Paolo Bonzini @ 2017-03-28  8:17 UTC (permalink / raw)
  To: Borislav Petkov, KVM; +Cc: LKML, Joerg Roedel, Radim Krčmář



On 26/03/2017 23:51, Borislav Petkov wrote:
> From: Borislav Petkov <bp@suse.de>
> 
> MCG_CAP[63:9] bits are reserved on AMD. However, on an AMD guest, this
> MSR returns 0x100010a. More specifically, bit 24 is set, which is simply
> wrong. That bit is MCG_SER_P and is present only on Intel. Thus, clean
> up the reserved bits in order not to confuse guests.
> 
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Cc: Joerg Roedel <joro@8bytes.org>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: "Radim Krčmář" <rkrcmar@redhat.com>
> ---
>  arch/x86/kvm/svm.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index c02b9af2056a..aba6100ebb8d 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -5251,6 +5251,12 @@ static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
>  	avic_handle_ldr_update(vcpu);
>  }
>  
> +static void svm_setup_mce(struct kvm_vcpu *vcpu)
> +{
> +	/* [63:9] are reserved. */
> +	vcpu->arch.mcg_cap &= 0x1ff;
> +}
> +
>  static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
>  	.cpu_has_kvm_support = has_svm,
>  	.disabled_by_bios = is_disabled,
> @@ -5362,6 +5368,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
>  	.pmu_ops = &amd_pmu_ops,
>  	.deliver_posted_interrupt = svm_deliver_avic_intr,
>  	.update_pi_irte = svm_update_pi_irte,
> +	.setup_mce = svm_setup_mce,
>  };
>  
>  static int __init svm_init(void)
> 

Queued for 4.12, thanks.

Paolo

^ permalink raw reply	[flat|nested] 2+ messages in thread

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