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* [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3
@ 2017-03-25 11:32 Chris Wilson
  2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Chris Wilson @ 2017-03-25 11:32 UTC (permalink / raw)
  To: intel-gfx; +Cc: # v4 . 11-rc1+

Old devices have quite severe restrictions for using fences, and unlike
more recent device (anything from Pineview onwards) we need to enforce
those restrictions even for unfenced tiled access from the render
pipeline.

Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+
---
 drivers/gpu/drm/i915/i915_drv.h            | 1 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c            | 5 +++++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2911c49113b0..86f097db8ef6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -853,6 +853,7 @@ struct intel_csr {
 	func(has_resource_streamer); \
 	func(has_runtime_pm); \
 	func(has_snoop); \
+	func(unfenced_needs_alignment); \
 	func(cursor_needs_physical); \
 	func(hws_needs_physical); \
 	func(overlay_needs_physical); \
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index dd7181ed5eca..a3e59c8ef27b 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -890,6 +890,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 	struct list_head ordered_vmas;
 	struct list_head pinned_vmas;
 	bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
+	bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment;
 	int retry;
 
 	vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
@@ -910,7 +911,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 		if (!has_fenced_gpu_access)
 			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 		need_fence =
-			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
+			(entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
+			 needs_unfenced_map) &&
 			i915_gem_object_is_tiled(obj);
 		need_mappable = need_fence || need_reloc_mappable(vma);
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 732101ed57fb..f87b0c4e564d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -61,6 +61,7 @@
 	.has_overlay = 1, .overlay_needs_physical = 1, \
 	.has_gmch_display = 1, \
 	.hws_needs_physical = 1, \
+	.unfenced_needs_alignment = 1, \
 	.ring_mask = RENDER_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -102,6 +103,7 @@ static const struct intel_device_info intel_i915g_info = {
 	.platform = INTEL_I915G, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.hws_needs_physical = 1,
+	.unfenced_needs_alignment = 1,
 };
 
 static const struct intel_device_info intel_i915gm_info = {
@@ -113,6 +115,7 @@ static const struct intel_device_info intel_i915gm_info = {
 	.supports_tv = 1,
 	.has_fbc = 1,
 	.hws_needs_physical = 1,
+	.unfenced_needs_alignment = 1,
 };
 
 static const struct intel_device_info intel_i945g_info = {
@@ -121,6 +124,7 @@ static const struct intel_device_info intel_i945g_info = {
 	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.hws_needs_physical = 1,
+	.unfenced_needs_alignment = 1,
 };
 
 static const struct intel_device_info intel_i945gm_info = {
@@ -131,6 +135,7 @@ static const struct intel_device_info intel_i945gm_info = {
 	.supports_tv = 1,
 	.has_fbc = 1,
 	.hws_needs_physical = 1,
+	.unfenced_needs_alignment = 1,
 };
 
 static const struct intel_device_info intel_g33_info = {
-- 
2.11.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* ✗ Fi.CI.BAT: failure for drm/i915: Align "unfenced" tiled access on gen2, early gen3
  2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
@ 2017-03-25 11:55 ` Patchwork
  2017-03-27 12:24   ` Chris Wilson
  2017-03-27  7:10 ` [PATCH] " Daniel Vetter
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2017-03-25 11:55 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Align "unfenced" tiled access on gen2, early gen3
URL   : https://patchwork.freedesktop.org/series/21878/
State : failure

== Summary ==

Series 21878v1 drm/i915: Align "unfenced" tiled access on gen2, early gen3
https://patchwork.freedesktop.org/api/1.0/series/21878/revisions/1/mbox/

Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> INCOMPLETE (fi-byt-j1900)
Test kms_cursor_legacy:
        Subgroup basic-flip-before-cursor-varying-size:
                dmesg-warn -> PASS       (fi-byt-n2820) fdo#100094

fdo#100094 https://bugs.freedesktop.org/show_bug.cgi?id=100094

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 463s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 459s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 583s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 540s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 576s
fi-byt-j1900     total:5    pass:4    dwarn:0   dfail:0   fail:0   skip:0   time: 0s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 512s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 438s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 436s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 442s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 516s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 487s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 484s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 485s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 601s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 490s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 521s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 469s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 547s
fi-snb-2600 failed to collect. IGT log at Patchwork_4302/fi-snb-2600/igt.log

102397b5dbb1f68504739adefde2c28a5aba95b9 drm-tip: 2017y-03m-25d-00h-24m-58s UTC integration manifest
7e9f840 drm/i915: Align "unfenced" tiled access on gen2, early gen3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4302/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3
  2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
  2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-03-27  7:10 ` Daniel Vetter
  2017-03-27 10:22 ` Joonas Lahtinen
  2017-03-27 10:36 ` Ville Syrjälä
  3 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2017-03-27  7:10 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx, # v4 . 11-rc1+

On Sat, Mar 25, 2017 at 11:32:43AM +0000, Chris Wilson wrote:
> Old devices have quite severe restrictions for using fences, and unlike
> more recent device (anything from Pineview onwards) we need to enforce
> those restrictions even for unfenced tiled access from the render
> pipeline.
> 
> Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/i915_drv.h            | 1 +
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c            | 5 +++++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2911c49113b0..86f097db8ef6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -853,6 +853,7 @@ struct intel_csr {
>  	func(has_resource_streamer); \
>  	func(has_runtime_pm); \
>  	func(has_snoop); \
> +	func(unfenced_needs_alignment); \
>  	func(cursor_needs_physical); \
>  	func(hws_needs_physical); \
>  	func(overlay_needs_physical); \
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index dd7181ed5eca..a3e59c8ef27b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -890,6 +890,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  	struct list_head ordered_vmas;
>  	struct list_head pinned_vmas;
>  	bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
> +	bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment;
>  	int retry;
>  
>  	vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
> @@ -910,7 +911,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  		if (!has_fenced_gpu_access)
>  			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
>  		need_fence =
> -			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
> +			(entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
> +			 needs_unfenced_map) &&
>  			i915_gem_object_is_tiled(obj);
>  		need_mappable = need_fence || need_reloc_mappable(vma);
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 732101ed57fb..f87b0c4e564d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -61,6 +61,7 @@
>  	.has_overlay = 1, .overlay_needs_physical = 1, \
>  	.has_gmch_display = 1, \
>  	.hws_needs_physical = 1, \
> +	.unfenced_needs_alignment = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -102,6 +103,7 @@ static const struct intel_device_info intel_i915g_info = {
>  	.platform = INTEL_I915G, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i915gm_info = {
> @@ -113,6 +115,7 @@ static const struct intel_device_info intel_i915gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945g_info = {
> @@ -121,6 +124,7 @@ static const struct intel_device_info intel_i945g_info = {
>  	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945gm_info = {
> @@ -131,6 +135,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
> -- 
> 2.11.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3
  2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
  2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
  2017-03-27  7:10 ` [PATCH] " Daniel Vetter
@ 2017-03-27 10:22 ` Joonas Lahtinen
  2017-03-27 10:36 ` Ville Syrjälä
  3 siblings, 0 replies; 6+ messages in thread
From: Joonas Lahtinen @ 2017-03-27 10:22 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx; +Cc: # v4 . 11-rc1+

On la, 2017-03-25 at 11:32 +0000, Chris Wilson wrote:
> Old devices have quite severe restrictions for using fences, and unlike
> more recent device (anything from Pineview onwards) we need to enforce
> those restrictions even for unfenced tiled access from the render
> pipeline.
> 
> Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Could use some T-bs.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3
  2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
                   ` (2 preceding siblings ...)
  2017-03-27 10:22 ` Joonas Lahtinen
@ 2017-03-27 10:36 ` Ville Syrjälä
  3 siblings, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2017-03-27 10:36 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx, # v4 . 11-rc1+

On Sat, Mar 25, 2017 at 11:32:43AM +0000, Chris Wilson wrote:
> Old devices have quite severe restrictions for using fences, and unlike
> more recent device (anything from Pineview onwards) we need to enforce
> those restrictions even for unfenced tiled access from the render
> pipeline.
> 
> Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+

Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h            | 1 +
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c            | 5 +++++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2911c49113b0..86f097db8ef6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -853,6 +853,7 @@ struct intel_csr {
>  	func(has_resource_streamer); \
>  	func(has_runtime_pm); \
>  	func(has_snoop); \
> +	func(unfenced_needs_alignment); \
>  	func(cursor_needs_physical); \
>  	func(hws_needs_physical); \
>  	func(overlay_needs_physical); \
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index dd7181ed5eca..a3e59c8ef27b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -890,6 +890,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  	struct list_head ordered_vmas;
>  	struct list_head pinned_vmas;
>  	bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
> +	bool needs_unfenced_map = INTEL_INFO(engine->i915)->unfenced_needs_alignment;
>  	int retry;
>  
>  	vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
> @@ -910,7 +911,8 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
>  		if (!has_fenced_gpu_access)
>  			entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
>  		need_fence =
> -			entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
> +			(entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
> +			 needs_unfenced_map) &&
>  			i915_gem_object_is_tiled(obj);
>  		need_mappable = need_fence || need_reloc_mappable(vma);
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 732101ed57fb..f87b0c4e564d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -61,6 +61,7 @@
>  	.has_overlay = 1, .overlay_needs_physical = 1, \
>  	.has_gmch_display = 1, \
>  	.hws_needs_physical = 1, \
> +	.unfenced_needs_alignment = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -102,6 +103,7 @@ static const struct intel_device_info intel_i915g_info = {
>  	.platform = INTEL_I915G, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i915gm_info = {
> @@ -113,6 +115,7 @@ static const struct intel_device_info intel_i915gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945g_info = {
> @@ -121,6 +124,7 @@ static const struct intel_device_info intel_i945g_info = {
>  	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_i945gm_info = {
> @@ -131,6 +135,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  	.supports_tv = 1,
>  	.has_fbc = 1,
>  	.hws_needs_physical = 1,
> +	.unfenced_needs_alignment = 1,
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: ✗ Fi.CI.BAT: failure for drm/i915: Align "unfenced" tiled access on gen2, early gen3
  2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-03-27 12:24   ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-03-27 12:24 UTC (permalink / raw)
  To: intel-gfx

On Sat, Mar 25, 2017 at 11:55:52AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Align "unfenced" tiled access on gen2, early gen3
> URL   : https://patchwork.freedesktop.org/series/21878/
> State : failure
> 
> == Summary ==
> 
> Series 21878v1 drm/i915: Align "unfenced" tiled access on gen2, early gen3
> https://patchwork.freedesktop.org/api/1.0/series/21878/revisions/1/mbox/
> 
> Test drv_hangman:
>         Subgroup error-state-basic:
>                 pass       -> INCOMPLETE (fi-byt-j1900)

Unrelated silent failure :|

> Test kms_cursor_legacy:
>         Subgroup basic-flip-before-cursor-varying-size:
>                 dmesg-warn -> PASS       (fi-byt-n2820) fdo#100094
> 
> fdo#100094 https://bugs.freedesktop.org/show_bug.cgi?id=100094

Pushed, thanks for the bug report, testing and review.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2017-03-27 12:24 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-25 11:32 [PATCH] drm/i915: Align "unfenced" tiled access on gen2, early gen3 Chris Wilson
2017-03-25 11:55 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-03-27 12:24   ` Chris Wilson
2017-03-27  7:10 ` [PATCH] " Daniel Vetter
2017-03-27 10:22 ` Joonas Lahtinen
2017-03-27 10:36 ` Ville Syrjälä

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