[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Hi,

>From functional code point of view, this is mostly just a rebase of v1 of the
series on top of 4.11-rc1:

https://www.spinics.net/lists/arm-kernel/msg562460.html

This series depends on the TI clock cleanup series I posted last week:

https://www.spinics.net/lists/arm-kernel/msg567920.html

Patch #5 has been changed to accommodate for the existence of multiple
hwmods under single DT node, for example the "ocp" node for omap4
contains 3 hwmods for the different buses; support for this is enabled
by accepting index for the clkctrl clocks also.

Patch #6 is a new one to properly assign the clock for timers. This is
needed as currently timer code only fetches the main clock info from
hwmod itself.

Patches #7, #8 and #9 add the DT data for omap4.

Boot tested on am335x-evm, am335x-evmsk, am47x-evm, am437x-sk, am437x-gp-evm,
  am57xx-evm, omap3-beagle-xm, omap3-beagle, am335x-boneblack, craneboard,
  dra72x-evm, dra7xx-evm, n900, omap5-uevm, omap4-panda-es, omap4-panda,
  omap2430-sdp, omap3430-sdp, omap4430-sdp.

Suspend-resume tested on omap4-panda-es.

Any additional testing on omap4 welcome as this series basically
tweaks every possible peripheral clock on the SoC.

Branch available on top of 4.11-rc1 (+ the cleanup series) here:

tree: https://github.com/t-kristo/linux-pm.git
branch: for-4.12-ti-clkctrl

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Hi,

>From functional code point of view, this is mostly just a rebase of v1 of the
series on top of 4.11-rc1:

https://www.spinics.net/lists/arm-kernel/msg562460.html

This series depends on the TI clock cleanup series I posted last week:

https://www.spinics.net/lists/arm-kernel/msg567920.html

Patch #5 has been changed to accommodate for the existence of multiple
hwmods under single DT node, for example the "ocp" node for omap4
contains 3 hwmods for the different buses; support for this is enabled
by accepting index for the clkctrl clocks also.

Patch #6 is a new one to properly assign the clock for timers. This is
needed as currently timer code only fetches the main clock info from
hwmod itself.

Patches #7, #8 and #9 add the DT data for omap4.

Boot tested on am335x-evm, am335x-evmsk, am47x-evm, am437x-sk, am437x-gp-evm,
  am57xx-evm, omap3-beagle-xm, omap3-beagle, am335x-boneblack, craneboard,
  dra72x-evm, dra7xx-evm, n900, omap5-uevm, omap4-panda-es, omap4-panda,
  omap2430-sdp, omap3430-sdp, omap4430-sdp.

Suspend-resume tested on omap4-panda-es.

Any additional testing on omap4 welcome as this series basically
tweaks every possible peripheral clock on the SoC.

Branch available on top of 4.11-rc1 (+ the cleanup series) here:

tree: https://github.com/t-kristo/linux-pm.git
branch: for-4.12-ti-clkctrl

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Hi,

>From functional code point of view, this is mostly just a rebase of v1 of the
series on top of 4.11-rc1:

https://www.spinics.net/lists/arm-kernel/msg562460.html

This series depends on the TI clock cleanup series I posted last week:

https://www.spinics.net/lists/arm-kernel/msg567920.html

Patch #5 has been changed to accommodate for the existence of multiple
hwmods under single DT node, for example the "ocp" node for omap4
contains 3 hwmods for the different buses; support for this is enabled
by accepting index for the clkctrl clocks also.

Patch #6 is a new one to properly assign the clock for timers. This is
needed as currently timer code only fetches the main clock info from
hwmod itself.

Patches #7, #8 and #9 add the DT data for omap4.

Boot tested on am335x-evm, am335x-evmsk, am47x-evm, am437x-sk, am437x-gp-evm,
  am57xx-evm, omap3-beagle-xm, omap3-beagle, am335x-boneblack, craneboard,
  dra72x-evm, dra7xx-evm, n900, omap5-uevm, omap4-panda-es, omap4-panda,
  omap2430-sdp, omap3430-sdp, omap4430-sdp.

Suspend-resume tested on omap4-panda-es.

Any additional testing on omap4 welcome as this series basically
tweaks every possible peripheral clock on the SoC.

Branch available on top of 4.11-rc1 (+ the cleanup series) here:

tree: https://github.com/t-kristo/linux-pm.git
branch: for-4.12-ti-clkctrl

-Tero

[PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

From: Tony Lindgren <tony@atomide.com>

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti-clkctrl.txt       | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti-clkctrl.txt

diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
new file mode 100644
index 0000000..7e5d9f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
@@ -0,0 +1,56 @@
+Texas Instruments clkctrl clock binding
+
+Texas Instruments SoCs can have a clkctrl clock controller for each
+interconnect target module. The clkctrl clock controller manages functional
+and interface clocks for each module. Each clkctrl controller can also
+gate one or more optional functional clocks for a module, and can have one
+or more clock muxes. There is a clkctrl clock controller typically for each
+interconnect target module on omap4 and later variants.
+
+The clock consumers can specify the index of the clkctrl clock using
+the hardware offset from the clkctrl instance register space. The optional
+clocks can be specified by clkctrl hardware offset and the index of the
+optional clock.
+
+For more information, please see the Linux clock framework binding at
+Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+Required properties :
+- compatible : shall be "ti,clkctrl"
+- #clock-cells : shall contain 2 with the first entry being the instance
+		 offset from the clock domain base and the second being the
+		 clock index
+
+Example: Clock controller node on omap 4430:
+
+&cm2 {
+	l4per: cm@1400 {
+		cm_l4per@0 {
+			cm_l4per_clkctrl: clk@20 {
+				compatible = "ti,clkctrl";
+				reg = <0x20 0x1b0>;
+				#clock-cells = <4>;
+			};
+		};
+	};
+};
+
+Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
+
+#define OMAP4_CLKCTRL_OFFSET		0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define MODULEMODE_HWCTRL		1
+#define MODULEMODE_SWCTRL		2
+
+#define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)
+...
+#define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)
+
+Example: Clock consumer node for GPIO2:
+
+&gpio2 {
+       clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
+		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+};
-- 
1.9.1

[PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

From: Tony Lindgren <tony@atomide.com>

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti-clkctrl.txt       | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti-clkctrl.txt

diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
new file mode 100644
index 0000000..7e5d9f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
@@ -0,0 +1,56 @@
+Texas Instruments clkctrl clock binding
+
+Texas Instruments SoCs can have a clkctrl clock controller for each
+interconnect target module. The clkctrl clock controller manages functional
+and interface clocks for each module. Each clkctrl controller can also
+gate one or more optional functional clocks for a module, and can have one
+or more clock muxes. There is a clkctrl clock controller typically for each
+interconnect target module on omap4 and later variants.
+
+The clock consumers can specify the index of the clkctrl clock using
+the hardware offset from the clkctrl instance register space. The optional
+clocks can be specified by clkctrl hardware offset and the index of the
+optional clock.
+
+For more information, please see the Linux clock framework binding at
+Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+Required properties :
+- compatible : shall be "ti,clkctrl"
+- #clock-cells : shall contain 2 with the first entry being the instance
+		 offset from the clock domain base and the second being the
+		 clock index
+
+Example: Clock controller node on omap 4430:
+
+&cm2 {
+	l4per: cm at 1400 {
+		cm_l4per at 0 {
+			cm_l4per_clkctrl: clk at 20 {
+				compatible = "ti,clkctrl";
+				reg = <0x20 0x1b0>;
+				#clock-cells = <4>;
+			};
+		};
+	};
+};
+
+Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
+
+#define OMAP4_CLKCTRL_OFFSET		0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define MODULEMODE_HWCTRL		1
+#define MODULEMODE_SWCTRL		2
+
+#define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)
+...
+#define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)
+
+Example: Clock consumer node for GPIO2:
+
+&gpio2 {
+       clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
+		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+};
-- 
1.9.1

[PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

From: Tony Lindgren <tony@atomide.com>

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 .../devicetree/bindings/clock/ti-clkctrl.txt       | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti-clkctrl.txt

diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
new file mode 100644
index 0000000..7e5d9f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt
@@ -0,0 +1,56 @@
+Texas Instruments clkctrl clock binding
+
+Texas Instruments SoCs can have a clkctrl clock controller for each
+interconnect target module. The clkctrl clock controller manages functional
+and interface clocks for each module. Each clkctrl controller can also
+gate one or more optional functional clocks for a module, and can have one
+or more clock muxes. There is a clkctrl clock controller typically for each
+interconnect target module on omap4 and later variants.
+
+The clock consumers can specify the index of the clkctrl clock using
+the hardware offset from the clkctrl instance register space. The optional
+clocks can be specified by clkctrl hardware offset and the index of the
+optional clock.
+
+For more information, please see the Linux clock framework binding at
+Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+Required properties :
+- compatible : shall be "ti,clkctrl"
+- #clock-cells : shall contain 2 with the first entry being the instance
+		 offset from the clock domain base and the second being the
+		 clock index
+
+Example: Clock controller node on omap 4430:
+
+&cm2 {
+	l4per: cm@1400 {
+		cm_l4per@0 {
+			cm_l4per_clkctrl: clk@20 {
+				compatible = "ti,clkctrl";
+				reg = <0x20 0x1b0>;
+				#clock-cells = <4>;
+			};
+		};
+	};
+};
+
+Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
+
+#define OMAP4_CLKCTRL_OFFSET		0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define MODULEMODE_HWCTRL		1
+#define MODULEMODE_SWCTRL		2
+
+#define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)
+...
+#define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)
+
+Example: Clock consumer node for GPIO2:
+
+&gpio2 {
+       clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
+		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
+};
-- 
1.9.1

Re: [PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> From: Tony Lindgren <tony@atomide.com>
> +Example: Clock controller node on omap 4430:
> +
> +&cm2 {
> +	l4per: cm@1400 {
> +		cm_l4per@0 {
> +			cm_l4per_clkctrl: clk@20 {
> +				compatible = "ti,clkctrl";
> +				reg = <0x20 0x1b0>;
> +				#clock-cells = <4>;
> +			};
> +		};
> +	};
> +};

The #clock-cells = <4> is a typo left over from earlier revisions,
care to update it to 2 like the binding doc specifies?

Regards,

Tony

[PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> From: Tony Lindgren <tony@atomide.com>
> +Example: Clock controller node on omap 4430:
> +
> +&cm2 {
> +	l4per: cm at 1400 {
> +		cm_l4per at 0 {
> +			cm_l4per_clkctrl: clk at 20 {
> +				compatible = "ti,clkctrl";
> +				reg = <0x20 0x1b0>;
> +				#clock-cells = <4>;
> +			};
> +		};
> +	};
> +};

The #clock-cells = <4> is a typo left over from earlier revisions,
care to update it to 2 like the binding doc specifies?

Regards,

Tony

Re: [PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> From: Tony Lindgren <tony@atomide.com>
> +Example: Clock controller node on omap 4430:
> +
> +&cm2 {
> +	l4per: cm@1400 {
> +		cm_l4per@0 {
> +			cm_l4per_clkctrl: clk@20 {
> +				compatible = "ti,clkctrl";
> +				reg = <0x20 0x1b0>;
> +				#clock-cells = <4>;
> +			};
> +		};
> +	};
> +};

The #clock-cells = <4> is a typo left over from earlier revisions,
care to update it to 2 like the binding doc specifies?

Regards,

Tony

Re: [PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

On 17/03/17 16:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> From: Tony Lindgren <tony@atomide.com>
>> +Example: Clock controller node on omap 4430:
>> +
>> +&cm2 {
>> +	l4per: cm@1400 {
>> +		cm_l4per@0 {
>> +			cm_l4per_clkctrl: clk@20 {
>> +				compatible = "ti,clkctrl";
>> +				reg = <0x20 0x1b0>;
>> +				#clock-cells = <4>;
>> +			};
>> +		};
>> +	};
>> +};
>
> The #clock-cells = <4> is a typo left over from earlier revisions,
> care to update it to 2 like the binding doc specifies?

Ouch, yea I can update that. Will post along with v3 once more comments 
pour in.

-Tero

[PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

On 17/03/17 16:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> From: Tony Lindgren <tony@atomide.com>
>> +Example: Clock controller node on omap 4430:
>> +
>> +&cm2 {
>> +	l4per: cm at 1400 {
>> +		cm_l4per at 0 {
>> +			cm_l4per_clkctrl: clk at 20 {
>> +				compatible = "ti,clkctrl";
>> +				reg = <0x20 0x1b0>;
>> +				#clock-cells = <4>;
>> +			};
>> +		};
>> +	};
>> +};
>
> The #clock-cells = <4> is a typo left over from earlier revisions,
> care to update it to 2 like the binding doc specifies?

Ouch, yea I can update that. Will post along with v3 once more comments 
pour in.

-Tero

Re: [PATCHv2 1/9] Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

[Tero Kristo]

On 17/03/17 16:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> From: Tony Lindgren <tony@atomide.com>
>> +Example: Clock controller node on omap 4430:
>> +
>> +&cm2 {
>> +	l4per: cm@1400 {
>> +		cm_l4per@0 {
>> +			cm_l4per_clkctrl: clk@20 {
>> +				compatible = "ti,clkctrl";
>> +				reg = <0x20 0x1b0>;
>> +				#clock-cells = <4>;
>> +			};
>> +		};
>> +	};
>> +};
>
> The #clock-cells = <4> is a typo left over from earlier revisions,
> care to update it to 2 like the binding doc specifies?

Ouch, yea I can update that. Will post along with v3 once more comments 
pour in.

-Tero

[PATCHv2 2/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/Makefile  |   3 +-
 drivers/clk/ti/clkctrl.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/ti/clock.h   |  31 +++
 3 files changed, 515 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clkctrl.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 0deac98..edb9f47 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,8 @@ ifeq ($(CONFIG_ARCH_OMAP2PLUS), y)
 obj-y					+= clk.o autoidle.o clockdomain.o
 clk-common				= dpll.o composite.o divider.o gate.o \
 					  fixed-factor.o mux.o apll.o \
-					  clkt_dpll.o clkt_iclk.o clkt_dflt.o
+					  clkt_dpll.o clkt_iclk.o clkt_dflt.o \
+					  clkctrl.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o
 obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-814x.o clk-816x.o
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
new file mode 100644
index 0000000..f517ac6
--- /dev/null
+++ b/drivers/clk/ti/clkctrl.c
@@ -0,0 +1,482 @@
+/*
+ * OMAP clkctrl clock support
+ *
+ * Copyright (C) 2017 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+#include "clock.h"
+
+#define NO_IDLEST			0x1
+
+#define OMAP4_MODULEMODE_MASK		0x3
+
+#define MODULEMODE_HWCTRL		0x1
+#define MODULEMODE_SWCTRL		0x2
+
+#define OMAP4_IDLEST_MASK		(0x3 << 16)
+#define OMAP4_IDLEST_SHIFT		16
+
+#define CLKCTRL_IDLEST_FUNCTIONAL	0x0
+#define CLKCTRL_IDLEST_INTERFACE_IDLE	0x2
+#define CLKCTRL_IDLEST_DISABLED		0x3
+
+/* These timeouts are in us */
+#define OMAP4_MAX_MODULE_READY_TIME	2000
+#define OMAP4_MAX_MODULE_DISABLE_TIME	5000
+
+static bool _early_timeout = true;
+
+struct omap_clkctrl_provider {
+	void __iomem *base;
+	struct list_head clocks;
+};
+
+struct omap_clkctrl_clk {
+	struct clk_hw *clk;
+	u16 reg_offset;
+	int bit_offset;
+	struct list_head node;
+};
+
+union omap4_timeout {
+	u32 cycles;
+	ktime_t start;
+};
+
+static u32 _omap4_idlest(u32 val)
+{
+	val &= OMAP4_IDLEST_MASK;
+	val >>= OMAP4_IDLEST_SHIFT;
+
+	return val;
+}
+
+static bool _omap4_is_idle(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_DISABLED;
+}
+
+static bool _omap4_is_ready(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_FUNCTIONAL ||
+	       val == CLKCTRL_IDLEST_INTERFACE_IDLE;
+}
+
+static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
+{
+	if (unlikely(_early_timeout)) {
+		if (time->cycles++ < timeout) {
+			udelay(1);
+			return false;
+		}
+	} else {
+		if (!ktime_to_ns(time->start)) {
+			time->start = ktime_get();
+			return false;
+		}
+
+		if (ktime_us_delta(ktime_get(), time->start) < timeout) {
+			cpu_relax();
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static int __init _omap4_disable_early_timeout(void)
+{
+	_early_timeout = false;
+
+	return 0;
+}
+arch_initcall(_omap4_disable_early_timeout);
+
+static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	int ret;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return 0;
+
+	if (clk->clkdm) {
+		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
+		if (ret) {
+			WARN(1,
+			     "%s: could not enable %s's clockdomain %s: %d\n",
+			     __func__, clk_hw_get_name(hw),
+			     clk->clkdm_name, ret);
+			return ret;
+		}
+	}
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+	val |= clk->enable_bit;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		return 0;
+
+	/* Wait until module is enabled */
+	while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
+			pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
+			return -EBUSY;
+		}
+	}
+
+	return 0;
+}
+
+static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		goto exit;
+
+	/* Wait until module is disabled */
+	while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout,
+				      OMAP4_MAX_MODULE_DISABLE_TIME)) {
+			pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
+			break;
+		}
+	}
+
+exit:
+	if (clk->clkdm)
+		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
+}
+
+static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	if (val & clk->enable_bit)
+		return 1;
+
+	return 0;
+}
+
+static const struct clk_ops omap4_clkctrl_clk_ops = {
+	.enable		= _omap4_clkctrl_clk_enable,
+	.disable	= _omap4_clkctrl_clk_disable,
+	.is_enabled	= _omap4_clkctrl_clk_is_enabled,
+};
+
+static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
+					      void *data)
+{
+	struct omap_clkctrl_provider *provider = data;
+	struct omap_clkctrl_clk *entry;
+
+	if (clkspec->args_count != 2)
+		return ERR_PTR(-EINVAL);
+
+	pr_debug("%s: looking for %x:%x\n", __func__,
+		 clkspec->args[0], clkspec->args[1]);
+
+	list_for_each_entry(entry, &provider->clocks, node) {
+		if (entry->reg_offset == clkspec->args[0] &&
+		    entry->bit_offset == clkspec->args[1])
+			break;
+	}
+
+	if (!entry)
+		return ERR_PTR(-EINVAL);
+
+	return entry->clk;
+}
+
+static int __init
+_ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
+			 struct device_node *node, struct clk_hw *clk_hw,
+			 u16 offset, u8 bit, const char * const *parents,
+			 int num_parents, const struct clk_ops *ops)
+{
+	struct clk_init_data init = { NULL };
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+
+	init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
+			      node->name, offset, bit);
+	clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+	if (!init.name || !clkctrl_clk) {
+		kfree(init.name);
+		return -ENOMEM;
+	}
+
+	clk_hw->init = &init;
+	init.parent_names = parents;
+	init.num_parents = num_parents;
+	init.ops = ops;
+	init.flags = CLK_IS_BASIC;
+
+	clk = ti_clk_register(NULL, clk_hw, init.name);
+
+	if (IS_ERR_OR_NULL(clk))
+		return -EINVAL;
+
+	clkctrl_clk->reg_offset = offset;
+	clkctrl_clk->bit_offset = bit;
+	clkctrl_clk->clk = clk_hw;
+
+	list_add(&clkctrl_clk->node, &provider->clocks);
+
+	return 0;
+}
+
+static void __init
+_ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
+		       struct device_node *node, u16 offset,
+		       const struct omap_clkctrl_bit_data *data,
+		       void __iomem *reg)
+{
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->enable_bit = data->bit;
+	clk_hw->enable_reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
+				     data->bit, data->parents, 1,
+				     &omap_gate_clk_ops))
+		kfree(clk_hw);
+}
+
+static void __init
+_ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_mux *mux;
+	int num_parents = 0;
+	const char * const *pname;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return;
+
+	pname = data->parents;
+	while (*pname) {
+		num_parents++;
+		pname++;
+	}
+
+	mux->mask = num_parents;
+	mux->mask = (1 << fls(mux->mask)) - 1;
+
+	mux->shift = data->bit;
+	mux->reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
+				     data->bit, data->parents, num_parents,
+				     &ti_clk_mux_ops))
+		kfree(mux);
+}
+
+static void __init
+_ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_divider *div;
+	const struct omap_clkctrl_div_data *div_data = data->data;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return;
+
+	div->reg.ptr = reg;
+	div->shift = data->bit;
+
+	if (ti_clk_parse_divider_data((int *)div_data->dividers,
+				      div_data->max_div, 0, 0,
+				      &div->width, &div->table)) {
+		pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
+		       node->name, offset, data->bit);
+		kfree(div);
+		return;
+	}
+
+	if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
+				     data->bit, data->parents, 1,
+				     &ti_clk_divider_ops))
+		kfree(div);
+}
+
+static void __init
+_ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
+			  struct device_node *node,
+			  const struct omap_clkctrl_reg_data *data,
+			  void __iomem *reg)
+{
+	const struct omap_clkctrl_bit_data *bits = data->bit_data;
+
+	if (!bits)
+		return;
+
+	while (bits->bit) {
+		switch (bits->type) {
+		case TI_CLK_GATE:
+			_ti_clkctrl_setup_gate(provider, node, data->offset,
+					       bits, reg);
+			break;
+
+		case TI_CLK_DIVIDER:
+			_ti_clkctrl_setup_div(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		case TI_CLK_MUX:
+			_ti_clkctrl_setup_mux(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		default:
+			pr_err("%s: bad subclk type: %d\n", __func__,
+			       bits->type);
+			return;
+		}
+		bits++;
+	}
+}
+
+static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
+{
+	struct omap_clkctrl_provider *provider;
+	const struct omap_clkctrl_data *data;
+	const struct omap_clkctrl_reg_data *reg_data;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *hw;
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+	const __be32 *addrp;
+	u32 addr;
+
+	addrp = of_get_address(node, 0, NULL, NULL);
+	addr = (u32)of_translate_address(node, addrp);
+
+	if (of_machine_is_compatible("ti,omap4"))
+		data = omap4_clkctrl_data;
+	else
+		return;
+
+	while (data->addr) {
+		if (addr == data->addr)
+			break;
+
+		data++;
+	}
+
+	if (!data->addr) {
+		pr_err("%s not found from clkctrl data.\n", node->name);
+		return;
+	}
+
+	provider = kzalloc(sizeof(*provider), GFP_KERNEL);
+	if (!provider)
+		return;
+
+	provider->base = of_iomap(node, 0);
+
+	INIT_LIST_HEAD(&provider->clocks);
+
+	/* Generate clocks */
+	reg_data = data->regs;
+
+	while (reg_data->parent) {
+		hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+		if (!hw)
+			return;
+
+		hw->enable_reg.ptr = provider->base + reg_data->offset;
+
+		_ti_clkctrl_setup_subclks(provider, node, reg_data,
+					  hw->enable_reg.ptr);
+
+		if (reg_data->flags & CLKF_SW_SUP)
+			hw->enable_bit = MODULEMODE_SWCTRL;
+		if (reg_data->flags & CLKF_HW_SUP)
+			hw->enable_bit = MODULEMODE_HWCTRL;
+		if (reg_data->flags & CLKF_NO_IDLEST)
+			hw->flags |= NO_IDLEST;
+
+		init.parent_names = &reg_data->parent;
+		init.num_parents = 1;
+		init.flags = 0;
+		init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
+				      node->parent->name, node->name,
+				      reg_data->offset, 0);
+		clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+		if (!init.name || !clkctrl_clk) {
+			kfree(init.name);
+			kfree(hw);
+			return;
+		}
+		init.ops = &omap4_clkctrl_clk_ops;
+		hw->hw.init = &init;
+
+		clk = ti_clk_register(NULL, &hw->hw, init.name);
+		if (IS_ERR_OR_NULL(clk))
+			return;
+
+		clkctrl_clk->reg_offset = reg_data->offset;
+		clkctrl_clk->clk = &hw->hw;
+
+		list_add(&clkctrl_clk->node, &provider->clocks);
+
+		reg_data++;
+	}
+
+	of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+}
+CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
+	       _ti_omap4_clkctrl_setup);
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 3f7b265..561dbe9 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -203,6 +203,37 @@ struct ti_dt_clk {
 		.node_name = name,	\
 	}
 
+/* CLKCTRL type definitions */
+struct omap_clkctrl_div_data {
+	const int *dividers;
+	int max_div;
+};
+
+struct omap_clkctrl_bit_data {
+	u8 bit;
+	u8 type;
+	const char * const *parents;
+	const void *data;
+};
+
+struct omap_clkctrl_reg_data {
+	u16 offset;
+	const struct omap_clkctrl_bit_data *bit_data;
+	u16 flags;
+	const char *parent;
+};
+
+struct omap_clkctrl_data {
+	u32 addr;
+	const struct omap_clkctrl_reg_data *regs;
+};
+
+extern const struct omap_clkctrl_data omap4_clkctrl_data[];
+
+#define CLKF_SW_SUP	BIT(0)
+#define CLKF_HW_SUP	BIT(1)
+#define CLKF_NO_IDLEST	BIT(2)
+
 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
 
 struct clk *ti_clk_register_gate(struct ti_clk *setup);
-- 
1.9.1

[PATCHv2 2/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/Makefile  |   3 +-
 drivers/clk/ti/clkctrl.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/ti/clock.h   |  31 +++
 3 files changed, 515 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clkctrl.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 0deac98..edb9f47 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,8 @@ ifeq ($(CONFIG_ARCH_OMAP2PLUS), y)
 obj-y					+= clk.o autoidle.o clockdomain.o
 clk-common				= dpll.o composite.o divider.o gate.o \
 					  fixed-factor.o mux.o apll.o \
-					  clkt_dpll.o clkt_iclk.o clkt_dflt.o
+					  clkt_dpll.o clkt_iclk.o clkt_dflt.o \
+					  clkctrl.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o
 obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-814x.o clk-816x.o
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
new file mode 100644
index 0000000..f517ac6
--- /dev/null
+++ b/drivers/clk/ti/clkctrl.c
@@ -0,0 +1,482 @@
+/*
+ * OMAP clkctrl clock support
+ *
+ * Copyright (C) 2017 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+#include "clock.h"
+
+#define NO_IDLEST			0x1
+
+#define OMAP4_MODULEMODE_MASK		0x3
+
+#define MODULEMODE_HWCTRL		0x1
+#define MODULEMODE_SWCTRL		0x2
+
+#define OMAP4_IDLEST_MASK		(0x3 << 16)
+#define OMAP4_IDLEST_SHIFT		16
+
+#define CLKCTRL_IDLEST_FUNCTIONAL	0x0
+#define CLKCTRL_IDLEST_INTERFACE_IDLE	0x2
+#define CLKCTRL_IDLEST_DISABLED		0x3
+
+/* These timeouts are in us */
+#define OMAP4_MAX_MODULE_READY_TIME	2000
+#define OMAP4_MAX_MODULE_DISABLE_TIME	5000
+
+static bool _early_timeout = true;
+
+struct omap_clkctrl_provider {
+	void __iomem *base;
+	struct list_head clocks;
+};
+
+struct omap_clkctrl_clk {
+	struct clk_hw *clk;
+	u16 reg_offset;
+	int bit_offset;
+	struct list_head node;
+};
+
+union omap4_timeout {
+	u32 cycles;
+	ktime_t start;
+};
+
+static u32 _omap4_idlest(u32 val)
+{
+	val &= OMAP4_IDLEST_MASK;
+	val >>= OMAP4_IDLEST_SHIFT;
+
+	return val;
+}
+
+static bool _omap4_is_idle(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_DISABLED;
+}
+
+static bool _omap4_is_ready(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_FUNCTIONAL ||
+	       val == CLKCTRL_IDLEST_INTERFACE_IDLE;
+}
+
+static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
+{
+	if (unlikely(_early_timeout)) {
+		if (time->cycles++ < timeout) {
+			udelay(1);
+			return false;
+		}
+	} else {
+		if (!ktime_to_ns(time->start)) {
+			time->start = ktime_get();
+			return false;
+		}
+
+		if (ktime_us_delta(ktime_get(), time->start) < timeout) {
+			cpu_relax();
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static int __init _omap4_disable_early_timeout(void)
+{
+	_early_timeout = false;
+
+	return 0;
+}
+arch_initcall(_omap4_disable_early_timeout);
+
+static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	int ret;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return 0;
+
+	if (clk->clkdm) {
+		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
+		if (ret) {
+			WARN(1,
+			     "%s: could not enable %s's clockdomain %s: %d\n",
+			     __func__, clk_hw_get_name(hw),
+			     clk->clkdm_name, ret);
+			return ret;
+		}
+	}
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+	val |= clk->enable_bit;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		return 0;
+
+	/* Wait until module is enabled */
+	while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
+			pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
+			return -EBUSY;
+		}
+	}
+
+	return 0;
+}
+
+static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		goto exit;
+
+	/* Wait until module is disabled */
+	while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout,
+				      OMAP4_MAX_MODULE_DISABLE_TIME)) {
+			pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
+			break;
+		}
+	}
+
+exit:
+	if (clk->clkdm)
+		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
+}
+
+static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	if (val & clk->enable_bit)
+		return 1;
+
+	return 0;
+}
+
+static const struct clk_ops omap4_clkctrl_clk_ops = {
+	.enable		= _omap4_clkctrl_clk_enable,
+	.disable	= _omap4_clkctrl_clk_disable,
+	.is_enabled	= _omap4_clkctrl_clk_is_enabled,
+};
+
+static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
+					      void *data)
+{
+	struct omap_clkctrl_provider *provider = data;
+	struct omap_clkctrl_clk *entry;
+
+	if (clkspec->args_count != 2)
+		return ERR_PTR(-EINVAL);
+
+	pr_debug("%s: looking for %x:%x\n", __func__,
+		 clkspec->args[0], clkspec->args[1]);
+
+	list_for_each_entry(entry, &provider->clocks, node) {
+		if (entry->reg_offset == clkspec->args[0] &&
+		    entry->bit_offset == clkspec->args[1])
+			break;
+	}
+
+	if (!entry)
+		return ERR_PTR(-EINVAL);
+
+	return entry->clk;
+}
+
+static int __init
+_ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
+			 struct device_node *node, struct clk_hw *clk_hw,
+			 u16 offset, u8 bit, const char * const *parents,
+			 int num_parents, const struct clk_ops *ops)
+{
+	struct clk_init_data init = { NULL };
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+
+	init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
+			      node->name, offset, bit);
+	clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+	if (!init.name || !clkctrl_clk) {
+		kfree(init.name);
+		return -ENOMEM;
+	}
+
+	clk_hw->init = &init;
+	init.parent_names = parents;
+	init.num_parents = num_parents;
+	init.ops = ops;
+	init.flags = CLK_IS_BASIC;
+
+	clk = ti_clk_register(NULL, clk_hw, init.name);
+
+	if (IS_ERR_OR_NULL(clk))
+		return -EINVAL;
+
+	clkctrl_clk->reg_offset = offset;
+	clkctrl_clk->bit_offset = bit;
+	clkctrl_clk->clk = clk_hw;
+
+	list_add(&clkctrl_clk->node, &provider->clocks);
+
+	return 0;
+}
+
+static void __init
+_ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
+		       struct device_node *node, u16 offset,
+		       const struct omap_clkctrl_bit_data *data,
+		       void __iomem *reg)
+{
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->enable_bit = data->bit;
+	clk_hw->enable_reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
+				     data->bit, data->parents, 1,
+				     &omap_gate_clk_ops))
+		kfree(clk_hw);
+}
+
+static void __init
+_ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_mux *mux;
+	int num_parents = 0;
+	const char * const *pname;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return;
+
+	pname = data->parents;
+	while (*pname) {
+		num_parents++;
+		pname++;
+	}
+
+	mux->mask = num_parents;
+	mux->mask = (1 << fls(mux->mask)) - 1;
+
+	mux->shift = data->bit;
+	mux->reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
+				     data->bit, data->parents, num_parents,
+				     &ti_clk_mux_ops))
+		kfree(mux);
+}
+
+static void __init
+_ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_divider *div;
+	const struct omap_clkctrl_div_data *div_data = data->data;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return;
+
+	div->reg.ptr = reg;
+	div->shift = data->bit;
+
+	if (ti_clk_parse_divider_data((int *)div_data->dividers,
+				      div_data->max_div, 0, 0,
+				      &div->width, &div->table)) {
+		pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
+		       node->name, offset, data->bit);
+		kfree(div);
+		return;
+	}
+
+	if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
+				     data->bit, data->parents, 1,
+				     &ti_clk_divider_ops))
+		kfree(div);
+}
+
+static void __init
+_ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
+			  struct device_node *node,
+			  const struct omap_clkctrl_reg_data *data,
+			  void __iomem *reg)
+{
+	const struct omap_clkctrl_bit_data *bits = data->bit_data;
+
+	if (!bits)
+		return;
+
+	while (bits->bit) {
+		switch (bits->type) {
+		case TI_CLK_GATE:
+			_ti_clkctrl_setup_gate(provider, node, data->offset,
+					       bits, reg);
+			break;
+
+		case TI_CLK_DIVIDER:
+			_ti_clkctrl_setup_div(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		case TI_CLK_MUX:
+			_ti_clkctrl_setup_mux(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		default:
+			pr_err("%s: bad subclk type: %d\n", __func__,
+			       bits->type);
+			return;
+		}
+		bits++;
+	}
+}
+
+static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
+{
+	struct omap_clkctrl_provider *provider;
+	const struct omap_clkctrl_data *data;
+	const struct omap_clkctrl_reg_data *reg_data;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *hw;
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+	const __be32 *addrp;
+	u32 addr;
+
+	addrp = of_get_address(node, 0, NULL, NULL);
+	addr = (u32)of_translate_address(node, addrp);
+
+	if (of_machine_is_compatible("ti,omap4"))
+		data = omap4_clkctrl_data;
+	else
+		return;
+
+	while (data->addr) {
+		if (addr == data->addr)
+			break;
+
+		data++;
+	}
+
+	if (!data->addr) {
+		pr_err("%s not found from clkctrl data.\n", node->name);
+		return;
+	}
+
+	provider = kzalloc(sizeof(*provider), GFP_KERNEL);
+	if (!provider)
+		return;
+
+	provider->base = of_iomap(node, 0);
+
+	INIT_LIST_HEAD(&provider->clocks);
+
+	/* Generate clocks */
+	reg_data = data->regs;
+
+	while (reg_data->parent) {
+		hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+		if (!hw)
+			return;
+
+		hw->enable_reg.ptr = provider->base + reg_data->offset;
+
+		_ti_clkctrl_setup_subclks(provider, node, reg_data,
+					  hw->enable_reg.ptr);
+
+		if (reg_data->flags & CLKF_SW_SUP)
+			hw->enable_bit = MODULEMODE_SWCTRL;
+		if (reg_data->flags & CLKF_HW_SUP)
+			hw->enable_bit = MODULEMODE_HWCTRL;
+		if (reg_data->flags & CLKF_NO_IDLEST)
+			hw->flags |= NO_IDLEST;
+
+		init.parent_names = &reg_data->parent;
+		init.num_parents = 1;
+		init.flags = 0;
+		init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
+				      node->parent->name, node->name,
+				      reg_data->offset, 0);
+		clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+		if (!init.name || !clkctrl_clk) {
+			kfree(init.name);
+			kfree(hw);
+			return;
+		}
+		init.ops = &omap4_clkctrl_clk_ops;
+		hw->hw.init = &init;
+
+		clk = ti_clk_register(NULL, &hw->hw, init.name);
+		if (IS_ERR_OR_NULL(clk))
+			return;
+
+		clkctrl_clk->reg_offset = reg_data->offset;
+		clkctrl_clk->clk = &hw->hw;
+
+		list_add(&clkctrl_clk->node, &provider->clocks);
+
+		reg_data++;
+	}
+
+	of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+}
+CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
+	       _ti_omap4_clkctrl_setup);
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 3f7b265..561dbe9 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -203,6 +203,37 @@ struct ti_dt_clk {
 		.node_name = name,	\
 	}
 
+/* CLKCTRL type definitions */
+struct omap_clkctrl_div_data {
+	const int *dividers;
+	int max_div;
+};
+
+struct omap_clkctrl_bit_data {
+	u8 bit;
+	u8 type;
+	const char * const *parents;
+	const void *data;
+};
+
+struct omap_clkctrl_reg_data {
+	u16 offset;
+	const struct omap_clkctrl_bit_data *bit_data;
+	u16 flags;
+	const char *parent;
+};
+
+struct omap_clkctrl_data {
+	u32 addr;
+	const struct omap_clkctrl_reg_data *regs;
+};
+
+extern const struct omap_clkctrl_data omap4_clkctrl_data[];
+
+#define CLKF_SW_SUP	BIT(0)
+#define CLKF_HW_SUP	BIT(1)
+#define CLKF_NO_IDLEST	BIT(2)
+
 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
 
 struct clk *ti_clk_register_gate(struct ti_clk *setup);
-- 
1.9.1

[PATCHv2 2/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/Makefile  |   3 +-
 drivers/clk/ti/clkctrl.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/ti/clock.h   |  31 +++
 3 files changed, 515 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/ti/clkctrl.c

diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 0deac98..edb9f47 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,7 +3,8 @@ ifeq ($(CONFIG_ARCH_OMAP2PLUS), y)
 obj-y					+= clk.o autoidle.o clockdomain.o
 clk-common				= dpll.o composite.o divider.o gate.o \
 					  fixed-factor.o mux.o apll.o \
-					  clkt_dpll.o clkt_iclk.o clkt_dflt.o
+					  clkt_dpll.o clkt_iclk.o clkt_dflt.o \
+					  clkctrl.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o
 obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-814x.o clk-816x.o
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
new file mode 100644
index 0000000..f517ac6
--- /dev/null
+++ b/drivers/clk/ti/clkctrl.c
@@ -0,0 +1,482 @@
+/*
+ * OMAP clkctrl clock support
+ *
+ * Copyright (C) 2017 Texas Instruments, Inc.
+ *
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk/ti.h>
+#include <linux/delay.h>
+#include "clock.h"
+
+#define NO_IDLEST			0x1
+
+#define OMAP4_MODULEMODE_MASK		0x3
+
+#define MODULEMODE_HWCTRL		0x1
+#define MODULEMODE_SWCTRL		0x2
+
+#define OMAP4_IDLEST_MASK		(0x3 << 16)
+#define OMAP4_IDLEST_SHIFT		16
+
+#define CLKCTRL_IDLEST_FUNCTIONAL	0x0
+#define CLKCTRL_IDLEST_INTERFACE_IDLE	0x2
+#define CLKCTRL_IDLEST_DISABLED		0x3
+
+/* These timeouts are in us */
+#define OMAP4_MAX_MODULE_READY_TIME	2000
+#define OMAP4_MAX_MODULE_DISABLE_TIME	5000
+
+static bool _early_timeout = true;
+
+struct omap_clkctrl_provider {
+	void __iomem *base;
+	struct list_head clocks;
+};
+
+struct omap_clkctrl_clk {
+	struct clk_hw *clk;
+	u16 reg_offset;
+	int bit_offset;
+	struct list_head node;
+};
+
+union omap4_timeout {
+	u32 cycles;
+	ktime_t start;
+};
+
+static u32 _omap4_idlest(u32 val)
+{
+	val &= OMAP4_IDLEST_MASK;
+	val >>= OMAP4_IDLEST_SHIFT;
+
+	return val;
+}
+
+static bool _omap4_is_idle(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_DISABLED;
+}
+
+static bool _omap4_is_ready(u32 val)
+{
+	val = _omap4_idlest(val);
+
+	return val == CLKCTRL_IDLEST_FUNCTIONAL ||
+	       val == CLKCTRL_IDLEST_INTERFACE_IDLE;
+}
+
+static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
+{
+	if (unlikely(_early_timeout)) {
+		if (time->cycles++ < timeout) {
+			udelay(1);
+			return false;
+		}
+	} else {
+		if (!ktime_to_ns(time->start)) {
+			time->start = ktime_get();
+			return false;
+		}
+
+		if (ktime_us_delta(ktime_get(), time->start) < timeout) {
+			cpu_relax();
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static int __init _omap4_disable_early_timeout(void)
+{
+	_early_timeout = false;
+
+	return 0;
+}
+arch_initcall(_omap4_disable_early_timeout);
+
+static int _omap4_clkctrl_clk_enable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	int ret;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return 0;
+
+	if (clk->clkdm) {
+		ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
+		if (ret) {
+			WARN(1,
+			     "%s: could not enable %s's clockdomain %s: %d\n",
+			     __func__, clk_hw_get_name(hw),
+			     clk->clkdm_name, ret);
+			return ret;
+		}
+	}
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+	val |= clk->enable_bit;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		return 0;
+
+	/* Wait until module is enabled */
+	while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) {
+			pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
+			return -EBUSY;
+		}
+	}
+
+	return 0;
+}
+
+static void _omap4_clkctrl_clk_disable(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+	union omap4_timeout timeout = { 0 };
+
+	if (!clk->enable_bit)
+		return;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	val &= ~OMAP4_MODULEMODE_MASK;
+
+	ti_clk_ll_ops->clk_writel(val, &clk->enable_reg);
+
+	if (clk->flags & NO_IDLEST)
+		goto exit;
+
+	/* Wait until module is disabled */
+	while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) {
+		if (_omap4_is_timeout(&timeout,
+				      OMAP4_MAX_MODULE_DISABLE_TIME)) {
+			pr_err("%s: failed to disable\n", clk_hw_get_name(hw));
+			break;
+		}
+	}
+
+exit:
+	if (clk->clkdm)
+		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
+}
+
+static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	u32 val;
+
+	val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
+
+	if (val & clk->enable_bit)
+		return 1;
+
+	return 0;
+}
+
+static const struct clk_ops omap4_clkctrl_clk_ops = {
+	.enable		= _omap4_clkctrl_clk_enable,
+	.disable	= _omap4_clkctrl_clk_disable,
+	.is_enabled	= _omap4_clkctrl_clk_is_enabled,
+};
+
+static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
+					      void *data)
+{
+	struct omap_clkctrl_provider *provider = data;
+	struct omap_clkctrl_clk *entry;
+
+	if (clkspec->args_count != 2)
+		return ERR_PTR(-EINVAL);
+
+	pr_debug("%s: looking for %x:%x\n", __func__,
+		 clkspec->args[0], clkspec->args[1]);
+
+	list_for_each_entry(entry, &provider->clocks, node) {
+		if (entry->reg_offset == clkspec->args[0] &&
+		    entry->bit_offset == clkspec->args[1])
+			break;
+	}
+
+	if (!entry)
+		return ERR_PTR(-EINVAL);
+
+	return entry->clk;
+}
+
+static int __init
+_ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
+			 struct device_node *node, struct clk_hw *clk_hw,
+			 u16 offset, u8 bit, const char * const *parents,
+			 int num_parents, const struct clk_ops *ops)
+{
+	struct clk_init_data init = { NULL };
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+
+	init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d", node->parent->name,
+			      node->name, offset, bit);
+	clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+	if (!init.name || !clkctrl_clk) {
+		kfree(init.name);
+		return -ENOMEM;
+	}
+
+	clk_hw->init = &init;
+	init.parent_names = parents;
+	init.num_parents = num_parents;
+	init.ops = ops;
+	init.flags = CLK_IS_BASIC;
+
+	clk = ti_clk_register(NULL, clk_hw, init.name);
+
+	if (IS_ERR_OR_NULL(clk))
+		return -EINVAL;
+
+	clkctrl_clk->reg_offset = offset;
+	clkctrl_clk->bit_offset = bit;
+	clkctrl_clk->clk = clk_hw;
+
+	list_add(&clkctrl_clk->node, &provider->clocks);
+
+	return 0;
+}
+
+static void __init
+_ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider,
+		       struct device_node *node, u16 offset,
+		       const struct omap_clkctrl_bit_data *data,
+		       void __iomem *reg)
+{
+	struct clk_hw_omap *clk_hw;
+
+	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+	if (!clk_hw)
+		return;
+
+	clk_hw->enable_bit = data->bit;
+	clk_hw->enable_reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset,
+				     data->bit, data->parents, 1,
+				     &omap_gate_clk_ops))
+		kfree(clk_hw);
+}
+
+static void __init
+_ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_mux *mux;
+	int num_parents = 0;
+	const char * const *pname;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		return;
+
+	pname = data->parents;
+	while (*pname) {
+		num_parents++;
+		pname++;
+	}
+
+	mux->mask = num_parents;
+	mux->mask = (1 << fls(mux->mask)) - 1;
+
+	mux->shift = data->bit;
+	mux->reg.ptr = reg;
+
+	if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset,
+				     data->bit, data->parents, num_parents,
+				     &ti_clk_mux_ops))
+		kfree(mux);
+}
+
+static void __init
+_ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
+		      struct device_node *node, u16 offset,
+		      const struct omap_clkctrl_bit_data *data,
+		      void __iomem *reg)
+{
+	struct clk_omap_divider *div;
+	const struct omap_clkctrl_div_data *div_data = data->data;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		return;
+
+	div->reg.ptr = reg;
+	div->shift = data->bit;
+
+	if (ti_clk_parse_divider_data((int *)div_data->dividers,
+				      div_data->max_div, 0, 0,
+				      &div->width, &div->table)) {
+		pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
+		       node->name, offset, data->bit);
+		kfree(div);
+		return;
+	}
+
+	if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset,
+				     data->bit, data->parents, 1,
+				     &ti_clk_divider_ops))
+		kfree(div);
+}
+
+static void __init
+_ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
+			  struct device_node *node,
+			  const struct omap_clkctrl_reg_data *data,
+			  void __iomem *reg)
+{
+	const struct omap_clkctrl_bit_data *bits = data->bit_data;
+
+	if (!bits)
+		return;
+
+	while (bits->bit) {
+		switch (bits->type) {
+		case TI_CLK_GATE:
+			_ti_clkctrl_setup_gate(provider, node, data->offset,
+					       bits, reg);
+			break;
+
+		case TI_CLK_DIVIDER:
+			_ti_clkctrl_setup_div(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		case TI_CLK_MUX:
+			_ti_clkctrl_setup_mux(provider, node, data->offset,
+					      bits, reg);
+			break;
+
+		default:
+			pr_err("%s: bad subclk type: %d\n", __func__,
+			       bits->type);
+			return;
+		}
+		bits++;
+	}
+}
+
+static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
+{
+	struct omap_clkctrl_provider *provider;
+	const struct omap_clkctrl_data *data;
+	const struct omap_clkctrl_reg_data *reg_data;
+	struct clk_init_data init = { NULL };
+	struct clk_hw_omap *hw;
+	struct clk *clk;
+	struct omap_clkctrl_clk *clkctrl_clk;
+	const __be32 *addrp;
+	u32 addr;
+
+	addrp = of_get_address(node, 0, NULL, NULL);
+	addr = (u32)of_translate_address(node, addrp);
+
+	if (of_machine_is_compatible("ti,omap4"))
+		data = omap4_clkctrl_data;
+	else
+		return;
+
+	while (data->addr) {
+		if (addr == data->addr)
+			break;
+
+		data++;
+	}
+
+	if (!data->addr) {
+		pr_err("%s not found from clkctrl data.\n", node->name);
+		return;
+	}
+
+	provider = kzalloc(sizeof(*provider), GFP_KERNEL);
+	if (!provider)
+		return;
+
+	provider->base = of_iomap(node, 0);
+
+	INIT_LIST_HEAD(&provider->clocks);
+
+	/* Generate clocks */
+	reg_data = data->regs;
+
+	while (reg_data->parent) {
+		hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+		if (!hw)
+			return;
+
+		hw->enable_reg.ptr = provider->base + reg_data->offset;
+
+		_ti_clkctrl_setup_subclks(provider, node, reg_data,
+					  hw->enable_reg.ptr);
+
+		if (reg_data->flags & CLKF_SW_SUP)
+			hw->enable_bit = MODULEMODE_SWCTRL;
+		if (reg_data->flags & CLKF_HW_SUP)
+			hw->enable_bit = MODULEMODE_HWCTRL;
+		if (reg_data->flags & CLKF_NO_IDLEST)
+			hw->flags |= NO_IDLEST;
+
+		init.parent_names = &reg_data->parent;
+		init.num_parents = 1;
+		init.flags = 0;
+		init.name = kasprintf(GFP_KERNEL, "%s:%s:%04x:%d",
+				      node->parent->name, node->name,
+				      reg_data->offset, 0);
+		clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL);
+		if (!init.name || !clkctrl_clk) {
+			kfree(init.name);
+			kfree(hw);
+			return;
+		}
+		init.ops = &omap4_clkctrl_clk_ops;
+		hw->hw.init = &init;
+
+		clk = ti_clk_register(NULL, &hw->hw, init.name);
+		if (IS_ERR_OR_NULL(clk))
+			return;
+
+		clkctrl_clk->reg_offset = reg_data->offset;
+		clkctrl_clk->clk = &hw->hw;
+
+		list_add(&clkctrl_clk->node, &provider->clocks);
+
+		reg_data++;
+	}
+
+	of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+}
+CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
+	       _ti_omap4_clkctrl_setup);
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 3f7b265..561dbe9 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -203,6 +203,37 @@ struct ti_dt_clk {
 		.node_name = name,	\
 	}
 
+/* CLKCTRL type definitions */
+struct omap_clkctrl_div_data {
+	const int *dividers;
+	int max_div;
+};
+
+struct omap_clkctrl_bit_data {
+	u8 bit;
+	u8 type;
+	const char * const *parents;
+	const void *data;
+};
+
+struct omap_clkctrl_reg_data {
+	u16 offset;
+	const struct omap_clkctrl_bit_data *bit_data;
+	u16 flags;
+	const char *parent;
+};
+
+struct omap_clkctrl_data {
+	u32 addr;
+	const struct omap_clkctrl_reg_data *regs;
+};
+
+extern const struct omap_clkctrl_data omap4_clkctrl_data[];
+
+#define CLKF_SW_SUP	BIT(0)
+#define CLKF_HW_SUP	BIT(1)
+#define CLKF_NO_IDLEST	BIT(2)
+
 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
 
 struct clk *ti_clk_register_gate(struct ti_clk *setup);
-- 
1.9.1

[PATCHv2 3/9] dt-bindings: clk: add omap4 clkctrl definitions

[Tero Kristo]

Contains offsets for all omap4 clkctrl main and optional clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 include/dt-bindings/clock/omap4.h | 106 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 include/dt-bindings/clock/omap4.h

diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h
new file mode 100644
index 0000000..638b03b
--- /dev/null
+++ b/include/dt-bindings/clock/omap4.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET	0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define OMAP4_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DSP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_ABE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_L3_MAIN_1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_IPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMA_SYSTEM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_C2C_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_CFG_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_L3_MAIN_3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_ISS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_DSS_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_MMC1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_TIMER10_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x160)
+#define OMAP4_L4_WKUP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_DEBUGSS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
-- 
1.9.1

[PATCHv2 3/9] dt-bindings: clk: add omap4 clkctrl definitions

[Tero Kristo]

Contains offsets for all omap4 clkctrl main and optional clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 include/dt-bindings/clock/omap4.h | 106 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 include/dt-bindings/clock/omap4.h

diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h
new file mode 100644
index 0000000..638b03b
--- /dev/null
+++ b/include/dt-bindings/clock/omap4.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET	0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define OMAP4_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DSP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_ABE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_L3_MAIN_1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_IPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMA_SYSTEM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_C2C_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_CFG_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_L3_MAIN_3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_ISS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_DSS_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_MMC1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_TIMER10_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x160)
+#define OMAP4_L4_WKUP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_DEBUGSS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
-- 
1.9.1

[PATCHv2 3/9] dt-bindings: clk: add omap4 clkctrl definitions

[Tero Kristo]

Contains offsets for all omap4 clkctrl main and optional clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 include/dt-bindings/clock/omap4.h | 106 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 include/dt-bindings/clock/omap4.h

diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h
new file mode 100644
index 0000000..638b03b
--- /dev/null
+++ b/include/dt-bindings/clock/omap4.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET	0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+#define OMAP4_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DSP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_ABE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_L3_MAIN_1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_IPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMA_SYSTEM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_DMM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_C2C_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L4_CFG_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_L3_MAIN_3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_ISS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_DSS_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_MMC1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_TIMER10_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x160)
+#define OMAP4_L4_WKUP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_DEBUGSS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
-- 
1.9.1

Re: [PATCHv2 3/9] dt-bindings: clk: add omap4 clkctrl definitions

[Tony Lindgren]

Hi Tero,

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Contains offsets for all omap4 clkctrl main and optional clocks.

Can you please sort these by the clock controller instance and
add comments to this file to make easier to read?

This way it will be easy to see how the clocks are grouped
just by looking at this file :)

> --- /dev/null
> +++ b/include/dt-bindings/clock/omap4.h
...
> +#define OMAP4_CLKCTRL_OFFSET	0x20
> +#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
...

Something like below for example:

/* abe clocks */
#define OMAP4_L4_ABE_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x20)
> +#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
> +#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
> +#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
> +#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
> +#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
> +#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
> +#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
> +#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
> +#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
> +#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
> +#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
> +#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
...

/* l3_2 clocks */
> +#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
> +#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
...

Regards,

Tony

[PATCHv2 3/9] dt-bindings: clk: add omap4 clkctrl definitions

[Tony Lindgren]

Hi Tero,

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Contains offsets for all omap4 clkctrl main and optional clocks.

Can you please sort these by the clock controller instance and
add comments to this file to make easier to read?

This way it will be easy to see how the clocks are grouped
just by looking at this file :)

> --- /dev/null
> +++ b/include/dt-bindings/clock/omap4.h
...
> +#define OMAP4_CLKCTRL_OFFSET	0x20
> +#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
...

Something like below for example:

/* abe clocks */
#define OMAP4_L4_ABE_CLKCTRL    OMAP4_CLKCTRL_INDEX(0x20)
> +#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
> +#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
> +#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
> +#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
> +#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
> +#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
> +#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
> +#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
> +#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
> +#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
> +#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
> +#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
...

/* l3_2 clocks */
> +#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
> +#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
...

Regards,

Tony

[PATCHv2 4/9] clk: ti: omap4: add clkctrl clock data

[Tero Kristo]

Add data for omap4 clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/clk-44xx.c | 663 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 663 insertions(+)

diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 1c8bb83..2005f03 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
+#include <dt-bindings/clock/omap4.h>
 
 #include "clock.h"
 
@@ -33,6 +34,668 @@
  */
 #define OMAP4_DPLL_USB_DEFFREQ				960000000
 
+static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
+	{ OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_aess_fclk_parents[] __initconst = {
+	"abe_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
+	.max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
+	{ 0 },
+};
+
+static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
+	"dmic_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
+	"abe_24m_fclk",
+	"syc_clk_div_ck",
+	"func_24m_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
+	"mcasp_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
+	"mcbsp1_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
+	"mcbsp2_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
+	"mcbsp3_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
+	"abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
+	"func_24m_clk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
+	"syc_clk_div_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
+	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
+	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
+	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
+	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
+	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
+	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
+	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
+	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
+	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
+	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
+	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
+	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
+	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
+	{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
+	{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
+	{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
+	{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_fdif_fck_parents[] __initconst = {
+	"dpll_per_m4x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
+	{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
+	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
+	{ 0 },
+};
+
+static const char * const omap4_dss_dss_clk_parents[] __initconst = {
+	"dpll_per_m5x2_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
+	"func_48mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_dss_sys_clk_parents[] __initconst = {
+	"syc_clk_div_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_tv_clk_parents[] __initconst = {
+	"extalt_clkin_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
+	{ 0 },
+};
+
+static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
+	"dpll_core_m7x2_ck",
+	"dpll_per_m7x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
+	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
+	{ 0 },
+};
+
+static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
+	"func_64m_fclk",
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_hsi_fck_parents[] __initconst = {
+	"dpll_per_m2x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
+	{ 0 },
+};
+
+static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
+	"utmi_p1_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
+	"utmi_p2_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
+	"init_60m_fclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
+	"dpll_usb_m2_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp1_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
+	"otg_60m_gfclk",
+	NULL,
+};
+
+static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
+	"utmi_phy_clkout_ck",
+	"xclk60motg_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
+	"func_48m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
+	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
+	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
+	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
+	{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
+	{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
+	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
+	{ 0 },
+};
+
+static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
+	"sys_clkin_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
+	"mcbsp4_sync_mux_ck",
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
+	"func_96m_fclk",
+	"per_abe_nc_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
+	"func_24mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
+	"per_abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
+	"pad_slimbus_core_clks_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
+	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
+	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
+	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
+	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
+	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
+	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
+	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
+	{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
+	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
+	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
+	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
+	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
+	"sys_clkin_ck",
+	"dpll_core_m6x2_ck",
+	"tie_low_clock_ck",
+	NULL,
+};
+
+static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
+	"pmd_trace_clk_mux_ck",
+	NULL,
+};
+
+static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
+	0,
+	1,
+	2,
+	0,
+	4,
+	-1,
+};
+
+static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
+	.dividers = omap4_trace_clk_div_div_ck_divs,
+};
+
+static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
+	"pmd_stm_clock_mux_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
+	.max_div = 64,
+};
+
+static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
+	{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
+	{ 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
+	{ OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
+	{ 0 },
+};
+
+const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
+	{ 0x4a004320, omap4_mpuss_clkctrl_regs },
+	{ 0x4a004420, omap4_tesla_clkctrl_regs },
+	{ 0x4a004520, omap4_abe_clkctrl_regs },
+	{ 0x4a008620, omap4_l4_ao_clkctrl_regs },
+	{ 0x4a008720, omap4_l3_1_clkctrl_regs },
+	{ 0x4a008820, omap4_l3_2_clkctrl_regs },
+	{ 0x4a008920, omap4_ducati_clkctrl_regs },
+	{ 0x4a008a20, omap4_l3_dma_clkctrl_regs },
+	{ 0x4a008b20, omap4_l3_emif_clkctrl_regs },
+	{ 0x4a008c20, omap4_d2d_clkctrl_regs },
+	{ 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
+	{ 0x4a008e20, omap4_l3_instr_clkctrl_regs },
+	{ 0x4a008f20, omap4_ivahd_clkctrl_regs },
+	{ 0x4a009020, omap4_iss_clkctrl_regs },
+	{ 0x4a009120, omap4_l3_dss_clkctrl_regs },
+	{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
+	{ 0x4a009320, omap4_l3_init_clkctrl_regs },
+	{ 0x4a009420, omap4_l4_per_clkctrl_regs },
+	{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
+	{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
+	{ 0 },
+};
+
 static struct ti_dt_clk omap44xx_clks[] = {
 	DT_CLK("smp_twd", NULL, "mpu_periphclk"),
 	DT_CLK("omapdss_dss", "ick", "dss_fck"),
-- 
1.9.1

[PATCHv2 4/9] clk: ti: omap4: add clkctrl clock data

[Tero Kristo]

Add data for omap4 clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/clk-44xx.c | 663 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 663 insertions(+)

diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 1c8bb83..2005f03 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
+#include <dt-bindings/clock/omap4.h>
 
 #include "clock.h"
 
@@ -33,6 +34,668 @@
  */
 #define OMAP4_DPLL_USB_DEFFREQ				960000000
 
+static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
+	{ OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_aess_fclk_parents[] __initconst = {
+	"abe_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
+	.max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
+	{ 0 },
+};
+
+static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
+	"dmic_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
+	"abe_24m_fclk",
+	"syc_clk_div_ck",
+	"func_24m_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
+	"mcasp_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
+	"mcbsp1_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
+	"mcbsp2_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
+	"mcbsp3_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
+	"abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
+	"func_24m_clk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
+	"syc_clk_div_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
+	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
+	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
+	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
+	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
+	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
+	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
+	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
+	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
+	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
+	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
+	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
+	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
+	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
+	{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
+	{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
+	{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
+	{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_fdif_fck_parents[] __initconst = {
+	"dpll_per_m4x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
+	{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
+	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
+	{ 0 },
+};
+
+static const char * const omap4_dss_dss_clk_parents[] __initconst = {
+	"dpll_per_m5x2_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
+	"func_48mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_dss_sys_clk_parents[] __initconst = {
+	"syc_clk_div_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_tv_clk_parents[] __initconst = {
+	"extalt_clkin_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
+	{ 0 },
+};
+
+static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
+	"dpll_core_m7x2_ck",
+	"dpll_per_m7x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
+	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
+	{ 0 },
+};
+
+static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
+	"func_64m_fclk",
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_hsi_fck_parents[] __initconst = {
+	"dpll_per_m2x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
+	{ 0 },
+};
+
+static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
+	"utmi_p1_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
+	"utmi_p2_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
+	"init_60m_fclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
+	"dpll_usb_m2_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp1_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
+	"otg_60m_gfclk",
+	NULL,
+};
+
+static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
+	"utmi_phy_clkout_ck",
+	"xclk60motg_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
+	"func_48m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
+	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
+	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
+	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
+	{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
+	{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
+	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
+	{ 0 },
+};
+
+static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
+	"sys_clkin_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
+	"mcbsp4_sync_mux_ck",
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
+	"func_96m_fclk",
+	"per_abe_nc_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
+	"func_24mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
+	"per_abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
+	"pad_slimbus_core_clks_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
+	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
+	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
+	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
+	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
+	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
+	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
+	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
+	{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
+	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
+	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
+	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
+	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
+	"sys_clkin_ck",
+	"dpll_core_m6x2_ck",
+	"tie_low_clock_ck",
+	NULL,
+};
+
+static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
+	"pmd_trace_clk_mux_ck",
+	NULL,
+};
+
+static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
+	0,
+	1,
+	2,
+	0,
+	4,
+	-1,
+};
+
+static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
+	.dividers = omap4_trace_clk_div_div_ck_divs,
+};
+
+static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
+	"pmd_stm_clock_mux_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
+	.max_div = 64,
+};
+
+static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
+	{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
+	{ 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
+	{ OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
+	{ 0 },
+};
+
+const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
+	{ 0x4a004320, omap4_mpuss_clkctrl_regs },
+	{ 0x4a004420, omap4_tesla_clkctrl_regs },
+	{ 0x4a004520, omap4_abe_clkctrl_regs },
+	{ 0x4a008620, omap4_l4_ao_clkctrl_regs },
+	{ 0x4a008720, omap4_l3_1_clkctrl_regs },
+	{ 0x4a008820, omap4_l3_2_clkctrl_regs },
+	{ 0x4a008920, omap4_ducati_clkctrl_regs },
+	{ 0x4a008a20, omap4_l3_dma_clkctrl_regs },
+	{ 0x4a008b20, omap4_l3_emif_clkctrl_regs },
+	{ 0x4a008c20, omap4_d2d_clkctrl_regs },
+	{ 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
+	{ 0x4a008e20, omap4_l3_instr_clkctrl_regs },
+	{ 0x4a008f20, omap4_ivahd_clkctrl_regs },
+	{ 0x4a009020, omap4_iss_clkctrl_regs },
+	{ 0x4a009120, omap4_l3_dss_clkctrl_regs },
+	{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
+	{ 0x4a009320, omap4_l3_init_clkctrl_regs },
+	{ 0x4a009420, omap4_l4_per_clkctrl_regs },
+	{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
+	{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
+	{ 0 },
+};
+
 static struct ti_dt_clk omap44xx_clks[] = {
 	DT_CLK("smp_twd", NULL, "mpu_periphclk"),
 	DT_CLK("omapdss_dss", "ick", "dss_fck"),
-- 
1.9.1

[PATCHv2 4/9] clk: ti: omap4: add clkctrl clock data

[Tero Kristo]

Add data for omap4 clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
---
 drivers/clk/ti/clk-44xx.c | 663 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 663 insertions(+)

diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 1c8bb83..2005f03 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk/ti.h>
+#include <dt-bindings/clock/omap4.h>
 
 #include "clock.h"
 
@@ -33,6 +34,668 @@
  */
 #define OMAP4_DPLL_USB_DEFFREQ				960000000
 
+static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
+	{ OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_aess_fclk_parents[] __initconst = {
+	"abe_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
+	.max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
+	{ 0 },
+};
+
+static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
+	"dmic_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
+	"abe_24m_fclk",
+	"syc_clk_div_ck",
+	"func_24m_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
+	"mcasp_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
+	"mcbsp1_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
+	"mcbsp2_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
+	"mcbsp3_sync_mux_ck",
+	"pad_clks_ck",
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
+	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
+	"abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
+	"func_24m_clk",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
+	"slimbus_clk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
+	"syc_clk_div_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
+	{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
+	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
+	{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
+	{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
+	{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
+	{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
+	{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
+	{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
+	{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
+	{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
+	{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
+	{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
+	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
+	{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
+	{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
+	{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
+	{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
+	{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
+	{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
+	{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_fdif_fck_parents[] __initconst = {
+	"dpll_per_m4x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
+	{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
+	{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
+	{ 0 },
+};
+
+static const char * const omap4_dss_dss_clk_parents[] __initconst = {
+	"dpll_per_m5x2_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
+	"func_48mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_dss_sys_clk_parents[] __initconst = {
+	"syc_clk_div_ck",
+	NULL,
+};
+
+static const char * const omap4_dss_tv_clk_parents[] __initconst = {
+	"extalt_clkin_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
+	{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
+	{ 0 },
+};
+
+static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
+	"dpll_core_m7x2_ck",
+	"dpll_per_m7x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
+	{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
+	{ 0 },
+};
+
+static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
+	"func_64m_fclk",
+	"func_96m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_hsi_fck_parents[] __initconst = {
+	"dpll_per_m2x2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
+	.max_div = 4,
+};
+
+static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
+	{ 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
+	{ 0 },
+};
+
+static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
+	"utmi_p1_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
+	"utmi_p2_gfclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
+	"init_60m_fclk",
+	NULL,
+};
+
+static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
+	"dpll_usb_m2_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp1_ck",
+	NULL,
+};
+
+static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
+	"init_60m_fclk",
+	"xclk60mhsp2_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
+	{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
+	"otg_60m_gfclk",
+	NULL,
+};
+
+static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
+	"utmi_phy_clkout_ck",
+	"xclk60motg_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
+	{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
+	"func_48m_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
+	{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
+	{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
+	{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
+	{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
+	{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
+	{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
+	{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
+	{ 0 },
+};
+
+static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
+	"sys_clkin_ck",
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
+	"sys_32k_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
+	"mcbsp4_sync_mux_ck",
+	"pad_clks_ck",
+	NULL,
+};
+
+static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
+	"func_96m_fclk",
+	"per_abe_nc_fclk",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
+	{ 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
+	{ 0 },
+};
+
+static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
+	"func_24mc_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
+	"per_abe_24m_fclk",
+	NULL,
+};
+
+static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
+	"pad_slimbus_core_clks_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
+	{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
+	{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
+	{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
+	{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
+	{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
+	{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
+	{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
+	{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
+	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
+	{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
+	{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
+	{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
+	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
+	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
+	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
+	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
+	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
+	{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
+	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
+	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+	{ 0 },
+};
+
+static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
+	"sys_clkin_ck",
+	"dpll_core_m6x2_ck",
+	"tie_low_clock_ck",
+	NULL,
+};
+
+static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
+	"pmd_trace_clk_mux_ck",
+	NULL,
+};
+
+static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
+	0,
+	1,
+	2,
+	0,
+	4,
+	-1,
+};
+
+static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
+	.dividers = omap4_trace_clk_div_div_ck_divs,
+};
+
+static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
+	"pmd_stm_clock_mux_ck",
+	NULL,
+};
+
+static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
+	.max_div = 64,
+};
+
+static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
+	{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
+	{ 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
+	{ 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
+	{ 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
+	{ OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
+	{ 0 },
+};
+
+const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
+	{ 0x4a004320, omap4_mpuss_clkctrl_regs },
+	{ 0x4a004420, omap4_tesla_clkctrl_regs },
+	{ 0x4a004520, omap4_abe_clkctrl_regs },
+	{ 0x4a008620, omap4_l4_ao_clkctrl_regs },
+	{ 0x4a008720, omap4_l3_1_clkctrl_regs },
+	{ 0x4a008820, omap4_l3_2_clkctrl_regs },
+	{ 0x4a008920, omap4_ducati_clkctrl_regs },
+	{ 0x4a008a20, omap4_l3_dma_clkctrl_regs },
+	{ 0x4a008b20, omap4_l3_emif_clkctrl_regs },
+	{ 0x4a008c20, omap4_d2d_clkctrl_regs },
+	{ 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
+	{ 0x4a008e20, omap4_l3_instr_clkctrl_regs },
+	{ 0x4a008f20, omap4_ivahd_clkctrl_regs },
+	{ 0x4a009020, omap4_iss_clkctrl_regs },
+	{ 0x4a009120, omap4_l3_dss_clkctrl_regs },
+	{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
+	{ 0x4a009320, omap4_l3_init_clkctrl_regs },
+	{ 0x4a009420, omap4_l4_per_clkctrl_regs },
+	{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
+	{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
+	{ 0 },
+};
+
 static struct ti_dt_clk omap44xx_clks[] = {
 	DT_CLK("smp_twd", NULL, "mpu_periphclk"),
 	DT_CLK("omapdss_dss", "ick", "dss_fck"),
-- 
1.9.1

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

Fix the main clock assignment to assign clkctrl clk from DT as the main
clock if available. If main clock is assigned via DT, the direct PRCM
access for module handling is not used on OMAP4+ architectures either,
as it is assumed the main clock will be doing this instead.

This patch also drops the obsolete "_mod_ck" search as the implementation
required for this was not accepted upstream.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c | 57 ++++++++++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 0da4f2e..99783f1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -731,31 +731,48 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 /**
  * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
  * @oh: struct omap_hwmod *
+ * @np: device node mapped to this hwmod
  *
  * Called from _init_clocks().  Populates the @oh _clk (main
  * functional clock pointer) if a clock matching the hwmod name is found,
  * or a main_clk is present.  Returns 0 on success or -EINVAL on error.
  */
-static int _init_main_clk(struct omap_hwmod *oh)
+static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
-	char name[MOD_CLK_MAX_NAME_LEN];
-	struct clk *clk;
-	static const char modck[] = "_mod_ck";
-
-	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
-		pr_warn("%s: warning: cropping name for %s\n", __func__,
-			oh->name);
+	struct clk *clk = NULL;
+	int i;
+	int count;
+	const char *name;
+	char clk_name[strlen("clkctrl-x") + 1];
 
-	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
-	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
+	if (np) {
+		clk = of_clk_get_by_name(np, "clkctrl");
+		if (IS_ERR(clk)) {
+			/* Try matching by hwmod name */
+			count = of_property_count_strings(np, "ti,hwmods");
+			for (i = 0; i < count; i++) {
+				ret = of_property_read_string_index(np,
+								    "ti,hwmods",
+								    i, &name);
+				if (ret)
+					continue;
+				if (!strcmp(name, oh->name)) {
+					sprintf(clk_name, "clkctrl-%d", i);
+					clk = of_clk_get_by_name(np, clk_name);
+				}
+			}
+		}
+		if (!IS_ERR(clk)) {
+			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
+				 __clk_get_name(clk), oh->name);
+			oh->main_clk = __clk_get_name(clk);
+			oh->_clk = clk;
+			soc_ops.disable_direct_prcm(oh);
+		}
+	}
 
-	clk = clk_get(NULL, name);
-	if (!IS_ERR(clk)) {
-		oh->_clk = clk;
-		soc_ops.disable_direct_prcm(oh);
-		oh->main_clk = kstrdup(name, GFP_KERNEL);
-	} else {
+	if (IS_ERR_OR_NULL(clk)) {
 		if (!oh->main_clk)
 			return 0;
 
@@ -1547,13 +1564,13 @@ static int _init_clkdm(struct omap_hwmod *oh)
  * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
  * well the clockdomain.
  * @oh: struct omap_hwmod *
- * @data: not used; pass NULL
+ * @np: device_node mapped to this hwmod
  *
  * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
  * Resolves all clock names embedded in the hwmod.  Returns 0 on
  * success, or a negative error code on failure.
  */
-static int _init_clocks(struct omap_hwmod *oh, void *data)
+static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
 
@@ -1565,7 +1582,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 	if (soc_ops.init_clkdm)
 		ret |= soc_ops.init_clkdm(oh);
 
-	ret |= _init_main_clk(oh);
+	ret |= _init_main_clk(oh, np);
 	ret |= _init_interface_clks(oh);
 	ret |= _init_opt_clks(oh);
 
@@ -2420,7 +2437,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
 		return 0;
 	}
 
-	r = _init_clocks(oh, NULL);
+	r = _init_clocks(oh, np);
 	if (r < 0) {
 		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
 		return -EINVAL;
-- 
1.9.1

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

Fix the main clock assignment to assign clkctrl clk from DT as the main
clock if available. If main clock is assigned via DT, the direct PRCM
access for module handling is not used on OMAP4+ architectures either,
as it is assumed the main clock will be doing this instead.

This patch also drops the obsolete "_mod_ck" search as the implementation
required for this was not accepted upstream.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c | 57 ++++++++++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 0da4f2e..99783f1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -731,31 +731,48 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 /**
  * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
  * @oh: struct omap_hwmod *
+ * @np: device node mapped to this hwmod
  *
  * Called from _init_clocks().  Populates the @oh _clk (main
  * functional clock pointer) if a clock matching the hwmod name is found,
  * or a main_clk is present.  Returns 0 on success or -EINVAL on error.
  */
-static int _init_main_clk(struct omap_hwmod *oh)
+static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
-	char name[MOD_CLK_MAX_NAME_LEN];
-	struct clk *clk;
-	static const char modck[] = "_mod_ck";
-
-	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
-		pr_warn("%s: warning: cropping name for %s\n", __func__,
-			oh->name);
+	struct clk *clk = NULL;
+	int i;
+	int count;
+	const char *name;
+	char clk_name[strlen("clkctrl-x") + 1];
 
-	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
-	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
+	if (np) {
+		clk = of_clk_get_by_name(np, "clkctrl");
+		if (IS_ERR(clk)) {
+			/* Try matching by hwmod name */
+			count = of_property_count_strings(np, "ti,hwmods");
+			for (i = 0; i < count; i++) {
+				ret = of_property_read_string_index(np,
+								    "ti,hwmods",
+								    i, &name);
+				if (ret)
+					continue;
+				if (!strcmp(name, oh->name)) {
+					sprintf(clk_name, "clkctrl-%d", i);
+					clk = of_clk_get_by_name(np, clk_name);
+				}
+			}
+		}
+		if (!IS_ERR(clk)) {
+			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
+				 __clk_get_name(clk), oh->name);
+			oh->main_clk = __clk_get_name(clk);
+			oh->_clk = clk;
+			soc_ops.disable_direct_prcm(oh);
+		}
+	}
 
-	clk = clk_get(NULL, name);
-	if (!IS_ERR(clk)) {
-		oh->_clk = clk;
-		soc_ops.disable_direct_prcm(oh);
-		oh->main_clk = kstrdup(name, GFP_KERNEL);
-	} else {
+	if (IS_ERR_OR_NULL(clk)) {
 		if (!oh->main_clk)
 			return 0;
 
@@ -1547,13 +1564,13 @@ static int _init_clkdm(struct omap_hwmod *oh)
  * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
  * well the clockdomain.
  * @oh: struct omap_hwmod *
- * @data: not used; pass NULL
+ * @np: device_node mapped to this hwmod
  *
  * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
  * Resolves all clock names embedded in the hwmod.  Returns 0 on
  * success, or a negative error code on failure.
  */
-static int _init_clocks(struct omap_hwmod *oh, void *data)
+static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
 
@@ -1565,7 +1582,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 	if (soc_ops.init_clkdm)
 		ret |= soc_ops.init_clkdm(oh);
 
-	ret |= _init_main_clk(oh);
+	ret |= _init_main_clk(oh, np);
 	ret |= _init_interface_clks(oh);
 	ret |= _init_opt_clks(oh);
 
@@ -2420,7 +2437,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
 		return 0;
 	}
 
-	r = _init_clocks(oh, NULL);
+	r = _init_clocks(oh, np);
 	if (r < 0) {
 		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
 		return -EINVAL;
-- 
1.9.1

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

Fix the main clock assignment to assign clkctrl clk from DT as the main
clock if available. If main clock is assigned via DT, the direct PRCM
access for module handling is not used on OMAP4+ architectures either,
as it is assumed the main clock will be doing this instead.

This patch also drops the obsolete "_mod_ck" search as the implementation
required for this was not accepted upstream.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c | 57 ++++++++++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 0da4f2e..99783f1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -731,31 +731,48 @@ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 /**
  * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
  * @oh: struct omap_hwmod *
+ * @np: device node mapped to this hwmod
  *
  * Called from _init_clocks().  Populates the @oh _clk (main
  * functional clock pointer) if a clock matching the hwmod name is found,
  * or a main_clk is present.  Returns 0 on success or -EINVAL on error.
  */
-static int _init_main_clk(struct omap_hwmod *oh)
+static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
-	char name[MOD_CLK_MAX_NAME_LEN];
-	struct clk *clk;
-	static const char modck[] = "_mod_ck";
-
-	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
-		pr_warn("%s: warning: cropping name for %s\n", __func__,
-			oh->name);
+	struct clk *clk = NULL;
+	int i;
+	int count;
+	const char *name;
+	char clk_name[strlen("clkctrl-x") + 1];
 
-	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
-	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
+	if (np) {
+		clk = of_clk_get_by_name(np, "clkctrl");
+		if (IS_ERR(clk)) {
+			/* Try matching by hwmod name */
+			count = of_property_count_strings(np, "ti,hwmods");
+			for (i = 0; i < count; i++) {
+				ret = of_property_read_string_index(np,
+								    "ti,hwmods",
+								    i, &name);
+				if (ret)
+					continue;
+				if (!strcmp(name, oh->name)) {
+					sprintf(clk_name, "clkctrl-%d", i);
+					clk = of_clk_get_by_name(np, clk_name);
+				}
+			}
+		}
+		if (!IS_ERR(clk)) {
+			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
+				 __clk_get_name(clk), oh->name);
+			oh->main_clk = __clk_get_name(clk);
+			oh->_clk = clk;
+			soc_ops.disable_direct_prcm(oh);
+		}
+	}
 
-	clk = clk_get(NULL, name);
-	if (!IS_ERR(clk)) {
-		oh->_clk = clk;
-		soc_ops.disable_direct_prcm(oh);
-		oh->main_clk = kstrdup(name, GFP_KERNEL);
-	} else {
+	if (IS_ERR_OR_NULL(clk)) {
 		if (!oh->main_clk)
 			return 0;
 
@@ -1547,13 +1564,13 @@ static int _init_clkdm(struct omap_hwmod *oh)
  * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
  * well the clockdomain.
  * @oh: struct omap_hwmod *
- * @data: not used; pass NULL
+ * @np: device_node mapped to this hwmod
  *
  * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
  * Resolves all clock names embedded in the hwmod.  Returns 0 on
  * success, or a negative error code on failure.
  */
-static int _init_clocks(struct omap_hwmod *oh, void *data)
+static int _init_clocks(struct omap_hwmod *oh, struct device_node *np)
 {
 	int ret = 0;
 
@@ -1565,7 +1582,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 	if (soc_ops.init_clkdm)
 		ret |= soc_ops.init_clkdm(oh);
 
-	ret |= _init_main_clk(oh);
+	ret |= _init_main_clk(oh, np);
 	ret |= _init_interface_clks(oh);
 	ret |= _init_opt_clks(oh);
 
@@ -2420,7 +2437,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
 		return 0;
 	}
 
-	r = _init_clocks(oh, NULL);
+	r = _init_clocks(oh, np);
 	if (r < 0) {
 		WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
 		return -EINVAL;
-- 
1.9.1

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> -static int _init_main_clk(struct omap_hwmod *oh)
> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>  {
>  	int ret = 0;
> -	char name[MOD_CLK_MAX_NAME_LEN];
> -	struct clk *clk;
> -	static const char modck[] = "_mod_ck";
> -
> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
> -			oh->name);
> +	struct clk *clk = NULL;
> +	int i;
> +	int count;
> +	const char *name;
> +	char clk_name[strlen("clkctrl-x") + 1];
>  
> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
> +	if (np) {
> +		clk = of_clk_get_by_name(np, "clkctrl");
> +		if (IS_ERR(clk)) {
> +			/* Try matching by hwmod name */
> +			count = of_property_count_strings(np, "ti,hwmods");
> +			for (i = 0; i < count; i++) {
> +				ret = of_property_read_string_index(np,
> +								    "ti,hwmods",
> +								    i, &name);
> +				if (ret)
> +					continue;
> +				if (!strcmp(name, oh->name)) {
> +					sprintf(clk_name, "clkctrl-%d", i);
> +					clk = of_clk_get_by_name(np, clk_name);
> +				}
> +			}
> +		}
> +		if (!IS_ERR(clk)) {
> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
> +				 __clk_get_name(clk), oh->name);
> +			oh->main_clk = __clk_get_name(clk);
> +			oh->_clk = clk;
> +			soc_ops.disable_direct_prcm(oh);
> +		}
> +	}

You should bail out and do nothing here if legacy "ti,hwmods" property is
not found. Eventually it will be the interconnect target IP wrapper module
that will manage the clock and populate the rest of the hwmod data
dynamically.

Regards,

Tony

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> -static int _init_main_clk(struct omap_hwmod *oh)
> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>  {
>  	int ret = 0;
> -	char name[MOD_CLK_MAX_NAME_LEN];
> -	struct clk *clk;
> -	static const char modck[] = "_mod_ck";
> -
> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
> -			oh->name);
> +	struct clk *clk = NULL;
> +	int i;
> +	int count;
> +	const char *name;
> +	char clk_name[strlen("clkctrl-x") + 1];
>  
> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
> +	if (np) {
> +		clk = of_clk_get_by_name(np, "clkctrl");
> +		if (IS_ERR(clk)) {
> +			/* Try matching by hwmod name */
> +			count = of_property_count_strings(np, "ti,hwmods");
> +			for (i = 0; i < count; i++) {
> +				ret = of_property_read_string_index(np,
> +								    "ti,hwmods",
> +								    i, &name);
> +				if (ret)
> +					continue;
> +				if (!strcmp(name, oh->name)) {
> +					sprintf(clk_name, "clkctrl-%d", i);
> +					clk = of_clk_get_by_name(np, clk_name);
> +				}
> +			}
> +		}
> +		if (!IS_ERR(clk)) {
> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
> +				 __clk_get_name(clk), oh->name);
> +			oh->main_clk = __clk_get_name(clk);
> +			oh->_clk = clk;
> +			soc_ops.disable_direct_prcm(oh);
> +		}
> +	}

You should bail out and do nothing here if legacy "ti,hwmods" property is
not found. Eventually it will be the interconnect target IP wrapper module
that will manage the clock and populate the rest of the hwmod data
dynamically.

Regards,

Tony

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 17/03/17 17:41, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> -static int _init_main_clk(struct omap_hwmod *oh)
>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>  {
>>  	int ret = 0;
>> -	char name[MOD_CLK_MAX_NAME_LEN];
>> -	struct clk *clk;
>> -	static const char modck[] = "_mod_ck";
>> -
>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>> -			oh->name);
>> +	struct clk *clk = NULL;
>> +	int i;
>> +	int count;
>> +	const char *name;
>> +	char clk_name[strlen("clkctrl-x") + 1];
>>
>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>> +	if (np) {
>> +		clk = of_clk_get_by_name(np, "clkctrl");
>> +		if (IS_ERR(clk)) {
>> +			/* Try matching by hwmod name */
>> +			count = of_property_count_strings(np, "ti,hwmods");
>> +			for (i = 0; i < count; i++) {
>> +				ret = of_property_read_string_index(np,
>> +								    "ti,hwmods",
>> +								    i, &name);
>> +				if (ret)
>> +					continue;
>> +				if (!strcmp(name, oh->name)) {
>> +					sprintf(clk_name, "clkctrl-%d", i);
>> +					clk = of_clk_get_by_name(np, clk_name);
>> +				}
>> +			}
>> +		}
>> +		if (!IS_ERR(clk)) {
>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>> +				 __clk_get_name(clk), oh->name);
>> +			oh->main_clk = __clk_get_name(clk);
>> +			oh->_clk = clk;
>> +			soc_ops.disable_direct_prcm(oh);
>> +		}
>> +	}
>
> You should bail out and do nothing here if legacy "ti,hwmods" property is
> not found. Eventually it will be the interconnect target IP wrapper module
> that will manage the clock and populate the rest of the hwmod data
> dynamically.

This is only for transitional support of hwmod, this patch will not be 
needed for anything later on; or you probably need to do something 
similar within the interconnect driver itself. The code still needs to 
care for the cases where we want to find the main clock based on the 
clock link within hwmod data, so bailing out early will break any boards 
that don't support the new clkctrl clocks yet.

-Tero

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 17/03/17 17:41, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> -static int _init_main_clk(struct omap_hwmod *oh)
>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>  {
>>  	int ret = 0;
>> -	char name[MOD_CLK_MAX_NAME_LEN];
>> -	struct clk *clk;
>> -	static const char modck[] = "_mod_ck";
>> -
>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>> -			oh->name);
>> +	struct clk *clk = NULL;
>> +	int i;
>> +	int count;
>> +	const char *name;
>> +	char clk_name[strlen("clkctrl-x") + 1];
>>
>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>> +	if (np) {
>> +		clk = of_clk_get_by_name(np, "clkctrl");
>> +		if (IS_ERR(clk)) {
>> +			/* Try matching by hwmod name */
>> +			count = of_property_count_strings(np, "ti,hwmods");
>> +			for (i = 0; i < count; i++) {
>> +				ret = of_property_read_string_index(np,
>> +								    "ti,hwmods",
>> +								    i, &name);
>> +				if (ret)
>> +					continue;
>> +				if (!strcmp(name, oh->name)) {
>> +					sprintf(clk_name, "clkctrl-%d", i);
>> +					clk = of_clk_get_by_name(np, clk_name);
>> +				}
>> +			}
>> +		}
>> +		if (!IS_ERR(clk)) {
>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>> +				 __clk_get_name(clk), oh->name);
>> +			oh->main_clk = __clk_get_name(clk);
>> +			oh->_clk = clk;
>> +			soc_ops.disable_direct_prcm(oh);
>> +		}
>> +	}
>
> You should bail out and do nothing here if legacy "ti,hwmods" property is
> not found. Eventually it will be the interconnect target IP wrapper module
> that will manage the clock and populate the rest of the hwmod data
> dynamically.

This is only for transitional support of hwmod, this patch will not be 
needed for anything later on; or you probably need to do something 
similar within the interconnect driver itself. The code still needs to 
care for the cases where we want to find the main clock based on the 
clock link within hwmod data, so bailing out early will break any boards 
that don't support the new clkctrl clocks yet.

-Tero

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 17/03/17 17:41, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> -static int _init_main_clk(struct omap_hwmod *oh)
>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>  {
>>  	int ret = 0;
>> -	char name[MOD_CLK_MAX_NAME_LEN];
>> -	struct clk *clk;
>> -	static const char modck[] = "_mod_ck";
>> -
>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>> -			oh->name);
>> +	struct clk *clk = NULL;
>> +	int i;
>> +	int count;
>> +	const char *name;
>> +	char clk_name[strlen("clkctrl-x") + 1];
>>
>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>> +	if (np) {
>> +		clk = of_clk_get_by_name(np, "clkctrl");
>> +		if (IS_ERR(clk)) {
>> +			/* Try matching by hwmod name */
>> +			count = of_property_count_strings(np, "ti,hwmods");
>> +			for (i = 0; i < count; i++) {
>> +				ret = of_property_read_string_index(np,
>> +								    "ti,hwmods",
>> +								    i, &name);
>> +				if (ret)
>> +					continue;
>> +				if (!strcmp(name, oh->name)) {
>> +					sprintf(clk_name, "clkctrl-%d", i);
>> +					clk = of_clk_get_by_name(np, clk_name);
>> +				}
>> +			}
>> +		}
>> +		if (!IS_ERR(clk)) {
>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>> +				 __clk_get_name(clk), oh->name);
>> +			oh->main_clk = __clk_get_name(clk);
>> +			oh->_clk = clk;
>> +			soc_ops.disable_direct_prcm(oh);
>> +		}
>> +	}
>
> You should bail out and do nothing here if legacy "ti,hwmods" property is
> not found. Eventually it will be the interconnect target IP wrapper module
> that will manage the clock and populate the rest of the hwmod data
> dynamically.

This is only for transitional support of hwmod, this patch will not be 
needed for anything later on; or you probably need to do something 
similar within the interconnect driver itself. The code still needs to 
care for the cases where we want to find the main clock based on the 
clock link within hwmod data, so bailing out early will break any boards 
that don't support the new clkctrl clocks yet.

-Tero

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 14:42]:
> On 17/03/17 17:41, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > -static int _init_main_clk(struct omap_hwmod *oh)
> > > +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
> > >  {
> > >  	int ret = 0;
> > > -	char name[MOD_CLK_MAX_NAME_LEN];
> > > -	struct clk *clk;
> > > -	static const char modck[] = "_mod_ck";
> > > -
> > > -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
> > > -		pr_warn("%s: warning: cropping name for %s\n", __func__,
> > > -			oh->name);
> > > +	struct clk *clk = NULL;
> > > +	int i;
> > > +	int count;
> > > +	const char *name;
> > > +	char clk_name[strlen("clkctrl-x") + 1];
> > > 
> > > -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
> > > -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
> > > +	if (np) {
> > > +		clk = of_clk_get_by_name(np, "clkctrl");
> > > +		if (IS_ERR(clk)) {
> > > +			/* Try matching by hwmod name */
> > > +			count = of_property_count_strings(np, "ti,hwmods");
> > > +			for (i = 0; i < count; i++) {
> > > +				ret = of_property_read_string_index(np,
> > > +								    "ti,hwmods",
> > > +								    i, &name);
> > > +				if (ret)
> > > +					continue;
> > > +				if (!strcmp(name, oh->name)) {
> > > +					sprintf(clk_name, "clkctrl-%d", i);
> > > +					clk = of_clk_get_by_name(np, clk_name);
> > > +				}
> > > +			}
> > > +		}
> > > +		if (!IS_ERR(clk)) {
> > > +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
> > > +				 __clk_get_name(clk), oh->name);
> > > +			oh->main_clk = __clk_get_name(clk);
> > > +			oh->_clk = clk;
> > > +			soc_ops.disable_direct_prcm(oh);
> > > +		}
> > > +	}
> > 
> > You should bail out and do nothing here if legacy "ti,hwmods" property is
> > not found. Eventually it will be the interconnect target IP wrapper module
> > that will manage the clock and populate the rest of the hwmod data
> > dynamically.
> 
> This is only for transitional support of hwmod, this patch will not be
> needed for anything later on; or you probably need to do something similar
> within the interconnect driver itself. The code still needs to care for the
> cases where we want to find the main clock based on the clock link within
> hwmod data, so bailing out early will break any boards that don't support
> the new clkctrl clocks yet.

Well we really don't want hwmod code parsing anything out of the dtb
unless "ti,hwmods" property is set. That makes moving driver like features
to live under drivers much harder.

I don't quite follow you, what breaks if you fall back to the old clock
lookup if no "ti,hwmods" is set?

Regards,

Tony

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 14:42]:
> On 17/03/17 17:41, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > -static int _init_main_clk(struct omap_hwmod *oh)
> > > +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
> > >  {
> > >  	int ret = 0;
> > > -	char name[MOD_CLK_MAX_NAME_LEN];
> > > -	struct clk *clk;
> > > -	static const char modck[] = "_mod_ck";
> > > -
> > > -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
> > > -		pr_warn("%s: warning: cropping name for %s\n", __func__,
> > > -			oh->name);
> > > +	struct clk *clk = NULL;
> > > +	int i;
> > > +	int count;
> > > +	const char *name;
> > > +	char clk_name[strlen("clkctrl-x") + 1];
> > > 
> > > -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
> > > -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
> > > +	if (np) {
> > > +		clk = of_clk_get_by_name(np, "clkctrl");
> > > +		if (IS_ERR(clk)) {
> > > +			/* Try matching by hwmod name */
> > > +			count = of_property_count_strings(np, "ti,hwmods");
> > > +			for (i = 0; i < count; i++) {
> > > +				ret = of_property_read_string_index(np,
> > > +								    "ti,hwmods",
> > > +								    i, &name);
> > > +				if (ret)
> > > +					continue;
> > > +				if (!strcmp(name, oh->name)) {
> > > +					sprintf(clk_name, "clkctrl-%d", i);
> > > +					clk = of_clk_get_by_name(np, clk_name);
> > > +				}
> > > +			}
> > > +		}
> > > +		if (!IS_ERR(clk)) {
> > > +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
> > > +				 __clk_get_name(clk), oh->name);
> > > +			oh->main_clk = __clk_get_name(clk);
> > > +			oh->_clk = clk;
> > > +			soc_ops.disable_direct_prcm(oh);
> > > +		}
> > > +	}
> > 
> > You should bail out and do nothing here if legacy "ti,hwmods" property is
> > not found. Eventually it will be the interconnect target IP wrapper module
> > that will manage the clock and populate the rest of the hwmod data
> > dynamically.
> 
> This is only for transitional support of hwmod, this patch will not be
> needed for anything later on; or you probably need to do something similar
> within the interconnect driver itself. The code still needs to care for the
> cases where we want to find the main clock based on the clock link within
> hwmod data, so bailing out early will break any boards that don't support
> the new clkctrl clocks yet.

Well we really don't want hwmod code parsing anything out of the dtb
unless "ti,hwmods" property is set. That makes moving driver like features
to live under drivers much harder.

I don't quite follow you, what breaks if you fall back to the old clock
lookup if no "ti,hwmods" is set?

Regards,

Tony

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 14:42]:
> On 17/03/17 17:41, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > -static int _init_main_clk(struct omap_hwmod *oh)
> > > +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
> > >  {
> > >  	int ret = 0;
> > > -	char name[MOD_CLK_MAX_NAME_LEN];
> > > -	struct clk *clk;
> > > -	static const char modck[] = "_mod_ck";
> > > -
> > > -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
> > > -		pr_warn("%s: warning: cropping name for %s\n", __func__,
> > > -			oh->name);
> > > +	struct clk *clk = NULL;
> > > +	int i;
> > > +	int count;
> > > +	const char *name;
> > > +	char clk_name[strlen("clkctrl-x") + 1];
> > > 
> > > -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
> > > -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
> > > +	if (np) {
> > > +		clk = of_clk_get_by_name(np, "clkctrl");
> > > +		if (IS_ERR(clk)) {
> > > +			/* Try matching by hwmod name */
> > > +			count = of_property_count_strings(np, "ti,hwmods");
> > > +			for (i = 0; i < count; i++) {
> > > +				ret = of_property_read_string_index(np,
> > > +								    "ti,hwmods",
> > > +								    i, &name);
> > > +				if (ret)
> > > +					continue;
> > > +				if (!strcmp(name, oh->name)) {
> > > +					sprintf(clk_name, "clkctrl-%d", i);
> > > +					clk = of_clk_get_by_name(np, clk_name);
> > > +				}
> > > +			}
> > > +		}
> > > +		if (!IS_ERR(clk)) {
> > > +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
> > > +				 __clk_get_name(clk), oh->name);
> > > +			oh->main_clk = __clk_get_name(clk);
> > > +			oh->_clk = clk;
> > > +			soc_ops.disable_direct_prcm(oh);
> > > +		}
> > > +	}
> > 
> > You should bail out and do nothing here if legacy "ti,hwmods" property is
> > not found. Eventually it will be the interconnect target IP wrapper module
> > that will manage the clock and populate the rest of the hwmod data
> > dynamically.
> 
> This is only for transitional support of hwmod, this patch will not be
> needed for anything later on; or you probably need to do something similar
> within the interconnect driver itself. The code still needs to care for the
> cases where we want to find the main clock based on the clock link within
> hwmod data, so bailing out early will break any boards that don't support
> the new clkctrl clocks yet.

Well we really don't want hwmod code parsing anything out of the dtb
unless "ti,hwmods" property is set. That makes moving driver like features
to live under drivers much harder.

I don't quite follow you, what breaks if you fall back to the old clock
lookup if no "ti,hwmods" is set?

Regards,

Tony

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 18/03/17 00:17, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 14:42]:
>> On 17/03/17 17:41, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> -static int _init_main_clk(struct omap_hwmod *oh)
>>>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>>>  {
>>>>  	int ret = 0;
>>>> -	char name[MOD_CLK_MAX_NAME_LEN];
>>>> -	struct clk *clk;
>>>> -	static const char modck[] = "_mod_ck";
>>>> -
>>>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>>>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>>>> -			oh->name);
>>>> +	struct clk *clk = NULL;
>>>> +	int i;
>>>> +	int count;
>>>> +	const char *name;
>>>> +	char clk_name[strlen("clkctrl-x") + 1];
>>>>
>>>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>>>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>>>> +	if (np) {
>>>> +		clk = of_clk_get_by_name(np, "clkctrl");
>>>> +		if (IS_ERR(clk)) {
>>>> +			/* Try matching by hwmod name */
>>>> +			count = of_property_count_strings(np, "ti,hwmods");
>>>> +			for (i = 0; i < count; i++) {
>>>> +				ret = of_property_read_string_index(np,
>>>> +								    "ti,hwmods",
>>>> +								    i, &name);
>>>> +				if (ret)
>>>> +					continue;
>>>> +				if (!strcmp(name, oh->name)) {
>>>> +					sprintf(clk_name, "clkctrl-%d", i);
>>>> +					clk = of_clk_get_by_name(np, clk_name);
>>>> +				}
>>>> +			}
>>>> +		}
>>>> +		if (!IS_ERR(clk)) {
>>>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>>>> +				 __clk_get_name(clk), oh->name);
>>>> +			oh->main_clk = __clk_get_name(clk);
>>>> +			oh->_clk = clk;
>>>> +			soc_ops.disable_direct_prcm(oh);
>>>> +		}
>>>> +	}
>>>
>>> You should bail out and do nothing here if legacy "ti,hwmods" property is
>>> not found. Eventually it will be the interconnect target IP wrapper module
>>> that will manage the clock and populate the rest of the hwmod data
>>> dynamically.
>>
>> This is only for transitional support of hwmod, this patch will not be
>> needed for anything later on; or you probably need to do something similar
>> within the interconnect driver itself. The code still needs to care for the
>> cases where we want to find the main clock based on the clock link within
>> hwmod data, so bailing out early will break any boards that don't support
>> the new clkctrl clocks yet.
>
> Well we really don't want hwmod code parsing anything out of the dtb
> unless "ti,hwmods" property is set. That makes moving driver like features
> to live under drivers much harder.
>
> I don't quite follow you, what breaks if you fall back to the old clock
> lookup if no "ti,hwmods" is set?

I think I misunderstood your earlier comment. So basically the code 
already bails out early if ti,hwmods is not set. In this case, the 
earlier lookup done by hwmod core sets the node pointer for this code to 
be NULL, and this just parses the existing main_clk info.

-Tero

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 18/03/17 00:17, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 14:42]:
>> On 17/03/17 17:41, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> -static int _init_main_clk(struct omap_hwmod *oh)
>>>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>>>  {
>>>>  	int ret = 0;
>>>> -	char name[MOD_CLK_MAX_NAME_LEN];
>>>> -	struct clk *clk;
>>>> -	static const char modck[] = "_mod_ck";
>>>> -
>>>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>>>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>>>> -			oh->name);
>>>> +	struct clk *clk = NULL;
>>>> +	int i;
>>>> +	int count;
>>>> +	const char *name;
>>>> +	char clk_name[strlen("clkctrl-x") + 1];
>>>>
>>>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>>>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>>>> +	if (np) {
>>>> +		clk = of_clk_get_by_name(np, "clkctrl");
>>>> +		if (IS_ERR(clk)) {
>>>> +			/* Try matching by hwmod name */
>>>> +			count = of_property_count_strings(np, "ti,hwmods");
>>>> +			for (i = 0; i < count; i++) {
>>>> +				ret = of_property_read_string_index(np,
>>>> +								    "ti,hwmods",
>>>> +								    i, &name);
>>>> +				if (ret)
>>>> +					continue;
>>>> +				if (!strcmp(name, oh->name)) {
>>>> +					sprintf(clk_name, "clkctrl-%d", i);
>>>> +					clk = of_clk_get_by_name(np, clk_name);
>>>> +				}
>>>> +			}
>>>> +		}
>>>> +		if (!IS_ERR(clk)) {
>>>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>>>> +				 __clk_get_name(clk), oh->name);
>>>> +			oh->main_clk = __clk_get_name(clk);
>>>> +			oh->_clk = clk;
>>>> +			soc_ops.disable_direct_prcm(oh);
>>>> +		}
>>>> +	}
>>>
>>> You should bail out and do nothing here if legacy "ti,hwmods" property is
>>> not found. Eventually it will be the interconnect target IP wrapper module
>>> that will manage the clock and populate the rest of the hwmod data
>>> dynamically.
>>
>> This is only for transitional support of hwmod, this patch will not be
>> needed for anything later on; or you probably need to do something similar
>> within the interconnect driver itself. The code still needs to care for the
>> cases where we want to find the main clock based on the clock link within
>> hwmod data, so bailing out early will break any boards that don't support
>> the new clkctrl clocks yet.
>
> Well we really don't want hwmod code parsing anything out of the dtb
> unless "ti,hwmods" property is set. That makes moving driver like features
> to live under drivers much harder.
>
> I don't quite follow you, what breaks if you fall back to the old clock
> lookup if no "ti,hwmods" is set?

I think I misunderstood your earlier comment. So basically the code 
already bails out early if ti,hwmods is not set. In this case, the 
earlier lookup done by hwmod core sets the node pointer for this code to 
be NULL, and this just parses the existing main_clk info.

-Tero

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tero Kristo]

On 18/03/17 00:17, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 14:42]:
>> On 17/03/17 17:41, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> -static int _init_main_clk(struct omap_hwmod *oh)
>>>> +static int _init_main_clk(struct omap_hwmod *oh, struct device_node *np)
>>>>  {
>>>>  	int ret = 0;
>>>> -	char name[MOD_CLK_MAX_NAME_LEN];
>>>> -	struct clk *clk;
>>>> -	static const char modck[] = "_mod_ck";
>>>> -
>>>> -	if (strlen(oh->name) >= MOD_CLK_MAX_NAME_LEN - strlen(modck))
>>>> -		pr_warn("%s: warning: cropping name for %s\n", __func__,
>>>> -			oh->name);
>>>> +	struct clk *clk = NULL;
>>>> +	int i;
>>>> +	int count;
>>>> +	const char *name;
>>>> +	char clk_name[strlen("clkctrl-x") + 1];
>>>>
>>>> -	strlcpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - strlen(modck));
>>>> -	strlcat(name, modck, MOD_CLK_MAX_NAME_LEN);
>>>> +	if (np) {
>>>> +		clk = of_clk_get_by_name(np, "clkctrl");
>>>> +		if (IS_ERR(clk)) {
>>>> +			/* Try matching by hwmod name */
>>>> +			count = of_property_count_strings(np, "ti,hwmods");
>>>> +			for (i = 0; i < count; i++) {
>>>> +				ret = of_property_read_string_index(np,
>>>> +								    "ti,hwmods",
>>>> +								    i, &name);
>>>> +				if (ret)
>>>> +					continue;
>>>> +				if (!strcmp(name, oh->name)) {
>>>> +					sprintf(clk_name, "clkctrl-%d", i);
>>>> +					clk = of_clk_get_by_name(np, clk_name);
>>>> +				}
>>>> +			}
>>>> +		}
>>>> +		if (!IS_ERR(clk)) {
>>>> +			pr_debug("%s: mapped main_clk %s for %s\n", __func__,
>>>> +				 __clk_get_name(clk), oh->name);
>>>> +			oh->main_clk = __clk_get_name(clk);
>>>> +			oh->_clk = clk;
>>>> +			soc_ops.disable_direct_prcm(oh);
>>>> +		}
>>>> +	}
>>>
>>> You should bail out and do nothing here if legacy "ti,hwmods" property is
>>> not found. Eventually it will be the interconnect target IP wrapper module
>>> that will manage the clock and populate the rest of the hwmod data
>>> dynamically.
>>
>> This is only for transitional support of hwmod, this patch will not be
>> needed for anything later on; or you probably need to do something similar
>> within the interconnect driver itself. The code still needs to care for the
>> cases where we want to find the main clock based on the clock link within
>> hwmod data, so bailing out early will break any boards that don't support
>> the new clkctrl clocks yet.
>
> Well we really don't want hwmod code parsing anything out of the dtb
> unless "ti,hwmods" property is set. That makes moving driver like features
> to live under drivers much harder.
>
> I don't quite follow you, what breaks if you fall back to the old clock
> lookup if no "ti,hwmods" is set?

I think I misunderstood your earlier comment. So basically the code 
already bails out early if ti,hwmods is not set. In this case, the 
earlier lookup done by hwmod core sets the node pointer for this code to 
be NULL, and this just parses the existing main_clk info.

-Tero

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:25]:
> On 18/03/17 00:17, Tony Lindgren wrote:
> > I don't quite follow you, what breaks if you fall back to the old clock
> > lookup if no "ti,hwmods" is set?
> 
> I think I misunderstood your earlier comment. So basically the code already
> bails out early if ti,hwmods is not set. In this case, the earlier lookup
> done by hwmod core sets the node pointer for this code to be NULL, and this
> just parses the existing main_clk info.

OK thanks for confirming that.

Regards,

Tony

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:25]:
> On 18/03/17 00:17, Tony Lindgren wrote:
> > I don't quite follow you, what breaks if you fall back to the old clock
> > lookup if no "ti,hwmods" is set?
> 
> I think I misunderstood your earlier comment. So basically the code already
> bails out early if ti,hwmods is not set. In this case, the earlier lookup
> done by hwmod core sets the node pointer for this code to be NULL, and this
> just parses the existing main_clk info.

OK thanks for confirming that.

Regards,

Tony

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:25]:
> On 18/03/17 00:17, Tony Lindgren wrote:
> > I don't quite follow you, what breaks if you fall back to the old clock
> > lookup if no "ti,hwmods" is set?
> 
> I think I misunderstood your earlier comment. So basically the code already
> bails out early if ti,hwmods is not set. In this case, the earlier lookup
> done by hwmod core sets the node pointer for this code to be NULL, and this
> just parses the existing main_clk info.

OK thanks for confirming that.

Regards,

Tony

Re: [PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [170320 07:37]:
> * Tero Kristo <t-kristo@ti.com> [170320 06:25]:
> > On 18/03/17 00:17, Tony Lindgren wrote:
> > > I don't quite follow you, what breaks if you fall back to the old clock
> > > lookup if no "ti,hwmods" is set?
> > 
> > I think I misunderstood your earlier comment. So basically the code already
> > bails out early if ti,hwmods is not set. In this case, the earlier lookup
> > done by hwmod core sets the node pointer for this code to be NULL, and this
> > just parses the existing main_clk info.
> 
> OK thanks for confirming that.

And also for this patch:

Acked-by: Tony Lindgren <tony@atomide.com>

[PATCHv2 5/9] ARM: OMAP2+: hwmod: assign main clock from DT if available

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [170320 07:37]:
> * Tero Kristo <t-kristo@ti.com> [170320 06:25]:
> > On 18/03/17 00:17, Tony Lindgren wrote:
> > > I don't quite follow you, what breaks if you fall back to the old clock
> > > lookup if no "ti,hwmods" is set?
> > 
> > I think I misunderstood your earlier comment. So basically the code already
> > bails out early if ti,hwmods is not set. In this case, the earlier lookup
> > done by hwmod core sets the node pointer for this code to be NULL, and this
> > just parses the existing main_clk info.
> 
> OK thanks for confirming that.

And also for this patch:

Acked-by: Tony Lindgren <tony@atomide.com>

[PATCHv2 6/9] ARM: OMAP2+: timer: add support for fetching fck handle from DT

[Tero Kristo]

The mux clock handle shall be provided via "fck" DT handle. This avoids
the need to lookup the main clock via hwmod core, which will not work
with the clkctrl clock support anymore; the main clock is not going to
be a mux.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/timer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 07dd692..af90f95 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -255,6 +255,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
 		timer->io_base = of_iomap(np, 0);
 
+		timer->fclk = of_clk_get_by_name(np, "fck");
+
 		of_node_put(np);
 	} else {
 		if (omap_dm_timer_reserve_systimer(timer->id))
@@ -292,7 +294,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 	omap_hwmod_setup_one(oh_name);
 
 	/* After the dmtimer is using hwmod these clocks won't be needed */
-	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+	if (IS_ERR_OR_NULL(timer->fclk))
+		timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 	if (IS_ERR(timer->fclk))
 		return PTR_ERR(timer->fclk);
 
-- 
1.9.1

[PATCHv2 6/9] ARM: OMAP2+: timer: add support for fetching fck handle from DT

[Tero Kristo]

The mux clock handle shall be provided via "fck" DT handle. This avoids
the need to lookup the main clock via hwmod core, which will not work
with the clkctrl clock support anymore; the main clock is not going to
be a mux.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/timer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 07dd692..af90f95 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -255,6 +255,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
 		timer->io_base = of_iomap(np, 0);
 
+		timer->fclk = of_clk_get_by_name(np, "fck");
+
 		of_node_put(np);
 	} else {
 		if (omap_dm_timer_reserve_systimer(timer->id))
@@ -292,7 +294,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 	omap_hwmod_setup_one(oh_name);
 
 	/* After the dmtimer is using hwmod these clocks won't be needed */
-	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+	if (IS_ERR_OR_NULL(timer->fclk))
+		timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 	if (IS_ERR(timer->fclk))
 		return PTR_ERR(timer->fclk);
 
-- 
1.9.1

[PATCHv2 6/9] ARM: OMAP2+: timer: add support for fetching fck handle from DT

[Tero Kristo]

The mux clock handle shall be provided via "fck" DT handle. This avoids
the need to lookup the main clock via hwmod core, which will not work
with the clkctrl clock support anymore; the main clock is not going to
be a mux.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-omap2/timer.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 07dd692..af90f95 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -255,6 +255,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
 		timer->io_base = of_iomap(np, 0);
 
+		timer->fclk = of_clk_get_by_name(np, "fck");
+
 		of_node_put(np);
 	} else {
 		if (omap_dm_timer_reserve_systimer(timer->id))
@@ -292,7 +294,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 	omap_hwmod_setup_one(oh_name);
 
 	/* After the dmtimer is using hwmod these clocks won't be needed */
-	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
+	if (IS_ERR_OR_NULL(timer->fclk))
+		timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 	if (IS_ERR(timer->fclk))
 		return PTR_ERR(timer->fclk);
 
-- 
1.9.1

Re: [PATCHv2 6/9] ARM: OMAP2+: timer: add support for fetching fck handle from DT

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> The mux clock handle shall be provided via "fck" DT handle. This avoids
> the need to lookup the main clock via hwmod core, which will not work
> with the clkctrl clock support anymore; the main clock is not going to
> be a mux.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

[PATCHv2 6/9] ARM: OMAP2+: timer: add support for fetching fck handle from DT

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> The mux clock handle shall be provided via "fck" DT handle. This avoids
> the need to lookup the main clock via hwmod core, which will not work
> with the clkctrl clock support anymore; the main clock is not going to
> be a mux.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Acked-by: Tony Lindgren <tony@atomide.com>

[PATCHv2 7/9] ARM: dts: omap4: add bus functionality to base PRCM nodes

[Tero Kristo]

Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 578c53f..0cbd6c1 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -132,8 +132,11 @@
 			ranges = <0 0x4a000000 0x1000000>;
 
 			cm1: cm1@4000 {
-				compatible = "ti,omap4-cm1";
+				compatible = "ti,omap4-cm1", "simple-bus";
 				reg = <0x4000 0x2000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4000 0x2000>;
 
 				cm1_clocks: clocks {
 					#address-cells = <1>;
@@ -145,8 +148,11 @@
 			};
 
 			cm2: cm2@8000 {
-				compatible = "ti,omap4-cm2";
+				compatible = "ti,omap4-cm2", "simple-bus";
 				reg = <0x8000 0x3000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x8000 0x3000>;
 
 				cm2_clocks: clocks {
 					#address-cells = <1>;
@@ -229,6 +235,9 @@
 					compatible = "ti,omap4-prm";
 					reg = <0x6000 0x3000>;
 					interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges = <0 0x6000 0x3000>;
 
 					prm_clocks: clocks {
 						#address-cells = <1>;
-- 
1.9.1

[PATCHv2 7/9] ARM: dts: omap4: add bus functionality to base PRCM nodes

[Tero Kristo]

Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 578c53f..0cbd6c1 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -132,8 +132,11 @@
 			ranges = <0 0x4a000000 0x1000000>;
 
 			cm1: cm1 at 4000 {
-				compatible = "ti,omap4-cm1";
+				compatible = "ti,omap4-cm1", "simple-bus";
 				reg = <0x4000 0x2000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4000 0x2000>;
 
 				cm1_clocks: clocks {
 					#address-cells = <1>;
@@ -145,8 +148,11 @@
 			};
 
 			cm2: cm2 at 8000 {
-				compatible = "ti,omap4-cm2";
+				compatible = "ti,omap4-cm2", "simple-bus";
 				reg = <0x8000 0x3000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x8000 0x3000>;
 
 				cm2_clocks: clocks {
 					#address-cells = <1>;
@@ -229,6 +235,9 @@
 					compatible = "ti,omap4-prm";
 					reg = <0x6000 0x3000>;
 					interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges = <0 0x6000 0x3000>;
 
 					prm_clocks: clocks {
 						#address-cells = <1>;
-- 
1.9.1

[PATCHv2 7/9] ARM: dts: omap4: add bus functionality to base PRCM nodes

[Tero Kristo]

Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 578c53f..0cbd6c1 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -132,8 +132,11 @@
 			ranges = <0 0x4a000000 0x1000000>;
 
 			cm1: cm1@4000 {
-				compatible = "ti,omap4-cm1";
+				compatible = "ti,omap4-cm1", "simple-bus";
 				reg = <0x4000 0x2000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4000 0x2000>;
 
 				cm1_clocks: clocks {
 					#address-cells = <1>;
@@ -145,8 +148,11 @@
 			};
 
 			cm2: cm2@8000 {
-				compatible = "ti,omap4-cm2";
+				compatible = "ti,omap4-cm2", "simple-bus";
 				reg = <0x8000 0x3000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x8000 0x3000>;
 
 				cm2_clocks: clocks {
 					#address-cells = <1>;
@@ -229,6 +235,9 @@
 					compatible = "ti,omap4-prm";
 					reg = <0x6000 0x3000>;
 					interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges = <0 0x6000 0x3000>;
 
 					prm_clocks: clocks {
 						#address-cells = <1>;
-- 
1.9.1

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi           |   1 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 289 +++++++++++++++++++++++++++++++++
 2 files changed, 290 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0cbd6c1..3ecf616 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..c7d517c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -622,6 +622,7 @@
 		clock-frequency = <0>;
 	};
 };
+
 &prm_clocks {
 	sys_clkin_ck: sys_clkin_ck@110 {
 		#clock-cells = <0>;
@@ -1641,3 +1642,291 @@
 		reg = <0x0224>;
 	};
 };
+
+&cm1 {
+	mpuss_cm: mpuss_cm@300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x300 0x100>;
+
+		mpuss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	tesla_cm: tesla_cm@400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x400 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x400 0x100>;
+
+		tesla_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	abe_cm: abe_cm@500 {
+		compatible = "ti,omap4-cm";
+		reg = <0x500 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x500 0x100>;
+
+		abe_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x6c>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&cm2 {
+	l4_ao_cm: l4_ao_cm@600 {
+		compatible = "ti,omap4-cm";
+		reg = <0x600 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x600 0x100>;
+
+		l4_ao_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_1_cm: l3_1_cm@700 {
+		compatible = "ti,omap4-cm";
+		reg = <0x700 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x700 0x100>;
+
+		l3_1_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_2_cm: l3_2_cm@800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x800 0x100>;
+
+		l3_2_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ducati_cm: ducati_cm@900 {
+		compatible = "ti,omap4-cm";
+		reg = <0x900 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x900 0x100>;
+
+		ducati_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dma_cm: l3_dma_cm@a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xa00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xa00 0x100>;
+
+		l3_dma_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_emif_cm: l3_emif_cm@b00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xb00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xb00 0x100>;
+
+		l3_emif_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	d2d_cm: d2d_cm@c00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xc00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xc00 0x100>;
+
+		d2d_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_cfg_cm: l4_cfg_cm@d00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xd00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd00 0x100>;
+
+		l4_cfg_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_instr_cm: l3_instr_cm@e00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xe00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xe00 0x100>;
+
+		l3_instr_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x24>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ivahd_cm: ivahd_cm@f00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xf00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xf00 0x100>;
+
+		ivahd_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	iss_cm: iss_cm@1000 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1000 0x100>;
+
+		iss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dss_cm: l3_dss_cm@1100 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1100 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1100 0x100>;
+
+		l3_dss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_gfx_cm: l3_gfx_cm@1200 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1200 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1200 0x100>;
+
+		l3_gfx_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_init_cm: l3_init_cm@1300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1300 0x100>;
+
+		l3_init_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_per_cm: l4_per_cm@1400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1400 0x200>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1400 0x200>;
+
+		l4_per_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x144>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&prm {
+	l4_wkup_cm: l4_wkup_cm@1800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1800 0x100>;
+
+		l4_wkup_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x5c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	emu_sys_cm: emu_sys_cm@1a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1a00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1a00 0x100>;
+
+		emu_sys_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+};
-- 
1.9.1

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi           |   1 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 289 +++++++++++++++++++++++++++++++++
 2 files changed, 290 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0cbd6c1..3ecf616 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..c7d517c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -622,6 +622,7 @@
 		clock-frequency = <0>;
 	};
 };
+
 &prm_clocks {
 	sys_clkin_ck: sys_clkin_ck at 110 {
 		#clock-cells = <0>;
@@ -1641,3 +1642,291 @@
 		reg = <0x0224>;
 	};
 };
+
+&cm1 {
+	mpuss_cm: mpuss_cm at 300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x300 0x100>;
+
+		mpuss_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	tesla_cm: tesla_cm at 400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x400 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x400 0x100>;
+
+		tesla_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	abe_cm: abe_cm at 500 {
+		compatible = "ti,omap4-cm";
+		reg = <0x500 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x500 0x100>;
+
+		abe_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x6c>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&cm2 {
+	l4_ao_cm: l4_ao_cm at 600 {
+		compatible = "ti,omap4-cm";
+		reg = <0x600 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x600 0x100>;
+
+		l4_ao_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_1_cm: l3_1_cm at 700 {
+		compatible = "ti,omap4-cm";
+		reg = <0x700 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x700 0x100>;
+
+		l3_1_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_2_cm: l3_2_cm at 800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x800 0x100>;
+
+		l3_2_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ducati_cm: ducati_cm at 900 {
+		compatible = "ti,omap4-cm";
+		reg = <0x900 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x900 0x100>;
+
+		ducati_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dma_cm: l3_dma_cm at a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xa00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xa00 0x100>;
+
+		l3_dma_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_emif_cm: l3_emif_cm at b00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xb00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xb00 0x100>;
+
+		l3_emif_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	d2d_cm: d2d_cm at c00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xc00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xc00 0x100>;
+
+		d2d_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_cfg_cm: l4_cfg_cm at d00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xd00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd00 0x100>;
+
+		l4_cfg_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_instr_cm: l3_instr_cm at e00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xe00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xe00 0x100>;
+
+		l3_instr_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x24>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ivahd_cm: ivahd_cm at f00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xf00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xf00 0x100>;
+
+		ivahd_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	iss_cm: iss_cm at 1000 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1000 0x100>;
+
+		iss_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dss_cm: l3_dss_cm at 1100 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1100 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1100 0x100>;
+
+		l3_dss_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_gfx_cm: l3_gfx_cm at 1200 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1200 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1200 0x100>;
+
+		l3_gfx_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_init_cm: l3_init_cm at 1300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1300 0x100>;
+
+		l3_init_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_per_cm: l4_per_cm at 1400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1400 0x200>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1400 0x200>;
+
+		l4_per_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x144>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&prm {
+	l4_wkup_cm: l4_wkup_cm at 1800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1800 0x100>;
+
+		l4_wkup_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x5c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	emu_sys_cm: emu_sys_cm at 1a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1a00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1a00 0x100>;
+
+		emu_sys_clkctrl: clk at 20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+};
-- 
1.9.1

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi           |   1 +
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 289 +++++++++++++++++++++++++++++++++
 2 files changed, 290 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0cbd6c1..3ecf616 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
 
 / {
 	compatible = "ti,omap4430", "ti,omap4";
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37..c7d517c 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -622,6 +622,7 @@
 		clock-frequency = <0>;
 	};
 };
+
 &prm_clocks {
 	sys_clkin_ck: sys_clkin_ck@110 {
 		#clock-cells = <0>;
@@ -1641,3 +1642,291 @@
 		reg = <0x0224>;
 	};
 };
+
+&cm1 {
+	mpuss_cm: mpuss_cm@300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x300 0x100>;
+
+		mpuss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	tesla_cm: tesla_cm@400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x400 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x400 0x100>;
+
+		tesla_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	abe_cm: abe_cm@500 {
+		compatible = "ti,omap4-cm";
+		reg = <0x500 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x500 0x100>;
+
+		abe_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x6c>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&cm2 {
+	l4_ao_cm: l4_ao_cm@600 {
+		compatible = "ti,omap4-cm";
+		reg = <0x600 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x600 0x100>;
+
+		l4_ao_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_1_cm: l3_1_cm@700 {
+		compatible = "ti,omap4-cm";
+		reg = <0x700 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x700 0x100>;
+
+		l3_1_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_2_cm: l3_2_cm@800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x800 0x100>;
+
+		l3_2_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ducati_cm: ducati_cm@900 {
+		compatible = "ti,omap4-cm";
+		reg = <0x900 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x900 0x100>;
+
+		ducati_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dma_cm: l3_dma_cm@a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xa00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xa00 0x100>;
+
+		l3_dma_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_emif_cm: l3_emif_cm@b00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xb00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xb00 0x100>;
+
+		l3_emif_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x1c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	d2d_cm: d2d_cm@c00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xc00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xc00 0x100>;
+
+		d2d_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_cfg_cm: l4_cfg_cm@d00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xd00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd00 0x100>;
+
+		l4_cfg_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x14>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_instr_cm: l3_instr_cm@e00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xe00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xe00 0x100>;
+
+		l3_instr_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x24>;
+			#clock-cells = <2>;
+		};
+	};
+
+	ivahd_cm: ivahd_cm@f00 {
+		compatible = "ti,omap4-cm";
+		reg = <0xf00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xf00 0x100>;
+
+		ivahd_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	iss_cm: iss_cm@1000 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1000 0x100>;
+
+		iss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_dss_cm: l3_dss_cm@1100 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1100 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1100 0x100>;
+
+		l3_dss_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_gfx_cm: l3_gfx_cm@1200 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1200 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1200 0x100>;
+
+		l3_gfx_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l3_init_cm: l3_init_cm@1300 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1300 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1300 0x100>;
+
+		l3_init_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0xc4>;
+			#clock-cells = <2>;
+		};
+	};
+
+	l4_per_cm: l4_per_cm@1400 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1400 0x200>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1400 0x200>;
+
+		l4_per_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x144>;
+			#clock-cells = <2>;
+		};
+	};
+
+};
+
+&prm {
+	l4_wkup_cm: l4_wkup_cm@1800 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1800 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1800 0x100>;
+
+		l4_wkup_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x5c>;
+			#clock-cells = <2>;
+		};
+	};
+
+	emu_sys_cm: emu_sys_cm@1a00 {
+		compatible = "ti,omap4-cm";
+		reg = <0x1a00 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x1a00 0x100>;
+
+		emu_sys_clkctrl: clk@20 {
+			compatible = "ti,clkctrl";
+			reg = <0x20 0x4>;
+			#clock-cells = <2>;
+		};
+	};
+};
-- 
1.9.1

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
> replacement for part of the existing clock data and the existing
> clkctrl hooks under hwmod data.

It seems to be actually this patch in the series that breaks booting
if the last patch in this series is not applied.

Regards,

Tony

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
> replacement for part of the existing clock data and the existing
> clkctrl hooks under hwmod data.

It seems to be actually this patch in the series that breaks booting
if the last patch in this series is not applied.

Regards,

Tony

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 17:43, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>> replacement for part of the existing clock data and the existing
>> clkctrl hooks under hwmod data.
>
> It seems to be actually this patch in the series that breaks booting
> if the last patch in this series is not applied.

Yea I guess we need to squash this and patch #9, I'll double check next 
week. Sorry about not catching this one.

-Tero

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 17:43, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>> replacement for part of the existing clock data and the existing
>> clkctrl hooks under hwmod data.
>
> It seems to be actually this patch in the series that breaks booting
> if the last patch in this series is not applied.

Yea I guess we need to squash this and patch #9, I'll double check next 
week. Sorry about not catching this one.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 17:43, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>> replacement for part of the existing clock data and the existing
>> clkctrl hooks under hwmod data.
>
> It seems to be actually this patch in the series that breaks booting
> if the last patch in this series is not applied.

Yea I guess we need to squash this and patch #9, I'll double check next 
week. Sorry about not catching this one.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 23:41, Tero Kristo wrote:
> On 17/03/17 17:43, Tony Lindgren wrote:
>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>> replacement for part of the existing clock data and the existing
>>> clkctrl hooks under hwmod data.
>>
>> It seems to be actually this patch in the series that breaks booting
>> if the last patch in this series is not applied.
>
> Yea I guess we need to squash this and patch #9, I'll double check next
> week. Sorry about not catching this one.

Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, 
is that you get all the clkctrl clocks registered, but as nobody is 
using them, the clock core disables them later on in clk_disable_unused.

-Tero

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 23:41, Tero Kristo wrote:
> On 17/03/17 17:43, Tony Lindgren wrote:
>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>> replacement for part of the existing clock data and the existing
>>> clkctrl hooks under hwmod data.
>>
>> It seems to be actually this patch in the series that breaks booting
>> if the last patch in this series is not applied.
>
> Yea I guess we need to squash this and patch #9, I'll double check next
> week. Sorry about not catching this one.

Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, 
is that you get all the clkctrl clocks registered, but as nobody is 
using them, the clock core disables them later on in clk_disable_unused.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 17/03/17 23:41, Tero Kristo wrote:
> On 17/03/17 17:43, Tony Lindgren wrote:
>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>> replacement for part of the existing clock data and the existing
>>> clkctrl hooks under hwmod data.
>>
>> It seems to be actually this patch in the series that breaks booting
>> if the last patch in this series is not applied.
>
> Yea I guess we need to squash this and patch #9, I'll double check next
> week. Sorry about not catching this one.

Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, 
is that you get all the clkctrl clocks registered, but as nobody is 
using them, the clock core disables them later on in clk_disable_unused.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:27]:
> On 17/03/17 23:41, Tero Kristo wrote:
> > On 17/03/17 17:43, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
> > > > replacement for part of the existing clock data and the existing
> > > > clkctrl hooks under hwmod data.
> > > 
> > > It seems to be actually this patch in the series that breaks booting
> > > if the last patch in this series is not applied.
> > 
> > Yea I guess we need to squash this and patch #9, I'll double check next
> > week. Sorry about not catching this one.
> 
> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
> that you get all the clkctrl clocks registered, but as nobody is using them,
> the clock core disables them later on in clk_disable_unused.

So how hard would it to do a mixed approach where we don't need
to have everything in place in the dts in order to flip a SoC?

This atomic transaction worries me..

Regards,

Tony

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:27]:
> On 17/03/17 23:41, Tero Kristo wrote:
> > On 17/03/17 17:43, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
> > > > replacement for part of the existing clock data and the existing
> > > > clkctrl hooks under hwmod data.
> > > 
> > > It seems to be actually this patch in the series that breaks booting
> > > if the last patch in this series is not applied.
> > 
> > Yea I guess we need to squash this and patch #9, I'll double check next
> > week. Sorry about not catching this one.
> 
> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
> that you get all the clkctrl clocks registered, but as nobody is using them,
> the clock core disables them later on in clk_disable_unused.

So how hard would it to do a mixed approach where we don't need
to have everything in place in the dts in order to flip a SoC?

This atomic transaction worries me..

Regards,

Tony

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 06:27]:
> On 17/03/17 23:41, Tero Kristo wrote:
> > On 17/03/17 17:43, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
> > > > replacement for part of the existing clock data and the existing
> > > > clkctrl hooks under hwmod data.
> > > 
> > > It seems to be actually this patch in the series that breaks booting
> > > if the last patch in this series is not applied.
> > 
> > Yea I guess we need to squash this and patch #9, I'll double check next
> > week. Sorry about not catching this one.
> 
> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
> that you get all the clkctrl clocks registered, but as nobody is using them,
> the clock core disables them later on in clk_disable_unused.

So how hard would it to do a mixed approach where we don't need
to have everything in place in the dts in order to flip a SoC?

This atomic transaction worries me..

Regards,

Tony

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 20/03/17 16:35, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170320 06:27]:
>> On 17/03/17 23:41, Tero Kristo wrote:
>>> On 17/03/17 17:43, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>>>> replacement for part of the existing clock data and the existing
>>>>> clkctrl hooks under hwmod data.
>>>>
>>>> It seems to be actually this patch in the series that breaks booting
>>>> if the last patch in this series is not applied.
>>>
>>> Yea I guess we need to squash this and patch #9, I'll double check next
>>> week. Sorry about not catching this one.
>>
>> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
>> that you get all the clkctrl clocks registered, but as nobody is using them,
>> the clock core disables them later on in clk_disable_unused.
>
> So how hard would it to do a mixed approach where we don't need
> to have everything in place in the dts in order to flip a SoC?
>
> This atomic transaction worries me..

Well, you could do few things.

- You can use clk_ignore_unused cmdline option between patch #8 and #9 
and it should work, but will most likely break PM.
- You can introduce the DTS changes on a clkctrl module basis, e.g. 
introduce the node for l4_per_clkctrl along with the clock node changes 
for the same
- Do some sort of split between DTS / vs. clkctrl data introduction 
within the clock driver, this forces the files to be in sync with each 
other though.
- Try parsing the DTs for matching clock handles while registering DT 
clocks, if not found, toss our a pr_warn and skip registering the clock. 
Will be very ineffective though as one needs to parse the whole DTS to 
find the clock entries. This clock parsing could be dropped later.

-Tero

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 20/03/17 16:35, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170320 06:27]:
>> On 17/03/17 23:41, Tero Kristo wrote:
>>> On 17/03/17 17:43, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>>>> replacement for part of the existing clock data and the existing
>>>>> clkctrl hooks under hwmod data.
>>>>
>>>> It seems to be actually this patch in the series that breaks booting
>>>> if the last patch in this series is not applied.
>>>
>>> Yea I guess we need to squash this and patch #9, I'll double check next
>>> week. Sorry about not catching this one.
>>
>> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
>> that you get all the clkctrl clocks registered, but as nobody is using them,
>> the clock core disables them later on in clk_disable_unused.
>
> So how hard would it to do a mixed approach where we don't need
> to have everything in place in the dts in order to flip a SoC?
>
> This atomic transaction worries me..

Well, you could do few things.

- You can use clk_ignore_unused cmdline option between patch #8 and #9 
and it should work, but will most likely break PM.
- You can introduce the DTS changes on a clkctrl module basis, e.g. 
introduce the node for l4_per_clkctrl along with the clock node changes 
for the same
- Do some sort of split between DTS / vs. clkctrl data introduction 
within the clock driver, this forces the files to be in sync with each 
other though.
- Try parsing the DTs for matching clock handles while registering DT 
clocks, if not found, toss our a pr_warn and skip registering the clock. 
Will be very ineffective though as one needs to parse the whole DTS to 
find the clock entries. This clock parsing could be dropped later.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tero Kristo]

On 20/03/17 16:35, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170320 06:27]:
>> On 17/03/17 23:41, Tero Kristo wrote:
>>> On 17/03/17 17:43, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Add clkctrl nodes for OMAP4 SoC. These are going to be acting as
>>>>> replacement for part of the existing clock data and the existing
>>>>> clkctrl hooks under hwmod data.
>>>>
>>>> It seems to be actually this patch in the series that breaks booting
>>>> if the last patch in this series is not applied.
>>>
>>> Yea I guess we need to squash this and patch #9, I'll double check next
>>> week. Sorry about not catching this one.
>>
>> Yes, patch #8 and #9 must be squashed. What happens with patch #8 alone, is
>> that you get all the clkctrl clocks registered, but as nobody is using them,
>> the clock core disables them later on in clk_disable_unused.
>
> So how hard would it to do a mixed approach where we don't need
> to have everything in place in the dts in order to flip a SoC?
>
> This atomic transaction worries me..

Well, you could do few things.

- You can use clk_ignore_unused cmdline option between patch #8 and #9 
and it should work, but will most likely break PM.
- You can introduce the DTS changes on a clkctrl module basis, e.g. 
introduce the node for l4_per_clkctrl along with the clock node changes 
for the same
- Do some sort of split between DTS / vs. clkctrl data introduction 
within the clock driver, this forces the files to be in sync with each 
other though.
- Try parsing the DTs for matching clock handles while registering DT 
clocks, if not found, toss our a pr_warn and skip registering the clock. 
Will be very ineffective though as one needs to parse the whole DTS to 
find the clock entries. This clock parsing could be dropped later.

-Tero

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 07:54]:
> - You can introduce the DTS changes on a clkctrl module basis, e.g.
> introduce the node for l4_per_clkctrl along with the clock node changes for
> the same

I don't mind introducing them all at once, I'm worried about
reverting in case of trouble. But as long as we can revert things on
a clkctrl module basis in case of trouble, we should be good to go as
far as I'm concerned.

Regards,

Tony

[PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 07:54]:
> - You can introduce the DTS changes on a clkctrl module basis, e.g.
> introduce the node for l4_per_clkctrl along with the clock node changes for
> the same

I don't mind introducing them all at once, I'm worried about
reverting in case of trouble. But as long as we can revert things on
a clkctrl module basis in case of trouble, we should be good to go as
far as I'm concerned.

Regards,

Tony

Re: [PATCHv2 8/9] ARM: dts: omap4: add clkctrl nodes

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170320 07:54]:
> - You can introduce the DTS changes on a clkctrl module basis, e.g.
> introduce the node for l4_per_clkctrl along with the clock node changes for
> the same

I don't mind introducing them all at once, I'm worried about
reverting in case of trouble. But as long as we can revert things on
a clkctrl module basis in case of trouble, we should be good to go as
far as I'm concerned.

Regards,

Tony

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

Convert the drivers to use the new clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 146 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3ecf616..c39304a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -94,16 +94,22 @@
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
 			sram = <&ocmcram>;
+			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dsp {
 			compatible = "ti,omap3-c64";
 			ti,hwmods = "dsp";
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		iva {
 			compatible = "ti,ivahd";
 			ti,hwmods = "iva";
+			clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 	};
 
@@ -125,6 +131,10 @@
 		      <0x45000000 0x1000>;
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
+			 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
+			 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
+		clock-names = "clkctrl-0", "clkctrl-1", "clkctrl-2";
 
 		l4_cfg: l4@4a000000 {
 			compatible = "ti,omap4-l4-cfg", "simple-bus";
@@ -230,6 +240,8 @@
 					compatible = "ti,omap-counter32k";
 					reg = <0x4000 0x20>;
 					ti,hwmods = "counter_32k";
+					clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
+					clock-names = "clkctrl";
 				};
 
 				prm: prm@6000 {
@@ -304,6 +316,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio2: gpio@48055000 {
@@ -315,6 +329,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio3: gpio@48057000 {
@@ -326,6 +342,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio4: gpio@48059000 {
@@ -337,6 +355,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio5: gpio@4805b000 {
@@ -348,6 +368,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio6: gpio@4805d000 {
@@ -359,6 +381,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		elm: elm@48078000 {
@@ -367,6 +391,8 @@
 			interrupts = <4>;
 			ti,hwmods = "elm";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpmc: gpmc@50000000 {
@@ -381,8 +407,9 @@
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
 			ti,no-idle-on-init;
-			clocks = <&l3_div_ck>;
-			clock-names = "fck";
+			clocks = <&l3_div_ck>,
+				 <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			gpio-controller;
@@ -395,6 +422,8 @@
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart2: serial@4806c000 {
@@ -403,6 +432,8 @@
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart3: serial@48020000 {
@@ -411,6 +442,8 @@
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart4: serial@4806e000 {
@@ -419,6 +452,8 @@
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		hwspinlock: spinlock@4a0f6000 {
@@ -426,6 +461,8 @@
 			reg = <0x4a0f6000 0x1000>;
 			ti,hwmods = "spinlock";
 			#hwlock-cells = <1>;
+			clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c1: i2c@48070000 {
@@ -435,6 +472,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c2: i2c@48072000 {
@@ -444,6 +483,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c3: i2c@48060000 {
@@ -453,6 +494,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c4: i2c@48350000 {
@@ -462,6 +505,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
+			clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi1: spi@48098000 {
@@ -482,6 +527,8 @@
 			       <&sdma 42>;
 			dma-names = "tx0", "rx0", "tx1", "rx1",
 				    "tx2", "rx2", "tx3", "rx3";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi2: spi@4809a000 {
@@ -497,6 +544,8 @@
 			       <&sdma 45>,
 			       <&sdma 46>;
 			dma-names = "tx0", "rx0", "tx1", "rx1";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi3: spi@480b8000 {
@@ -509,6 +558,8 @@
 			ti,spi-num-cs = <2>;
 			dmas = <&sdma 15>, <&sdma 16>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi4: spi@480ba000 {
@@ -521,6 +572,8 @@
 			ti,spi-num-cs = <1>;
 			dmas = <&sdma 70>, <&sdma 71>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc1: mmc@4809c000 {
@@ -533,6 +586,8 @@
 			dmas = <&sdma 61>, <&sdma 62>;
 			dma-names = "tx", "rx";
 			pbias-supply = <&pbias_mmc_reg>;
+			clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc2: mmc@480b4000 {
@@ -543,6 +598,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
 			dma-names = "tx", "rx";
+			clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc3: mmc@480ad000 {
@@ -553,6 +610,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc4: mmc@480d1000 {
@@ -563,6 +622,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc5: mmc@480d5000 {
@@ -573,6 +634,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_dsp: mmu@4a066000 {
@@ -581,6 +644,8 @@
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmu_dsp";
 			#iommu-cells = <0>;
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_ipu: mmu@55082000 {
@@ -590,6 +655,8 @@
 			ti,hwmods = "mmu_ipu";
 			#iommu-cells = <0>;
 			ti,iommu-bus-err-back;
+			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		wdt2: wdt@4a314000 {
@@ -597,6 +664,8 @@
 			reg = <0x4a314000 0x80>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
+			clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcpdm: mcpdm@40132000 {
@@ -610,6 +679,8 @@
 			       <&sdma 66>;
 			dma-names = "up_link", "dn_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmic: dmic@4012e000 {
@@ -622,6 +693,8 @@
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp1: mcbsp@40122000 {
@@ -637,6 +710,8 @@
 			       <&sdma 34>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp2: mcbsp@40124000 {
@@ -652,6 +727,8 @@
 			       <&sdma 18>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp3: mcbsp@40126000 {
@@ -667,6 +744,8 @@
 			       <&sdma 20>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp4: mcbsp@48096000 {
@@ -681,6 +760,8 @@
 			       <&sdma 32>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		keypad: keypad@4a31c000 {
@@ -689,6 +770,8 @@
 			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
+			clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmm@4e000000 {
@@ -696,6 +779,8 @@
 			reg = <0x4e000000 0x800>;
 			interrupts = <0 113 0x4>;
 			ti,hwmods = "dmm";
+			clocks = <&l3_emif_clkctrl OMAP4_DMM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif1: emif@4c000000 {
@@ -708,6 +793,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif2: emif@4d000000 {
@@ -720,6 +807,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		ocp2scp@4a0ad000 {
@@ -729,6 +818,8 @@
 			#size-cells = <1>;
 			ranges;
 			ti,hwmods = "ocp2scp_usb_phy";
+			clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			usb2_phy: usb2phy@4a0ad080 {
 				compatible = "ti,omap-usb2";
 				reg = <0x4a0ad080 0x58>;
@@ -747,6 +838,8 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <3>;
 			ti,mbox-num-fifos = <8>;
+			clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			mbox_ipu: mbox_ipu {
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <1 0 0>;
@@ -763,6 +856,8 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
+			clocks = <&dmt1_clk_mux>, <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 		};
 
 		timer2: timer@48032000 {
@@ -770,6 +865,8 @@
 			reg = <0x48032000 0x80>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer3: timer@48034000 {
@@ -777,6 +874,8 @@
 			reg = <0x48034000 0x80>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer4: timer@48036000 {
@@ -784,6 +883,8 @@
 			reg = <0x48036000 0x80>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer5: timer@40138000 {
@@ -793,6 +894,8 @@
 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer6: timer@4013a000 {
@@ -802,6 +905,8 @@
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer7: timer@4013c000 {
@@ -811,6 +916,8 @@
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer8: timer@4013e000 {
@@ -821,6 +928,8 @@
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer9: timer@4803e000 {
@@ -829,6 +938,8 @@
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer10: timer@48086000 {
@@ -837,6 +948,8 @@
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer11: timer@48088000 {
@@ -845,6 +958,8 @@
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhstll: usbhstll@4a062000 {
@@ -852,6 +967,8 @@
 			reg = <0x4a062000 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
+			clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhshost: usbhshost@4a064000 {
@@ -863,10 +980,12 @@
 			ranges;
 			clocks = <&init_60m_fclk>,
 				 <&xclk60mhsp1_ck>,
-				 <&xclk60mhsp2_ck>;
+				 <&xclk60mhsp2_ck>,
+				 <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
 			clock-names = "refclk_60m_int",
 				      "refclk_60m_ext_p1",
-				      "refclk_60m_ext_p2";
+				      "refclk_60m_ext_p2",
+				      "clkctrl";
 
 			usbhsohci: ohci@4a064800 {
 				compatible = "ti,ohci-omap3";
@@ -908,6 +1027,8 @@
 			num-eps = <16>;
 			ram-bits = <12>;
 			ctrl-module = <&omap_control_usbotg>;
+			clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		aes: aes@4b501000 {
@@ -959,8 +1080,9 @@
 			reg = <0x58000000 0x80>;
 			status = "disabled";
 			ti,hwmods = "dss_core";
-			clocks = <&dss_dss_clk>;
-			clock-names = "fck";
+			clocks = <&dss_dss_clk>,
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -970,8 +1092,9 @@
 				reg = <0x58001000 0x1000>;
 				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				ti,hwmods = "dss_dispc";
-				clocks = <&dss_dss_clk>;
-				clock-names = "fck";
+				clocks = <&dss_dss_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			rfbi: encoder@58002000  {
@@ -979,8 +1102,9 @@
 				reg = <0x58002000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_rfbi";
-				clocks = <&dss_dss_clk>, <&l3_div_ck>;
-				clock-names = "fck", "ick";
+				clocks = <&dss_dss_clk>, <&l3_div_ck>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "ick", "clkctrl";
 			};
 
 			venc: encoder@58003000 {
@@ -988,8 +1112,9 @@
 				reg = <0x58003000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_venc";
-				clocks = <&dss_tv_clk>;
-				clock-names = "fck";
+				clocks = <&dss_tv_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			dsi1: encoder@58004000 {
@@ -1001,8 +1126,9 @@
 				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi1";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			dsi2: encoder@58005000 {
@@ -1014,8 +1140,9 @@
 				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi2";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			hdmi: encoder@58006000 {
@@ -1028,8 +1155,9 @@
 				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_hdmi";
-				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 				dmas = <&sdma 76>;
 				dma-names = "audio_tx";
 			};
-- 
1.9.1

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

Convert the drivers to use the new clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 146 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3ecf616..c39304a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -94,16 +94,22 @@
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
 			sram = <&ocmcram>;
+			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dsp {
 			compatible = "ti,omap3-c64";
 			ti,hwmods = "dsp";
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		iva {
 			compatible = "ti,ivahd";
 			ti,hwmods = "iva";
+			clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 	};
 
@@ -125,6 +131,10 @@
 		      <0x45000000 0x1000>;
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
+			 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
+			 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
+		clock-names = "clkctrl-0", "clkctrl-1", "clkctrl-2";
 
 		l4_cfg: l4 at 4a000000 {
 			compatible = "ti,omap4-l4-cfg", "simple-bus";
@@ -230,6 +240,8 @@
 					compatible = "ti,omap-counter32k";
 					reg = <0x4000 0x20>;
 					ti,hwmods = "counter_32k";
+					clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
+					clock-names = "clkctrl";
 				};
 
 				prm: prm at 6000 {
@@ -304,6 +316,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio2: gpio at 48055000 {
@@ -315,6 +329,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio3: gpio at 48057000 {
@@ -326,6 +342,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio4: gpio at 48059000 {
@@ -337,6 +355,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio5: gpio at 4805b000 {
@@ -348,6 +368,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio6: gpio at 4805d000 {
@@ -359,6 +381,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		elm: elm at 48078000 {
@@ -367,6 +391,8 @@
 			interrupts = <4>;
 			ti,hwmods = "elm";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpmc: gpmc at 50000000 {
@@ -381,8 +407,9 @@
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
 			ti,no-idle-on-init;
-			clocks = <&l3_div_ck>;
-			clock-names = "fck";
+			clocks = <&l3_div_ck>,
+				 <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			gpio-controller;
@@ -395,6 +422,8 @@
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart2: serial at 4806c000 {
@@ -403,6 +432,8 @@
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart3: serial at 48020000 {
@@ -411,6 +442,8 @@
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart4: serial at 4806e000 {
@@ -419,6 +452,8 @@
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		hwspinlock: spinlock at 4a0f6000 {
@@ -426,6 +461,8 @@
 			reg = <0x4a0f6000 0x1000>;
 			ti,hwmods = "spinlock";
 			#hwlock-cells = <1>;
+			clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c1: i2c at 48070000 {
@@ -435,6 +472,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c2: i2c at 48072000 {
@@ -444,6 +483,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c3: i2c at 48060000 {
@@ -453,6 +494,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c4: i2c at 48350000 {
@@ -462,6 +505,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
+			clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi1: spi at 48098000 {
@@ -482,6 +527,8 @@
 			       <&sdma 42>;
 			dma-names = "tx0", "rx0", "tx1", "rx1",
 				    "tx2", "rx2", "tx3", "rx3";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi2: spi at 4809a000 {
@@ -497,6 +544,8 @@
 			       <&sdma 45>,
 			       <&sdma 46>;
 			dma-names = "tx0", "rx0", "tx1", "rx1";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi3: spi at 480b8000 {
@@ -509,6 +558,8 @@
 			ti,spi-num-cs = <2>;
 			dmas = <&sdma 15>, <&sdma 16>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi4: spi at 480ba000 {
@@ -521,6 +572,8 @@
 			ti,spi-num-cs = <1>;
 			dmas = <&sdma 70>, <&sdma 71>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc1: mmc at 4809c000 {
@@ -533,6 +586,8 @@
 			dmas = <&sdma 61>, <&sdma 62>;
 			dma-names = "tx", "rx";
 			pbias-supply = <&pbias_mmc_reg>;
+			clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc2: mmc at 480b4000 {
@@ -543,6 +598,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
 			dma-names = "tx", "rx";
+			clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc3: mmc at 480ad000 {
@@ -553,6 +610,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc4: mmc at 480d1000 {
@@ -563,6 +622,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc5: mmc at 480d5000 {
@@ -573,6 +634,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_dsp: mmu at 4a066000 {
@@ -581,6 +644,8 @@
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmu_dsp";
 			#iommu-cells = <0>;
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_ipu: mmu at 55082000 {
@@ -590,6 +655,8 @@
 			ti,hwmods = "mmu_ipu";
 			#iommu-cells = <0>;
 			ti,iommu-bus-err-back;
+			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		wdt2: wdt at 4a314000 {
@@ -597,6 +664,8 @@
 			reg = <0x4a314000 0x80>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
+			clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcpdm: mcpdm at 40132000 {
@@ -610,6 +679,8 @@
 			       <&sdma 66>;
 			dma-names = "up_link", "dn_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmic: dmic at 4012e000 {
@@ -622,6 +693,8 @@
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp1: mcbsp at 40122000 {
@@ -637,6 +710,8 @@
 			       <&sdma 34>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp2: mcbsp at 40124000 {
@@ -652,6 +727,8 @@
 			       <&sdma 18>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp3: mcbsp at 40126000 {
@@ -667,6 +744,8 @@
 			       <&sdma 20>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp4: mcbsp at 48096000 {
@@ -681,6 +760,8 @@
 			       <&sdma 32>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		keypad: keypad at 4a31c000 {
@@ -689,6 +770,8 @@
 			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
+			clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmm at 4e000000 {
@@ -696,6 +779,8 @@
 			reg = <0x4e000000 0x800>;
 			interrupts = <0 113 0x4>;
 			ti,hwmods = "dmm";
+			clocks = <&l3_emif_clkctrl OMAP4_DMM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif1: emif at 4c000000 {
@@ -708,6 +793,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif2: emif at 4d000000 {
@@ -720,6 +807,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		ocp2scp at 4a0ad000 {
@@ -729,6 +818,8 @@
 			#size-cells = <1>;
 			ranges;
 			ti,hwmods = "ocp2scp_usb_phy";
+			clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			usb2_phy: usb2phy at 4a0ad080 {
 				compatible = "ti,omap-usb2";
 				reg = <0x4a0ad080 0x58>;
@@ -747,6 +838,8 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <3>;
 			ti,mbox-num-fifos = <8>;
+			clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			mbox_ipu: mbox_ipu {
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <1 0 0>;
@@ -763,6 +856,8 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
+			clocks = <&dmt1_clk_mux>, <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 		};
 
 		timer2: timer at 48032000 {
@@ -770,6 +865,8 @@
 			reg = <0x48032000 0x80>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer3: timer at 48034000 {
@@ -777,6 +874,8 @@
 			reg = <0x48034000 0x80>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer4: timer at 48036000 {
@@ -784,6 +883,8 @@
 			reg = <0x48036000 0x80>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer5: timer at 40138000 {
@@ -793,6 +894,8 @@
 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer6: timer at 4013a000 {
@@ -802,6 +905,8 @@
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer7: timer at 4013c000 {
@@ -811,6 +916,8 @@
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer8: timer at 4013e000 {
@@ -821,6 +928,8 @@
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer9: timer at 4803e000 {
@@ -829,6 +938,8 @@
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer10: timer at 48086000 {
@@ -837,6 +948,8 @@
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer11: timer at 48088000 {
@@ -845,6 +958,8 @@
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhstll: usbhstll at 4a062000 {
@@ -852,6 +967,8 @@
 			reg = <0x4a062000 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
+			clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhshost: usbhshost at 4a064000 {
@@ -863,10 +980,12 @@
 			ranges;
 			clocks = <&init_60m_fclk>,
 				 <&xclk60mhsp1_ck>,
-				 <&xclk60mhsp2_ck>;
+				 <&xclk60mhsp2_ck>,
+				 <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
 			clock-names = "refclk_60m_int",
 				      "refclk_60m_ext_p1",
-				      "refclk_60m_ext_p2";
+				      "refclk_60m_ext_p2",
+				      "clkctrl";
 
 			usbhsohci: ohci at 4a064800 {
 				compatible = "ti,ohci-omap3";
@@ -908,6 +1027,8 @@
 			num-eps = <16>;
 			ram-bits = <12>;
 			ctrl-module = <&omap_control_usbotg>;
+			clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		aes: aes at 4b501000 {
@@ -959,8 +1080,9 @@
 			reg = <0x58000000 0x80>;
 			status = "disabled";
 			ti,hwmods = "dss_core";
-			clocks = <&dss_dss_clk>;
-			clock-names = "fck";
+			clocks = <&dss_dss_clk>,
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -970,8 +1092,9 @@
 				reg = <0x58001000 0x1000>;
 				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				ti,hwmods = "dss_dispc";
-				clocks = <&dss_dss_clk>;
-				clock-names = "fck";
+				clocks = <&dss_dss_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			rfbi: encoder at 58002000  {
@@ -979,8 +1102,9 @@
 				reg = <0x58002000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_rfbi";
-				clocks = <&dss_dss_clk>, <&l3_div_ck>;
-				clock-names = "fck", "ick";
+				clocks = <&dss_dss_clk>, <&l3_div_ck>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "ick", "clkctrl";
 			};
 
 			venc: encoder at 58003000 {
@@ -988,8 +1112,9 @@
 				reg = <0x58003000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_venc";
-				clocks = <&dss_tv_clk>;
-				clock-names = "fck";
+				clocks = <&dss_tv_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			dsi1: encoder at 58004000 {
@@ -1001,8 +1126,9 @@
 				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi1";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			dsi2: encoder at 58005000 {
@@ -1014,8 +1140,9 @@
 				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi2";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			hdmi: encoder at 58006000 {
@@ -1028,8 +1155,9 @@
 				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_hdmi";
-				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 				dmas = <&sdma 76>;
 				dma-names = "audio_tx";
 			};
-- 
1.9.1

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

Convert the drivers to use the new clkctrl clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 146 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3ecf616..c39304a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -94,16 +94,22 @@
 			compatible = "ti,omap4-mpu";
 			ti,hwmods = "mpu";
 			sram = <&ocmcram>;
+			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dsp {
 			compatible = "ti,omap3-c64";
 			ti,hwmods = "dsp";
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		iva {
 			compatible = "ti,ivahd";
 			ti,hwmods = "iva";
+			clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 	};
 
@@ -125,6 +131,10 @@
 		      <0x45000000 0x1000>;
 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
+			 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
+			 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
+		clock-names = "clkctrl-0", "clkctrl-1", "clkctrl-2";
 
 		l4_cfg: l4@4a000000 {
 			compatible = "ti,omap4-l4-cfg", "simple-bus";
@@ -230,6 +240,8 @@
 					compatible = "ti,omap-counter32k";
 					reg = <0x4000 0x20>;
 					ti,hwmods = "counter_32k";
+					clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
+					clock-names = "clkctrl";
 				};
 
 				prm: prm@6000 {
@@ -304,6 +316,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio2: gpio@48055000 {
@@ -315,6 +329,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio3: gpio@48057000 {
@@ -326,6 +342,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio4: gpio@48059000 {
@@ -337,6 +355,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio5: gpio@4805b000 {
@@ -348,6 +368,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpio6: gpio@4805d000 {
@@ -359,6 +381,8 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		elm: elm@48078000 {
@@ -367,6 +391,8 @@
 			interrupts = <4>;
 			ti,hwmods = "elm";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		gpmc: gpmc@50000000 {
@@ -381,8 +407,9 @@
 			gpmc,num-waitpins = <4>;
 			ti,hwmods = "gpmc";
 			ti,no-idle-on-init;
-			clocks = <&l3_div_ck>;
-			clock-names = "fck";
+			clocks = <&l3_div_ck>,
+				 <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			gpio-controller;
@@ -395,6 +422,8 @@
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart1";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart2: serial@4806c000 {
@@ -403,6 +432,8 @@
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart2";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart3: serial@48020000 {
@@ -411,6 +442,8 @@
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart3";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		uart4: serial@4806e000 {
@@ -419,6 +452,8 @@
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
+			clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		hwspinlock: spinlock@4a0f6000 {
@@ -426,6 +461,8 @@
 			reg = <0x4a0f6000 0x1000>;
 			ti,hwmods = "spinlock";
 			#hwlock-cells = <1>;
+			clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c1: i2c@48070000 {
@@ -435,6 +472,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c1";
+			clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c2: i2c@48072000 {
@@ -444,6 +483,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c2";
+			clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c3: i2c@48060000 {
@@ -453,6 +494,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
+			clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		i2c4: i2c@48350000 {
@@ -462,6 +505,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
+			clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi1: spi@48098000 {
@@ -482,6 +527,8 @@
 			       <&sdma 42>;
 			dma-names = "tx0", "rx0", "tx1", "rx1",
 				    "tx2", "rx2", "tx3", "rx3";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi2: spi@4809a000 {
@@ -497,6 +544,8 @@
 			       <&sdma 45>,
 			       <&sdma 46>;
 			dma-names = "tx0", "rx0", "tx1", "rx1";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi3: spi@480b8000 {
@@ -509,6 +558,8 @@
 			ti,spi-num-cs = <2>;
 			dmas = <&sdma 15>, <&sdma 16>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcspi4: spi@480ba000 {
@@ -521,6 +572,8 @@
 			ti,spi-num-cs = <1>;
 			dmas = <&sdma 70>, <&sdma 71>;
 			dma-names = "tx0", "rx0";
+			clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc1: mmc@4809c000 {
@@ -533,6 +586,8 @@
 			dmas = <&sdma 61>, <&sdma 62>;
 			dma-names = "tx", "rx";
 			pbias-supply = <&pbias_mmc_reg>;
+			clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc2: mmc@480b4000 {
@@ -543,6 +598,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 47>, <&sdma 48>;
 			dma-names = "tx", "rx";
+			clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc3: mmc@480ad000 {
@@ -553,6 +610,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 77>, <&sdma 78>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc4: mmc@480d1000 {
@@ -563,6 +622,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 57>, <&sdma 58>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmc5: mmc@480d5000 {
@@ -573,6 +634,8 @@
 			ti,needs-special-reset;
 			dmas = <&sdma 59>, <&sdma 60>;
 			dma-names = "tx", "rx";
+			clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_dsp: mmu@4a066000 {
@@ -581,6 +644,8 @@
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "mmu_dsp";
 			#iommu-cells = <0>;
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mmu_ipu: mmu@55082000 {
@@ -590,6 +655,8 @@
 			ti,hwmods = "mmu_ipu";
 			#iommu-cells = <0>;
 			ti,iommu-bus-err-back;
+			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		wdt2: wdt@4a314000 {
@@ -597,6 +664,8 @@
 			reg = <0x4a314000 0x80>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "wd_timer2";
+			clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcpdm: mcpdm@40132000 {
@@ -610,6 +679,8 @@
 			       <&sdma 66>;
 			dma-names = "up_link", "dn_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmic: dmic@4012e000 {
@@ -622,6 +693,8 @@
 			dmas = <&sdma 67>;
 			dma-names = "up_link";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp1: mcbsp@40122000 {
@@ -637,6 +710,8 @@
 			       <&sdma 34>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp2: mcbsp@40124000 {
@@ -652,6 +727,8 @@
 			       <&sdma 18>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp3: mcbsp@40126000 {
@@ -667,6 +744,8 @@
 			       <&sdma 20>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		mcbsp4: mcbsp@48096000 {
@@ -681,6 +760,8 @@
 			       <&sdma 32>;
 			dma-names = "tx", "rx";
 			status = "disabled";
+			clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		keypad: keypad@4a31c000 {
@@ -689,6 +770,8 @@
 			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			reg-names = "mpu";
 			ti,hwmods = "kbd";
+			clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		dmm@4e000000 {
@@ -696,6 +779,8 @@
 			reg = <0x4e000000 0x800>;
 			interrupts = <0 113 0x4>;
 			ti,hwmods = "dmm";
+			clocks = <&l3_emif_clkctrl OMAP4_DMM_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif1: emif@4c000000 {
@@ -708,6 +793,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		emif2: emif@4d000000 {
@@ -720,6 +807,8 @@
 			hw-caps-read-idle-ctrl;
 			hw-caps-ll-interface;
 			hw-caps-temp-alert;
+			clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		ocp2scp@4a0ad000 {
@@ -729,6 +818,8 @@
 			#size-cells = <1>;
 			ranges;
 			ti,hwmods = "ocp2scp_usb_phy";
+			clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			usb2_phy: usb2phy@4a0ad080 {
 				compatible = "ti,omap-usb2";
 				reg = <0x4a0ad080 0x58>;
@@ -747,6 +838,8 @@
 			#mbox-cells = <1>;
 			ti,mbox-num-users = <3>;
 			ti,mbox-num-fifos = <8>;
+			clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
+			clock-names = "clkctrl";
 			mbox_ipu: mbox_ipu {
 				ti,mbox-tx = <0 0 0>;
 				ti,mbox-rx = <1 0 0>;
@@ -763,6 +856,8 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer1";
 			ti,timer-alwon;
+			clocks = <&dmt1_clk_mux>, <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 		};
 
 		timer2: timer@48032000 {
@@ -770,6 +865,8 @@
 			reg = <0x48032000 0x80>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer2";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer3: timer@48034000 {
@@ -777,6 +874,8 @@
 			reg = <0x48034000 0x80>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer3";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer4: timer@48036000 {
@@ -784,6 +883,8 @@
 			reg = <0x48036000 0x80>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer4";
+			clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer5: timer@40138000 {
@@ -793,6 +894,8 @@
 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer5";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer6: timer@4013a000 {
@@ -802,6 +905,8 @@
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer6";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer7: timer@4013c000 {
@@ -811,6 +916,8 @@
 			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer7";
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer8: timer@4013e000 {
@@ -821,6 +928,8 @@
 			ti,hwmods = "timer8";
 			ti,timer-pwm;
 			ti,timer-dsp;
+			clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer9: timer@4803e000 {
@@ -829,6 +938,8 @@
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer9";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer10: timer@48086000 {
@@ -837,6 +948,8 @@
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer10";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		timer11: timer@48088000 {
@@ -845,6 +958,8 @@
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
+			clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhstll: usbhstll@4a062000 {
@@ -852,6 +967,8 @@
 			reg = <0x4a062000 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 			ti,hwmods = "usb_tll_hs";
+			clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		usbhshost: usbhshost@4a064000 {
@@ -863,10 +980,12 @@
 			ranges;
 			clocks = <&init_60m_fclk>,
 				 <&xclk60mhsp1_ck>,
-				 <&xclk60mhsp2_ck>;
+				 <&xclk60mhsp2_ck>,
+				 <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
 			clock-names = "refclk_60m_int",
 				      "refclk_60m_ext_p1",
-				      "refclk_60m_ext_p2";
+				      "refclk_60m_ext_p2",
+				      "clkctrl";
 
 			usbhsohci: ohci@4a064800 {
 				compatible = "ti,ohci-omap3";
@@ -908,6 +1027,8 @@
 			num-eps = <16>;
 			ram-bits = <12>;
 			ctrl-module = <&omap_control_usbotg>;
+			clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+			clock-names = "clkctrl";
 		};
 
 		aes: aes@4b501000 {
@@ -959,8 +1080,9 @@
 			reg = <0x58000000 0x80>;
 			status = "disabled";
 			ti,hwmods = "dss_core";
-			clocks = <&dss_dss_clk>;
-			clock-names = "fck";
+			clocks = <&dss_dss_clk>,
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+			clock-names = "fck", "clkctrl";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -970,8 +1092,9 @@
 				reg = <0x58001000 0x1000>;
 				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				ti,hwmods = "dss_dispc";
-				clocks = <&dss_dss_clk>;
-				clock-names = "fck";
+				clocks = <&dss_dss_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			rfbi: encoder@58002000  {
@@ -979,8 +1102,9 @@
 				reg = <0x58002000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_rfbi";
-				clocks = <&dss_dss_clk>, <&l3_div_ck>;
-				clock-names = "fck", "ick";
+				clocks = <&dss_dss_clk>, <&l3_div_ck>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "ick", "clkctrl";
 			};
 
 			venc: encoder@58003000 {
@@ -988,8 +1112,9 @@
 				reg = <0x58003000 0x1000>;
 				status = "disabled";
 				ti,hwmods = "dss_venc";
-				clocks = <&dss_tv_clk>;
-				clock-names = "fck";
+				clocks = <&dss_tv_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "clkctrl";
 			};
 
 			dsi1: encoder@58004000 {
@@ -1001,8 +1126,9 @@
 				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi1";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			dsi2: encoder@58005000 {
@@ -1014,8 +1140,9 @@
 				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_dsi2";
-				clocks = <&dss_dss_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_dss_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 			};
 
 			hdmi: encoder@58006000 {
@@ -1028,8 +1155,9 @@
 				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 				ti,hwmods = "dss_hdmi";
-				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
-				clock-names = "fck", "sys_clk";
+				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>,
+					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>;
+				clock-names = "fck", "sys_clk", "clkctrl";
 				dmas = <&sdma 76>;
 				dma-names = "audio_tx";
 			};
-- 
1.9.1

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Convert the drivers to use the new clkctrl clocks.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 146 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 3ecf616..c39304a 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -94,16 +94,22 @@
>  			compatible = "ti,omap4-mpu";
>  			ti,hwmods = "mpu";
>  			sram = <&ocmcram>;
> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> +			clock-names = "clkctrl";
>  		};

Oh one more thing. I don't think we should add the clocks
here as they are now wrongly allocated to the device within
the interconnect target module. These clocks really belong
to each interconnect target module that we don't have in the
dts yet.

So we're better off adding the clockctrl clocks and then
changing the dts to use the interconnect target modules
with the clockctrl clocks.

Regards,

Tony

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Convert the drivers to use the new clkctrl clocks.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 146 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 3ecf616..c39304a 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -94,16 +94,22 @@
>  			compatible = "ti,omap4-mpu";
>  			ti,hwmods = "mpu";
>  			sram = <&ocmcram>;
> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> +			clock-names = "clkctrl";
>  		};

Oh one more thing. I don't think we should add the clocks
here as they are now wrongly allocated to the device within
the interconnect target module. These clocks really belong
to each interconnect target module that we don't have in the
dts yet.

So we're better off adding the clockctrl clocks and then
changing the dts to use the interconnect target modules
with the clockctrl clocks.

Regards,

Tony

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Convert the drivers to use the new clkctrl clocks.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 146 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> index 3ecf616..c39304a 100644
> --- a/arch/arm/boot/dts/omap4.dtsi
> +++ b/arch/arm/boot/dts/omap4.dtsi
> @@ -94,16 +94,22 @@
>  			compatible = "ti,omap4-mpu";
>  			ti,hwmods = "mpu";
>  			sram = <&ocmcram>;
> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> +			clock-names = "clkctrl";
>  		};

Oh one more thing. I don't think we should add the clocks
here as they are now wrongly allocated to the device within
the interconnect target module. These clocks really belong
to each interconnect target module that we don't have in the
dts yet.

So we're better off adding the clockctrl clocks and then
changing the dts to use the interconnect target modules
with the clockctrl clocks.

Regards,

Tony

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 03:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Convert the drivers to use the new clkctrl clocks.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 3ecf616..c39304a 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -94,16 +94,22 @@
>>  			compatible = "ti,omap4-mpu";
>>  			ti,hwmods = "mpu";
>>  			sram = <&ocmcram>;
>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>> +			clock-names = "clkctrl";
>>  		};
>
> Oh one more thing. I don't think we should add the clocks
> here as they are now wrongly allocated to the device within
> the interconnect target module. These clocks really belong
> to each interconnect target module that we don't have in the
> dts yet.
>
> So we're better off adding the clockctrl clocks and then
> changing the dts to use the interconnect target modules
> with the clockctrl clocks.

The problem is, you can't just add the clkctrl clock nodes themselves 
alone, as this introduces the problem that any clocks with no users will 
get disabled => causes a boot time hang when all the device clocks get 
shut down.

If you want to delay the usage of the clocks until you have interconnect 
target modules in place, you need to introduce the clock nodes also at 
that point, similar to what needs to be done now to squash patch #8 or #9.

-Tero

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 03:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Convert the drivers to use the new clkctrl clocks.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 3ecf616..c39304a 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -94,16 +94,22 @@
>>  			compatible = "ti,omap4-mpu";
>>  			ti,hwmods = "mpu";
>>  			sram = <&ocmcram>;
>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>> +			clock-names = "clkctrl";
>>  		};
>
> Oh one more thing. I don't think we should add the clocks
> here as they are now wrongly allocated to the device within
> the interconnect target module. These clocks really belong
> to each interconnect target module that we don't have in the
> dts yet.
>
> So we're better off adding the clockctrl clocks and then
> changing the dts to use the interconnect target modules
> with the clockctrl clocks.

The problem is, you can't just add the clkctrl clock nodes themselves 
alone, as this introduces the problem that any clocks with no users will 
get disabled => causes a boot time hang when all the device clocks get 
shut down.

If you want to delay the usage of the clocks until you have interconnect 
target modules in place, you need to introduce the clock nodes also at 
that point, similar to what needs to be done now to squash patch #8 or #9.

-Tero

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 03:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Convert the drivers to use the new clkctrl clocks.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 3ecf616..c39304a 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -94,16 +94,22 @@
>>  			compatible = "ti,omap4-mpu";
>>  			ti,hwmods = "mpu";
>>  			sram = <&ocmcram>;
>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>> +			clock-names = "clkctrl";
>>  		};
>
> Oh one more thing. I don't think we should add the clocks
> here as they are now wrongly allocated to the device within
> the interconnect target module. These clocks really belong
> to each interconnect target module that we don't have in the
> dts yet.
>
> So we're better off adding the clockctrl clocks and then
> changing the dts to use the interconnect target modules
> with the clockctrl clocks.

The problem is, you can't just add the clkctrl clock nodes themselves 
alone, as this introduces the problem that any clocks with no users will 
get disabled => causes a boot time hang when all the device clocks get 
shut down.

If you want to delay the usage of the clocks until you have interconnect 
target modules in place, you need to introduce the clock nodes also at 
that point, similar to what needs to be done now to squash patch #8 or #9.

-Tero

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170327 22:46]:
> On 28/03/17 03:18, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > Convert the drivers to use the new clkctrl clocks.
> > > 
> > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > ---
> > >  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
> > >  1 file changed, 146 insertions(+), 18 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > > index 3ecf616..c39304a 100644
> > > --- a/arch/arm/boot/dts/omap4.dtsi
> > > +++ b/arch/arm/boot/dts/omap4.dtsi
> > > @@ -94,16 +94,22 @@
> > >  			compatible = "ti,omap4-mpu";
> > >  			ti,hwmods = "mpu";
> > >  			sram = <&ocmcram>;
> > > +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> > > +			clock-names = "clkctrl";
> > >  		};
> > 
> > Oh one more thing. I don't think we should add the clocks
> > here as they are now wrongly allocated to the device within
> > the interconnect target module. These clocks really belong
> > to each interconnect target module that we don't have in the
> > dts yet.
> > 
> > So we're better off adding the clockctrl clocks and then
> > changing the dts to use the interconnect target modules
> > with the clockctrl clocks.
> 
> The problem is, you can't just add the clkctrl clock nodes themselves alone,
> as this introduces the problem that any clocks with no users will get
> disabled => causes a boot time hang when all the device clocks get shut
> down.

Hmm yeah. I wonder how to work around that.. What if we first updated
the clocks in the hwmod code? Or updated the aliases?

> If you want to delay the usage of the clocks until you have interconnect
> target modules in place, you need to introduce the clock nodes also at that
> point, similar to what needs to be done now to squash patch #8 or #9.

I'd like to do this one device at a time without any large
flips as we have quite a few devices with special handling for
reset and idling in the hwmod code.

Regards,

Tony

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170327 22:46]:
> On 28/03/17 03:18, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > Convert the drivers to use the new clkctrl clocks.
> > > 
> > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > ---
> > >  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
> > >  1 file changed, 146 insertions(+), 18 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > > index 3ecf616..c39304a 100644
> > > --- a/arch/arm/boot/dts/omap4.dtsi
> > > +++ b/arch/arm/boot/dts/omap4.dtsi
> > > @@ -94,16 +94,22 @@
> > >  			compatible = "ti,omap4-mpu";
> > >  			ti,hwmods = "mpu";
> > >  			sram = <&ocmcram>;
> > > +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> > > +			clock-names = "clkctrl";
> > >  		};
> > 
> > Oh one more thing. I don't think we should add the clocks
> > here as they are now wrongly allocated to the device within
> > the interconnect target module. These clocks really belong
> > to each interconnect target module that we don't have in the
> > dts yet.
> > 
> > So we're better off adding the clockctrl clocks and then
> > changing the dts to use the interconnect target modules
> > with the clockctrl clocks.
> 
> The problem is, you can't just add the clkctrl clock nodes themselves alone,
> as this introduces the problem that any clocks with no users will get
> disabled => causes a boot time hang when all the device clocks get shut
> down.

Hmm yeah. I wonder how to work around that.. What if we first updated
the clocks in the hwmod code? Or updated the aliases?

> If you want to delay the usage of the clocks until you have interconnect
> target modules in place, you need to introduce the clock nodes also at that
> point, similar to what needs to be done now to squash patch #8 or #9.

I'd like to do this one device at a time without any large
flips as we have quite a few devices with special handling for
reset and idling in the hwmod code.

Regards,

Tony

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170327 22:46]:
> On 28/03/17 03:18, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > Convert the drivers to use the new clkctrl clocks.
> > > 
> > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > ---
> > >  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
> > >  1 file changed, 146 insertions(+), 18 deletions(-)
> > > 
> > > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > > index 3ecf616..c39304a 100644
> > > --- a/arch/arm/boot/dts/omap4.dtsi
> > > +++ b/arch/arm/boot/dts/omap4.dtsi
> > > @@ -94,16 +94,22 @@
> > >  			compatible = "ti,omap4-mpu";
> > >  			ti,hwmods = "mpu";
> > >  			sram = <&ocmcram>;
> > > +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> > > +			clock-names = "clkctrl";
> > >  		};
> > 
> > Oh one more thing. I don't think we should add the clocks
> > here as they are now wrongly allocated to the device within
> > the interconnect target module. These clocks really belong
> > to each interconnect target module that we don't have in the
> > dts yet.
> > 
> > So we're better off adding the clockctrl clocks and then
> > changing the dts to use the interconnect target modules
> > with the clockctrl clocks.
> 
> The problem is, you can't just add the clkctrl clock nodes themselves alone,
> as this introduces the problem that any clocks with no users will get
> disabled => causes a boot time hang when all the device clocks get shut
> down.

Hmm yeah. I wonder how to work around that.. What if we first updated
the clocks in the hwmod code? Or updated the aliases?

> If you want to delay the usage of the clocks until you have interconnect
> target modules in place, you need to introduce the clock nodes also at that
> point, similar to what needs to be done now to squash patch #8 or #9.

I'd like to do this one device at a time without any large
flips as we have quite a few devices with special handling for
reset and idling in the hwmod code.

Regards,

Tony

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 18:03, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170327 22:46]:
>> On 28/03/17 03:18, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> Convert the drivers to use the new clkctrl clocks.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>>> index 3ecf616..c39304a 100644
>>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>>> @@ -94,16 +94,22 @@
>>>>  			compatible = "ti,omap4-mpu";
>>>>  			ti,hwmods = "mpu";
>>>>  			sram = <&ocmcram>;
>>>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>>>> +			clock-names = "clkctrl";
>>>>  		};
>>>
>>> Oh one more thing. I don't think we should add the clocks
>>> here as they are now wrongly allocated to the device within
>>> the interconnect target module. These clocks really belong
>>> to each interconnect target module that we don't have in the
>>> dts yet.
>>>
>>> So we're better off adding the clockctrl clocks and then
>>> changing the dts to use the interconnect target modules
>>> with the clockctrl clocks.
>>
>> The problem is, you can't just add the clkctrl clock nodes themselves alone,
>> as this introduces the problem that any clocks with no users will get
>> disabled => causes a boot time hang when all the device clocks get shut
>> down.
>
> Hmm yeah. I wonder how to work around that.. What if we first updated
> the clocks in the hwmod code? Or updated the aliases?

Kind of a chicken-egg problem. You could maybe probe the "ti,clkctrl" 
driver manually to avoid the issue.

The core clocks get disabled when CCF notices they are not used. You 
can't really avoid that with updating aliases / updating the clocks in 
hwmod code. And, hwmod basically tries to still use the same registers 
through the legacy route, which leads to conflict.

>
>> If you want to delay the usage of the clocks until you have interconnect
>> target modules in place, you need to introduce the clock nodes also at that
>> point, similar to what needs to be done now to squash patch #8 or #9.
>
> I'd like to do this one device at a time without any large
> flips as we have quite a few devices with special handling for
> reset and idling in the hwmod code.

One thing that can be done also is to introduce the clkctrl clocks one 
at a time in the data file also, but this is going to be cumbersome, as 
you need to keep these three in sync:

- drivers/clk/ti/clk-44xx.c
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c
- arch/arm/boot/dts/omap4.dtsi

... and that per SoC of course.

With the interconnect driver introduction, you should be able to flip 
one device at a time from hwmod to interconnect. In this case, all the 
clocks are already there, and you just need to modify DT + hwmod data to 
do the flip.

-Tero

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 18:03, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170327 22:46]:
>> On 28/03/17 03:18, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> Convert the drivers to use the new clkctrl clocks.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>>> index 3ecf616..c39304a 100644
>>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>>> @@ -94,16 +94,22 @@
>>>>  			compatible = "ti,omap4-mpu";
>>>>  			ti,hwmods = "mpu";
>>>>  			sram = <&ocmcram>;
>>>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>>>> +			clock-names = "clkctrl";
>>>>  		};
>>>
>>> Oh one more thing. I don't think we should add the clocks
>>> here as they are now wrongly allocated to the device within
>>> the interconnect target module. These clocks really belong
>>> to each interconnect target module that we don't have in the
>>> dts yet.
>>>
>>> So we're better off adding the clockctrl clocks and then
>>> changing the dts to use the interconnect target modules
>>> with the clockctrl clocks.
>>
>> The problem is, you can't just add the clkctrl clock nodes themselves alone,
>> as this introduces the problem that any clocks with no users will get
>> disabled => causes a boot time hang when all the device clocks get shut
>> down.
>
> Hmm yeah. I wonder how to work around that.. What if we first updated
> the clocks in the hwmod code? Or updated the aliases?

Kind of a chicken-egg problem. You could maybe probe the "ti,clkctrl" 
driver manually to avoid the issue.

The core clocks get disabled when CCF notices they are not used. You 
can't really avoid that with updating aliases / updating the clocks in 
hwmod code. And, hwmod basically tries to still use the same registers 
through the legacy route, which leads to conflict.

>
>> If you want to delay the usage of the clocks until you have interconnect
>> target modules in place, you need to introduce the clock nodes also at that
>> point, similar to what needs to be done now to squash patch #8 or #9.
>
> I'd like to do this one device at a time without any large
> flips as we have quite a few devices with special handling for
> reset and idling in the hwmod code.

One thing that can be done also is to introduce the clkctrl clocks one 
at a time in the data file also, but this is going to be cumbersome, as 
you need to keep these three in sync:

- drivers/clk/ti/clk-44xx.c
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c
- arch/arm/boot/dts/omap4.dtsi

... and that per SoC of course.

With the interconnect driver introduction, you should be able to flip 
one device at a time from hwmod to interconnect. In this case, all the 
clocks are already there, and you just need to modify DT + hwmod data to 
do the flip.

-Tero

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tero Kristo]

On 28/03/17 18:03, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170327 22:46]:
>> On 28/03/17 03:18, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>> Convert the drivers to use the new clkctrl clocks.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
>>>>  1 file changed, 146 insertions(+), 18 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>>>> index 3ecf616..c39304a 100644
>>>> --- a/arch/arm/boot/dts/omap4.dtsi
>>>> +++ b/arch/arm/boot/dts/omap4.dtsi
>>>> @@ -94,16 +94,22 @@
>>>>  			compatible = "ti,omap4-mpu";
>>>>  			ti,hwmods = "mpu";
>>>>  			sram = <&ocmcram>;
>>>> +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
>>>> +			clock-names = "clkctrl";
>>>>  		};
>>>
>>> Oh one more thing. I don't think we should add the clocks
>>> here as they are now wrongly allocated to the device within
>>> the interconnect target module. These clocks really belong
>>> to each interconnect target module that we don't have in the
>>> dts yet.
>>>
>>> So we're better off adding the clockctrl clocks and then
>>> changing the dts to use the interconnect target modules
>>> with the clockctrl clocks.
>>
>> The problem is, you can't just add the clkctrl clock nodes themselves alone,
>> as this introduces the problem that any clocks with no users will get
>> disabled => causes a boot time hang when all the device clocks get shut
>> down.
>
> Hmm yeah. I wonder how to work around that.. What if we first updated
> the clocks in the hwmod code? Or updated the aliases?

Kind of a chicken-egg problem. You could maybe probe the "ti,clkctrl" 
driver manually to avoid the issue.

The core clocks get disabled when CCF notices they are not used. You 
can't really avoid that with updating aliases / updating the clocks in 
hwmod code. And, hwmod basically tries to still use the same registers 
through the legacy route, which leads to conflict.

>
>> If you want to delay the usage of the clocks until you have interconnect
>> target modules in place, you need to introduce the clock nodes also at that
>> point, similar to what needs to be done now to squash patch #8 or #9.
>
> I'd like to do this one device at a time without any large
> flips as we have quite a few devices with special handling for
> reset and idling in the hwmod code.

One thing that can be done also is to introduce the clkctrl clocks one 
at a time in the data file also, but this is going to be cumbersome, as 
you need to keep these three in sync:

- drivers/clk/ti/clk-44xx.c
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c
- arch/arm/boot/dts/omap4.dtsi

... and that per SoC of course.

With the interconnect driver introduction, you should be able to flip 
one device at a time from hwmod to interconnect. In this case, all the 
clocks are already there, and you just need to modify DT + hwmod data to 
do the flip.

-Tero

Re: [PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170330 00:36]:
> On 28/03/17 18:03, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170327 22:46]:
> > > On 28/03/17 03:18, Tony Lindgren wrote:
> > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > Convert the drivers to use the new clkctrl clocks.
> > > > > 
> > > > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > > > ---
> > > > >  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
> > > > >  1 file changed, 146 insertions(+), 18 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > > > > index 3ecf616..c39304a 100644
> > > > > --- a/arch/arm/boot/dts/omap4.dtsi
> > > > > +++ b/arch/arm/boot/dts/omap4.dtsi
> > > > > @@ -94,16 +94,22 @@
> > > > >  			compatible = "ti,omap4-mpu";
> > > > >  			ti,hwmods = "mpu";
> > > > >  			sram = <&ocmcram>;
> > > > > +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> > > > > +			clock-names = "clkctrl";
> > > > >  		};
> > > > 
> > > > Oh one more thing. I don't think we should add the clocks
> > > > here as they are now wrongly allocated to the device within
> > > > the interconnect target module. These clocks really belong
> > > > to each interconnect target module that we don't have in the
> > > > dts yet.
> > > > 
> > > > So we're better off adding the clockctrl clocks and then
> > > > changing the dts to use the interconnect target modules
> > > > with the clockctrl clocks.
> > > 
> > > The problem is, you can't just add the clkctrl clock nodes themselves alone,
> > > as this introduces the problem that any clocks with no users will get
> > > disabled => causes a boot time hang when all the device clocks get shut
> > > down.
> > 
> > Hmm yeah. I wonder how to work around that.. What if we first updated
> > the clocks in the hwmod code? Or updated the aliases?
> 
> Kind of a chicken-egg problem. You could maybe probe the "ti,clkctrl" driver
> manually to avoid the issue.
> 
> The core clocks get disabled when CCF notices they are not used. You can't
> really avoid that with updating aliases / updating the clocks in hwmod code.
> And, hwmod basically tries to still use the same registers through the
> legacy route, which leads to conflict.

Yeah OK. Using status = "disabled" won't help much there either as the
amount of patching is still pretty much the same.

> > > If you want to delay the usage of the clocks until you have interconnect
> > > target modules in place, you need to introduce the clock nodes also at that
> > > point, similar to what needs to be done now to squash patch #8 or #9.
> > 
> > I'd like to do this one device at a time without any large
> > flips as we have quite a few devices with special handling for
> > reset and idling in the hwmod code.
> 
> One thing that can be done also is to introduce the clkctrl clocks one at a
> time in the data file also, but this is going to be cumbersome, as you need
> to keep these three in sync:
> 
> - drivers/clk/ti/clk-44xx.c
> - arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> - arch/arm/boot/dts/omap4.dtsi
> 
> ... and that per SoC of course.
> 
> With the interconnect driver introduction, you should be able to flip one
> device at a time from hwmod to interconnect. In this case, all the clocks
> are already there, and you just need to modify DT + hwmod data to do the
> flip.

Yes seems like that's what we should do then.

Regards,

Tony

[PATCHv2 9/9] ARM: dts: omap4: convert to use the new clkctrl clocks for the drivers

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170330 00:36]:
> On 28/03/17 18:03, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170327 22:46]:
> > > On 28/03/17 03:18, Tony Lindgren wrote:
> > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > Convert the drivers to use the new clkctrl clocks.
> > > > > 
> > > > > Signed-off-by: Tero Kristo <t-kristo@ti.com>
> > > > > ---
> > > > >  arch/arm/boot/dts/omap4.dtsi | 164 ++++++++++++++++++++++++++++++++++++++-----
> > > > >  1 file changed, 146 insertions(+), 18 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> > > > > index 3ecf616..c39304a 100644
> > > > > --- a/arch/arm/boot/dts/omap4.dtsi
> > > > > +++ b/arch/arm/boot/dts/omap4.dtsi
> > > > > @@ -94,16 +94,22 @@
> > > > >  			compatible = "ti,omap4-mpu";
> > > > >  			ti,hwmods = "mpu";
> > > > >  			sram = <&ocmcram>;
> > > > > +			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
> > > > > +			clock-names = "clkctrl";
> > > > >  		};
> > > > 
> > > > Oh one more thing. I don't think we should add the clocks
> > > > here as they are now wrongly allocated to the device within
> > > > the interconnect target module. These clocks really belong
> > > > to each interconnect target module that we don't have in the
> > > > dts yet.
> > > > 
> > > > So we're better off adding the clockctrl clocks and then
> > > > changing the dts to use the interconnect target modules
> > > > with the clockctrl clocks.
> > > 
> > > The problem is, you can't just add the clkctrl clock nodes themselves alone,
> > > as this introduces the problem that any clocks with no users will get
> > > disabled => causes a boot time hang when all the device clocks get shut
> > > down.
> > 
> > Hmm yeah. I wonder how to work around that.. What if we first updated
> > the clocks in the hwmod code? Or updated the aliases?
> 
> Kind of a chicken-egg problem. You could maybe probe the "ti,clkctrl" driver
> manually to avoid the issue.
> 
> The core clocks get disabled when CCF notices they are not used. You can't
> really avoid that with updating aliases / updating the clocks in hwmod code.
> And, hwmod basically tries to still use the same registers through the
> legacy route, which leads to conflict.

Yeah OK. Using status = "disabled" won't help much there either as the
amount of patching is still pretty much the same.

> > > If you want to delay the usage of the clocks until you have interconnect
> > > target modules in place, you need to introduce the clock nodes also at that
> > > point, similar to what needs to be done now to squash patch #8 or #9.
> > 
> > I'd like to do this one device at a time without any large
> > flips as we have quite a few devices with special handling for
> > reset and idling in the hwmod code.
> 
> One thing that can be done also is to introduce the clkctrl clocks one at a
> time in the data file also, but this is going to be cumbersome, as you need
> to keep these three in sync:
> 
> - drivers/clk/ti/clk-44xx.c
> - arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> - arch/arm/boot/dts/omap4.dtsi
> 
> ... and that per SoC of course.
> 
> With the interconnect driver introduction, you should be able to flip one
> device at a time from hwmod to interconnect. In this case, all the clocks
> are already there, and you just need to modify DT + hwmod data to do the
> flip.

Yes seems like that's what we should do then.

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Any additional testing on omap4 welcome as this series basically
> tweaks every possible peripheral clock on the SoC.

Without the last patch in this series, booting fails for me:

[    5.074890] l4_per_cm:clk:0120:0: failed to disable
[    5.085113] l4_per_cm:clk:0128:0: failed to disable

Care to check that booting keeps working for each patch in the
series to avoid breaking git bisect for booting?

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> Any additional testing on omap4 welcome as this series basically
> tweaks every possible peripheral clock on the SoC.

Without the last patch in this series, booting fails for me:

[    5.074890] l4_per_cm:clk:0120:0: failed to disable
[    5.085113] l4_per_cm:clk:0128:0: failed to disable

Care to check that booting keeps working for each patch in the
series to avoid breaking git bisect for booting?

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 17/03/17 17:25, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Any additional testing on omap4 welcome as this series basically
>> tweaks every possible peripheral clock on the SoC.
>
> Without the last patch in this series, booting fails for me:
>
> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>
> Care to check that booting keeps working for each patch in the
> series to avoid breaking git bisect for booting?

Hmm, I think patch 8+9 need to be squashed then. I can double check this 
next week though.

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 17/03/17 17:25, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Any additional testing on omap4 welcome as this series basically
>> tweaks every possible peripheral clock on the SoC.
>
> Without the last patch in this series, booting fails for me:
>
> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>
> Care to check that booting keeps working for each patch in the
> series to avoid breaking git bisect for booting?

Hmm, I think patch 8+9 need to be squashed then. I can double check this 
next week though.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 17/03/17 17:25, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>> Any additional testing on omap4 welcome as this series basically
>> tweaks every possible peripheral clock on the SoC.
>
> Without the last patch in this series, booting fails for me:
>
> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>
> Care to check that booting keeps working for each patch in the
> series to avoid breaking git bisect for booting?

Hmm, I think patch 8+9 need to be squashed then. I can double check this 
next week though.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> On 17/03/17 17:25, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > Any additional testing on omap4 welcome as this series basically
> > > tweaks every possible peripheral clock on the SoC.
> > 
> > Without the last patch in this series, booting fails for me:
> > 
> > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > 
> > Care to check that booting keeps working for each patch in the
> > series to avoid breaking git bisect for booting?
> 
> Hmm, I think patch 8+9 need to be squashed then. I can double check this
> next week though.

Also looks like with this set merged HDMI stops working on
omap4 with:

HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1

Other than that, things seem to behave quite nicely for me
with this set.

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> On 17/03/17 17:25, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > Any additional testing on omap4 welcome as this series basically
> > > tweaks every possible peripheral clock on the SoC.
> > 
> > Without the last patch in this series, booting fails for me:
> > 
> > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > 
> > Care to check that booting keeps working for each patch in the
> > series to avoid breaking git bisect for booting?
> 
> Hmm, I think patch 8+9 need to be squashed then. I can double check this
> next week though.

Also looks like with this set merged HDMI stops working on
omap4 with:

HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1

Other than that, things seem to behave quite nicely for me
with this set.

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [170322 18:03]:
> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > On 17/03/17 17:25, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Any additional testing on omap4 welcome as this series basically
> > > > tweaks every possible peripheral clock on the SoC.
> > > 
> > > Without the last patch in this series, booting fails for me:
> > > 
> > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > 
> > > Care to check that booting keeps working for each patch in the
> > > series to avoid breaking git bisect for booting?
> > 
> > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > next week though.
> 
> Also looks like with this set merged HDMI stops working on
> omap4 with:
> 
> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1

Forgot to mention that's with omapdrm with encoder-tpd12s015 and
encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
dmesg output in case that provides more clues:

[   91.042877] omapdss HDMICORE error: operation stopped when reading edid
[   91.078308] [drm] Enabling DMM ywrap scrolling
[   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
[   91.107879] omapdss HDMI error: failed to power on device
[   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
[   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.620300] Console: switching to colour frame buffer device 128x48
[   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
[   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[   92.818054] omapdss HDMICORE error: operation stopped when reading edid
[   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [170322 18:03]:
> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > On 17/03/17 17:25, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Any additional testing on omap4 welcome as this series basically
> > > > tweaks every possible peripheral clock on the SoC.
> > > 
> > > Without the last patch in this series, booting fails for me:
> > > 
> > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > 
> > > Care to check that booting keeps working for each patch in the
> > > series to avoid breaking git bisect for booting?
> > 
> > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > next week though.
> 
> Also looks like with this set merged HDMI stops working on
> omap4 with:
> 
> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1

Forgot to mention that's with omapdrm with encoder-tpd12s015 and
encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
dmesg output in case that provides more clues:

[   91.042877] omapdss HDMICORE error: operation stopped when reading edid
[   91.078308] [drm] Enabling DMM ywrap scrolling
[   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
[   91.107879] omapdss HDMI error: failed to power on device
[   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
[   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.620300] Console: switching to colour frame buffer device 128x48
[   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
[   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[   92.818054] omapdss HDMICORE error: operation stopped when reading edid
[   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [170322 18:03]:
> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > On 17/03/17 17:25, Tony Lindgren wrote:
> > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > Any additional testing on omap4 welcome as this series basically
> > > > tweaks every possible peripheral clock on the SoC.
> > > 
> > > Without the last patch in this series, booting fails for me:
> > > 
> > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > 
> > > Care to check that booting keeps working for each patch in the
> > > series to avoid breaking git bisect for booting?
> > 
> > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > next week though.
> 
> Also looks like with this set merged HDMI stops working on
> omap4 with:
> 
> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1

Forgot to mention that's with omapdrm with encoder-tpd12s015 and
encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
dmesg output in case that provides more clues:

[   91.042877] omapdss HDMICORE error: operation stopped when reading edid
[   91.078308] [drm] Enabling DMM ywrap scrolling
[   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
[   91.107879] omapdss HDMI error: failed to power on device
[   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
[   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   91.620300] Console: switching to colour frame buffer device 128x48
[   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
[   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[   92.818054] omapdss HDMICORE error: operation stopped when reading edid
[   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
[   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

I have an idea what is wrong here, and also an idea how to fix it. 
Basically the display clock hierarchy is kind of special from hwmod 
point of view, so need to tweak the data for this a bit. This should not 
result into code changes if my idea works out well.

I'll try to have a look at this during this week still, I've been busy 
with some bug fixing lately.

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

I have an idea what is wrong here, and also an idea how to fix it. 
Basically the display clock hierarchy is kind of special from hwmod 
point of view, so need to tweak the data for this a bit. This should not 
result into code changes if my idea works out well.

I'll try to have a look at this during this week still, I've been busy 
with some bug fixing lately.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!

I have an idea what is wrong here, and also an idea how to fix it. 
Basically the display clock hierarchy is kind of special from hwmod 
point of view, so need to tweak the data for this a bit. This should not 
result into code changes if my idea works out well.

I'll try to have a look at this during this week still, I've been busy 
with some bug fixing lately.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>
> Regards,
>
> Tony
>

Can you try with this additional hwmod data tweak in place? Apply this 
on top of the existing series.

===========


 From 8ba1829078ea9a7417a34564fde8a30c9bdeb273 Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@ti.com>
Date: Thu, 30 Mar 2017 10:09:59 +0300
Subject: [PATCH] ARM: OMAP4: hwmod_data: add opt clks for dss_hdmi and
  dss_venc

These extra optional clocks are required as main clock for these modules
are going to be routed to the main module clock. Otherwise, the hdmi / tv
clocks are not going to be enabled during usage, leading to failure.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 7 +++++++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..2a9d092 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -858,6 +859,10 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
@@ -870,6 +875,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*
-- 
1.9.1

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>
> Regards,
>
> Tony
>

Can you try with this additional hwmod data tweak in place? Apply this 
on top of the existing series.

===========


 From 8ba1829078ea9a7417a34564fde8a30c9bdeb273 Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@ti.com>
Date: Thu, 30 Mar 2017 10:09:59 +0300
Subject: [PATCH] ARM: OMAP4: hwmod_data: add opt clks for dss_hdmi and
  dss_venc

These extra optional clocks are required as main clock for these modules
are going to be routed to the main module clock. Otherwise, the hdmi / tv
clocks are not going to be enabled during usage, leading to failure.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 7 +++++++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..2a9d092 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -858,6 +859,10 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
@@ -870,6 +875,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*
-- 
1.9.1

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 23/03/17 19:02, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>> Any additional testing on omap4 welcome as this series basically
>>>>> tweaks every possible peripheral clock on the SoC.
>>>>
>>>> Without the last patch in this series, booting fails for me:
>>>>
>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>
>>>> Care to check that booting keeps working for each patch in the
>>>> series to avoid breaking git bisect for booting?
>>>
>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>> next week though.
>>
>> Also looks like with this set merged HDMI stops working on
>> omap4 with:
>>
>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>
> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> dmesg output in case that provides more clues:
>
> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> [   91.078308] [drm] Enabling DMM ywrap scrolling
> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> [   91.107879] omapdss HDMI error: failed to power on device
> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   91.620300] Console: switching to colour frame buffer device 128x48
> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>
> Regards,
>
> Tony
>

Can you try with this additional hwmod data tweak in place? Apply this 
on top of the existing series.

===========


 From 8ba1829078ea9a7417a34564fde8a30c9bdeb273 Mon Sep 17 00:00:00 2001
From: Tero Kristo <t-kristo@ti.com>
Date: Thu, 30 Mar 2017 10:09:59 +0300
Subject: [PATCH] ARM: OMAP4: hwmod_data: add opt clks for dss_hdmi and
  dss_venc

These extra optional clocks are required as main clock for these modules
are going to be routed to the main module clock. Otherwise, the hdmi / tv
clocks are not going to be enabled during usage, leading to failure.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 7 +++++++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..2a9d092 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -858,6 +859,10 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
@@ -870,6 +875,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*
-- 
1.9.1

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> On 23/03/17 19:02, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > 
> > > > > Without the last patch in this series, booting fails for me:
> > > > > 
> > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > 
> > > > > Care to check that booting keeps working for each patch in the
> > > > > series to avoid breaking git bisect for booting?
> > > > 
> > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > next week though.
> > > 
> > > Also looks like with this set merged HDMI stops working on
> > > omap4 with:
> > > 
> > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > 
> > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > dmesg output in case that provides more clues:
> > 
> > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > [   91.107879] omapdss HDMI error: failed to power on device
> > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   91.620300] Console: switching to colour frame buffer device 128x48
> > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > 
> > Regards,
> > 
> > Tony
> > 
> 
> Can you try with this additional hwmod data tweak in place? Apply this on
> top of the existing series.

Does not seem to help, still get the same errors. But maybe I'm doing
something wrong as the patch did not apply and I applied it manually.

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> On 23/03/17 19:02, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > 
> > > > > Without the last patch in this series, booting fails for me:
> > > > > 
> > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > 
> > > > > Care to check that booting keeps working for each patch in the
> > > > > series to avoid breaking git bisect for booting?
> > > > 
> > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > next week though.
> > > 
> > > Also looks like with this set merged HDMI stops working on
> > > omap4 with:
> > > 
> > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > 
> > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > dmesg output in case that provides more clues:
> > 
> > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > [   91.107879] omapdss HDMI error: failed to power on device
> > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   91.620300] Console: switching to colour frame buffer device 128x48
> > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > 
> > Regards,
> > 
> > Tony
> > 
> 
> Can you try with this additional hwmod data tweak in place? Apply this on
> top of the existing series.

Does not seem to help, still get the same errors. But maybe I'm doing
something wrong as the patch did not apply and I applied it manually.

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 30/03/17 19:54, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>> On 23/03/17 19:02, Tony Lindgren wrote:
>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>
>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>
>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>
>>>>>> Care to check that booting keeps working for each patch in the
>>>>>> series to avoid breaking git bisect for booting?
>>>>>
>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>> next week though.
>>>>
>>>> Also looks like with this set merged HDMI stops working on
>>>> omap4 with:
>>>>
>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>
>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>> dmesg output in case that provides more clues:
>>>
>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>> [   91.107879] omapdss HDMI error: failed to power on device
>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Can you try with this additional hwmod data tweak in place? Apply this on
>> top of the existing series.
>
> Does not seem to help, still get the same errors. But maybe I'm doing
> something wrong as the patch did not apply and I applied it manually.
>
> Regards,
>
> Tony
>

Hmm ok, can you provide some brief instructions how to test what you are 
doing with the HDMI? Just connect it to some external monitor? My 
monitor has a spare HDMI connector so I could try it out.

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 30/03/17 19:54, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>> On 23/03/17 19:02, Tony Lindgren wrote:
>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>
>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>
>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>
>>>>>> Care to check that booting keeps working for each patch in the
>>>>>> series to avoid breaking git bisect for booting?
>>>>>
>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>> next week though.
>>>>
>>>> Also looks like with this set merged HDMI stops working on
>>>> omap4 with:
>>>>
>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>
>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>> dmesg output in case that provides more clues:
>>>
>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>> [   91.107879] omapdss HDMI error: failed to power on device
>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Can you try with this additional hwmod data tweak in place? Apply this on
>> top of the existing series.
>
> Does not seem to help, still get the same errors. But maybe I'm doing
> something wrong as the patch did not apply and I applied it manually.
>
> Regards,
>
> Tony
>

Hmm ok, can you provide some brief instructions how to test what you are 
doing with the HDMI? Just connect it to some external monitor? My 
monitor has a spare HDMI connector so I could try it out.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 30/03/17 19:54, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>> On 23/03/17 19:02, Tony Lindgren wrote:
>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>
>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>
>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>
>>>>>> Care to check that booting keeps working for each patch in the
>>>>>> series to avoid breaking git bisect for booting?
>>>>>
>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>> next week though.
>>>>
>>>> Also looks like with this set merged HDMI stops working on
>>>> omap4 with:
>>>>
>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>
>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>> dmesg output in case that provides more clues:
>>>
>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>> [   91.107879] omapdss HDMI error: failed to power on device
>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Can you try with this additional hwmod data tweak in place? Apply this on
>> top of the existing series.
>
> Does not seem to help, still get the same errors. But maybe I'm doing
> something wrong as the patch did not apply and I applied it manually.
>
> Regards,
>
> Tony
>

Hmm ok, can you provide some brief instructions how to test what you are 
doing with the HDMI? Just connect it to some external monitor? My 
monitor has a spare HDMI connector so I could try it out.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170403 07:54]:
> On 30/03/17 19:54, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> > > On 23/03/17 19:02, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > > > 
> > > > > > > Without the last patch in this series, booting fails for me:
> > > > > > > 
> > > > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > > > 
> > > > > > > Care to check that booting keeps working for each patch in the
> > > > > > > series to avoid breaking git bisect for booting?
> > > > > > 
> > > > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > > > next week though.
> > > > > 
> > > > > Also looks like with this set merged HDMI stops working on
> > > > > omap4 with:
> > > > > 
> > > > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > 
> > > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > > > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > > > dmesg output in case that provides more clues:
> > > > 
> > > > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > > > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > [   91.107879] omapdss HDMI error: failed to power on device
> > > > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > > > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.620300] Console: switching to colour frame buffer device 128x48
> > > > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > > > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > > > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > 
> > > > Regards,
> > > > 
> > > > Tony
> > > > 
> > > 
> > > Can you try with this additional hwmod data tweak in place? Apply this on
> > > top of the existing series.
> > 
> > Does not seem to help, still get the same errors. But maybe I'm doing
> > something wrong as the patch did not apply and I applied it manually.
> > 
> > Regards,
> > 
> > Tony
> > 
> 
> Hmm ok, can you provide some brief instructions how to test what you are
> doing with the HDMI? Just connect it to some external monitor? My monitor
> has a spare HDMI connector so I could try it out.

Well build a kernel using omap2plus_defconfig, then with HDMI cable
connected load the following modules:

encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb

And a console should appear on the HDMI monitor. If using omapdrm, then
load omapdss and omapdrm instead.

And if using NFSroot, you need to have ehci and smsc drivers built-in
or use an initramfs.

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170403 07:54]:
> On 30/03/17 19:54, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> > > On 23/03/17 19:02, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > > > 
> > > > > > > Without the last patch in this series, booting fails for me:
> > > > > > > 
> > > > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > > > 
> > > > > > > Care to check that booting keeps working for each patch in the
> > > > > > > series to avoid breaking git bisect for booting?
> > > > > > 
> > > > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > > > next week though.
> > > > > 
> > > > > Also looks like with this set merged HDMI stops working on
> > > > > omap4 with:
> > > > > 
> > > > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > 
> > > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > > > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > > > dmesg output in case that provides more clues:
> > > > 
> > > > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > > > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > [   91.107879] omapdss HDMI error: failed to power on device
> > > > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > > > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.620300] Console: switching to colour frame buffer device 128x48
> > > > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > > > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > > > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > 
> > > > Regards,
> > > > 
> > > > Tony
> > > > 
> > > 
> > > Can you try with this additional hwmod data tweak in place? Apply this on
> > > top of the existing series.
> > 
> > Does not seem to help, still get the same errors. But maybe I'm doing
> > something wrong as the patch did not apply and I applied it manually.
> > 
> > Regards,
> > 
> > Tony
> > 
> 
> Hmm ok, can you provide some brief instructions how to test what you are
> doing with the HDMI? Just connect it to some external monitor? My monitor
> has a spare HDMI connector so I could try it out.

Well build a kernel using omap2plus_defconfig, then with HDMI cable
connected load the following modules:

encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb

And a console should appear on the HDMI monitor. If using omapdrm, then
load omapdss and omapdrm instead.

And if using NFSroot, you need to have ehci and smsc drivers built-in
or use an initramfs.

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170403 07:54]:
> On 30/03/17 19:54, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> > > On 23/03/17 19:02, Tony Lindgren wrote:
> > > > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > > > 
> > > > > > > Without the last patch in this series, booting fails for me:
> > > > > > > 
> > > > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > > > 
> > > > > > > Care to check that booting keeps working for each patch in the
> > > > > > > series to avoid breaking git bisect for booting?
> > > > > > 
> > > > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > > > next week though.
> > > > > 
> > > > > Also looks like with this set merged HDMI stops working on
> > > > > omap4 with:
> > > > > 
> > > > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > 
> > > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > > > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > > > dmesg output in case that provides more clues:
> > > > 
> > > > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > > > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > [   91.107879] omapdss HDMI error: failed to power on device
> > > > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > > > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   91.620300] Console: switching to colour frame buffer device 128x48
> > > > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > > > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > > > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > > > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > 
> > > > Regards,
> > > > 
> > > > Tony
> > > > 
> > > 
> > > Can you try with this additional hwmod data tweak in place? Apply this on
> > > top of the existing series.
> > 
> > Does not seem to help, still get the same errors. But maybe I'm doing
> > something wrong as the patch did not apply and I applied it manually.
> > 
> > Regards,
> > 
> > Tony
> > 
> 
> Hmm ok, can you provide some brief instructions how to test what you are
> doing with the HDMI? Just connect it to some external monitor? My monitor
> has a spare HDMI connector so I could try it out.

Well build a kernel using omap2plus_defconfig, then with HDMI cable
connected load the following modules:

encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb

And a console should appear on the HDMI monitor. If using omapdrm, then
load omapdss and omapdrm instead.

And if using NFSroot, you need to have ehci and smsc drivers built-in
or use an initramfs.

Regards,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok I am able to reproduce the issue. Seems something weird with the hdmi 
hwmod itself, if I revert it back to its original form (just the hdmi 
one) then it works fine. Haven't figured out yet what is the actual 
problem but seems something timing related, as it also starts magically 
working with the clkctrl clock driver setup if I add enough traces to 
some critical points.

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok I am able to reproduce the issue. Seems something weird with the hdmi 
hwmod itself, if I revert it back to its original form (just the hdmi 
one) then it works fine. Haven't figured out yet what is the actual 
problem but seems something timing related, as it also starts magically 
working with the clkctrl clock driver setup if I add enough traces to 
some critical points.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok I am able to reproduce the issue. Seems something weird with the hdmi 
hwmod itself, if I revert it back to its original form (just the hdmi 
one) then it works fine. Haven't figured out yet what is the actual 
problem but seems something timing related, as it also starts magically 
working with the clkctrl clock driver setup if I add enough traces to 
some critical points.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok, I have a solution to the issue.

Try the slightly modified patch below. It just required a couple of 
hwmod flags applied in addition to the patch I sent before.

I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, 
where also the hdmi works fine on omap4.

===================================

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..43163b5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -785,7 +786,7 @@
  	 * HDMI audio requires to use no-idle mode. Hence,
  	 * set idle mode by software.
  	 */
-	.flags		= HWMOD_SWSUP_SIDLE,
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
  	.xlate_irq	= omap4_xlate_irq,
  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
@@ -858,11 +859,16 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
  	.clkdm_name	= "l3_dss_clkdm",
  	.main_clk	= "dss_tv_clk",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
  	.prcm = {
  		.omap4 = {
  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -870,6 +876,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok, I have a solution to the issue.

Try the slightly modified patch below. It just required a couple of 
hwmod flags applied in addition to the patch I sent before.

I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, 
where also the hdmi works fine on omap4.

===================================

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..43163b5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -785,7 +786,7 @@
  	 * HDMI audio requires to use no-idle mode. Hence,
  	 * set idle mode by software.
  	 */
-	.flags		= HWMOD_SWSUP_SIDLE,
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
  	.xlate_irq	= omap4_xlate_irq,
  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
@@ -858,11 +859,16 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
  	.clkdm_name	= "l3_dss_clkdm",
  	.main_clk	= "dss_tv_clk",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
  	.prcm = {
  		.omap4 = {
  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -870,6 +876,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 03/04/17 18:36, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>> On 30/03/17 19:54, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>
>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>
>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>
>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>
>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>> next week though.
>>>>>>
>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>> omap4 with:
>>>>>>
>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>
>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>> dmesg output in case that provides more clues:
>>>>>
>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>> top of the existing series.
>>>
>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>> something wrong as the patch did not apply and I applied it manually.
>>>
>>> Regards,
>>>
>>> Tony
>>>
>>
>> Hmm ok, can you provide some brief instructions how to test what you are
>> doing with the HDMI? Just connect it to some external monitor? My monitor
>> has a spare HDMI connector so I could try it out.
>
> Well build a kernel using omap2plus_defconfig, then with HDMI cable
> connected load the following modules:
>
> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>
> And a console should appear on the HDMI monitor. If using omapdrm, then
> load omapdss and omapdrm instead.
>
> And if using NFSroot, you need to have ehci and smsc drivers built-in
> or use an initramfs.

Ok, I have a solution to the issue.

Try the slightly modified patch below. It just required a couple of 
hwmod flags applied in addition to the patch I sent before.

I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, 
where also the hdmi works fine on omap4.

===================================

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dad871a..43163b5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -775,6 +775,7 @@

  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
+	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
  };

  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
@@ -785,7 +786,7 @@
  	 * HDMI audio requires to use no-idle mode. Hence,
  	 * set idle mode by software.
  	 */
-	.flags		= HWMOD_SWSUP_SIDLE,
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
  	.xlate_irq	= omap4_xlate_irq,
  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
@@ -858,11 +859,16 @@
  };

  /* dss_venc */
+static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
+	{ .role = "tv_clk", .clk = "dss_tv_clk" },
+};
+
  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
  	.name		= "dss_venc",
  	.class		= &omap44xx_venc_hwmod_class,
  	.clkdm_name	= "l3_dss_clkdm",
  	.main_clk	= "dss_tv_clk",
+	.flags		= HWMOD_OPT_CLKS_NEEDED,
  	.prcm = {
  		.omap4 = {
  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -870,6 +876,8 @@
  		},
  	},
  	.parent_hwmod	= &omap44xx_dss_hwmod,
+	.opt_clks	= dss_venc_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
  };

  /*

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170406 09:51]:
> On 03/04/17 18:36, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
> > > On 30/03/17 19:54, Tony Lindgren wrote:
> > > > * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> > > > > On 23/03/17 19:02, Tony Lindgren wrote:
> > > > > > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > > > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > > > > > 
> > > > > > > > > Without the last patch in this series, booting fails for me:
> > > > > > > > > 
> > > > > > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > > > > > 
> > > > > > > > > Care to check that booting keeps working for each patch in the
> > > > > > > > > series to avoid breaking git bisect for booting?
> > > > > > > > 
> > > > > > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > > > > > next week though.
> > > > > > > 
> > > > > > > Also looks like with this set merged HDMI stops working on
> > > > > > > omap4 with:
> > > > > > > 
> > > > > > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > > > 
> > > > > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > > > > > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > > > > > dmesg output in case that provides more clues:
> > > > > > 
> > > > > > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > > > > > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > > > > > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > > > [   91.107879] omapdss HDMI error: failed to power on device
> > > > > > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > > > > > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   91.620300] Console: switching to colour frame buffer device 128x48
> > > > > > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > > > > > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > > > > > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > > > > > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > 
> > > > > > Regards,
> > > > > > 
> > > > > > Tony
> > > > > > 
> > > > > 
> > > > > Can you try with this additional hwmod data tweak in place? Apply this on
> > > > > top of the existing series.
> > > > 
> > > > Does not seem to help, still get the same errors. But maybe I'm doing
> > > > something wrong as the patch did not apply and I applied it manually.
> > > > 
> > > > Regards,
> > > > 
> > > > Tony
> > > > 
> > > 
> > > Hmm ok, can you provide some brief instructions how to test what you are
> > > doing with the HDMI? Just connect it to some external monitor? My monitor
> > > has a spare HDMI connector so I could try it out.
> > 
> > Well build a kernel using omap2plus_defconfig, then with HDMI cable
> > connected load the following modules:
> > 
> > encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
> > 
> > And a console should appear on the HDMI monitor. If using omapdrm, then
> > load omapdss and omapdrm instead.
> > 
> > And if using NFSroot, you need to have ehci and smsc drivers built-in
> > or use an initramfs.
> 
> Ok, I have a solution to the issue.
> 
> Try the slightly modified patch below. It just required a couple of hwmod
> flags applied in addition to the patch I sent before.
> 
> I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, where
> also the hdmi works fine on omap4.

OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
that change is now needed though?

Regards,

Tony

> ===================================
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index dad871a..43163b5 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -775,6 +775,7 @@
> 
>  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
>  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>  };
> 
>  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
> @@ -785,7 +786,7 @@
>  	 * HDMI audio requires to use no-idle mode. Hence,
>  	 * set idle mode by software.
>  	 */
> -	.flags		= HWMOD_SWSUP_SIDLE,
> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
>  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>  	.xlate_irq	= omap4_xlate_irq,
>  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
> @@ -858,11 +859,16 @@
>  };
> 
>  /* dss_venc */
> +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> +};
> +
>  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>  	.name		= "dss_venc",
>  	.class		= &omap44xx_venc_hwmod_class,
>  	.clkdm_name	= "l3_dss_clkdm",
>  	.main_clk	= "dss_tv_clk",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> @@ -870,6 +876,8 @@
>  		},
>  	},
>  	.parent_hwmod	= &omap44xx_dss_hwmod,
> +	.opt_clks	= dss_venc_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
>  };
> 
>  /*
> 
> 
> 

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170406 09:51]:
> On 03/04/17 18:36, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
> > > On 30/03/17 19:54, Tony Lindgren wrote:
> > > > * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
> > > > > On 23/03/17 19:02, Tony Lindgren wrote:
> > > > > > * Tony Lindgren <tony@atomide.com> [170322 18:03]:
> > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
> > > > > > > > On 17/03/17 17:25, Tony Lindgren wrote:
> > > > > > > > > * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
> > > > > > > > > > Any additional testing on omap4 welcome as this series basically
> > > > > > > > > > tweaks every possible peripheral clock on the SoC.
> > > > > > > > > 
> > > > > > > > > Without the last patch in this series, booting fails for me:
> > > > > > > > > 
> > > > > > > > > [    5.074890] l4_per_cm:clk:0120:0: failed to disable
> > > > > > > > > [    5.085113] l4_per_cm:clk:0128:0: failed to disable
> > > > > > > > > 
> > > > > > > > > Care to check that booting keeps working for each patch in the
> > > > > > > > > series to avoid breaking git bisect for booting?
> > > > > > > > 
> > > > > > > > Hmm, I think patch 8+9 need to be squashed then. I can double check this
> > > > > > > > next week though.
> > > > > > > 
> > > > > > > Also looks like with this set merged HDMI stops working on
> > > > > > > omap4 with:
> > > > > > > 
> > > > > > > HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > > > 
> > > > > > Forgot to mention that's with omapdrm with encoder-tpd12s015 and
> > > > > > encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
> > > > > > dmesg output in case that provides more clues:
> > > > > > 
> > > > > > [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
> > > > > > [   91.078308] [drm] Enabling DMM ywrap scrolling
> > > > > > [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
> > > > > > [   91.107879] omapdss HDMI error: failed to power on device
> > > > > > [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
> > > > > > [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   91.620300] Console: switching to colour frame buffer device 128x48
> > > > > > [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
> > > > > > [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
> > > > > > [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
> > > > > > [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
> > > > > > 
> > > > > > Regards,
> > > > > > 
> > > > > > Tony
> > > > > > 
> > > > > 
> > > > > Can you try with this additional hwmod data tweak in place? Apply this on
> > > > > top of the existing series.
> > > > 
> > > > Does not seem to help, still get the same errors. But maybe I'm doing
> > > > something wrong as the patch did not apply and I applied it manually.
> > > > 
> > > > Regards,
> > > > 
> > > > Tony
> > > > 
> > > 
> > > Hmm ok, can you provide some brief instructions how to test what you are
> > > doing with the HDMI? Just connect it to some external monitor? My monitor
> > > has a spare HDMI connector so I could try it out.
> > 
> > Well build a kernel using omap2plus_defconfig, then with HDMI cable
> > connected load the following modules:
> > 
> > encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
> > 
> > And a console should appear on the HDMI monitor. If using omapdrm, then
> > load omapdss and omapdrm instead.
> > 
> > And if using NFSroot, you need to have ehci and smsc drivers built-in
> > or use an initramfs.
> 
> Ok, I have a solution to the issue.
> 
> Try the slightly modified patch below. It just required a couple of hwmod
> flags applied in addition to the patch I sent before.
> 
> I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, where
> also the hdmi works fine on omap4.

OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
that change is now needed though?

Regards,

Tony

> ===================================
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index dad871a..43163b5 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -775,6 +775,7 @@
> 
>  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
>  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>  };
> 
>  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
> @@ -785,7 +786,7 @@
>  	 * HDMI audio requires to use no-idle mode. Hence,
>  	 * set idle mode by software.
>  	 */
> -	.flags		= HWMOD_SWSUP_SIDLE,
> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
>  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>  	.xlate_irq	= omap4_xlate_irq,
>  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
> @@ -858,11 +859,16 @@
>  };
> 
>  /* dss_venc */
> +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
> +};
> +
>  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>  	.name		= "dss_venc",
>  	.class		= &omap44xx_venc_hwmod_class,
>  	.clkdm_name	= "l3_dss_clkdm",
>  	.main_clk	= "dss_tv_clk",
> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
> @@ -870,6 +876,8 @@
>  		},
>  	},
>  	.parent_hwmod	= &omap44xx_dss_hwmod,
> +	.opt_clks	= dss_venc_opt_clks,
> +	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
>  };
> 
>  /*
> 
> 
> 

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 07/04/17 19:47, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170406 09:51]:
>> On 03/04/17 18:36, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>>>> On 30/03/17 19:54, Tony Lindgren wrote:
>>>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>>>
>>>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>>>
>>>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>>>
>>>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>>>
>>>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>>>> next week though.
>>>>>>>>
>>>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>>>> omap4 with:
>>>>>>>>
>>>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>>
>>>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>>>> dmesg output in case that provides more clues:
>>>>>>>
>>>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>>
>>>>>>> Regards,
>>>>>>>
>>>>>>> Tony
>>>>>>>
>>>>>>
>>>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>>>> top of the existing series.
>>>>>
>>>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>>>> something wrong as the patch did not apply and I applied it manually.
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Hmm ok, can you provide some brief instructions how to test what you are
>>>> doing with the HDMI? Just connect it to some external monitor? My monitor
>>>> has a spare HDMI connector so I could try it out.
>>>
>>> Well build a kernel using omap2plus_defconfig, then with HDMI cable
>>> connected load the following modules:
>>>
>>> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>>>
>>> And a console should appear on the HDMI monitor. If using omapdrm, then
>>> load omapdss and omapdrm instead.
>>>
>>> And if using NFSroot, you need to have ehci and smsc drivers built-in
>>> or use an initramfs.
>>
>> Ok, I have a solution to the issue.
>>
>> Try the slightly modified patch below. It just required a couple of hwmod
>> flags applied in addition to the patch I sent before.
>>
>> I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, where
>> also the hdmi works fine on omap4.
>
> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> that change is now needed though?

Yes, it is pretty clear actually. Previously, the hwmod main clock was 
controlling the hdmi clock, but this is now rerouted to the clkctrl 
module clock, which is shared between all DSS submodules. This leaves 
the hdmi clock disabled, causing the failure.

The fix just puts the hdmi clock into the optional clocks list, and 
forces all the optional clocks on when pm_runtime is enabled for the module.

-Tero

>
> Regards,
>
> Tony
>
>> ===================================
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> index dad871a..43163b5 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> @@ -775,6 +775,7 @@
>>
>>  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
>>  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
>> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>>  };
>>
>>  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
>> @@ -785,7 +786,7 @@
>>  	 * HDMI audio requires to use no-idle mode. Hence,
>>  	 * set idle mode by software.
>>  	 */
>> -	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
>>  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>>  	.xlate_irq	= omap4_xlate_irq,
>>  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
>> @@ -858,11 +859,16 @@
>>  };
>>
>>  /* dss_venc */
>> +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
>> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
>> +};
>> +
>>  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>>  	.name		= "dss_venc",
>>  	.class		= &omap44xx_venc_hwmod_class,
>>  	.clkdm_name	= "l3_dss_clkdm",
>>  	.main_clk	= "dss_tv_clk",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>>  	.prcm = {
>>  		.omap4 = {
>>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>> @@ -870,6 +876,8 @@
>>  		},
>>  	},
>>  	.parent_hwmod	= &omap44xx_dss_hwmod,
>> +	.opt_clks	= dss_venc_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
>>  };
>>
>>  /*
>>
>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 07/04/17 19:47, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170406 09:51]:
>> On 03/04/17 18:36, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>>>> On 30/03/17 19:54, Tony Lindgren wrote:
>>>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>>>
>>>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>>>
>>>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>>>
>>>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>>>
>>>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>>>> next week though.
>>>>>>>>
>>>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>>>> omap4 with:
>>>>>>>>
>>>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>>
>>>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>>>> dmesg output in case that provides more clues:
>>>>>>>
>>>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>>
>>>>>>> Regards,
>>>>>>>
>>>>>>> Tony
>>>>>>>
>>>>>>
>>>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>>>> top of the existing series.
>>>>>
>>>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>>>> something wrong as the patch did not apply and I applied it manually.
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Hmm ok, can you provide some brief instructions how to test what you are
>>>> doing with the HDMI? Just connect it to some external monitor? My monitor
>>>> has a spare HDMI connector so I could try it out.
>>>
>>> Well build a kernel using omap2plus_defconfig, then with HDMI cable
>>> connected load the following modules:
>>>
>>> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>>>
>>> And a console should appear on the HDMI monitor. If using omapdrm, then
>>> load omapdss and omapdrm instead.
>>>
>>> And if using NFSroot, you need to have ehci and smsc drivers built-in
>>> or use an initramfs.
>>
>> Ok, I have a solution to the issue.
>>
>> Try the slightly modified patch below. It just required a couple of hwmod
>> flags applied in addition to the patch I sent before.
>>
>> I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, where
>> also the hdmi works fine on omap4.
>
> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> that change is now needed though?

Yes, it is pretty clear actually. Previously, the hwmod main clock was 
controlling the hdmi clock, but this is now rerouted to the clkctrl 
module clock, which is shared between all DSS submodules. This leaves 
the hdmi clock disabled, causing the failure.

The fix just puts the hdmi clock into the optional clocks list, and 
forces all the optional clocks on when pm_runtime is enabled for the module.

-Tero

>
> Regards,
>
> Tony
>
>> ===================================
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> index dad871a..43163b5 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> @@ -775,6 +775,7 @@
>>
>>  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
>>  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
>> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>>  };
>>
>>  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
>> @@ -785,7 +786,7 @@
>>  	 * HDMI audio requires to use no-idle mode. Hence,
>>  	 * set idle mode by software.
>>  	 */
>> -	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
>>  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>>  	.xlate_irq	= omap4_xlate_irq,
>>  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
>> @@ -858,11 +859,16 @@
>>  };
>>
>>  /* dss_venc */
>> +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
>> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
>> +};
>> +
>>  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>>  	.name		= "dss_venc",
>>  	.class		= &omap44xx_venc_hwmod_class,
>>  	.clkdm_name	= "l3_dss_clkdm",
>>  	.main_clk	= "dss_tv_clk",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>>  	.prcm = {
>>  		.omap4 = {
>>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>> @@ -870,6 +876,8 @@
>>  		},
>>  	},
>>  	.parent_hwmod	= &omap44xx_dss_hwmod,
>> +	.opt_clks	= dss_venc_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
>>  };
>>
>>  /*
>>
>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 07/04/17 19:47, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170406 09:51]:
>> On 03/04/17 18:36, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [170403 07:54]:
>>>> On 30/03/17 19:54, Tony Lindgren wrote:
>>>>> * Tero Kristo <t-kristo@ti.com> [170330 00:20]:
>>>>>> On 23/03/17 19:02, Tony Lindgren wrote:
>>>>>>> * Tony Lindgren <tony@atomide.com> [170322 18:03]:
>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 14:39]:
>>>>>>>>> On 17/03/17 17:25, Tony Lindgren wrote:
>>>>>>>>>> * Tero Kristo <t-kristo@ti.com> [170317 02:12]:
>>>>>>>>>>> Any additional testing on omap4 welcome as this series basically
>>>>>>>>>>> tweaks every possible peripheral clock on the SoC.
>>>>>>>>>>
>>>>>>>>>> Without the last patch in this series, booting fails for me:
>>>>>>>>>>
>>>>>>>>>> [    5.074890] l4_per_cm:clk:0120:0: failed to disable
>>>>>>>>>> [    5.085113] l4_per_cm:clk:0128:0: failed to disable
>>>>>>>>>>
>>>>>>>>>> Care to check that booting keeps working for each patch in the
>>>>>>>>>> series to avoid breaking git bisect for booting?
>>>>>>>>>
>>>>>>>>> Hmm, I think patch 8+9 need to be squashed then. I can double check this
>>>>>>>>> next week though.
>>>>>>>>
>>>>>>>> Also looks like with this set merged HDMI stops working on
>>>>>>>> omap4 with:
>>>>>>>>
>>>>>>>> HDMIWP: omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>>
>>>>>>> Forgot to mention that's with omapdrm with encoder-tpd12s015 and
>>>>>>> encoder-tfp410 modules loaded to get HDMI working. Here's more verbose
>>>>>>> dmesg output in case that provides more clues:
>>>>>>>
>>>>>>> [   91.042877] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   91.078308] [drm] Enabling DMM ywrap scrolling
>>>>>>> [   91.099243] omapdss HDMIWP error: Failed to set PHY power mode to 1
>>>>>>> [   91.107879] omapdss HDMI error: failed to power on device
>>>>>>> [   91.107879] omapdrm omapdrm.0: Failed to enable display 'hdmi': -5
>>>>>>> [   91.359619] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.619964] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   91.620300] Console: switching to colour frame buffer device 128x48
>>>>>>> [   91.682434] omapdrm omapdrm.0: fb0: omapdrm frame buffer device
>>>>>>> [   91.770812] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
>>>>>>> [   92.818054] omapdss HDMICORE error: operation stopped when reading edid
>>>>>>> [   93.090087] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>> [   93.349853] omapdrm omapdrm.0: atomic complete timeout (pipe 0)!
>>>>>>>
>>>>>>> Regards,
>>>>>>>
>>>>>>> Tony
>>>>>>>
>>>>>>
>>>>>> Can you try with this additional hwmod data tweak in place? Apply this on
>>>>>> top of the existing series.
>>>>>
>>>>> Does not seem to help, still get the same errors. But maybe I'm doing
>>>>> something wrong as the patch did not apply and I applied it manually.
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tony
>>>>>
>>>>
>>>> Hmm ok, can you provide some brief instructions how to test what you are
>>>> doing with the HDMI? Just connect it to some external monitor? My monitor
>>>> has a spare HDMI connector so I could try it out.
>>>
>>> Well build a kernel using omap2plus_defconfig, then with HDMI cable
>>> connected load the following modules:
>>>
>>> encoder-tpd12s015 encoder-tfp410 connector-hdmi omapfb
>>>
>>> And a console should appear on the HDMI monitor. If using omapdrm, then
>>> load omapdss and omapdrm instead.
>>>
>>> And if using NFSroot, you need to have ehci and smsc drivers built-in
>>> or use an initramfs.
>>
>> Ok, I have a solution to the issue.
>>
>> Try the slightly modified patch below. It just required a couple of hwmod
>> flags applied in addition to the patch I sent before.
>>
>> I also pushed a branch named "4.11-rc1-clkctrl-wip" as a reference, where
>> also the hdmi works fine on omap4.
>
> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> that change is now needed though?

Yes, it is pretty clear actually. Previously, the hwmod main clock was 
controlling the hdmi clock, but this is now rerouted to the clkctrl 
module clock, which is shared between all DSS submodules. This leaves 
the hdmi clock disabled, causing the failure.

The fix just puts the hdmi clock into the optional clocks list, and 
forces all the optional clocks on when pm_runtime is enabled for the module.

-Tero

>
> Regards,
>
> Tony
>
>> ===================================
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> index dad871a..43163b5 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
>> @@ -775,6 +775,7 @@
>>
>>  static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
>>  	{ .role = "sys_clk", .clk = "dss_sys_clk" },
>> +	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
>>  };
>>
>>  static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
>> @@ -785,7 +786,7 @@
>>  	 * HDMI audio requires to use no-idle mode. Hence,
>>  	 * set idle mode by software.
>>  	 */
>> -	.flags		= HWMOD_SWSUP_SIDLE,
>> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
>>  	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
>>  	.xlate_irq	= omap4_xlate_irq,
>>  	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
>> @@ -858,11 +859,16 @@
>>  };
>>
>>  /* dss_venc */
>> +static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
>> +	{ .role = "tv_clk", .clk = "dss_tv_clk" },
>> +};
>> +
>>  static struct omap_hwmod omap44xx_dss_venc_hwmod = {
>>  	.name		= "dss_venc",
>>  	.class		= &omap44xx_venc_hwmod_class,
>>  	.clkdm_name	= "l3_dss_clkdm",
>>  	.main_clk	= "dss_tv_clk",
>> +	.flags		= HWMOD_OPT_CLKS_NEEDED,
>>  	.prcm = {
>>  		.omap4 = {
>>  			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
>> @@ -870,6 +876,8 @@
>>  		},
>>  	},
>>  	.parent_hwmod	= &omap44xx_dss_hwmod,
>> +	.opt_clks	= dss_venc_opt_clks,
>> +	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
>>  };
>>
>>  /*
>>
>>
>>
> --
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Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170410 00:34]:
> On 07/04/17 19:47, Tony Lindgren wrote:
> > OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> > that change is now needed though?
> 
> Yes, it is pretty clear actually. Previously, the hwmod main clock was
> controlling the hdmi clock, but this is now rerouted to the clkctrl module
> clock, which is shared between all DSS submodules. This leaves the hdmi
> clock disabled, causing the failure.
> 
> The fix just puts the hdmi clock into the optional clocks list, and forces
> all the optional clocks on when pm_runtime is enabled for the module.

OK so no need to fix it in the current kernels then.

Thanks,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170410 00:34]:
> On 07/04/17 19:47, Tony Lindgren wrote:
> > OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> > that change is now needed though?
> 
> Yes, it is pretty clear actually. Previously, the hwmod main clock was
> controlling the hdmi clock, but this is now rerouted to the clkctrl module
> clock, which is shared between all DSS submodules. This leaves the hdmi
> clock disabled, causing the failure.
> 
> The fix just puts the hdmi clock into the optional clocks list, and forces
> all the optional clocks on when pm_runtime is enabled for the module.

OK so no need to fix it in the current kernels then.

Thanks,

Tony

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 10/04/17 19:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170410 00:34]:
>> On 07/04/17 19:47, Tony Lindgren wrote:
>>> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
>>> that change is now needed though?
>>
>> Yes, it is pretty clear actually. Previously, the hwmod main clock was
>> controlling the hdmi clock, but this is now rerouted to the clkctrl module
>> clock, which is shared between all DSS submodules. This leaves the hdmi
>> clock disabled, causing the failure.
>>
>> The fix just puts the hdmi clock into the optional clocks list, and forces
>> all the optional clocks on when pm_runtime is enabled for the module.
>
> OK so no need to fix it in the current kernels then.

Yeah, just need to figure out a clean order of applying these patches. 
The hwmod data change for DSS modules can most likely be applied before 
the dts change for clkctrl is going in, as it is just causing double 
clk_enable / disable for the main clocks in that case.

-Tero

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 10/04/17 19:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170410 00:34]:
>> On 07/04/17 19:47, Tony Lindgren wrote:
>>> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
>>> that change is now needed though?
>>
>> Yes, it is pretty clear actually. Previously, the hwmod main clock was
>> controlling the hdmi clock, but this is now rerouted to the clkctrl module
>> clock, which is shared between all DSS submodules. This leaves the hdmi
>> clock disabled, causing the failure.
>>
>> The fix just puts the hdmi clock into the optional clocks list, and forces
>> all the optional clocks on when pm_runtime is enabled for the module.
>
> OK so no need to fix it in the current kernels then.

Yeah, just need to figure out a clean order of applying these patches. 
The hwmod data change for DSS modules can most likely be applied before 
the dts change for clkctrl is going in, as it is just causing double 
clk_enable / disable for the main clocks in that case.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tero Kristo]

On 10/04/17 19:18, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [170410 00:34]:
>> On 07/04/17 19:47, Tony Lindgren wrote:
>>> OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
>>> that change is now needed though?
>>
>> Yes, it is pretty clear actually. Previously, the hwmod main clock was
>> controlling the hdmi clock, but this is now rerouted to the clkctrl module
>> clock, which is shared between all DSS submodules. This leaves the hdmi
>> clock disabled, causing the failure.
>>
>> The fix just puts the hdmi clock into the optional clocks list, and forces
>> all the optional clocks on when pm_runtime is enabled for the module.
>
> OK so no need to fix it in the current kernels then.

Yeah, just need to figure out a clean order of applying these patches. 
The hwmod data change for DSS modules can most likely be applied before 
the dts change for clkctrl is going in, as it is just causing double 
clk_enable / disable for the main clocks in that case.

-Tero

Re: [PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170410 11:36]:
> On 10/04/17 19:18, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170410 00:34]:
> > > On 07/04/17 19:47, Tony Lindgren wrote:
> > > > OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> > > > that change is now needed though?
> > > 
> > > Yes, it is pretty clear actually. Previously, the hwmod main clock was
> > > controlling the hdmi clock, but this is now rerouted to the clkctrl module
> > > clock, which is shared between all DSS submodules. This leaves the hdmi
> > > clock disabled, causing the failure.
> > > 
> > > The fix just puts the hdmi clock into the optional clocks list, and forces
> > > all the optional clocks on when pm_runtime is enabled for the module.
> > 
> > OK so no need to fix it in the current kernels then.
> 
> Yeah, just need to figure out a clean order of applying these patches. The
> hwmod data change for DSS modules can most likely be applied before the dts
> change for clkctrl is going in, as it is just causing double clk_enable /
> disable for the main clocks in that case.

Yeah no idea about the hwmod change needed for DSS.. Maybe patch it in
only in the no "ti,hwmods" path?

For the rest, how about the following for getting things patched with
a minimal patching needed to revert in case of regressions:

1. Let's add the clkctrl driver and it's dts clocks. Let's tag the
   new clkctrl clocks with status = "disabled" and not add the
   consumers into any existing devices

2. Let's modify the dts files to add the hwmod related items for the
   wrapper IP module but let's keep things probing the old way using
   compatible = "simple-bus" for now

3. Let's add the wrapper IP driver and make sure it does nothing
   except probe the children just like "simple-bus" currently does if
   the child module has the "ti,hwmods" property set

4. Then we can finally start flipping things over one module at a
   time just by removing "ti,hwmods" for the child device and
   status = "disabled" for the related module clock

Regards,

Tony

[PATCHv2 0/9] clk: ti: add support for clkctrl clocks

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [170410 11:36]:
> On 10/04/17 19:18, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [170410 00:34]:
> > > On 07/04/17 19:47, Tony Lindgren wrote:
> > > > OK hdmi works now on panda for both omapfb and omapdrm. Any ideas why
> > > > that change is now needed though?
> > > 
> > > Yes, it is pretty clear actually. Previously, the hwmod main clock was
> > > controlling the hdmi clock, but this is now rerouted to the clkctrl module
> > > clock, which is shared between all DSS submodules. This leaves the hdmi
> > > clock disabled, causing the failure.
> > > 
> > > The fix just puts the hdmi clock into the optional clocks list, and forces
> > > all the optional clocks on when pm_runtime is enabled for the module.
> > 
> > OK so no need to fix it in the current kernels then.
> 
> Yeah, just need to figure out a clean order of applying these patches. The
> hwmod data change for DSS modules can most likely be applied before the dts
> change for clkctrl is going in, as it is just causing double clk_enable /
> disable for the main clocks in that case.

Yeah no idea about the hwmod change needed for DSS.. Maybe patch it in
only in the no "ti,hwmods" path?

For the rest, how about the following for getting things patched with
a minimal patching needed to revert in case of regressions:

1. Let's add the clkctrl driver and it's dts clocks. Let's tag the
   new clkctrl clocks with status = "disabled" and not add the
   consumers into any existing devices

2. Let's modify the dts files to add the hwmod related items for the
   wrapper IP module but let's keep things probing the old way using
   compatible = "simple-bus" for now

3. Let's add the wrapper IP driver and make sure it does nothing
   except probe the children just like "simple-bus" currently does if
   the child module has the "ti,hwmods" property set

4. Then we can finally start flipping things over one module at a
   time just by removing "ti,hwmods" for the child device and
   status = "disabled" for the related module clock

Regards,

Tony