* [CRTC:24] vblank wait timed out
@ 2017-03-21 9:50 Martyn Welch
2017-03-21 17:18 ` Philipp Zabel
0 siblings, 1 reply; 10+ messages in thread
From: Martyn Welch @ 2017-03-21 9:50 UTC (permalink / raw)
To: dri-devel
I have an i.MX6 platform with 2 display port interfaces, one driven by the
HDMI interface, the other by LVDS, both via bridges. We are currently
experiencing the following error when we boot with the monitor connected
to the LVDS backed interface and then connect a monitor to the HDMI backed
interface after boot:
Mar 20 18:15:23 GE00409729044C kernel: ------------[ cut here ]------------
Mar 20 18:15:23 GE00409729044C kernel: WARNING: CPU: 1 PID: 85 at /home/martyn/build-helix/tmp/work-shared/csmon/kernel-source/drivers/gpu/drm/drm_atomic_helper.c:1121 drm_atomic_helper_wait_for_vblanks+0x264/0x274
Mar 20 18:15:23 GE00409729044C kernel: [CRTC:24] vblank wait timed out
Mar 20 18:15:23 GE00409729044C kernel: Modules linked in: bonding snd_usb_audio snd_hwdep snd_usbmidi_lib snd_rawmidi cp210x usbserial atmel_mxt_ts
Mar 20 18:15:23 GE00409729044C kernel: CPU: 1 PID: 85 Comm: kworker/u4:1 Not tainted 4.8.0 #4
Mar 20 18:15:23 GE00409729044C kernel: Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
Mar 20 18:15:23 GE00409729044C kernel: Workqueue: events_unbound commit_work
Mar 20 18:15:23 GE00409729044C kernel: Backtrace:
Mar 20 18:15:23 GE00409729044C kernel: [<8010c968>] (dump_backtrace) from [<8010cbb0>] (show_stack+0x20/0x24)
Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:80d2bf98 r5:600b0013 r4:00000000
Mar 20 18:15:23 GE00409729044C kernel: [<8010cb90>] (show_stack) from [<803c0e68>] (dump_stack+0x98/0xb4)
Mar 20 18:15:23 GE00409729044C kernel: [<803c0dd0>] (dump_stack) from [<80122abc>] (__warn+0xe4/0x110)
Mar 20 18:15:23 GE00409729044C kernel: r7:00000009 r6:80a8d490 r5:00000000 r4:ee173e10
Mar 20 18:15:23 GE00409729044C kernel: [<801229d8>] (__warn) from [<80122b2c>] (warn_slowpath_fmt+0x44/0x4c)
Mar 20 18:15:23 GE00409729044C kernel: r9:ee1e5418 r8:00000000 r7:00000000 r6:00000000 r5:ecc04f00 r4:80a8d5ec
Mar 20 18:15:23 GE00409729044C kernel: [<80122aec>] (warn_slowpath_fmt) from [<80486ce0>] (drm_atomic_helper_wait_for_vblanks+0x264/0x274)
Mar 20 18:15:23 GE00409729044C kernel: r3:00000018 r2:80a8d5ec
Mar 20 18:15:23 GE00409729044C kernel: r4:edaa8200
Mar 20 18:15:23 GE00409729044C kernel: [<80486a7c>] (drm_atomic_helper_wait_for_vblanks) from [<804b3990>] (imx_drm_atomic_commit_tail+0x1b4/0x1e0)
Mar 20 18:15:23 GE00409729044C kernel: r10:0ee80680 r9:80d76580 r8:00000000 r7:ee1e5000 r6:ecc04f00 r5:00000000
Mar 20 18:15:23 GE00409729044C kernel: r4:00000004
Mar 20 18:15:23 GE00409729044C kernel: [<804b37dc>] (imx_drm_atomic_commit_tail) from [<80487498>] (commit_tail+0x50/0x6c)
Mar 20 18:15:23 GE00409729044C kernel: r7:ee806800 r6:ee82b000 r5:80d3a5fc r4:ecc04f00
Mar 20 18:15:23 GE00409729044C kernel: [<80487448>] (commit_tail) from [<804874d0>] (commit_work+0x1c/0x20)
Mar 20 18:15:23 GE00409729044C kernel: r5:eeb97280 r4:ecc04f1c
Mar 20 18:15:23 GE00409729044C kernel: [<804874b4>] (commit_work) from [<8013b638>] (process_one_work+0x154/0x510)
Mar 20 18:15:23 GE00409729044C kernel: [<8013b4e4>] (process_one_work) from [<8013ba30>] (worker_thread+0x3c/0x5cc)
Mar 20 18:15:23 GE00409729044C kernel: r10:eeb97280 r9:ee82b000 r8:80d02100 r7:ee82b018 r6:00000088 r5:eeb97298
Mar 20 18:15:23 GE00409729044C kernel: r4:ee82b000
Mar 20 18:15:23 GE00409729044C kernel: [<8013b9f4>] (worker_thread) from [<80141670>] (kthread+0xe4/0x100)
Mar 20 18:15:23 GE00409729044C kernel: r10:00000000 r9:00000000 r8:00000000 r7:8013b9f4 r6:eeb97280 r5:eebae640
Mar 20 18:15:23 GE00409729044C kernel: r4:00000000
Mar 20 18:15:23 GE00409729044C kernel: [<8014158c>] (kthread) from [<80108278>] (ret_from_fork+0x14/0x3c)
Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:00000000 r5:8014158c r4:eebae640
Mar 20 18:15:23 GE00409729044C kernel: ---[ end trace ba005811962ba6f2 ]---
We believe this may be due to the vblank interrupt for the LVDS interface
being affected when the vblank interface for the HDMI backed interface
gets enabled. Any pointers regarding how to proceed narrowing down/fixing
this would be appreciated.
We are currently running 4.8 kernel with 1.11 Weston compositor.
Martyn
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-21 9:50 [CRTC:24] vblank wait timed out Martyn Welch
@ 2017-03-21 17:18 ` Philipp Zabel
2017-03-24 10:24 ` Martyn Welch
0 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2017-03-21 17:18 UTC (permalink / raw)
To: Martyn Welch; +Cc: dri-devel
Hi Martyn,
On Tue, 2017-03-21 at 09:50 +0000, Martyn Welch wrote:
> I have an i.MX6 platform with 2 display port interfaces, one driven by the
> HDMI interface, the other by LVDS, both via bridges. We are currently
> experiencing the following error when we boot with the monitor connected
> to the LVDS backed interface and then connect a monitor to the HDMI backed
> interface after boot:
>
> Mar 20 18:15:23 GE00409729044C kernel: ------------[ cut here ]------------
> Mar 20 18:15:23 GE00409729044C kernel: WARNING: CPU: 1 PID: 85 at /home/martyn/build-helix/tmp/work-shared/csmon/kernel-source/drivers/gpu/drm/drm_atomic_helper.c:1121 drm_atomic_helper_wait_for_vblanks+0x264/0x274
> Mar 20 18:15:23 GE00409729044C kernel: [CRTC:24] vblank wait timed out
> Mar 20 18:15:23 GE00409729044C kernel: Modules linked in: bonding snd_usb_audio snd_hwdep snd_usbmidi_lib snd_rawmidi cp210x usbserial atmel_mxt_ts
> Mar 20 18:15:23 GE00409729044C kernel: CPU: 1 PID: 85 Comm: kworker/u4:1 Not tainted 4.8.0 #4
> Mar 20 18:15:23 GE00409729044C kernel: Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> Mar 20 18:15:23 GE00409729044C kernel: Workqueue: events_unbound commit_work
> Mar 20 18:15:23 GE00409729044C kernel: Backtrace:
> Mar 20 18:15:23 GE00409729044C kernel: [<8010c968>] (dump_backtrace) from [<8010cbb0>] (show_stack+0x20/0x24)
> Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:80d2bf98 r5:600b0013 r4:00000000
> Mar 20 18:15:23 GE00409729044C kernel: [<8010cb90>] (show_stack) from [<803c0e68>] (dump_stack+0x98/0xb4)
> Mar 20 18:15:23 GE00409729044C kernel: [<803c0dd0>] (dump_stack) from [<80122abc>] (__warn+0xe4/0x110)
> Mar 20 18:15:23 GE00409729044C kernel: r7:00000009 r6:80a8d490 r5:00000000 r4:ee173e10
> Mar 20 18:15:23 GE00409729044C kernel: [<801229d8>] (__warn) from [<80122b2c>] (warn_slowpath_fmt+0x44/0x4c)
> Mar 20 18:15:23 GE00409729044C kernel: r9:ee1e5418 r8:00000000 r7:00000000 r6:00000000 r5:ecc04f00 r4:80a8d5ec
> Mar 20 18:15:23 GE00409729044C kernel: [<80122aec>] (warn_slowpath_fmt) from [<80486ce0>] (drm_atomic_helper_wait_for_vblanks+0x264/0x274)
> Mar 20 18:15:23 GE00409729044C kernel: r3:00000018 r2:80a8d5ec
> Mar 20 18:15:23 GE00409729044C kernel: r4:edaa8200
> Mar 20 18:15:23 GE00409729044C kernel: [<80486a7c>] (drm_atomic_helper_wait_for_vblanks) from [<804b3990>] (imx_drm_atomic_commit_tail+0x1b4/0x1e0)
> Mar 20 18:15:23 GE00409729044C kernel: r10:0ee80680 r9:80d76580 r8:00000000 r7:ee1e5000 r6:ecc04f00 r5:00000000
> Mar 20 18:15:23 GE00409729044C kernel: r4:00000004
> Mar 20 18:15:23 GE00409729044C kernel: [<804b37dc>] (imx_drm_atomic_commit_tail) from [<80487498>] (commit_tail+0x50/0x6c)
> Mar 20 18:15:23 GE00409729044C kernel: r7:ee806800 r6:ee82b000 r5:80d3a5fc r4:ecc04f00
> Mar 20 18:15:23 GE00409729044C kernel: [<80487448>] (commit_tail) from [<804874d0>] (commit_work+0x1c/0x20)
> Mar 20 18:15:23 GE00409729044C kernel: r5:eeb97280 r4:ecc04f1c
> Mar 20 18:15:23 GE00409729044C kernel: [<804874b4>] (commit_work) from [<8013b638>] (process_one_work+0x154/0x510)
> Mar 20 18:15:23 GE00409729044C kernel: [<8013b4e4>] (process_one_work) from [<8013ba30>] (worker_thread+0x3c/0x5cc)
> Mar 20 18:15:23 GE00409729044C kernel: r10:eeb97280 r9:ee82b000 r8:80d02100 r7:ee82b018 r6:00000088 r5:eeb97298
> Mar 20 18:15:23 GE00409729044C kernel: r4:ee82b000
> Mar 20 18:15:23 GE00409729044C kernel: [<8013b9f4>] (worker_thread) from [<80141670>] (kthread+0xe4/0x100)
> Mar 20 18:15:23 GE00409729044C kernel: r10:00000000 r9:00000000 r8:00000000 r7:8013b9f4 r6:eeb97280 r5:eebae640
> Mar 20 18:15:23 GE00409729044C kernel: r4:00000000
> Mar 20 18:15:23 GE00409729044C kernel: [<8014158c>] (kthread) from [<80108278>] (ret_from_fork+0x14/0x3c)
> Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:00000000 r5:8014158c r4:eebae640
> Mar 20 18:15:23 GE00409729044C kernel: ---[ end trace ba005811962ba6f2 ]---
>
> We believe this may be due to the vblank interrupt for the LVDS interface
> being affected when the vblank interface for the HDMI backed interface
> gets enabled. Any pointers regarding how to proceed narrowing down/fixing
> this would be appreciated.
>
> We are currently running 4.8 kernel with 1.11 Weston compositor.
>
> Martyn
Could you move to v4.9 or v4.10 and check if the four patches in
https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
or
https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
help?
regards
Philipp
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-21 17:18 ` Philipp Zabel
@ 2017-03-24 10:24 ` Martyn Welch
2017-03-24 10:42 ` Philipp Zabel
0 siblings, 1 reply; 10+ messages in thread
From: Martyn Welch @ 2017-03-24 10:24 UTC (permalink / raw)
To: Philipp Zabel; +Cc: dri-devel
On Tue, Mar 21, 2017 at 06:18:44PM +0100, Philipp Zabel wrote:
> Hi Martyn,
>
> On Tue, 2017-03-21 at 09:50 +0000, Martyn Welch wrote:
> > I have an i.MX6 platform with 2 display port interfaces, one driven by the
> > HDMI interface, the other by LVDS, both via bridges. We are currently
> > experiencing the following error when we boot with the monitor connected
> > to the LVDS backed interface and then connect a monitor to the HDMI backed
> > interface after boot:
> >
> > Mar 20 18:15:23 GE00409729044C kernel: ------------[ cut here ]------------
> > Mar 20 18:15:23 GE00409729044C kernel: WARNING: CPU: 1 PID: 85 at /home/martyn/build-helix/tmp/work-shared/csmon/kernel-source/drivers/gpu/drm/drm_atomic_helper.c:1121 drm_atomic_helper_wait_for_vblanks+0x264/0x274
> > Mar 20 18:15:23 GE00409729044C kernel: [CRTC:24] vblank wait timed out
> > Mar 20 18:15:23 GE00409729044C kernel: Modules linked in: bonding snd_usb_audio snd_hwdep snd_usbmidi_lib snd_rawmidi cp210x usbserial atmel_mxt_ts
> > Mar 20 18:15:23 GE00409729044C kernel: CPU: 1 PID: 85 Comm: kworker/u4:1 Not tainted 4.8.0 #4
> > Mar 20 18:15:23 GE00409729044C kernel: Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> > Mar 20 18:15:23 GE00409729044C kernel: Workqueue: events_unbound commit_work
> > Mar 20 18:15:23 GE00409729044C kernel: Backtrace:
> > Mar 20 18:15:23 GE00409729044C kernel: [<8010c968>] (dump_backtrace) from [<8010cbb0>] (show_stack+0x20/0x24)
> > Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:80d2bf98 r5:600b0013 r4:00000000
> > Mar 20 18:15:23 GE00409729044C kernel: [<8010cb90>] (show_stack) from [<803c0e68>] (dump_stack+0x98/0xb4)
> > Mar 20 18:15:23 GE00409729044C kernel: [<803c0dd0>] (dump_stack) from [<80122abc>] (__warn+0xe4/0x110)
> > Mar 20 18:15:23 GE00409729044C kernel: r7:00000009 r6:80a8d490 r5:00000000 r4:ee173e10
> > Mar 20 18:15:23 GE00409729044C kernel: [<801229d8>] (__warn) from [<80122b2c>] (warn_slowpath_fmt+0x44/0x4c)
> > Mar 20 18:15:23 GE00409729044C kernel: r9:ee1e5418 r8:00000000 r7:00000000 r6:00000000 r5:ecc04f00 r4:80a8d5ec
> > Mar 20 18:15:23 GE00409729044C kernel: [<80122aec>] (warn_slowpath_fmt) from [<80486ce0>] (drm_atomic_helper_wait_for_vblanks+0x264/0x274)
> > Mar 20 18:15:23 GE00409729044C kernel: r3:00000018 r2:80a8d5ec
> > Mar 20 18:15:23 GE00409729044C kernel: r4:edaa8200
> > Mar 20 18:15:23 GE00409729044C kernel: [<80486a7c>] (drm_atomic_helper_wait_for_vblanks) from [<804b3990>] (imx_drm_atomic_commit_tail+0x1b4/0x1e0)
> > Mar 20 18:15:23 GE00409729044C kernel: r10:0ee80680 r9:80d76580 r8:00000000 r7:ee1e5000 r6:ecc04f00 r5:00000000
> > Mar 20 18:15:23 GE00409729044C kernel: r4:00000004
> > Mar 20 18:15:23 GE00409729044C kernel: [<804b37dc>] (imx_drm_atomic_commit_tail) from [<80487498>] (commit_tail+0x50/0x6c)
> > Mar 20 18:15:23 GE00409729044C kernel: r7:ee806800 r6:ee82b000 r5:80d3a5fc r4:ecc04f00
> > Mar 20 18:15:23 GE00409729044C kernel: [<80487448>] (commit_tail) from [<804874d0>] (commit_work+0x1c/0x20)
> > Mar 20 18:15:23 GE00409729044C kernel: r5:eeb97280 r4:ecc04f1c
> > Mar 20 18:15:23 GE00409729044C kernel: [<804874b4>] (commit_work) from [<8013b638>] (process_one_work+0x154/0x510)
> > Mar 20 18:15:23 GE00409729044C kernel: [<8013b4e4>] (process_one_work) from [<8013ba30>] (worker_thread+0x3c/0x5cc)
> > Mar 20 18:15:23 GE00409729044C kernel: r10:eeb97280 r9:ee82b000 r8:80d02100 r7:ee82b018 r6:00000088 r5:eeb97298
> > Mar 20 18:15:23 GE00409729044C kernel: r4:ee82b000
> > Mar 20 18:15:23 GE00409729044C kernel: [<8013b9f4>] (worker_thread) from [<80141670>] (kthread+0xe4/0x100)
> > Mar 20 18:15:23 GE00409729044C kernel: r10:00000000 r9:00000000 r8:00000000 r7:8013b9f4 r6:eeb97280 r5:eebae640
> > Mar 20 18:15:23 GE00409729044C kernel: r4:00000000
> > Mar 20 18:15:23 GE00409729044C kernel: [<8014158c>] (kthread) from [<80108278>] (ret_from_fork+0x14/0x3c)
> > Mar 20 18:15:23 GE00409729044C kernel: r7:00000000 r6:00000000 r5:8014158c r4:eebae640
> > Mar 20 18:15:23 GE00409729044C kernel: ---[ end trace ba005811962ba6f2 ]---
> >
> > We believe this may be due to the vblank interrupt for the LVDS interface
> > being affected when the vblank interface for the HDMI backed interface
> > gets enabled. Any pointers regarding how to proceed narrowing down/fixing
> > this would be appreciated.
> >
> > We are currently running 4.8 kernel with 1.11 Weston compositor.
> >
> > Martyn
>
> Could you move to v4.9 or v4.10 and check if the four patches in
> https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> or
> https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> help?
>
I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
the error, though we are unfortunately still experiencing the loss of
output on LVDS display. Time to look elsewhere for the cause of that I
guess. :-)
Thanks for your help,
Martyn
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-24 10:24 ` Martyn Welch
@ 2017-03-24 10:42 ` Philipp Zabel
2017-03-27 11:11 ` Martyn Welch
0 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2017-03-24 10:42 UTC (permalink / raw)
To: Martyn Welch; +Cc: dri-devel
On Fri, 2017-03-24 at 10:24 +0000, Martyn Welch wrote:
[...]
> > Could you move to v4.9 or v4.10 and check if the four patches in
> > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> > or
> > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> > help?
> >
>
> I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
> the error, though we are unfortunately still experiencing the loss of
> output on LVDS display. Time to look elsewhere for the cause of that I
> guess. :-)
Is the LVDS serial clock derived from the video PLL on that board?
(What is the output of /sys/kernel/debug/clk/clk_summary?)
If you are driving high resolution displays from the same IPU, this
could also be a bandwidth issue. Maybe try severing the ipu1->hdmi and
ipu2->ldb links in the device tree as done in imx6q-utilite-pro.dts.
regards
Philipp
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-24 10:42 ` Philipp Zabel
@ 2017-03-27 11:11 ` Martyn Welch
2017-03-28 10:49 ` Martyn Welch
0 siblings, 1 reply; 10+ messages in thread
From: Martyn Welch @ 2017-03-27 11:11 UTC (permalink / raw)
To: Philipp Zabel; +Cc: dri-devel
On Fri, Mar 24, 2017 at 11:42:53AM +0100, Philipp Zabel wrote:
> On Fri, 2017-03-24 at 10:24 +0000, Martyn Welch wrote:
> [...]
> > > Could you move to v4.9 or v4.10 and check if the four patches in
> > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> > > or
> > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> > > help?
> > >
> >
> > I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
> > the error, though we are unfortunately still experiencing the loss of
> > output on LVDS display. Time to look elsewhere for the cause of that I
> > guess. :-)
>
> Is the LVDS serial clock derived from the video PLL on that board?
> (What is the output of /sys/kernel/debug/clk/clk_summary?)
>
I beleive so. I've included a few dumps from clk_summary below.
> If you are driving high resolution displays from the same IPU, this
> could also be a bandwidth issue. Maybe try severing the ipu1->hdmi and
> ipu2->ldb links in the device tree as done in imx6q-utilite-pro.dts.
>
This didn't help. Both displays work if either both are plugged in from
boot or the HDMI display is plugged in prior to boot (the LVDS display
can then be plugged in post-boot).
One thing I did notice is that the clock values differ quite a lot when
the LVDS display is plugged in from boot and the HDMI display is plugged
in post-boot. Booting with both displays connected, or booting with the
HDMI display connected and plugging in the LVDS display post-boot result
in matching clock values.
Here are the output of clk_summary for each state:
HDMI attached pre boot, LVDS attached pre boot:
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
anaclk2 0 0 0 0 0
lvds2_in 0 0 0 0 0
anaclk1 0 0 0 0 0
lvds1_in 0 0 0 0 0
dummy 3 3 0 0 0
lvds2_sel 0 0 0 0 0
lvds2_gate 0 0 0 0 0
usbphy2_gate 1 1 0 0 0
usbphy1_gate 1 1 0 0 0
clock 1 1 22000000 0 0
osc 7 7 24000000 0 0
cko2_sel 0 0 24000000 0 0
cko2_podf 0 0 24000000 0 0
cko2 0 0 24000000 0 0
cko 0 0 24000000 0 0
periph_clk2_sel 0 0 24000000 0 0
periph_clk2 0 0 24000000 0 0
gpt_3m 1 1 3000000 0 0
pll7 1 1 480000000 0 0
pll7_bypass 1 1 480000000 0 0
pll7_usb_host 1 1 480000000 0 0
usbphy2 1 1 480000000 0 0
pll6 1 1 500000000 0 0
pll6_bypass 1 1 500000000 0 0
pll6_enet 3 3 500000000 0 0
enet_ref 1 1 50000000 0 0
pcie_ref 1 1 125000000 0 0
pcie_ref_125m 1 1 125000000 0 0
sata_ref 1 1 100000000 0 0
sata_ref_100m 1 1 100000000 0 0
lvds1_sel 1 1 100000000 0 0
lvds1_gate 1 1 100000000 0 0
pll5 1 1 756000000 0 0
pll5_bypass 1 1 756000000 0 0
pll5_video 1 1 756000000 0 0
pll5_post_div 1 1 378000000 0 0
pll5_video_div 2 2 378000000 0 0
ipu2_di1_pre_sel 0 0 378000000 0 0
ipu2_di1_pre 0 0 126000000 0 0
ipu2_di1_sel 0 0 126000000 0 0
ipu2_di1 0 0 126000000 0 0
ipu2_di0_pre_sel 0 0 378000000 0 0
ipu2_di0_pre 0 0 126000000 0 0
ldb_di1_sel 1 1 378000000 0 0
ldb_di1_div_3_5 1 1 108000000 0 0
ldb_di1_podf 1 1 108000000 0 0
ldb_di1 2 2 108000000 0 0
ipu2_di0_sel 1 1 108000000 0 0
ipu2_di0 1 1 108000000 0 0
ldb_di0_sel 1 1 378000000 0 0
ldb_di0_div_3_5 1 1 108000000 0 0
ldb_di0_podf 1 1 108000000 0 0
ldb_di0 1 1 108000000 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
pll4_post_div 0 0 36864000 0 0
pll4_audio_div 0 0 36864000 0 0
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 5 6 480000000 0 0
gpu2d_core_sel 1 1 480000000 0 0
gpu2d_core_podf 1 1 480000000 0 0
gpu2d_core 2 2 480000000 0 0
asrc_sel 0 0 480000000 0 0
asrc_pred 0 0 240000000 0 0
asrc_podf 0 0 30000000 0 0
asrc 0 0 30000000 0 0
esai_sel 0 0 480000000 0 0
esai_pred 0 0 240000000 0 0
esai_podf 0 0 30000000 0 0
esai_extal 0 0 30000000 0 0
periph2_clk2_sel 0 0 480000000 0 0
periph2_clk2 0 0 480000000 0 0
pll3_60m 0 1 60000000 0 0
can_root 0 0 30000000 0 0
can2_serial 0 0 30000000 0 0
can1_serial 0 0 30000000 0 0
ecspi_root 0 2 60000000 0 0
ecspi5 0 2 60000000 0 0
ecspi4 0 0 60000000 0 0
ecspi3 0 0 60000000 0 0
ecspi2 0 0 60000000 0 0
ecspi1 0 2 60000000 0 0
pll3_80m 1 1 80000000 0 0
uart_serial_podf 1 1 80000000 0 0
uart_serial 1 2 80000000 0 0
pll3_120m 0 0 120000000 0 0
pll3_pfd3_454m 0 0 454736842 0 0
spdif_sel 0 0 454736842 0 0
spdif_pred 0 0 227368421 0 0
spdif_podf 0 0 28421053 0 0
spdif 0 0 28421053 0 0
pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0
ssi1_sel 0 0 508235294 0 0
ssi1_pred 0 0 127058824 0 0
ssi1_podf 0 0 63529412 0 0
ssi1 0 0 63529412 0 0
pll3_pfd1_540m 1 1 540000000 0 0
video_27m 1 1 27000000 0 0
mipi_core_cfg 0 0 27000000 0 0
hdmi_isfr 1 1 27000000 0 0
pll3_pfd0_720m 0 0 720000000 0 0
usbphy1 1 1 480000000 0 0
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 0 0 528000000 0 0
periph2 0 0 528000000 0 0
mmdc_ch1_axi_podf 0 0 528000000 0 0
mmdc_ch1_axi 0 0 528000000 0 0
periph_pre 1 1 528000000 0 0
periph 3 3 528000000 0 0
ahb 6 6 132000000 0 0
sdma 12 2 132000000 0 0
sata 1 1 132000000 0 0
rom 1 1 132000000 0 0
ocram 1 1 132000000 0 0
hdmi_iahb 1 1 132000000 0 0
esai_mem 0 0 132000000 0 0
esai_ipg 0 0 132000000 0 0
caam_aclk 0 0 132000000 0 0
caam_mem 0 0 132000000 0 0
asrc_mem 0 0 132000000 0 0
asrc_ipg 0 0 132000000 0 0
cko1_sel 0 0 132000000 0 0
cko1_podf 0 0 16500000 0 0
cko1 0 0 16500000 0 0
ipg 6 6 66000000 0 0
usboh3 2 2 66000000 0 0
uart_ipg 1 2 66000000 0 0
ssi3_ipg 0 0 66000000 0 0
ssi2_ipg 0 0 66000000 0 0
ssi1_ipg 1 2 66000000 0 0
spdif_gclk 0 0 66000000 0 0
spba 0 0 66000000 0 0
mipi_ipg 0 0 66000000 0 0
iim 0 0 66000000 0 0
gpt_ipg 1 1 66000000 0 0
enet 2 2 66000000 0 0
can2_ipg 0 0 66000000 0 0
can1_ipg 0 0 66000000 0 0
caam_ipg 0 0 66000000 0 0
ipg_per 4 4 66000000 0 0
pwm4 0 0 66000000 0 0
pwm3 0 0 66000000 0 0
pwm2 0 0 66000000 0 0
pwm1 1 1 66000000 0 0
i2c3 1 1 66000000 0 0
i2c2 1 1 66000000 0 0
i2c1 1 1 66000000 0 0
gpt_ipg_per 0 0 66000000 0 0
mmdc_ch0_axi_podf 1 1 528000000 0 0
mmdc_ch0_axi 4 4 528000000 0 0
gpu3d_core_sel 1 1 528000000 0 0
gpu3d_core_podf 1 1 528000000 0 0
gpu3d_core 1 1 528000000 0 0
ipu1_sel 1 1 528000000 0 0
ipu1_podf 1 1 264000000 0 0
ipu1 1 1 264000000 0 0
ipu2_sel 1 1 528000000 0 0
ipu2_podf 1 1 264000000 0 0
ipu2 1 1 264000000 0 0
axi_sel 1 1 528000000 0 0
axi 4 4 264000000 0 0
openvg_axi 1 1 264000000 0 0
mlb 0 0 264000000 0 0
gpu2d_axi 1 1 264000000 0 0
gpu3d_axi 1 1 264000000 0 0
pcie_axi_sel 1 1 264000000 0 0
pcie_axi 1 1 264000000 0 0
eim_slow_sel 0 0 264000000 0 0
eim_slow_podf 0 0 132000000 0 0
eim_slow 0 0 132000000 0 0
vdo_axi_sel 0 0 264000000 0 0
vdo_axi 0 0 264000000 0 0
vdoa 0 0 264000000 0 0
vpu_axi_sel 0 0 264000000 0 0
vpu_axi_podf 0 0 264000000 0 0
vpu_axi 0 0 264000000 0 0
pll2_pfd2_396m 3 3 432000000 0 0
ipu1_di1_pre_sel 0 0 432000000 0 0
ipu1_di1_pre 0 0 144000000 0 0
ipu1_di1_sel 0 0 144000000 0 0
ipu1_di1 0 0 144000000 0 0
ipu1_di0_pre_sel 1 1 432000000 0 0
ipu1_di0_pre 1 1 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
enfc_sel 0 0 432000000 0 0
enfc_pred 0 0 86400000 0 0
enfc_podf 0 0 21600000 0 0
enfc 0 0 21600000 0 0
gpmi_io 0 0 21600000 0 0
eim_sel 0 0 432000000 0 0
eim_podf 0 0 216000000 0 0
usdhc4_sel 1 1 432000000 0 0
usdhc4_podf 1 1 216000000 0 0
usdhc4 3 3 216000000 0 0
gpmi_bch 0 0 216000000 0 0
usdhc3_sel 1 1 432000000 0 0
usdhc3_podf 1 1 216000000 0 0
usdhc3 3 3 216000000 0 0
apbh_dma 0 0 216000000 0 0
per1_bch 0 0 216000000 0 0
gpmi_bch_apb 0 0 216000000 0 0
gpmi_apb 0 0 216000000 0 0
usdhc2_sel 0 0 432000000 0 0
usdhc2_podf 0 0 216000000 0 0
usdhc2 0 0 216000000 0 0
usdhc1_sel 0 0 432000000 0 0
usdhc1_podf 0 0 216000000 0 0
usdhc1 0 0 216000000 0 0
hsi_tx_sel 0 0 432000000 0 0
hsi_tx_podf 0 0 216000000 0 0
hsi_tx 0 0 216000000 0 0
step 0 0 432000000 0 0
pll2_198m 0 0 216000000 0 0
pll2_pfd1_594m 1 1 594000000 0 0
gpu3d_shader_sel 1 1 594000000 0 0
gpu3d_shader 1 1 594000000 0 0
pll2_pfd0_352m 0 0 352000000 0 0
pll1 1 1 996000000 0 0
pll1_bypass 1 1 996000000 0 0
pll1_sys 1 1 996000000 0 0
pll1_sw 1 1 996000000 0 0
arm 2 2 996000000 0 0
twd 1 1 498000000 0 0
pll7_bypass_src 0 0 24000000 0 0
pll6_bypass_src 0 0 24000000 0 0
pll5_bypass_src 0 0 24000000 0 0
pll4_bypass_src 0 0 24000000 0 0
pll3_bypass_src 0 0 24000000 0 0
pll2_bypass_src 0 0 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
ckih1 0 0 0 0 0
ckil 0 0 32768 0 0
HDMI attached pre boot, no LVDS:
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
anaclk2 0 0 0 0 0
lvds2_in 0 0 0 0 0
anaclk1 0 0 0 0 0
lvds1_in 0 0 0 0 0
dummy 3 3 0 0 0
lvds2_sel 0 0 0 0 0
lvds2_gate 0 0 0 0 0
usbphy2_gate 1 1 0 0 0
usbphy1_gate 1 1 0 0 0
clock 1 1 22000000 0 0
osc 6 6 24000000 0 0
cko2_sel 0 0 24000000 0 0
cko2_podf 0 0 24000000 0 0
cko2 0 0 24000000 0 0
cko 0 0 24000000 0 0
periph_clk2_sel 0 0 24000000 0 0
periph_clk2 0 0 24000000 0 0
gpt_3m 1 1 3000000 0 0
pll7 1 1 480000000 0 0
pll7_bypass 1 1 480000000 0 0
pll7_usb_host 1 1 480000000 0 0
usbphy2 1 1 480000000 0 0
pll6 1 1 500000000 0 0
pll6_bypass 1 1 500000000 0 0
pll6_enet 3 3 500000000 0 0
enet_ref 1 1 50000000 0 0
pcie_ref 1 1 125000000 0 0
pcie_ref_125m 1 1 125000000 0 0
sata_ref 1 1 100000000 0 0
sata_ref_100m 1 1 100000000 0 0
lvds1_sel 1 1 100000000 0 0
lvds1_gate 1 1 100000000 0 0
pll5 0 0 296600000 0 0
pll5_bypass 0 0 296600000 0 0
pll5_video 0 0 296600000 0 0
pll5_post_div 0 0 74150000 0 0
pll5_video_div 0 0 74150000 0 0
ipu2_di1_pre_sel 0 0 74150000 0 0
ipu2_di1_pre 0 0 24716667 0 0
ipu2_di1_sel 0 0 24716667 0 0
ipu2_di1 0 0 24716667 0 0
ipu2_di0_pre_sel 0 0 74150000 0 0
ipu2_di0_pre 0 0 24716667 0 0
ipu2_di0_sel 0 0 24716667 0 0
ipu2_di0 0 0 24716667 0 0
ldb_di1_sel 0 0 74150000 0 0
ldb_di1_div_3_5 0 0 21185714 0 0
ldb_di1_podf 0 0 10592857 0 0
ldb_di1 0 0 10592857 0 0
ldb_di0_sel 0 0 74150000 0 0
ldb_di0_div_3_5 0 0 21185714 0 0
ldb_di0_podf 0 0 10592857 0 0
ldb_di0 0 0 10592857 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
pll4_post_div 0 0 36864000 0 0
pll4_audio_div 0 0 36864000 0 0
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 5 6 480000000 0 0
gpu2d_core_sel 1 1 480000000 0 0
gpu2d_core_podf 1 1 480000000 0 0
gpu2d_core 2 2 480000000 0 0
asrc_sel 0 0 480000000 0 0
asrc_pred 0 0 240000000 0 0
asrc_podf 0 0 30000000 0 0
asrc 0 0 30000000 0 0
esai_sel 0 0 480000000 0 0
esai_pred 0 0 240000000 0 0
esai_podf 0 0 30000000 0 0
esai_extal 0 0 30000000 0 0
periph2_clk2_sel 0 0 480000000 0 0
periph2_clk2 0 0 480000000 0 0
pll3_60m 0 1 60000000 0 0
can_root 0 0 30000000 0 0
can2_serial 0 0 30000000 0 0
can1_serial 0 0 30000000 0 0
ecspi_root 0 2 60000000 0 0
ecspi5 0 2 60000000 0 0
ecspi4 0 0 60000000 0 0
ecspi3 0 0 60000000 0 0
ecspi2 0 0 60000000 0 0
ecspi1 0 2 60000000 0 0
pll3_80m 1 1 80000000 0 0
uart_serial_podf 1 1 80000000 0 0
uart_serial 1 2 80000000 0 0
pll3_120m 0 0 120000000 0 0
pll3_pfd3_454m 0 0 454736842 0 0
spdif_sel 0 0 454736842 0 0
spdif_pred 0 0 227368421 0 0
spdif_podf 0 0 28421053 0 0
spdif 0 0 28421053 0 0
pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0
ssi1_sel 0 0 508235294 0 0
ssi1_pred 0 0 127058824 0 0
ssi1_podf 0 0 63529412 0 0
ssi1 0 0 63529412 0 0
pll3_pfd1_540m 1 1 540000000 0 0
video_27m 1 1 27000000 0 0
mipi_core_cfg 0 0 27000000 0 0
hdmi_isfr 1 1 27000000 0 0
pll3_pfd0_720m 0 0 720000000 0 0
usbphy1 1 1 480000000 0 0
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 0 0 528000000 0 0
periph2 0 0 528000000 0 0
mmdc_ch1_axi_podf 0 0 528000000 0 0
mmdc_ch1_axi 0 0 528000000 0 0
periph_pre 1 1 528000000 0 0
periph 3 3 528000000 0 0
ahb 6 6 132000000 0 0
sdma 12 2 132000000 0 0
sata 1 1 132000000 0 0
rom 1 1 132000000 0 0
ocram 1 1 132000000 0 0
hdmi_iahb 1 1 132000000 0 0
esai_mem 0 0 132000000 0 0
esai_ipg 0 0 132000000 0 0
caam_aclk 0 0 132000000 0 0
caam_mem 0 0 132000000 0 0
asrc_mem 0 0 132000000 0 0
asrc_ipg 0 0 132000000 0 0
cko1_sel 0 0 132000000 0 0
cko1_podf 0 0 16500000 0 0
cko1 0 0 16500000 0 0
ipg 6 6 66000000 0 0
usboh3 2 2 66000000 0 0
uart_ipg 1 2 66000000 0 0
ssi3_ipg 0 0 66000000 0 0
ssi2_ipg 0 0 66000000 0 0
ssi1_ipg 1 2 66000000 0 0
spdif_gclk 0 0 66000000 0 0
spba 0 0 66000000 0 0
mipi_ipg 0 0 66000000 0 0
iim 0 0 66000000 0 0
gpt_ipg 1 1 66000000 0 0
enet 2 2 66000000 0 0
can2_ipg 0 0 66000000 0 0
can1_ipg 0 0 66000000 0 0
caam_ipg 0 0 66000000 0 0
ipg_per 4 4 66000000 0 0
pwm4 0 0 66000000 0 0
pwm3 0 0 66000000 0 0
pwm2 0 0 66000000 0 0
pwm1 1 1 66000000 0 0
i2c3 1 1 66000000 0 0
i2c2 1 1 66000000 0 0
i2c1 1 1 66000000 0 0
gpt_ipg_per 0 0 66000000 0 0
mmdc_ch0_axi_podf 1 1 528000000 0 0
mmdc_ch0_axi 4 4 528000000 0 0
gpu3d_core_sel 1 1 528000000 0 0
gpu3d_core_podf 1 1 528000000 0 0
gpu3d_core 1 1 528000000 0 0
ipu1_sel 1 1 528000000 0 0
ipu1_podf 1 1 264000000 0 0
ipu1 1 1 264000000 0 0
ipu2_sel 1 1 528000000 0 0
ipu2_podf 1 1 264000000 0 0
ipu2 1 1 264000000 0 0
axi_sel 1 1 528000000 0 0
axi 4 4 264000000 0 0
openvg_axi 1 1 264000000 0 0
mlb 0 0 264000000 0 0
gpu2d_axi 1 1 264000000 0 0
gpu3d_axi 1 1 264000000 0 0
pcie_axi_sel 1 1 264000000 0 0
pcie_axi 1 1 264000000 0 0
eim_slow_sel 0 0 264000000 0 0
eim_slow_podf 0 0 132000000 0 0
eim_slow 0 0 132000000 0 0
vdo_axi_sel 0 0 264000000 0 0
vdo_axi 0 0 264000000 0 0
vdoa 0 0 264000000 0 0
vpu_axi_sel 0 0 264000000 0 0
vpu_axi_podf 0 0 264000000 0 0
vpu_axi 0 0 264000000 0 0
pll2_pfd2_396m 3 3 432000000 0 0
ipu1_di1_pre_sel 0 0 432000000 0 0
ipu1_di1_pre 0 0 144000000 0 0
ipu1_di1_sel 0 0 144000000 0 0
ipu1_di1 0 0 144000000 0 0
ipu1_di0_pre_sel 1 1 432000000 0 0
ipu1_di0_pre 1 1 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
enfc_sel 0 0 432000000 0 0
enfc_pred 0 0 86400000 0 0
enfc_podf 0 0 21600000 0 0
enfc 0 0 21600000 0 0
gpmi_io 0 0 21600000 0 0
eim_sel 0 0 432000000 0 0
eim_podf 0 0 216000000 0 0
usdhc4_sel 1 1 432000000 0 0
usdhc4_podf 1 1 216000000 0 0
usdhc4 3 3 216000000 0 0
gpmi_bch 0 0 216000000 0 0
usdhc3_sel 1 1 432000000 0 0
usdhc3_podf 1 1 216000000 0 0
usdhc3 3 3 216000000 0 0
apbh_dma 0 0 216000000 0 0
per1_bch 0 0 216000000 0 0
gpmi_bch_apb 0 0 216000000 0 0
gpmi_apb 0 0 216000000 0 0
usdhc2_sel 0 0 432000000 0 0
usdhc2_podf 0 0 216000000 0 0
usdhc2 0 0 216000000 0 0
usdhc1_sel 0 0 432000000 0 0
usdhc1_podf 0 0 216000000 0 0
usdhc1 0 0 216000000 0 0
hsi_tx_sel 0 0 432000000 0 0
hsi_tx_podf 0 0 216000000 0 0
hsi_tx 0 0 216000000 0 0
step 0 0 432000000 0 0
pll2_198m 0 0 216000000 0 0
pll2_pfd1_594m 1 1 594000000 0 0
gpu3d_shader_sel 1 1 594000000 0 0
gpu3d_shader 1 1 594000000 0 0
pll2_pfd0_352m 0 0 352000000 0 0
pll1 1 1 996000000 0 0
pll1_bypass 1 1 996000000 0 0
pll1_sys 1 1 996000000 0 0
pll1_sw 1 1 996000000 0 0
arm 2 2 996000000 0 0
twd 1 1 498000000 0 0
pll7_bypass_src 0 0 24000000 0 0
pll6_bypass_src 0 0 24000000 0 0
pll5_bypass_src 0 0 24000000 0 0
pll4_bypass_src 0 0 24000000 0 0
pll3_bypass_src 0 0 24000000 0 0
pll2_bypass_src 0 0 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
ckih1 0 0 0 0 0
ckil 0 0 32768 0 0
HDMI attached pre boot, LVDS attached after boot:
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
anaclk2 0 0 0 0 0
lvds2_in 0 0 0 0 0
anaclk1 0 0 0 0 0
lvds1_in 0 0 0 0 0
dummy 3 3 0 0 0
lvds2_sel 0 0 0 0 0
lvds2_gate 0 0 0 0 0
usbphy2_gate 1 1 0 0 0
usbphy1_gate 1 1 0 0 0
clock 1 1 22000000 0 0
osc 7 7 24000000 0 0
cko2_sel 0 0 24000000 0 0
cko2_podf 0 0 24000000 0 0
cko2 0 0 24000000 0 0
cko 0 0 24000000 0 0
periph_clk2_sel 0 0 24000000 0 0
periph_clk2 0 0 24000000 0 0
gpt_3m 1 1 3000000 0 0
pll7 1 1 480000000 0 0
pll7_bypass 1 1 480000000 0 0
pll7_usb_host 1 1 480000000 0 0
usbphy2 1 1 480000000 0 0
pll6 1 1 500000000 0 0
pll6_bypass 1 1 500000000 0 0
pll6_enet 3 3 500000000 0 0
enet_ref 1 1 50000000 0 0
pcie_ref 1 1 125000000 0 0
pcie_ref_125m 1 1 125000000 0 0
sata_ref 1 1 100000000 0 0
sata_ref_100m 1 1 100000000 0 0
lvds1_sel 1 1 100000000 0 0
lvds1_gate 1 1 100000000 0 0
pll5 1 1 756000000 0 0
pll5_bypass 1 1 756000000 0 0
pll5_video 1 1 756000000 0 0
pll5_post_div 1 1 378000000 0 0
pll5_video_div 2 2 378000000 0 0
ipu2_di1_pre_sel 0 0 378000000 0 0
ipu2_di1_pre 0 0 126000000 0 0
ipu2_di1_sel 0 0 126000000 0 0
ipu2_di1 0 0 126000000 0 0
ipu2_di0_pre_sel 0 0 378000000 0 0
ipu2_di0_pre 0 0 126000000 0 0
ldb_di1_sel 1 1 378000000 0 0
ldb_di1_div_3_5 1 1 108000000 0 0
ldb_di1_podf 1 1 108000000 0 0
ldb_di1 2 2 108000000 0 0
ipu2_di0_sel 1 1 108000000 0 0
ipu2_di0 1 1 108000000 0 0
ldb_di0_sel 1 1 378000000 0 0
ldb_di0_div_3_5 1 1 108000000 0 0
ldb_di0_podf 1 1 108000000 0 0
ldb_di0 1 1 108000000 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
pll4_post_div 0 0 36864000 0 0
pll4_audio_div 0 0 36864000 0 0
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 5 6 480000000 0 0
gpu2d_core_sel 1 1 480000000 0 0
gpu2d_core_podf 1 1 480000000 0 0
gpu2d_core 2 2 480000000 0 0
asrc_sel 0 0 480000000 0 0
asrc_pred 0 0 240000000 0 0
asrc_podf 0 0 30000000 0 0
asrc 0 0 30000000 0 0
esai_sel 0 0 480000000 0 0
esai_pred 0 0 240000000 0 0
esai_podf 0 0 30000000 0 0
esai_extal 0 0 30000000 0 0
periph2_clk2_sel 0 0 480000000 0 0
periph2_clk2 0 0 480000000 0 0
pll3_60m 0 1 60000000 0 0
can_root 0 0 30000000 0 0
can2_serial 0 0 30000000 0 0
can1_serial 0 0 30000000 0 0
ecspi_root 0 2 60000000 0 0
ecspi5 0 2 60000000 0 0
ecspi4 0 0 60000000 0 0
ecspi3 0 0 60000000 0 0
ecspi2 0 0 60000000 0 0
ecspi1 0 2 60000000 0 0
pll3_80m 1 1 80000000 0 0
uart_serial_podf 1 1 80000000 0 0
uart_serial 1 2 80000000 0 0
pll3_120m 0 0 120000000 0 0
pll3_pfd3_454m 0 0 454736842 0 0
spdif_sel 0 0 454736842 0 0
spdif_pred 0 0 227368421 0 0
spdif_podf 0 0 28421053 0 0
spdif 0 0 28421053 0 0
pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0
ssi1_sel 0 0 508235294 0 0
ssi1_pred 0 0 127058824 0 0
ssi1_podf 0 0 63529412 0 0
ssi1 0 0 63529412 0 0
pll3_pfd1_540m 1 1 540000000 0 0
video_27m 1 1 27000000 0 0
mipi_core_cfg 0 0 27000000 0 0
hdmi_isfr 1 1 27000000 0 0
pll3_pfd0_720m 0 0 720000000 0 0
usbphy1 1 1 480000000 0 0
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 0 0 528000000 0 0
periph2 0 0 528000000 0 0
mmdc_ch1_axi_podf 0 0 528000000 0 0
mmdc_ch1_axi 0 0 528000000 0 0
periph_pre 1 1 528000000 0 0
periph 3 3 528000000 0 0
ahb 6 6 132000000 0 0
sdma 12 2 132000000 0 0
sata 1 1 132000000 0 0
rom 1 1 132000000 0 0
ocram 1 1 132000000 0 0
hdmi_iahb 1 1 132000000 0 0
esai_mem 0 0 132000000 0 0
esai_ipg 0 0 132000000 0 0
caam_aclk 0 0 132000000 0 0
caam_mem 0 0 132000000 0 0
asrc_mem 0 0 132000000 0 0
asrc_ipg 0 0 132000000 0 0
cko1_sel 0 0 132000000 0 0
cko1_podf 0 0 16500000 0 0
cko1 0 0 16500000 0 0
ipg 6 6 66000000 0 0
usboh3 2 2 66000000 0 0
uart_ipg 1 2 66000000 0 0
ssi3_ipg 0 0 66000000 0 0
ssi2_ipg 0 0 66000000 0 0
ssi1_ipg 1 2 66000000 0 0
spdif_gclk 0 0 66000000 0 0
spba 0 0 66000000 0 0
mipi_ipg 0 0 66000000 0 0
iim 0 0 66000000 0 0
gpt_ipg 1 1 66000000 0 0
enet 2 2 66000000 0 0
can2_ipg 0 0 66000000 0 0
can1_ipg 0 0 66000000 0 0
caam_ipg 0 0 66000000 0 0
ipg_per 4 4 66000000 0 0
pwm4 0 0 66000000 0 0
pwm3 0 0 66000000 0 0
pwm2 0 0 66000000 0 0
pwm1 1 1 66000000 0 0
i2c3 1 1 66000000 0 0
i2c2 1 1 66000000 0 0
i2c1 1 1 66000000 0 0
gpt_ipg_per 0 0 66000000 0 0
mmdc_ch0_axi_podf 1 1 528000000 0 0
mmdc_ch0_axi 4 4 528000000 0 0
gpu3d_core_sel 1 1 528000000 0 0
gpu3d_core_podf 1 1 528000000 0 0
gpu3d_core 1 1 528000000 0 0
ipu1_sel 1 1 528000000 0 0
ipu1_podf 1 1 264000000 0 0
ipu1 1 1 264000000 0 0
ipu2_sel 1 1 528000000 0 0
ipu2_podf 1 1 264000000 0 0
ipu2 1 1 264000000 0 0
axi_sel 1 1 528000000 0 0
axi 4 4 264000000 0 0
openvg_axi 1 1 264000000 0 0
mlb 0 0 264000000 0 0
gpu2d_axi 1 1 264000000 0 0
gpu3d_axi 1 1 264000000 0 0
pcie_axi_sel 1 1 264000000 0 0
pcie_axi 1 1 264000000 0 0
eim_slow_sel 0 0 264000000 0 0
eim_slow_podf 0 0 132000000 0 0
eim_slow 0 0 132000000 0 0
vdo_axi_sel 0 0 264000000 0 0
vdo_axi 0 0 264000000 0 0
vdoa 0 0 264000000 0 0
vpu_axi_sel 0 0 264000000 0 0
vpu_axi_podf 0 0 264000000 0 0
vpu_axi 0 0 264000000 0 0
pll2_pfd2_396m 3 3 432000000 0 0
ipu1_di1_pre_sel 0 0 432000000 0 0
ipu1_di1_pre 0 0 144000000 0 0
ipu1_di1_sel 0 0 144000000 0 0
ipu1_di1 0 0 144000000 0 0
ipu1_di0_pre_sel 1 1 432000000 0 0
ipu1_di0_pre 1 1 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
enfc_sel 0 0 432000000 0 0
enfc_pred 0 0 86400000 0 0
enfc_podf 0 0 21600000 0 0
enfc 0 0 21600000 0 0
gpmi_io 0 0 21600000 0 0
eim_sel 0 0 432000000 0 0
eim_podf 0 0 216000000 0 0
usdhc4_sel 1 1 432000000 0 0
usdhc4_podf 1 1 216000000 0 0
usdhc4 3 3 216000000 0 0
gpmi_bch 0 0 216000000 0 0
usdhc3_sel 1 1 432000000 0 0
usdhc3_podf 1 1 216000000 0 0
usdhc3 3 3 216000000 0 0
apbh_dma 0 0 216000000 0 0
per1_bch 0 0 216000000 0 0
gpmi_bch_apb 0 0 216000000 0 0
gpmi_apb 0 0 216000000 0 0
usdhc2_sel 0 0 432000000 0 0
usdhc2_podf 0 0 216000000 0 0
usdhc2 0 0 216000000 0 0
usdhc1_sel 0 0 432000000 0 0
usdhc1_podf 0 0 216000000 0 0
usdhc1 0 0 216000000 0 0
hsi_tx_sel 0 0 432000000 0 0
hsi_tx_podf 0 0 216000000 0 0
hsi_tx 0 0 216000000 0 0
step 0 0 432000000 0 0
pll2_198m 0 0 216000000 0 0
pll2_pfd1_594m 1 1 594000000 0 0
gpu3d_shader_sel 1 1 594000000 0 0
gpu3d_shader 1 1 594000000 0 0
pll2_pfd0_352m 0 0 352000000 0 0
pll1 1 1 996000000 0 0
pll1_bypass 1 1 996000000 0 0
pll1_sys 1 1 996000000 0 0
pll1_sw 1 1 996000000 0 0
arm 2 2 996000000 0 0
twd 1 1 498000000 0 0
pll7_bypass_src 0 0 24000000 0 0
pll6_bypass_src 0 0 24000000 0 0
pll5_bypass_src 0 0 24000000 0 0
pll4_bypass_src 0 0 24000000 0 0
pll3_bypass_src 0 0 24000000 0 0
pll2_bypass_src 0 0 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
ckih1 0 0 0 0 0
ckil 0 0 32768 0 0
No HDMI, LVDS attached pre boot:
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
anaclk2 0 0 0 0 0
lvds2_in 0 0 0 0 0
anaclk1 0 0 0 0 0
lvds1_in 0 0 0 0 0
dummy 3 3 0 0 0
lvds2_sel 0 0 0 0 0
lvds2_gate 0 0 0 0 0
usbphy2_gate 1 1 0 0 0
usbphy1_gate 1 1 0 0 0
clock 1 1 22000000 0 0
osc 7 7 24000000 0 0
cko2_sel 0 0 24000000 0 0
cko2_podf 0 0 24000000 0 0
cko2 0 0 24000000 0 0
cko 0 0 24000000 0 0
periph_clk2_sel 0 0 24000000 0 0
periph_clk2 0 0 24000000 0 0
gpt_3m 1 1 3000000 0 0
pll7 1 1 480000000 0 0
pll7_bypass 1 1 480000000 0 0
pll7_usb_host 1 1 480000000 0 0
usbphy2 1 1 480000000 0 0
pll6 1 1 500000000 0 0
pll6_bypass 1 1 500000000 0 0
pll6_enet 3 3 500000000 0 0
enet_ref 1 1 50000000 0 0
pcie_ref 1 1 125000000 0 0
pcie_ref_125m 1 1 125000000 0 0
sata_ref 1 1 100000000 0 0
sata_ref_100m 1 1 100000000 0 0
lvds1_sel 1 1 100000000 0 0
lvds1_gate 1 1 100000000 0 0
pll5 1 1 756000000 0 0
pll5_bypass 1 1 756000000 0 0
pll5_video 1 1 756000000 0 0
pll5_post_div 1 1 378000000 0 0
pll5_video_div 2 2 378000000 0 0
ipu2_di1_pre_sel 0 0 378000000 0 0
ipu2_di1_pre 0 0 126000000 0 0
ipu2_di1_sel 0 0 126000000 0 0
ipu2_di1 0 0 126000000 0 0
ipu2_di0_pre_sel 0 0 378000000 0 0
ipu2_di0_pre 0 0 126000000 0 0
ipu2_di0_sel 0 0 126000000 0 0
ipu2_di0 0 0 126000000 0 0
ldb_di1_sel 1 1 378000000 0 0
ldb_di1_div_3_5 1 1 108000000 0 0
ldb_di1_podf 1 1 108000000 0 0
ldb_di1 2 2 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
ldb_di0_sel 1 1 378000000 0 0
ldb_di0_div_3_5 1 1 108000000 0 0
ldb_di0_podf 1 1 108000000 0 0
ldb_di0 1 1 108000000 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
pll4_post_div 0 0 36864000 0 0
pll4_audio_div 0 0 36864000 0 0
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 5 6 480000000 0 0
gpu2d_core_sel 1 1 480000000 0 0
gpu2d_core_podf 1 1 480000000 0 0
gpu2d_core 2 2 480000000 0 0
asrc_sel 0 0 480000000 0 0
asrc_pred 0 0 240000000 0 0
asrc_podf 0 0 30000000 0 0
asrc 0 0 30000000 0 0
esai_sel 0 0 480000000 0 0
esai_pred 0 0 240000000 0 0
esai_podf 0 0 30000000 0 0
esai_extal 0 0 30000000 0 0
periph2_clk2_sel 0 0 480000000 0 0
periph2_clk2 0 0 480000000 0 0
pll3_60m 0 1 60000000 0 0
can_root 0 0 30000000 0 0
can2_serial 0 0 30000000 0 0
can1_serial 0 0 30000000 0 0
ecspi_root 0 2 60000000 0 0
ecspi5 0 2 60000000 0 0
ecspi4 0 0 60000000 0 0
ecspi3 0 0 60000000 0 0
ecspi2 0 0 60000000 0 0
ecspi1 0 2 60000000 0 0
pll3_80m 1 1 80000000 0 0
uart_serial_podf 1 1 80000000 0 0
uart_serial 1 2 80000000 0 0
pll3_120m 0 0 120000000 0 0
pll3_pfd3_454m 0 0 454736842 0 0
spdif_sel 0 0 454736842 0 0
spdif_pred 0 0 227368421 0 0
spdif_podf 0 0 28421053 0 0
spdif 0 0 28421053 0 0
pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0
ssi1_sel 0 0 508235294 0 0
ssi1_pred 0 0 127058824 0 0
ssi1_podf 0 0 63529412 0 0
ssi1 0 0 63529412 0 0
pll3_pfd1_540m 1 1 540000000 0 0
video_27m 1 1 27000000 0 0
mipi_core_cfg 0 0 27000000 0 0
hdmi_isfr 1 1 27000000 0 0
pll3_pfd0_720m 0 0 720000000 0 0
usbphy1 1 1 480000000 0 0
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 0 0 528000000 0 0
periph2 0 0 528000000 0 0
mmdc_ch1_axi_podf 0 0 528000000 0 0
mmdc_ch1_axi 0 0 528000000 0 0
periph_pre 1 1 528000000 0 0
periph 3 3 528000000 0 0
ahb 6 6 132000000 0 0
sdma 12 2 132000000 0 0
sata 1 1 132000000 0 0
rom 1 1 132000000 0 0
ocram 1 1 132000000 0 0
hdmi_iahb 1 1 132000000 0 0
esai_mem 0 0 132000000 0 0
esai_ipg 0 0 132000000 0 0
caam_aclk 0 0 132000000 0 0
caam_mem 0 0 132000000 0 0
asrc_mem 0 0 132000000 0 0
asrc_ipg 0 0 132000000 0 0
cko1_sel 0 0 132000000 0 0
cko1_podf 0 0 16500000 0 0
cko1 0 0 16500000 0 0
ipg 6 6 66000000 0 0
usboh3 2 2 66000000 0 0
uart_ipg 1 2 66000000 0 0
ssi3_ipg 0 0 66000000 0 0
ssi2_ipg 0 0 66000000 0 0
ssi1_ipg 1 2 66000000 0 0
spdif_gclk 0 0 66000000 0 0
spba 0 0 66000000 0 0
mipi_ipg 0 0 66000000 0 0
iim 0 0 66000000 0 0
gpt_ipg 1 1 66000000 0 0
enet 2 2 66000000 0 0
can2_ipg 0 0 66000000 0 0
can1_ipg 0 0 66000000 0 0
caam_ipg 0 0 66000000 0 0
ipg_per 4 4 66000000 0 0
pwm4 0 0 66000000 0 0
pwm3 0 0 66000000 0 0
pwm2 0 0 66000000 0 0
pwm1 1 1 66000000 0 0
i2c3 1 1 66000000 0 0
i2c2 1 1 66000000 0 0
i2c1 1 1 66000000 0 0
gpt_ipg_per 0 0 66000000 0 0
mmdc_ch0_axi_podf 1 1 528000000 0 0
mmdc_ch0_axi 4 4 528000000 0 0
gpu3d_core_sel 1 1 528000000 0 0
gpu3d_core_podf 1 1 528000000 0 0
gpu3d_core 1 1 528000000 0 0
ipu1_sel 1 1 528000000 0 0
ipu1_podf 1 1 264000000 0 0
ipu1 1 1 264000000 0 0
ipu2_sel 1 1 528000000 0 0
ipu2_podf 1 1 264000000 0 0
ipu2 1 1 264000000 0 0
axi_sel 1 1 528000000 0 0
axi 4 4 264000000 0 0
openvg_axi 1 1 264000000 0 0
mlb 0 0 264000000 0 0
gpu2d_axi 1 1 264000000 0 0
gpu3d_axi 1 1 264000000 0 0
pcie_axi_sel 1 1 264000000 0 0
pcie_axi 1 1 264000000 0 0
eim_slow_sel 0 0 264000000 0 0
eim_slow_podf 0 0 132000000 0 0
eim_slow 0 0 132000000 0 0
vdo_axi_sel 0 0 264000000 0 0
vdo_axi 0 0 264000000 0 0
vdoa 0 0 264000000 0 0
vpu_axi_sel 0 0 264000000 0 0
vpu_axi_podf 0 0 264000000 0 0
vpu_axi 0 0 264000000 0 0
pll2_pfd2_396m 2 2 396000000 0 0
ipu1_di1_pre_sel 0 0 396000000 0 0
ipu1_di1_pre 0 0 132000000 0 0
ipu1_di1_sel 0 0 132000000 0 0
ipu1_di1 0 0 132000000 0 0
ipu1_di0_pre_sel 0 0 396000000 0 0
ipu1_di0_pre 0 0 132000000 0 0
enfc_sel 0 0 396000000 0 0
enfc_pred 0 0 79200000 0 0
enfc_podf 0 0 19800000 0 0
enfc 0 0 19800000 0 0
gpmi_io 0 0 19800000 0 0
eim_sel 0 0 396000000 0 0
eim_podf 0 0 198000000 0 0
usdhc4_sel 1 1 396000000 0 0
usdhc4_podf 1 1 198000000 0 0
usdhc4 3 3 198000000 0 0
gpmi_bch 0 0 198000000 0 0
usdhc3_sel 1 1 396000000 0 0
usdhc3_podf 1 1 198000000 0 0
usdhc3 3 3 198000000 0 0
apbh_dma 0 0 198000000 0 0
per1_bch 0 0 198000000 0 0
gpmi_bch_apb 0 0 198000000 0 0
gpmi_apb 0 0 198000000 0 0
usdhc2_sel 0 0 396000000 0 0
usdhc2_podf 0 0 198000000 0 0
usdhc2 0 0 198000000 0 0
usdhc1_sel 0 0 396000000 0 0
usdhc1_podf 0 0 198000000 0 0
usdhc1 0 0 198000000 0 0
hsi_tx_sel 0 0 396000000 0 0
hsi_tx_podf 0 0 198000000 0 0
hsi_tx 0 0 198000000 0 0
step 0 0 396000000 0 0
pll2_198m 0 0 198000000 0 0
pll2_pfd1_594m 1 1 594000000 0 0
gpu3d_shader_sel 1 1 594000000 0 0
gpu3d_shader 1 1 594000000 0 0
pll2_pfd0_352m 0 0 352000000 0 0
pll1 1 1 996000000 0 0
pll1_bypass 1 1 996000000 0 0
pll1_sys 1 1 996000000 0 0
pll1_sw 1 1 996000000 0 0
arm 2 2 996000000 0 0
twd 1 1 498000000 0 0
pll7_bypass_src 0 0 24000000 0 0
pll6_bypass_src 0 0 24000000 0 0
pll5_bypass_src 0 0 24000000 0 0
pll4_bypass_src 0 0 24000000 0 0
pll3_bypass_src 0 0 24000000 0 0
pll2_bypass_src 0 0 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
ckih1 0 0 0 0 0
ckil 0 0 32768 0 0
HDMI attached after boot, LVDS attached pre boot:
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
anaclk2 0 0 0 0 0
lvds2_in 0 0 0 0 0
anaclk1 0 0 0 0 0
lvds1_in 0 0 0 0 0
dummy 3 3 0 0 0
lvds2_sel 0 0 0 0 0
lvds2_gate 0 0 0 0 0
usbphy2_gate 1 1 0 0 0
usbphy1_gate 1 1 0 0 0
clock 1 1 22000000 0 0
osc 7 7 24000000 0 0
cko2_sel 0 0 24000000 0 0
cko2_podf 0 0 24000000 0 0
cko2 0 0 24000000 0 0
cko 0 0 24000000 0 0
periph_clk2_sel 0 0 24000000 0 0
periph_clk2 0 0 24000000 0 0
gpt_3m 1 1 3000000 0 0
pll7 1 1 480000000 0 0
pll7_bypass 1 1 480000000 0 0
pll7_usb_host 1 1 480000000 0 0
usbphy2 1 1 480000000 0 0
pll6 1 1 500000000 0 0
pll6_bypass 1 1 500000000 0 0
pll6_enet 3 3 500000000 0 0
enet_ref 1 1 50000000 0 0
pcie_ref 1 1 125000000 0 0
pcie_ref_125m 1 1 125000000 0 0
sata_ref 1 1 100000000 0 0
sata_ref_100m 1 1 100000000 0 0
lvds1_sel 1 1 100000000 0 0
lvds1_gate 1 1 100000000 0 0
pll5 1 1 864000000 0 0
pll5_bypass 1 1 864000000 0 0
pll5_video 1 1 864000000 0 0
pll5_post_div 1 1 216000000 0 0
pll5_video_div 3 3 108000000 0 0
ipu2_di1_pre_sel 0 0 108000000 0 0
ipu2_di1_pre 0 0 36000000 0 0
ipu2_di1_sel 0 0 36000000 0 0
ipu2_di1 0 0 36000000 0 0
ipu2_di0_pre_sel 1 1 108000000 0 0
ipu2_di0_pre 1 1 108000000 0 0
ipu2_di0_sel 1 1 108000000 0 0
ipu2_di0 1 1 108000000 0 0
ldb_di1_sel 1 1 108000000 0 0
ldb_di1_div_3_5 1 1 30857142 0 0
ldb_di1_podf 1 1 30857142 0 0
ldb_di1 2 2 30857142 0 0
ipu1_di0_sel 1 1 30857142 0 0
ipu1_di0 1 1 30857142 0 0
ldb_di0_sel 1 1 108000000 0 0
ldb_di0_div_3_5 1 1 30857142 0 0
ldb_di0_podf 1 1 30857142 0 0
ldb_di0 1 1 30857142 0 0
pll4 0 0 147456000 0 0
pll4_bypass 0 0 147456000 0 0
pll4_audio 0 0 147456000 0 0
pll4_post_div 0 0 36864000 0 0
pll4_audio_div 0 0 36864000 0 0
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 5 6 480000000 0 0
gpu2d_core_sel 1 1 480000000 0 0
gpu2d_core_podf 1 1 480000000 0 0
gpu2d_core 2 2 480000000 0 0
asrc_sel 0 0 480000000 0 0
asrc_pred 0 0 240000000 0 0
asrc_podf 0 0 30000000 0 0
asrc 0 0 30000000 0 0
esai_sel 0 0 480000000 0 0
esai_pred 0 0 240000000 0 0
esai_podf 0 0 30000000 0 0
esai_extal 0 0 30000000 0 0
periph2_clk2_sel 0 0 480000000 0 0
periph2_clk2 0 0 480000000 0 0
pll3_60m 0 1 60000000 0 0
can_root 0 0 30000000 0 0
can2_serial 0 0 30000000 0 0
can1_serial 0 0 30000000 0 0
ecspi_root 0 2 60000000 0 0
ecspi5 0 2 60000000 0 0
ecspi4 0 0 60000000 0 0
ecspi3 0 0 60000000 0 0
ecspi2 0 0 60000000 0 0
ecspi1 0 2 60000000 0 0
pll3_80m 1 1 80000000 0 0
uart_serial_podf 1 1 80000000 0 0
uart_serial 1 2 80000000 0 0
pll3_120m 0 0 120000000 0 0
pll3_pfd3_454m 0 0 454736842 0 0
spdif_sel 0 0 454736842 0 0
spdif_pred 0 0 227368421 0 0
spdif_podf 0 0 28421053 0 0
spdif 0 0 28421053 0 0
pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0
ssi1_sel 0 0 508235294 0 0
ssi1_pred 0 0 127058824 0 0
ssi1_podf 0 0 63529412 0 0
ssi1 0 0 63529412 0 0
pll3_pfd1_540m 1 1 540000000 0 0
video_27m 1 1 27000000 0 0
mipi_core_cfg 0 0 27000000 0 0
hdmi_isfr 1 1 27000000 0 0
pll3_pfd0_720m 0 0 720000000 0 0
usbphy1 1 1 480000000 0 0
pll2 1 1 528000000 0 0
pll2_bypass 1 1 528000000 0 0
pll2_bus 3 3 528000000 0 0
periph2_pre 0 0 528000000 0 0
periph2 0 0 528000000 0 0
mmdc_ch1_axi_podf 0 0 528000000 0 0
mmdc_ch1_axi 0 0 528000000 0 0
periph_pre 1 1 528000000 0 0
periph 3 3 528000000 0 0
ahb 6 6 132000000 0 0
sdma 12 2 132000000 0 0
sata 1 1 132000000 0 0
rom 1 1 132000000 0 0
ocram 1 1 132000000 0 0
hdmi_iahb 1 1 132000000 0 0
esai_mem 0 0 132000000 0 0
esai_ipg 0 0 132000000 0 0
caam_aclk 0 0 132000000 0 0
caam_mem 0 0 132000000 0 0
asrc_mem 0 0 132000000 0 0
asrc_ipg 0 0 132000000 0 0
cko1_sel 0 0 132000000 0 0
cko1_podf 0 0 16500000 0 0
cko1 0 0 16500000 0 0
ipg 6 6 66000000 0 0
usboh3 2 2 66000000 0 0
uart_ipg 1 2 66000000 0 0
ssi3_ipg 0 0 66000000 0 0
ssi2_ipg 0 0 66000000 0 0
ssi1_ipg 1 2 66000000 0 0
spdif_gclk 0 0 66000000 0 0
spba 0 0 66000000 0 0
mipi_ipg 0 0 66000000 0 0
iim 0 0 66000000 0 0
gpt_ipg 1 1 66000000 0 0
enet 2 2 66000000 0 0
can2_ipg 0 0 66000000 0 0
can1_ipg 0 0 66000000 0 0
caam_ipg 0 0 66000000 0 0
ipg_per 4 4 66000000 0 0
pwm4 0 0 66000000 0 0
pwm3 0 0 66000000 0 0
pwm2 0 0 66000000 0 0
pwm1 1 1 66000000 0 0
i2c3 1 1 66000000 0 0
i2c2 1 1 66000000 0 0
i2c1 1 1 66000000 0 0
gpt_ipg_per 0 0 66000000 0 0
mmdc_ch0_axi_podf 1 1 528000000 0 0
mmdc_ch0_axi 4 4 528000000 0 0
gpu3d_core_sel 1 1 528000000 0 0
gpu3d_core_podf 1 1 528000000 0 0
gpu3d_core 1 1 528000000 0 0
ipu1_sel 1 1 528000000 0 0
ipu1_podf 1 1 264000000 0 0
ipu1 1 1 264000000 0 0
ipu2_sel 1 1 528000000 0 0
ipu2_podf 1 1 264000000 0 0
ipu2 1 1 264000000 0 0
axi_sel 1 1 528000000 0 0
axi 4 4 264000000 0 0
openvg_axi 1 1 264000000 0 0
mlb 0 0 264000000 0 0
gpu2d_axi 1 1 264000000 0 0
gpu3d_axi 1 1 264000000 0 0
pcie_axi_sel 1 1 264000000 0 0
pcie_axi 1 1 264000000 0 0
eim_slow_sel 0 0 264000000 0 0
eim_slow_podf 0 0 132000000 0 0
eim_slow 0 0 132000000 0 0
vdo_axi_sel 0 0 264000000 0 0
vdo_axi 0 0 264000000 0 0
vdoa 0 0 264000000 0 0
vpu_axi_sel 0 0 264000000 0 0
vpu_axi_podf 0 0 264000000 0 0
vpu_axi 0 0 264000000 0 0
pll2_pfd2_396m 2 2 396000000 0 0
ipu1_di1_pre_sel 0 0 396000000 0 0
ipu1_di1_pre 0 0 132000000 0 0
ipu1_di1_sel 0 0 132000000 0 0
ipu1_di1 0 0 132000000 0 0
ipu1_di0_pre_sel 0 0 396000000 0 0
ipu1_di0_pre 0 0 132000000 0 0
enfc_sel 0 0 396000000 0 0
enfc_pred 0 0 79200000 0 0
enfc_podf 0 0 19800000 0 0
enfc 0 0 19800000 0 0
gpmi_io 0 0 19800000 0 0
eim_sel 0 0 396000000 0 0
eim_podf 0 0 198000000 0 0
usdhc4_sel 1 1 396000000 0 0
usdhc4_podf 1 1 198000000 0 0
usdhc4 3 3 198000000 0 0
gpmi_bch 0 0 198000000 0 0
usdhc3_sel 1 1 396000000 0 0
usdhc3_podf 1 1 198000000 0 0
usdhc3 3 3 198000000 0 0
apbh_dma 0 0 198000000 0 0
per1_bch 0 0 198000000 0 0
gpmi_bch_apb 0 0 198000000 0 0
gpmi_apb 0 0 198000000 0 0
usdhc2_sel 0 0 396000000 0 0
usdhc2_podf 0 0 198000000 0 0
usdhc2 0 0 198000000 0 0
usdhc1_sel 0 0 396000000 0 0
usdhc1_podf 0 0 198000000 0 0
usdhc1 0 0 198000000 0 0
hsi_tx_sel 0 0 396000000 0 0
hsi_tx_podf 0 0 198000000 0 0
hsi_tx 0 0 198000000 0 0
step 0 0 396000000 0 0
pll2_198m 0 0 198000000 0 0
pll2_pfd1_594m 1 1 594000000 0 0
gpu3d_shader_sel 1 1 594000000 0 0
gpu3d_shader 1 1 594000000 0 0
pll2_pfd0_352m 0 0 352000000 0 0
pll1 1 1 996000000 0 0
pll1_bypass 1 1 996000000 0 0
pll1_sys 1 1 996000000 0 0
pll1_sw 1 1 996000000 0 0
arm 2 2 996000000 0 0
twd 1 1 498000000 0 0
pll7_bypass_src 0 0 24000000 0 0
pll6_bypass_src 0 0 24000000 0 0
pll5_bypass_src 0 0 24000000 0 0
pll4_bypass_src 0 0 24000000 0 0
pll3_bypass_src 0 0 24000000 0 0
pll2_bypass_src 0 0 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
ckih1 0 0 0 0 0
ckil 0 0 32768 0 0
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-27 11:11 ` Martyn Welch
@ 2017-03-28 10:49 ` Martyn Welch
2017-03-28 16:44 ` Philipp Zabel
0 siblings, 1 reply; 10+ messages in thread
From: Martyn Welch @ 2017-03-28 10:49 UTC (permalink / raw)
To: Philipp Zabel; +Cc: dri-devel
On Mon, Mar 27, 2017 at 12:11:12PM +0100, Martyn Welch wrote:
> On Fri, Mar 24, 2017 at 11:42:53AM +0100, Philipp Zabel wrote:
> > On Fri, 2017-03-24 at 10:24 +0000, Martyn Welch wrote:
> > [...]
> > > > Could you move to v4.9 or v4.10 and check if the four patches in
> > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> > > > or
> > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> > > > help?
> > > >
> > >
> > > I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
> > > the error, though we are unfortunately still experiencing the loss of
> > > output on LVDS display. Time to look elsewhere for the cause of that I
> > > guess. :-)
> >
> > Is the LVDS serial clock derived from the video PLL on that board?
> > (What is the output of /sys/kernel/debug/clk/clk_summary?)
> >
>
> I beleive so. I've included a few dumps from clk_summary below.
>
After looking at the dumps in more detail, I think I know what's
happening:
Problem appears to be a clocking issue. When we have a display connected
to the HDMI port pre-boot, it uses the following chain to drive IPU2
(which is used for this display):
PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
LDB_DI1(108000000) -> IPU2_DI0(108000000)
If the display connected via the LVDS interface is connected either
before or after boot, we end up with IPU1 being drive thus:
PLL2_PFD2(432000000) -> IPU2_DI1_PRE_CLK(432000000) ->
IPU2DI1_PODF(432000000/4) -> IPU1_DI0(108000000)
On the other hand, if only the LVDS is connected at boot, instead it is
sets up IPU1 as follows:
PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
LDB_DI1(108000000) -> IPU1_DI0(108000000)
Which interestingly matches how IPU2 is configured previously.
When the HDMI interface is then connected it does this to configure IPU2:
PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
PLL5_VIDEO_DIV(216000000/2) -> IPU2DI0_PODF(108000000/1) ->
IPU2_DI0(108000000)
But as the path "PLL5 -> PLL5_POST_DIV -> PLL5_VIDEO_DIV" is shared with
IPU1 the change in frequency and divider values results in:
PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
PLL5_VIDEO_DIV(216000000/2) -> LDB_DI1_IPU_DIV(108000000/3.5) ->
LDB_DI1(30857142) -> IPU1_DI0(30857142)
So the LVDS Bridge and IPU1 are now underclocked by 3.5 times.
I suspect that (theoretically) as IPU1_DI0 is already configured at the
required frequency via LDB_DI1, it might have been sufficient for the
IPU2_DI0_SEL MUX to select LDB_DI1 as its source?
Martyn
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-28 10:49 ` Martyn Welch
@ 2017-03-28 16:44 ` Philipp Zabel
2017-03-28 17:52 ` Martyn Welch
0 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2017-03-28 16:44 UTC (permalink / raw)
To: Martyn Welch; +Cc: dri-devel
Hi Martyn,
On Tue, 2017-03-28 at 11:49 +0100, Martyn Welch wrote:
> On Mon, Mar 27, 2017 at 12:11:12PM +0100, Martyn Welch wrote:
> > On Fri, Mar 24, 2017 at 11:42:53AM +0100, Philipp Zabel wrote:
> > > On Fri, 2017-03-24 at 10:24 +0000, Martyn Welch wrote:
> > > [...]
> > > > > Could you move to v4.9 or v4.10 and check if the four patches in
> > > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> > > > > or
> > > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> > > > > help?
> > > > >
> > > >
> > > > I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
> > > > the error, though we are unfortunately still experiencing the loss of
> > > > output on LVDS display. Time to look elsewhere for the cause of that I
> > > > guess. :-)
> > >
> > > Is the LVDS serial clock derived from the video PLL on that board?
> > > (What is the output of /sys/kernel/debug/clk/clk_summary?)
> > >
> >
> > I beleive so. I've included a few dumps from clk_summary below.
> >
>
> After looking at the dumps in more detail, I think I know what's
> happening:
>
> Problem appears to be a clocking issue.
I concur.
> When we have a display connected
> to the HDMI port pre-boot, it uses the following chain to drive IPU2
> (which is used for this display):
>
> PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
> PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
> LDB_DI1(108000000) -> IPU2_DI0(108000000)
That's not what the "HDMI attached pre boot, no LVDS" summary from your
last mail says:
pll2_pfd2_396m 3 3 432000000 0 0
ipu1_di0_pre_sel 1 1 432000000 0 0
ipu1_di0_pre 1 1 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
This looks like IPU1 DI0 drives the HDMI display, pll5 and IPU2 are
disabled.
> If the display connected via the LVDS interface is connected either
> before or after boot, we end up with IPU1 being drive thus:
>
> PLL2_PFD2(432000000) -> IPU2_DI1_PRE_CLK(432000000) ->
> IPU2DI1_PODF(432000000/4) -> IPU1_DI0(108000000)
I see this in the "HDMI attached pre boot, LVDS attached after boot" and
"HDMI attached pre boot, LVDS attached pre boot" summaries:
pll2_pfd2_396m 3 3 432000000 0 0
ipu1_di0_pre_sel 1 1 432000000 0 0
ipu1_di0_pre 1 1 108000000 0 0
ipu1_di0_sel 1 1 108000000 0 0
ipu1_di0 1 1 108000000 0 0
Same as above. Did you already set the ipu1_di0_pre_sel parent to
pll2_pfd2_396m?
> On the other hand, if only the LVDS is connected at boot, instead it is
> sets up IPU1 as follows:
>
> PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
> PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
> LDB_DI1(108000000) -> IPU1_DI0(108000000)
There's the difference. Now IPU1 DI0 is used to drive LVDS, but both
ldb_di0/1_sel (now the clock source for IPU1) and ipu2_di0_pre_sel are
parented to pll5_video_div.
> Which interestingly matches how IPU2 is configured previously.
>
> When the HDMI interface is then connected it does this to configure IPU2:
>
> PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
> PLL5_VIDEO_DIV(216000000/2) -> IPU2DI0_PODF(108000000/1) ->
> IPU2_DI0(108000000)
In this scenario only IPU2 should be used for LVDS, as IPU1 is clocked
from PLL2.
> But as the path "PLL5 -> PLL5_POST_DIV -> PLL5_VIDEO_DIV" is shared with
> IPU1 the change in frequency and divider values results in:
>
> PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
> PLL5_VIDEO_DIV(216000000/2) -> LDB_DI1_IPU_DIV(108000000/3.5) ->
> LDB_DI1(30857142) -> IPU1_DI0(30857142)
>
>
> So the LVDS Bridge and IPU1 are now underclocked by 3.5 times.
Exactly.
> I suspect that (theoretically) as IPU1_DI0 is already configured at the
> required frequency via LDB_DI1, it might have been sufficient for the
> IPU2_DI0_SEL MUX to select LDB_DI1 as its source?
It is the ipu1_di0_pre_sel and ipu2_di0_pre_sel setup that is important
here (and you have to pin LVDS and HDMI to separate IPUs). The LDB
driver will switch the ipu1_di0_sel from ipu1_di0_pre to ldb_di1 if IPU1
DI0 drives LVDS (imx_ldb_set_clock), so in that case it would be
ipu2_di0_pre_sel that had to be switched away from pll5_video_div, to
pll2_pfd2_396m.
In short, the IPU that drives HDMI must have its pre_sel set to
pll2_pfd_396m in your case, to avoid stepping on the LVDS output's toes,
as the PLL can't be clocked to the pixel clock and to the LVDS serial
clock (3.5*pixel clock) at the same time. The pre_sel setup for the LVDS
IPU shouldn't matter as that will be switched to the ldb_di clocks. So
just switching both ipu1/2_di0_pre_sel to pll2_pfd2_396m could do the
trick?
regards
Philipp
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-28 16:44 ` Philipp Zabel
@ 2017-03-28 17:52 ` Martyn Welch
2017-03-29 8:07 ` Philipp Zabel
0 siblings, 1 reply; 10+ messages in thread
From: Martyn Welch @ 2017-03-28 17:52 UTC (permalink / raw)
To: Philipp Zabel; +Cc: dri-devel
On Tue, Mar 28, 2017 at 06:44:50PM +0200, Philipp Zabel wrote:
> Hi Martyn,
>
> On Tue, 2017-03-28 at 11:49 +0100, Martyn Welch wrote:
> > On Mon, Mar 27, 2017 at 12:11:12PM +0100, Martyn Welch wrote:
> > > On Fri, Mar 24, 2017 at 11:42:53AM +0100, Philipp Zabel wrote:
> > > > On Fri, 2017-03-24 at 10:24 +0000, Martyn Welch wrote:
> > > > [...]
> > > > > > Could you move to v4.9 or v4.10 and check if the four patches in
> > > > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.9-ipu-dp-plane-fix
> > > > > > or
> > > > > > https://git.pengutronix.de/cgit/pza/linux/tag/?id=v4.10-ipu-dp-plane-fix-2
> > > > > > help?
> > > > > >
> > > > >
> > > > > I've updated to v4.10, the patches from v4.10-ipu-dp-plane-fix-2 resolve
> > > > > the error, though we are unfortunately still experiencing the loss of
> > > > > output on LVDS display. Time to look elsewhere for the cause of that I
> > > > > guess. :-)
> > > >
> > > > Is the LVDS serial clock derived from the video PLL on that board?
> > > > (What is the output of /sys/kernel/debug/clk/clk_summary?)
> > > >
> > >
> > > I beleive so. I've included a few dumps from clk_summary below.
> > >
> >
> > After looking at the dumps in more detail, I think I know what's
> > happening:
> >
> > Problem appears to be a clocking issue.
>
> I concur.
>
> > When we have a display connected
> > to the HDMI port pre-boot, it uses the following chain to drive IPU2
> > (which is used for this display):
> >
> > PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
> > PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
> > LDB_DI1(108000000) -> IPU2_DI0(108000000)
>
> That's not what the "HDMI attached pre boot, no LVDS" summary from your
> last mail says:
>
> pll2_pfd2_396m 3 3 432000000 0 0
> ipu1_di0_pre_sel 1 1 432000000 0 0
> ipu1_di0_pre 1 1 108000000 0 0
> ipu1_di0_sel 1 1 108000000 0 0
> ipu1_di0 1 1 108000000 0 0
>
> This looks like IPU1 DI0 drives the HDMI display, pll5 and IPU2 are
> disabled.
>
> > If the display connected via the LVDS interface is connected either
> > before or after boot, we end up with IPU1 being drive thus:
> >
> > PLL2_PFD2(432000000) -> IPU2_DI1_PRE_CLK(432000000) ->
> > IPU2DI1_PODF(432000000/4) -> IPU1_DI0(108000000)
>
> I see this in the "HDMI attached pre boot, LVDS attached after boot" and
> "HDMI attached pre boot, LVDS attached pre boot" summaries:
>
> pll2_pfd2_396m 3 3 432000000 0 0
> ipu1_di0_pre_sel 1 1 432000000 0 0
> ipu1_di0_pre 1 1 108000000 0 0
> ipu1_di0_sel 1 1 108000000 0 0
> ipu1_di0 1 1 108000000 0 0
>
> Same as above. Did you already set the ipu1_di0_pre_sel parent to
> pll2_pfd2_396m?
>
> > On the other hand, if only the LVDS is connected at boot, instead it is
> > sets up IPU1 as follows:
> >
> > PLL5(756000000) -> PLL5_POST_DIV(756000000/2) ->
> > PLL5_VIDEO_DIV(378000000/1) -> LDB_DI1_IPU_DIV(378000000/3.5) ->
> > LDB_DI1(108000000) -> IPU1_DI0(108000000)
>
> There's the difference. Now IPU1 DI0 is used to drive LVDS, but both
> ldb_di0/1_sel (now the clock source for IPU1) and ipu2_di0_pre_sel are
> parented to pll5_video_div.
>
> > Which interestingly matches how IPU2 is configured previously.
> >
> > When the HDMI interface is then connected it does this to configure IPU2:
> >
> > PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
> > PLL5_VIDEO_DIV(216000000/2) -> IPU2DI0_PODF(108000000/1) ->
> > IPU2_DI0(108000000)
>
> In this scenario only IPU2 should be used for LVDS, as IPU1 is clocked
> from PLL2.
>
> > But as the path "PLL5 -> PLL5_POST_DIV -> PLL5_VIDEO_DIV" is shared with
> > IPU1 the change in frequency and divider values results in:
> >
> > PLL5(864000000) -> PLL5_POST_DIV(756000000/4) ->
> > PLL5_VIDEO_DIV(216000000/2) -> LDB_DI1_IPU_DIV(108000000/3.5) ->
> > LDB_DI1(30857142) -> IPU1_DI0(30857142)
> >
> >
> > So the LVDS Bridge and IPU1 are now underclocked by 3.5 times.
>
> Exactly.
>
> > I suspect that (theoretically) as IPU1_DI0 is already configured at the
> > required frequency via LDB_DI1, it might have been sufficient for the
> > IPU2_DI0_SEL MUX to select LDB_DI1 as its source?
>
> It is the ipu1_di0_pre_sel and ipu2_di0_pre_sel setup that is important
> here (and you have to pin LVDS and HDMI to separate IPUs). The LDB
> driver will switch the ipu1_di0_sel from ipu1_di0_pre to ldb_di1 if IPU1
> DI0 drives LVDS (imx_ldb_set_clock), so in that case it would be
> ipu2_di0_pre_sel that had to be switched away from pll5_video_div, to
> pll2_pfd2_396m.
> In short, the IPU that drives HDMI must have its pre_sel set to
> pll2_pfd_396m in your case, to avoid stepping on the LVDS output's toes,
> as the PLL can't be clocked to the pixel clock and to the LVDS serial
> clock (3.5*pixel clock) at the same time. The pre_sel setup for the LVDS
> IPU shouldn't matter as that will be switched to the ldb_di clocks. So
> just switching both ipu1/2_di0_pre_sel to pll2_pfd2_396m could do the
> trick?
>
As you can probably tell by how much I got in a muddle with my explanation
above, this isn't territory I'm familiar with.
It sounds good, not sure I 100% understand how to do this yet. :-)
I'll look into this more.
Thanks for your help, I'll give this a try.
Martyn
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-28 17:52 ` Martyn Welch
@ 2017-03-29 8:07 ` Philipp Zabel
2017-03-29 8:21 ` Martyn Welch
0 siblings, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2017-03-29 8:07 UTC (permalink / raw)
To: Martyn Welch; +Cc: dri-devel
On Tue, 2017-03-28 at 18:52 +0100, Martyn Welch wrote:
> On Tue, Mar 28, 2017 at 06:44:50PM +0200, Philipp Zabel wrote:
[...]
> > It is the ipu1_di0_pre_sel and ipu2_di0_pre_sel setup that is important
> > here (and you have to pin LVDS and HDMI to separate IPUs). The LDB
> > driver will switch the ipu1_di0_sel from ipu1_di0_pre to ldb_di1 if IPU1
> > DI0 drives LVDS (imx_ldb_set_clock), so in that case it would be
> > ipu2_di0_pre_sel that had to be switched away from pll5_video_div, to
> > pll2_pfd2_396m.
> > In short, the IPU that drives HDMI must have its pre_sel set to
> > pll2_pfd_396m in your case, to avoid stepping on the LVDS output's toes,
> > as the PLL can't be clocked to the pixel clock and to the LVDS serial
> > clock (3.5*pixel clock) at the same time. The pre_sel setup for the LVDS
> > IPU shouldn't matter as that will be switched to the ldb_di clocks. So
> > just switching both ipu1/2_di0_pre_sel to pll2_pfd2_396m could do the
> > trick?
> >
>
> As you can probably tell by how much I got in a muddle with my explanation
> above, this isn't territory I'm familiar with.
Well, the i.MX6 display clock setup is a bit convoluted.
> It sounds good, not sure I 100% understand how to do this yet. :-)
> I'll look into this more.
Have a look at how arch/arm/boot/dts/imx6q-b850v3.dts assigns the
clocks. I'd propose trying this setup:
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
I hope that way, whichever IPU1/2 DI0 is chosen for HDMI will use PLL2,
while the IPU1/2 DI0 chosen for LVDS will be undisturbed in using PLL5.
regards
Philipp
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [CRTC:24] vblank wait timed out
2017-03-29 8:07 ` Philipp Zabel
@ 2017-03-29 8:21 ` Martyn Welch
0 siblings, 0 replies; 10+ messages in thread
From: Martyn Welch @ 2017-03-29 8:21 UTC (permalink / raw)
To: Philipp Zabel; +Cc: dri-devel
On Wed, Mar 29, 2017 at 10:07:45AM +0200, Philipp Zabel wrote:
> On Tue, 2017-03-28 at 18:52 +0100, Martyn Welch wrote:
> > On Tue, Mar 28, 2017 at 06:44:50PM +0200, Philipp Zabel wrote:
> [...]
> > > It is the ipu1_di0_pre_sel and ipu2_di0_pre_sel setup that is important
> > > here (and you have to pin LVDS and HDMI to separate IPUs). The LDB
> > > driver will switch the ipu1_di0_sel from ipu1_di0_pre to ldb_di1 if IPU1
> > > DI0 drives LVDS (imx_ldb_set_clock), so in that case it would be
> > > ipu2_di0_pre_sel that had to be switched away from pll5_video_div, to
> > > pll2_pfd2_396m.
> > > In short, the IPU that drives HDMI must have its pre_sel set to
> > > pll2_pfd_396m in your case, to avoid stepping on the LVDS output's toes,
> > > as the PLL can't be clocked to the pixel clock and to the LVDS serial
> > > clock (3.5*pixel clock) at the same time. The pre_sel setup for the LVDS
> > > IPU shouldn't matter as that will be switched to the ldb_di clocks. So
> > > just switching both ipu1/2_di0_pre_sel to pll2_pfd2_396m could do the
> > > trick?
> > >
> >
> > As you can probably tell by how much I got in a muddle with my explanation
> > above, this isn't territory I'm familiar with.
>
> Well, the i.MX6 display clock setup is a bit convoluted.
>
> > It sounds good, not sure I 100% understand how to do this yet. :-)
> > I'll look into this more.
>
> Have a look at how arch/arm/boot/dts/imx6q-b850v3.dts assigns the
> clocks. I'd propose trying this setup:
>
> &clks {
> assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
> <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
> <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
> <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
> assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
> <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
> <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
> <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
> };
>
> I hope that way, whichever IPU1/2 DI0 is chosen for HDMI will use PLL2,
> while the IPU1/2 DI0 chosen for LVDS will be undisturbed in using PLL5.
>
That's exactly what I figured I needed to do last night! Thanks for the
confirmation. :-)
Maybe I'm beginning to understand this a /tiny/ bit more than I thought...
Martyn
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-03-29 8:21 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-21 9:50 [CRTC:24] vblank wait timed out Martyn Welch
2017-03-21 17:18 ` Philipp Zabel
2017-03-24 10:24 ` Martyn Welch
2017-03-24 10:42 ` Philipp Zabel
2017-03-27 11:11 ` Martyn Welch
2017-03-28 10:49 ` Martyn Welch
2017-03-28 16:44 ` Philipp Zabel
2017-03-28 17:52 ` Martyn Welch
2017-03-29 8:07 ` Philipp Zabel
2017-03-29 8:21 ` Martyn Welch
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