* [PATCH 01/12] drm/amd/display: using calculated values for VReady/Startup
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 02/12] drm/amd/display: Add audio/video ContainerId implementation Harry Wentland
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
Change-Id: I23ebcf87fab296f94930bcfdd9e2851398e9d161
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 9 +++++++++
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 ++
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 1 -
drivers/gpu/drm/amd/display/include/logger_types.h | 1 +
4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 33e3377f69fe..568b7f0569f8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -28,6 +28,7 @@
#include "os_types.h"
#include "fixed31_32.h"
+#include "signal_types.h"
/******************************************************************************
* Data types for Virtual HW Layer of DAL3.
@@ -647,5 +648,13 @@ struct dc_crtc_timing {
struct dc_crtc_timing_flags flags;
};
+struct _dlg_otg_param {
+ int vstartup_start;
+ int vupdate_offset;
+ int vupdate_width;
+ int vready_offset;
+ enum signal_type signal;
+};
+
#endif /* DC_HW_TYPES_H */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index c631dec489e7..f89395e0c107 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -180,6 +180,8 @@ struct dm_pp_display_configuration {
uint32_t avail_mclk_switch_time_us;
uint32_t avail_mclk_switch_time_in_disp_active_us;
+ uint32_t min_dcfclock_khz;
+ uint32_t min_dcfc_deep_sleep_clock_khz;
uint32_t disp_clk_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index baa9445833fb..62c19358254b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -96,7 +96,6 @@ enum crtc_state {
CRTC_STATE_VBLANK = 0,
CRTC_STATE_VACTIVE
};
-
struct timing_generator {
const struct timing_generator_funcs *funcs;
struct dc_bios *bp;
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 832d17e1cc49..982c67f7de43 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -63,6 +63,7 @@ enum dc_log_type {
LOG_EVENT_LINK_LOSS,
LOG_EVENT_UNDERFLOW,
LOG_IF_TRACE,
+ LOG_HW_MARKS,
LOG_SECTION_TOTAL_COUNT
};
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/12] drm/amd/display: Add audio/video ContainerId implementation
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-03-28 21:09 ` [PATCH 01/12] drm/amd/display: using calculated values for VReady/Startup Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 03/12] drm/amd/display: Power on front end during set mode Harry Wentland
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: xhdu
From: xhdu <Duke.Du@amd.com>
Leave hardcoded if no ContainerId provided by DM.
Change-Id: Ifb1639992a771f08c3b57ee09d11cc3ac8f8dfd2
Signed-off-by: Duke Du <Duke.Du@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 39 ++++++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +++++++--
drivers/gpu/drm/amd/display/dc/dc.h | 14 +++++++++
3 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
index 8a204731301d..da9955675fbf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
@@ -45,7 +45,10 @@ struct sink {
static void destruct(struct sink *sink)
{
-
+ if (sink->protected.public.dc_container_id) {
+ dm_free(sink->protected.public.dc_container_id);
+ sink->protected.public.dc_container_id = NULL;
+ }
}
static bool construct(struct sink *sink, const struct dc_sink_init_data *init_params)
@@ -63,6 +66,7 @@ static bool construct(struct sink *sink, const struct dc_sink_init_data *init_pa
sink->protected.public.dongle_max_pix_clk = init_params->dongle_max_pix_clk;
sink->protected.public.converter_disable_audio =
init_params->converter_disable_audio;
+ sink->protected.public.dc_container_id = NULL;
return true;
}
@@ -113,6 +117,39 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
return NULL;
}
+bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id)
+{
+ if (dc_sink && container_id && dc_sink->dc_container_id) {
+ memmove(&container_id->guid, &dc_sink->dc_container_id->guid,
+ sizeof(container_id->guid));
+ memmove(&container_id->portId, &dc_sink->dc_container_id->portId,
+ sizeof(container_id->portId));
+ container_id->manufacturerName = dc_sink->dc_container_id->manufacturerName;
+ container_id->productCode = dc_sink->dc_container_id->productCode;
+ return true;
+ }
+ return false;
+}
+
+bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id)
+{
+ if (dc_sink && container_id) {
+ if (!dc_sink->dc_container_id)
+ dc_sink->dc_container_id = dm_alloc(sizeof(*dc_sink->dc_container_id));
+
+ if (dc_sink->dc_container_id) {
+ memmove(&dc_sink->dc_container_id->guid, &container_id->guid,
+ sizeof(container_id->guid));
+ memmove(&dc_sink->dc_container_id->portId, &container_id->portId,
+ sizeof(container_id->portId));
+ dc_sink->dc_container_id->manufacturerName = container_id->manufacturerName;
+ dc_sink->dc_container_id->productCode = container_id->productCode;
+ return true;
+ }
+ }
+ return false;
+}
+
/*******************************************************************************
* Protected functions - visible only inside of DC (not visible in DM)
******************************************************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index bafba1f13a1a..512a53bdc32f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -76,9 +76,17 @@ static bool construct(struct core_stream *stream,
stream->public.audio_info.product_id = dc_sink_data->edid_caps.product_id;
stream->public.audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
- /* TODO - Unhardcode port_id */
- stream->public.audio_info.port_id[0] = 0x5558859e;
- stream->public.audio_info.port_id[1] = 0xd989449;
+ if (dc_sink_data->dc_container_id != NULL) {
+ struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
+
+ stream->public.audio_info.port_id[0] = dc_container_id->portId[0];
+ stream->public.audio_info.port_id[1] = dc_container_id->portId[1];
+ } else {
+ /* TODO - WindowDM has implemented,
+ other DMs need Unhardcode port_id */
+ stream->public.audio_info.port_id[0] = 0x5558859e;
+ stream->public.audio_info.port_id[1] = 0xd989449;
+ }
/* EDID CAP translation for HDMI 2.0 */
stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 8b033ba5df6e..b3d5b922aae4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -695,6 +695,17 @@ bool dc_link_dp_set_test_pattern(
* Sink Interfaces - A sink corresponds to a display output device
******************************************************************************/
+struct dc_container_id {
+ // 128bit GUID in binary form
+ unsigned char guid[16];
+ // 8 byte port ID -> ELD.PortID
+ unsigned int portId[2];
+ // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
+ unsigned short manufacturerName;
+ // 2 byte product code -> ELD.ProductCode
+ unsigned short productCode;
+};
+
/*
* The sink structure contains EDID and other display device properties
*/
@@ -702,6 +713,7 @@ struct dc_sink {
enum signal_type sink_signal;
struct dc_edid dc_edid; /* raw edid */
struct dc_edid_caps edid_caps; /* parse display caps */
+ struct dc_container_id *dc_container_id;
uint32_t dongle_max_pix_clk;
bool converter_disable_audio;
};
@@ -719,6 +731,8 @@ struct dc_sink_init_data {
};
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
+bool dc_sink_get_container_id(struct dc_sink *dc_sink, struct dc_container_id *container_id);
+bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container_id *container_id);
/*******************************************************************************
* Cursor interfaces - To manages the cursor within a stream
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 03/12] drm/amd/display: Power on front end during set mode.
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-03-28 21:09 ` [PATCH 01/12] drm/amd/display: using calculated values for VReady/Startup Harry Wentland
2017-03-28 21:09 ` [PATCH 02/12] drm/amd/display: Add audio/video ContainerId implementation Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 04/12] drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h Harry Wentland
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: If307b84716d2bb8e5035a410398f4c40982418da
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e5e52c705954..2a3a39e31717 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1722,6 +1722,9 @@ enum dc_status dce110_apply_ctx_to_hw(
context,
dc);
+ if (dc->hwss.power_on_front_end)
+ dc->hwss.power_on_front_end(dc, pipe_ctx, context);
+
if (DC_OK != status)
return status;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index bcb267295cb9..077dc7573c52 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -104,6 +104,11 @@ struct hw_sequencer_funcs {
enum pipe_gating_control power_gating);
void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe);
+
+ void (*power_on_front_end)(struct core_dc *dc,
+ struct pipe_ctx *pipe,
+ struct validate_context *context);
+
void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
void (*enable_stream)(struct pipe_ctx *pipe_ctx);
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 04/12] drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 03/12] drm/amd/display: Power on front end during set mode Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 05/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as VBLANK trigger Harry Wentland
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Change-Id: I58faa0924c573d23a75a9ef33e7f58e10afdac31
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +-
.../gpu/drm/amd/display/dc/inc/{bandwidth_calcs.h => dce_calcs.h} | 8 +++++---
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 +-
7 files changed, 11 insertions(+), 9 deletions(-)
rename drivers/gpu/drm/amd/display/dc/inc/{bandwidth_calcs.h => dce_calcs.h} (99%)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 4820660f51d6..5ac614f433f8 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -24,7 +24,7 @@
*/
#include "dm_services.h"
-#include "bandwidth_calcs.h"
+#include "dce_calcs.h"
#include "dc.h"
#include "core_types.h"
#include "dal_asic_id.h"
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c0889ad8357e..b3891228b499 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -35,7 +35,7 @@
#include "clock_source.h"
#include "dc_bios_types.h"
-#include "bandwidth_calcs.h"
+#include "dce_calcs.h"
#include "bios_parser_interface.h"
#include "include/irq_service_interface.h"
#include "transform.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index aac47955e9bf..9c32b5bbdff5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -31,7 +31,7 @@
#include "gmc/gmc_8_2_sh_mask.h"
#include "include/logger_interface.h"
-#include "inc/bandwidth_calcs.h"
+#include "inc/dce_calcs.h"
#include "dce110_mem_input.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
index ebb8df3cdf4a..933e3d819f27 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
@@ -31,7 +31,7 @@
#include "gmc/gmc_7_1_sh_mask.h"
#include "include/logger_interface.h"
-#include "inc/bandwidth_calcs.h"
+#include "inc/dce_calcs.h"
#include "../dce110/dce110_mem_input.h"
#include "dce80_mem_input.h"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 7f3c6da1ebd7..405608318ccc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -27,7 +27,7 @@
#define _CORE_TYPES_H_
#include "dc.h"
-#include "bandwidth_calcs.h"
+#include "dce_calcs.h"
#include "ddc_service_types.h"
#include "dc_bios_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
similarity index 99%
rename from drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h
rename to drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
index 81fab9ef3637..580dee95e57a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Advanced Micro Devices, Inc.
+ * Copyright 2015-2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,12 +27,14 @@
* Bandwidth and Watermark calculations interface.
* (Refer to "DCEx_mode_support.xlsm" from Perforce.)
*/
-#ifndef __BANDWIDTH_CALCS_H__
-#define __BANDWIDTH_CALCS_H__
+#ifndef __DCE_CALCS_H__
+#define __DCE_CALCS_H__
#include "bw_fixed.h"
struct pipe_ctx;
+struct core_dc;
+struct validate_context;
enum bw_calcs_version {
BW_CALCS_VERSION_INVALID,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 7ec4027700d8..179f5ad70f48 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -27,7 +27,7 @@
#include "dc.h"
#include "include/grph_object_id.h"
-#include "inc/bandwidth_calcs.h"
+#include "inc/dce_calcs.h"
#include "dce/dce_mem_input.h" /* temporary */
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 05/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as VBLANK trigger.
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 04/12] drm/amd/display: Rename bandwidth_calcs.h to dce_calcs.h Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 06/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as a trigger for VBLANK Harry Wentland
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
VBLANK interrupt is driven bu line buffer vcounter which is
ahead of CRTC vcounter. Use an interrupt that fires at the actual
CRTC vblank start boundry.
Change-Id: I2d397447e105137451c966ddfc73f533f0d8bc4b
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
---
.../display/dc/dce110/dce110_timing_generator.c | 46 ++++++++++++++-
.../display/dc/dce110/dce110_timing_generator.h | 3 +
.../display/dc/dce120/dce120_timing_generator.c | 32 +++++++++-
.../amd/display/dc/dce80/dce80_timing_generator.c | 1 +
.../drm/amd/display/dc/inc/hw/timing_generator.h | 2 +
.../amd/display/dc/irq/dce110/irq_service_dce110.c | 68 +++++++++++++++-------
.../amd/display/dc/irq/dce110/irq_service_dce110.h | 5 ++
.../amd/display/dc/irq/dce120/irq_service_dce120.c | 11 ++--
.../amd/display/dc/irq/dce80/irq_service_dce80.c | 22 ++++---
9 files changed, 152 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index f4b8576a0546..006412be7a02 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1869,6 +1869,48 @@ void dce110_tg_set_colors(struct timing_generator *tg,
dce110_tg_set_overscan_color(tg, overscan_color);
}
+/* Gets first line of blank region of the display timing for CRTC
+ * and programms is as a trigger to fire vertical interrupt
+ */
+bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width)
+{
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+ uint32_t vbl = 0;
+ uint32_t val = 0;
+ uint32_t position, vbl_start;
+
+ tg->funcs->get_scanoutpos(
+ tg,
+ &vbl,
+ &position);
+
+ if (vbl == 0)
+ return false;
+
+ vbl_start =
+ get_reg_field_value(
+ vbl,
+ CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_START);
+
+ set_reg_field_value(
+ val,
+ vbl_start,
+ CRTC_VERTICAL_INTERRUPT0_POSITION,
+ CRTC_VERTICAL_INTERRUPT0_LINE_START);
+
+ /* Set interaval width for interrupt to fire to 1 scanline */
+ set_reg_field_value(
+ val,
+ vbl_start + width,
+ CRTC_VERTICAL_INTERRUPT0_POSITION,
+ CRTC_VERTICAL_INTERRUPT0_LINE_END);
+
+ dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val);
+
+ return true;
+}
+
static const struct timing_generator_funcs dce110_tg_funcs = {
.validate_timing = dce110_tg_validate_timing,
.program_timing = dce110_tg_program_timing,
@@ -1901,8 +1943,8 @@ static const struct timing_generator_funcs dce110_tg_funcs = {
dce110_timing_generator_set_drr,
.set_static_screen_control =
dce110_timing_generator_set_static_screen_control,
- .set_test_pattern = dce110_timing_generator_set_test_pattern
-
+ .set_test_pattern = dce110_timing_generator_set_test_pattern,
+ .arm_vert_intr = dce110_arm_vert_intr,
};
bool dce110_timing_generator_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index 378509b8e56c..ca387b40fc67 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -271,4 +271,7 @@ void dce110_tg_set_colors(struct timing_generator *tg,
const struct tg_color *blank_color,
const struct tg_color *overscan_color);
+bool dce110_arm_vert_intr(
+ struct timing_generator *tg, uint8_t width);
+
#endif /* __DC_TIMING_GENERATOR_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index d7e787b591a0..95cb1768aeb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1039,6 +1039,35 @@ void dce120_timing_generator_set_test_pattern(
}
}
+static bool dce120_arm_vert_intr(
+ struct timing_generator *tg,
+ uint8_t width)
+{
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+ uint32_t vbl, position, vbl_start;
+
+ tg->funcs->get_scanoutpos(
+ tg,
+ &vbl,
+ &position);
+
+ if (vbl == 0)
+ return false;
+
+ vbl_start =
+ get_reg_field_value(
+ vbl,
+ CRTC0_CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_START);
+
+ CRTC_REG_SET_2(
+ CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION,
+ CRTC_VERTICAL_INTERRUPT0_LINE_START, vbl_start,
+ CRTC_VERTICAL_INTERRUPT0_LINE_END, vbl_start + width);
+
+ return true;
+}
+
static struct timing_generator_funcs dce120_tg_funcs = {
.validate_timing = dce120_tg_validate_timing,
.program_timing = dce120_tg_program_timing,
@@ -1068,7 +1097,8 @@ static struct timing_generator_funcs dce120_tg_funcs = {
.enable_advanced_request = dce120_timing_generator_enable_advanced_request,
.set_drr = dce120_timing_generator_set_drr,
.set_static_screen_control = dce120_timing_generator_set_static_screen_control,
- .set_test_pattern = dce120_timing_generator_set_test_pattern
+ .set_test_pattern = dce120_timing_generator_set_test_pattern,
+ .arm_vert_intr = dce120_arm_vert_intr,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index eeccabd65a7a..1198f2fbf9c7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -145,6 +145,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = {
.set_static_screen_control =
dce110_timing_generator_set_static_screen_control,
.set_test_pattern = dce110_timing_generator_set_test_pattern,
+ .arm_vert_intr = dce110_arm_vert_intr,
/* DCE8.0 overrides */
.enable_advanced_request =
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 62c19358254b..51902a4f8798 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -156,6 +156,8 @@ struct timing_generator_funcs {
enum controller_dp_test_pattern test_pattern,
enum dc_color_depth color_depth);
+ bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
+
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 4c7c85d45518..52361d1472fa 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -31,14 +31,10 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
+
#include "ivsrcid/ivsrcid_vislands30.h"
-#define VISLANDS30_IV_SRCID_D1_VBLANK 1
-#define VISLANDS30_IV_SRCID_D2_VBLANK 2
-#define VISLANDS30_IV_SRCID_D3_VBLANK 3
-#define VISLANDS30_IV_SRCID_D4_VBLANK 4
-#define VISLANDS30_IV_SRCID_D5_VBLANK 5
-#define VISLANDS30_IV_SRCID_D6_VBLANK 6
+#include "core_dc.h"
static bool hpd_ack(
struct irq_service *irq_service,
@@ -83,7 +79,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
};
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
- .set = NULL,
+ .set = dce110_vblank_set,
.ack = NULL
};
@@ -148,18 +144,19 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
#define vblank_int_entry(reg_num)\
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
- .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
+ .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
.enable_mask =\
- LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
.enable_value = {\
- LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
- ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
- .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+ ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+ .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
.ack_mask =\
- LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
.ack_value =\
- LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
- .funcs = &vblank_irq_info_funcs\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+ .funcs = &vblank_irq_info_funcs,\
+ .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
}
#define dummy_irq_entry() \
@@ -202,6 +199,35 @@ bool dal_irq_service_dummy_ack(
return false;
}
+
+bool dce110_vblank_set(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info,
+ bool enable)
+{
+ struct dc_context *dc_ctx = irq_service->ctx;
+ struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc);
+ enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source(
+ irq_service->ctx->dc,
+ info->src_id,
+ info->ext_id);
+ uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
+
+ struct timing_generator *tg =
+ core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].tg;
+
+ if (enable) {
+ if (!tg->funcs->arm_vert_intr(tg, 2)) {
+ DC_ERROR("Failed to get VBLANK!\n");
+ return false;
+ }
+ }
+
+ dal_irq_service_set_generic(irq_service, info, enable);
+ return true;
+
+}
+
static const struct irq_source_info_funcs dummy_irq_info_funcs = {
.set = dal_irq_service_dummy_set,
.ack = dal_irq_service_dummy_ack
@@ -302,17 +328,17 @@ enum dc_irq_source to_dal_irq_source_dce110(
uint32_t ext_id)
{
switch (src_id) {
- case VISLANDS30_IV_SRCID_D1_VBLANK:
+ case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK1;
- case VISLANDS30_IV_SRCID_D2_VBLANK:
+ case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK2;
- case VISLANDS30_IV_SRCID_D3_VBLANK:
+ case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK3;
- case VISLANDS30_IV_SRCID_D4_VBLANK:
+ case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK4;
- case VISLANDS30_IV_SRCID_D5_VBLANK:
+ case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK5;
- case VISLANDS30_IV_SRCID_D6_VBLANK:
+ case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
return DC_IRQ_SOURCE_VBLANK6;
case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
return DC_IRQ_SOURCE_VUPDATE1;
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
index a84f360c6515..9237646c0959 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h
@@ -45,4 +45,9 @@ bool dal_irq_service_dummy_ack(
struct irq_service *irq_service,
const struct irq_source_info *info);
+bool dce110_vblank_set(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info,
+ bool enable);
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
index 5a263b2efa51..3871633ac635 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -79,7 +79,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
};
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
- .set = NULL,
+ .set = dce110_vblank_set,
.ack = NULL
};
@@ -144,10 +144,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
#define vblank_int_entry(reg_num)\
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
- IRQ_REG_ENTRY(LB, reg_num,\
- LB_INTERRUPT_MASK, VBLANK_INTERRUPT_MASK,\
- LB_VBLANK_STATUS, VBLANK_ACK),\
- .funcs = &vblank_irq_info_funcs\
+ IRQ_REG_ENTRY(CRTC, reg_num,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
+ .funcs = &vblank_irq_info_funcs,\
+ .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
}
#define dummy_irq_entry() \
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
index dd09d2b6d4a7..7e8cb22f280f 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
@@ -35,6 +35,9 @@
#include "ivsrcid/ivsrcid_vislands30.h"
+#include "dc_types.h"
+#include "inc/core_dc.h"
+
static bool hpd_ack(
struct irq_service *irq_service,
const struct irq_source_info *info)
@@ -78,7 +81,7 @@ static const struct irq_source_info_funcs pflip_irq_info_funcs = {
};
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
- .set = NULL,
+ .set = dce110_vblank_set,
.ack = NULL
};
@@ -145,18 +148,19 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
#define vblank_int_entry(reg_num)\
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
- .enable_reg = mmLB ## reg_num ## _LB_INTERRUPT_MASK,\
+ .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
.enable_mask =\
- LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
.enable_value = {\
- LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK,\
- ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK},\
- .ack_reg = mmLB ## reg_num ## _LB_VBLANK_STATUS,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+ ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+ .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
.ack_mask =\
- LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
.ack_value =\
- LB_VBLANK_STATUS__VBLANK_ACK_MASK,\
- .funcs = &vblank_irq_info_funcs\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+ .funcs = &vblank_irq_info_funcs,\
+ .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
}
#define dummy_irq_entry() \
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 06/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as a trigger for VBLANK.
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 05/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as VBLANK trigger Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 07/12] drm/amd/display: voltage request related change Harry Wentland
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Register ISR hnadler on the new interrupt.
Change-Id: Ib934f2197b8b58a9534b53b102d8f0be5e97a43c
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index df7f08b46123..ed7ca675ff37 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -913,9 +913,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
* for acknowledging and handling. */
/* Use VBLANK interrupt */
- for (i = 1; i <= adev->mode_info.num_crtc; i++) {
+ for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
-
if (r) {
DRM_ERROR("Failed to add crtc irq id!\n");
return r;
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 07/12] drm/amd/display: voltage request related change
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 06/12] drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as a trigger for VBLANK Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 08/12] drm/amd/display: increase timeout for dmif dealloc Harry Wentland
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
Change-Id: I8700420838f9038a00d3db7be5810c04f32f3b94
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
---
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 27 +++++++++++-----------
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 2 ++
drivers/gpu/drm/amd/display/include/logger_types.h | 1 +
4 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index bd4524ef3a37..8ddad3a877d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1035,6 +1035,7 @@ static void get_ss_info_from_atombios(
}
*spread_spectrum_data = ss_data;
+ dm_free(ss_data);
dm_free(ss_info);
return;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 263f8900e39c..b4fd02219c2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -495,6 +495,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
}
}
+
static bool dce_apply_clock_voltage_request(
struct display_clock *clk,
enum dm_pp_clock_type clocks_type,
@@ -502,6 +503,7 @@ static bool dce_apply_clock_voltage_request(
bool pre_mode_set,
bool update_dp_phyclk)
{
+ bool send_request = false;
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
switch (clocks_type) {
@@ -522,9 +524,8 @@ static bool dce_apply_clock_voltage_request(
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.dispclk_notify_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.dispclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -532,9 +533,8 @@ static bool dce_apply_clock_voltage_request(
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.pixelclk_notify_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.pixelclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -542,9 +542,8 @@ static bool dce_apply_clock_voltage_request(
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.phyclk_notigy_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.phyclk_notigy_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -554,29 +553,30 @@ static bool dce_apply_clock_voltage_request(
ASSERT(0);
break;
}
+
} else {
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (!clk->cur_clocks_value.dispclk_notify_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (!clk->cur_clocks_value.pixelclk_notify_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (!clk->cur_clocks_value.phyclk_notigy_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
default:
ASSERT(0);
break;
}
}
-
+ if (send_request) {
+ dm_pp_apply_clock_for_voltage_request(
+ clk->ctx, &clock_voltage_req);
+ }
if (update_dp_phyclk && (clocks_in_khz >
clk->cur_clocks_value.max_dp_phyclk_in_khz))
clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz;
@@ -584,6 +584,7 @@ static bool dce_apply_clock_voltage_request(
return true;
}
+
static const struct display_clock_funcs dce120_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
.apply_clock_voltage_request = dce_apply_clock_voltage_request,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
index 79aa75c150ec..97f26b55535f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
@@ -28,6 +28,7 @@
#include "dm_services_types.h"
+
struct clocks_value {
int dispclk_in_khz;
int max_pixelclk_in_khz;
@@ -38,6 +39,7 @@ struct clocks_value {
bool phyclk_notigy_pplib_done;
};
+
/* Structure containing all state-dependent clocks
* (dependent on "enum clocks_state") */
struct state_dependent_clocks {
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 982c67f7de43..dfc0f102b33d 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -64,6 +64,7 @@ enum dc_log_type {
LOG_EVENT_UNDERFLOW,
LOG_IF_TRACE,
LOG_HW_MARKS,
+ LOG_PPLIB,
LOG_SECTION_TOTAL_COUNT
};
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 08/12] drm/amd/display: increase timeout for dmif dealloc
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 07/12] drm/amd/display: voltage request related change Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 09/12] drm/amd/display: Fix MPO exit and cursor issue Harry Wentland
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Roman Li
From: Roman Li <Roman.Li@amd.com>
In some use-cases, e.g. multiple 4K displays,
exisitng wait time for reg update of 30msec timed out
during mode setiing that sometimes resulted in system bad state
as we continue without waiting for registry update complete.
Increasing timeout to 35msec fixes that problem.
Change-Id: I280155f6e336066b810fe9e3533c345114aca725
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 7acd87152811..884f453d91b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -524,7 +524,7 @@ void dce_mem_input_free_dmif(struct mem_input *mi,
REG_WAIT(DMIF_BUFFER_CONTROL,
DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
- 10, 0xBB8);
+ 10, 3500);
if (mi->wa.single_head_rdreq_dmif_limit) {
uint32_t eanble = (total_stream_num > 1) ? 0 :
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 09/12] drm/amd/display: Fix MPO exit and cursor issue.
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 08/12] drm/amd/display: increase timeout for dmif dealloc Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 10/12] drm/amd/display: use CP2520-3 for PHY compliance automation Harry Wentland
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: Idaa862166c069adba8ce034143851fab3b01a781
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 ++++-
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 512a53bdc32f..bf209f7bbf98 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -215,7 +215,7 @@ bool dc_stream_set_cursor_attributes(
bool dc_stream_set_cursor_position(
const struct dc_stream *dc_stream,
- const struct dc_cursor_position *position)
+ struct dc_cursor_position *position)
{
int i;
struct core_stream *stream;
@@ -251,6 +251,9 @@ bool dc_stream_set_cursor_position(
.h_scale_ratio = pipe_ctx->scl_data.ratios.horz,
};
+ if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface)
+ position->enable = false;
+
ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m);
ret = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index b3d5b922aae4..0731045f6084 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -744,7 +744,7 @@ bool dc_stream_set_cursor_attributes(
bool dc_stream_set_cursor_position(
const struct dc_stream *stream,
- const struct dc_cursor_position *position);
+ struct dc_cursor_position *position);
/* Newer interfaces */
struct dc_cursor {
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 10/12] drm/amd/display: use CP2520-3 for PHY compliance automation
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 09/12] drm/amd/display: Fix MPO exit and cursor issue Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 11/12] drm/amd/display: stereo support Harry Wentland
2017-03-28 21:09 ` [PATCH 12/12] drm/amd/display: obtain usHBR3En bit from BP 1 Harry Wentland
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Change-Id: Ida1e78b4785adc6b1362d57c436797d5e37185ee
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 3 +++
drivers/gpu/drm/amd/display/include/link_service_types.h | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index ed46e9aaf357..df116f86ab45 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1405,6 +1405,9 @@ void dce110_link_encoder_dp_set_phy_pattern(
case DP_TEST_PATTERN_CP2520_2:
set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
break;
+ case DP_TEST_PATTERN_CP2520_3:
+ set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
+ break;
case DP_TEST_PATTERN_VIDEO_MODE: {
set_dp_phy_pattern_passthrough_mode(
enc110, param->dp_panel_mode);
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index b2326017e4c7..fe8b5144e03f 100644
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -85,13 +85,13 @@ enum dp_test_pattern {
DP_TEST_PATTERN_CP2520_1,
DP_TEST_PATTERN_CP2520_2,
DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
+ DP_TEST_PATTERN_CP2520_3,
/* Link Training Patterns */
DP_TEST_PATTERN_TRAINING_PATTERN1,
DP_TEST_PATTERN_TRAINING_PATTERN2,
DP_TEST_PATTERN_TRAINING_PATTERN3,
DP_TEST_PATTERN_TRAINING_PATTERN4,
- DP_TEST_PATTERN_CP2520_3 = DP_TEST_PATTERN_TRAINING_PATTERN4,
DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
/* link test patterns*/
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 11/12] drm/amd/display: stereo support
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 10/12] drm/amd/display: use CP2520-3 for PHY compliance automation Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
2017-03-28 21:09 ` [PATCH 12/12] drm/amd/display: obtain usHBR3En bit from BP 1 Harry Wentland
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Frame sequential, top-bottom and side-by-side support.
Change-Id: Iea9193028af358d66d5011f9a9971ce405603de7
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 34 +++++++++++++++++------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 61ca1e21ae66..8f53d7a9f4dd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -422,6 +422,11 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
bool sec_split = pipe_ctx->top_pipe &&
pipe_ctx->top_pipe->surface == pipe_ctx->surface;
+ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
+ stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
+ pri_split = false;
+ sec_split = false;
+ }
/* The actual clip is an intersection between stream
* source and surface clip
*/
@@ -532,14 +537,27 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip
stream->public.dst.y + stream->public.dst.height
- pipe_ctx->scl_data.recout.y;
- /* Handle hsplit */
- if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) {
- pipe_ctx->scl_data.recout.width /= 2;
- pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
- /* Floor primary pipe, ceil 2ndary pipe */
- pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
- } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
- pipe_ctx->scl_data.recout.width /= 2;
+ /* Handle h & vsplit */
+ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface ==
+ pipe_ctx->surface) {
+ if (stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_TOP_AND_BOTTOM) {
+ pipe_ctx->scl_data.recout.height /= 2;
+ pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height;
+ /* Floor primary pipe, ceil 2ndary pipe */
+ pipe_ctx->scl_data.recout.height += pipe_ctx->scl_data.recout.height % 2;
+ } else {
+ pipe_ctx->scl_data.recout.width /= 2;
+ pipe_ctx->scl_data.recout.x += pipe_ctx->scl_data.recout.width;
+ pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2;
+ }
+ } else if (pipe_ctx->bottom_pipe &&
+ pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) {
+ if (stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_TOP_AND_BOTTOM)
+ pipe_ctx->scl_data.recout.height /= 2;
+ else
+ pipe_ctx->scl_data.recout.width /= 2;
}
/* Unclipped recout offset = stream dst offset + ((surf dst offset - stream src offset)
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 12/12] drm/amd/display: obtain usHBR3En bit from BP 1
[not found] ` <20170328210955.11281-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2017-03-28 21:09 ` [PATCH 11/12] drm/amd/display: stereo support Harry Wentland
@ 2017-03-28 21:09 ` Harry Wentland
11 siblings, 0 replies; 13+ messages in thread
From: Harry Wentland @ 2017-03-28 21:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ding Wang
From: Ding Wang <Ding.Wang@amd.com>
ASICs using bios parser 1 don't check HBR3 capability as there is no such
a bit usHBR3En in ATOM_ENCODER_CAP_RECORDER.
Therefore, will use ATOM_ENCODER_CAP_RECORDER_V2 and thus obtain the usHBR3En
bit.
Change-Id: I05e3fa6bfcbe9e55cb3ea2ff736dfc3c0b1b8a9f
Signed-off-by: Ding Wang <ding.wang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 14 +++++++-------
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 50163a06a653..47a467688073 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -88,7 +88,7 @@ static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
static struct device_id device_type_from_device_id(uint16_t device_id);
static uint32_t signal_to_ss_id(enum as_signal_type signal);
static uint32_t get_support_mask_for_device_id(struct device_id device_id);
-static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
struct bios_parser *bp,
ATOM_OBJECT *object);
@@ -1837,7 +1837,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
ATOM_OBJECT *object;
- ATOM_ENCODER_CAP_RECORD *record = NULL;
+ ATOM_ENCODER_CAP_RECORD_V2 *record = NULL;
if (!info)
return BP_RESULT_BADINPUT;
@@ -1851,8 +1851,8 @@ static enum bp_result bios_parser_get_encoder_cap_info(
if (!record)
return BP_RESULT_NORECORD;
- info->DP_HBR2_CAP = record->usHBR2Cap;
info->DP_HBR2_EN = record->usHBR2En;
+ info->DP_HBR3_EN = record->usHBR3En;
return BP_RESULT_OK;
}
@@ -1867,9 +1867,9 @@ static enum bp_result bios_parser_get_encoder_cap_info(
* @return atom encoder cap record
*
* @note
- * search all records to find the ATOM_ENCODER_CAP_RECORD record
+ * search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record
*/
-static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
struct bios_parser *bp,
ATOM_OBJECT *object)
{
@@ -1899,8 +1899,8 @@ static ATOM_ENCODER_CAP_RECORD *get_encoder_cap_record(
if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
continue;
- if (sizeof(ATOM_ENCODER_CAP_RECORD) <= header->ucRecordSize)
- return (ATOM_ENCODER_CAP_RECORD *)header;
+ if (sizeof(ATOM_ENCODER_CAP_RECORD_V2) <= header->ucRecordSize)
+ return (ATOM_ENCODER_CAP_RECORD_V2 *)header;
}
return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index df116f86ab45..1a84ee0105da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -993,7 +993,7 @@ bool dce110_link_encoder_construct(
enc110->base.ctx->dc_bios, enc110->base.id,
&bp_cap_info)) {
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
- bp_cap_info.DP_HBR2_CAP;
+ bp_cap_info.DP_HBR2_EN;
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread