From: Antoine Tenart <antoine.tenart@free-electrons.com> To: herbert@gondor.apana.org.au, davem@davemloft.net, jason@lakedaemon.net, andrew@lunn.ch, gregory.clement@free-electrons.com, sebastian.hesselbarth@gmail.com Cc: Antoine Tenart <antoine.tenart@free-electrons.com>, linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, boris.brezillon@free-electrons.com, oferh@marvell.com, igall@marvell.com, nadavh@marvell.com Subject: [PATCH 1/7] Documentation/bindings: Document the SafeXel cryptographic engine driver Date: Wed, 29 Mar 2017 14:44:26 +0200 [thread overview] Message-ID: <20170329124432.27457-2-antoine.tenart@free-electrons.com> (raw) In-Reply-To: <20170329124432.27457-1-antoine.tenart@free-electrons.com> The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> --- .../bindings/crypto/inside-secure-safexcel.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt new file mode 100644 index 000000000000..ff56b9384fcc --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt @@ -0,0 +1,27 @@ +Inside Secure SafeXcel cryptographic engine + +Required properties: +- compatible: Should be "inside-secure,safexcel-eip197". +- reg: Base physical address of the engine and length of memory mapped region. +- interrupts: Interrupt numbers for the rings and engine. +- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". + +Optional properties: +- clocks: Reference to the crypto engine clock. + +Example: + + crypto: crypto@800000 { + compatible = "inside-secure,safexcel-eip197"; + reg = <0x800000 0x200000>; + interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", + "eip"; + clocks = <&cpm_syscon0 1 26>; + status = "disabled"; + }; -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: antoine.tenart@free-electrons.com (Antoine Tenart) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/7] Documentation/bindings: Document the SafeXel cryptographic engine driver Date: Wed, 29 Mar 2017 14:44:26 +0200 [thread overview] Message-ID: <20170329124432.27457-2-antoine.tenart@free-electrons.com> (raw) In-Reply-To: <20170329124432.27457-1-antoine.tenart@free-electrons.com> The Inside Secure Safexcel cryptographic engine is found on some Marvell SoCs (7k/8k). Document the bindings used by its driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> --- .../bindings/crypto/inside-secure-safexcel.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt new file mode 100644 index 000000000000..ff56b9384fcc --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt @@ -0,0 +1,27 @@ +Inside Secure SafeXcel cryptographic engine + +Required properties: +- compatible: Should be "inside-secure,safexcel-eip197". +- reg: Base physical address of the engine and length of memory mapped region. +- interrupts: Interrupt numbers for the rings and engine. +- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". + +Optional properties: +- clocks: Reference to the crypto engine clock. + +Example: + + crypto: crypto at 800000 { + compatible = "inside-secure,safexcel-eip197"; + reg = <0x800000 0x200000>; + interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", + "eip"; + clocks = <&cpm_syscon0 1 26>; + status = "disabled"; + }; -- 2.11.0
next prev parent reply other threads:[~2017-03-29 12:44 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-29 12:44 [PATCH 0/7] arm64: marvell: add cryptographic engine support for 7k/8k Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart [this message] 2017-03-29 12:44 ` [PATCH 1/7] Documentation/bindings: Document the SafeXel cryptographic engine driver Antoine Tenart 2017-03-29 12:44 ` [PATCH 2/7] crypto: inside-secure: add SafeXcel EIP197 crypto " Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-04-12 13:54 ` Robin Murphy 2017-04-12 13:54 ` Robin Murphy 2017-04-18 8:04 ` Antoine Tenart 2017-04-18 8:04 ` Antoine Tenart 2017-03-29 12:44 ` [PATCH 3/7] MAINTAINERS: add a maintainer for the Inside Secure crypto driver Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-03-29 12:44 ` [PATCH 4/7] arm64: marvell: dts: add crypto engine description for 7k/8k Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-04-12 8:36 ` Gregory CLEMENT 2017-04-12 8:36 ` Gregory CLEMENT 2017-04-12 8:56 ` Thomas Petazzoni 2017-04-12 8:56 ` Thomas Petazzoni 2017-04-18 7:34 ` Antoine Tenart 2017-04-18 7:34 ` Antoine Tenart 2017-03-29 12:44 ` [PATCH 5/7] arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-04-12 8:36 ` Gregory CLEMENT 2017-04-12 8:36 ` Gregory CLEMENT 2017-03-29 12:44 ` [PATCH 6/7] arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-04-12 8:37 ` Gregory CLEMENT 2017-04-12 8:37 ` Gregory CLEMENT 2017-03-29 12:44 ` [PATCH 7/7] arm64: defconfig: enable the Safexcel crypto engine as a module Antoine Tenart 2017-03-29 12:44 ` Antoine Tenart 2017-04-12 8:38 ` Gregory CLEMENT 2017-04-12 8:38 ` Gregory CLEMENT 2017-04-10 9:39 ` [PATCH 0/7] arm64: marvell: add cryptographic engine support for 7k/8k Herbert Xu 2017-04-10 9:39 ` Herbert Xu 2017-04-11 16:12 ` Gregory CLEMENT 2017-04-11 16:12 ` Gregory CLEMENT 2017-04-12 6:11 ` Herbert Xu 2017-04-12 6:11 ` Herbert Xu
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