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* [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1()
@ 2017-04-03 17:07 Jim Bride
  2017-04-03 17:42 ` Vivi, Rodrigo
  2017-04-03 17:55 ` ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 2 replies; 4+ messages in thread
From: Jim Bride @ 2017-04-03 17:07 UTC (permalink / raw)
  To: intel-gfx; +Cc: Wayne Boyer, Rodrigo Vivi

On SKL+ there is a bit in SRD_CTL that software is not supposed to
modify, but we currently clobber that bit when we enable PSR.  In
order to preserve the value of that bit, go ahead and read SRD_CTL and
do a field-wise setting of the various bits that we need to initialize
before writing the register back out.  Additionally, go ahead and
explicitly disable single-frame update since we aren't currently
supporting it.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Wayne Boyer <wayne.boyer@intel.com>

Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  3 +++
 drivers/gpu/drm/i915/intel_psr.c | 23 +++++++++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4..54d39e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3590,14 +3590,17 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
 #define   EDP_PSR_TP1_TP2_SEL			(0<<11)
 #define   EDP_PSR_TP1_TP3_SEL			(1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_MASK             (3<<8)
 #define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
 #define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
 #define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
+#define   EDP_PSR_TP1_TIME_MASK                 (0x3<<4)
 #define   EDP_PSR_TP1_TIME_500us		(0<<4)
 #define   EDP_PSR_TP1_TIME_100us		(1<<4)
 #define   EDP_PSR_TP1_TIME_2500us		(2<<4)
 #define   EDP_PSR_TP1_TIME_0us			(3<<4)
+#define   EDP_PSR_IDLE_FRAME_MASK               (0xf<<0)
 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
 
 #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c3780d0..a050859 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
 	 * with the 5 or 6 idle patterns.
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-	uint32_t val = EDP_PSR_ENABLE;
+	uint32_t val = I915_READ(EDP_PSR_CTL);
 
+	val |= EDP_PSR_ENABLE;
+
+	/* We always set the max sleep time to the maximum value, so
+	 * no need to zero out the field first.
+	 */
 	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+
+	val &= ~EDP_PSR_IDLE_FRAME_MASK;
 	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
+	val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
 	if (IS_HASWELL(dev_priv))
 		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
-	if (dev_priv->psr.link_standby)
+	if (dev_priv->psr.link_standby) {
 		val |= EDP_PSR_LINK_STANDBY;
 
+		/* SFU should only be enabled with link standby, but for
+		 * now we do not support it. */
+		val &= ~BDW_PSR_SINGLE_FRAME;
+	} else {
+		val &= ~EDP_PSR_LINK_STANDBY;
+		val &= ~BDW_PSR_SINGLE_FRAME;
+	}
+
+	val &= ~EDP_PSR_TP1_TIME_MASK;
 	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
 		val |= EDP_PSR_TP1_TIME_2500us;
 	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
@@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR_TP1_TIME_0us;
 
+	val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -309,6 +327,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR_TP2_TP3_TIME_0us;
 
+	val &= ~EDP_PSR_TP1_TP3_SEL;
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
 		val |= EDP_PSR_TP1_TP3_SEL;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1()
  2017-04-03 17:07 [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1() Jim Bride
@ 2017-04-03 17:42 ` Vivi, Rodrigo
  2017-04-03 22:05   ` Jim Bride
  2017-04-03 17:55 ` ✓ Fi.CI.BAT: success for " Patchwork
  1 sibling, 1 reply; 4+ messages in thread
From: Vivi, Rodrigo @ 2017-04-03 17:42 UTC (permalink / raw)
  To: jim.bride; +Cc: intel-gfx, Boyer, Wayne

On Mon, 2017-04-03 at 10:07 -0700, Jim Bride wrote:
> On SKL+ there is a bit in SRD_CTL that software is not supposed to
> modify, but we currently clobber that bit when we enable PSR.  In
> order to preserve the value of that bit, go ahead and read SRD_CTL and
> do a field-wise setting of the various bits that we need to initialize
> before writing the register back out.  Additionally, go ahead and
> explicitly disable single-frame update since we aren't currently
> supporting it.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Wayne Boyer <wayne.boyer@intel.com>
> 
> Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_psr.c | 23 +++++++++++++++++++++--
>  2 files changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 11b12f4..54d39e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3590,14 +3590,17 @@ enum {
>  #define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
>  #define   EDP_PSR_TP1_TP2_SEL			(0<<11)
>  #define   EDP_PSR_TP1_TP3_SEL			(1<<11)
> +#define   EDP_PSR_TP2_TP3_TIME_MASK             (3<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
>  #define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
> +#define   EDP_PSR_TP1_TIME_MASK                 (0x3<<4)
>  #define   EDP_PSR_TP1_TIME_500us		(0<<4)
>  #define   EDP_PSR_TP1_TIME_100us		(1<<4)
>  #define   EDP_PSR_TP1_TIME_2500us		(2<<4)
>  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
> +#define   EDP_PSR_IDLE_FRAME_MASK               (0xf<<0)
>  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
>  
>  #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index c3780d0..a050859 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
>  	 * with the 5 or 6 idle patterns.
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> -	uint32_t val = EDP_PSR_ENABLE;
> +	uint32_t val = I915_READ(EDP_PSR_CTL);
>  
> +	val |= EDP_PSR_ENABLE;
> +
> +	/* We always set the max sleep time to the maximum value, so
> +	 * no need to zero out the field first.
> +	 */

I believe it is better to zero out instead of adding a comment.
So we could play with max_sleep_time if needed.

Otherwise we shouldn't allow the flexible value here so we should create
a define EDP_PSR_MAX_SLEEP_TIME (0x1f << 20)
and here do a val |= EDP_PSR_MAX_SLEEP_TIME;

>  	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> +
> +	val &= ~EDP_PSR_IDLE_FRAME_MASK;
>  	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> +	val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
>  	if (IS_HASWELL(dev_priv))
>  		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>  
> -	if (dev_priv->psr.link_standby)
> +	if (dev_priv->psr.link_standby) {
>  		val |= EDP_PSR_LINK_STANDBY;
>  
> +		/* SFU should only be enabled with link standby, but for
> +		 * now we do not support it. */
> +		val &= ~BDW_PSR_SINGLE_FRAME;
> +	} else {
> +		val &= ~EDP_PSR_LINK_STANDBY;
> +		val &= ~BDW_PSR_SINGLE_FRAME;
> +	}
> +
> +	val &= ~EDP_PSR_TP1_TIME_MASK;
>  	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>  		val |= EDP_PSR_TP1_TIME_2500us;
>  	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> @@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR_TP1_TIME_0us;
>  
> +	val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> @@ -309,6 +327,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR_TP2_TP3_TIME_0us;
>  
> +	val &= ~EDP_PSR_TP1_TP3_SEL;
>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>  		val |= EDP_PSR_TP1_TP3_SEL;

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Clean-up intel_enable_source_psr1()
  2017-04-03 17:07 [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1() Jim Bride
  2017-04-03 17:42 ` Vivi, Rodrigo
@ 2017-04-03 17:55 ` Patchwork
  1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-04-03 17:55 UTC (permalink / raw)
  To: jim.bride; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: Clean-up intel_enable_source_psr1()
URL   : https://patchwork.freedesktop.org/series/22375/
State : success

== Summary ==

Series 22375v1 drm/i915/psr: Clean-up intel_enable_source_psr1()
https://patchwork.freedesktop.org/api/1.0/series/22375/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 430s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 432s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 577s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 509s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 547s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 487s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 481s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 410s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 406s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 424s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 485s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 467s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 458s
fi-kbl-7560u     total:278  pass:267  dwarn:1   dfail:0   fail:0   skip:10  time: 567s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 447s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 577s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 462s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 490s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 436s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 532s
fi-snb-2600      total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  time: 408s

5bc82ec7f62322a91ecf48fa966e68c876637fcd drm-tip: 2017y-04m-03d-16h-44m-48s UTC integration manifest
c8cb54e drm/i915/psr: Clean-up intel_enable_source_psr1()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4384/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1()
  2017-04-03 17:42 ` Vivi, Rodrigo
@ 2017-04-03 22:05   ` Jim Bride
  0 siblings, 0 replies; 4+ messages in thread
From: Jim Bride @ 2017-04-03 22:05 UTC (permalink / raw)
  To: Vivi, Rodrigo; +Cc: intel-gfx, Boyer, Wayne

On Mon, Apr 03, 2017 at 05:42:39PM +0000, Vivi, Rodrigo wrote:
> On Mon, 2017-04-03 at 10:07 -0700, Jim Bride wrote:
> > On SKL+ there is a bit in SRD_CTL that software is not supposed to
> > modify, but we currently clobber that bit when we enable PSR.  In
> > order to preserve the value of that bit, go ahead and read SRD_CTL and
> > do a field-wise setting of the various bits that we need to initialize
> > before writing the register back out.  Additionally, go ahead and
> > explicitly disable single-frame update since we aren't currently
> > supporting it.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Wayne Boyer <wayne.boyer@intel.com>
> > 
> > Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
> >  drivers/gpu/drm/i915/intel_psr.c | 23 +++++++++++++++++++++--
> >  2 files changed, 24 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 11b12f4..54d39e4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3590,14 +3590,17 @@ enum {
> >  #define   EDP_PSR_SKIP_AUX_EXIT			(1<<12)
> >  #define   EDP_PSR_TP1_TP2_SEL			(0<<11)
> >  #define   EDP_PSR_TP1_TP3_SEL			(1<<11)
> > +#define   EDP_PSR_TP2_TP3_TIME_MASK             (3<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_500us		(0<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_100us		(1<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2<<8)
> >  #define   EDP_PSR_TP2_TP3_TIME_0us		(3<<8)
> > +#define   EDP_PSR_TP1_TIME_MASK                 (0x3<<4)
> >  #define   EDP_PSR_TP1_TIME_500us		(0<<4)
> >  #define   EDP_PSR_TP1_TIME_100us		(1<<4)
> >  #define   EDP_PSR_TP1_TIME_2500us		(2<<4)
> >  #define   EDP_PSR_TP1_TIME_0us			(3<<4)
> > +#define   EDP_PSR_IDLE_FRAME_MASK               (0xf<<0)
> >  #define   EDP_PSR_IDLE_FRAME_SHIFT		0
> >  
> >  #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index c3780d0..a050859 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -280,17 +280,34 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> >  	 * with the 5 or 6 idle patterns.
> >  	 */
> >  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -	uint32_t val = EDP_PSR_ENABLE;
> > +	uint32_t val = I915_READ(EDP_PSR_CTL);
> >  
> > +	val |= EDP_PSR_ENABLE;
> > +
> > +	/* We always set the max sleep time to the maximum value, so
> > +	 * no need to zero out the field first.
> > +	 */
> 
> I believe it is better to zero out instead of adding a comment.
> So we could play with max_sleep_time if needed.
> 
> Otherwise we shouldn't allow the flexible value here so we should create
> a define EDP_PSR_MAX_SLEEP_TIME (0x1f << 20)
> and here do a val |= EDP_PSR_MAX_SLEEP_TIME;

That's fair.  I'll wait a bit in case there's further comments, and then
spin a new version without said comment and with zeroing out the field.

Jim


> >  	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > +
> > +	val &= ~EDP_PSR_IDLE_FRAME_MASK;
> >  	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> >  
> > +	val &= ~EDP_PSR_MIN_LINK_ENTRY_TIME_MASK;
> >  	if (IS_HASWELL(dev_priv))
> >  		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> >  
> > -	if (dev_priv->psr.link_standby)
> > +	if (dev_priv->psr.link_standby) {
> >  		val |= EDP_PSR_LINK_STANDBY;
> >  
> > +		/* SFU should only be enabled with link standby, but for
> > +		 * now we do not support it. */
> > +		val &= ~BDW_PSR_SINGLE_FRAME;
> > +	} else {
> > +		val &= ~EDP_PSR_LINK_STANDBY;
> > +		val &= ~BDW_PSR_SINGLE_FRAME;
> > +	}
> > +
> > +	val &= ~EDP_PSR_TP1_TIME_MASK;
> >  	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
> >  		val |= EDP_PSR_TP1_TIME_2500us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
> > @@ -300,6 +317,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> >  	else
> >  		val |= EDP_PSR_TP1_TIME_0us;
> >  
> > +	val &= ~EDP_PSR_TP2_TP3_TIME_MASK;
> >  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> >  		val |= EDP_PSR_TP2_TP3_TIME_2500us;
> >  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
> > @@ -309,6 +327,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> >  	else
> >  		val |= EDP_PSR_TP2_TP3_TIME_0us;
> >  
> > +	val &= ~EDP_PSR_TP1_TP3_SEL;
> >  	if (intel_dp_source_supports_hbr2(intel_dp) &&
> >  	    drm_dp_tps3_supported(intel_dp->dpcd))
> >  		val |= EDP_PSR_TP1_TP3_SEL;
> 
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-04-03 22:07 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-04-03 17:07 [PATCH] drm/i915/psr: Clean-up intel_enable_source_psr1() Jim Bride
2017-04-03 17:42 ` Vivi, Rodrigo
2017-04-03 22:05   ` Jim Bride
2017-04-03 17:55 ` ✓ Fi.CI.BAT: success for " Patchwork

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