All of lore.kernel.org
 help / color / mirror / Atom feed
From: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Jordan Lazare <Jordan.Lazare-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 13/16] drm/amd/display: Fill in vrefresh and min_vblank_time for dce8/dce10
Date: Mon, 3 Apr 2017 19:07:27 -0400	[thread overview]
Message-ID: <20170403230730.9884-14-harry.wentland@amd.com> (raw)
In-Reply-To: <20170403230730.9884-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>

From: Jordan Lazare <Jordan.Lazare@amd.com>

PPLib is now calling into DC to get vrefresh and min_vblank_time, but
since full bandwidth calcs are missing for those generations, the pplib
structures were never being filled. This change fills the currently
required fields to prevent screen corruption.

Change-Id: I5438407f2e3b85f108daa3dd52afd11f702dff84
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
 .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 21 +++++++++++++++++++++
 .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h |  5 +++++
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c |  8 ++++----
 .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h |  8 ++++++++
 .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c   |  2 ++
 5 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index bd8e19f1038b..f11044e0245c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -104,6 +104,26 @@ static bool dce100_enable_display_power_gating(
 		return false;
 }
 
+void dce100_pplib_apply_display_requirements(
+	struct core_dc *dc,
+	struct validate_context *context)
+{
+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+
+	pp_display_cfg->avail_mclk_switch_time_us =
+						dce110_get_min_vblank_time_us(context);
+
+	dce110_fill_display_configs(context, pp_display_cfg);
+
+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
+			struct dm_pp_display_configuration)) !=  0)
+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+
+	dc->prev_display_config = *pp_display_cfg;
+}
+
+
+
 static void set_displaymarks(
 		const struct core_dc *dc, struct validate_context *context)
 {
@@ -116,6 +136,7 @@ static void set_bandwidth(
 		bool decrease_allowed)
 {
 	dc->hwss.set_displaymarks(dc, context);
+	dce100_pplib_apply_display_requirements(dc, context);
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
index cf497ea605c8..f51d04a66a49 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
@@ -29,8 +29,13 @@
 #include "core_types.h"
 
 struct core_dc;
+struct validate_context;
 
 bool dce100_hw_sequencer_construct(struct core_dc *dc);
 
+void dce100_pplib_apply_display_requirements(
+	struct core_dc *dc,
+	struct validate_context *context);
+
 #endif /* __DC_HWSS_DCE100_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2a3a39e31717..839c34409c63 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2097,7 +2097,7 @@ static void init_hw(struct core_dc *dc)
 	}
 }
 
-static void fill_display_configs(
+void dce110_fill_display_configs(
 	const struct validate_context *context,
 	struct dm_pp_display_configuration *pp_display_cfg)
 {
@@ -2146,7 +2146,7 @@ static void fill_display_configs(
 	pp_display_cfg->display_count = num_cfgs;
 }
 
-static uint32_t get_min_vblank_time_us(const struct validate_context *context)
+uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
 {
 	uint8_t j;
 	uint32_t min_vertical_blank_time = -1;
@@ -2224,13 +2224,13 @@ static void pplib_apply_display_requirements(
 			= context->bw_results.required_sclk_deep_sleep;
 
 	pp_display_cfg->avail_mclk_switch_time_us =
-						get_min_vblank_time_us(context);
+						dce110_get_min_vblank_time_us(context);
 	/* TODO: dce11.2*/
 	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
 
 	pp_display_cfg->disp_clk_khz = context->dispclk_khz;
 
-	fill_display_configs(context, pp_display_cfg);
+	dce110_fill_display_configs(context, pp_display_cfg);
 
 	/* TODO: is this still applicable?*/
 	if (pp_display_cfg->display_count == 1) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index a6b4d0d2429f..52462c17b2e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -30,6 +30,8 @@
 
 #define GAMMA_HW_POINTS_NUM 256
 struct core_dc;
+struct validate_context;
+struct dm_pp_display_configuration;
 
 bool dce110_hw_sequencer_construct(struct core_dc *dc);
 
@@ -58,5 +60,11 @@ void dce110_power_down(struct core_dc *dc);
 
 void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
 
+void dce110_fill_display_configs(
+	const struct validate_context *context,
+	struct dm_pp_display_configuration *pp_display_cfg);
+
+uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context);
+
 #endif /* __DC_HWSS_DCE110_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
index 85a54d963f8d..9d4e7d8b836e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
@@ -31,6 +31,7 @@
 
 #include "dce/dce_hwseq.h"
 #include "dce110/dce110_hw_sequencer.h"
+#include "dce100/dce100_hw_sequencer.h"
 
 /* include DCE8 register header files */
 #include "dce/dce_8_0_d.h"
@@ -118,6 +119,7 @@ static void set_bandwidth(
 		bool decrease_allowed)
 {
 	dc->hwss.set_displaymarks(dc, context);
+	dce100_pplib_apply_display_requirements(dc, context);
 }
 
 
-- 
2.11.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2017-04-03 23:07 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-03 23:07 [PATCH 00/16] DC Patches Apr 3, 2017 Harry Wentland
     [not found] ` <20170403230730.9884-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-04-03 23:07   ` [PATCH 01/16] drm/amd/display: decouple per-crtc-plane model Harry Wentland
2017-04-03 23:07   ` [PATCH 02/16] drm/amd/display: Fix cleanup in amdgpu_dm_initialize_drm_device Harry Wentland
2017-04-03 23:07   ` [PATCH 03/16] drm/amd/display: update plane functionalities Harry Wentland
2017-04-03 23:07   ` [PATCH 04/16] drm/amd/display: remove surface validation against stream rect Harry Wentland
2017-04-03 23:07   ` [PATCH 05/16] drm/amd/display: refactor member referencing to improve readability Harry Wentland
2017-04-03 23:07   ` [PATCH 06/16] drm/amd/display: Temporary disable PSR for HBR2 & HBR3 Harry Wentland
2017-04-03 23:07   ` [PATCH 07/16] drm/amd/display: fix dce_calc surface pitch setting for non underlay pipes Harry Wentland
2017-04-03 23:07   ` [PATCH 08/16] drm/amd/display: Remove get_connector_for_link Harry Wentland
2017-04-03 23:07   ` [PATCH 09/16] drm/amd/display: Remove get_connector_for_sink Harry Wentland
2017-04-03 23:07   ` [PATCH 10/16] drm/amd/display: Fix i2c write flag Harry Wentland
2017-04-03 23:07   ` [PATCH 11/16] drm/amd/display: Refactor edid read Harry Wentland
2017-04-03 23:07   ` [PATCH 12/16] drm/amd/display: PSR Aux Channel and Static Screen Support Fix Harry Wentland
2017-04-03 23:07   ` Harry Wentland [this message]
2017-04-03 23:07   ` [PATCH 14/16] drm/amd/display: Ignore visible flag when check surface update type Harry Wentland
2017-04-03 23:07   ` [PATCH 15/16] drm/amd/display: Log clock source in error condition Harry Wentland
2017-04-03 23:07   ` [PATCH 16/16] drm/amd/display: Fix s3 hang on resume Harry Wentland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170403230730.9884-14-harry.wentland@amd.com \
    --to=harry.wentland-5c7gfcevmho@public.gmane.org \
    --cc=Jordan.Lazare-5C7GfCeVMHo@public.gmane.org \
    --cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.