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* [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state()
@ 2017-04-04 14:03 Tom St Denis
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Tom St Denis @ 2017-04-04 14:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Use new WREG32_FIELD_OFFSET() to clean up code.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++------------------------
 2 files changed, 15 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 86fba1af1cdd..0e746db61a72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1730,6 +1730,9 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
 #define WREG32_FIELD(reg, field, val)	\
 	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 
+#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
+	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+
 /*
  * BIOS helpers.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1f35497089a6..595dc14019dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6814,40 +6814,24 @@ static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
 					    unsigned int type,
 					    enum amdgpu_interrupt_state state)
 {
-	uint32_t tmp, target;
 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
 
 	BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ);
 
-	if (ring->me == 1)
-		target = mmCP_ME1_PIPE0_INT_CNTL;
-	else
-		target = mmCP_ME2_PIPE0_INT_CNTL;
-	target += ring->pipe;
-
 	switch (type) {
 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
-		if (state == AMDGPU_IRQ_STATE_DISABLE) {
-			tmp = RREG32(mmCPC_INT_CNTL);
-			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
-						 GENERIC2_INT_ENABLE, 0);
-			WREG32(mmCPC_INT_CNTL, tmp);
-
-			tmp = RREG32(target);
-			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
-						 GENERIC2_INT_ENABLE, 0);
-			WREG32(target, tmp);
-		} else {
-			tmp = RREG32(mmCPC_INT_CNTL);
-			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
-						 GENERIC2_INT_ENABLE, 1);
-			WREG32(mmCPC_INT_CNTL, tmp);
-
-			tmp = RREG32(target);
-			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
-						 GENERIC2_INT_ENABLE, 1);
-			WREG32(target, tmp);
-		}
+		WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE,
+			     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
+		if (ring->me == 1)
+			WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL,
+				     ring->pipe,
+				     GENERIC2_INT_ENABLE,
+				     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
+		else
+			WREG32_FIELD_OFFSET(CP_ME2_PIPE0_INT_CNTL,
+				     ring->pipe,
+				     GENERIC2_INT_ENABLE,
+				     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
 		break;
 	default:
 		BUG(); /* kiq only support GENERIC2_INT now */
-- 
2.12.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd()
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2017-04-04 14:03   ` Tom St Denis
  2017-04-04 14:03   ` [PATCH 3/5] drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register() Tom St Denis
                     ` (3 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-04-04 14:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Swap read/write pattern for WREG32_FIELD()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 595dc14019dd..3c43c10d0ada 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5301,11 +5301,7 @@ static void gfx_v8_0_inactive_hqd(struct amdgpu_device *adev,
 
 	vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 	if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
-		u32 tmp;
-		tmp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
-		tmp = REG_SET_FIELD(tmp, CP_HQD_DEQUEUE_REQUEST,
-				    DEQUEUE_REQ, 2);
-		WREG32(mmCP_HQD_DEQUEUE_REQUEST, tmp);
+		WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, 2);
 		for (i = 0; i < adev->usec_timeout; i++) {
 			if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
 				break;
-- 
2.12.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register()
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2017-04-04 14:03   ` [PATCH 2/5] drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd() Tom St Denis
@ 2017-04-04 14:03   ` Tom St Denis
  2017-04-04 14:03   ` [PATCH 4/5] drm/amd/amdgpu: de-numberify HQD_ACTIVE check Tom St Denis
                     ` (2 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-04-04 14:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Swap read/write pattern for WREG32_FIELD()

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3c43c10d0ada..d09d69b0d096 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4869,13 +4869,10 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	struct vi_mqd *mqd = ring->mqd_ptr;
-	uint32_t tmp;
 	int j;
 
 	/* disable wptr polling */
-	tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
-	tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-	WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
+	WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
 
 	WREG32(mmCP_HQD_EOP_BASE_ADDR, mqd->cp_hqd_eop_base_addr_lo);
 	WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, mqd->cp_hqd_eop_base_addr_hi);
@@ -4947,11 +4944,8 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring)
 	/* activate the queue */
 	WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
 
-	if (ring->use_doorbell) {
-		tmp = RREG32(mmCP_PQ_STATUS);
-		tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-		WREG32(mmCP_PQ_STATUS, tmp);
-	}
+	if (ring->use_doorbell)
+		WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
 
 	return 0;
 }
-- 
2.12.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amd/amdgpu: de-numberify HQD_ACTIVE check.
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2017-04-04 14:03   ` [PATCH 2/5] drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd() Tom St Denis
  2017-04-04 14:03   ` [PATCH 3/5] drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register() Tom St Denis
@ 2017-04-04 14:03   ` Tom St Denis
  2017-04-04 14:03   ` [PATCH 5/5] drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init() Tom St Denis
  2017-04-04 14:07   ` [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state() Christian König
  4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-04-04 14:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index d09d69b0d096..46e2367405de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4884,10 +4884,10 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring)
 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control);
 
 	/* disable the queue if it's active */
-	if (RREG32(mmCP_HQD_ACTIVE) & 1) {
+	if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
 		WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
 		for (j = 0; j < adev->usec_timeout; j++) {
-			if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
+			if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
 				break;
 			udelay(1);
 		}
-- 
2.12.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init()
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2017-04-04 14:03   ` [PATCH 4/5] drm/amd/amdgpu: de-numberify HQD_ACTIVE check Tom St Denis
@ 2017-04-04 14:03   ` Tom St Denis
  2017-04-04 14:07   ` [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state() Christian König
  4 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2017-04-04 14:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Clean up a toggle with ?:.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 46e2367405de..5a8e8aea99b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4774,14 +4774,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
 	mqd->cp_hqd_eop_control = tmp;
 
 	/* enable doorbell? */
-	tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
-
-	if (ring->use_doorbell)
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-					 DOORBELL_EN, 1);
-	else
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-					 DOORBELL_EN, 0);
+	tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
+			    CP_HQD_PQ_DOORBELL_CONTROL,
+			    DOORBELL_EN,
+			    ring->use_doorbell ? 1 : 0);
 
 	mqd->cp_hqd_pq_doorbell_control = tmp;
 
-- 
2.12.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state()
       [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2017-04-04 14:03   ` [PATCH 5/5] drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init() Tom St Denis
@ 2017-04-04 14:07   ` Christian König
  4 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2017-04-04 14:07 UTC (permalink / raw)
  To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Am 04.04.2017 um 16:03 schrieb Tom St Denis:
> Use new WREG32_FIELD_OFFSET() to clean up code.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com> for the whole 
series.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++------------------------
>   2 files changed, 15 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 86fba1af1cdd..0e746db61a72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1730,6 +1730,9 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
>   #define WREG32_FIELD(reg, field, val)	\
>   	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
>   
> +#define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
> +	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
> +
>   /*
>    * BIOS helpers.
>    */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 1f35497089a6..595dc14019dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6814,40 +6814,24 @@ static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
>   					    unsigned int type,
>   					    enum amdgpu_interrupt_state state)
>   {
> -	uint32_t tmp, target;
>   	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
>   
>   	BUG_ON(ring->funcs->type != AMDGPU_RING_TYPE_KIQ);
>   
> -	if (ring->me == 1)
> -		target = mmCP_ME1_PIPE0_INT_CNTL;
> -	else
> -		target = mmCP_ME2_PIPE0_INT_CNTL;
> -	target += ring->pipe;
> -
>   	switch (type) {
>   	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
> -		if (state == AMDGPU_IRQ_STATE_DISABLE) {
> -			tmp = RREG32(mmCPC_INT_CNTL);
> -			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
> -						 GENERIC2_INT_ENABLE, 0);
> -			WREG32(mmCPC_INT_CNTL, tmp);
> -
> -			tmp = RREG32(target);
> -			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
> -						 GENERIC2_INT_ENABLE, 0);
> -			WREG32(target, tmp);
> -		} else {
> -			tmp = RREG32(mmCPC_INT_CNTL);
> -			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
> -						 GENERIC2_INT_ENABLE, 1);
> -			WREG32(mmCPC_INT_CNTL, tmp);
> -
> -			tmp = RREG32(target);
> -			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
> -						 GENERIC2_INT_ENABLE, 1);
> -			WREG32(target, tmp);
> -		}
> +		WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE,
> +			     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
> +		if (ring->me == 1)
> +			WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL,
> +				     ring->pipe,
> +				     GENERIC2_INT_ENABLE,
> +				     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
> +		else
> +			WREG32_FIELD_OFFSET(CP_ME2_PIPE0_INT_CNTL,
> +				     ring->pipe,
> +				     GENERIC2_INT_ENABLE,
> +				     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
>   		break;
>   	default:
>   		BUG(); /* kiq only support GENERIC2_INT now */


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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-04-04 14:07 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-04 14:03 [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state() Tom St Denis
     [not found] ` <20170404140344.17441-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2017-04-04 14:03   ` [PATCH 2/5] drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd() Tom St Denis
2017-04-04 14:03   ` [PATCH 3/5] drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register() Tom St Denis
2017-04-04 14:03   ` [PATCH 4/5] drm/amd/amdgpu: de-numberify HQD_ACTIVE check Tom St Denis
2017-04-04 14:03   ` [PATCH 5/5] drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init() Tom St Denis
2017-04-04 14:07   ` [PATCH 1/5] drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state() Christian König

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