* [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. (V3s and R40 do not have it, as they have even no PRCM) This patch adds support for the ones on H3/A64. Some clock/reset values are reserved for easier extending the support to A31/A23, but for this I think some changes to the PRCM MFD should be made, see [1] (Although this is only a sketch). The r_pio device node is also added for A64, as the driver is already merged, and its depends (r_ccu) is now met. [1] https://github.com/wens/linux/commits/sunxi-ng-prcm Icenowy Zheng (5): dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: add support for PRCM CCUs arm64: allwinner: a64: add r_ccu node ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu arm64: allwinner: a64: add R_PIO pinctrl node .../devicetree/bindings/clock/sunxi-ccu.txt | 17 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++--- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 29 +++ drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 +++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 +++++ 9 files changed, 418 insertions(+), 32 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h -- 2.12.2 ^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: linux-arm-kernel Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. (V3s and R40 do not have it, as they have even no PRCM) This patch adds support for the ones on H3/A64. Some clock/reset values are reserved for easier extending the support to A31/A23, but for this I think some changes to the PRCM MFD should be made, see [1] (Although this is only a sketch). The r_pio device node is also added for A64, as the driver is already merged, and its depends (r_ccu) is now met. [1] https://github.com/wens/linux/commits/sunxi-ng-prcm Icenowy Zheng (5): dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: add support for PRCM CCUs arm64: allwinner: a64: add r_ccu node ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu arm64: allwinner: a64: add R_PIO pinctrl node .../devicetree/bindings/clock/sunxi-ccu.txt | 17 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++--- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 29 +++ drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 +++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 +++++ 9 files changed, 418 insertions(+), 32 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h -- 2.12.2 ^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. (V3s and R40 do not have it, as they have even no PRCM) This patch adds support for the ones on H3/A64. Some clock/reset values are reserved for easier extending the support to A31/A23, but for this I think some changes to the PRCM MFD should be made, see [1] (Although this is only a sketch). The r_pio device node is also added for A64, as the driver is already merged, and its depends (r_ccu) is now met. [1] https://github.com/wens/linux/commits/sunxi-ng-prcm Icenowy Zheng (5): dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: add support for PRCM CCUs arm64: allwinner: a64: add r_ccu node ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu arm64: allwinner: a64: add R_PIO pinctrl node .../devicetree/bindings/clock/sunxi-ccu.txt | 17 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++--- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 29 +++ drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 +++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 +++++ 9 files changed, 418 insertions(+), 32 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h -- 2.12.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng From: Icenowy Zheng <icenowy@aosc.xyz> Many Allwinner SoCs after A31 have a CCU in PRCM block. Give the ones on H3 and A64 compatible strings. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Rob Herring <robh@kernel.org> --- Changes in v4: - Add Rob's ACK. Changes in v3: - Removed frequency info of iosc in this device tree binding document. Changes in v2: - Add iosc for R_CCU's on H3/A64. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 68512aa398a9..e9c5a1d9834a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,9 +7,11 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" + - "allwinner,sun50i-a64-r-ccu" - "allwinner,sun50i-h5-ccu" - reg: Must contain the registers base address and length @@ -20,7 +22,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 -Example: +For the PRCM CCUs on H3/A64, one more clock is needed: +- "iosc": the SoC's internal frequency oscillator + +Example for generic CCU: ccu: clock@01c20000 { compatible = "allwinner,sun8i-h3-ccu"; reg = <0x01c20000 0x400>; @@ -29,3 +34,13 @@ ccu: clock@01c20000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Example for PRCM CCU: +r_ccu: clock@01f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Many Allwinner SoCs after A31 have a CCU in PRCM block. Give the ones on H3 and A64 compatible strings. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Rob Herring <robh@kernel.org> --- Changes in v4: - Add Rob's ACK. Changes in v3: - Removed frequency info of iosc in this device tree binding document. Changes in v2: - Add iosc for R_CCU's on H3/A64. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 68512aa398a9..e9c5a1d9834a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,9 +7,11 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" + - "allwinner,sun50i-a64-r-ccu" - "allwinner,sun50i-h5-ccu" - reg: Must contain the registers base address and length @@ -20,7 +22,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 -Example: +For the PRCM CCUs on H3/A64, one more clock is needed: +- "iosc": the SoC's internal frequency oscillator + +Example for generic CCU: ccu: clock at 01c20000 { compatible = "allwinner,sun8i-h3-ccu"; reg = <0x01c20000 0x400>; @@ -29,3 +34,13 @@ ccu: clock at 01c20000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Example for PRCM CCU: +r_ccu: clock at 01f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Many Allwinner SoCs after A31 have a CCU in PRCM block. Give the ones on H3 and A64 compatible strings. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Rob Herring <robh@kernel.org> --- Changes in v4: - Add Rob's ACK. Changes in v3: - Removed frequency info of iosc in this device tree binding document. Changes in v2: - Add iosc for R_CCU's on H3/A64. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 68512aa398a9..e9c5a1d9834a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,9 +7,11 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" + - "allwinner,sun50i-a64-r-ccu" - "allwinner,sun50i-h5-ccu" - reg: Must contain the registers base address and length @@ -20,7 +22,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 -Example: +For the PRCM CCUs on H3/A64, one more clock is needed: +- "iosc": the SoC's internal frequency oscillator + +Example for generic CCU: ccu: clock@01c20000 { compatible = "allwinner,sun8i-h3-ccu"; reg = <0x01c20000 0x400>; @@ -29,3 +34,13 @@ ccu: clock@01c20000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Example for PRCM CCU: +r_ccu: clock@01f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; -- 2.12.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> Many Allwinner SoCs after A31 have a CCU in PRCM block. Give the ones on H3 and A64 compatible strings. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- Changes in v4: - Add Rob's ACK. Changes in v3: - Removed frequency info of iosc in this device tree binding document. Changes in v2: - Add iosc for R_CCU's on H3/A64. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 68512aa398a9..e9c5a1d9834a 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -7,9 +7,11 @@ Required properties : - "allwinner,sun8i-a23-ccu" - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" + - "allwinner,sun8i-h3-r-ccu" - "allwinner,sun8i-v3s-ccu" - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" + - "allwinner,sun50i-a64-r-ccu" - "allwinner,sun50i-h5-ccu" - reg: Must contain the registers base address and length @@ -20,7 +22,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 -Example: +For the PRCM CCUs on H3/A64, one more clock is needed: +- "iosc": the SoC's internal frequency oscillator + +Example for generic CCU: ccu: clock@01c20000 { compatible = "allwinner,sun8i-h3-ccu"; reg = <0x01c20000 0x400>; @@ -29,3 +34,13 @@ ccu: clock@01c20000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Example for PRCM CCU: +r_ccu: clock@01f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 2/5] clk: sunxi-ng: add support for PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng From: Icenowy Zheng <icenowy@aosc.xyz> SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Add missing twd items in *_ccu_clks. Changes in v3: - Change osc32000 mux to iosc, as its frequency varies between SoCs. (And none of them is really 32000Hz) Changes in v2: - Replace all sun6i to sun8i, as this driver currently doesn't really support sun6i(A31). - Add osc32000 mux for ar100 clk. (Note: the frequency is proven to be wrong during the development of PATCH v3). - Rename some clocks. - Add gate of TWD (Trusted Watchdog). There's no reset for TWD. - Removed reset of PIO, which doesn't exist really. drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 ++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++ 6 files changed, 359 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8af8f4be8e3b..fbd3f8cd5c22 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -151,4 +151,10 @@ config SUN9I_A80_CCU default MACH_SUN9I depends on MACH_SUN9I || COMPILE_TEST +config SUN8I_R_CCU + bool "Support for Allwinner SoCs' PRCM CCUs" + select SUNXI_CCU_DIV + select SUNXI_CCU_GATE + default MACH_SUN8I || (ARCH_SUNXI && ARM64) + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6feaac0c5600..0ec02fe14c50 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o +obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c new file mode 100644 index 000000000000..0d027d53dbdf --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_nm.h" + +#include "ccu-sun8i-r.h" + +static const char * const ar100_parents[] = { "osc32k", "osc24M", + "pll-periph0", "iosc" }; + +static struct ccu_div ar100_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 16, + .width = 2, + + .variable_prediv = { + .index = 2, + .shift = 8, + .width = 5, + }, + }, + + .common = { + .reg = 0x00, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ar100", + ar100_parents, + &ccu_div_ops, + 0), + }, +}; + +static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); + +static struct ccu_div apb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + + .common = { + .reg = 0x0c, + .hw.init = CLK_HW_INIT("apb0", + "ahb0", + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", + 0x28, BIT(0), 0); +static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", + 0x28, BIT(1), 0); +static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", + 0x28, BIT(2), 0); +static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", + 0x28, BIT(3), 0); +static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", + 0x28, BIT(4), 0); +static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", + 0x28, BIT(6), 0); +static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", + 0x28, BIT(7), 0); + +static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + r_mod0_default_parents, 0x54, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static struct ccu_common *sun8i_h3_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct ccu_common *sun50i_a64_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_rsb_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_RSB] = { 0xb0, BIT(3) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { + .ccu_clks = sun8i_h3_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), + + .hw_clks = &sun8i_h3_r_hw_clks, + + .resets = sun8i_h3_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), +}; + +static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { + .ccu_clks = sun50i_a64_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), + + .hw_clks = &sun50i_a64_r_hw_clks, + + .resets = sun50i_a64_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), +}; + +static void __init sunxi_r_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *desc) +{ + void __iomem *reg; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + sunxi_ccu_probe(node, reg, desc); +} + +static void __init sun8i_h3_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); +} +CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", + sun8i_h3_r_ccu_setup); + +static void __init sun50i_a64_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", + sun50i_a64_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h new file mode 100644 index 000000000000..eaa431fd1d8f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h @@ -0,0 +1,27 @@ +/* + * Copyright 2016 Icenowy <icenowy@aosc.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN8I_R_H +#define _CCU_SUN8I_R_H_ + +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> + +/* AHB/APB bus clocks are not exported */ +#define CLK_AHB0 1 +#define CLK_APB0 2 + +#define CLK_NUMBER (CLK_APB0_TWD + 1) + +#endif /* _CCU_SUN8I_R_H */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h new file mode 100644 index 000000000000..779d20aa0d05 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-r-ccu.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_APB0_PIO 3 +#define CLK_APB0_IR 4 +#define CLK_APB0_TIMER 5 +#define CLK_APB0_RSB 6 +#define CLK_APB0_UART 7 +/* 8 is reserved for CLK_APB0_W1 on A31 */ +#define CLK_APB0_I2C 9 +#define CLK_APB0_TWD 10 + +#define CLK_IR 11 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h new file mode 100644 index 000000000000..4ba64f3d6fc9 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-r-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ + +#define RST_APB0_IR 0 +#define RST_APB0_TIMER 1 +#define RST_APB0_RSB 2 +#define RST_APB0_UART 3 +/* 4 is reserved for RST_APB0_W1 on A31 */ +#define RST_APB0_I2C 5 + +#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 2/5] clk: sunxi-ng: add support for PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Add missing twd items in *_ccu_clks. Changes in v3: - Change osc32000 mux to iosc, as its frequency varies between SoCs. (And none of them is really 32000Hz) Changes in v2: - Replace all sun6i to sun8i, as this driver currently doesn't really support sun6i(A31). - Add osc32000 mux for ar100 clk. (Note: the frequency is proven to be wrong during the development of PATCH v3). - Rename some clocks. - Add gate of TWD (Trusted Watchdog). There's no reset for TWD. - Removed reset of PIO, which doesn't exist really. drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 ++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++ 6 files changed, 359 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8af8f4be8e3b..fbd3f8cd5c22 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -151,4 +151,10 @@ config SUN9I_A80_CCU default MACH_SUN9I depends on MACH_SUN9I || COMPILE_TEST +config SUN8I_R_CCU + bool "Support for Allwinner SoCs' PRCM CCUs" + select SUNXI_CCU_DIV + select SUNXI_CCU_GATE + default MACH_SUN8I || (ARCH_SUNXI && ARM64) + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6feaac0c5600..0ec02fe14c50 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o +obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c new file mode 100644 index 000000000000..0d027d53dbdf --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_nm.h" + +#include "ccu-sun8i-r.h" + +static const char * const ar100_parents[] = { "osc32k", "osc24M", + "pll-periph0", "iosc" }; + +static struct ccu_div ar100_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 16, + .width = 2, + + .variable_prediv = { + .index = 2, + .shift = 8, + .width = 5, + }, + }, + + .common = { + .reg = 0x00, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ar100", + ar100_parents, + &ccu_div_ops, + 0), + }, +}; + +static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); + +static struct ccu_div apb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + + .common = { + .reg = 0x0c, + .hw.init = CLK_HW_INIT("apb0", + "ahb0", + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", + 0x28, BIT(0), 0); +static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", + 0x28, BIT(1), 0); +static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", + 0x28, BIT(2), 0); +static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", + 0x28, BIT(3), 0); +static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", + 0x28, BIT(4), 0); +static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", + 0x28, BIT(6), 0); +static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", + 0x28, BIT(7), 0); + +static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + r_mod0_default_parents, 0x54, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static struct ccu_common *sun8i_h3_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct ccu_common *sun50i_a64_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_rsb_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_RSB] = { 0xb0, BIT(3) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { + .ccu_clks = sun8i_h3_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), + + .hw_clks = &sun8i_h3_r_hw_clks, + + .resets = sun8i_h3_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), +}; + +static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { + .ccu_clks = sun50i_a64_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), + + .hw_clks = &sun50i_a64_r_hw_clks, + + .resets = sun50i_a64_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), +}; + +static void __init sunxi_r_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *desc) +{ + void __iomem *reg; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + sunxi_ccu_probe(node, reg, desc); +} + +static void __init sun8i_h3_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); +} +CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", + sun8i_h3_r_ccu_setup); + +static void __init sun50i_a64_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", + sun50i_a64_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h new file mode 100644 index 000000000000..eaa431fd1d8f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h @@ -0,0 +1,27 @@ +/* + * Copyright 2016 Icenowy <icenowy@aosc.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN8I_R_H +#define _CCU_SUN8I_R_H_ + +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> + +/* AHB/APB bus clocks are not exported */ +#define CLK_AHB0 1 +#define CLK_APB0 2 + +#define CLK_NUMBER (CLK_APB0_TWD + 1) + +#endif /* _CCU_SUN8I_R_H */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h new file mode 100644 index 000000000000..779d20aa0d05 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-r-ccu.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_APB0_PIO 3 +#define CLK_APB0_IR 4 +#define CLK_APB0_TIMER 5 +#define CLK_APB0_RSB 6 +#define CLK_APB0_UART 7 +/* 8 is reserved for CLK_APB0_W1 on A31 */ +#define CLK_APB0_I2C 9 +#define CLK_APB0_TWD 10 + +#define CLK_IR 11 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h new file mode 100644 index 000000000000..4ba64f3d6fc9 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-r-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ + +#define RST_APB0_IR 0 +#define RST_APB0_TIMER 1 +#define RST_APB0_RSB 2 +#define RST_APB0_UART 3 +/* 4 is reserved for RST_APB0_W1 on A31 */ +#define RST_APB0_I2C 5 + +#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 2/5] clk: sunxi-ng: add support for PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Add missing twd items in *_ccu_clks. Changes in v3: - Change osc32000 mux to iosc, as its frequency varies between SoCs. (And none of them is really 32000Hz) Changes in v2: - Replace all sun6i to sun8i, as this driver currently doesn't really support sun6i(A31). - Add osc32000 mux for ar100 clk. (Note: the frequency is proven to be wrong during the development of PATCH v3). - Rename some clocks. - Add gate of TWD (Trusted Watchdog). There's no reset for TWD. - Removed reset of PIO, which doesn't exist really. drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 ++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++ 6 files changed, 359 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8af8f4be8e3b..fbd3f8cd5c22 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -151,4 +151,10 @@ config SUN9I_A80_CCU default MACH_SUN9I depends on MACH_SUN9I || COMPILE_TEST +config SUN8I_R_CCU + bool "Support for Allwinner SoCs' PRCM CCUs" + select SUNXI_CCU_DIV + select SUNXI_CCU_GATE + default MACH_SUN8I || (ARCH_SUNXI && ARM64) + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6feaac0c5600..0ec02fe14c50 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o +obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c new file mode 100644 index 000000000000..0d027d53dbdf --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_nm.h" + +#include "ccu-sun8i-r.h" + +static const char * const ar100_parents[] = { "osc32k", "osc24M", + "pll-periph0", "iosc" }; + +static struct ccu_div ar100_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 16, + .width = 2, + + .variable_prediv = { + .index = 2, + .shift = 8, + .width = 5, + }, + }, + + .common = { + .reg = 0x00, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ar100", + ar100_parents, + &ccu_div_ops, + 0), + }, +}; + +static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); + +static struct ccu_div apb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + + .common = { + .reg = 0x0c, + .hw.init = CLK_HW_INIT("apb0", + "ahb0", + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", + 0x28, BIT(0), 0); +static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", + 0x28, BIT(1), 0); +static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", + 0x28, BIT(2), 0); +static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", + 0x28, BIT(3), 0); +static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", + 0x28, BIT(4), 0); +static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", + 0x28, BIT(6), 0); +static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", + 0x28, BIT(7), 0); + +static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + r_mod0_default_parents, 0x54, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static struct ccu_common *sun8i_h3_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct ccu_common *sun50i_a64_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_rsb_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_RSB] = { 0xb0, BIT(3) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { + .ccu_clks = sun8i_h3_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), + + .hw_clks = &sun8i_h3_r_hw_clks, + + .resets = sun8i_h3_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), +}; + +static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { + .ccu_clks = sun50i_a64_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), + + .hw_clks = &sun50i_a64_r_hw_clks, + + .resets = sun50i_a64_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), +}; + +static void __init sunxi_r_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *desc) +{ + void __iomem *reg; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + sunxi_ccu_probe(node, reg, desc); +} + +static void __init sun8i_h3_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); +} +CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", + sun8i_h3_r_ccu_setup); + +static void __init sun50i_a64_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", + sun50i_a64_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h new file mode 100644 index 000000000000..eaa431fd1d8f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h @@ -0,0 +1,27 @@ +/* + * Copyright 2016 Icenowy <icenowy@aosc.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN8I_R_H +#define _CCU_SUN8I_R_H_ + +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> + +/* AHB/APB bus clocks are not exported */ +#define CLK_AHB0 1 +#define CLK_APB0 2 + +#define CLK_NUMBER (CLK_APB0_TWD + 1) + +#endif /* _CCU_SUN8I_R_H */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h new file mode 100644 index 000000000000..779d20aa0d05 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-r-ccu.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_APB0_PIO 3 +#define CLK_APB0_IR 4 +#define CLK_APB0_TIMER 5 +#define CLK_APB0_RSB 6 +#define CLK_APB0_UART 7 +/* 8 is reserved for CLK_APB0_W1 on A31 */ +#define CLK_APB0_I2C 9 +#define CLK_APB0_TWD 10 + +#define CLK_IR 11 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h new file mode 100644 index 000000000000..4ba64f3d6fc9 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-r-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ + +#define RST_APB0_IR 0 +#define RST_APB0_TIMER 1 +#define RST_APB0_RSB 2 +#define RST_APB0_UART 3 +/* 4 is reserved for RST_APB0_W1 on A31 */ +#define RST_APB0_I2C 5 + +#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ -- 2.12.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 2/5] clk: sunxi-ng: add support for PRCM CCUs @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> --- Changes in v4: - Add missing twd items in *_ccu_clks. Changes in v3: - Change osc32000 mux to iosc, as its frequency varies between SoCs. (And none of them is really 32000Hz) Changes in v2: - Replace all sun6i to sun8i, as this driver currently doesn't really support sun6i(A31). - Add osc32000 mux for ar100 clk. (Note: the frequency is proven to be wrong during the development of PATCH v3). - Rename some clocks. - Add gate of TWD (Trusted Watchdog). There's no reset for TWD. - Removed reset of PIO, which doesn't exist really. drivers/clk/sunxi-ng/Kconfig | 6 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-r.c | 213 ++++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-r.h | 27 ++++ include/dt-bindings/clock/sun8i-r-ccu.h | 59 +++++++++ include/dt-bindings/reset/sun8i-r-ccu.h | 53 ++++++++ 6 files changed, 359 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r.h create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8af8f4be8e3b..fbd3f8cd5c22 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -151,4 +151,10 @@ config SUN9I_A80_CCU default MACH_SUN9I depends on MACH_SUN9I || COMPILE_TEST +config SUN8I_R_CCU + bool "Support for Allwinner SoCs' PRCM CCUs" + select SUNXI_CCU_DIV + select SUNXI_CCU_GATE + default MACH_SUN8I || (ARCH_SUNXI && ARM64) + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 6feaac0c5600..0ec02fe14c50 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o +obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c new file mode 100644 index 000000000000..0d027d53dbdf --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_nm.h" + +#include "ccu-sun8i-r.h" + +static const char * const ar100_parents[] = { "osc32k", "osc24M", + "pll-periph0", "iosc" }; + +static struct ccu_div ar100_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 16, + .width = 2, + + .variable_prediv = { + .index = 2, + .shift = 8, + .width = 5, + }, + }, + + .common = { + .reg = 0x00, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ar100", + ar100_parents, + &ccu_div_ops, + 0), + }, +}; + +static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); + +static struct ccu_div apb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + + .common = { + .reg = 0x0c, + .hw.init = CLK_HW_INIT("apb0", + "ahb0", + &ccu_div_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", + 0x28, BIT(0), 0); +static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", + 0x28, BIT(1), 0); +static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", + 0x28, BIT(2), 0); +static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", + 0x28, BIT(3), 0); +static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", + 0x28, BIT(4), 0); +static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", + 0x28, BIT(6), 0); +static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", + 0x28, BIT(7), 0); + +static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" }; +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", + r_mod0_default_parents, 0x54, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static struct ccu_common *sun8i_h3_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct ccu_common *sun50i_a64_r_ccu_clks[] = { + &ar100_clk.common, + &apb0_clk.common, + &apb0_pio_clk.common, + &apb0_ir_clk.common, + &apb0_timer_clk.common, + &apb0_rsb_clk.common, + &apb0_uart_clk.common, + &apb0_i2c_clk.common, + &apb0_twd_clk.common, + &ir_clk.common, +}; + +static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { + .hws = { + [CLK_AR100] = &ar100_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, + [CLK_APB0_IR] = &apb0_ir_clk.common.hw, + [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, + [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, + [CLK_APB0_UART] = &apb0_uart_clk.common.hw, + [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, + [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, + [CLK_IR] = &ir_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { + [RST_APB0_IR] = { 0xb0, BIT(1) }, + [RST_APB0_TIMER] = { 0xb0, BIT(2) }, + [RST_APB0_RSB] = { 0xb0, BIT(3) }, + [RST_APB0_UART] = { 0xb0, BIT(4) }, + [RST_APB0_I2C] = { 0xb0, BIT(6) }, +}; + +static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { + .ccu_clks = sun8i_h3_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), + + .hw_clks = &sun8i_h3_r_hw_clks, + + .resets = sun8i_h3_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), +}; + +static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { + .ccu_clks = sun50i_a64_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), + + .hw_clks = &sun50i_a64_r_hw_clks, + + .resets = sun50i_a64_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), +}; + +static void __init sunxi_r_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *desc) +{ + void __iomem *reg; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) { + pr_err("%s: Could not map the clock registers\n", + of_node_full_name(node)); + return; + } + + sunxi_ccu_probe(node, reg, desc); +} + +static void __init sun8i_h3_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); +} +CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", + sun8i_h3_r_ccu_setup); + +static void __init sun50i_a64_r_ccu_setup(struct device_node *node) +{ + sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); +} +CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", + sun50i_a64_r_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h new file mode 100644 index 000000000000..eaa431fd1d8f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h @@ -0,0 +1,27 @@ +/* + * Copyright 2016 Icenowy <icenowy-ymACFijhrKM@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN8I_R_H +#define _CCU_SUN8I_R_H_ + +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> + +/* AHB/APB bus clocks are not exported */ +#define CLK_AHB0 1 +#define CLK_APB0 2 + +#define CLK_NUMBER (CLK_APB0_TWD + 1) + +#endif /* _CCU_SUN8I_R_H */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h new file mode 100644 index 000000000000..779d20aa0d05 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-r-ccu.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_APB0_PIO 3 +#define CLK_APB0_IR 4 +#define CLK_APB0_TIMER 5 +#define CLK_APB0_RSB 6 +#define CLK_APB0_UART 7 +/* 8 is reserved for CLK_APB0_W1 on A31 */ +#define CLK_APB0_I2C 9 +#define CLK_APB0_TWD 10 + +#define CLK_IR 11 + +#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h new file mode 100644 index 000000000000..4ba64f3d6fc9 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-r-ccu.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ + +#define RST_APB0_IR 0 +#define RST_APB0_TIMER 1 +#define RST_APB0_RSB 2 +#define RST_APB0_UART 3 +/* 4 is reserved for RST_APB0_W1 on A31 */ +#define RST_APB0_I2C 5 + +#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng From: Icenowy Zheng <icenowy@aosc.xyz> A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc, which is 16MHz plus minus 30%, according to the RTC chapter of the user manual and our experiences on A33. Changes in v2: - Add osc32000. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1c64ea2d23f9..1d4e5bcced0c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -98,6 +98,14 @@ clock-output-names = "osc32k"; }; + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -392,5 +400,14 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc, which is 16MHz plus minus 30%, according to the RTC chapter of the user manual and our experiences on A33. Changes in v2: - Add osc32000. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1c64ea2d23f9..1d4e5bcced0c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -98,6 +98,14 @@ clock-output-names = "osc32k"; }; + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -392,5 +400,14 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + r_ccu: clock at 1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc, which is 16MHz plus minus 30%, according to the RTC chapter of the user manual and our experiences on A33. Changes in v2: - Add osc32000. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1c64ea2d23f9..1d4e5bcced0c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -98,6 +98,14 @@ clock-output-names = "osc32k"; }; + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -392,5 +400,14 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- 2.12.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc, which is 16MHz plus minus 30%, according to the RTC chapter of the user manual and our experiences on A33. Changes in v2: - Add osc32000. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1c64ea2d23f9..1d4e5bcced0c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -98,6 +98,14 @@ clock-output-names = "osc32k"; }; + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -392,5 +400,14 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng From: Icenowy Zheng <icenowy@aosc.xyz> Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6640ebfa6419..1aeeacb3a884 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -68,31 +68,12 @@ clock-output-names = "osc32k"; }; - apb0: apb0_clk { - compatible = "fixed-factor-clock"; + iosc: internal-osc-clk { #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; }; }; @@ -576,9 +557,12 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -589,9 +573,9 @@ ir: ir@01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; + clocks = <&r_ccu 4>, <&r_ccu 11>; clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; + resets = <&r_ccu 0>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x40>; status = "disabled"; @@ -601,9 +585,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; interrupt-controller; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6640ebfa6419..1aeeacb3a884 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -68,31 +68,12 @@ clock-output-names = "osc32k"; }; - apb0: apb0_clk { - compatible = "fixed-factor-clock"; + iosc: internal-osc-clk { #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk at 01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk at 01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; }; }; @@ -576,9 +557,12 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - apb0_reset: reset at 01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; + r_ccu: clock at 1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -589,9 +573,9 @@ ir: ir at 01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; + clocks = <&r_ccu 4>, <&r_ccu 11>; clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; + resets = <&r_ccu 0>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x40>; status = "disabled"; @@ -601,9 +585,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; interrupt-controller; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6640ebfa6419..1aeeacb3a884 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -68,31 +68,12 @@ clock-output-names = "osc32k"; }; - apb0: apb0_clk { - compatible = "fixed-factor-clock"; + iosc: internal-osc-clk { #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; }; }; @@ -576,9 +557,12 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -589,9 +573,9 @@ ir: ir@01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; + clocks = <&r_ccu 4>, <&r_ccu 11>; clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; + resets = <&r_ccu 0>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x40>; status = "disabled"; @@ -601,9 +585,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; interrupt-controller; -- 2.12.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-04-04 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:50 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> Now we have driver for the PRCM CCU, switch to use it instead of old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . The mux 3 of R_CCU is still the internal oscillator, which is said to be 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two H3 boards and one H5 board. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> --- Changes in v4: - Temporarily dropped the CCU headers. Changes in v3: - Change osc32000 to iosc. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6640ebfa6419..1aeeacb3a884 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -68,31 +68,12 @@ clock-output-names = "osc32k"; }; - apb0: apb0_clk { - compatible = "fixed-factor-clock"; + iosc: internal-osc-clk { #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; }; }; @@ -576,9 +557,12 @@ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; - apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; #reset-cells = <1>; }; @@ -589,9 +573,9 @@ ir: ir@01f02000 { compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; + clocks = <&r_ccu 4>, <&r_ccu 11>; clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; + resets = <&r_ccu 0>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01f02000 0x40>; status = "disabled"; @@ -601,9 +585,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_reset 0>; gpio-controller; #gpio-cells = <3>; interrupt-controller; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-19 22:59 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: Ondřej Jirman @ 2017-07-19 22:59 UTC (permalink / raw) To: icenowy, Maxime Ripard, Chen-Yu Tsai Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng [-- Attachment #1: Type: text/plain, Size: 4496 bytes --] Hi, Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: > From: Icenowy Zheng <icenowy@aosc.xyz> > > Now we have driver for the PRCM CCU, switch to use it instead of > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > The mux 3 of R_CCU is still the internal oscillator, which is said to be > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two > H3 boards and one H5 board. There's issue with the new r_ccu that breaks r_i2c. (no devices can be found on the bus). Reverting this patch fixes the issue with the I2C controller. (everything else being the same) Here's the code I'm using: https://github.com/megous/linux/commits/oran ge-pi-4.12 The last commit is the revert. The issue manifests itself by non-working DVFS, because kernel lacks access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng clock driver (sun8i-r). Relevant difference in registers between working/non-working state is just this (diff -u): 0x01f02400 = 0x00000000 0x01f02404 = 0x00000000 -0x01f02408 = 0x00000091 +0x01f02408 = 0x00000095 DATA register inisde the I2C controller 0x01f0240c = 0x00000044 0x01f02410 = 0x000000f8 -0x01f02414 = 0x00000059 +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller 0x01f02418 = 0x00000000 0x01f0241c = 0x00000000 0x01f02420 = 0x0000003a It looks like the new sunxi-ng clock driver causes the I2C driver to not correctly configure the CLOCK register. I don't know why and I'm not sure how to deal with this. Any ideas what can I do next? thank you and regards, o. > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > --- > Changes in v4: > - Temporarily dropped the CCU headers. > Changes in v3: > - Change osc32000 to iosc. > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 31 deletions(-) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 6640ebfa6419..1aeeacb3a884 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -68,31 +68,12 @@ > clock-output-names = "osc32k"; > }; > > - apb0: apb0_clk { > - compatible = "fixed-factor-clock"; > + iosc: internal-osc-clk { > #clock-cells = <0>; > - clock-div = <1>; > - clock-mult = <1>; > - clocks = <&osc24M>; > - clock-output-names = "apb0"; > - }; > - > - apb0_gates: clk@01f01428 { > - compatible = "allwinner,sun8i-h3-apb0-gates-clk", > - "allwinner,sun4i-a10-gates-clk"; > - reg = <0x01f01428 0x4>; > - #clock-cells = <1>; > - clocks = <&apb0>; > - clock-indices = <0>, <1>; > - clock-output-names = "apb0_pio", "apb0_ir"; > - }; > - > - ir_clk: ir_clk@01f01454 { > - compatible = "allwinner,sun4i-a10-mod0-clk"; > - reg = <0x01f01454 0x4>; > - #clock-cells = <0>; > - clocks = <&osc32k>, <&osc24M>; > - clock-output-names = "ir"; > + compatible = "fixed-clock"; > + clock-frequency = <16000000>; > + clock-accuracy = <300000000>; > + clock-output-names = "iosc"; > }; > }; > > @@ -576,9 +557,12 @@ > <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > }; > > - apb0_reset: reset@01f014b0 { > - reg = <0x01f014b0 0x4>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > + r_ccu: clock@1f01400 { > + compatible = "allwinner,sun50i-a64-r-ccu"; > + reg = <0x01f01400 0x100>; > + clocks = <&osc24M>, <&osc32k>, <&iosc>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > #reset-cells = <1>; > }; > > @@ -589,9 +573,9 @@ > > ir: ir@01f02000 { > compatible = "allwinner,sun5i-a13-ir"; > - clocks = <&apb0_gates 1>, <&ir_clk>; > + clocks = <&r_ccu 4>, <&r_ccu 11>; > clock-names = "apb", "ir"; > - resets = <&apb0_reset 1>; > + resets = <&r_ccu 0>; > interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x01f02000 0x40>; > status = "disabled"; > @@ -601,9 +585,8 @@ > compatible = "allwinner,sun8i-h3-r-pinctrl"; > reg = <0x01f02c00 0x400>; > interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; > + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; > clock-names = "apb", "hosc", "losc"; > - resets = <&apb0_reset 0>; > gpio-controller; > #gpio-cells = <3>; > interrupt-controller; > -- > 2.12.2 > [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 850 bytes --] ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-19 22:59 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: Ondřej Jirman @ 2017-07-19 22:59 UTC (permalink / raw) To: linux-arm-kernel Hi, Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: > From: Icenowy Zheng <icenowy@aosc.xyz> > > Now we have driver for the PRCM CCU, switch to use it instead of > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > The mux 3 of R_CCU is still the internal oscillator, which is said to be > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two > H3 boards and one H5 board. There's issue with the new r_ccu that breaks r_i2c. (no devices can be found on the bus). Reverting this patch fixes the issue with the I2C controller. (everything else being the same) Here's the code I'm using: https://github.com/megous/linux/commits/oran ge-pi-4.12 The last commit is the revert. The issue manifests itself by non-working DVFS, because kernel lacks access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng clock driver (sun8i-r). Relevant difference in registers between working/non-working state is just this (diff -u): 0x01f02400 = 0x00000000 0x01f02404 = 0x00000000 -0x01f02408 = 0x00000091 +0x01f02408 = 0x00000095 DATA register inisde the I2C controller 0x01f0240c = 0x00000044 0x01f02410 = 0x000000f8 -0x01f02414 = 0x00000059 +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller 0x01f02418 = 0x00000000 0x01f0241c = 0x00000000 0x01f02420 = 0x0000003a It looks like the new sunxi-ng clock driver causes the I2C driver to not correctly configure the CLOCK register. I don't know why and I'm not sure how to deal with this. Any ideas what can I do next? thank you and regards, o. > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > --- > Changes in v4: > - Temporarily dropped the CCU headers. > Changes in v3: > - Change osc32000 to iosc. > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 31 deletions(-) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 6640ebfa6419..1aeeacb3a884 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -68,31 +68,12 @@ > clock-output-names = "osc32k"; > }; > > - apb0: apb0_clk { > - compatible = "fixed-factor-clock"; > + iosc: internal-osc-clk { > #clock-cells = <0>; > - clock-div = <1>; > - clock-mult = <1>; > - clocks = <&osc24M>; > - clock-output-names = "apb0"; > - }; > - > - apb0_gates: clk at 01f01428 { > - compatible = "allwinner,sun8i-h3-apb0-gates-clk", > - "allwinner,sun4i-a10-gates-clk"; > - reg = <0x01f01428 0x4>; > - #clock-cells = <1>; > - clocks = <&apb0>; > - clock-indices = <0>, <1>; > - clock-output-names = "apb0_pio", "apb0_ir"; > - }; > - > - ir_clk: ir_clk at 01f01454 { > - compatible = "allwinner,sun4i-a10-mod0-clk"; > - reg = <0x01f01454 0x4>; > - #clock-cells = <0>; > - clocks = <&osc32k>, <&osc24M>; > - clock-output-names = "ir"; > + compatible = "fixed-clock"; > + clock-frequency = <16000000>; > + clock-accuracy = <300000000>; > + clock-output-names = "iosc"; > }; > }; > > @@ -576,9 +557,12 @@ > <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > }; > > - apb0_reset: reset at 01f014b0 { > - reg = <0x01f014b0 0x4>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > + r_ccu: clock at 1f01400 { > + compatible = "allwinner,sun50i-a64-r-ccu"; > + reg = <0x01f01400 0x100>; > + clocks = <&osc24M>, <&osc32k>, <&iosc>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > #reset-cells = <1>; > }; > > @@ -589,9 +573,9 @@ > > ir: ir at 01f02000 { > compatible = "allwinner,sun5i-a13-ir"; > - clocks = <&apb0_gates 1>, <&ir_clk>; > + clocks = <&r_ccu 4>, <&r_ccu 11>; > clock-names = "apb", "ir"; > - resets = <&apb0_reset 1>; > + resets = <&r_ccu 0>; > interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x01f02000 0x40>; > status = "disabled"; > @@ -601,9 +585,8 @@ > compatible = "allwinner,sun8i-h3-r-pinctrl"; > reg = <0x01f02c00 0x400>; > interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; > + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; > clock-names = "apb", "hosc", "losc"; > - resets = <&apb0_reset 0>; > gpio-controller; > #gpio-cells = <3>; > interrupt-controller; > -- > 2.12.2 > -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 850 bytes Desc: This is a digitally signed message part URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170720/c8772b79/attachment-0001.sig> ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-19 22:59 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: 'Ondřej Jirman' via linux-sunxi @ 2017-07-19 22:59 UTC (permalink / raw) To: icenowy-h8G6r0blFSE, Maxime Ripard, Chen-Yu Tsai Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng [-- Attachment #1: Type: text/plain, Size: 4860 bytes --] Hi, Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: > From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> > > Now we have driver for the PRCM CCU, switch to use it instead of > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > The mux 3 of R_CCU is still the internal oscillator, which is said to be > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two > H3 boards and one H5 board. There's issue with the new r_ccu that breaks r_i2c. (no devices can be found on the bus). Reverting this patch fixes the issue with the I2C controller. (everything else being the same) Here's the code I'm using: https://github.com/megous/linux/commits/oran ge-pi-4.12 The last commit is the revert. The issue manifests itself by non-working DVFS, because kernel lacks access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng clock driver (sun8i-r). Relevant difference in registers between working/non-working state is just this (diff -u): 0x01f02400 = 0x00000000 0x01f02404 = 0x00000000 -0x01f02408 = 0x00000091 +0x01f02408 = 0x00000095 DATA register inisde the I2C controller 0x01f0240c = 0x00000044 0x01f02410 = 0x000000f8 -0x01f02414 = 0x00000059 +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller 0x01f02418 = 0x00000000 0x01f0241c = 0x00000000 0x01f02420 = 0x0000003a It looks like the new sunxi-ng clock driver causes the I2C driver to not correctly configure the CLOCK register. I don't know why and I'm not sure how to deal with this. Any ideas what can I do next? thank you and regards, o. > Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> > --- > Changes in v4: > - Temporarily dropped the CCU headers. > Changes in v3: > - Change osc32000 to iosc. > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 ++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 31 deletions(-) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 6640ebfa6419..1aeeacb3a884 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -68,31 +68,12 @@ > clock-output-names = "osc32k"; > }; > > - apb0: apb0_clk { > - compatible = "fixed-factor-clock"; > + iosc: internal-osc-clk { > #clock-cells = <0>; > - clock-div = <1>; > - clock-mult = <1>; > - clocks = <&osc24M>; > - clock-output-names = "apb0"; > - }; > - > - apb0_gates: clk@01f01428 { > - compatible = "allwinner,sun8i-h3-apb0-gates-clk", > - "allwinner,sun4i-a10-gates-clk"; > - reg = <0x01f01428 0x4>; > - #clock-cells = <1>; > - clocks = <&apb0>; > - clock-indices = <0>, <1>; > - clock-output-names = "apb0_pio", "apb0_ir"; > - }; > - > - ir_clk: ir_clk@01f01454 { > - compatible = "allwinner,sun4i-a10-mod0-clk"; > - reg = <0x01f01454 0x4>; > - #clock-cells = <0>; > - clocks = <&osc32k>, <&osc24M>; > - clock-output-names = "ir"; > + compatible = "fixed-clock"; > + clock-frequency = <16000000>; > + clock-accuracy = <300000000>; > + clock-output-names = "iosc"; > }; > }; > > @@ -576,9 +557,12 @@ > <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > }; > > - apb0_reset: reset@01f014b0 { > - reg = <0x01f014b0 0x4>; > - compatible = "allwinner,sun6i-a31-clock-reset"; > + r_ccu: clock@1f01400 { > + compatible = "allwinner,sun50i-a64-r-ccu"; > + reg = <0x01f01400 0x100>; > + clocks = <&osc24M>, <&osc32k>, <&iosc>; > + clock-names = "hosc", "losc", "iosc"; > + #clock-cells = <1>; > #reset-cells = <1>; > }; > > @@ -589,9 +573,9 @@ > > ir: ir@01f02000 { > compatible = "allwinner,sun5i-a13-ir"; > - clocks = <&apb0_gates 1>, <&ir_clk>; > + clocks = <&r_ccu 4>, <&r_ccu 11>; > clock-names = "apb", "ir"; > - resets = <&apb0_reset 1>; > + resets = <&r_ccu 0>; > interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x01f02000 0x40>; > status = "disabled"; > @@ -601,9 +585,8 @@ > compatible = "allwinner,sun8i-h3-r-pinctrl"; > reg = <0x01f02c00 0x400>; > interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; > + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; > clock-names = "apb", "hosc", "losc"; > - resets = <&apb0_reset 0>; > gpio-controller; > #gpio-cells = <3>; > interrupt-controller; > -- > 2.12.2 > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 850 bytes --] ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:03 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 2:03 UTC (permalink / raw) To: Ondřej Jirman Cc: Maxime Ripard, Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel 在 2017-07-20 06:59,Ondřej Jirman 写道: > Hi, > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy@aosc.xyz> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? > > thank you and regards, > o. It seems to be a very very very weird problem -- the CPUS_CFG register seems to be not accessible in non-secure mode on H3, and if the r_ccu driver reads it a value of 0x0 is read out (which means that the parent of ar100 is osc32k), but the real initial value of the register is 0x00010000 (which means the parent is osc24M). So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then the r_i2c fails to work. This clock problem doesn't exist for A64. > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk@01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk@01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset@01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock@1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir@01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:03 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy at aosc.io @ 2017-07-20 2:03 UTC (permalink / raw) To: linux-arm-kernel ? 2017-07-20 06:59?Ond?ej Jirman ??? > Hi, > > Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy@aosc.xyz> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? > > thank you and regards, > o. It seems to be a very very very weird problem -- the CPUS_CFG register seems to be not accessible in non-secure mode on H3, and if the r_ccu driver reads it a value of 0x0 is read out (which means that the parent of ar100 is osc32k), but the real initial value of the register is 0x00010000 (which means the parent is osc24M). So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then the r_i2c fails to work. This clock problem doesn't exist for A64. > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk at 01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk at 01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset at 01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock at 1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir at 01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:03 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 2:03 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-sunxi, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 5ZyoIDIwMTctMDctMjAgMDY6NTnvvIxPbmTFmWVqIEppcm1hbiDlhpnpgZPvvJoKPiBIaSwKPiAK PiBJY2Vub3d5IFpoZW5nIHDDrcWhZSB2IMOadCAwNC4gMDQuIDIwMTcgdiAxNzo1MCArMDgwMDoK Pj4gRnJvbTogSWNlbm93eSBaaGVuZyA8aWNlbm93eUBhb3NjLnh5ej4KPj4gCj4+IE5vdyB3ZSBo YXZlIGRyaXZlciBmb3IgdGhlIFBSQ00gQ0NVLCBzd2l0Y2ggdG8gdXNlIGl0IGluc3RlYWQgb2YK Pj4gb2xkLXN0eWxlIGNsb2NrIG5vZGVzIGZvciBhcGIwLXJlbGF0ZWQgY2xvY2tzIGluIHN1bnhp LWgzLWg1LmR0c2kgLgo+PiAKPj4gVGhlIG11eCAzIG9mIFJfQ0NVIGlzIHN0aWxsIHRoZSBpbnRl cm5hbCBvc2NpbGxhdG9yLCB3aGljaCBpcyBzYWlkIHRvIAo+PiBiZQo+PiAxNk1IeiBwbHVzIG1p bnVzIDMwJSwgYW5kIGdldCBhIG1lYXN1cmVkIHZhbHVlIG9mIDE1TUh6fjE2TUh6IG9uIG15IAo+ PiB0d28KPj4gSDMgYm9hcmRzIGFuZCBvbmUgSDUgYm9hcmQuCj4gCj4gVGhlcmUncyBpc3N1ZSB3 aXRoIHRoZSBuZXcgcl9jY3UgdGhhdCBicmVha3Mgcl9pMmMuIChubyBkZXZpY2VzIGNhbiBiZQo+ IGZvdW5kIG9uIHRoZSBidXMpLiBSZXZlcnRpbmcgdGhpcyBwYXRjaCBmaXhlcyB0aGUgaXNzdWUg d2l0aCB0aGUgSTJDCj4gY29udHJvbGxlci4gKGV2ZXJ5dGhpbmcgZWxzZSBiZWluZyB0aGUgc2Ft ZSkKPiAKPiBIZXJlJ3MgdGhlIGNvZGUgSSdtIHVzaW5nOiBodHRwczovL2dpdGh1Yi5jb20vbWVn b3VzL2xpbnV4L2NvbW1pdHMvb3Jhbgo+IGdlLXBpLTQuMTIKPiAKPiBUaGUgbGFzdCBjb21taXQg aXMgdGhlIHJldmVydC4KPiAKPiBUaGUgaXNzdWUgbWFuaWZlc3RzIGl0c2VsZiBieSBub24td29y a2luZyBEVkZTLCBiZWNhdXNlIGtlcm5lbCBsYWNrcwo+IGFjY2VzcyB0byBTWTgxMDZBIHJlZ3Vs YXRvciwgYmVjYXVzZSByX2kyYyBkb2Vzbid0IHdvcmsgd2l0aCBzdW54aS1uZwo+IGNsb2NrIGRy aXZlciAoc3VuOGktcikuCj4gCj4gUmVsZXZhbnQgZGlmZmVyZW5jZSBpbiByZWdpc3RlcnMgYmV0 d2VlbiB3b3JraW5nL25vbi13b3JraW5nIHN0YXRlIGlzCj4ganVzdCB0aGlzIChkaWZmIC11KToK PiAKPiAgMHgwMWYwMjQwMCA9IDB4MDAwMDAwMDAKPiAgMHgwMWYwMjQwNCA9IDB4MDAwMDAwMDAK PiAtMHgwMWYwMjQwOCA9IDB4MDAwMDAwOTEKPiArMHgwMWYwMjQwOCA9IDB4MDAwMDAwOTUgREFU QSByZWdpc3RlciBpbmlzZGUgdGhlIEkyQyBjb250cm9sbGVyCj4gIDB4MDFmMDI0MGMgPSAweDAw MDAwMDQ0Cj4gIDB4MDFmMDI0MTAgPSAweDAwMDAwMGY4Cj4gLTB4MDFmMDI0MTQgPSAweDAwMDAw MDU5Cj4gKzB4MDFmMDI0MTQgPSAweDAwMDAwMDAwIENMT0NLIHNldHVwIHJlZ2lzdGVyIGluc2lk ZSB0aGUgSTJDIGNvbnRyb2xsZXIKPiAgMHgwMWYwMjQxOCA9IDB4MDAwMDAwMDAKPiAgMHgwMWYw MjQxYyA9IDB4MDAwMDAwMDAKPiAgMHgwMWYwMjQyMCA9IDB4MDAwMDAwM2EKPiAKPiBJdCBsb29r cyBsaWtlIHRoZSBuZXcgc3VueGktbmcgY2xvY2sgZHJpdmVyIGNhdXNlcyB0aGUgSTJDIGRyaXZl ciB0bwo+IG5vdCBjb3JyZWN0bHkgY29uZmlndXJlIHRoZSBDTE9DSyByZWdpc3Rlci4gSSBkb24n dCBrbm93IHdoeSBhbmQgSSdtCj4gbm90IHN1cmUgaG93IHRvIGRlYWwgd2l0aCB0aGlzLiBBbnkg aWRlYXMgd2hhdCBjYW4gSSBkbyBuZXh0Pwo+IAo+IHRoYW5rIHlvdSBhbmQgcmVnYXJkcywKPiAg IG8uCgpJdCBzZWVtcyB0byBiZSBhIHZlcnkgdmVyeSB2ZXJ5IHdlaXJkIHByb2JsZW0gLS0gdGhl IENQVVNfQ0ZHIHJlZ2lzdGVyCnNlZW1zIHRvIGJlIG5vdCBhY2Nlc3NpYmxlIGluIG5vbi1zZWN1 cmUgbW9kZSBvbiBIMywgYW5kIGlmIHRoZSByX2NjdQpkcml2ZXIgcmVhZHMgaXQgYSB2YWx1ZSBv ZiAweDAgaXMgcmVhZCBvdXQgKHdoaWNoIG1lYW5zIHRoYXQgdGhlIHBhcmVudApvZiBhcjEwMCBp cyBvc2MzMmspLCBidXQgdGhlIHJlYWwgaW5pdGlhbCB2YWx1ZSBvZiB0aGUgcmVnaXN0ZXIgaXMK MHgwMDAxMDAwMCAod2hpY2ggbWVhbnMgdGhlIHBhcmVudCBpcyBvc2MyNE0pLgoKU28gdGhlIGJ1 cyBjbG9jayBvZiByX2kyYyBpcyB3cm9uZ2x5IGNsYWltZWQgYXMgMzJrSHosIG5vdCAyNE1Ieiwg dGhlbgp0aGUgcl9pMmMgZmFpbHMgdG8gd29yay4KClRoaXMgY2xvY2sgcHJvYmxlbSBkb2Vzbid0 IGV4aXN0IGZvciBBNjQuCgo+IAo+PiBTaWduZWQtb2ZmLWJ5OiBJY2Vub3d5IFpoZW5nIDxpY2Vu b3d5QGFvc2MueHl6Pgo+PiAtLS0KPj4gQ2hhbmdlcyBpbiB2NDoKPj4gLSBUZW1wb3JhcmlseSBk cm9wcGVkIHRoZSBDQ1UgaGVhZGVycy4KPj4gQ2hhbmdlcyBpbiB2MzoKPj4gLSBDaGFuZ2Ugb3Nj MzIwMDAgdG8gaW9zYy4KPj4gCj4+ICBhcmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNp IHwgNDUgCj4+ICsrKysrKysrKysrKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4+ICAxIGZp bGUgY2hhbmdlZCwgMTQgaW5zZXJ0aW9ucygrKSwgMzEgZGVsZXRpb25zKC0pCj4+IAo+PiBkaWZm IC0tZ2l0IGEvYXJjaC9hcm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRzaSAKPj4gYi9hcmNoL2Fy bS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNpCj4+IGluZGV4IDY2NDBlYmZhNjQxOS4uMWFlZWFj YjNhODg0IDEwMDY0NAo+PiAtLS0gYS9hcmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNp Cj4+ICsrKyBiL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bnhpLWgzLWg1LmR0c2kKPj4gQEAgLTY4LDMx ICs2OCwxMiBAQAo+PiAgCQkJY2xvY2stb3V0cHV0LW5hbWVzID0gIm9zYzMyayI7Cj4+ICAJCX07 Cj4+IAo+PiAtCQlhcGIwOiBhcGIwX2NsayB7Cj4+IC0JCQljb21wYXRpYmxlID0gImZpeGVkLWZh Y3Rvci1jbG9jayI7Cj4+ICsJCWlvc2M6IGludGVybmFsLW9zYy1jbGsgewo+PiAgCQkJI2Nsb2Nr LWNlbGxzID0gPDA+Owo+PiAtCQkJY2xvY2stZGl2ID0gPDE+Owo+PiAtCQkJY2xvY2stbXVsdCA9 IDwxPjsKPj4gLQkJCWNsb2NrcyA9IDwmb3NjMjRNPjsKPj4gLQkJCWNsb2NrLW91dHB1dC1uYW1l cyA9ICJhcGIwIjsKPj4gLQkJfTsKPj4gLQo+PiAtCQlhcGIwX2dhdGVzOiBjbGtAMDFmMDE0Mjgg ewo+PiAtCQkJY29tcGF0aWJsZSA9ICJhbGx3aW5uZXIsc3VuOGktaDMtYXBiMC1nYXRlcy1jbGsi LAo+PiAtCQkJCSAgICAgImFsbHdpbm5lcixzdW40aS1hMTAtZ2F0ZXMtY2xrIjsKPj4gLQkJCXJl ZyA9IDwweDAxZjAxNDI4IDB4ND47Cj4+IC0JCQkjY2xvY2stY2VsbHMgPSA8MT47Cj4+IC0JCQlj bG9ja3MgPSA8JmFwYjA+Owo+PiAtCQkJY2xvY2staW5kaWNlcyA9IDwwPiwgPDE+Owo+PiAtCQkJ Y2xvY2stb3V0cHV0LW5hbWVzID0gImFwYjBfcGlvIiwgImFwYjBfaXIiOwo+PiAtCQl9Owo+PiAt Cj4+IC0JCWlyX2NsazogaXJfY2xrQDAxZjAxNDU0IHsKPj4gLQkJCWNvbXBhdGlibGUgPSAiYWxs d2lubmVyLHN1bjRpLWExMC1tb2QwLWNsayI7Cj4+IC0JCQlyZWcgPSA8MHgwMWYwMTQ1NCAweDQ+ Owo+PiAtCQkJI2Nsb2NrLWNlbGxzID0gPDA+Owo+PiAtCQkJY2xvY2tzID0gPCZvc2MzMms+LCA8 Jm9zYzI0TT47Cj4+IC0JCQljbG9jay1vdXRwdXQtbmFtZXMgPSAiaXIiOwo+PiArCQkJY29tcGF0 aWJsZSA9ICJmaXhlZC1jbG9jayI7Cj4+ICsJCQljbG9jay1mcmVxdWVuY3kgPSA8MTYwMDAwMDA+ Owo+PiArCQkJY2xvY2stYWNjdXJhY3kgPSA8MzAwMDAwMDAwPjsKPj4gKwkJCWNsb2NrLW91dHB1 dC1uYW1lcyA9ICJpb3NjIjsKPj4gIAkJfTsKPj4gIAl9Owo+PiAKPj4gQEAgLTU3Niw5ICs1NTcs MTIgQEAKPj4gIAkJCQkgICAgIDxHSUNfU1BJIDQxIElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+PiAg CQl9Owo+PiAKPj4gLQkJYXBiMF9yZXNldDogcmVzZXRAMDFmMDE0YjAgewo+PiAtCQkJcmVnID0g PDB4MDFmMDE0YjAgMHg0PjsKPj4gLQkJCWNvbXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjZpLWEz MS1jbG9jay1yZXNldCI7Cj4+ICsJCXJfY2N1OiBjbG9ja0AxZjAxNDAwIHsKPj4gKwkJCWNvbXBh dGlibGUgPSAiYWxsd2lubmVyLHN1bjUwaS1hNjQtci1jY3UiOwo+PiArCQkJcmVnID0gPDB4MDFm MDE0MDAgMHgxMDA+Owo+PiArCQkJY2xvY2tzID0gPCZvc2MyNE0+LCA8Jm9zYzMyaz4sIDwmaW9z Yz47Cj4+ICsJCQljbG9jay1uYW1lcyA9ICJob3NjIiwgImxvc2MiLCAiaW9zYyI7Cj4+ICsJCQkj Y2xvY2stY2VsbHMgPSA8MT47Cj4+ICAJCQkjcmVzZXQtY2VsbHMgPSA8MT47Cj4+ICAJCX07Cj4+ IAo+PiBAQCAtNTg5LDkgKzU3Myw5IEBACj4+IAo+PiAgCQlpcjogaXJAMDFmMDIwMDAgewo+PiAg CQkJY29tcGF0aWJsZSA9ICJhbGx3aW5uZXIsc3VuNWktYTEzLWlyIjsKPj4gLQkJCWNsb2NrcyA9 IDwmYXBiMF9nYXRlcyAxPiwgPCZpcl9jbGs+Owo+PiArCQkJY2xvY2tzID0gPCZyX2NjdSA0Piwg PCZyX2NjdSAxMT47Cj4+ICAJCQljbG9jay1uYW1lcyA9ICJhcGIiLCAiaXIiOwo+PiAtCQkJcmVz ZXRzID0gPCZhcGIwX3Jlc2V0IDE+Owo+PiArCQkJcmVzZXRzID0gPCZyX2NjdSAwPjsKPj4gIAkJ CWludGVycnVwdHMgPSA8R0lDX1NQSSAzNyBJUlFfVFlQRV9MRVZFTF9ISUdIPjsKPj4gIAkJCXJl ZyA9IDwweDAxZjAyMDAwIDB4NDA+Owo+PiAgCQkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4gQEAg LTYwMSw5ICs1ODUsOCBAQAo+PiAgCQkJY29tcGF0aWJsZSA9ICJhbGx3aW5uZXIsc3VuOGktaDMt ci1waW5jdHJsIjsKPj4gIAkJCXJlZyA9IDwweDAxZjAyYzAwIDB4NDAwPjsKPj4gIAkJCWludGVy cnVwdHMgPSA8R0lDX1NQSSA0NSBJUlFfVFlQRV9MRVZFTF9ISUdIPjsKPj4gLQkJCWNsb2NrcyA9 IDwmYXBiMF9nYXRlcyAwPiwgPCZvc2MyNE0+LCA8Jm9zYzMyaz47Cj4+ICsJCQljbG9ja3MgPSA8 JnJfY2N1IDM+LCA8Jm9zYzI0TT4sIDwmb3NjMzJrPjsKPj4gIAkJCWNsb2NrLW5hbWVzID0gImFw YiIsICJob3NjIiwgImxvc2MiOwo+PiAtCQkJcmVzZXRzID0gPCZhcGIwX3Jlc2V0IDA+Owo+PiAg CQkJZ3Bpby1jb250cm9sbGVyOwo+PiAgCQkJI2dwaW8tY2VsbHMgPSA8Mz47Cj4+ICAJCQlpbnRl cnJ1cHQtY29udHJvbGxlcjsKPj4gLS0KPj4gMi4xMi4yCj4+IAo+IF9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gbGludXgtYXJtLWtlcm5lbCBtYWlsaW5n IGxpc3QKPiBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKPiBodHRwOi8vbGlz dHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwKCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJu ZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRw Oi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:03 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy-h8G6r0blFSE @ 2017-07-20 2:03 UTC (permalink / raw) To: Ondřej Jirman Cc: Maxime Ripard, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r 在 2017-07-20 06:59,Ondřej Jirman 写道: > Hi, > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? > > thank you and regards, > o. It seems to be a very very very weird problem -- the CPUS_CFG register seems to be not accessible in non-secure mode on H3, and if the r_ccu driver reads it a value of 0x0 is read out (which means that the parent of ar100 is osc32k), but the real initial value of the register is 0x00010000 (which means the parent is osc24M). So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then the r_i2c fails to work. This clock problem doesn't exist for A64. > >> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk@01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk@01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset@01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock@1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir@01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:19 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 2:19 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-sunxi, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 在 2017-07-20 10:03,icenowy@aosc.io 写道: > 在 2017-07-20 06:59,Ondřej Jirman 写道: >> Hi, >> >> Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy@aosc.xyz> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. > > This clock problem doesn't exist for A64. H5 doesn't have this issue either. > >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk@01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk@01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset@01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock@1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir@01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:19 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy at aosc.io @ 2017-07-20 2:19 UTC (permalink / raw) To: linux-arm-kernel ? 2017-07-20 10:03?icenowy at aosc.io ??? > ? 2017-07-20 06:59?Ond?ej Jirman ??? >> Hi, >> >> Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy@aosc.xyz> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. > > This clock problem doesn't exist for A64. H5 doesn't have this issue either. > >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk at 01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk at 01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset at 01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock at 1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir at 01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel at lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:19 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 2:19 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, linux-sunxi, linux-kernel, Chen-Yu Tsai, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 5ZyoIDIwMTctMDctMjAgMTA6MDPvvIxpY2Vub3d5QGFvc2MuaW8g5YaZ6YGT77yaCj4g5ZyoIDIw MTctMDctMjAgMDY6NTnvvIxPbmTFmWVqIEppcm1hbiDlhpnpgZPvvJoKPj4gSGksCj4+IAo+PiBJ Y2Vub3d5IFpoZW5nIHDDrcWhZSB2IMOadCAwNC4gMDQuIDIwMTcgdiAxNzo1MCArMDgwMDoKPj4+ IEZyb206IEljZW5vd3kgWmhlbmcgPGljZW5vd3lAYW9zYy54eXo+Cj4+PiAKPj4+IE5vdyB3ZSBo YXZlIGRyaXZlciBmb3IgdGhlIFBSQ00gQ0NVLCBzd2l0Y2ggdG8gdXNlIGl0IGluc3RlYWQgb2YK Pj4+IG9sZC1zdHlsZSBjbG9jayBub2RlcyBmb3IgYXBiMC1yZWxhdGVkIGNsb2NrcyBpbiBzdW54 aS1oMy1oNS5kdHNpIC4KPj4+IAo+Pj4gVGhlIG11eCAzIG9mIFJfQ0NVIGlzIHN0aWxsIHRoZSBp bnRlcm5hbCBvc2NpbGxhdG9yLCB3aGljaCBpcyBzYWlkIHRvIAo+Pj4gYmUKPj4+IDE2TUh6IHBs dXMgbWludXMgMzAlLCBhbmQgZ2V0IGEgbWVhc3VyZWQgdmFsdWUgb2YgMTVNSHp+MTZNSHogb24g bXkgCj4+PiB0d28KPj4+IEgzIGJvYXJkcyBhbmQgb25lIEg1IGJvYXJkLgo+PiAKPj4gVGhlcmUn cyBpc3N1ZSB3aXRoIHRoZSBuZXcgcl9jY3UgdGhhdCBicmVha3Mgcl9pMmMuIChubyBkZXZpY2Vz IGNhbiBiZQo+PiBmb3VuZCBvbiB0aGUgYnVzKS4gUmV2ZXJ0aW5nIHRoaXMgcGF0Y2ggZml4ZXMg dGhlIGlzc3VlIHdpdGggdGhlIEkyQwo+PiBjb250cm9sbGVyLiAoZXZlcnl0aGluZyBlbHNlIGJl aW5nIHRoZSBzYW1lKQo+PiAKPj4gSGVyZSdzIHRoZSBjb2RlIEknbSB1c2luZzogCj4+IGh0dHBz Oi8vZ2l0aHViLmNvbS9tZWdvdXMvbGludXgvY29tbWl0cy9vcmFuCj4+IGdlLXBpLTQuMTIKPj4g Cj4+IFRoZSBsYXN0IGNvbW1pdCBpcyB0aGUgcmV2ZXJ0Lgo+PiAKPj4gVGhlIGlzc3VlIG1hbmlm ZXN0cyBpdHNlbGYgYnkgbm9uLXdvcmtpbmcgRFZGUywgYmVjYXVzZSBrZXJuZWwgbGFja3MKPj4g YWNjZXNzIHRvIFNZODEwNkEgcmVndWxhdG9yLCBiZWNhdXNlIHJfaTJjIGRvZXNuJ3Qgd29yayB3 aXRoIHN1bnhpLW5nCj4+IGNsb2NrIGRyaXZlciAoc3VuOGktcikuCj4+IAo+PiBSZWxldmFudCBk aWZmZXJlbmNlIGluIHJlZ2lzdGVycyBiZXR3ZWVuIHdvcmtpbmcvbm9uLXdvcmtpbmcgc3RhdGUg aXMKPj4ganVzdCB0aGlzIChkaWZmIC11KToKPj4gCj4+ICAweDAxZjAyNDAwID0gMHgwMDAwMDAw MAo+PiAgMHgwMWYwMjQwNCA9IDB4MDAwMDAwMDAKPj4gLTB4MDFmMDI0MDggPSAweDAwMDAwMDkx Cj4+ICsweDAxZjAyNDA4ID0gMHgwMDAwMDA5NSBEQVRBIHJlZ2lzdGVyIGluaXNkZSB0aGUgSTJD IGNvbnRyb2xsZXIKPj4gIDB4MDFmMDI0MGMgPSAweDAwMDAwMDQ0Cj4+ICAweDAxZjAyNDEwID0g MHgwMDAwMDBmOAo+PiAtMHgwMWYwMjQxNCA9IDB4MDAwMDAwNTkKPj4gKzB4MDFmMDI0MTQgPSAw eDAwMDAwMDAwIENMT0NLIHNldHVwIHJlZ2lzdGVyIGluc2lkZSB0aGUgSTJDIAo+PiBjb250cm9s bGVyCj4+ICAweDAxZjAyNDE4ID0gMHgwMDAwMDAwMAo+PiAgMHgwMWYwMjQxYyA9IDB4MDAwMDAw MDAKPj4gIDB4MDFmMDI0MjAgPSAweDAwMDAwMDNhCj4+IAo+PiBJdCBsb29rcyBsaWtlIHRoZSBu ZXcgc3VueGktbmcgY2xvY2sgZHJpdmVyIGNhdXNlcyB0aGUgSTJDIGRyaXZlciB0bwo+PiBub3Qg Y29ycmVjdGx5IGNvbmZpZ3VyZSB0aGUgQ0xPQ0sgcmVnaXN0ZXIuIEkgZG9uJ3Qga25vdyB3aHkg YW5kIEknbQo+PiBub3Qgc3VyZSBob3cgdG8gZGVhbCB3aXRoIHRoaXMuIEFueSBpZGVhcyB3aGF0 IGNhbiBJIGRvIG5leHQ/Cj4+IAo+PiB0aGFuayB5b3UgYW5kIHJlZ2FyZHMsCj4+ICAgby4KPiAK PiBJdCBzZWVtcyB0byBiZSBhIHZlcnkgdmVyeSB2ZXJ5IHdlaXJkIHByb2JsZW0gLS0gdGhlIENQ VVNfQ0ZHIHJlZ2lzdGVyCj4gc2VlbXMgdG8gYmUgbm90IGFjY2Vzc2libGUgaW4gbm9uLXNlY3Vy ZSBtb2RlIG9uIEgzLCBhbmQgaWYgdGhlIHJfY2N1Cj4gZHJpdmVyIHJlYWRzIGl0IGEgdmFsdWUg b2YgMHgwIGlzIHJlYWQgb3V0ICh3aGljaCBtZWFucyB0aGF0IHRoZSBwYXJlbnQKPiBvZiBhcjEw MCBpcyBvc2MzMmspLCBidXQgdGhlIHJlYWwgaW5pdGlhbCB2YWx1ZSBvZiB0aGUgcmVnaXN0ZXIg aXMKPiAweDAwMDEwMDAwICh3aGljaCBtZWFucyB0aGUgcGFyZW50IGlzIG9zYzI0TSkuCj4gCj4g U28gdGhlIGJ1cyBjbG9jayBvZiByX2kyYyBpcyB3cm9uZ2x5IGNsYWltZWQgYXMgMzJrSHosIG5v dCAyNE1IeiwgdGhlbgo+IHRoZSByX2kyYyBmYWlscyB0byB3b3JrLgo+IAo+IFRoaXMgY2xvY2sg cHJvYmxlbSBkb2Vzbid0IGV4aXN0IGZvciBBNjQuCgpINSBkb2Vzbid0IGhhdmUgdGhpcyBpc3N1 ZSBlaXRoZXIuCgo+IAo+PiAKPj4+IFNpZ25lZC1vZmYtYnk6IEljZW5vd3kgWmhlbmcgPGljZW5v d3lAYW9zYy54eXo+Cj4+PiAtLS0KPj4+IENoYW5nZXMgaW4gdjQ6Cj4+PiAtIFRlbXBvcmFyaWx5 IGRyb3BwZWQgdGhlIENDVSBoZWFkZXJzLgo+Pj4gQ2hhbmdlcyBpbiB2MzoKPj4+IC0gQ2hhbmdl IG9zYzMyMDAwIHRvIGlvc2MuCj4+PiAKPj4+ICBhcmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1o NS5kdHNpIHwgNDUgCj4+PiArKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQo+ Pj4gIDEgZmlsZSBjaGFuZ2VkLCAxNCBpbnNlcnRpb25zKCspLCAzMSBkZWxldGlvbnMoLSkKPj4+ IAo+Pj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bnhpLWgzLWg1LmR0c2kgCj4+ PiBiL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bnhpLWgzLWg1LmR0c2kKPj4+IGluZGV4IDY2NDBlYmZh NjQxOS4uMWFlZWFjYjNhODg0IDEwMDY0NAo+Pj4gLS0tIGEvYXJjaC9hcm0vYm9vdC9kdHMvc3Vu eGktaDMtaDUuZHRzaQo+Pj4gKysrIGIvYXJjaC9hcm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRz aQo+Pj4gQEAgLTY4LDMxICs2OCwxMiBAQAo+Pj4gIAkJCWNsb2NrLW91dHB1dC1uYW1lcyA9ICJv c2MzMmsiOwo+Pj4gIAkJfTsKPj4+IAo+Pj4gLQkJYXBiMDogYXBiMF9jbGsgewo+Pj4gLQkJCWNv bXBhdGlibGUgPSAiZml4ZWQtZmFjdG9yLWNsb2NrIjsKPj4+ICsJCWlvc2M6IGludGVybmFsLW9z Yy1jbGsgewo+Pj4gIAkJCSNjbG9jay1jZWxscyA9IDwwPjsKPj4+IC0JCQljbG9jay1kaXYgPSA8 MT47Cj4+PiAtCQkJY2xvY2stbXVsdCA9IDwxPjsKPj4+IC0JCQljbG9ja3MgPSA8Jm9zYzI0TT47 Cj4+PiAtCQkJY2xvY2stb3V0cHV0LW5hbWVzID0gImFwYjAiOwo+Pj4gLQkJfTsKPj4+IC0KPj4+ IC0JCWFwYjBfZ2F0ZXM6IGNsa0AwMWYwMTQyOCB7Cj4+PiAtCQkJY29tcGF0aWJsZSA9ICJhbGx3 aW5uZXIsc3VuOGktaDMtYXBiMC1nYXRlcy1jbGsiLAo+Pj4gLQkJCQkgICAgICJhbGx3aW5uZXIs c3VuNGktYTEwLWdhdGVzLWNsayI7Cj4+PiAtCQkJcmVnID0gPDB4MDFmMDE0MjggMHg0PjsKPj4+ IC0JCQkjY2xvY2stY2VsbHMgPSA8MT47Cj4+PiAtCQkJY2xvY2tzID0gPCZhcGIwPjsKPj4+IC0J CQljbG9jay1pbmRpY2VzID0gPDA+LCA8MT47Cj4+PiAtCQkJY2xvY2stb3V0cHV0LW5hbWVzID0g ImFwYjBfcGlvIiwgImFwYjBfaXIiOwo+Pj4gLQkJfTsKPj4+IC0KPj4+IC0JCWlyX2NsazogaXJf Y2xrQDAxZjAxNDU0IHsKPj4+IC0JCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW40aS1hMTAt bW9kMC1jbGsiOwo+Pj4gLQkJCXJlZyA9IDwweDAxZjAxNDU0IDB4ND47Cj4+PiAtCQkJI2Nsb2Nr LWNlbGxzID0gPDA+Owo+Pj4gLQkJCWNsb2NrcyA9IDwmb3NjMzJrPiwgPCZvc2MyNE0+Owo+Pj4g LQkJCWNsb2NrLW91dHB1dC1uYW1lcyA9ICJpciI7Cj4+PiArCQkJY29tcGF0aWJsZSA9ICJmaXhl ZC1jbG9jayI7Cj4+PiArCQkJY2xvY2stZnJlcXVlbmN5ID0gPDE2MDAwMDAwPjsKPj4+ICsJCQlj bG9jay1hY2N1cmFjeSA9IDwzMDAwMDAwMDA+Owo+Pj4gKwkJCWNsb2NrLW91dHB1dC1uYW1lcyA9 ICJpb3NjIjsKPj4+ICAJCX07Cj4+PiAgCX07Cj4+PiAKPj4+IEBAIC01NzYsOSArNTU3LDEyIEBA Cj4+PiAgCQkJCSAgICAgPEdJQ19TUEkgNDEgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+PiAgCQl9 Owo+Pj4gCj4+PiAtCQlhcGIwX3Jlc2V0OiByZXNldEAwMWYwMTRiMCB7Cj4+PiAtCQkJcmVnID0g PDB4MDFmMDE0YjAgMHg0PjsKPj4+IC0JCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW42aS1h MzEtY2xvY2stcmVzZXQiOwo+Pj4gKwkJcl9jY3U6IGNsb2NrQDFmMDE0MDAgewo+Pj4gKwkJCWNv bXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjUwaS1hNjQtci1jY3UiOwo+Pj4gKwkJCXJlZyA9IDww eDAxZjAxNDAwIDB4MTAwPjsKPj4+ICsJCQljbG9ja3MgPSA8Jm9zYzI0TT4sIDwmb3NjMzJrPiwg PCZpb3NjPjsKPj4+ICsJCQljbG9jay1uYW1lcyA9ICJob3NjIiwgImxvc2MiLCAiaW9zYyI7Cj4+ PiArCQkJI2Nsb2NrLWNlbGxzID0gPDE+Owo+Pj4gIAkJCSNyZXNldC1jZWxscyA9IDwxPjsKPj4+ ICAJCX07Cj4+PiAKPj4+IEBAIC01ODksOSArNTczLDkgQEAKPj4+IAo+Pj4gIAkJaXI6IGlyQDAx ZjAyMDAwIHsKPj4+ICAJCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW41aS1hMTMtaXIiOwo+ Pj4gLQkJCWNsb2NrcyA9IDwmYXBiMF9nYXRlcyAxPiwgPCZpcl9jbGs+Owo+Pj4gKwkJCWNsb2Nr cyA9IDwmcl9jY3UgND4sIDwmcl9jY3UgMTE+Owo+Pj4gIAkJCWNsb2NrLW5hbWVzID0gImFwYiIs ICJpciI7Cj4+PiAtCQkJcmVzZXRzID0gPCZhcGIwX3Jlc2V0IDE+Owo+Pj4gKwkJCXJlc2V0cyA9 IDwmcl9jY3UgMD47Cj4+PiAgCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDM3IElSUV9UWVBFX0xF VkVMX0hJR0g+Owo+Pj4gIAkJCXJlZyA9IDwweDAxZjAyMDAwIDB4NDA+Owo+Pj4gIAkJCXN0YXR1 cyA9ICJkaXNhYmxlZCI7Cj4+PiBAQCAtNjAxLDkgKzU4NSw4IEBACj4+PiAgCQkJY29tcGF0aWJs ZSA9ICJhbGx3aW5uZXIsc3VuOGktaDMtci1waW5jdHJsIjsKPj4+ICAJCQlyZWcgPSA8MHgwMWYw MmMwMCAweDQwMD47Cj4+PiAgCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDQ1IElSUV9UWVBFX0xF VkVMX0hJR0g+Owo+Pj4gLQkJCWNsb2NrcyA9IDwmYXBiMF9nYXRlcyAwPiwgPCZvc2MyNE0+LCA8 Jm9zYzMyaz47Cj4+PiArCQkJY2xvY2tzID0gPCZyX2NjdSAzPiwgPCZvc2MyNE0+LCA8Jm9zYzMy az47Cj4+PiAgCQkJY2xvY2stbmFtZXMgPSAiYXBiIiwgImhvc2MiLCAibG9zYyI7Cj4+PiAtCQkJ cmVzZXRzID0gPCZhcGIwX3Jlc2V0IDA+Owo+Pj4gIAkJCWdwaW8tY29udHJvbGxlcjsKPj4+ICAJ CQkjZ3Bpby1jZWxscyA9IDwzPjsKPj4+ICAJCQlpbnRlcnJ1cHQtY29udHJvbGxlcjsKPj4+IC0t Cj4+PiAyLjEyLjIKPj4+IAo+PiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwo+PiBsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdAo+PiBsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKPj4gaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcv bWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCj4gCj4gX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPiBsaW51eC1hcm0ta2VybmVsIG1haWxpbmcg bGlzdAo+IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwo+IGh0dHA6Ly9saXN0 cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5l bCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6 Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 2:19 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy-h8G6r0blFSE @ 2017-07-20 2:19 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Chen-Yu Tsai, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, Maxime Ripard, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r 在 2017-07-20 10:03,icenowy-h8G6r0blFSE@public.gmane.org 写道: > 在 2017-07-20 06:59,Ondřej Jirman 写道: >> Hi, >> >> Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. > > This clock problem doesn't exist for A64. H5 doesn't have this issue either. > >> >>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk@01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk@01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset@01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock@1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir@01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 5:15 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 5:15 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-sunxi, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 在 2017-07-20 10:03,icenowy@aosc.io 写道: > 在 2017-07-20 06:59,Ondřej Jirman 写道: >> Hi, >> >> Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy@aosc.xyz> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. The protection to AR100 registers can be removed by writing 1 to 0x01f015d0 (0x1d0 at PRCM memory region). Interestingly this controlling register can be written in non-secure world, so it's still broken secure/non-secure division ;-) > > This clock problem doesn't exist for A64. > >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk@01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk@01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset@01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock@1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir@01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 5:15 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy at aosc.io @ 2017-07-20 5:15 UTC (permalink / raw) To: linux-arm-kernel ? 2017-07-20 10:03?icenowy at aosc.io ??? > ? 2017-07-20 06:59?Ond?ej Jirman ??? >> Hi, >> >> Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy@aosc.xyz> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. The protection to AR100 registers can be removed by writing 1 to 0x01f015d0 (0x1d0 at PRCM memory region). Interestingly this controlling register can be written in non-secure world, so it's still broken secure/non-secure division ;-) > > This clock problem doesn't exist for A64. > >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk at 01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk at 01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset at 01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock at 1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir at 01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel at lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 5:15 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 5:15 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, linux-sunxi, linux-kernel, Chen-Yu Tsai, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 5ZyoIDIwMTctMDctMjAgMTA6MDPvvIxpY2Vub3d5QGFvc2MuaW8g5YaZ6YGT77yaCj4g5ZyoIDIw MTctMDctMjAgMDY6NTnvvIxPbmTFmWVqIEppcm1hbiDlhpnpgZPvvJoKPj4gSGksCj4+IAo+PiBJ Y2Vub3d5IFpoZW5nIHDDrcWhZSB2IMOadCAwNC4gMDQuIDIwMTcgdiAxNzo1MCArMDgwMDoKPj4+ IEZyb206IEljZW5vd3kgWmhlbmcgPGljZW5vd3lAYW9zYy54eXo+Cj4+PiAKPj4+IE5vdyB3ZSBo YXZlIGRyaXZlciBmb3IgdGhlIFBSQ00gQ0NVLCBzd2l0Y2ggdG8gdXNlIGl0IGluc3RlYWQgb2YK Pj4+IG9sZC1zdHlsZSBjbG9jayBub2RlcyBmb3IgYXBiMC1yZWxhdGVkIGNsb2NrcyBpbiBzdW54 aS1oMy1oNS5kdHNpIC4KPj4+IAo+Pj4gVGhlIG11eCAzIG9mIFJfQ0NVIGlzIHN0aWxsIHRoZSBp bnRlcm5hbCBvc2NpbGxhdG9yLCB3aGljaCBpcyBzYWlkIHRvIAo+Pj4gYmUKPj4+IDE2TUh6IHBs dXMgbWludXMgMzAlLCBhbmQgZ2V0IGEgbWVhc3VyZWQgdmFsdWUgb2YgMTVNSHp+MTZNSHogb24g bXkgCj4+PiB0d28KPj4+IEgzIGJvYXJkcyBhbmQgb25lIEg1IGJvYXJkLgo+PiAKPj4gVGhlcmUn cyBpc3N1ZSB3aXRoIHRoZSBuZXcgcl9jY3UgdGhhdCBicmVha3Mgcl9pMmMuIChubyBkZXZpY2Vz IGNhbiBiZQo+PiBmb3VuZCBvbiB0aGUgYnVzKS4gUmV2ZXJ0aW5nIHRoaXMgcGF0Y2ggZml4ZXMg dGhlIGlzc3VlIHdpdGggdGhlIEkyQwo+PiBjb250cm9sbGVyLiAoZXZlcnl0aGluZyBlbHNlIGJl aW5nIHRoZSBzYW1lKQo+PiAKPj4gSGVyZSdzIHRoZSBjb2RlIEknbSB1c2luZzogCj4+IGh0dHBz Oi8vZ2l0aHViLmNvbS9tZWdvdXMvbGludXgvY29tbWl0cy9vcmFuCj4+IGdlLXBpLTQuMTIKPj4g Cj4+IFRoZSBsYXN0IGNvbW1pdCBpcyB0aGUgcmV2ZXJ0Lgo+PiAKPj4gVGhlIGlzc3VlIG1hbmlm ZXN0cyBpdHNlbGYgYnkgbm9uLXdvcmtpbmcgRFZGUywgYmVjYXVzZSBrZXJuZWwgbGFja3MKPj4g YWNjZXNzIHRvIFNZODEwNkEgcmVndWxhdG9yLCBiZWNhdXNlIHJfaTJjIGRvZXNuJ3Qgd29yayB3 aXRoIHN1bnhpLW5nCj4+IGNsb2NrIGRyaXZlciAoc3VuOGktcikuCj4+IAo+PiBSZWxldmFudCBk aWZmZXJlbmNlIGluIHJlZ2lzdGVycyBiZXR3ZWVuIHdvcmtpbmcvbm9uLXdvcmtpbmcgc3RhdGUg aXMKPj4ganVzdCB0aGlzIChkaWZmIC11KToKPj4gCj4+ICAweDAxZjAyNDAwID0gMHgwMDAwMDAw MAo+PiAgMHgwMWYwMjQwNCA9IDB4MDAwMDAwMDAKPj4gLTB4MDFmMDI0MDggPSAweDAwMDAwMDkx Cj4+ICsweDAxZjAyNDA4ID0gMHgwMDAwMDA5NSBEQVRBIHJlZ2lzdGVyIGluaXNkZSB0aGUgSTJD IGNvbnRyb2xsZXIKPj4gIDB4MDFmMDI0MGMgPSAweDAwMDAwMDQ0Cj4+ICAweDAxZjAyNDEwID0g MHgwMDAwMDBmOAo+PiAtMHgwMWYwMjQxNCA9IDB4MDAwMDAwNTkKPj4gKzB4MDFmMDI0MTQgPSAw eDAwMDAwMDAwIENMT0NLIHNldHVwIHJlZ2lzdGVyIGluc2lkZSB0aGUgSTJDIAo+PiBjb250cm9s bGVyCj4+ICAweDAxZjAyNDE4ID0gMHgwMDAwMDAwMAo+PiAgMHgwMWYwMjQxYyA9IDB4MDAwMDAw MDAKPj4gIDB4MDFmMDI0MjAgPSAweDAwMDAwMDNhCj4+IAo+PiBJdCBsb29rcyBsaWtlIHRoZSBu ZXcgc3VueGktbmcgY2xvY2sgZHJpdmVyIGNhdXNlcyB0aGUgSTJDIGRyaXZlciB0bwo+PiBub3Qg Y29ycmVjdGx5IGNvbmZpZ3VyZSB0aGUgQ0xPQ0sgcmVnaXN0ZXIuIEkgZG9uJ3Qga25vdyB3aHkg YW5kIEknbQo+PiBub3Qgc3VyZSBob3cgdG8gZGVhbCB3aXRoIHRoaXMuIEFueSBpZGVhcyB3aGF0 IGNhbiBJIGRvIG5leHQ/Cj4+IAo+PiB0aGFuayB5b3UgYW5kIHJlZ2FyZHMsCj4+ICAgby4KPiAK PiBJdCBzZWVtcyB0byBiZSBhIHZlcnkgdmVyeSB2ZXJ5IHdlaXJkIHByb2JsZW0gLS0gdGhlIENQ VVNfQ0ZHIHJlZ2lzdGVyCj4gc2VlbXMgdG8gYmUgbm90IGFjY2Vzc2libGUgaW4gbm9uLXNlY3Vy ZSBtb2RlIG9uIEgzLCBhbmQgaWYgdGhlIHJfY2N1Cj4gZHJpdmVyIHJlYWRzIGl0IGEgdmFsdWUg b2YgMHgwIGlzIHJlYWQgb3V0ICh3aGljaCBtZWFucyB0aGF0IHRoZSBwYXJlbnQKPiBvZiBhcjEw MCBpcyBvc2MzMmspLCBidXQgdGhlIHJlYWwgaW5pdGlhbCB2YWx1ZSBvZiB0aGUgcmVnaXN0ZXIg aXMKPiAweDAwMDEwMDAwICh3aGljaCBtZWFucyB0aGUgcGFyZW50IGlzIG9zYzI0TSkuCj4gCj4g U28gdGhlIGJ1cyBjbG9jayBvZiByX2kyYyBpcyB3cm9uZ2x5IGNsYWltZWQgYXMgMzJrSHosIG5v dCAyNE1IeiwgdGhlbgo+IHRoZSByX2kyYyBmYWlscyB0byB3b3JrLgoKVGhlIHByb3RlY3Rpb24g dG8gQVIxMDAgcmVnaXN0ZXJzIGNhbiBiZSByZW1vdmVkIGJ5IHdyaXRpbmcgMSB0byAKMHgwMWYw MTVkMAooMHgxZDAgYXQgUFJDTSBtZW1vcnkgcmVnaW9uKS4KCkludGVyZXN0aW5nbHkgdGhpcyBj b250cm9sbGluZyByZWdpc3RlciBjYW4gYmUgd3JpdHRlbiBpbiBub24tc2VjdXJlIAp3b3JsZCwK c28gaXQncyBzdGlsbCBicm9rZW4gc2VjdXJlL25vbi1zZWN1cmUgZGl2aXNpb24gOy0pCgo+IAo+ IFRoaXMgY2xvY2sgcHJvYmxlbSBkb2Vzbid0IGV4aXN0IGZvciBBNjQuCj4gCj4+IAo+Pj4gU2ln bmVkLW9mZi1ieTogSWNlbm93eSBaaGVuZyA8aWNlbm93eUBhb3NjLnh5ej4KPj4+IC0tLQo+Pj4g Q2hhbmdlcyBpbiB2NDoKPj4+IC0gVGVtcG9yYXJpbHkgZHJvcHBlZCB0aGUgQ0NVIGhlYWRlcnMu Cj4+PiBDaGFuZ2VzIGluIHYzOgo+Pj4gLSBDaGFuZ2Ugb3NjMzIwMDAgdG8gaW9zYy4KPj4+IAo+ Pj4gIGFyY2gvYXJtL2Jvb3QvZHRzL3N1bnhpLWgzLWg1LmR0c2kgfCA0NSAKPj4+ICsrKysrKysr KysrKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCj4+PiAgMSBmaWxlIGNoYW5nZWQsIDE0IGlu c2VydGlvbnMoKyksIDMxIGRlbGV0aW9ucygtKQo+Pj4gCj4+PiBkaWZmIC0tZ2l0IGEvYXJjaC9h cm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRzaSAKPj4+IGIvYXJjaC9hcm0vYm9vdC9kdHMvc3Vu eGktaDMtaDUuZHRzaQo+Pj4gaW5kZXggNjY0MGViZmE2NDE5Li4xYWVlYWNiM2E4ODQgMTAwNjQ0 Cj4+PiAtLS0gYS9hcmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNpCj4+PiArKysgYi9h cmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNpCj4+PiBAQCAtNjgsMzEgKzY4LDEyIEBA Cj4+PiAgCQkJY2xvY2stb3V0cHV0LW5hbWVzID0gIm9zYzMyayI7Cj4+PiAgCQl9Owo+Pj4gCj4+ PiAtCQlhcGIwOiBhcGIwX2NsayB7Cj4+PiAtCQkJY29tcGF0aWJsZSA9ICJmaXhlZC1mYWN0b3It Y2xvY2siOwo+Pj4gKwkJaW9zYzogaW50ZXJuYWwtb3NjLWNsayB7Cj4+PiAgCQkJI2Nsb2NrLWNl bGxzID0gPDA+Owo+Pj4gLQkJCWNsb2NrLWRpdiA9IDwxPjsKPj4+IC0JCQljbG9jay1tdWx0ID0g PDE+Owo+Pj4gLQkJCWNsb2NrcyA9IDwmb3NjMjRNPjsKPj4+IC0JCQljbG9jay1vdXRwdXQtbmFt ZXMgPSAiYXBiMCI7Cj4+PiAtCQl9Owo+Pj4gLQo+Pj4gLQkJYXBiMF9nYXRlczogY2xrQDAxZjAx NDI4IHsKPj4+IC0JCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW44aS1oMy1hcGIwLWdhdGVz LWNsayIsCj4+PiAtCQkJCSAgICAgImFsbHdpbm5lcixzdW40aS1hMTAtZ2F0ZXMtY2xrIjsKPj4+ IC0JCQlyZWcgPSA8MHgwMWYwMTQyOCAweDQ+Owo+Pj4gLQkJCSNjbG9jay1jZWxscyA9IDwxPjsK Pj4+IC0JCQljbG9ja3MgPSA8JmFwYjA+Owo+Pj4gLQkJCWNsb2NrLWluZGljZXMgPSA8MD4sIDwx PjsKPj4+IC0JCQljbG9jay1vdXRwdXQtbmFtZXMgPSAiYXBiMF9waW8iLCAiYXBiMF9pciI7Cj4+ PiAtCQl9Owo+Pj4gLQo+Pj4gLQkJaXJfY2xrOiBpcl9jbGtAMDFmMDE0NTQgewo+Pj4gLQkJCWNv bXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjRpLWExMC1tb2QwLWNsayI7Cj4+PiAtCQkJcmVnID0g PDB4MDFmMDE0NTQgMHg0PjsKPj4+IC0JCQkjY2xvY2stY2VsbHMgPSA8MD47Cj4+PiAtCQkJY2xv Y2tzID0gPCZvc2MzMms+LCA8Jm9zYzI0TT47Cj4+PiAtCQkJY2xvY2stb3V0cHV0LW5hbWVzID0g ImlyIjsKPj4+ICsJCQljb21wYXRpYmxlID0gImZpeGVkLWNsb2NrIjsKPj4+ICsJCQljbG9jay1m cmVxdWVuY3kgPSA8MTYwMDAwMDA+Owo+Pj4gKwkJCWNsb2NrLWFjY3VyYWN5ID0gPDMwMDAwMDAw MD47Cj4+PiArCQkJY2xvY2stb3V0cHV0LW5hbWVzID0gImlvc2MiOwo+Pj4gIAkJfTsKPj4+ICAJ fTsKPj4+IAo+Pj4gQEAgLTU3Niw5ICs1NTcsMTIgQEAKPj4+ICAJCQkJICAgICA8R0lDX1NQSSA0 MSBJUlFfVFlQRV9MRVZFTF9ISUdIPjsKPj4+ICAJCX07Cj4+PiAKPj4+IC0JCWFwYjBfcmVzZXQ6 IHJlc2V0QDAxZjAxNGIwIHsKPj4+IC0JCQlyZWcgPSA8MHgwMWYwMTRiMCAweDQ+Owo+Pj4gLQkJ CWNvbXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjZpLWEzMS1jbG9jay1yZXNldCI7Cj4+PiArCQly X2NjdTogY2xvY2tAMWYwMTQwMCB7Cj4+PiArCQkJY29tcGF0aWJsZSA9ICJhbGx3aW5uZXIsc3Vu NTBpLWE2NC1yLWNjdSI7Cj4+PiArCQkJcmVnID0gPDB4MDFmMDE0MDAgMHgxMDA+Owo+Pj4gKwkJ CWNsb2NrcyA9IDwmb3NjMjRNPiwgPCZvc2MzMms+LCA8Jmlvc2M+Owo+Pj4gKwkJCWNsb2NrLW5h bWVzID0gImhvc2MiLCAibG9zYyIsICJpb3NjIjsKPj4+ICsJCQkjY2xvY2stY2VsbHMgPSA8MT47 Cj4+PiAgCQkJI3Jlc2V0LWNlbGxzID0gPDE+Owo+Pj4gIAkJfTsKPj4+IAo+Pj4gQEAgLTU4OSw5 ICs1NzMsOSBAQAo+Pj4gCj4+PiAgCQlpcjogaXJAMDFmMDIwMDAgewo+Pj4gIAkJCWNvbXBhdGli bGUgPSAiYWxsd2lubmVyLHN1bjVpLWExMy1pciI7Cj4+PiAtCQkJY2xvY2tzID0gPCZhcGIwX2dh dGVzIDE+LCA8JmlyX2Nsaz47Cj4+PiArCQkJY2xvY2tzID0gPCZyX2NjdSA0PiwgPCZyX2NjdSAx MT47Cj4+PiAgCQkJY2xvY2stbmFtZXMgPSAiYXBiIiwgImlyIjsKPj4+IC0JCQlyZXNldHMgPSA8 JmFwYjBfcmVzZXQgMT47Cj4+PiArCQkJcmVzZXRzID0gPCZyX2NjdSAwPjsKPj4+ICAJCQlpbnRl cnJ1cHRzID0gPEdJQ19TUEkgMzcgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+PiAgCQkJcmVnID0g PDB4MDFmMDIwMDAgMHg0MD47Cj4+PiAgCQkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4+IEBAIC02 MDEsOSArNTg1LDggQEAKPj4+ICAJCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW44aS1oMy1y LXBpbmN0cmwiOwo+Pj4gIAkJCXJlZyA9IDwweDAxZjAyYzAwIDB4NDAwPjsKPj4+ICAJCQlpbnRl cnJ1cHRzID0gPEdJQ19TUEkgNDUgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+PiAtCQkJY2xvY2tz ID0gPCZhcGIwX2dhdGVzIDA+LCA8Jm9zYzI0TT4sIDwmb3NjMzJrPjsKPj4+ICsJCQljbG9ja3Mg PSA8JnJfY2N1IDM+LCA8Jm9zYzI0TT4sIDwmb3NjMzJrPjsKPj4+ICAJCQljbG9jay1uYW1lcyA9 ICJhcGIiLCAiaG9zYyIsICJsb3NjIjsKPj4+IC0JCQlyZXNldHMgPSA8JmFwYjBfcmVzZXQgMD47 Cj4+PiAgCQkJZ3Bpby1jb250cm9sbGVyOwo+Pj4gIAkJCSNncGlvLWNlbGxzID0gPDM+Owo+Pj4g IAkJCWludGVycnVwdC1jb250cm9sbGVyOwo+Pj4gLS0KPj4+IDIuMTIuMgo+Pj4gCj4+IF9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4+IGxpbnV4LWFybS1r ZXJuZWwgbWFpbGluZyBsaXN0Cj4+IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9y Zwo+PiBodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFy bS1rZXJuZWwKPiAKPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fXwo+IGxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0Cj4gbGludXgtYXJtLWtlcm5lbEBs aXN0cy5pbmZyYWRlYWQub3JnCj4gaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9s aXN0aW5mby9saW51eC1hcm0ta2VybmVsCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 5:15 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy-h8G6r0blFSE @ 2017-07-20 5:15 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Chen-Yu Tsai, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, Maxime Ripard, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r 在 2017-07-20 10:03,icenowy-h8G6r0blFSE@public.gmane.org 写道: > 在 2017-07-20 06:59,Ondřej Jirman 写道: >> Hi, >> >> Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >>> From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >>> >>> Now we have driver for the PRCM CCU, switch to use it instead of >>> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >>> >>> The mux 3 of R_CCU is still the internal oscillator, which is said to >>> be >>> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >>> two >>> H3 boards and one H5 board. >> >> There's issue with the new r_ccu that breaks r_i2c. (no devices can be >> found on the bus). Reverting this patch fixes the issue with the I2C >> controller. (everything else being the same) >> >> Here's the code I'm using: >> https://github.com/megous/linux/commits/oran >> ge-pi-4.12 >> >> The last commit is the revert. >> >> The issue manifests itself by non-working DVFS, because kernel lacks >> access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng >> clock driver (sun8i-r). >> >> Relevant difference in registers between working/non-working state is >> just this (diff -u): >> >> 0x01f02400 = 0x00000000 >> 0x01f02404 = 0x00000000 >> -0x01f02408 = 0x00000091 >> +0x01f02408 = 0x00000095 DATA register inisde the I2C controller >> 0x01f0240c = 0x00000044 >> 0x01f02410 = 0x000000f8 >> -0x01f02414 = 0x00000059 >> +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C >> controller >> 0x01f02418 = 0x00000000 >> 0x01f0241c = 0x00000000 >> 0x01f02420 = 0x0000003a >> >> It looks like the new sunxi-ng clock driver causes the I2C driver to >> not correctly configure the CLOCK register. I don't know why and I'm >> not sure how to deal with this. Any ideas what can I do next? >> >> thank you and regards, >> o. > > It seems to be a very very very weird problem -- the CPUS_CFG register > seems to be not accessible in non-secure mode on H3, and if the r_ccu > driver reads it a value of 0x0 is read out (which means that the parent > of ar100 is osc32k), but the real initial value of the register is > 0x00010000 (which means the parent is osc24M). > > So the bus clock of r_i2c is wrongly claimed as 32kHz, not 24MHz, then > the r_i2c fails to work. The protection to AR100 registers can be removed by writing 1 to 0x01f015d0 (0x1d0 at PRCM memory region). Interestingly this controlling register can be written in non-secure world, so it's still broken secure/non-secure division ;-) > > This clock problem doesn't exist for A64. > >> >>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >>> --- >>> Changes in v4: >>> - Temporarily dropped the CCU headers. >>> Changes in v3: >>> - Change osc32000 to iosc. >>> >>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >>> ++++++++++++-------------------------- >>> 1 file changed, 14 insertions(+), 31 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> index 6640ebfa6419..1aeeacb3a884 100644 >>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >>> @@ -68,31 +68,12 @@ >>> clock-output-names = "osc32k"; >>> }; >>> >>> - apb0: apb0_clk { >>> - compatible = "fixed-factor-clock"; >>> + iosc: internal-osc-clk { >>> #clock-cells = <0>; >>> - clock-div = <1>; >>> - clock-mult = <1>; >>> - clocks = <&osc24M>; >>> - clock-output-names = "apb0"; >>> - }; >>> - >>> - apb0_gates: clk@01f01428 { >>> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >>> - "allwinner,sun4i-a10-gates-clk"; >>> - reg = <0x01f01428 0x4>; >>> - #clock-cells = <1>; >>> - clocks = <&apb0>; >>> - clock-indices = <0>, <1>; >>> - clock-output-names = "apb0_pio", "apb0_ir"; >>> - }; >>> - >>> - ir_clk: ir_clk@01f01454 { >>> - compatible = "allwinner,sun4i-a10-mod0-clk"; >>> - reg = <0x01f01454 0x4>; >>> - #clock-cells = <0>; >>> - clocks = <&osc32k>, <&osc24M>; >>> - clock-output-names = "ir"; >>> + compatible = "fixed-clock"; >>> + clock-frequency = <16000000>; >>> + clock-accuracy = <300000000>; >>> + clock-output-names = "iosc"; >>> }; >>> }; >>> >>> @@ -576,9 +557,12 @@ >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>> >>> - apb0_reset: reset@01f014b0 { >>> - reg = <0x01f014b0 0x4>; >>> - compatible = "allwinner,sun6i-a31-clock-reset"; >>> + r_ccu: clock@1f01400 { >>> + compatible = "allwinner,sun50i-a64-r-ccu"; >>> + reg = <0x01f01400 0x100>; >>> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >>> + clock-names = "hosc", "losc", "iosc"; >>> + #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> @@ -589,9 +573,9 @@ >>> >>> ir: ir@01f02000 { >>> compatible = "allwinner,sun5i-a13-ir"; >>> - clocks = <&apb0_gates 1>, <&ir_clk>; >>> + clocks = <&r_ccu 4>, <&r_ccu 11>; >>> clock-names = "apb", "ir"; >>> - resets = <&apb0_reset 1>; >>> + resets = <&r_ccu 0>; >>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >>> reg = <0x01f02000 0x40>; >>> status = "disabled"; >>> @@ -601,9 +585,8 @@ >>> compatible = "allwinner,sun8i-h3-r-pinctrl"; >>> reg = <0x01f02c00 0x400>; >>> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >>> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >>> clock-names = "apb", "hosc", "losc"; >>> - resets = <&apb0_reset 0>; >>> gpio-controller; >>> #gpio-cells = <3>; >>> interrupt-controller; >>> -- >>> 2.12.2 >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 8:21 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 8:21 UTC (permalink / raw) To: Ondřej Jirman Cc: Maxime Ripard, Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel 在 2017-07-20 06:59,Ondřej Jirman 写道: > Hi, > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy@aosc.xyz> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? Could you apply the patches at [1] and [2] to U-Boot and re-try with r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which makes it possible to be accessed from the kernel running in non-secure. I think these patches can solve this problem. [1] https://patchwork.ozlabs.org/patch/791414/ [2] https://patchwork.ozlabs.org/patch/791415/ > > thank you and regards, > o. > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk@01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk@01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset@01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock@1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir@01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 8:21 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy at aosc.io @ 2017-07-20 8:21 UTC (permalink / raw) To: linux-arm-kernel ? 2017-07-20 06:59?Ond?ej Jirman ??? > Hi, > > Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy@aosc.xyz> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? Could you apply the patches at [1] and [2] to U-Boot and re-try with r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which makes it possible to be accessed from the kernel running in non-secure. I think these patches can solve this problem. [1] https://patchwork.ozlabs.org/patch/791414/ [2] https://patchwork.ozlabs.org/patch/791415/ > > thank you and regards, > o. > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk at 01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk at 01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset at 01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock at 1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir at 01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 8:21 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy @ 2017-07-20 8:21 UTC (permalink / raw) To: Ondřej Jirman Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-sunxi, Icenowy Zheng, Maxime Ripard, linux-clk, linux-arm-kernel 5ZyoIDIwMTctMDctMjAgMDY6NTnvvIxPbmTFmWVqIEppcm1hbiDlhpnpgZPvvJoKPiBIaSwKPiAK PiBJY2Vub3d5IFpoZW5nIHDDrcWhZSB2IMOadCAwNC4gMDQuIDIwMTcgdiAxNzo1MCArMDgwMDoK Pj4gRnJvbTogSWNlbm93eSBaaGVuZyA8aWNlbm93eUBhb3NjLnh5ej4KPj4gCj4+IE5vdyB3ZSBo YXZlIGRyaXZlciBmb3IgdGhlIFBSQ00gQ0NVLCBzd2l0Y2ggdG8gdXNlIGl0IGluc3RlYWQgb2YK Pj4gb2xkLXN0eWxlIGNsb2NrIG5vZGVzIGZvciBhcGIwLXJlbGF0ZWQgY2xvY2tzIGluIHN1bnhp LWgzLWg1LmR0c2kgLgo+PiAKPj4gVGhlIG11eCAzIG9mIFJfQ0NVIGlzIHN0aWxsIHRoZSBpbnRl cm5hbCBvc2NpbGxhdG9yLCB3aGljaCBpcyBzYWlkIHRvIAo+PiBiZQo+PiAxNk1IeiBwbHVzIG1p bnVzIDMwJSwgYW5kIGdldCBhIG1lYXN1cmVkIHZhbHVlIG9mIDE1TUh6fjE2TUh6IG9uIG15IAo+ PiB0d28KPj4gSDMgYm9hcmRzIGFuZCBvbmUgSDUgYm9hcmQuCj4gCj4gVGhlcmUncyBpc3N1ZSB3 aXRoIHRoZSBuZXcgcl9jY3UgdGhhdCBicmVha3Mgcl9pMmMuIChubyBkZXZpY2VzIGNhbiBiZQo+ IGZvdW5kIG9uIHRoZSBidXMpLiBSZXZlcnRpbmcgdGhpcyBwYXRjaCBmaXhlcyB0aGUgaXNzdWUg d2l0aCB0aGUgSTJDCj4gY29udHJvbGxlci4gKGV2ZXJ5dGhpbmcgZWxzZSBiZWluZyB0aGUgc2Ft ZSkKPiAKPiBIZXJlJ3MgdGhlIGNvZGUgSSdtIHVzaW5nOiBodHRwczovL2dpdGh1Yi5jb20vbWVn b3VzL2xpbnV4L2NvbW1pdHMvb3Jhbgo+IGdlLXBpLTQuMTIKPiAKPiBUaGUgbGFzdCBjb21taXQg aXMgdGhlIHJldmVydC4KPiAKPiBUaGUgaXNzdWUgbWFuaWZlc3RzIGl0c2VsZiBieSBub24td29y a2luZyBEVkZTLCBiZWNhdXNlIGtlcm5lbCBsYWNrcwo+IGFjY2VzcyB0byBTWTgxMDZBIHJlZ3Vs YXRvciwgYmVjYXVzZSByX2kyYyBkb2Vzbid0IHdvcmsgd2l0aCBzdW54aS1uZwo+IGNsb2NrIGRy aXZlciAoc3VuOGktcikuCj4gCj4gUmVsZXZhbnQgZGlmZmVyZW5jZSBpbiByZWdpc3RlcnMgYmV0 d2VlbiB3b3JraW5nL25vbi13b3JraW5nIHN0YXRlIGlzCj4ganVzdCB0aGlzIChkaWZmIC11KToK PiAKPiAgMHgwMWYwMjQwMCA9IDB4MDAwMDAwMDAKPiAgMHgwMWYwMjQwNCA9IDB4MDAwMDAwMDAK PiAtMHgwMWYwMjQwOCA9IDB4MDAwMDAwOTEKPiArMHgwMWYwMjQwOCA9IDB4MDAwMDAwOTUgREFU QSByZWdpc3RlciBpbmlzZGUgdGhlIEkyQyBjb250cm9sbGVyCj4gIDB4MDFmMDI0MGMgPSAweDAw MDAwMDQ0Cj4gIDB4MDFmMDI0MTAgPSAweDAwMDAwMGY4Cj4gLTB4MDFmMDI0MTQgPSAweDAwMDAw MDU5Cj4gKzB4MDFmMDI0MTQgPSAweDAwMDAwMDAwIENMT0NLIHNldHVwIHJlZ2lzdGVyIGluc2lk ZSB0aGUgSTJDIGNvbnRyb2xsZXIKPiAgMHgwMWYwMjQxOCA9IDB4MDAwMDAwMDAKPiAgMHgwMWYw MjQxYyA9IDB4MDAwMDAwMDAKPiAgMHgwMWYwMjQyMCA9IDB4MDAwMDAwM2EKPiAKPiBJdCBsb29r cyBsaWtlIHRoZSBuZXcgc3VueGktbmcgY2xvY2sgZHJpdmVyIGNhdXNlcyB0aGUgSTJDIGRyaXZl ciB0bwo+IG5vdCBjb3JyZWN0bHkgY29uZmlndXJlIHRoZSBDTE9DSyByZWdpc3Rlci4gSSBkb24n dCBrbm93IHdoeSBhbmQgSSdtCj4gbm90IHN1cmUgaG93IHRvIGRlYWwgd2l0aCB0aGlzLiBBbnkg aWRlYXMgd2hhdCBjYW4gSSBkbyBuZXh0PwoKQ291bGQgeW91IGFwcGx5IHRoZSBwYXRjaGVzIGF0 IFsxXSBhbmQgWzJdIHRvIFUtQm9vdCBhbmQgcmUtdHJ5IHdpdGgKcl9jY3U/IFRoZXkgc3dpdGNo ZWQgdGhlIENQVXMgY2xvY2sgb2Ygcl9jY3UgdG8gbm9uLXNlY3VyZSBtb2RlLCB3aGljaAptYWtl cyBpdCBwb3NzaWJsZSB0byBiZSBhY2Nlc3NlZCBmcm9tIHRoZSBrZXJuZWwgcnVubmluZyBpbiBu b24tc2VjdXJlLgoKSSB0aGluayB0aGVzZSBwYXRjaGVzIGNhbiBzb2x2ZSB0aGlzIHByb2JsZW0u CgpbMV0gaHR0cHM6Ly9wYXRjaHdvcmsub3psYWJzLm9yZy9wYXRjaC83OTE0MTQvClsyXSBodHRw czovL3BhdGNod29yay5vemxhYnMub3JnL3BhdGNoLzc5MTQxNS8KCj4gCj4gdGhhbmsgeW91IGFu ZCByZWdhcmRzLAo+ICAgby4KPiAKPj4gU2lnbmVkLW9mZi1ieTogSWNlbm93eSBaaGVuZyA8aWNl bm93eUBhb3NjLnh5ej4KPj4gLS0tCj4+IENoYW5nZXMgaW4gdjQ6Cj4+IC0gVGVtcG9yYXJpbHkg ZHJvcHBlZCB0aGUgQ0NVIGhlYWRlcnMuCj4+IENoYW5nZXMgaW4gdjM6Cj4+IC0gQ2hhbmdlIG9z YzMyMDAwIHRvIGlvc2MuCj4+IAo+PiAgYXJjaC9hcm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRz aSB8IDQ1IAo+PiArKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQo+PiAgMSBm aWxlIGNoYW5nZWQsIDE0IGluc2VydGlvbnMoKyksIDMxIGRlbGV0aW9ucygtKQo+PiAKPj4gZGlm ZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bnhpLWgzLWg1LmR0c2kgCj4+IGIvYXJjaC9h cm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRzaQo+PiBpbmRleCA2NjQwZWJmYTY0MTkuLjFhZWVh Y2IzYTg4NCAxMDA2NDQKPj4gLS0tIGEvYXJjaC9hcm0vYm9vdC9kdHMvc3VueGktaDMtaDUuZHRz aQo+PiArKysgYi9hcmNoL2FybS9ib290L2R0cy9zdW54aS1oMy1oNS5kdHNpCj4+IEBAIC02OCwz MSArNjgsMTIgQEAKPj4gIAkJCWNsb2NrLW91dHB1dC1uYW1lcyA9ICJvc2MzMmsiOwo+PiAgCQl9 Owo+PiAKPj4gLQkJYXBiMDogYXBiMF9jbGsgewo+PiAtCQkJY29tcGF0aWJsZSA9ICJmaXhlZC1m YWN0b3ItY2xvY2siOwo+PiArCQlpb3NjOiBpbnRlcm5hbC1vc2MtY2xrIHsKPj4gIAkJCSNjbG9j ay1jZWxscyA9IDwwPjsKPj4gLQkJCWNsb2NrLWRpdiA9IDwxPjsKPj4gLQkJCWNsb2NrLW11bHQg PSA8MT47Cj4+IC0JCQljbG9ja3MgPSA8Jm9zYzI0TT47Cj4+IC0JCQljbG9jay1vdXRwdXQtbmFt ZXMgPSAiYXBiMCI7Cj4+IC0JCX07Cj4+IC0KPj4gLQkJYXBiMF9nYXRlczogY2xrQDAxZjAxNDI4 IHsKPj4gLQkJCWNvbXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjhpLWgzLWFwYjAtZ2F0ZXMtY2xr IiwKPj4gLQkJCQkgICAgICJhbGx3aW5uZXIsc3VuNGktYTEwLWdhdGVzLWNsayI7Cj4+IC0JCQly ZWcgPSA8MHgwMWYwMTQyOCAweDQ+Owo+PiAtCQkJI2Nsb2NrLWNlbGxzID0gPDE+Owo+PiAtCQkJ Y2xvY2tzID0gPCZhcGIwPjsKPj4gLQkJCWNsb2NrLWluZGljZXMgPSA8MD4sIDwxPjsKPj4gLQkJ CWNsb2NrLW91dHB1dC1uYW1lcyA9ICJhcGIwX3BpbyIsICJhcGIwX2lyIjsKPj4gLQkJfTsKPj4g LQo+PiAtCQlpcl9jbGs6IGlyX2Nsa0AwMWYwMTQ1NCB7Cj4+IC0JCQljb21wYXRpYmxlID0gImFs bHdpbm5lcixzdW40aS1hMTAtbW9kMC1jbGsiOwo+PiAtCQkJcmVnID0gPDB4MDFmMDE0NTQgMHg0 PjsKPj4gLQkJCSNjbG9jay1jZWxscyA9IDwwPjsKPj4gLQkJCWNsb2NrcyA9IDwmb3NjMzJrPiwg PCZvc2MyNE0+Owo+PiAtCQkJY2xvY2stb3V0cHV0LW5hbWVzID0gImlyIjsKPj4gKwkJCWNvbXBh dGlibGUgPSAiZml4ZWQtY2xvY2siOwo+PiArCQkJY2xvY2stZnJlcXVlbmN5ID0gPDE2MDAwMDAw PjsKPj4gKwkJCWNsb2NrLWFjY3VyYWN5ID0gPDMwMDAwMDAwMD47Cj4+ICsJCQljbG9jay1vdXRw dXQtbmFtZXMgPSAiaW9zYyI7Cj4+ICAJCX07Cj4+ICAJfTsKPj4gCj4+IEBAIC01NzYsOSArNTU3 LDEyIEBACj4+ICAJCQkJICAgICA8R0lDX1NQSSA0MSBJUlFfVFlQRV9MRVZFTF9ISUdIPjsKPj4g IAkJfTsKPj4gCj4+IC0JCWFwYjBfcmVzZXQ6IHJlc2V0QDAxZjAxNGIwIHsKPj4gLQkJCXJlZyA9 IDwweDAxZjAxNGIwIDB4ND47Cj4+IC0JCQljb21wYXRpYmxlID0gImFsbHdpbm5lcixzdW42aS1h MzEtY2xvY2stcmVzZXQiOwo+PiArCQlyX2NjdTogY2xvY2tAMWYwMTQwMCB7Cj4+ICsJCQljb21w YXRpYmxlID0gImFsbHdpbm5lcixzdW41MGktYTY0LXItY2N1IjsKPj4gKwkJCXJlZyA9IDwweDAx ZjAxNDAwIDB4MTAwPjsKPj4gKwkJCWNsb2NrcyA9IDwmb3NjMjRNPiwgPCZvc2MzMms+LCA8Jmlv c2M+Owo+PiArCQkJY2xvY2stbmFtZXMgPSAiaG9zYyIsICJsb3NjIiwgImlvc2MiOwo+PiArCQkJ I2Nsb2NrLWNlbGxzID0gPDE+Owo+PiAgCQkJI3Jlc2V0LWNlbGxzID0gPDE+Owo+PiAgCQl9Owo+ PiAKPj4gQEAgLTU4OSw5ICs1NzMsOSBAQAo+PiAKPj4gIAkJaXI6IGlyQDAxZjAyMDAwIHsKPj4g IAkJCWNvbXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjVpLWExMy1pciI7Cj4+IC0JCQljbG9ja3Mg PSA8JmFwYjBfZ2F0ZXMgMT4sIDwmaXJfY2xrPjsKPj4gKwkJCWNsb2NrcyA9IDwmcl9jY3UgND4s IDwmcl9jY3UgMTE+Owo+PiAgCQkJY2xvY2stbmFtZXMgPSAiYXBiIiwgImlyIjsKPj4gLQkJCXJl c2V0cyA9IDwmYXBiMF9yZXNldCAxPjsKPj4gKwkJCXJlc2V0cyA9IDwmcl9jY3UgMD47Cj4+ICAJ CQlpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMzcgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+ICAJCQly ZWcgPSA8MHgwMWYwMjAwMCAweDQwPjsKPj4gIAkJCXN0YXR1cyA9ICJkaXNhYmxlZCI7Cj4+IEBA IC02MDEsOSArNTg1LDggQEAKPj4gIAkJCWNvbXBhdGlibGUgPSAiYWxsd2lubmVyLHN1bjhpLWgz LXItcGluY3RybCI7Cj4+ICAJCQlyZWcgPSA8MHgwMWYwMmMwMCAweDQwMD47Cj4+ICAJCQlpbnRl cnJ1cHRzID0gPEdJQ19TUEkgNDUgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+IC0JCQljbG9ja3Mg PSA8JmFwYjBfZ2F0ZXMgMD4sIDwmb3NjMjRNPiwgPCZvc2MzMms+Owo+PiArCQkJY2xvY2tzID0g PCZyX2NjdSAzPiwgPCZvc2MyNE0+LCA8Jm9zYzMyaz47Cj4+ICAJCQljbG9jay1uYW1lcyA9ICJh cGIiLCAiaG9zYyIsICJsb3NjIjsKPj4gLQkJCXJlc2V0cyA9IDwmYXBiMF9yZXNldCAwPjsKPj4g IAkJCWdwaW8tY29udHJvbGxlcjsKPj4gIAkJCSNncGlvLWNlbGxzID0gPDM+Owo+PiAgCQkJaW50 ZXJydXB0LWNvbnRyb2xsZXI7Cj4+IC0tCj4+IDIuMTIuMgo+PiAKPiBfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+IGxpbnV4LWFybS1rZXJuZWwgbWFpbGlu ZyBsaXN0Cj4gbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCj4gaHR0cDovL2xp c3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2Vy bmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVs Cg== ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 8:21 ` icenowy-h8G6r0blFSE 0 siblings, 0 replies; 48+ messages in thread From: icenowy-h8G6r0blFSE @ 2017-07-20 8:21 UTC (permalink / raw) To: Ondřej Jirman Cc: Maxime Ripard, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r 在 2017-07-20 06:59,Ondřej Jirman 写道: > Hi, > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: >> From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >> >> Now we have driver for the PRCM CCU, switch to use it instead of >> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . >> >> The mux 3 of R_CCU is still the internal oscillator, which is said to >> be >> 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my >> two >> H3 boards and one H5 board. > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > found on the bus). Reverting this patch fixes the issue with the I2C > controller. (everything else being the same) > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > ge-pi-4.12 > > The last commit is the revert. > > The issue manifests itself by non-working DVFS, because kernel lacks > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > clock driver (sun8i-r). > > Relevant difference in registers between working/non-working state is > just this (diff -u): > > 0x01f02400 = 0x00000000 > 0x01f02404 = 0x00000000 > -0x01f02408 = 0x00000091 > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > 0x01f0240c = 0x00000044 > 0x01f02410 = 0x000000f8 > -0x01f02414 = 0x00000059 > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > 0x01f02418 = 0x00000000 > 0x01f0241c = 0x00000000 > 0x01f02420 = 0x0000003a > > It looks like the new sunxi-ng clock driver causes the I2C driver to > not correctly configure the CLOCK register. I don't know why and I'm > not sure how to deal with this. Any ideas what can I do next? Could you apply the patches at [1] and [2] to U-Boot and re-try with r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which makes it possible to be accessed from the kernel running in non-secure. I think these patches can solve this problem. [1] https://patchwork.ozlabs.org/patch/791414/ [2] https://patchwork.ozlabs.org/patch/791415/ > > thank you and regards, > o. > >> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> >> --- >> Changes in v4: >> - Temporarily dropped the CCU headers. >> Changes in v3: >> - Change osc32000 to iosc. >> >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 >> ++++++++++++-------------------------- >> 1 file changed, 14 insertions(+), 31 deletions(-) >> >> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> index 6640ebfa6419..1aeeacb3a884 100644 >> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi >> @@ -68,31 +68,12 @@ >> clock-output-names = "osc32k"; >> }; >> >> - apb0: apb0_clk { >> - compatible = "fixed-factor-clock"; >> + iosc: internal-osc-clk { >> #clock-cells = <0>; >> - clock-div = <1>; >> - clock-mult = <1>; >> - clocks = <&osc24M>; >> - clock-output-names = "apb0"; >> - }; >> - >> - apb0_gates: clk@01f01428 { >> - compatible = "allwinner,sun8i-h3-apb0-gates-clk", >> - "allwinner,sun4i-a10-gates-clk"; >> - reg = <0x01f01428 0x4>; >> - #clock-cells = <1>; >> - clocks = <&apb0>; >> - clock-indices = <0>, <1>; >> - clock-output-names = "apb0_pio", "apb0_ir"; >> - }; >> - >> - ir_clk: ir_clk@01f01454 { >> - compatible = "allwinner,sun4i-a10-mod0-clk"; >> - reg = <0x01f01454 0x4>; >> - #clock-cells = <0>; >> - clocks = <&osc32k>, <&osc24M>; >> - clock-output-names = "ir"; >> + compatible = "fixed-clock"; >> + clock-frequency = <16000000>; >> + clock-accuracy = <300000000>; >> + clock-output-names = "iosc"; >> }; >> }; >> >> @@ -576,9 +557,12 @@ >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> - apb0_reset: reset@01f014b0 { >> - reg = <0x01f014b0 0x4>; >> - compatible = "allwinner,sun6i-a31-clock-reset"; >> + r_ccu: clock@1f01400 { >> + compatible = "allwinner,sun50i-a64-r-ccu"; >> + reg = <0x01f01400 0x100>; >> + clocks = <&osc24M>, <&osc32k>, <&iosc>; >> + clock-names = "hosc", "losc", "iosc"; >> + #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> @@ -589,9 +573,9 @@ >> >> ir: ir@01f02000 { >> compatible = "allwinner,sun5i-a13-ir"; >> - clocks = <&apb0_gates 1>, <&ir_clk>; >> + clocks = <&r_ccu 4>, <&r_ccu 11>; >> clock-names = "apb", "ir"; >> - resets = <&apb0_reset 1>; >> + resets = <&r_ccu 0>; >> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0x01f02000 0x40>; >> status = "disabled"; >> @@ -601,9 +585,8 @@ >> compatible = "allwinner,sun8i-h3-r-pinctrl"; >> reg = <0x01f02c00 0x400>; >> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; >> + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; >> clock-names = "apb", "hosc", "losc"; >> - resets = <&apb0_reset 0>; >> gpio-controller; >> #gpio-cells = <3>; >> interrupt-controller; >> -- >> 2.12.2 >> > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 12:12 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: Ondřej Jirman @ 2017-07-20 12:12 UTC (permalink / raw) To: icenowy Cc: Maxime Ripard, Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel Hi Icenowy, icenowy@aosc.io píše v Čt 20. 07. 2017 v 16:21 +0800: > 在 2017-07-20 06:59,Ondřej Jirman 写道: > > Hi, > > > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: > > > From: Icenowy Zheng <icenowy@aosc.xyz> > > > > > > Now we have driver for the PRCM CCU, switch to use it instead of > > > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > > > > > The mux 3 of R_CCU is still the internal oscillator, which is said to > > > be > > > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my > > > two > > > H3 boards and one H5 board. > > > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > > found on the bus). Reverting this patch fixes the issue with the I2C > > controller. (everything else being the same) > > > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > > ge-pi-4.12 > > > > The last commit is the revert. > > > > The issue manifests itself by non-working DVFS, because kernel lacks > > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > > clock driver (sun8i-r). > > > > Relevant difference in registers between working/non-working state is > > just this (diff -u): > > > > 0x01f02400 = 0x00000000 > > 0x01f02404 = 0x00000000 > > -0x01f02408 = 0x00000091 > > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > > 0x01f0240c = 0x00000044 > > 0x01f02410 = 0x000000f8 > > -0x01f02414 = 0x00000059 > > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > > 0x01f02418 = 0x00000000 > > 0x01f0241c = 0x00000000 > > 0x01f02420 = 0x0000003a > > > > It looks like the new sunxi-ng clock driver causes the I2C driver to > > not correctly configure the CLOCK register. I don't know why and I'm > > not sure how to deal with this. Any ideas what can I do next? > > Could you apply the patches at [1] and [2] to U-Boot and re-try with > r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which > makes it possible to be accessed from the kernel running in non-secure. I have verified that r_ccu works correctly with the u-boot patches on H3 and H5. Thank you very much for looking into the issue. :) regards, o. > I think these patches can solve this problem. > > [1] https://patchwork.ozlabs.org/patch/791414/ > [2] https://patchwork.ozlabs.org/patch/791415/ ^ permalink raw reply [flat|nested] 48+ messages in thread
* [linux-sunxi] [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 12:12 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: Ondřej Jirman @ 2017-07-20 12:12 UTC (permalink / raw) To: linux-arm-kernel Hi Icenowy, icenowy at aosc.io p??e v ?t 20. 07. 2017 v 16:21 +0800: > ? 2017-07-20 06:59?Ond?ej Jirman ??? > > Hi, > > > > Icenowy Zheng p??e v ?t 04. 04. 2017 v 17:50 +0800: > > > From: Icenowy Zheng <icenowy@aosc.xyz> > > > > > > Now we have driver for the PRCM CCU, switch to use it instead of > > > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > > > > > The mux 3 of R_CCU is still the internal oscillator, which is said to > > > be > > > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my > > > two > > > H3 boards and one H5 board. > > > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > > found on the bus). Reverting this patch fixes the issue with the I2C > > controller. (everything else being the same) > > > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > > ge-pi-4.12 > > > > The last commit is the revert. > > > > The issue manifests itself by non-working DVFS, because kernel lacks > > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > > clock driver (sun8i-r). > > > > Relevant difference in registers between working/non-working state is > > just this (diff -u): > > > > 0x01f02400 = 0x00000000 > > 0x01f02404 = 0x00000000 > > -0x01f02408 = 0x00000091 > > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > > 0x01f0240c = 0x00000044 > > 0x01f02410 = 0x000000f8 > > -0x01f02414 = 0x00000059 > > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > > 0x01f02418 = 0x00000000 > > 0x01f0241c = 0x00000000 > > 0x01f02420 = 0x0000003a > > > > It looks like the new sunxi-ng clock driver causes the I2C driver to > > not correctly configure the CLOCK register. I don't know why and I'm > > not sure how to deal with this. Any ideas what can I do next? > > Could you apply the patches at [1] and [2] to U-Boot and re-try with > r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which > makes it possible to be accessed from the kernel running in non-secure. I have verified that r_ccu works correctly with the u-boot patches on H3 and H5. Thank you very much for looking into the issue. :) regards, o. > I think these patches can solve this problem. > > [1] https://patchwork.ozlabs.org/patch/791414/ > [2] https://patchwork.ozlabs.org/patch/791415/ ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu @ 2017-07-20 12:12 ` 'Ondřej Jirman' via linux-sunxi 0 siblings, 0 replies; 48+ messages in thread From: 'Ondřej Jirman' via linux-sunxi @ 2017-07-20 12:12 UTC (permalink / raw) To: icenowy-h8G6r0blFSE Cc: Maxime Ripard, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Icenowy, icenowy-h8G6r0blFSE@public.gmane.org píše v Čt 20. 07. 2017 v 16:21 +0800: > 在 2017-07-20 06:59,Ondřej Jirman 写道: > > Hi, > > > > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800: > > > From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> > > > > > > Now we have driver for the PRCM CCU, switch to use it instead of > > > old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi . > > > > > > The mux 3 of R_CCU is still the internal oscillator, which is said to > > > be > > > 16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my > > > two > > > H3 boards and one H5 board. > > > > There's issue with the new r_ccu that breaks r_i2c. (no devices can be > > found on the bus). Reverting this patch fixes the issue with the I2C > > controller. (everything else being the same) > > > > Here's the code I'm using: https://github.com/megous/linux/commits/oran > > ge-pi-4.12 > > > > The last commit is the revert. > > > > The issue manifests itself by non-working DVFS, because kernel lacks > > access to SY8106A regulator, because r_i2c doesn't work with sunxi-ng > > clock driver (sun8i-r). > > > > Relevant difference in registers between working/non-working state is > > just this (diff -u): > > > > 0x01f02400 = 0x00000000 > > 0x01f02404 = 0x00000000 > > -0x01f02408 = 0x00000091 > > +0x01f02408 = 0x00000095 DATA register inisde the I2C controller > > 0x01f0240c = 0x00000044 > > 0x01f02410 = 0x000000f8 > > -0x01f02414 = 0x00000059 > > +0x01f02414 = 0x00000000 CLOCK setup register inside the I2C controller > > 0x01f02418 = 0x00000000 > > 0x01f0241c = 0x00000000 > > 0x01f02420 = 0x0000003a > > > > It looks like the new sunxi-ng clock driver causes the I2C driver to > > not correctly configure the CLOCK register. I don't know why and I'm > > not sure how to deal with this. Any ideas what can I do next? > > Could you apply the patches at [1] and [2] to U-Boot and re-try with > r_ccu? They switched the CPUs clock of r_ccu to non-secure mode, which > makes it possible to be accessed from the kernel running in non-secure. I have verified that r_ccu works correctly with the u-boot patches on H3 and H5. Thank you very much for looking into the issue. :) regards, o. > I think these patches can solve this problem. > > [1] https://patchwork.ozlabs.org/patch/791414/ > [2] https://patchwork.ozlabs.org/patch/791415/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node @ 2017-04-04 9:51 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:51 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng From: Icenowy Zheng <icenowy@aosc.xyz> Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1d4e5bcced0c..6bc606b4d74d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -409,5 +409,17 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node @ 2017-04-04 9:51 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:51 UTC (permalink / raw) To: linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1d4e5bcced0c..6bc606b4d74d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -409,5 +409,17 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl at 01f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node @ 2017-04-04 9:51 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:51 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: devicetree, linux-kernel, linux-sunxi, Icenowy Zheng, linux-clk, linux-arm-kernel From: Icenowy Zheng <icenowy@aosc.xyz> Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1d4e5bcced0c..6bc606b4d74d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -409,5 +409,17 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- 2.12.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node @ 2017-04-04 9:51 ` Icenowy Zheng 0 siblings, 0 replies; 48+ messages in thread From: Icenowy Zheng @ 2017-04-04 9:51 UTC (permalink / raw) To: Maxime Ripard, Chen-Yu Tsai, Rob Herring Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1d4e5bcced0c..6bc606b4d74d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -409,5 +409,17 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- 2.12.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 15:45 ` Maxime Ripard 0 siblings, 0 replies; 48+ messages in thread From: Maxime Ripard @ 2017-04-04 15:45 UTC (permalink / raw) To: Icenowy Zheng Cc: Chen-Yu Tsai, Rob Herring, linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 713 bytes --] On Tue, Apr 04, 2017 at 05:50:55PM +0800, Icenowy Zheng wrote: > Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. > (V3s and R40 do not have it, as they have even no PRCM) > > This patch adds support for the ones on H3/A64. > > Some clock/reset values are reserved for easier extending the support to > A31/A23, but for this I think some changes to the PRCM MFD should be made, > see [1] (Although this is only a sketch). > > The r_pio device node is also added for A64, as the driver is already > merged, and its depends (r_ccu) is now met. Applied all, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 15:45 ` Maxime Ripard 0 siblings, 0 replies; 48+ messages in thread From: Maxime Ripard @ 2017-04-04 15:45 UTC (permalink / raw) To: linux-arm-kernel On Tue, Apr 04, 2017 at 05:50:55PM +0800, Icenowy Zheng wrote: > Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. > (V3s and R40 do not have it, as they have even no PRCM) > > This patch adds support for the ones on H3/A64. > > Some clock/reset values are reserved for easier extending the support to > A31/A23, but for this I think some changes to the PRCM MFD should be made, > see [1] (Although this is only a sketch). > > The r_pio device node is also added for A64, as the driver is already > merged, and its depends (r_ccu) is now met. Applied all, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170404/bcf68c72/attachment-0001.sig> ^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs @ 2017-04-04 15:45 ` Maxime Ripard 0 siblings, 0 replies; 48+ messages in thread From: Maxime Ripard @ 2017-04-04 15:45 UTC (permalink / raw) To: Icenowy Zheng Cc: Chen-Yu Tsai, Rob Herring, linux-clk-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw [-- Attachment #1: Type: text/plain, Size: 692 bytes --] On Tue, Apr 04, 2017 at 05:50:55PM +0800, Icenowy Zheng wrote: > Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part. > (V3s and R40 do not have it, as they have even no PRCM) > > This patch adds support for the ones on H3/A64. > > Some clock/reset values are reserved for easier extending the support to > A31/A23, but for this I think some changes to the PRCM MFD should be made, > see [1] (Although this is only a sketch). > > The r_pio device node is also added for A64, as the driver is already > merged, and its depends (r_ccu) is now met. Applied all, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com ^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2017-07-20 12:12 UTC | newest] Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-04-04 9:50 [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` [PATCH v4 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` [PATCH v4 2/5] clk: sunxi-ng: add support for " Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` [PATCH v4 3/5] arm64: allwinner: a64: add r_ccu node Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` [PATCH v4 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-04-04 9:50 ` Icenowy Zheng 2017-07-19 22:59 ` [linux-sunxi] " Ondřej Jirman 2017-07-19 22:59 ` Ondřej Jirman 2017-07-19 22:59 ` 'Ondřej Jirman' via linux-sunxi 2017-07-20 2:03 ` [linux-sunxi] " icenowy 2017-07-20 2:03 ` icenowy at aosc.io 2017-07-20 2:03 ` icenowy 2017-07-20 2:03 ` icenowy-h8G6r0blFSE 2017-07-20 2:19 ` [linux-sunxi] " icenowy 2017-07-20 2:19 ` icenowy at aosc.io 2017-07-20 2:19 ` icenowy 2017-07-20 2:19 ` icenowy-h8G6r0blFSE 2017-07-20 5:15 ` [linux-sunxi] " icenowy 2017-07-20 5:15 ` icenowy at aosc.io 2017-07-20 5:15 ` icenowy 2017-07-20 5:15 ` icenowy-h8G6r0blFSE 2017-07-20 8:21 ` [linux-sunxi] " icenowy 2017-07-20 8:21 ` icenowy at aosc.io 2017-07-20 8:21 ` icenowy 2017-07-20 8:21 ` icenowy-h8G6r0blFSE 2017-07-20 12:12 ` [linux-sunxi] " Ondřej Jirman 2017-07-20 12:12 ` Ondřej Jirman 2017-07-20 12:12 ` 'Ondřej Jirman' via linux-sunxi 2017-04-04 9:51 ` [PATCH v4 5/5] arm64: allwinner: a64: add R_PIO pinctrl node Icenowy Zheng 2017-04-04 9:51 ` Icenowy Zheng 2017-04-04 9:51 ` Icenowy Zheng 2017-04-04 9:51 ` Icenowy Zheng 2017-04-04 15:45 ` [PATCH v4 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Maxime Ripard 2017-04-04 15:45 ` Maxime Ripard 2017-04-04 15:45 ` Maxime Ripard
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.