* [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround
@ 2017-04-05 13:04 Madhav Chauhan
2017-04-05 13:22 ` ✓ Fi.CI.BAT: success for drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2) Patchwork
2017-04-06 11:47 ` [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Jani Nikula
0 siblings, 2 replies; 3+ messages in thread
From: Madhav Chauhan @ 2017-04-05 13:04 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, shashidhar.hiremath
As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values (HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption, explained below:
1. For DSI AUO panel(1920x1200 @60) required pixclk is 157100 KHZ
2. glk_calc_cdclk returns 79200 KHZ for this pixclk, For 2PPC it
will be 158400 KHZ
3. Practically 100% of the cdclk can’t be achieved, so 99% of 158400
KHZ = 156816 which is less than the desired pixlclk and causes
panel corruption.
v2: Rebased to new CDLCK code framework
v3: Addressed review comments from Ander/Jani
- Add comment in code about 99% usage of CDCLK
- Calculate max dot clock as well with 99% limit
v4 by Jani:
- drop superfluous whitespace change
- rewrite code comments to clarify
v5: Added details of non-working scenario in commit message
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index dd3ad52..763010f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1071,9 +1071,15 @@ static int bxt_calc_cdclk(int max_pixclk)
static int glk_calc_cdclk(int max_pixclk)
{
- if (max_pixclk > 2 * 158400)
+ /*
+ * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
+ * as a temporary workaround. Use a higher cdclk instead. (Note that
+ * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
+ * cdclk.)
+ */
+ if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
return 316800;
- else if (max_pixclk > 2 * 79200)
+ else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
return 158400;
else
return 79200;
@@ -1664,7 +1670,11 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
int max_cdclk_freq = dev_priv->max_cdclk_freq;
if (IS_GEMINILAKE(dev_priv))
- return 2 * max_cdclk_freq;
+ /*
+ * FIXME: Limiting to 99% as a temporary workaround. See
+ * glk_calc_cdclk() for details.
+ */
+ return 2 * max_cdclk_freq * 99 / 100;
else if (INTEL_INFO(dev_priv)->gen >= 9 ||
IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return max_cdclk_freq;
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2)
2017-04-05 13:04 [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Madhav Chauhan
@ 2017-04-05 13:22 ` Patchwork
2017-04-06 11:47 ` [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Jani Nikula
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2017-04-05 13:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2)
URL : https://patchwork.freedesktop.org/series/22404/
State : success
== Summary ==
Series 22404v2 drm/i915/glk: limit pixel clock to 99% of cdclk workaround
https://patchwork.freedesktop.org/api/1.0/series/22404/revisions/2/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass -> FAIL (fi-snb-2600) fdo#100007
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
incomplete -> PASS (fi-snb-2520m)
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 429s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time: 425s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time: 581s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 503s
fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time: 547s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time: 485s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 481s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 410s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 400s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 419s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 490s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 465s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 457s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time: 564s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 456s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 568s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 459s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 483s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time: 431s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 539s
fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time: 404s
3c5f424b9e2697352118ee33514b29b7cd57f69c drm-tip: 2017y-04m-05d-11h-46m-45s UTC integration manifest
6dbd9dc drm/i915/glk: limit pixel clock to 99% of cdclk workaround
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4408/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround
2017-04-05 13:04 [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Madhav Chauhan
2017-04-05 13:22 ` ✓ Fi.CI.BAT: success for drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2) Patchwork
@ 2017-04-06 11:47 ` Jani Nikula
1 sibling, 0 replies; 3+ messages in thread
From: Jani Nikula @ 2017-04-06 11:47 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
Cc: ander.conselvan.de.oliveira, shashidhar.hiremath
On Wed, 05 Apr 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
> Practically we can achive only 99% of these cdclk values (HW team
> checking on this). So cdclk should be calculated for the given pixclk as
> per that otherwise it may lead to screen corruption, explained below:
> 1. For DSI AUO panel(1920x1200 @60) required pixclk is 157100 KHZ
> 2. glk_calc_cdclk returns 79200 KHZ for this pixclk, For 2PPC it
> will be 158400 KHZ
> 3. Practically 100% of the cdclk can’t be achieved, so 99% of 158400
> KHZ = 156816 which is less than the desired pixlclk and causes
> panel corruption.
>
> v2: Rebased to new CDLCK code framework
> v3: Addressed review comments from Ander/Jani
> - Add comment in code about 99% usage of CDCLK
> - Calculate max dot clock as well with 99% limit
> v4 by Jani:
> - drop superfluous whitespace change
> - rewrite code comments to clarify
> v5: Added details of non-working scenario in commit message
>
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Pushed to drm-intel-next-queued, thanks for the patch and review.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index dd3ad52..763010f 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1071,9 +1071,15 @@ static int bxt_calc_cdclk(int max_pixclk)
>
> static int glk_calc_cdclk(int max_pixclk)
> {
> - if (max_pixclk > 2 * 158400)
> + /*
> + * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
> + * as a temporary workaround. Use a higher cdclk instead. (Note that
> + * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
> + * cdclk.)
> + */
> + if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
> return 316800;
> - else if (max_pixclk > 2 * 79200)
> + else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
> return 158400;
> else
> return 79200;
> @@ -1664,7 +1670,11 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
>
> if (IS_GEMINILAKE(dev_priv))
> - return 2 * max_cdclk_freq;
> + /*
> + * FIXME: Limiting to 99% as a temporary workaround. See
> + * glk_calc_cdclk() for details.
> + */
> + return 2 * max_cdclk_freq * 99 / 100;
> else if (INTEL_INFO(dev_priv)->gen >= 9 ||
> IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return max_cdclk_freq;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2017-04-05 13:04 [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Madhav Chauhan
2017-04-05 13:22 ` ✓ Fi.CI.BAT: success for drm/i915/glk: limit pixel clock to 99% of cdclk workaround (rev2) Patchwork
2017-04-06 11:47 ` [PATCH] drm/i915/glk: limit pixel clock to 99% of cdclk workaround Jani Nikula
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