[U-Boot] [PATCH 1/2] arm: Correct signature for get_ticks()

[U-Boot] [PATCH 1/2] arm: Correct signature for get_ticks()

[Simon Glass]

This should be uint64_t to match its definition in common.h. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/cpu/armv8/generic_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index cd92b2c761..a2dda333fe 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -43,7 +43,7 @@ unsigned long timer_read_counter(void)
 	return cntpct;
 }
 
-unsigned long long get_ticks(void)
+uint64_t get_ticks(void)
 {
 	unsigned long ticks = timer_read_counter();
 
-- 
2.12.2.715.g7642488e1d-goog

[U-Boot] [PATCH 2/2] arm: Support cache invalidate

[Simon Glass]

At present there is not operation to invalidate a cache range. This seems
to be needed to fill out the cache operations. Add an implementation based
on the flush operation.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/cpu/armv8/cache.S    | 24 ++++++++++++++++++++++++
 arch/arm/cpu/armv8/cache_v8.c |  2 +-
 arch/arm/include/asm/system.h | 15 +++++++++++++++
 3 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index f1deaa7230..7cba308ee7 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -138,6 +138,30 @@ ENTRY(__asm_flush_dcache_range)
 	dsb	sy
 	ret
 ENDPROC(__asm_flush_dcache_range)
+/*
+ * void __asm_invalidate_dcache_range(start, end)
+ *
+ * invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+ENTRY(__asm_invalidate_dcache_range)
+	mrs	x3, ctr_el0
+	ubfm	x3, x3, #16, #19
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	ivac, x0	/* invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(__asm_invalidate_dcache_range)
 
 /*
  * void __asm_invalidate_icache_all(void)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index bd1c3e0335..adc7e1746f 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -446,7 +446,7 @@ inline void flush_dcache_all(void)
  */
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-	__asm_flush_dcache_range(start, stop);
+	__asm_invalidate_dcache_range(start, stop);
 }
 
 /*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9c3261c884..79bd19af7d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -180,6 +180,21 @@ static inline unsigned long read_mpidr(void)
 void __asm_flush_dcache_all(void);
 void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
+
+/**
+ * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
+ *
+ * This performance an invalidate from @start to @end - 1. Both addresses
+ * should be cache-aligned, otherwise this function will align the start
+ * address and may continue past the end address.
+ *
+ * Data in the address range is evicted from the cache and is not written back
+ * to memory.
+ *
+ * @start: Start address to invalidate
+ * @end: End address to invalidate up to (exclusive)
+ */
+void __asm_invalidate_dcache_range(u64 start, u64 end);
 void __asm_invalidate_tlb_all(void);
 void __asm_invalidate_icache_all(void);
 int __asm_invalidate_l3_dcache(void);
-- 
2.12.2.715.g7642488e1d-goog

[U-Boot] [PATCH 2/2] arm: Support cache invalidate

[york sun]

On 04/05/2017 04:53 PM, Simon Glass wrote:
> At present there is not operation to invalidate a cache range. This seems
> to be needed to fill out the cache operations. Add an implementation based
> on the flush operation.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/arm/cpu/armv8/cache.S    | 24 ++++++++++++++++++++++++
>  arch/arm/cpu/armv8/cache_v8.c |  2 +-
>  arch/arm/include/asm/system.h | 15 +++++++++++++++
>  3 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
> index f1deaa7230..7cba308ee7 100644
> --- a/arch/arm/cpu/armv8/cache.S
> +++ b/arch/arm/cpu/armv8/cache.S
> @@ -138,6 +138,30 @@ ENTRY(__asm_flush_dcache_range)
>  	dsb	sy
>  	ret
>  ENDPROC(__asm_flush_dcache_range)
> +/*
> + * void __asm_invalidate_dcache_range(start, end)
> + *
> + * invalidate data cache in the range
> + *
> + * x0: start address
> + * x1: end address
> + */
> +ENTRY(__asm_invalidate_dcache_range)
> +	mrs	x3, ctr_el0
> +	ubfm	x3, x3, #16, #19
> +	mov	x2, #4
> +	lsl	x2, x2, x3		/* cache line size */
> +
> +	/* x2 <- minimal cache line size in cache system */
> +	sub	x3, x2, #1
> +	bic	x0, x0, x3
> +1:	dc	ivac, x0	/* invalidate data or unified cache */
> +	add	x0, x0, x2
> +	cmp	x0, x1
> +	b.lo	1b
> +	dsb	sy
> +	ret
> +ENDPROC(__asm_invalidate_dcache_range)
>

The only difference from __asm_flush_dcache_range is the dcivac vs 
dccivac. It can also be wrapped up like we have for 
__asm_invalidate_dcache_all. This function is small enough to be 
duplicated though.

Reviewed-by: York Sun <york.sun@nxp.com>

[U-Boot] [U-Boot,1/2] arm: Correct signature for get_ticks()

[Tom Rini]

On Wed, Apr 05, 2017 at 05:53:17PM -0600, Simon Glass wrote:

> This should be uint64_t to match its definition in common.h. Fix it.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot,2/2] arm: Support cache invalidate

[Tom Rini]

On Wed, Apr 05, 2017 at 05:53:18PM -0600, Simon Glass wrote:

> At present there is not operation to invalidate a cache range. This seems
> to be needed to fill out the cache operations. Add an implementation based
> on the flush operation.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: York Sun <york.sun@nxp.com>

Applied to u-boot/master, thanks!

-- 
Tom
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