* [U-Boot] [PATCH 1/3] Blackfin: Remove
@ 2017-03-14 15:08 Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 2/3] SPARC: Remove Tom Rini
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Tom Rini @ 2017-03-14 15:08 UTC (permalink / raw)
To: u-boot
The architecture is currently unmaintained, remove.
Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
.travis.yml | 3 +-
MAINTAINERS | 6 -
README | 8 -
arch/Kconfig | 5 -
arch/blackfin/Kconfig | 150 -
arch/blackfin/Makefile | 8 -
arch/blackfin/config.mk | 68 -
arch/blackfin/cpu/.gitignore | 2 -
arch/blackfin/cpu/Makefile | 45 -
arch/blackfin/cpu/cache.S | 87 -
arch/blackfin/cpu/cpu.c | 415 --
arch/blackfin/cpu/cpu.h | 23 -
arch/blackfin/cpu/gpio.c | 841 ----
arch/blackfin/cpu/init.S | 9 -
arch/blackfin/cpu/init.lds.S | 25 -
arch/blackfin/cpu/initcode.c | 1041 -----
arch/blackfin/cpu/initcode.h | 123 -
arch/blackfin/cpu/interrupt.S | 157 -
arch/blackfin/cpu/interrupts.c | 151 -
arch/blackfin/cpu/jtag-console.c | 228 --
arch/blackfin/cpu/os_log.c | 30 -
arch/blackfin/cpu/reset.c | 96 -
arch/blackfin/cpu/start.S | 263 --
arch/blackfin/cpu/traps.c | 435 ---
arch/blackfin/cpu/u-boot.lds | 142 -
arch/blackfin/include/asm/bfin_logo_230x230_gzip.h | 2377 ------------
arch/blackfin/include/asm/bfin_logo_230x230_lzma.h | 1819 ---------
.../include/asm/bfin_logo_rgb565_230x230_gzip.h | 1242 ------
.../include/asm/bfin_logo_rgb565_230x230_lzma.h | 1079 ------
arch/blackfin/include/asm/bitops.h | 358 --
arch/blackfin/include/asm/blackfin.h | 15 -
arch/blackfin/include/asm/blackfin_cdef.h | 91 -
arch/blackfin/include/asm/blackfin_def.h | 145 -
arch/blackfin/include/asm/blackfin_local.h | 208 -
arch/blackfin/include/asm/byteorder.h | 24 -
arch/blackfin/include/asm/cache.h | 70 -
arch/blackfin/include/asm/clock.h | 88 -
arch/blackfin/include/asm/config-pre.h | 82 -
arch/blackfin/include/asm/config.h | 176 -
arch/blackfin/include/asm/cplb.h | 99 -
arch/blackfin/include/asm/deferred.h | 20 -
arch/blackfin/include/asm/delay.h | 39 -
arch/blackfin/include/asm/dma.h | 104 -
arch/blackfin/include/asm/entry.h | 243 --
arch/blackfin/include/asm/global_data.h | 26 -
arch/blackfin/include/asm/gpio.h | 167 -
arch/blackfin/include/asm/io.h | 228 --
arch/blackfin/include/asm/linkage.h | 12 -
arch/blackfin/include/asm/mach-bf506/BF504_cdef.h | 1782 ---------
arch/blackfin/include/asm/mach-bf506/BF504_def.h | 944 -----
arch/blackfin/include/asm/mach-bf506/BF506_cdef.h | 11 -
arch/blackfin/include/asm/mach-bf506/BF506_def.h | 11 -
arch/blackfin/include/asm/mach-bf506/anomaly.h | 145 -
arch/blackfin/include/asm/mach-bf506/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf506/gpio.h | 52 -
arch/blackfin/include/asm/mach-bf506/portmux.h | 148 -
arch/blackfin/include/asm/mach-bf506/ports.h | 59 -
arch/blackfin/include/asm/mach-bf518/BF512_cdef.h | 1000 -----
arch/blackfin/include/asm/mach-bf518/BF512_def.h | 517 ---
arch/blackfin/include/asm/mach-bf518/BF514_cdef.h | 68 -
arch/blackfin/include/asm/mach-bf518/BF514_def.h | 40 -
arch/blackfin/include/asm/mach-bf518/BF516_cdef.h | 170 -
arch/blackfin/include/asm/mach-bf518/BF516_def.h | 91 -
arch/blackfin/include/asm/mach-bf518/BF518_cdef.h | 58 -
arch/blackfin/include/asm/mach-bf518/BF518_def.h | 35 -
arch/blackfin/include/asm/mach-bf518/anomaly.h | 170 -
arch/blackfin/include/asm/mach-bf518/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf518/gpio.h | 58 -
arch/blackfin/include/asm/mach-bf518/portmux.h | 201 -
arch/blackfin/include/asm/mach-bf518/ports.h | 59 -
arch/blackfin/include/asm/mach-bf527/BF522_cdef.h | 1012 -----
arch/blackfin/include/asm/mach-bf527/BF522_def.h | 513 ---
arch/blackfin/include/asm/mach-bf527/BF523_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf527/BF523_def.h | 1 -
arch/blackfin/include/asm/mach-bf527/BF524_cdef.h | 350 --
arch/blackfin/include/asm/mach-bf527/BF524_def.h | 181 -
arch/blackfin/include/asm/mach-bf527/BF525_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf527/BF525_def.h | 1 -
arch/blackfin/include/asm/mach-bf527/BF526_cdef.h | 170 -
arch/blackfin/include/asm/mach-bf527/BF526_def.h | 91 -
arch/blackfin/include/asm/mach-bf527/BF527_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf527/BF527_def.h | 1 -
arch/blackfin/include/asm/mach-bf527/anomaly.h | 290 --
arch/blackfin/include/asm/mach-bf527/def_local.h | 6 -
arch/blackfin/include/asm/mach-bf527/gpio.h | 65 -
arch/blackfin/include/asm/mach-bf527/mem_map.h | 21 -
arch/blackfin/include/asm/mach-bf527/portmux.h | 220 --
arch/blackfin/include/asm/mach-bf527/ports.h | 60 -
arch/blackfin/include/asm/mach-bf533/BF531_cdef.h | 872 -----
arch/blackfin/include/asm/mach-bf533/BF531_def.h | 444 ---
arch/blackfin/include/asm/mach-bf533/BF532_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf533/BF532_def.h | 17 -
arch/blackfin/include/asm/mach-bf533/BF533_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf533/BF533_def.h | 21 -
arch/blackfin/include/asm/mach-bf533/anomaly.h | 383 --
arch/blackfin/include/asm/mach-bf533/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf533/gpio.h | 31 -
arch/blackfin/include/asm/mach-bf533/portmux.h | 71 -
arch/blackfin/include/asm/mach-bf533/ports.h | 10 -
arch/blackfin/include/asm/mach-bf537/BF534_cdef.h | 1624 --------
arch/blackfin/include/asm/mach-bf537/BF534_def.h | 831 ----
arch/blackfin/include/asm/mach-bf537/BF536_cdef.h | 170 -
arch/blackfin/include/asm/mach-bf537/BF536_def.h | 91 -
arch/blackfin/include/asm/mach-bf537/BF537_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf537/BF537_def.h | 1 -
arch/blackfin/include/asm/mach-bf537/anomaly.h | 241 --
arch/blackfin/include/asm/mach-bf537/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf537/gpio.h | 65 -
arch/blackfin/include/asm/mach-bf537/portmux.h | 152 -
arch/blackfin/include/asm/mach-bf537/ports.h | 28 -
arch/blackfin/include/asm/mach-bf538/BF538_cdef.h | 2014 ----------
arch/blackfin/include/asm/mach-bf538/BF538_def.h | 1025 -----
arch/blackfin/include/asm/mach-bf538/BF539_cdef.h | 1 -
arch/blackfin/include/asm/mach-bf538/BF539_def.h | 1 -
arch/blackfin/include/asm/mach-bf538/anomaly.h | 215 --
arch/blackfin/include/asm/mach-bf538/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf538/gpio.h | 73 -
arch/blackfin/include/asm/mach-bf538/portmux.h | 114 -
arch/blackfin/include/asm/mach-bf538/ports.h | 13 -
.../asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h | 2913 --------------
.../asm/mach-bf548/ADSP-EDN-BF542-extended_def.h | 1463 -------
.../asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h | 3309 ----------------
.../asm/mach-bf548/ADSP-EDN-BF544-extended_def.h | 1661 --------
.../asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h | 2404 ------------
.../asm/mach-bf548/ADSP-EDN-BF547-extended_def.h | 1209 ------
.../asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h | 3852 ------------------
.../asm/mach-bf548/ADSP-EDN-BF548-extended_def.h | 1933 ---------
.../asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h | 4084 --------------------
.../asm/mach-bf548/ADSP-EDN-BF549-extended_def.h | 2049 ----------
arch/blackfin/include/asm/mach-bf548/BF542_cdef.h | 20 -
arch/blackfin/include/asm/mach-bf548/BF542_def.h | 17 -
arch/blackfin/include/asm/mach-bf548/BF544_cdef.h | 20 -
arch/blackfin/include/asm/mach-bf548/BF544_def.h | 17 -
arch/blackfin/include/asm/mach-bf548/BF547_cdef.h | 20 -
arch/blackfin/include/asm/mach-bf548/BF547_def.h | 17 -
arch/blackfin/include/asm/mach-bf548/BF548_cdef.h | 20 -
arch/blackfin/include/asm/mach-bf548/BF548_def.h | 17 -
arch/blackfin/include/asm/mach-bf548/BF549_cdef.h | 20 -
arch/blackfin/include/asm/mach-bf548/BF549_def.h | 17 -
arch/blackfin/include/asm/mach-bf548/anomaly.h | 303 --
arch/blackfin/include/asm/mach-bf548/def_local.h | 6 -
arch/blackfin/include/asm/mach-bf548/gpio.h | 203 -
arch/blackfin/include/asm/mach-bf548/mem_map.h | 21 -
arch/blackfin/include/asm/mach-bf548/portmux.h | 320 --
arch/blackfin/include/asm/mach-bf548/ports.h | 106 -
arch/blackfin/include/asm/mach-bf561/BF561_cdef.h | 1410 -------
arch/blackfin/include/asm/mach-bf561/BF561_def.h | 719 ----
arch/blackfin/include/asm/mach-bf561/anomaly.h | 349 --
arch/blackfin/include/asm/mach-bf561/def_local.h | 16 -
arch/blackfin/include/asm/mach-bf561/gpio.h | 65 -
arch/blackfin/include/asm/mach-bf561/portmux.h | 97 -
arch/blackfin/include/asm/mach-bf561/ports.h | 44 -
arch/blackfin/include/asm/mach-bf609/BF609_cdef.h | 192 -
arch/blackfin/include/asm/mach-bf609/BF609_def.h | 254 --
arch/blackfin/include/asm/mach-bf609/anomaly.h | 97 -
arch/blackfin/include/asm/mach-bf609/def_local.h | 5 -
arch/blackfin/include/asm/mach-bf609/gpio.h | 151 -
arch/blackfin/include/asm/mach-bf609/portmux.h | 257 --
arch/blackfin/include/asm/mach-bf609/ports.h | 103 -
.../include/asm/mach-common/ADSP-EDN-core_cdef.h | 276 --
.../include/asm/mach-common/ADSP-EDN-core_def.h | 147 -
.../include/asm/mach-common/bits/bootrom.h | 293 --
arch/blackfin/include/asm/mach-common/bits/cgu.h | 80 -
arch/blackfin/include/asm/mach-common/bits/core.h | 112 -
arch/blackfin/include/asm/mach-common/bits/dde.h | 88 -
arch/blackfin/include/asm/mach-common/bits/dma.h | 102 -
arch/blackfin/include/asm/mach-common/bits/ebiu.h | 440 ---
arch/blackfin/include/asm/mach-common/bits/emac.h | 223 --
arch/blackfin/include/asm/mach-common/bits/eppi.h | 70 -
arch/blackfin/include/asm/mach-common/bits/mpu.h | 120 -
arch/blackfin/include/asm/mach-common/bits/otp.h | 71 -
arch/blackfin/include/asm/mach-common/bits/pata.h | 220 --
arch/blackfin/include/asm/mach-common/bits/pll.h | 101 -
.../include/asm/mach-common/bits/ports-a.h | 25 -
.../include/asm/mach-common/bits/ports-b.h | 25 -
.../include/asm/mach-common/bits/ports-c.h | 25 -
.../include/asm/mach-common/bits/ports-d.h | 25 -
.../include/asm/mach-common/bits/ports-e.h | 25 -
.../include/asm/mach-common/bits/ports-f.h | 25 -
.../include/asm/mach-common/bits/ports-g.h | 25 -
.../include/asm/mach-common/bits/ports-h.h | 25 -
.../include/asm/mach-common/bits/ports-i.h | 25 -
.../include/asm/mach-common/bits/ports-j.h | 25 -
arch/blackfin/include/asm/mach-common/bits/ppi.h | 38 -
arch/blackfin/include/asm/mach-common/bits/rtc.h | 42 -
arch/blackfin/include/asm/mach-common/bits/sdh.h | 156 -
arch/blackfin/include/asm/mach-common/bits/spi.h | 67 -
.../blackfin/include/asm/mach-common/bits/spi6xx.h | 240 --
arch/blackfin/include/asm/mach-common/bits/timer.h | 78 -
arch/blackfin/include/asm/mach-common/bits/trace.h | 19 -
arch/blackfin/include/asm/mach-common/bits/twi.h | 77 -
arch/blackfin/include/asm/mach-common/bits/uart.h | 98 -
arch/blackfin/include/asm/mach-common/bits/uart4.h | 66 -
arch/blackfin/include/asm/mach-common/bits/usb.h | 264 --
.../include/asm/mach-common/bits/watchdog.h | 19 -
arch/blackfin/include/asm/mem_map.h | 26 -
arch/blackfin/include/asm/portmux.h | 1193 ------
arch/blackfin/include/asm/posix_types.h | 72 -
arch/blackfin/include/asm/processor.h | 19 -
arch/blackfin/include/asm/ptrace.h | 198 -
arch/blackfin/include/asm/sdh.h | 17 -
arch/blackfin/include/asm/sections.h | 11 -
arch/blackfin/include/asm/serial.h | 131 -
arch/blackfin/include/asm/serial1.h | 342 --
arch/blackfin/include/asm/serial4.h | 150 -
arch/blackfin/include/asm/shared_resources.h | 17 -
arch/blackfin/include/asm/signal.h | 1 -
arch/blackfin/include/asm/soft_switch.h | 18 -
arch/blackfin/include/asm/string.h | 63 -
arch/blackfin/include/asm/system.h | 107 -
arch/blackfin/include/asm/traps.h | 50 -
arch/blackfin/include/asm/twi.h | 15 -
arch/blackfin/include/asm/types.h | 70 -
arch/blackfin/include/asm/u-boot.h | 36 -
arch/blackfin/include/asm/unaligned.h | 1 -
arch/blackfin/lib/.gitignore | 1 -
arch/blackfin/lib/Makefile | 27 -
arch/blackfin/lib/__kgdb.S | 154 -
arch/blackfin/lib/boot.c | 74 -
arch/blackfin/lib/cache.c | 123 -
arch/blackfin/lib/clocks.c | 140 -
arch/blackfin/lib/cmd_cache_dump.c | 146 -
arch/blackfin/lib/ins.S | 118 -
arch/blackfin/lib/kgdb.c | 423 --
arch/blackfin/lib/kgdb.h | 160 -
arch/blackfin/lib/memcmp.S | 90 -
arch/blackfin/lib/memcpy.S | 104 -
arch/blackfin/lib/memmove.S | 83 -
arch/blackfin/lib/memset.S | 83 -
arch/blackfin/lib/muldi3.c | 76 -
arch/blackfin/lib/outs.S | 64 -
arch/blackfin/lib/post.c | 85 -
arch/blackfin/lib/sections.c | 11 -
arch/blackfin/lib/string.c | 268 --
board/bct-brettl2/Kconfig | 9 -
board/bct-brettl2/MAINTAINERS | 6 -
board/bct-brettl2/Makefile | 13 -
board/bct-brettl2/bct-brettl2.c | 109 -
board/bct-brettl2/cled.c | 32 -
board/bct-brettl2/gpio_cfi_flash.c | 4 -
board/bct-brettl2/smsc9303.c | 176 -
board/bct-brettl2/smsc9303.h | 9 -
board/bf506f-ezkit/Kconfig | 9 -
board/bf506f-ezkit/MAINTAINERS | 6 -
board/bf506f-ezkit/Makefile | 12 -
board/bf506f-ezkit/bf506f-ezkit.c | 27 -
board/bf518f-ezbrd/Kconfig | 9 -
board/bf518f-ezbrd/MAINTAINERS | 6 -
board/bf518f-ezbrd/Makefile | 12 -
board/bf518f-ezbrd/bf518f-ezbrd.c | 162 -
board/bf525-ucr2/Kconfig | 9 -
board/bf525-ucr2/MAINTAINERS | 7 -
board/bf525-ucr2/Makefile | 12 -
board/bf525-ucr2/bf525-ucr2.c | 16 -
board/bf526-ezbrd/Kconfig | 9 -
board/bf526-ezbrd/MAINTAINERS | 6 -
board/bf526-ezbrd/Makefile | 12 -
board/bf526-ezbrd/bf526-ezbrd.c | 60 -
board/bf527-ad7160-eval/Kconfig | 9 -
board/bf527-ad7160-eval/MAINTAINERS | 6 -
board/bf527-ad7160-eval/Makefile | 12 -
board/bf527-ad7160-eval/bf527-ad7160-eval.c | 25 -
board/bf527-ezkit/Kconfig | 9 -
board/bf527-ezkit/MAINTAINERS | 7 -
board/bf527-ezkit/Makefile | 13 -
board/bf527-ezkit/bf527-ezkit.c | 72 -
board/bf527-ezkit/video.c | 445 ---
board/bf527-sdp/Kconfig | 9 -
board/bf527-sdp/MAINTAINERS | 6 -
board/bf527-sdp/Makefile | 12 -
board/bf527-sdp/bf527-sdp.c | 32 -
board/bf527-sdp/config.mk | 11 -
board/bf533-ezkit/Kconfig | 9 -
board/bf533-ezkit/MAINTAINERS | 6 -
board/bf533-ezkit/Makefile | 12 -
board/bf533-ezkit/bf533-ezkit.c | 44 -
board/bf533-ezkit/config.mk | 11 -
board/bf533-ezkit/flash-defines.h | 106 -
board/bf533-ezkit/flash.c | 473 ---
board/bf533-ezkit/psd4256.h | 51 -
board/bf533-stamp/Kconfig | 9 -
board/bf533-stamp/MAINTAINERS | 6 -
board/bf533-stamp/Makefile | 14 -
board/bf533-stamp/bf533-stamp.c | 127 -
board/bf533-stamp/config.mk | 11 -
board/bf533-stamp/ide-cf.c | 98 -
board/bf533-stamp/video.c | 169 -
board/bf533-stamp/video.h | 22 -
board/bf537-minotaur/Kconfig | 9 -
board/bf537-minotaur/MAINTAINERS | 6 -
board/bf537-minotaur/Makefile | 12 -
board/bf537-minotaur/bf537-minotaur.c | 30 -
board/bf537-minotaur/config.mk | 11 -
board/bf537-pnav/Kconfig | 9 -
board/bf537-pnav/MAINTAINERS | 6 -
board/bf537-pnav/Makefile | 12 -
board/bf537-pnav/bf537-pnav.c | 30 -
board/bf537-srv1/Kconfig | 9 -
board/bf537-srv1/MAINTAINERS | 6 -
board/bf537-srv1/Makefile | 12 -
board/bf537-srv1/bf537-srv1.c | 30 -
board/bf537-srv1/config.mk | 11 -
board/bf537-stamp/Kconfig | 9 -
board/bf537-stamp/MAINTAINERS | 6 -
board/bf537-stamp/Makefile | 14 -
board/bf537-stamp/bf537-stamp.c | 68 -
board/bf537-stamp/config.mk | 12 -
board/bf537-stamp/ide-cf.c | 66 -
board/bf537-stamp/post-memory.c | 257 --
board/bf538f-ezkit/Kconfig | 9 -
board/bf538f-ezkit/MAINTAINERS | 6 -
board/bf538f-ezkit/Makefile | 12 -
board/bf538f-ezkit/bf538f-ezkit.c | 28 -
board/bf538f-ezkit/config.mk | 11 -
board/bf548-ezkit/Kconfig | 9 -
board/bf548-ezkit/MAINTAINERS | 6 -
board/bf548-ezkit/Makefile | 13 -
board/bf548-ezkit/bf548-ezkit.c | 64 -
board/bf548-ezkit/config.mk | 15 -
board/bf548-ezkit/video.c | 335 --
board/bf561-acvilon/Kconfig | 9 -
board/bf561-acvilon/MAINTAINERS | 6 -
board/bf561-acvilon/Makefile | 14 -
board/bf561-acvilon/bf561-acvilon.c | 38 -
board/bf561-acvilon/config.mk | 11 -
board/bf561-ezkit/Kconfig | 9 -
board/bf561-ezkit/MAINTAINERS | 6 -
board/bf561-ezkit/Makefile | 12 -
board/bf561-ezkit/bf561-ezkit.c | 30 -
board/bf561-ezkit/config.mk | 11 -
board/bf609-ezkit/Kconfig | 9 -
board/bf609-ezkit/MAINTAINERS | 6 -
board/bf609-ezkit/Makefile | 13 -
board/bf609-ezkit/bf609-ezkit.c | 68 -
board/bf609-ezkit/soft_switch.c | 171 -
board/bf609-ezkit/soft_switch.h | 80 -
board/blackstamp/Kconfig | 9 -
board/blackstamp/MAINTAINERS | 8 -
board/blackstamp/Makefile | 12 -
board/blackstamp/blackstamp.c | 41 -
board/blackvme/Kconfig | 9 -
board/blackvme/MAINTAINERS | 8 -
board/blackvme/Makefile | 12 -
board/blackvme/blackvme.c | 31 -
board/br4/Kconfig | 9 -
board/br4/MAINTAINERS | 6 -
board/br4/Makefile | 14 -
board/br4/br4.c | 30 -
board/cm-bf527/Kconfig | 9 -
board/cm-bf527/MAINTAINERS | 6 -
board/cm-bf527/Makefile | 12 -
board/cm-bf527/cm-bf527.c | 62 -
board/cm-bf527/gpio_cfi_flash.c | 3 -
board/cm-bf533/Kconfig | 9 -
board/cm-bf533/MAINTAINERS | 6 -
board/cm-bf533/Makefile | 12 -
board/cm-bf533/cm-bf533.c | 26 -
board/cm-bf533/config.mk | 11 -
board/cm-bf537e/Kconfig | 9 -
board/cm-bf537e/MAINTAINERS | 6 -
board/cm-bf537e/Makefile | 12 -
board/cm-bf537e/cm-bf537e.c | 44 -
board/cm-bf537e/config.mk | 11 -
board/cm-bf537e/gpio_cfi_flash.c | 81 -
board/cm-bf537e/gpio_cfi_flash.h | 10 -
board/cm-bf537u/Kconfig | 9 -
board/cm-bf537u/MAINTAINERS | 6 -
board/cm-bf537u/Makefile | 12 -
board/cm-bf537u/cm-bf537u.c | 44 -
board/cm-bf537u/config.mk | 11 -
board/cm-bf537u/gpio_cfi_flash.c | 2 -
board/cm-bf548/Kconfig | 9 -
board/cm-bf548/MAINTAINERS | 6 -
board/cm-bf548/Makefile | 13 -
board/cm-bf548/cm-bf548.c | 43 -
board/cm-bf548/config.mk | 14 -
board/cm-bf548/video.c | 339 --
board/cm-bf561/Kconfig | 9 -
board/cm-bf561/MAINTAINERS | 6 -
board/cm-bf561/Makefile | 12 -
board/cm-bf561/cm-bf561.c | 26 -
board/cm-bf561/config.mk | 11 -
board/dnp5370/Kconfig | 9 -
board/dnp5370/MAINTAINERS | 6 -
board/dnp5370/Makefile | 12 -
board/dnp5370/README | 67 -
board/dnp5370/dnp5370.c | 73 -
board/ip04/Kconfig | 9 -
board/ip04/MAINTAINERS | 6 -
board/ip04/Makefile | 12 -
board/ip04/config.mk | 12 -
board/ip04/ip04.c | 29 -
board/pr1/Kconfig | 9 -
board/pr1/MAINTAINERS | 6 -
board/pr1/Makefile | 14 -
board/pr1/pr1.c | 30 -
board/tcm-bf518/Kconfig | 9 -
board/tcm-bf518/MAINTAINERS | 6 -
board/tcm-bf518/Makefile | 12 -
board/tcm-bf518/tcm-bf518.c | 37 -
board/tcm-bf537/Kconfig | 9 -
board/tcm-bf537/MAINTAINERS | 6 -
board/tcm-bf537/Makefile | 12 -
board/tcm-bf537/config.mk | 11 -
board/tcm-bf537/gpio_cfi_flash.c | 3 -
board/tcm-bf537/tcm-bf537.c | 44 -
cmd/bdinfo.c | 18 -
cmd/mem.c | 43 -
cmd/reginfo.c | 57 -
common/Kconfig | 2 +-
common/board_f.c | 19 +-
configs/bct-brettl2_defconfig | 15 -
configs/bf506f-ezkit_defconfig | 28 -
configs/bf518f-ezbrd_defconfig | 26 -
configs/bf525-ucr2_defconfig | 11 -
configs/bf526-ezbrd_defconfig | 24 -
configs/bf527-ad7160-eval_defconfig | 21 -
configs/bf527-ezkit-v2_defconfig | 25 -
configs/bf527-ezkit_defconfig | 24 -
configs/bf527-sdp_defconfig | 23 -
configs/bf533-ezkit_defconfig | 15 -
configs/bf533-stamp_defconfig | 17 -
configs/bf537-minotaur_defconfig | 15 -
configs/bf537-pnav_defconfig | 19 -
configs/bf537-srv1_defconfig | 15 -
configs/bf537-stamp_defconfig | 29 -
configs/bf538f-ezkit_defconfig | 16 -
configs/bf548-ezkit_defconfig | 27 -
configs/bf561-acvilon_defconfig | 20 -
configs/bf561-ezkit_defconfig | 14 -
configs/bf609-ezkit_defconfig | 29 -
configs/blackstamp_defconfig | 12 -
configs/blackvme_defconfig | 13 -
configs/br4_defconfig | 21 -
configs/cm-bf527_defconfig | 16 -
configs/cm-bf533_defconfig | 13 -
configs/cm-bf537e_defconfig | 21 -
configs/cm-bf537u_defconfig | 20 -
configs/cm-bf548_defconfig | 17 -
configs/cm-bf561_defconfig | 13 -
configs/dnp5370_defconfig | 9 -
configs/ibf-dsp561_defconfig | 13 -
configs/ip04_defconfig | 19 -
configs/pr1_defconfig | 21 -
configs/tcm-bf518_defconfig | 17 -
configs/tcm-bf537_defconfig | 21 -
drivers/bootcount/Makefile | 1 -
drivers/bootcount/bootcount_blackfin.c | 34 -
drivers/i2c/Makefile | 1 -
drivers/i2c/pca9564_i2c.c | 179 -
drivers/mtd/nand/nand_base.c | 2 -
drivers/net/smc91111.h | 7 -
drivers/serial/Makefile | 1 -
drivers/serial/serial_bfin.c | 411 --
drivers/spi/Makefile | 2 -
drivers/spi/bfin_spi.c | 309 --
drivers/spi/bfin_spi6xx.c | 305 --
drivers/usb/musb-new/musb_core.c | 9 +-
drivers/usb/musb-new/musb_core.h | 33 +-
drivers/usb/musb-new/musb_dma.h | 11 -
drivers/usb/musb-new/musb_io.h | 28 +-
drivers/usb/musb-new/musb_regs.h | 191 -
drivers/usb/musb/Makefile | 1 -
drivers/usb/musb/blackfin_usb.c | 172 -
drivers/usb/musb/blackfin_usb.h | 99 -
drivers/usb/musb/musb_core.h | 27 -
drivers/usb/musb/musb_hcd.c | 5 -
examples/standalone/stubs.c | 13 -
include/common.h | 3 -
include/configs/bct-brettl2.h | 137 -
include/configs/bf506f-ezkit.h | 91 -
include/configs/bf518f-ezbrd.h | 146 -
include/configs/bf525-ucr2.h | 90 -
include/configs/bf526-ezbrd.h | 147 -
include/configs/bf527-ad7160-eval.h | 131 -
include/configs/bf527-ezkit.h | 169 -
include/configs/bf527-sdp.h | 112 -
include/configs/bf533-ezkit.h | 111 -
include/configs/bf533-stamp.h | 196 -
include/configs/bf537-minotaur.h | 158 -
include/configs/bf537-pnav.h | 156 -
include/configs/bf537-srv1.h | 158 -
include/configs/bf537-stamp.h | 264 --
include/configs/bf538f-ezkit.h | 133 -
include/configs/bf548-ezkit.h | 190 -
include/configs/bf561-acvilon.h | 144 -
include/configs/bf561-ezkit.h | 108 -
include/configs/bf609-ezkit.h | 161 -
include/configs/bfin_adi_common.h | 282 --
include/configs/blackstamp.h | 219 --
include/configs/blackvme.h | 223 --
include/configs/br4.h | 136 -
include/configs/cm-bf527.h | 126 -
include/configs/cm-bf533.h | 97 -
include/configs/cm-bf537e.h | 141 -
include/configs/cm-bf537u.h | 139 -
include/configs/cm-bf548.h | 132 -
include/configs/cm-bf561.h | 99 -
include/configs/dnp5370.h | 117 -
include/configs/ibf-dsp561.h | 115 -
include/configs/ip04.h | 132 -
include/configs/pr1.h | 136 -
include/configs/tcm-bf518.h | 113 -
include/configs/tcm-bf537.h | 141 -
include/linux/usb/musb.h | 8 -
post/post.c | 2 +-
scripts/config_whitelist.txt | 158 -
507 files changed, 16 insertions(+), 82188 deletions(-)
delete mode 100644 arch/blackfin/Kconfig
delete mode 100644 arch/blackfin/Makefile
delete mode 100644 arch/blackfin/config.mk
delete mode 100644 arch/blackfin/cpu/.gitignore
delete mode 100644 arch/blackfin/cpu/Makefile
delete mode 100644 arch/blackfin/cpu/cache.S
delete mode 100644 arch/blackfin/cpu/cpu.c
delete mode 100644 arch/blackfin/cpu/cpu.h
delete mode 100644 arch/blackfin/cpu/gpio.c
delete mode 100644 arch/blackfin/cpu/init.S
delete mode 100644 arch/blackfin/cpu/init.lds.S
delete mode 100644 arch/blackfin/cpu/initcode.c
delete mode 100644 arch/blackfin/cpu/initcode.h
delete mode 100644 arch/blackfin/cpu/interrupt.S
delete mode 100644 arch/blackfin/cpu/interrupts.c
delete mode 100644 arch/blackfin/cpu/jtag-console.c
delete mode 100644 arch/blackfin/cpu/os_log.c
delete mode 100644 arch/blackfin/cpu/reset.c
delete mode 100644 arch/blackfin/cpu/start.S
delete mode 100644 arch/blackfin/cpu/traps.c
delete mode 100644 arch/blackfin/cpu/u-boot.lds
delete mode 100644 arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
delete mode 100644 arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
delete mode 100644 arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
delete mode 100644 arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
delete mode 100644 arch/blackfin/include/asm/bitops.h
delete mode 100644 arch/blackfin/include/asm/blackfin.h
delete mode 100644 arch/blackfin/include/asm/blackfin_cdef.h
delete mode 100644 arch/blackfin/include/asm/blackfin_def.h
delete mode 100644 arch/blackfin/include/asm/blackfin_local.h
delete mode 100644 arch/blackfin/include/asm/byteorder.h
delete mode 100644 arch/blackfin/include/asm/cache.h
delete mode 100644 arch/blackfin/include/asm/clock.h
delete mode 100644 arch/blackfin/include/asm/config-pre.h
delete mode 100644 arch/blackfin/include/asm/config.h
delete mode 100644 arch/blackfin/include/asm/cplb.h
delete mode 100644 arch/blackfin/include/asm/deferred.h
delete mode 100644 arch/blackfin/include/asm/delay.h
delete mode 100644 arch/blackfin/include/asm/dma.h
delete mode 100644 arch/blackfin/include/asm/entry.h
delete mode 100644 arch/blackfin/include/asm/global_data.h
delete mode 100644 arch/blackfin/include/asm/gpio.h
delete mode 100644 arch/blackfin/include/asm/io.h
delete mode 100644 arch/blackfin/include/asm/linkage.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/BF504_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/BF506_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf506/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF512_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF514_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF516_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/BF518_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf518/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF522_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF523_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF524_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF525_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF526_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/BF527_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/mem_map.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf527/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF531_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF532_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/BF533_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf533/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF534_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF536_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/BF537_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf537/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/BF538_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/BF538_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/BF539_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/BF539_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf538/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF542_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF544_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF547_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF548_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/BF549_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/mem_map.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf548/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/BF561_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf561/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_def.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/anomaly.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/def_local.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/gpio.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/portmux.h
delete mode 100644 arch/blackfin/include/asm/mach-bf609/ports.h
delete mode 100644 arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
delete mode 100644 arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/bootrom.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/cgu.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/core.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/dde.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/dma.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ebiu.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/emac.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/eppi.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/mpu.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/otp.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/pata.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/pll.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-a.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-b.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-c.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-d.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-e.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-f.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-g.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-h.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-i.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ports-j.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/ppi.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/rtc.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/sdh.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/spi.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/spi6xx.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/timer.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/trace.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/twi.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/uart.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/uart4.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/usb.h
delete mode 100644 arch/blackfin/include/asm/mach-common/bits/watchdog.h
delete mode 100644 arch/blackfin/include/asm/mem_map.h
delete mode 100644 arch/blackfin/include/asm/portmux.h
delete mode 100644 arch/blackfin/include/asm/posix_types.h
delete mode 100644 arch/blackfin/include/asm/processor.h
delete mode 100644 arch/blackfin/include/asm/ptrace.h
delete mode 100644 arch/blackfin/include/asm/sdh.h
delete mode 100644 arch/blackfin/include/asm/sections.h
delete mode 100644 arch/blackfin/include/asm/serial.h
delete mode 100644 arch/blackfin/include/asm/serial1.h
delete mode 100644 arch/blackfin/include/asm/serial4.h
delete mode 100644 arch/blackfin/include/asm/shared_resources.h
delete mode 100644 arch/blackfin/include/asm/signal.h
delete mode 100644 arch/blackfin/include/asm/soft_switch.h
delete mode 100644 arch/blackfin/include/asm/string.h
delete mode 100644 arch/blackfin/include/asm/system.h
delete mode 100644 arch/blackfin/include/asm/traps.h
delete mode 100644 arch/blackfin/include/asm/twi.h
delete mode 100644 arch/blackfin/include/asm/types.h
delete mode 100644 arch/blackfin/include/asm/u-boot.h
delete mode 100644 arch/blackfin/include/asm/unaligned.h
delete mode 100644 arch/blackfin/lib/.gitignore
delete mode 100644 arch/blackfin/lib/Makefile
delete mode 100644 arch/blackfin/lib/__kgdb.S
delete mode 100644 arch/blackfin/lib/boot.c
delete mode 100644 arch/blackfin/lib/cache.c
delete mode 100644 arch/blackfin/lib/clocks.c
delete mode 100644 arch/blackfin/lib/cmd_cache_dump.c
delete mode 100644 arch/blackfin/lib/ins.S
delete mode 100644 arch/blackfin/lib/kgdb.c
delete mode 100644 arch/blackfin/lib/kgdb.h
delete mode 100644 arch/blackfin/lib/memcmp.S
delete mode 100644 arch/blackfin/lib/memcpy.S
delete mode 100644 arch/blackfin/lib/memmove.S
delete mode 100644 arch/blackfin/lib/memset.S
delete mode 100644 arch/blackfin/lib/muldi3.c
delete mode 100644 arch/blackfin/lib/outs.S
delete mode 100644 arch/blackfin/lib/post.c
delete mode 100644 arch/blackfin/lib/sections.c
delete mode 100644 arch/blackfin/lib/string.c
delete mode 100644 board/bct-brettl2/Kconfig
delete mode 100644 board/bct-brettl2/MAINTAINERS
delete mode 100644 board/bct-brettl2/Makefile
delete mode 100644 board/bct-brettl2/bct-brettl2.c
delete mode 100644 board/bct-brettl2/cled.c
delete mode 100644 board/bct-brettl2/gpio_cfi_flash.c
delete mode 100644 board/bct-brettl2/smsc9303.c
delete mode 100644 board/bct-brettl2/smsc9303.h
delete mode 100644 board/bf506f-ezkit/Kconfig
delete mode 100644 board/bf506f-ezkit/MAINTAINERS
delete mode 100644 board/bf506f-ezkit/Makefile
delete mode 100644 board/bf506f-ezkit/bf506f-ezkit.c
delete mode 100644 board/bf518f-ezbrd/Kconfig
delete mode 100644 board/bf518f-ezbrd/MAINTAINERS
delete mode 100644 board/bf518f-ezbrd/Makefile
delete mode 100644 board/bf518f-ezbrd/bf518f-ezbrd.c
delete mode 100644 board/bf525-ucr2/Kconfig
delete mode 100644 board/bf525-ucr2/MAINTAINERS
delete mode 100644 board/bf525-ucr2/Makefile
delete mode 100644 board/bf525-ucr2/bf525-ucr2.c
delete mode 100644 board/bf526-ezbrd/Kconfig
delete mode 100644 board/bf526-ezbrd/MAINTAINERS
delete mode 100644 board/bf526-ezbrd/Makefile
delete mode 100644 board/bf526-ezbrd/bf526-ezbrd.c
delete mode 100644 board/bf527-ad7160-eval/Kconfig
delete mode 100644 board/bf527-ad7160-eval/MAINTAINERS
delete mode 100644 board/bf527-ad7160-eval/Makefile
delete mode 100644 board/bf527-ad7160-eval/bf527-ad7160-eval.c
delete mode 100644 board/bf527-ezkit/Kconfig
delete mode 100644 board/bf527-ezkit/MAINTAINERS
delete mode 100644 board/bf527-ezkit/Makefile
delete mode 100644 board/bf527-ezkit/bf527-ezkit.c
delete mode 100644 board/bf527-ezkit/video.c
delete mode 100644 board/bf527-sdp/Kconfig
delete mode 100644 board/bf527-sdp/MAINTAINERS
delete mode 100644 board/bf527-sdp/Makefile
delete mode 100644 board/bf527-sdp/bf527-sdp.c
delete mode 100644 board/bf527-sdp/config.mk
delete mode 100644 board/bf533-ezkit/Kconfig
delete mode 100644 board/bf533-ezkit/MAINTAINERS
delete mode 100644 board/bf533-ezkit/Makefile
delete mode 100644 board/bf533-ezkit/bf533-ezkit.c
delete mode 100644 board/bf533-ezkit/config.mk
delete mode 100644 board/bf533-ezkit/flash-defines.h
delete mode 100644 board/bf533-ezkit/flash.c
delete mode 100644 board/bf533-ezkit/psd4256.h
delete mode 100644 board/bf533-stamp/Kconfig
delete mode 100644 board/bf533-stamp/MAINTAINERS
delete mode 100644 board/bf533-stamp/Makefile
delete mode 100644 board/bf533-stamp/bf533-stamp.c
delete mode 100644 board/bf533-stamp/config.mk
delete mode 100644 board/bf533-stamp/ide-cf.c
delete mode 100644 board/bf533-stamp/video.c
delete mode 100644 board/bf533-stamp/video.h
delete mode 100644 board/bf537-minotaur/Kconfig
delete mode 100644 board/bf537-minotaur/MAINTAINERS
delete mode 100644 board/bf537-minotaur/Makefile
delete mode 100644 board/bf537-minotaur/bf537-minotaur.c
delete mode 100644 board/bf537-minotaur/config.mk
delete mode 100644 board/bf537-pnav/Kconfig
delete mode 100644 board/bf537-pnav/MAINTAINERS
delete mode 100644 board/bf537-pnav/Makefile
delete mode 100644 board/bf537-pnav/bf537-pnav.c
delete mode 100644 board/bf537-srv1/Kconfig
delete mode 100644 board/bf537-srv1/MAINTAINERS
delete mode 100644 board/bf537-srv1/Makefile
delete mode 100644 board/bf537-srv1/bf537-srv1.c
delete mode 100644 board/bf537-srv1/config.mk
delete mode 100644 board/bf537-stamp/Kconfig
delete mode 100644 board/bf537-stamp/MAINTAINERS
delete mode 100644 board/bf537-stamp/Makefile
delete mode 100644 board/bf537-stamp/bf537-stamp.c
delete mode 100644 board/bf537-stamp/config.mk
delete mode 100644 board/bf537-stamp/ide-cf.c
delete mode 100644 board/bf537-stamp/post-memory.c
delete mode 100644 board/bf538f-ezkit/Kconfig
delete mode 100644 board/bf538f-ezkit/MAINTAINERS
delete mode 100644 board/bf538f-ezkit/Makefile
delete mode 100644 board/bf538f-ezkit/bf538f-ezkit.c
delete mode 100644 board/bf538f-ezkit/config.mk
delete mode 100644 board/bf548-ezkit/Kconfig
delete mode 100644 board/bf548-ezkit/MAINTAINERS
delete mode 100644 board/bf548-ezkit/Makefile
delete mode 100644 board/bf548-ezkit/bf548-ezkit.c
delete mode 100644 board/bf548-ezkit/config.mk
delete mode 100644 board/bf548-ezkit/video.c
delete mode 100644 board/bf561-acvilon/Kconfig
delete mode 100644 board/bf561-acvilon/MAINTAINERS
delete mode 100644 board/bf561-acvilon/Makefile
delete mode 100644 board/bf561-acvilon/bf561-acvilon.c
delete mode 100644 board/bf561-acvilon/config.mk
delete mode 100644 board/bf561-ezkit/Kconfig
delete mode 100644 board/bf561-ezkit/MAINTAINERS
delete mode 100644 board/bf561-ezkit/Makefile
delete mode 100644 board/bf561-ezkit/bf561-ezkit.c
delete mode 100644 board/bf561-ezkit/config.mk
delete mode 100644 board/bf609-ezkit/Kconfig
delete mode 100644 board/bf609-ezkit/MAINTAINERS
delete mode 100644 board/bf609-ezkit/Makefile
delete mode 100644 board/bf609-ezkit/bf609-ezkit.c
delete mode 100644 board/bf609-ezkit/soft_switch.c
delete mode 100644 board/bf609-ezkit/soft_switch.h
delete mode 100644 board/blackstamp/Kconfig
delete mode 100644 board/blackstamp/MAINTAINERS
delete mode 100644 board/blackstamp/Makefile
delete mode 100644 board/blackstamp/blackstamp.c
delete mode 100644 board/blackvme/Kconfig
delete mode 100644 board/blackvme/MAINTAINERS
delete mode 100644 board/blackvme/Makefile
delete mode 100644 board/blackvme/blackvme.c
delete mode 100644 board/br4/Kconfig
delete mode 100644 board/br4/MAINTAINERS
delete mode 100644 board/br4/Makefile
delete mode 100644 board/br4/br4.c
delete mode 100644 board/cm-bf527/Kconfig
delete mode 100644 board/cm-bf527/MAINTAINERS
delete mode 100644 board/cm-bf527/Makefile
delete mode 100644 board/cm-bf527/cm-bf527.c
delete mode 100644 board/cm-bf527/gpio_cfi_flash.c
delete mode 100644 board/cm-bf533/Kconfig
delete mode 100644 board/cm-bf533/MAINTAINERS
delete mode 100644 board/cm-bf533/Makefile
delete mode 100644 board/cm-bf533/cm-bf533.c
delete mode 100644 board/cm-bf533/config.mk
delete mode 100644 board/cm-bf537e/Kconfig
delete mode 100644 board/cm-bf537e/MAINTAINERS
delete mode 100644 board/cm-bf537e/Makefile
delete mode 100644 board/cm-bf537e/cm-bf537e.c
delete mode 100644 board/cm-bf537e/config.mk
delete mode 100644 board/cm-bf537e/gpio_cfi_flash.c
delete mode 100644 board/cm-bf537e/gpio_cfi_flash.h
delete mode 100644 board/cm-bf537u/Kconfig
delete mode 100644 board/cm-bf537u/MAINTAINERS
delete mode 100644 board/cm-bf537u/Makefile
delete mode 100644 board/cm-bf537u/cm-bf537u.c
delete mode 100644 board/cm-bf537u/config.mk
delete mode 100644 board/cm-bf537u/gpio_cfi_flash.c
delete mode 100644 board/cm-bf548/Kconfig
delete mode 100644 board/cm-bf548/MAINTAINERS
delete mode 100644 board/cm-bf548/Makefile
delete mode 100644 board/cm-bf548/cm-bf548.c
delete mode 100644 board/cm-bf548/config.mk
delete mode 100644 board/cm-bf548/video.c
delete mode 100644 board/cm-bf561/Kconfig
delete mode 100644 board/cm-bf561/MAINTAINERS
delete mode 100644 board/cm-bf561/Makefile
delete mode 100644 board/cm-bf561/cm-bf561.c
delete mode 100644 board/cm-bf561/config.mk
delete mode 100644 board/dnp5370/Kconfig
delete mode 100644 board/dnp5370/MAINTAINERS
delete mode 100644 board/dnp5370/Makefile
delete mode 100644 board/dnp5370/README
delete mode 100644 board/dnp5370/dnp5370.c
delete mode 100644 board/ip04/Kconfig
delete mode 100644 board/ip04/MAINTAINERS
delete mode 100644 board/ip04/Makefile
delete mode 100644 board/ip04/config.mk
delete mode 100644 board/ip04/ip04.c
delete mode 100644 board/pr1/Kconfig
delete mode 100644 board/pr1/MAINTAINERS
delete mode 100644 board/pr1/Makefile
delete mode 100644 board/pr1/pr1.c
delete mode 100644 board/tcm-bf518/Kconfig
delete mode 100644 board/tcm-bf518/MAINTAINERS
delete mode 100644 board/tcm-bf518/Makefile
delete mode 100644 board/tcm-bf518/tcm-bf518.c
delete mode 100644 board/tcm-bf537/Kconfig
delete mode 100644 board/tcm-bf537/MAINTAINERS
delete mode 100644 board/tcm-bf537/Makefile
delete mode 100644 board/tcm-bf537/config.mk
delete mode 100644 board/tcm-bf537/gpio_cfi_flash.c
delete mode 100644 board/tcm-bf537/tcm-bf537.c
delete mode 100644 configs/bct-brettl2_defconfig
delete mode 100644 configs/bf506f-ezkit_defconfig
delete mode 100644 configs/bf518f-ezbrd_defconfig
delete mode 100644 configs/bf525-ucr2_defconfig
delete mode 100644 configs/bf526-ezbrd_defconfig
delete mode 100644 configs/bf527-ad7160-eval_defconfig
delete mode 100644 configs/bf527-ezkit-v2_defconfig
delete mode 100644 configs/bf527-ezkit_defconfig
delete mode 100644 configs/bf527-sdp_defconfig
delete mode 100644 configs/bf533-ezkit_defconfig
delete mode 100644 configs/bf533-stamp_defconfig
delete mode 100644 configs/bf537-minotaur_defconfig
delete mode 100644 configs/bf537-pnav_defconfig
delete mode 100644 configs/bf537-srv1_defconfig
delete mode 100644 configs/bf537-stamp_defconfig
delete mode 100644 configs/bf538f-ezkit_defconfig
delete mode 100644 configs/bf548-ezkit_defconfig
delete mode 100644 configs/bf561-acvilon_defconfig
delete mode 100644 configs/bf561-ezkit_defconfig
delete mode 100644 configs/bf609-ezkit_defconfig
delete mode 100644 configs/blackstamp_defconfig
delete mode 100644 configs/blackvme_defconfig
delete mode 100644 configs/br4_defconfig
delete mode 100644 configs/cm-bf527_defconfig
delete mode 100644 configs/cm-bf533_defconfig
delete mode 100644 configs/cm-bf537e_defconfig
delete mode 100644 configs/cm-bf537u_defconfig
delete mode 100644 configs/cm-bf548_defconfig
delete mode 100644 configs/cm-bf561_defconfig
delete mode 100644 configs/dnp5370_defconfig
delete mode 100644 configs/ibf-dsp561_defconfig
delete mode 100644 configs/ip04_defconfig
delete mode 100644 configs/pr1_defconfig
delete mode 100644 configs/tcm-bf518_defconfig
delete mode 100644 configs/tcm-bf537_defconfig
delete mode 100644 drivers/bootcount/bootcount_blackfin.c
delete mode 100644 drivers/i2c/pca9564_i2c.c
delete mode 100644 drivers/serial/serial_bfin.c
delete mode 100644 drivers/spi/bfin_spi.c
delete mode 100644 drivers/spi/bfin_spi6xx.c
delete mode 100644 drivers/usb/musb/blackfin_usb.c
delete mode 100644 drivers/usb/musb/blackfin_usb.h
delete mode 100644 include/configs/bct-brettl2.h
delete mode 100644 include/configs/bf506f-ezkit.h
delete mode 100644 include/configs/bf518f-ezbrd.h
delete mode 100644 include/configs/bf525-ucr2.h
delete mode 100644 include/configs/bf526-ezbrd.h
delete mode 100644 include/configs/bf527-ad7160-eval.h
delete mode 100644 include/configs/bf527-ezkit.h
delete mode 100644 include/configs/bf527-sdp.h
delete mode 100644 include/configs/bf533-ezkit.h
delete mode 100644 include/configs/bf533-stamp.h
delete mode 100644 include/configs/bf537-minotaur.h
delete mode 100644 include/configs/bf537-pnav.h
delete mode 100644 include/configs/bf537-srv1.h
delete mode 100644 include/configs/bf537-stamp.h
delete mode 100644 include/configs/bf538f-ezkit.h
delete mode 100644 include/configs/bf548-ezkit.h
delete mode 100644 include/configs/bf561-acvilon.h
delete mode 100644 include/configs/bf561-ezkit.h
delete mode 100644 include/configs/bf609-ezkit.h
delete mode 100644 include/configs/bfin_adi_common.h
delete mode 100644 include/configs/blackstamp.h
delete mode 100644 include/configs/blackvme.h
delete mode 100644 include/configs/br4.h
delete mode 100644 include/configs/cm-bf527.h
delete mode 100644 include/configs/cm-bf533.h
delete mode 100644 include/configs/cm-bf537e.h
delete mode 100644 include/configs/cm-bf537u.h
delete mode 100644 include/configs/cm-bf548.h
delete mode 100644 include/configs/cm-bf561.h
delete mode 100644 include/configs/dnp5370.h
delete mode 100644 include/configs/ibf-dsp561.h
delete mode 100644 include/configs/ip04.h
delete mode 100644 include/configs/pr1.h
delete mode 100644 include/configs/tcm-bf518.h
delete mode 100644 include/configs/tcm-bf537.h
diff --git a/.travis.yml b/.travis.yml
index 8333fae9b333..8fd612ba5259 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -40,7 +40,7 @@ install:
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
# prepare buildman environment
- echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
- cat ~/.buildman
- virtualenv /tmp/venv
- . /tmp/venv/bin/activate
@@ -60,7 +60,6 @@ env:
before_script:
# install toolchains based on TOOLCHAIN} variable
- if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
- - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
- if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
- if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
- if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
diff --git a/MAINTAINERS b/MAINTAINERS
index eaa2c3bbb860..c1aa594449fa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -216,12 +216,6 @@ S: Maintained
T: git git://git.denx.de/u-boot-avr32.git
F: arch/avr32/
-BLACKFIN
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-T: git git://git.denx.de/u-boot-blackfin.git
-F: arch/blackfin/
-
BUILDMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
diff --git a/README b/README
index 3174b18d9a89..486a71ebef6e 100644
--- a/README
+++ b/README
@@ -137,7 +137,6 @@ Directory Hierarchy:
/arc Files generic to ARC architecture
/arm Files generic to ARM architecture
/avr32 Files generic to AVR32 architecture
- /blackfin Files generic to Analog Devices Blackfin architecture
/m68k Files generic to m68k architecture
/microblaze Files generic to microblaze architecture
/mips Files generic to MIPS architecture
@@ -2877,8 +2876,6 @@ The following options need to be configured:
CONFIG_AT91SAM9XE
enable special bootcounter support on at91sam9xe based boards.
- CONFIG_BLACKFIN
- enable special bootcounter support on blackfin based boards.
CONFIG_SOC_DA8XX
enable special bootcounter support on da850 based boards.
CONFIG_BOOTCOUNT_RAM
@@ -5923,11 +5920,6 @@ For PowerPC, the following registers have specific use:
average for all boards 752 bytes for the whole U-Boot image,
624 text + 127 data).
-On Blackfin, the normal C ABI (except for P3) is followed as documented here:
- http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-
- ==> U-Boot will use P3 to hold a pointer to the global data
-
On ARM, the following registers are used:
R0: function argument word/integer result
diff --git a/arch/Kconfig b/arch/Kconfig
index 76c690f6675e..73e419223b5e 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -24,10 +24,6 @@ config AVR32
bool "AVR32 architecture"
select CREATE_ARCH_SYMLINK
-config BLACKFIN
- bool "Blackfin architecture"
- select ARCH_MISC_INIT
-
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
@@ -159,7 +155,6 @@ config SYS_CONFIG_NAME
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/avr32/Kconfig"
-source "arch/blackfin/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index 0a2fb4d4aa68..000000000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,150 +0,0 @@
-menu "Blackfin architecture"
- depends on BLACKFIN
-
-config SYS_ARCH
- default "blackfin"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_BCT_BRETTL2
- bool "Support bct-brettl2"
-
-config TARGET_BF506F_EZKIT
- bool "Support bf506f-ezkit"
-
-config TARGET_BF518F_EZBRD
- bool "Support bf518f-ezbrd"
-
-config TARGET_BF525_UCR2
- bool "Support bf525-ucr2"
-
-config TARGET_BF526_EZBRD
- bool "Support bf526-ezbrd"
-
-config TARGET_BF527_AD7160_EVAL
- bool "Support bf527-ad7160-eval"
-
-config TARGET_BF527_EZKIT
- bool "Support bf527-ezkit"
-
-config TARGET_BF527_SDP
- bool "Support bf527-sdp"
-
-config TARGET_BF533_EZKIT
- bool "Support bf533-ezkit"
-
-config TARGET_BF533_STAMP
- bool "Support bf533-stamp"
-
-config TARGET_BF537_MINOTAUR
- bool "Support bf537-minotaur"
-
-config TARGET_BF537_PNAV
- bool "Support bf537-pnav"
-
-config TARGET_BF537_SRV1
- bool "Support bf537-srv1"
-
-config TARGET_BF537_STAMP
- bool "Support bf537-stamp"
-
-config TARGET_BF538F_EZKIT
- bool "Support bf538f-ezkit"
-
-config TARGET_BF548_EZKIT
- bool "Support bf548-ezkit"
-
-config TARGET_BF561_ACVILON
- bool "Support bf561-acvilon"
-
-config TARGET_BF561_EZKIT
- bool "Support bf561-ezkit"
-
-config TARGET_BF609_EZKIT
- bool "Support bf609-ezkit"
-
-config TARGET_BLACKSTAMP
- bool "Support blackstamp"
-
-config TARGET_BLACKVME
- bool "Support blackvme"
-
-config TARGET_BR4
- bool "Support br4"
-
-config TARGET_CM_BF527
- bool "Support cm-bf527"
-
-config TARGET_CM_BF533
- bool "Support cm-bf533"
-
-config TARGET_CM_BF537E
- bool "Support cm-bf537e"
-
-config TARGET_CM_BF537U
- bool "Support cm-bf537u"
-
-config TARGET_CM_BF548
- bool "Support cm-bf548"
-
-config TARGET_CM_BF561
- bool "Support cm-bf561"
-
-config TARGET_DNP5370
- bool "Support dnp5370"
-
-config TARGET_IBF_DSP561
- bool "Support ibf-dsp561"
-
-config TARGET_IP04
- bool "Support ip04"
-
-config TARGET_PR1
- bool "Support pr1"
-
-config TARGET_TCM_BF518
- bool "Support tcm-bf518"
-
-config TARGET_TCM_BF537
- bool "Support tcm-bf537"
-
-endchoice
-
-source "board/bct-brettl2/Kconfig"
-source "board/bf506f-ezkit/Kconfig"
-source "board/bf518f-ezbrd/Kconfig"
-source "board/bf525-ucr2/Kconfig"
-source "board/bf526-ezbrd/Kconfig"
-source "board/bf527-ad7160-eval/Kconfig"
-source "board/bf527-ezkit/Kconfig"
-source "board/bf527-sdp/Kconfig"
-source "board/bf533-ezkit/Kconfig"
-source "board/bf533-stamp/Kconfig"
-source "board/bf537-minotaur/Kconfig"
-source "board/bf537-pnav/Kconfig"
-source "board/bf537-srv1/Kconfig"
-source "board/bf537-stamp/Kconfig"
-source "board/bf538f-ezkit/Kconfig"
-source "board/bf548-ezkit/Kconfig"
-source "board/bf561-acvilon/Kconfig"
-source "board/bf561-ezkit/Kconfig"
-source "board/bf609-ezkit/Kconfig"
-source "board/blackstamp/Kconfig"
-source "board/blackvme/Kconfig"
-source "board/br4/Kconfig"
-source "board/cm-bf527/Kconfig"
-source "board/cm-bf533/Kconfig"
-source "board/cm-bf537e/Kconfig"
-source "board/cm-bf537u/Kconfig"
-source "board/cm-bf548/Kconfig"
-source "board/cm-bf561/Kconfig"
-source "board/dnp5370/Kconfig"
-source "board/ibf-dsp561/Kconfig"
-source "board/ip04/Kconfig"
-source "board/pr1/Kconfig"
-source "board/tcm-bf518/Kconfig"
-source "board/tcm-bf537/Kconfig"
-
-endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 787475e13095..000000000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-head-y := arch/blackfin/cpu/start.o
-
-libs-y += arch/blackfin/cpu/
-libs-y += arch/blackfin/lib/
diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
deleted file mode 100644
index 7b17b757438f..000000000000
--- a/arch/blackfin/config.mk
+++ /dev/null
@@ -1,68 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
-
-ifeq ($(CONFIG_BFIN_CPU),)
-CONFIG_BFIN_CPU := \
- $(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \
- $(srctree)/include/configs/$(BOARD).h)
-else
-CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
-endif
-CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
-
-PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
-
-LDFLAGS_FINAL += --gc-sections
-LDFLAGS += -m elf32bfin
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-
-PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
-
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL-y += u-boot.ldr
-endif
-ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
-CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o
-HOSTCFLAGS_NOPED_ADSP := \
- $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
- | awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
-HOSTCFLAGS_NOPED += $(HOSTCFLAGS_NOPED_ADSP)
-else
-CREATE_LDR_ENV =
-endif
-
-SYM_PREFIX = _
-export SYM_PREFIX
-
-LDR_FLAGS-y :=
-LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
-
-LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
-LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(CPUDIR)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
-LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
- --punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):env-ldr.o
-endif
-ifneq (,$(findstring s,$(MAKEFLAGS)))
-LDR_FLAGS += --quiet
-endif
-
-LDR_FLAGS += $(LDR_FLAGS-y)
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
-
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-$(error do not set CONFIG_SYS_TEXT_BASE for Blackfin boards)
-endif
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
deleted file mode 100644
index 3df1fa21c958..000000000000
--- a/arch/blackfin/cpu/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-init.lds
-init.elf
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
deleted file mode 100644
index 7ba5f1b84811..000000000000
--- a/arch/blackfin/cpu/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y := init.elf
-extra-y += initcode.o
-extra-y += start.o
-obj-y := interrupt.o cache.o
-obj-y += cpu.o
-obj-y += gpio.o
-obj-y += interrupts.o
-obj-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
-obj-y += os_log.o
-obj-y += reset.o
-obj-y += traps.o
-
-extra-y += check_initcode
-clean-files := init.lds
-
-# make sure our initcode (which goes into LDR) does not
-# have relocs or external references
-CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections
-READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
-$(obj)/check_initcode: $(obj)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
- @if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
- echo "$< contains external references!" 1>&2 ; \
- exit 1 ; \
- fi
-endif
-
-CPPFLAGS_init.lds := -ansi
-
-quiet_cmd_link_init = LD $@
- cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@
-$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o
- $(call if_changed,link_init)
-targets += init.lds init.o
diff --git a/arch/blackfin/cpu/cache.S b/arch/blackfin/cpu/cache.S
deleted file mode 100644
index 5ca9e91d3f12..000000000000
--- a/arch/blackfin/cpu/cache.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2003-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.text
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them. Only the actual flush instruction differs. We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req optflushins optnopins label
-
- R2 = -L1_CACHE_BYTES;
-
- /* start = (start & -L1_CACHE_BYTES) */
- R0 = R0 & R2;
-
- /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
- R1 += -1;
- R1 = R1 & R2;
- R1 += L1_CACHE_BYTES;
-
- /* count = (end - start) >> L1_CACHE_SHIFT */
- R2 = R1 - R0;
- R2 >>= L1_CACHE_SHIFT;
- P1 = R2;
-
-.ifnb \label
-\label :
-.endif
- P0 = R0;
- LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifnb \optflushins
- \optflushins [P0];
-.endif
-#if ANOMALY_05000443
-.ifb \optnopins
-2:
-.endif
- \flushins [P0++];
-.ifnb \optnopins
-2: \optnopins;
-.endif
-#else
-2: \flushins [P0++];
-#endif
-
- RTS;
-.endm
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-ENTRY(_blackfin_icache_flush_range)
- do_flush IFLUSH, , nop
-ENDPROC(_blackfin_icache_flush_range)
-
-/* Flush all cache lines assocoiated with this area of memory. */
-ENTRY(_blackfin_icache_dcache_flush_range)
- do_flush FLUSH, IFLUSH
-ENDPROC(_blackfin_icache_dcache_flush_range)
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back. Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate. Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_flush_invalidate_range)
- do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_flush_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
- do_flush FLUSH, , , .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
deleted file mode 100644
index 529322a1743d..000000000000
--- a/arch/blackfin/cpu/cpu.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * U-Boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <version.h>
-#include <i2c.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/trace.h>
-
-#include "cpu.h"
-#include "initcode.h"
-#include "exports.h"
-
-ulong bfin_poweron_retx;
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
-void bfin_core1_start(void)
-{
-#ifdef BF561_FAMILY
- /* Enable core 1 */
- bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
-#else
- /* Enable core 1 */
- bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
- bfin_write32(RCU0_CRCTL, 0);
-
- bfin_write32(RCU0_CRCTL, 0x2);
-
- /* Check if core 1 starts */
- while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
- continue;
-
- bfin_write32(RCU0_CRCTL, 0);
-
- /* flag to notify cces core 1 application */
- bfin_write32(SDU0_MSG_SET, (1 << 19));
-#endif
-}
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- serial_puts("Early: ");
- serial_puts(s);
-#endif
-}
-
-static int global_board_data_init(void)
-{
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR 0
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR 0
-#endif
-
- bd_t *bd;
-
- if (CONFIG_SYS_GBL_DATA_ADDR) {
- gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
- } else {
- static gd_t _bfin_gd;
- gd = &_bfin_gd;
- }
- if (CONFIG_SYS_BD_INFO_ADDR) {
- bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
- memset(bd, 0, GENERATED_BD_INFO_SIZE);
- } else {
- static bd_t _bfin_bd;
- bd = &_bfin_bd;
- }
-
- gd->bd = bd;
-
- bd->bi_r_version = version_string;
- bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
- bd->bi_board_name = CONFIG_SYS_BOARD;
- bd->bi_vco = get_vco();
- bd->bi_cclk = get_cclk();
- bd->bi_sclk = get_sclk();
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
-
- gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
-
- return 0;
-}
-
-static void display_global_data(void)
-{
- bd_t *bd;
-
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
- return;
-#endif
-
- bd = gd->bd;
- printf(" gd: %p\n", gd);
- printf(" |-flags: %lx\n", gd->flags);
- printf(" |-board_type: %lx\n", gd->arch.board_type);
- printf(" |-baudrate: %u\n", gd->baudrate);
- printf(" |-have_console: %lx\n", gd->have_console);
- printf(" |-ram_size: %lx\n", gd->ram_size);
- printf(" |-env_addr: %lx\n", gd->env_addr);
- printf(" |-env_valid: %lx\n", gd->env_valid);
- printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
- printf(" \\-bd: %p\n", gd->bd);
- printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
- printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
- printf(" |-bi_memsize: %lx\n", bd->bi_memsize);
- printf(" |-bi_flashstart: %lx\n", bd->bi_flashstart);
- printf(" |-bi_flashsize: %lx\n", bd->bi_flashsize);
- printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-}
-
-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
-#if defined(__ADSPBF60x__)
-#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
-#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
-#else
-#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
-#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
-#endif
-void init_cplbtables(void)
-{
- uint32_t *ICPLB_ADDR, *ICPLB_DATA;
- uint32_t *DCPLB_ADDR, *DCPLB_DATA;
- uint32_t extern_memory;
- size_t i;
-
- void icplb_add(uint32_t addr, uint32_t data)
- {
- bfin_write32(ICPLB_ADDR + i, addr);
- bfin_write32(ICPLB_DATA + i, data);
- }
- void dcplb_add(uint32_t addr, uint32_t data)
- {
- bfin_write32(DCPLB_ADDR + i, addr);
- bfin_write32(DCPLB_DATA + i, data);
- }
-
- /* populate a few common entries ... we'll let
- * the memory map and cplb exception handler do
- * the rest of the work.
- */
- i = 0;
- ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
- ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
- DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
- DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
-
- icplb_add(0xFFA00000, L1_IMEMORY);
- dcplb_add(0xFF800000, L1_DMEMORY);
- ++i;
-#if defined(__ADSPBF60x__)
- icplb_add(0x0, 0x0);
- dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
- CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
- ++i;
-#endif
-
- if (CONFIG_MEM_SIZE) {
- uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
- uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN - 1;
- mbase &= CPLB_PAGE_MASK;
- mend &= CPLB_PAGE_MASK;
-
- icplb_add(mbase, SDRAM_IKERNEL);
- dcplb_add(mbase, SDRAM_DKERNEL);
- ++i;
-
- /*
- * If the monitor crosses a 4 meg boundary, we'll need
- * to lock two entries for it. We assume it doesn't
- * cross two 4 meg boundaries ...
- */
- if (mbase != mend) {
- icplb_add(mend, SDRAM_IKERNEL);
- dcplb_add(mend, SDRAM_DKERNEL);
- ++i;
- }
- }
-
-#ifndef __ADSPBF60x__
- icplb_add(0x20000000, SDRAM_INON_CHBL);
- dcplb_add(0x20000000, SDRAM_EBIU);
- ++i;
-#endif
-
- /* Add entries for the rest of external RAM up to the bootrom */
- extern_memory = 0;
-
-#ifdef CONFIG_DEBUG_NULL_PTR
- icplb_add(extern_memory,
- (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
- dcplb_add(extern_memory,
- (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
- ++i;
- icplb_add(extern_memory, SDRAM_IKERNEL);
- dcplb_add(extern_memory, SDRAM_DKERNEL);
- extern_memory += CPLB_PAGE_SIZE;
- ++i;
-#endif
-
- while (i < 16 && extern_memory <
- (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
- icplb_add(extern_memory, SDRAM_IGENERIC);
- dcplb_add(extern_memory, SDRAM_DGENERIC);
- extern_memory += CPLB_EX_PAGE_SIZE;
- ++i;
- }
- while (i < 16) {
- icplb_add(0, 0);
- dcplb_add(0, 0);
- ++i;
- }
-}
-
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU: ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
- gd->bd->bi_cpu,
- bfin_revid(),
- get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
-
- printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
- printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
-#if defined(__ADSPBF60x__)
- printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
- printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
- printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
-#else
- printf("System: %s MHz\n", strmhz(buf, get_sclk()));
-#endif
-
- return 0;
-}
-
-int exception_init(void)
-{
- bfin_write_EVT3(trap);
- return 0;
-}
-
-int irq_init(void)
-{
-#ifdef SIC_IMASK0
- bfin_write_SIC_IMASK0(0);
- bfin_write_SIC_IMASK1(0);
-# ifdef SIC_IMASK2
- bfin_write_SIC_IMASK2(0);
-# endif
-#elif defined(SICA_IMASK0)
- bfin_write_SICA_IMASK0(0);
- bfin_write_SICA_IMASK1(0);
-#elif defined(SIC_IMASK)
- bfin_write_SIC_IMASK(0);
-#endif
- /* Set up a dummy NMI handler if needed. */
- if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
- bfin_write_EVT2(evt_nmi); /* NMI */
- bfin_write_EVT5(evt_default); /* hardware error */
- bfin_write_EVT6(evt_default); /* core timer */
- bfin_write_EVT7(evt_default);
- bfin_write_EVT8(evt_default);
- bfin_write_EVT9(evt_default);
- bfin_write_EVT10(evt_default);
- bfin_write_EVT11(evt_default);
- bfin_write_EVT12(evt_default);
- bfin_write_EVT13(evt_default);
- bfin_write_EVT14(evt_default);
- bfin_write_EVT15(evt_default);
- bfin_write_ILAT(0);
- CSYNC();
- /* enable hardware error irq */
- irq_flags = 0x3f;
- local_irq_enable();
- return 0;
-}
-
-__attribute__ ((__noreturn__))
-void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
-{
-#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
- /* Build a NOP slide over the LDR jump block. Whee! */
- char nops[0xC];
- serial_early_puts("NOP Slide\n");
- memset(nops, 0x00, sizeof(nops));
- memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
-#endif
-
- if (!loaded_from_ldr) {
- /* Relocate sections into L1 if the LDR didn't do it -- don't
- * check length because the linker script does the size
- * checking at build time.
- */
- serial_early_puts("L1 Relocate\n");
- extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
- memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
- extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
- memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
- }
-
- /*
- * Make sure our async settings are committed. Some bootroms
- * (like the BF537) will reset some registers on us after it
- * has finished loading the LDR. Or if we're booting over
- * JTAG, the initcode never got a chance to run. Or if we
- * aren't booting from parallel flash, the initcode skipped
- * this step completely.
- */
- program_async_controller(NULL);
-
- /* Save RETX so we can pass it while booting Linux */
- bfin_poweron_retx = bootflag;
-
-#ifdef CONFIG_DEBUG_DUMP
- /* Turn on hardware trace buffer */
- bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
-#endif
-
-#ifndef CONFIG_PANIC_HANG
- /* Reset upon a double exception rather than just hanging.
- * Do not do bfin_read on SWRST as that will reset status bits.
- */
-# ifdef SWRST
- bfin_write_SWRST(DOUBLE_FAULT);
-# endif
-#endif
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
- bfin_core1_start();
-#endif
-
- serial_early_puts("Init global data\n");
- global_board_data_init();
-
- board_init_f(0);
-
- /* should not be reached */
- while (1);
-}
-
-int arch_cpu_init(void)
-{
- serial_early_puts("Init CPLB tables\n");
- init_cplbtables();
-
- serial_early_puts("Exceptions setup\n");
- exception_init();
-
-#ifndef CONFIG_ICACHE_OFF
- serial_early_puts("Turn on ICACHE\n");
- icache_enable();
-#endif
-#ifndef CONFIG_DCACHE_OFF
- serial_early_puts("Turn on DCACHE\n");
- dcache_enable();
-#endif
-
-#ifdef DEBUG
- if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
- hang();
-#endif
-
- /* Initialize */
- serial_early_puts("IRQ init\n");
- irq_init();
-
- return 0;
-}
-
-int arch_misc_init(void)
-{
-#if defined(CONFIG_SYS_I2C)
- i2c_reloc_fixup();
-#endif
-
- display_global_data();
-
- if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
- puts("\nLog buffer from operating system:\n");
- bfin_os_log_dump();
- puts("\n");
- }
-
- return 0;
-}
-
-int interrupt_init(void)
-{
- return 0;
-}
diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h
deleted file mode 100644
index a5fe02e53cda..000000000000
--- a/arch/blackfin/cpu/cpu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * U-Boot - cpu.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-void board_reset(void) __attribute__((__weak__));
-void bfin_dump(struct pt_regs *reg);
-void bfin_panic(struct pt_regs *reg);
-void dump(struct pt_regs *regs);
-
-asmlinkage void trap(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_default(void);
-
-#endif
diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c
deleted file mode 100644
index 81b709028fc0..000000000000
--- a/arch/blackfin/cpu/gpio.c
+++ /dev/null
@@ -1,841 +0,0 @@
-/*
- * ADI GPIO1 Abstraction Layer
- * Support BF50x, BF51x, BF52x, BF53x and BF561 only.
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_ADI_GPIO2
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
- AWA_data = SYSCR,
- AWA_data_clear = SYSCR,
- AWA_data_set = SYSCR,
- AWA_toggle = SYSCR,
- AWA_maska = UART_SCR,
- AWA_maska_clear = UART_SCR,
- AWA_maska_set = UART_SCR,
- AWA_maska_toggle = UART_SCR,
- AWA_maskb = UART_GCTL,
- AWA_maskb_clear = UART_GCTL,
- AWA_maskb_set = UART_GCTL,
- AWA_maskb_toggle = UART_GCTL,
- AWA_dir = SPORT1_STAT,
- AWA_polar = SPORT1_STAT,
- AWA_edge = SPORT1_STAT,
- AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
- AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
- AWA_inen = DMA1_1_CONFIG,
-#endif
-};
- /* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...) do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY)
- (struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \
- || defined(BF538_FAMILY) || defined(CONFIG_BF50x)
- (struct gpio_port_t *) PORTFIO,
-# if !defined(BF538_FAMILY)
- (struct gpio_port_t *) PORTGIO,
- (struct gpio_port_t *) PORTHIO,
-# endif
-#elif defined(BF561_FAMILY)
- (struct gpio_port_t *) FIO0_FLAG_D,
- (struct gpio_port_t *) FIO1_FLAG_D,
- (struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
- defined(CONFIG_BF50x)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTF_FER,
- (unsigned short *) PORTG_FER,
- (unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
- (unsigned short *) PORTF_MUX,
- (unsigned short *) PORTG_MUX,
- (unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-# if defined(CONFIG_BF52x)
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
- { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-# elif defined(CONFIG_BF51x)
- { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
- { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
- { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-# endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTCIO_FER,
- (unsigned short *) PORTDIO_FER,
- (unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#ifdef CONFIG_BFIN_GPIO_TRACK
-#define RESOURCE_LABEL_SIZE 16
-
-static struct str_ident {
- char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-static void gpio_error(unsigned gpio)
-{
- printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
- if (label) {
- strncpy(str_ident[ident].name, label,
- RESOURCE_LABEL_SIZE);
- str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
- }
-}
-
-static char *get_label(unsigned short ident)
-{
- return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
- if (label == NULL)
- printf("bfin-gpio: please provide none-null label\n");
-
- if (label)
- return strcmp(str_ident[ident].name, label);
- else
- return -EINVAL;
-}
-
-#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-#else
-#define is_reserved(m, i, e) (!(e))
-#define reserve(m, i)
-#define unreserve(m, i)
-#define DECLARE_RESERVED_MAP(m, c)
-#define gpio_error(gpio)
-#define set_label(...)
-#define get_label(...) ""
-#define cmp_label(...) 1
-#endif
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
-
-inline int check_gpio(unsigned gpio)
-{
- if (gpio >= MAX_BLACKFIN_GPIOS)
- return -EINVAL;
- return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
- /*
- * BF538/9 Port C,D and E are special.
- * Inverted PORT_FER polarity on CDE and no PORF_FER on F
- * Regular PORT F GPIOs are handled here, CDE are exclusively
- * managed by GPIOLIB
- */
-
- if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
- return;
-
- gpio -= MAX_BLACKFIN_GPIOS;
-
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
- return;
-#endif
-
- if (check_gpio(gpio))
- return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
- defined(CONFIG_BF50x)
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static struct {
- unsigned short res;
- unsigned short offset;
-} port_mux_lut[] = {
- {.res = P_PPI0_D13, .offset = 11},
- {.res = P_PPI0_D14, .offset = 11},
- {.res = P_PPI0_D15, .offset = 11},
- {.res = P_SPORT1_TFS, .offset = 11},
- {.res = P_SPORT1_TSCLK, .offset = 11},
- {.res = P_SPORT1_DTPRI, .offset = 11},
- {.res = P_PPI0_D10, .offset = 10},
- {.res = P_PPI0_D11, .offset = 10},
- {.res = P_PPI0_D12, .offset = 10},
- {.res = P_SPORT1_RSCLK, .offset = 10},
- {.res = P_SPORT1_RFS, .offset = 10},
- {.res = P_SPORT1_DRPRI, .offset = 10},
- {.res = P_PPI0_D8, .offset = 9},
- {.res = P_PPI0_D9, .offset = 9},
- {.res = P_SPORT1_DRSEC, .offset = 9},
- {.res = P_SPORT1_DTSEC, .offset = 9},
- {.res = P_TMR2, .offset = 8},
- {.res = P_PPI0_FS3, .offset = 8},
- {.res = P_TMR3, .offset = 7},
- {.res = P_SPI0_SSEL4, .offset = 7},
- {.res = P_TMR4, .offset = 6},
- {.res = P_SPI0_SSEL5, .offset = 6},
- {.res = P_TMR5, .offset = 5},
- {.res = P_SPI0_SSEL6, .offset = 5},
- {.res = P_UART1_RX, .offset = 4},
- {.res = P_UART1_TX, .offset = 4},
- {.res = P_TMR6, .offset = 4},
- {.res = P_TMR7, .offset = 4},
- {.res = P_UART0_RX, .offset = 3},
- {.res = P_UART0_TX, .offset = 3},
- {.res = P_DMAR0, .offset = 3},
- {.res = P_DMAR1, .offset = 3},
- {.res = P_SPORT0_DTSEC, .offset = 1},
- {.res = P_SPORT0_DRSEC, .offset = 1},
- {.res = P_CAN0_RX, .offset = 1},
- {.res = P_CAN0_TX, .offset = 1},
- {.res = P_SPI0_SSEL7, .offset = 1},
- {.res = P_SPORT0_TFS, .offset = 0},
- {.res = P_SPORT0_DTPRI, .offset = 0},
- {.res = P_SPI0_SSEL2, .offset = 0},
- {.res = P_SPI0_SSEL3, .offset = 0},
-};
-
-static void portmux_setup(unsigned short per)
-{
- u16 y, offset, muxreg, mask;
- u16 function = P_FUNCT2MUX(per);
-
- for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
- if (port_mux_lut[y].res == per) {
-
- /* SET PORTMUX REG */
-
- offset = port_mux_lut[y].offset;
- muxreg = bfin_read_PORT_MUX();
-
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- muxreg &= ~(mask << offset);
- muxreg |= ((function & mask) << offset);
- bfin_write_PORT_MUX(muxreg);
- }
- }
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-inline void portmux_setup(unsigned short per)
-{
- u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
-
- pmux = *port_mux[gpio_bank(ident)];
- pmux &= ~(3 << offset);
- pmux |= (function & 3) << offset;
- *port_mux[gpio_bank(ident)] = pmux;
- SSYNC();
-}
-#else
-# define portmux_setup(...) do { } while (0)
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- local_irq_save(flags); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
- AWA_DUMMY_READ(name); \
- local_irq_restore(flags); \
-}
-
-SET_GPIO(dir) /* set_gpio_dir() */
-SET_GPIO(inen) /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge) /* set_gpio_edge() */
-SET_GPIO(both) /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- local_irq_save(flags); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- local_irq_restore(flags); \
- } \
-}
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
- unsigned long flags;
- if (ANOMALY_05000311 || ANOMALY_05000323)
- local_irq_save(flags);
- gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
- if (ANOMALY_05000311 || ANOMALY_05000323) {
- AWA_DUMMY_READ(toggle);
- local_irq_restore(flags);
- }
-}
-
-/* Set current PORT date (16-bit word) */
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- local_irq_save(flags); \
- gpio_array[gpio_bank(gpio)]->name = arg; \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- local_irq_restore(flags); \
- } \
-}
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- local_irq_save(flags); \
- ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- local_irq_restore(flags); \
- } \
- return ret; \
-}
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/* Get current PORT date (16-bit word) */
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- local_irq_save(flags); \
- ret = (gpio_array[gpio_bank(gpio)]->name); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- local_irq_restore(flags); \
- } \
- return ret; \
-}
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin Peripheral Resource Allocation
-* and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per Peripheral Identifier
-* label String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
- unsigned short ident = P_IDENT(per);
-
- /*
- * Don't cares are pins with only one dedicated function
- */
-
- if (per & P_DONTCARE)
- return 0;
-
- if (!(per & P_DEFINED))
- return -ENODEV;
-
- BUG_ON(ident >= MAX_RESOURCES);
-
- /* If a pin can be muxed as either GPIO or peripheral, make
- * sure it is not already a GPIO pin when we request it.
- */
- if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
- printf("%s: Peripheral %d is already reserved as GPIO by %s !\n",
- __func__, ident, get_label(ident));
- return -EBUSY;
- }
-
- if (unlikely(is_reserved(peri, ident, 1))) {
-
- /*
- * Pin functions like AMC address strobes my
- * be requested and used by several drivers
- */
-
- if (!(per & P_MAYSHARE)) {
- /*
- * Allow that the identical pin function can
- * be requested from the same driver twice
- */
-
- if (cmp_label(ident, label) == 0)
- goto anyway;
-
- printf("%s: Peripheral %d function %d is already reserved by %s !\n",
- __func__, ident, P_FUNCT2MUX(per), get_label(ident));
- return -EBUSY;
- }
- }
-
- anyway:
- reserve(peri, ident);
-
- portmux_setup(per);
- port_setup(ident, PERIPHERAL_USAGE);
-
- set_label(ident, label);
-
- return 0;
-}
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
- u16 cnt;
- int ret;
-
- for (cnt = 0; per[cnt] != 0; cnt++) {
-
- ret = peripheral_request(per[cnt], label);
-
- if (ret < 0) {
- for ( ; cnt > 0; cnt--)
- peripheral_free(per[cnt - 1]);
-
- return ret;
- }
- }
-
- return 0;
-}
-
-void peripheral_free(unsigned short per)
-{
- unsigned short ident = P_IDENT(per);
-
- if (per & P_DONTCARE)
- return;
-
- if (!(per & P_DEFINED))
- return;
-
- if (unlikely(!is_reserved(peri, ident, 0)))
- return;
-
- if (!(per & P_MAYSHARE))
- port_setup(ident, GPIO_USAGE);
-
- unreserve(peri, ident);
-
- set_label(ident, "free");
-}
-
-void peripheral_free_list(const unsigned short per[])
-{
- u16 cnt;
- for (cnt = 0; per[cnt] != 0; cnt++)
- peripheral_free(per[cnt]);
-}
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int gpio_request(unsigned gpio, const char *label)
-{
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0)
- return 0;
-
- if (unlikely(is_reserved(gpio, gpio, 1))) {
- printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- return -EBUSY;
- }
- else { /* Reset POLAR setting when acquiring a gpio for the first time */
- set_gpio_polar(gpio, 0);
- }
-
- reserve(gpio, gpio);
- set_label(gpio, label);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
- if (check_gpio(gpio) < 0)
- return -1;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -1;
- }
-
- unreserve(gpio, gpio);
-
- set_label(gpio, "free");
-
- return 0;
-}
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int special_gpio_request(unsigned gpio, const char *label)
-{
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0)
- return 0;
-
- if (unlikely(is_reserved(special_gpio, gpio, 1))) {
- printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
-
- reserve(special_gpio, gpio);
- reserve(peri, gpio);
-
- set_label(gpio, label);
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-void special_gpio_free(unsigned gpio)
-{
- if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
- gpio_error(gpio);
- return;
- }
-
- unreserve(special_gpio, gpio);
- unreserve(peri, gpio);
- set_label(gpio, "free");
-}
-#endif
-
-static inline void __gpio_direction_input(unsigned gpio)
-{
- gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
- gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (!is_reserved(gpio, gpio, 0)) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- local_irq_save(flags);
- __gpio_direction_input(gpio);
- AWA_DUMMY_READ(inen);
- local_irq_restore(flags);
-
- return 0;
-}
-
-int gpio_set_value(unsigned gpio, int arg)
-{
- if (arg)
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- else
- gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-
- return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (!is_reserved(gpio, gpio, 0)) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- local_irq_save(flags);
-
- gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
- gpio_set_value(gpio, value);
- gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
- AWA_DUMMY_READ(dir);
- local_irq_restore(flags);
-
- return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(get_gpio_edge(gpio))) {
- int ret;
- local_irq_save(flags);
- set_gpio_edge(gpio, 0);
- ret = get_gpio_data(gpio);
- set_gpio_edge(gpio, 1);
- local_irq_restore(flags);
- return ret;
- } else
- return get_gpio_data(gpio);
-}
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high. To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
- unsigned short gpio = P_IDENT(pin);
- port_setup(gpio, GPIO_USAGE);
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- AWA_DUMMY_READ(data_set);
- udelay(1);
-}
-
-int name_to_gpio(const char *name)
-{
- int port_base;
-
- if (tolower(*name) == 'p') {
- ++name;
-
- switch (tolower(*name)) {
-#ifdef GPIO_PA0
- case 'a': port_base = GPIO_PA0; break;
-#endif
-#ifdef GPIO_PB0
- case 'b': port_base = GPIO_PB0; break;
-#endif
-#ifdef GPIO_PC0
- case 'c': port_base = GPIO_PC0; break;
-#endif
-#ifdef GPIO_PD0
- case 'd': port_base = GPIO_PD0; break;
-#endif
-#ifdef GPIO_PE0
- case 'e': port_base = GPIO_PE0; break;
-#endif
-#ifdef GPIO_PF0
- case 'f': port_base = GPIO_PF0; break;
-#endif
-#ifdef GPIO_PG0
- case 'g': port_base = GPIO_PG0; break;
-#endif
-#ifdef GPIO_PH0
- case 'h': port_base = GPIO_PH0; break;
-#endif
-#ifdef GPIO_PI0
- case 'i': port_base = GPIO_PI0; break;
-#endif
-#ifdef GPIO_PJ
- case 'j': port_base = GPIO_PJ0; break;
-#endif
- default: return -1;
- }
-
- ++name;
- } else
- port_base = 0;
-
- return port_base + simple_strtoul(name, NULL, 10);
-}
-
-void gpio_labels(void)
-{
- int c, gpio;
-
- for (c = 0; c < MAX_RESOURCES; c++) {
- gpio = is_reserved(gpio, c, 1);
- if (!check_gpio(c) && gpio)
- printf("GPIO_%d:\t%s\tGPIO %s\n", c,
- get_label(c),
- get_gpio_dir(c) ? "OUTPUT" : "INPUT");
- else if (is_reserved(peri, c, 1))
- printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
- else
- continue;
- }
-}
-#else
-struct gpio_port_t * const gpio_array[] = {
- (struct gpio_port_t *)PORTA_FER,
- (struct gpio_port_t *)PORTB_FER,
- (struct gpio_port_t *)PORTC_FER,
- (struct gpio_port_t *)PORTD_FER,
- (struct gpio_port_t *)PORTE_FER,
- (struct gpio_port_t *)PORTF_FER,
- (struct gpio_port_t *)PORTG_FER,
-#if defined(CONFIG_BF54x)
- (struct gpio_port_t *)PORTH_FER,
- (struct gpio_port_t *)PORTI_FER,
- (struct gpio_port_t *)PORTJ_FER,
-#endif
-};
-#endif
diff --git a/arch/blackfin/cpu/init.S b/arch/blackfin/cpu/init.S
deleted file mode 100644
index f48c113206fe..000000000000
--- a/arch/blackfin/cpu/init.S
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <asm/blackfin.h>
-ENTRY(_start)
- sp.l = LO(L1_SRAM_SCRATCH_END - 20);
- sp.h = HI(L1_SRAM_SCRATCH_END - 20);
- call _initcode;
-1:
- emuexcpt;
- jump 1b;
-END(_start)
diff --git a/arch/blackfin/cpu/init.lds.S b/arch/blackfin/cpu/init.lds.S
deleted file mode 100644
index 602e7c8791ac..000000000000
--- a/arch/blackfin/cpu/init.lds.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * linker script for simple init.elf
- *
- * Copyright (c) 2005-2011 Analog Device Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
- l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
- .text.l1 : { *(.text .text.*) } >l1_code
-}
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
deleted file mode 100644
index fde54eaa3e55..000000000000
--- a/arch/blackfin/cpu/initcode.c
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * initcode.c - Initialize the processor. This is usually entails things
- * like external memory, voltage regulators, etc... Note that this file
- * cannot make any function calls as it may be executed all by itself by
- * the Blackfin's bootrom in LDR format.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BFIN_IN_INITCODE
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/serial.h>
-
-#ifndef __ADSPBF60x__
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#else /* __ADSPBF60x__ */
-#include <asm/mach-common/bits/cgu.h>
-
-#define CONFIG_BFIN_GET_DCLK_M \
- ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
-
-#ifndef CONFIG_DMC_DDRCFG
-#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
- (CONFIG_BFIN_GET_DCLK_M != 133) && \
- (CONFIG_BFIN_GET_DCLK_M != 150) && \
- (CONFIG_BFIN_GET_DCLK_M != 166) && \
- (CONFIG_BFIN_GET_DCLK_M != 200) && \
- (CONFIG_BFIN_GET_DCLK_M != 225) && \
- (CONFIG_BFIN_GET_DCLK_M != 250))
-#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-#endif
-
-/* DMC control bits */
-#define SRREQ 0x8
-
-/* DMC status bits */
-#define IDLE 0x1
-#define MEMINITDONE 0x4
-#define SRACK 0x8
-#define PDACK 0x10
-#define DPDACK 0x20
-#define DLLCALDONE 0x2000
-#define PENDREF 0xF0000
-#define PHYRDPHASE 0xF00000
-#define PHYRDPHASE_OFFSET 20
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT 0xFF
-#define DATACYC_OFFSET 8
-
-struct ddr_config {
- u32 ddr_clk;
- u32 dmc_ddrctl;
- u32 dmc_ddrcfg;
- u32 dmc_ddrtr0;
- u32 dmc_ddrtr1;
- u32 dmc_ddrtr2;
- u32 dmc_ddrmr;
- u32 dmc_ddrmr1;
-};
-
-static struct ddr_config ddr_config_table[] = {
- [0] = {
- .ddr_clk = 125, /* 125MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20705212,
- .dmc_ddrtr1 = 0x201003CF,
- .dmc_ddrtr2 = 0x00320107,
- .dmc_ddrmr = 0x00000422,
- .dmc_ddrmr1 = 0x4,
- },
- [1] = {
- .ddr_clk = 133, /* 133MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20806313,
- .dmc_ddrtr1 = 0x2013040D,
- .dmc_ddrtr2 = 0x00320108,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [2] = {
- .ddr_clk = 150, /* 150MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x20160492,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [3] = {
- .ddr_clk = 166, /* 166MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x2016050E,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [4] = {
- .ddr_clk = 200, /* 200MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20a07323,
- .dmc_ddrtr1 = 0x2016050f,
- .dmc_ddrtr2 = 0x00320509,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [5] = {
- .ddr_clk = 225, /* 225MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x302006DB,
- .dmc_ddrtr2 = 0x0032020D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
- [6] = {
- .ddr_clk = 250, /* 250MHz */
- .dmc_ddrctl = 0x00000904,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x3020079E,
- .dmc_ddrtr2 = 0x0032050D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
-};
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline))
-static inline void serial_init(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
-# ifdef BFIN_BOOT_UART_USE_RTS
-# define BFIN_UART_USE_RTS 1
-# else
-# define BFIN_UART_USE_RTS 0
-# endif
- if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
- uint32_t uart_base = UART_BASE;
- size_t i;
-
- /* force RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
- bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
-#else
- bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
- FCPOL);
-#endif
-
- /* Wait for the line to clear up. We cannot rely on UART
- * registers as none of them reflect the status of the RSR.
- * Instead, we'll sleep for ~10 bit times at 9600 baud.
- * We can precalc things here by assuming boot values for
- * PLL rather than loading registers and calculating.
- * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
- * EDB0 = 0
- * Divisor = (SCLK / baud) / 16
- * SCLK = baud * 16 * Divisor
- * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
- * CCLK = (16 * Divisor * 5) * (9600 / 10)
- * In reality, this will probably be just about 1 second delay,
- * so assuming 9600 baud is OK (both as a very low and too high
- * speed as this will buffer things enough).
- */
-#define _NUMBITS (10) /* how many bits to delay */
-#define _LOWBAUD (9600) /* low baud rate */
-#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
-#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
-#define _NUMINS (3) /* how many instructions in loop */
-#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
- i = _CCLK;
- while (i--)
- asm volatile("" : : : "memory");
- }
-#endif
-
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
- if (BFIN_DEBUG_EARLY_SERIAL) {
- serial_early_init(UART_BASE);
- serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
- }
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_deinit(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
- uint32_t uart_base = UART_BASE;
-
- if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
- /* clear forced RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
- bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
-#else
- bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
- ~FCPOL);
-#endif
- }
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_putc(char c)
-{
- uint32_t uart_base = UART_BASE;
-
- if (!BFIN_DEBUG_EARLY_SERIAL)
- return;
-
- if (c == '\n')
- serial_putc('\r');
-
- bfin_write(&pUART->thr, c);
-
- while (!(_lsr_read(pUART) & TEMT))
- continue;
-}
-
-#include "initcode.h"
-
-__attribute__((always_inline)) static inline void
-program_nmi_handler(void)
-{
- u32 tmp1, tmp2;
-
- /* Older bootroms don't create a dummy NMI handler,
- * so make one ourselves ASAP in case it fires.
- */
- if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
- return;
-
- asm volatile (
- "%0 = RETS;" /* Save current RETS */
- "CALL 1f;" /* Figure out current PC */
- "RTN;" /* The simple NMI handler */
- "1:"
- "%1 = RETS;" /* Load addr of NMI handler */
- "RETS = %0;" /* Restore RETS */
- "[%2] = %1;" /* Write NMI handler */
- : "=d"(tmp1), "=d"(tmp2)
- : "ab"(EVT2)
- );
-}
-
-/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
- * us a freq of 16MHz for SPI which should generally be
- * slow enough for the slow reads the bootrom uses.
- */
-#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
- ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
- (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
-#else
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
-#endif
-#ifndef CONFIG_SPI_BAUD_INITBLOCK
-# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
-#endif
-#ifdef SPI0_BAUD
-# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
-#endif
-
-#ifdef __ADSPBF60x__
-
-#ifndef CONFIG_CGU_CTL_VAL
-# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
-#endif
-
-#ifndef CONFIG_CGU_DIV_VAL
-# define CONFIG_CGU_DIV_VAL \
- ((CONFIG_CCLK_DIV << CSEL_P) | \
- (CONFIG_SCLK0_DIV << S0SEL_P) | \
- (CONFIG_SCLK_DIV << SYSSEL_P) | \
- (CONFIG_SCLK1_DIV << S1SEL_P) | \
- (CONFIG_DCLK_DIV << DSEL_P) | \
- (CONFIG_OCLK_DIV << OSEL_P))
-#endif
-
-#else /* __ADSPBF60x__ */
-
-/* PLL_DIV defines */
-#ifndef CONFIG_PLL_DIV_VAL
-# if (CONFIG_CCLK_DIV == 1)
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# elif (CONFIG_CCLK_DIV == 2)
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# elif (CONFIG_CCLK_DIV == 4)
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# elif (CONFIG_CCLK_DIV == 8)
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# else
-# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-# endif
-# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
-#endif
-
-#ifndef CONFIG_PLL_LOCKCNT_VAL
-# define CONFIG_PLL_LOCKCNT_VAL 0x0300
-#endif
-
-#ifndef CONFIG_PLL_CTL_VAL
-# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
-#endif
-
-/* Make sure our voltage value is sane so we don't blow up! */
-#ifndef CONFIG_VR_CTL_VAL
-# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
-# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
-# define CCLK_VLEV_120 400000000
-# define CCLK_VLEV_125 533000000
-# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-# define CCLK_VLEV_120 401000000
-# define CCLK_VLEV_125 401000000
-# elif defined(__ADSPBF561__)
-# define CCLK_VLEV_120 300000000
-# define CCLK_VLEV_125 501000000
-# endif
-# if BFIN_CCLK < CCLK_VLEV_120
-# define CONFIG_VR_CTL_VLEV VLEV_120
-# elif BFIN_CCLK < CCLK_VLEV_125
-# define CONFIG_VR_CTL_VLEV VLEV_125
-# else
-# define CONFIG_VR_CTL_VLEV VLEV_130
-# endif
-# if defined(__ADSPBF52x__) /* TBD; use default */
-# undef CONFIG_VR_CTL_VLEV
-# define CONFIG_VR_CTL_VLEV VLEV_110
-# elif defined(__ADSPBF54x__) /* TBD; use default */
-# undef CONFIG_VR_CTL_VLEV
-# define CONFIG_VR_CTL_VLEV VLEV_120
-# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
-# undef CONFIG_VR_CTL_VLEV
-# define CONFIG_VR_CTL_VLEV VLEV_125
-# endif
-
-# ifdef CONFIG_BFIN_MAC
-# define CONFIG_VR_CTL_CLKBUF CLKBUFOE
-# else
-# define CONFIG_VR_CTL_CLKBUF 0
-# endif
-
-# if defined(__ADSPBF52x__)
-# define CONFIG_VR_CTL_FREQ FREQ_1000
-# else
-# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
-# endif
-
-# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
-#endif
-
-/* some parts do not have an on-chip voltage regulator */
-#if defined(__ADSPBF51x__)
-# define CONFIG_HAS_VR 0
-# undef CONFIG_VR_CTL_VAL
-# define CONFIG_VR_CTL_VAL 0
-#else
-# define CONFIG_HAS_VR 1
-#endif
-
-#if CONFIG_MEM_SIZE
-#ifndef EBIU_RSTCTL
-/* Blackfin with SDRAM */
-#ifndef CONFIG_EBIU_SDBCTL_VAL
-# if CONFIG_MEM_SIZE == 16
-# define CONFIG_EBSZ_VAL EBSZ_16
-# elif CONFIG_MEM_SIZE == 32
-# define CONFIG_EBSZ_VAL EBSZ_32
-# elif CONFIG_MEM_SIZE == 64
-# define CONFIG_EBSZ_VAL EBSZ_64
-# elif CONFIG_MEM_SIZE == 128
-# define CONFIG_EBSZ_VAL EBSZ_128
-# elif CONFIG_MEM_SIZE == 256
-# define CONFIG_EBSZ_VAL EBSZ_256
-# elif CONFIG_MEM_SIZE == 512
-# define CONFIG_EBSZ_VAL EBSZ_512
-# else
-# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
-# endif
-# if CONFIG_MEM_ADD_WDTH == 8
-# define CONFIG_EBCAW_VAL EBCAW_8
-# elif CONFIG_MEM_ADD_WDTH == 9
-# define CONFIG_EBCAW_VAL EBCAW_9
-# elif CONFIG_MEM_ADD_WDTH == 10
-# define CONFIG_EBCAW_VAL EBCAW_10
-# elif CONFIG_MEM_ADD_WDTH == 11
-# define CONFIG_EBCAW_VAL EBCAW_11
-# else
-# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
-# endif
-# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
-#endif
-#endif
-#endif
-
-/* Conflicting Column Address Widths Causes SDRAM Errors:
- * EB2CAW and EB3CAW must be the same
- */
-#if ANOMALY_05000362
-# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
-# error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
-# endif
-#endif
-
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
-{
- serial_putc('a');
-
- /* Save the clock pieces that are used in baud rate calculation */
- if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
- serial_putc('b');
-#ifdef __ADSPBF60x__
- *sdivB = bfin_read_CGU_DIV();
- *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
- *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
- *sdivB = bfin_read_PLL_DIV() & 0xf;
- *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
- *divB = serial_early_get_div();
- serial_putc('c');
- }
-
- serial_putc('d');
-
-#ifdef CONFIG_HW_WATCHDOG
-# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
-# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
-# endif
- /* Program the watchdog with an initial timeout of ~20 seconds.
- * Hopefully that should be long enough to load the u-boot LDR
- * (from wherever) and then the common u-boot code can take over.
- * In bypass mode, the start.S would have already set a much lower
- * timeout, so don't clobber that.
- */
- if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
- serial_putc('e');
-#ifdef __ADSPBF60x__
- /* Reset system event controller */
- bfin_write_SEC_GCTL(0x2);
- bfin_write_SEC_CCTL(0x2);
- SSYNC();
-
- /* Enable fault event input and system reset action in fault
- * controller. Route watchdog timeout event to fault interface.
- */
- bfin_write_SEC_FCTL(0xc1);
- /* Enable watchdog interrupt source */
- bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
- SSYNC();
-
- /* Enable system event controller */
- bfin_write_SEC_GCTL(0x1);
- bfin_write_SEC_CCTL(0x1);
- SSYNC();
-#endif
- bfin_write_WDOG_CTL(WDDIS);
- SSYNC();
- bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
- bfin_write_WDOG_CTL(WDEN);
-#endif
- serial_putc('f');
- }
-#endif
-
- serial_putc('g');
-
- /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
- * fast read, so we need to slow down the SPI clock a lot more during
- * boot. Once we switch over to u-boot's SPI flash driver, we'll
- * increase the speed appropriately.
- */
-#ifdef SPI_BAUD
- if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
- serial_putc('h');
- if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
- bs->dFlags |= BFLAG_FASTREAD;
- bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
- serial_putc('i');
- }
-#endif
-
- serial_putc('j');
-}
-
-__attribute__((always_inline)) static inline bool
-maybe_self_refresh(ADI_BOOT_DATA *bs)
-{
- serial_putc('a');
-
- if (!CONFIG_MEM_SIZE)
- return false;
-
-#ifdef __ADSPBF60x__
- /* resume from hibernate, return false let ddr initialize */
- if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
- serial_putc('b');
- return false;
- }
-
-#else /* __ADSPBF60x__ */
-
- /* If external memory is enabled, put it into self refresh first. */
-#if defined(EBIU_RSTCTL)
- if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
- serial_putc('b');
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
- return true;
- }
-#elif defined(EBIU_SDGCTL)
- if (bfin_read_EBIU_SDBCTL() & EBE) {
- serial_putc('b');
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
- return true;
- }
-#endif
-
-#endif /* __ADSPBF60x__ */
- serial_putc('c');
-
- return false;
-}
-
-__attribute__((always_inline)) static inline u16
-program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
- u16 vr_ctl = 0;
-
- serial_putc('a');
-
-#ifdef __ADSPBF60x__
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
- SSYNC();
- while (!(bfin_read_DMC0_STAT() & SRACK))
- continue;
- }
-
- /* Don't set the same value of MSEL and DF to CGU_CTL */
- if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
- != CONFIG_CGU_CTL_VAL) {
- bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
- bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
- while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
- !(bfin_read_CGU_STAT() & PLLLK))
- continue;
- }
-
- bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
- while (bfin_read_CGU_STAT() & CLKSALGN)
- continue;
-
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
- SSYNC();
- while (bfin_read_DMC0_STAT() & SRACK)
- continue;
- }
-
-#else /* __ADSPBF60x__ */
-
- vr_ctl = bfin_read_VR_CTL();
-
- serial_putc('b');
-
- /* If we're entering self refresh, make sure it has happened. */
- if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
- while (!(bfin_read_EBIU_RSTCTL() & SRACK))
- continue;
-#elif defined(EBIU_SDGCTL)
- while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
- continue;
-#else
- ;
-#endif
-
- serial_putc('c');
-
- /* With newer bootroms, we use the helper function to set up
- * the memory controller. Older bootroms lacks such helpers
- * so we do it ourselves.
- */
- if (!ANOMALY_05000386) {
- serial_putc('d');
-
- /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
- ADI_SYSCTRL_VALUES memory_settings;
- uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
- if (!ANOMALY_05000440)
- actions |= SYSCTRL_PLLDIV;
- if (CONFIG_HAS_VR) {
- actions |= SYSCTRL_VRCTL;
- if (CONFIG_VR_CTL_VAL & FREQ_MASK)
- actions |= SYSCTRL_INTVOLTAGE;
- else
- actions |= SYSCTRL_EXTVOLTAGE;
- memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
- } else
- actions |= SYSCTRL_EXTVOLTAGE;
- memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
- memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
- memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
-#if ANOMALY_05000432
- bfin_write_SIC_IWR1(0);
-#endif
- serial_putc('e');
- bfrom_SysControl(actions, &memory_settings, NULL);
- serial_putc('f');
- if (ANOMALY_05000440)
- bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-#if ANOMALY_05000432
- bfin_write_SIC_IWR1(-1);
-#endif
-#if ANOMALY_05000171
- bfin_write_SICA_IWR0(-1);
- bfin_write_SICA_IWR1(-1);
-#endif
- serial_putc('g');
- } else {
- serial_putc('h');
-
- /* Disable all peripheral wakeups except for the PLL event. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(1);
- bfin_write_SIC_IWR1(0);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(0);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(1);
- bfin_write_SICA_IWR1(0);
-#elif defined(SIC_IWR)
- bfin_write_SIC_IWR(1);
-#endif
-
- serial_putc('i');
-
- /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
- bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
-
- serial_putc('j');
-
- /* Only reprogram when needed to avoid triggering unnecessary
- * PLL relock sequences.
- */
- if (vr_ctl != CONFIG_VR_CTL_VAL) {
- serial_putc('?');
- bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
- asm("idle;");
- serial_putc('!');
- }
-
- serial_putc('k');
-
- bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-
- serial_putc('l');
-
- /* Only reprogram when needed to avoid triggering unnecessary
- * PLL relock sequences.
- */
- if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
- serial_putc('?');
- bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
- asm("idle;");
- serial_putc('!');
- }
-
- serial_putc('m');
-
- /* Restore all peripheral wakeups. */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(-1);
- bfin_write_SIC_IWR1(-1);
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(-1);
-# endif
-#elif defined(SICA_IWR0)
- bfin_write_SICA_IWR0(-1);
- bfin_write_SICA_IWR1(-1);
-#elif defined(SIC_IWR)
- bfin_write_SIC_IWR(-1);
-#endif
-
- serial_putc('n');
- }
-
-#endif /* __ADSPBF60x__ */
-
- serial_putc('o');
-
- return vr_ctl;
-}
-
-__attribute__((always_inline)) static inline void
-update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
-{
- /* Since we've changed the SCLK above, we may need to update
- * the UART divisors (UART baud rates are based on SCLK).
- * Do the division by hand as there are no native instructions
- * for dividing which means we'd generate a libgcc reference.
- */
- unsigned int sdivR, vcoR;
- unsigned int dividend;
- unsigned int divisor;
- unsigned int quotient;
-
- serial_putc('a');
-
- if (BFIN_DEBUG_EARLY_SERIAL ||
- CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-#ifdef __ADSPBF60x__
- sdivR = bfin_read_CGU_DIV();
- sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
- vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
- sdivR = bfin_read_PLL_DIV() & 0xf;
- vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
-
- dividend = sdivB * divB * vcoR;
- divisor = vcoB * sdivR;
- quotient = early_division(dividend, divisor);
- serial_early_put_div(quotient - ANOMALY_05000230);
- }
-
- serial_putc('c');
-}
-
-__attribute__((always_inline)) static inline void
-program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
- serial_putc('a');
-
- if (!CONFIG_MEM_SIZE)
- return;
-
- serial_putc('b');
-
-#ifdef __ADSPBF60x__
- int dlldatacycle;
- int dll_ctl;
- int i = 0;
-
- if (CONFIG_BFIN_GET_DCLK_M == 125)
- i = 0;
- else if (CONFIG_BFIN_GET_DCLK_M == 133)
- i = 1;
- else if (CONFIG_BFIN_GET_DCLK_M == 150)
- i = 2;
- else if (CONFIG_BFIN_GET_DCLK_M == 166)
- i = 3;
- else if (CONFIG_BFIN_GET_DCLK_M == 200)
- i = 4;
- else if (CONFIG_BFIN_GET_DCLK_M == 225)
- i = 5;
- else if (CONFIG_BFIN_GET_DCLK_M == 250)
- i = 6;
-
-#if 0
- for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
- if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
- break;
-#endif
-
-#ifndef CONFIG_DMC_DDRCFG
- bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
-#else
- bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
-#endif
-#ifndef CONFIG_DMC_DDRTR0
- bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
-#else
- bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
-#endif
-#ifndef CONFIG_DMC_DDRTR1
- bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
-#else
- bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
-#endif
-#ifndef CONFIG_DMC_DDRTR2
- bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
-#else
- bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
-#endif
-#ifndef CONFIG_DMC_DDRMR
- bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
-#else
- bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
-#endif
-#ifndef CONFIG_DMC_DDREMR1
- bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
-#else
- bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
-#endif
-#ifndef CONFIG_DMC_DDRCTL
- bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
-#else
- bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
-#endif
-
- SSYNC();
- while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
- continue;
-
- dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
- PHYRDPHASE_OFFSET;
- dll_ctl = bfin_read_DMC0_DLLCTL();
- dll_ctl &= 0x0ff;
- bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
- SSYNC();
- while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
- continue;
- serial_putc('!');
-
-#else /* __ADSPBF60x__ */
-
- /* Program the external memory controller before we come out of
- * self-refresh. This only works with our SDRAM controller.
- */
-#ifdef EBIU_SDGCTL
-# ifdef CONFIG_EBIU_SDRRC_VAL
- bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDBCTL_VAL
- bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDGCTL_VAL
- bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
-# endif
-#endif
-
- serial_putc('c');
-
- /* Now that we've reprogrammed, take things out of self refresh. */
- if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
-#elif defined(EBIU_SDGCTL)
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
-#endif
-
- serial_putc('d');
-
- /* Our DDR controller sucks and cannot be programmed while in
- * self-refresh. So we have to pull it out before programming.
- */
-#ifdef EBIU_RSTCTL
-# ifdef CONFIG_EBIU_RSTCTL_VAL
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL0_VAL
- bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL1_VAL
- bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL2_VAL
- bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL3_VAL
- /* default is disable, so don't need to force this */
- bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRQUE_VAL
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
-# endif
-#endif
-
-#endif /* __ADSPBF60x__ */
- serial_putc('e');
-}
-
-__attribute__((always_inline)) static inline void
-check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
-{
- serial_putc('a');
-
- if (!CONFIG_MEM_SIZE)
- return;
-
- serial_putc('b');
-#ifdef __ADSPBF60x__
- if (bfin_read32(DPM0_RESTORE0) != 0) {
- uint32_t reg = bfin_read_DMC0_CTL();
- reg &= ~0x8;
- bfin_write_DMC0_CTL(reg);
-
- while ((bfin_read_DMC0_STAT() & 0x8))
- continue;
- while (!(bfin_read_DMC0_STAT() & 0x1))
- continue;
-
- serial_putc('z');
- uint32_t *hibernate_magic =
- (uint32_t *)bfin_read32(DPM0_RESTORE4);
- SSYNC(); /* make sure memory controller is done */
- if (hibernate_magic[0] == 0xDEADBEEF) {
- serial_putc('c');
- SSYNC();
- bfin_write_EVT15(hibernate_magic[1]);
- bfin_write_IMASK(EVT_IVG15);
- __asm__ __volatile__ (
- /* load reti early to avoid anomaly 281 */
- "reti = %2;"
- /* clear hibernate magic */
- "[%0] = %1;"
- /* load stack pointer */
- "SP = [%0 + 8];"
- /* lower ourselves from reset ivg to ivg15 */
- "raise 15;"
- "nop;nop;nop;"
- "rti;"
- :
- : "p"(hibernate_magic),
- "d"(0x2000 /* jump.s 0 */),
- "d"(0xffa00000)
- );
- }
-
-
- }
-#else
- /* Are we coming out of hibernate (suspend to memory) ?
- * The memory layout is:
- * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
- * 0x4: return address
- * 0x8: stack pointer
- *
- * SCKELOW is unreliable on older parts (anomaly 307)
- */
- if (ANOMALY_05000307 || vr_ctl & 0x8000) {
- uint32_t *hibernate_magic = 0;
-
- SSYNC();
- /* cppcheck-suppress nullPointer */
- if (hibernate_magic[0] == 0xDEADBEEF) {
- serial_putc('c');
- bfin_write_EVT15(hibernate_magic[1]);
- bfin_write_IMASK(EVT_IVG15);
- __asm__ __volatile__ (
- /* load reti early to avoid anomaly 281 */
- "reti = %0;"
- /* clear hibernate magic */
- "[%0] = %1;"
- /* load stack pointer */
- "SP = [%0 + 8];"
- /* lower ourselves from reset ivg to ivg15 */
- "raise 15;"
- "rti;"
- :
- : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
- );
- }
- serial_putc('d');
- }
-#endif
-
- serial_putc('e');
-}
-
-BOOTROM_CALLED_FUNC_ATTR
-void initcode(ADI_BOOT_DATA *bs)
-{
- ADI_BOOT_DATA bootstruct_scratch;
-
- /* Setup NMI handler before anything else */
- program_nmi_handler();
-
- serial_init();
-
- serial_putc('A');
-
- /* If the bootstruct is NULL, then it's because we're loading
- * dynamically and not via LDR (bootrom). So set the struct to
- * some scratch space.
- */
- if (!bs)
- bs = &bootstruct_scratch;
-
- serial_putc('B');
- bool put_into_srfs = maybe_self_refresh(bs);
-
- serial_putc('C');
- uint sdivB, divB, vcoB;
- program_early_devices(bs, &sdivB, &divB, &vcoB);
-
- serial_putc('D');
- u16 vr_ctl = program_clocks(bs, put_into_srfs);
-
- serial_putc('E');
- update_serial_clocks(bs, sdivB, divB, vcoB);
-
- serial_putc('F');
- program_memory_controller(bs, put_into_srfs);
-
- serial_putc('G');
- check_hibernation(bs, vr_ctl, put_into_srfs);
-
- serial_putc('H');
- program_async_controller(bs);
-
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
- serial_putc('I');
- /* Tell the bootrom where our entry point is so that it knows
- * where to jump to when finishing processing the LDR. This
- * allows us to avoid small jump blocks in the LDR, and also
- * works around anomaly 05000389 (init address in external
- * memory causes bootrom to trigger external addressing IVHW).
- */
- if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
- bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
-#endif
-
- serial_putc('>');
- serial_putc('\n');
-
- serial_deinit();
-}
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
deleted file mode 100644
index ab7fa45075b2..000000000000
--- a/arch/blackfin/cpu/initcode.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Code for early processor initialization
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_INITCODE_H__
-#define __BFIN_INITCODE_H__
-
-#include <asm/mach-common/bits/bootrom.h>
-
-#ifndef BFIN_IN_INITCODE
-# define serial_putc(c)
-#endif
-
-#ifndef __ADSPBF60x__
-
-#ifndef CONFIG_EBIU_RSTCTL_VAL
-# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
-#endif
-#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
-# error invalid EBIU_RSTCTL value: must not set reserved bits
-#endif
-
-#ifndef CONFIG_EBIU_MBSCTL_VAL
-# define CONFIG_EBIU_MBSCTL_VAL 0
-#endif
-
-#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
-# error invalid EBIU_DDRQUE value: must not set reserved bits
-#endif
-
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_async_controller(ADI_BOOT_DATA *bs)
-{
-#ifdef BFIN_IN_INITCODE
- /*
- * We really only need to setup the async banks early if we're
- * booting out of it. Otherwise, do it later on in cpu_init.
- */
- if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
- CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
- return;
-#endif
-
- serial_putc('a');
-
-#ifndef __ADSPBF60x__
- /* Program the async banks controller. */
-#ifdef EBIU_AMGCTL
- bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
- bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
- bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
-
- serial_putc('b');
-
- /* Not all parts have these additional MMRs. */
-#ifdef EBIU_MBSCTL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-#endif
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MODE_VAL
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
-# endif
-# ifdef CONFIG_EBIU_FCTL_VAL
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
-# endif
-#endif
-
- serial_putc('c');
-
-#else /* __ADSPBF60x__ */
- /* Program the static memory controller. */
-# ifdef CONFIG_SMC_GCTL_VAL
- bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0CTL_VAL
- bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0TIM_VAL
- bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B0ETIM_VAL
- bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1CTL_VAL
- bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B1TIM_VAL
- bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1ETIM_VAL
- bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2CTL_VAL
- bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B2TIM_VAL
- bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2ETIM_VAL
- bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3CTL_VAL
- bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B3TIM_VAL
- bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3ETIM_VAL
- bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
-# endif
-
-#endif /* __ADSPBF60x__ */
- serial_putc('d');
-}
-
-#endif
diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S
deleted file mode 100644
index 0e5e59e15d6d..000000000000
--- a/arch/blackfin/cpu/interrupt.S
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * interrupt.S - trampoline default exceptions/interrupts to C handlers
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-#include <asm/ptrace.h>
-#include <asm/deferred.h>
-#include <asm/mach-common/bits/core.h>
-
-.text
-
-/* default entry point for exceptions */
-ENTRY(_trap)
- CONFIG_BFIN_SCRATCH_REG = sp;
- sp.l = LO(L1_SRAM_SCRATCH_END - 20);
- sp.h = HI(L1_SRAM_SCRATCH_END - 20);
- SAVE_ALL_SYS
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = 3; /* EVT3 space */
- sp += -12;
- call _trap_c;
- sp += 12;
-
-#ifdef CONFIG_EXCEPTION_DEFER
- CC = R0 == 0;
- IF CC JUMP .Lexit_trap;
-
- /* To avoid double faults, lower our priority to IRQ5 */
- p4.l = lo(COREMMR_BASE);
- p4.h = hi(COREMMR_BASE);
-
- r7.h = _exception_to_level5;
- r7.l = _exception_to_level5;
- [p4 + (EVT5 - COREMMR_BASE)] = r7;
-
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- */
- p5.l = _deferred_regs;
- p5.h = _deferred_regs;
- r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
- [p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
-
- r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
- [p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
-
- /* Save the state of single stepping */
- r6 = SYSCFG;
- [p5 + (deferred_regs_SYSCFG * 4)] = r6;
- /* Clear it while we handle the exception in IRQ5 mode
- * RESTORE_ALL_SYS will load it, so all we need to do is store it
- * in the right place
- */
- BITCLR(r6, SYSCFG_SSSTEP_P);
- [SP + PT_SYSCFG] = r6;
-
- /* Since we are going to clobber RETX, we need to save it */
- r6 = retx;
- [p5 + (deferred_regs_retx * 4)] = r6;
-
- /* Save the current IMASK, since we change in order to jump to level 5 */
- cli r6;
- [p5 + (deferred_regs_IMASK * 4)] = r6;
-
- /* Disable all interrupts, but make sure level 5 is enabled so
- * we can switch to that level.
- */
- r6 = 0x3f;
- sti r6;
-
- /* Clobber RETX so we don't end up back at a faulting instruction */
- [sp + PT_RETX] = r7;
-
- /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
- * clear it (re-enabling interrupts again) by the special sequence of pushing
- * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
- * exception was taken after the interrupt handler was called but before it
- * got a chance to enable global interrupts itself.
- */
- [--sp] = reti;
- sp += 4;
-
- RAISE 5;
-.Lexit_trap:
-#endif
-
-#if ANOMALY_05000257
- R7 = LC0;
- LC0 = R7;
- R7 = LC1;
- LC1 = R7;
-#endif
-
- RESTORE_ALL_SYS
- sp = CONFIG_BFIN_SCRATCH_REG;
- rtx;
-ENDPROC(_trap)
-
-#ifdef CONFIG_EXCEPTION_DEFER
-/* Deferred (IRQ5) exceptions */
-ENTRY(_exception_to_level5)
- SAVE_ALL_SYS
-
- /* Now we have to fix things up */
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- r0.l = _evt_default;
- r0.h = _evt_default;
- [p4] = r0;
- csync;
-
- p4.l = _deferred_regs;
- p4.h = _deferred_regs;
- r0 = [p4 + (deferred_regs_retx * 4)];
- [sp + PT_PC] = r0;
-
- r0 = [p4 + (deferred_regs_SYSCFG * 4)];
- [sp + PT_SYSCFG] = r0;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = 5; /* EVT5 space */
- sp += -12;
- call _trap_c;
- sp += 12;
-
- /* Restore IMASK */
- r0 = [p4 + (deferred_regs_IMASK * 4)];
- sti r0;
-
- RESTORE_ALL_SYS
-
- rti;
-ENDPROC(_exception_to_level5)
-#endif
-
-/* default entry point for interrupts */
-ENTRY(_evt_default)
- SAVE_ALL_SYS
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- sp += -12;
- call _bfin_panic;
- sp += 12;
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_evt_default)
-
-/* NMI handler */
-ENTRY(_evt_nmi)
- rtn;
-ENDPROC(_evt_nmi)
diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c
deleted file mode 100644
index abb7dc1d1ddf..000000000000
--- a/arch/blackfin/cpu/interrupts.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * U-Boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <watchdog.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags; /* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On Blackfin it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On Blackfin it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
-void enable_interrupts(void)
-{
- local_irq_restore(int_flag);
-}
-
-int disable_interrupts(void)
-{
- local_irq_save(int_flag);
- return 1;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long delay, start, stop;
- unsigned long cclk;
- cclk = (CONFIG_CCLK_HZ);
-
- while (usec > 1) {
- WATCHDOG_RESET();
-
- /*
- * how many clock ticks to delay?
- * - request(in useconds) * clock_ticks(Hz) / useconds/second
- */
- if (usec < 1000) {
- delay = (usec * (cclk / 244)) >> 12;
- usec = 0;
- } else {
- delay = (1000 * (cclk / 244)) >> 12;
- usec -= 1000;
- }
-
- asm volatile (" %0 = CYCLES;" : "=r" (start));
- do {
- asm volatile (" %0 = CYCLES; " : "=r" (stop));
- } while (stop - start < delay);
- }
-
- return;
-}
-
-#define MAX_TIM_LOAD 0xFFFFFFFF
-int timer_init(void)
-{
- bfin_write_TCNTL(0x1);
- CSYNC();
- bfin_write_TSCALE(0x0);
- bfin_write_TCOUNT(MAX_TIM_LOAD);
- bfin_write_TPERIOD(MAX_TIM_LOAD);
- bfin_write_TCNTL(0x7);
- CSYNC();
-
- timestamp = 0;
- last_time = 0;
-
- return 0;
-}
-
-/*
- * Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
- ulong milisec;
-
- /* Number of clocks elapsed */
- ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());
-
- /*
- * Find if the TCOUNT is reset
- * timestamp gives the number of times
- * TCOUNT got reset
- */
- if (clocks < last_time)
- timestamp++;
- last_time = clocks;
-
- /* Get the number of milliseconds */
- milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
- /*
- * Find the number of millisonds that
- * got elapsed before this TCOUNT cycle
- */
- milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
- return (milisec - base);
-}
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
deleted file mode 100644
index 29e7a441bcf7..000000000000
--- a/arch/blackfin/cpu/jtag-console.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * jtag-console.c - console driver over Blackfin JTAG
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <asm/blackfin.h>
-
-#ifdef DEBUG
-# define dprintf(...) serial_printf(__VA_ARGS__)
-#else
-# define dprintf(...) do { if (0) printf(__VA_ARGS__); } while (0)
-#endif
-
-static inline void dprintf_decode(const char *s, uint32_t len)
-{
- uint32_t i;
- for (i = 0; i < len; ++i)
- if (s[i] < 0x20 || s[i] >= 0x7f)
- dprintf("\\%o", s[i]);
- else
- dprintf("%c", s[i]);
-}
-
-static inline uint32_t bfin_write_emudat(uint32_t emudat)
-{
- __asm__ __volatile__("emudat = %0;" : : "d"(emudat));
- return emudat;
-}
-
-static inline uint32_t bfin_read_emudat(void)
-{
- uint32_t emudat;
- __asm__ __volatile__("%0 = emudat;" : "=d"(emudat));
- return emudat;
-}
-
-#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT
-# define CONFIG_JTAG_CONSOLE_TIMEOUT 500
-#endif
-
-/* The Blackfin tends to be much much faster than the JTAG hardware. */
-static bool jtag_write_emudat(uint32_t emudat)
-{
- static bool overflowed = false;
- ulong timeout = get_timer(0);
- while (bfin_read_DBGSTAT() & 0x1) {
- if (overflowed)
- return overflowed;
- if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT)
- overflowed = true;
- }
- overflowed = false;
- bfin_write_emudat(emudat);
- return overflowed;
-}
-/* Transmit a buffer. The format is:
- * [32bit length][actual data]
- */
-static void jtag_send(const char *raw_str, uint32_t len)
-{
- const char *cooked_str;
- uint32_t i, ex;
-
- if (len == 0)
- return;
-
- /* Ugh, need to output \r after \n */
- ex = 0;
- for (i = 0; i < len; ++i)
- if (raw_str[i] == '\n')
- ++ex;
- if (ex) {
- char *c = malloc(len + ex);
- cooked_str = c;
- for (i = 0; i < len; ++i) {
- *c++ = raw_str[i];
- if (raw_str[i] == '\n')
- *c++ = '\r';
- }
- len += ex;
- } else
- cooked_str = raw_str;
-
- dprintf("%s(\"", __func__);
- dprintf_decode(cooked_str, len);
- dprintf("\", %i)\n", len);
-
- /* First send the length */
- if (jtag_write_emudat(len))
- goto done;
-
- /* Then send the data */
- for (i = 0; i < len; i += 4) {
- uint32_t emudat =
- (cooked_str[i + 0] << 0) |
- (cooked_str[i + 1] << 8) |
- (cooked_str[i + 2] << 16) |
- (cooked_str[i + 3] << 24);
- if (jtag_write_emudat(emudat)) {
- bfin_write_emudat(0);
- goto done;
- }
- }
-
- done:
- if (cooked_str != raw_str)
- free((char *)cooked_str);
-}
-static void jtag_putc(struct stdio_dev *dev, const char c)
-{
- jtag_send(&c, 1);
-}
-static void jtag_puts(struct stdio_dev *dev, const char *s)
-{
- jtag_send(s, strlen(s));
-}
-
-static size_t inbound_len, leftovers_len;
-
-/* Lower layers want to know when jtag has data */
-static int jtag_tstc_dbg(void)
-{
- int ret = (bfin_read_DBGSTAT() & 0x2);
- if (ret)
- dprintf("%s: ret:%i\n", __func__, ret);
- return ret;
-}
-
-/* Higher layers want to know when any data is available */
-static int jtag_tstc(struct stdio_dev *dev)
-{
- return jtag_tstc_dbg() || leftovers_len;
-}
-
-/* Receive a buffer. The format is:
- * [32bit length][actual data]
- */
-static uint32_t leftovers;
-static int jtag_getc(struct stdio_dev *dev)
-{
- int ret;
- uint32_t emudat;
-
- dprintf("%s: inlen:%zu leftlen:%zu left:%x\n", __func__,
- inbound_len, leftovers_len, leftovers);
-
- /* see if any data is left over */
- if (leftovers_len) {
- --leftovers_len;
- ret = leftovers & 0xff;
- leftovers >>= 8;
- return ret;
- }
-
- /* wait for new data ! */
- while (!jtag_tstc_dbg())
- continue;
- emudat = bfin_read_emudat();
-
- if (inbound_len == 0) {
- /* grab the length */
- inbound_len = emudat;
- } else {
- /* store the bytes */
- leftovers_len = min((size_t)4, inbound_len);
- inbound_len -= leftovers_len;
- leftovers = emudat;
- }
-
- return jtag_getc(dev);
-}
-
-int drv_jtag_console_init(void)
-{
- struct stdio_dev dev;
- int ret;
-
- memset(&dev, 0x00, sizeof(dev));
- strcpy(dev.name, "jtag");
- dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
- dev.putc = jtag_putc;
- dev.puts = jtag_puts;
- dev.tstc = jtag_tstc;
- dev.getc = jtag_getc;
-
- ret = stdio_register(&dev);
- return (ret == 0 ? 1 : ret);
-}
-
-#ifdef CONFIG_UART_CONSOLE_IS_JTAG
-#include <serial.h>
-/* Since the JTAG is always available (at power on), allow it to fake a UART */
-void jtag_serial_setbrg(void)
-{
-}
-
-int jtag_serial_init(void)
-{
- return 0;
-}
-
-static struct serial_device serial_jtag_drv = {
- .name = "jtag",
- .start = jtag_serial_init,
- .stop = NULL,
- .setbrg = jtag_serial_setbrg,
- .putc = jtag_putc,
- .puts = jtag_puts,
- .tstc = jtag_tstc,
- .getc = jtag_getc,
-};
-
-void bfin_jtag_initialize(void)
-{
- serial_register(&serial_jtag_drv);
-}
-
-struct serial_device *default_serial_console(void)
-{
- return &serial_jtag_drv;
-}
-#endif
diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c
deleted file mode 100644
index 2092d9e3b6ef..000000000000
--- a/arch/blackfin/cpu/os_log.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * functions for handling OS log buffer
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-#include <common.h>
-
-#define OS_LOG_MAGIC 0xDEADBEEF
-#define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0)
-#define OS_LOG_PTR_ADDR ((char **)0x4f4)
-
-int bfin_os_log_check(void)
-{
- if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
- return 0;
- *OS_LOG_MAGIC_ADDR = 0;
- return 1;
-}
-
-void bfin_os_log_dump(void)
-{
- char *log = *OS_LOG_PTR_ADDR;
- while (*log) {
- puts(log);
- log += strlen(log) + 1;
- }
-}
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
deleted file mode 100644
index b6718d3bb5db..000000000000
--- a/arch/blackfin/cpu/reset.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * reset.c - logic for resetting the cpu
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include "cpu.h"
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1. We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1. We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifdef SWRST
- /* Wait for completion of "system" events such as cache line
- * line fills so that we avoid infinite stalls later on as
- * much as possible. This code is in L1, so it won't trigger
- * any such event after this point in time.
- */
- __builtin_bfin_ssync();
-
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
-
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
-
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- /* Seems to be fixed with newer parts though ... */
- if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
- bfin_read_SWRST();
-#endif
-
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
-#endif
-
- while (1)
-#if defined(__ADSPBF60x__)
- bfin_write_RCU0_CTL(0x1);
-#else
- /* Issue core reset */
- asm("raise 1");
-#endif
-}
-
-/* We need to trampoline ourselves up into L1 since our linker
- * does not have relaxtion support and will only generate a
- * PC relative call with a 25 bit immediate. This is not enough
- * to get us from the top of SDRAM into L1.
- */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (board_reset)
- board_reset();
- if (ANOMALY_05000353 || ANOMALY_05000386)
- while (1)
- asm("jump (%0);" : : "a" (bfin_reset));
- else
- bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
- return 0;
-}
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
deleted file mode 100644
index 823a1dfde897..000000000000
--- a/arch/blackfin/cpu/start.S
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * U-Boot - start.S Startup file for Blackfin U-Boot
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003 Metrowerks/Motorola
- * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- * Kenneth Albanowski <kjahds@kjahds.com>,
- * The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/serial.h>
-
-/* It may seem odd that we make calls to functions even though we haven't
- * relocated ourselves yet out of {flash,ram,wherever}. This is OK because
- * the "call" instruction in the Blackfin architecture is actually PC
- * relative. So we can call functions all we want and not worry about them
- * not being relocated yet.
- */
-
-.text
-ENTRY(_start)
-
- /* Set our initial stack to L1 scratch space */
- sp.l = LO(L1_SRAM_SCRATCH_END - 20);
- sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P4 - system MMR base
- * P5 - core MMR base
- */
-#ifdef CONFIG_HW_WATCHDOG
- p4.l = 0;
- p4.h = HI(SYSMMR_BASE);
-#endif
- p5.l = 0;
- p5.h = HI(COREMMR_BASE);
-
-#ifdef CONFIG_HW_WATCHDOG
- /* Program the watchdog with default timeout of ~5 seconds.
- * That should be long enough to bootstrap ourselves up and
- * then the common U-Boot code can take over.
- */
- r1 = WDDIS;
-# ifdef __ADSPBF60x__
- [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
- W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
- SSYNC;
- r0 = 0;
- r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS));
- [p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
- SSYNC;
- r1 = WDEN;
- /* fire up the watchdog - R0.L above needs to be 0x0000 */
-# ifdef __ADSPBF60x__
- [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
- W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
- SSYNC;
-#endif
-
- /* Turn on the serial for debugging the init process */
- serial_early_init
- serial_early_set_baud
-
- serial_early_puts("Init Registers");
-
- /* Disable self-nested interrupts and enable CYCLES for udelay() */
- R0 = CCEN | 0x30;
- SYSCFG = R0;
-
- /* Zero out registers required by Blackfin ABI.
- * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
- */
- r1 = 0 (x);
- /* Disable circular buffers */
- l0 = r1;
- l1 = r1;
- l2 = r1;
- l3 = r1;
- /* Disable hardware loops in case we were started by 'go' */
- lc0 = r1;
- lc1 = r1;
-
- /* Save RETX so we can pass it while booting Linux */
- r7 = RETX;
-
-#if CONFIG_MEM_SIZE
- /* Figure out where we are currently executing so that we can decide
- * how to best reprogram and relocate things. We'll pass below:
- * R4: load address of _start
- * R5: current (not load) address of _start
- */
- serial_early_puts("Find ourselves");
-
- call _get_pc;
-.Loffset:
- r1.l = .Loffset;
- r1.h = .Loffset;
- r4.l = _start;
- r4.h = _start;
- r3 = r1 - r4;
- r5 = r0 - r3;
-
- /* Inform upper layers if we had to do the relocation ourselves.
- * This allows us to detect whether we were loaded by 'go 0x1000'
- * or by the bootrom from an LDR. "R6" is "loaded_from_ldr".
- */
- r6 = 1 (x);
- cc = r4 == r5;
- if cc jump .Lnorelocate;
- r6 = 0 (x);
-
- /* Turn off caches as they require CPLBs and a CPLB miss requires
- * a software exception handler to process it. But we're about to
- * clobber any previous executing software (like U-Boot that just
- * launched a new U-Boot via 'go'), so any handler state will be
- * unreliable after the memcpy below.
- */
- serial_early_puts("Kill Caches");
- r0 = 0;
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0;
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0;
- ssync;
-
- /* In bypass mode, we don't have an LDR with an init block
- * so we need to explicitly call it ourselves. This will
- * reprogram our clocks, memory, and setup our async banks.
- */
- serial_early_puts("Program Clocks");
-
- /* if we're executing >=0x20000000, then we dont need to dma */
- r3 = 0x0;
- r3.h = 0x2000;
- cc = r5 < r3 (iu);
- if cc jump .Ldma_and_reprogram;
-#else
- r6 = 1 (x); /* fake loaded_from_ldr = 1 */
-#endif
- r0 = 0 (x); /* set bootstruct to NULL */
- call _initcode;
- jump .Lprogrammed;
-
- /* we're sitting in external memory, so dma into L1 and reprogram */
-.Ldma_and_reprogram:
- r0.l = LO(L1_INST_SRAM);
- r0.h = HI(L1_INST_SRAM);
- r1.l = __initcode_lma;
- r1.h = __initcode_lma;
- r2.l = __initcode_len;
- r2.h = __initcode_len;
- r1 = r1 - r4; /* convert r1 from load address of initcode ... */
- r1 = r1 + r5; /* ... to current (not load) address of initcode */
- p3 = r0;
- call _dma_memcpy_nocache;
- r0 = 0 (x); /* set bootstruct to NULL */
- call (p3);
-
- /* Since we reprogrammed SCLK, we need to update the serial divisor */
-.Lprogrammed:
- serial_early_set_baud
-
-#if CONFIG_MEM_SIZE
- /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
- * monitor location in the end of RAM. We know that memcpy() only
- * uses registers, so it is safe to call here. Note that this only
- * copies to external memory ... we do not start executing out of
- * it yet (see "lower to 15" below).
- */
- serial_early_puts("Relocate");
- r0 = r4;
- r1 = r5;
- r2.l = LO(CONFIG_SYS_MONITOR_LEN);
- r2.h = HI(CONFIG_SYS_MONITOR_LEN);
- call _memcpy_ASM;
-#endif
-
-.Lnorelocate:
- /* Initialize BSS section ... we know that memset() does not
- * use the BSS, so it is safe to call here. The bootrom LDR
- * takes care of clearing things for us.
- */
- serial_early_puts("Zero BSS");
- r0.l = __bss_start;
- r0.h = __bss_start;
- r1 = 0 (x);
- r2.l = __bss_len;
- r2.h = __bss_len;
- call _memset;
-
-
- /* Setup the actual stack in external memory */
- sp.h = HI(CONFIG_STACKBASE);
- sp.l = LO(CONFIG_STACKBASE);
- fp = sp;
-
- /* Now lower ourselves from the highest interrupt level to
- * the lowest. We do this by masking all interrupts but 15,
- * setting the 15 handler to ".Lenable_nested", raising the 15
- * interrupt, and then returning from the highest interrupt
- * level to the dummy "jump" until the interrupt controller
- * services the pending 15 interrupt. If executing out of
- * flash, these steps also changes the code flow from flash
- * to external memory.
- */
- serial_early_puts("Lower to 15");
- r0 = r7;
- r1 = r6;
- p1.l = .Lenable_nested;
- p1.h = .Lenable_nested;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- r7 = EVT_IVG15 (z);
- sti r7;
- raise 15;
- p3.l = .LWAIT_HERE;
- p3.h = .LWAIT_HERE;
- reti = p3;
- rti;
-
- /* Enable nested interrupts before continuing with cpu init */
-.Lenable_nested:
- cli r7;
- [--sp] = reti;
- jump.l _cpu_init_f;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(_start)
-
-LENTRY(_get_pc)
- r0 = rets;
-#if ANOMALY_05000371
- NOP;
- NOP;
- NOP;
-#endif
- rts;
-ENDPROC(_get_pc)
-
-ENTRY(_relocate_code)
- /* Fake relocate code. Setup the new stack only */
- sp = r0;
- fp = sp;
- r0 = p3;
- r1.h = 0x2000;
- r1.l = 0x10;
- jump.l _board_init_r
-ENDPROC(_relocate_code)
diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c
deleted file mode 100644
index 21760d01a7a9..000000000000
--- a/arch/blackfin/cpu/traps.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * U-Boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <kgdb.h>
-#include <linux/types.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-#include <asm/mach-common/bits/trace.h>
-#include <asm/deferred.h>
-#include "cpu.h"
-
-#ifdef CONFIG_DEBUG_DUMP
-# define ENABLE_DUMP 1
-#else
-# define ENABLE_DUMP 0
-#endif
-
-#define trace_buffer_save(x) \
- do { \
- if (!ENABLE_DUMP) \
- break; \
- (x) = bfin_read_TBUFCTL(); \
- bfin_write_TBUFCTL((x) & ~TBUFEN); \
- } while (0)
-
-#define trace_buffer_restore(x) \
- do { \
- if (!ENABLE_DUMP) \
- break; \
- bfin_write_TBUFCTL((x)); \
- } while (0);
-
-/* The purpose of this map is to provide a mapping of address<->cplb settings
- * rather than an exact map of what is actually addressable on the part. This
- * map covers all current Blackfin parts. If you try to access an address that
- * is in this map but not actually on the part, you won't get an exception and
- * reboot, you'll get an external hardware addressing error and reboot. Since
- * only the ends matter (you did something wrong and the board reset), the means
- * are largely irrelevant.
- */
-struct memory_map {
- uint32_t start, end;
- uint32_t data_flags, inst_flags;
-};
-const struct memory_map const bfin_memory_map[] = {
- { /* external memory */
- .start = 0x00000000,
- .end = 0x20000000,
- .data_flags = SDRAM_DGENERIC,
- .inst_flags = SDRAM_IGENERIC,
- },
- { /* async banks */
- .start = 0x20000000,
- .end = 0x30000000,
- .data_flags = SDRAM_EBIU,
- .inst_flags = SDRAM_INON_CHBL,
- },
- { /* everything on chip */
- .start = 0xE0000000,
- .end = 0xFFFFFFFF,
- .data_flags = L1_DMEMORY,
- .inst_flags = L1_IMEMORY,
- }
-};
-
-#ifdef CONFIG_EXCEPTION_DEFER
-unsigned int deferred_regs[deferred_regs_last];
-#endif
-
-/*
- * Handle all exceptions while running in EVT3 or EVT5
- */
-int trap_c(struct pt_regs *regs, uint32_t level)
-{
- uint32_t ret = 0;
- uint32_t trapnr = (regs->seqstat & EXCAUSE);
- unsigned long tflags;
- bool data = false;
-
- /*
- * Keep the trace buffer so that a miss here points people
- * to the right place (their code). Crashes here rarely
- * happen. If they do, only the Blackfin maintainer cares.
- */
- trace_buffer_save(tflags);
-
- switch (trapnr) {
- /* 0x26 - Data CPLB Miss */
- case VEC_CPLB_M:
-
- if (ANOMALY_05000261) {
- static uint32_t last_cplb_fault_retx;
- /*
- * Work around an anomaly: if we see a new DCPLB fault,
- * return without doing anything. Then,
- * if we get the same fault again, handle it.
- */
- if (last_cplb_fault_retx != regs->retx) {
- last_cplb_fault_retx = regs->retx;
- break;
- }
- }
-
- data = true;
- /* fall through */
-
- /* 0x27 - Instruction CPLB Miss */
- case VEC_CPLB_I_M: {
- volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
- uint32_t new_cplb_addr = 0, new_cplb_data = 0;
- static size_t last_evicted;
- size_t i;
-
-#ifdef CONFIG_EXCEPTION_DEFER
- /* This should never happen */
- if (level == 5)
- bfin_panic(regs);
-#endif
-
- new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
-
- for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
- /* if the exception is inside this range, lets use it */
- if (new_cplb_addr >= bfin_memory_map[i].start &&
- new_cplb_addr < bfin_memory_map[i].end)
- break;
- }
- if (i == ARRAY_SIZE(bfin_memory_map)) {
- printf("%cCPLB exception outside of memory map@0x%p\n",
- (data ? 'D' : 'I'), (void *)new_cplb_addr);
- bfin_panic(regs);
- } else
- debug("CPLB addr %p matches map 0x%p - 0x%p\n",
- (void *)new_cplb_addr,
- (void *)bfin_memory_map[i].start,
- (void *)bfin_memory_map[i].end);
- new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
-
- if (data) {
- CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
- CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
- } else {
- CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
- CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
- }
-
- /* find the next unlocked entry and evict it */
- i = last_evicted & 0xF;
- debug("last evicted = %zu\n", i);
- CPLB_DATA = CPLB_DATA_BASE + i;
- while (*CPLB_DATA & CPLB_LOCK) {
- debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
- i = (i + 1) & 0xF; /* wrap around */
- CPLB_DATA = CPLB_DATA_BASE + i;
- }
- CPLB_ADDR = CPLB_ADDR_BASE + i;
-
- debug("evicting entry %zu: 0x%p 0x%08X\n", i,
- (void *)*CPLB_ADDR, *CPLB_DATA);
- last_evicted = i + 1;
-
- /* need to turn off cplbs whenever we muck with the cplb table */
-#if ENDCPLB != ENICPLB
-# error cplb enable bit violates my sanity
-#endif
- uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
- bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
- *CPLB_ADDR = new_cplb_addr;
- *CPLB_DATA = new_cplb_data;
- bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
- SSYNC();
-
- /* dump current table for debugging purposes */
- CPLB_ADDR = CPLB_ADDR_BASE;
- CPLB_DATA = CPLB_DATA_BASE;
- for (i = 0; i < 16; ++i)
- debug("%2zu 0x%p 0x%08X\n", i,
- (void *)*CPLB_ADDR++, *CPLB_DATA++);
-
- break;
- }
-#ifdef CONFIG_CMD_KGDB
- /* Single step
- * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
- */
- case VEC_STEP:
- if (level == 3) {
- /* If we just returned from an interrupt, the single step
- * event is for the RTI instruction.
- */
- if (regs->retx == regs->pc)
- break;
- /* we just return if we are single stepping through IRQ5 */
- if (regs->ipend & 0x20)
- break;
- /* Otherwise, turn single stepping off & fall through,
- * which defers to IRQ5
- */
- regs->syscfg &= ~1;
- }
- /* fall through */
-#endif
- default:
-#ifdef CONFIG_CMD_KGDB
- if (level == 3) {
- /* We need to handle this at EVT5, so try again */
- bfin_dump(regs);
- ret = 1;
- break;
- }
- if (debugger_exception_handler && (*debugger_exception_handler)(regs))
- break;
-#endif
- bfin_panic(regs);
- }
-
- trace_buffer_restore(tflags);
-
- return ret;
-}
-
-#ifndef CONFIG_KALLSYMS
-const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
-{
- *caddr = addr;
- return "N/A";
-}
-#endif
-
-static void decode_address(char *buf, unsigned long address)
-{
- unsigned long sym_addr;
- void *paddr = (void *)address;
- const char *sym = symbol_lookup(address, &sym_addr);
-
- if (sym) {
- sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
- return;
- }
-
- if (!address)
- sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
- else if (address >= CONFIG_SYS_MONITOR_BASE &&
- address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
- else
- sprintf(buf, "<0x%p> /* unknown address */", paddr);
-}
-
-static char *strhwerrcause(uint16_t hwerrcause)
-{
- switch (hwerrcause) {
- case 0x02: return "system mmr error";
- case 0x03: return "external memory addressing error";
- case 0x12: return "performance monitor overflow";
- case 0x18: return "raise 5 instruction";
- default: return "undef";
- }
-}
-
-static char *strexcause(uint16_t excause)
-{
- switch (excause) {
- case 0x00 ... 0xf: return "custom exception";
- case 0x10: return "single step";
- case 0x11: return "trace buffer full";
- case 0x21: return "undef inst";
- case 0x22: return "illegal inst";
- case 0x23: return "dcplb prot violation";
- case 0x24: return "misaligned data";
- case 0x25: return "unrecoverable event";
- case 0x26: return "dcplb miss";
- case 0x27: return "multiple dcplb hit";
- case 0x28: return "emulation watchpoint";
- case 0x2a: return "misaligned inst";
- case 0x2b: return "icplb prot violation";
- case 0x2c: return "icplb miss";
- case 0x2d: return "multiple icplb hit";
- case 0x2e: return "illegal use of supervisor resource";
- default: return "undef";
- }
-}
-
-void dump(struct pt_regs *fp)
-{
- char buf[150];
- int i;
- uint16_t hwerrcause, excause;
-
- if (!ENABLE_DUMP)
- return;
-
-#ifndef CONFIG_CMD_KGDB
- /* fp->ipend is normally garbage, so load it ourself */
- fp->ipend = bfin_read_IPEND();
-#endif
-
- hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
- excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
-
- printf("SEQUENCER STATUS:\n");
- printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
- fp->seqstat, fp->ipend, fp->syscfg);
- printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
- printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
- for (i = 6; i <= 15; ++i) {
- if (fp->ipend & (1 << i)) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- printf(" physical IVG%i asserted : %s\n", i, buf);
- }
- }
- decode_address(buf, fp->rete);
- printf(" RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- printf(" RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- printf(" RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- printf(" RETS: %s\n", buf);
- /* we lie and store RETI in "pc" */
- decode_address(buf, fp->pc);
- printf(" RETI: %s\n", buf);
-
- if (fp->seqstat & EXCAUSE) {
- decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
- printf("DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
- printf("ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- printf("\nPROCESSOR STATE:\n");
- printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (unsigned long)fp);
- printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- printf("USP : %08lx ASTAT: %08lx\n",
- fp->usp, fp->astat);
-
- printf("\n");
-}
-
-static void _dump_bfin_trace_buffer(void)
-{
- char buf[150];
- int i = 0;
-
- if (!ENABLE_DUMP)
- return;
-
- printf("Hardware Trace:\n");
-
- if (bfin_read_TBUFSTAT() & TBUFCNT) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- decode_address(buf, bfin_read_TBUF());
- printf("%4i Target : %s\n", i, buf);
- decode_address(buf, bfin_read_TBUF());
- printf(" Source : %s\n", buf);
- }
- }
-}
-
-void dump_bfin_trace_buffer(void)
-{
- unsigned long tflags;
- trace_buffer_save(tflags);
- _dump_bfin_trace_buffer();
- trace_buffer_restore(tflags);
-}
-
-void bfin_dump(struct pt_regs *regs)
-{
- unsigned long tflags;
-
- trace_buffer_save(tflags);
-
- puts(
- "\n"
- "\n"
- "\n"
- "Ack! Something bad happened to the Blackfin!\n"
- "\n"
- );
- dump(regs);
- _dump_bfin_trace_buffer();
- puts("\n");
-
- trace_buffer_restore(tflags);
-}
-
-void bfin_panic(struct pt_regs *regs)
-{
- unsigned long tflags;
- trace_buffer_save(tflags);
- bfin_dump(regs);
- panic("PANIC: Blackfin internal error");
-}
diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds
deleted file mode 100644
index f407fb232752..000000000000
--- a/arch/blackfin/cpu/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * U-Boot - u-boot.lds.S
- *
- * Copyright (c) 2005-2010 Analog Device Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-#ifndef LDS_BOARD_TEXT
-# define LDS_BOARD_TEXT
-#endif
-
-/* If we don't actually load anything into L1 data, this will avoid
- * a syntax error. If we do actually load something into L1 data,
- * we'll get a linker memory load error (which is what we'd want).
- * This is here in the first place so we can quickly test building
- * for different CPU's which may lack non-cache L1 data.
- */
-#ifndef L1_DATA_A_SRAM
-# define L1_DATA_A_SRAM 0
-# define L1_DATA_A_SRAM_SIZE 0
-#endif
-#ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM L1_DATA_A_SRAM
-# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
-#endif
-
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
-# define L1_CODE_ORIGIN L1_INST_SRAM
-#else
-# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
-#endif
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
-#if CONFIG_MEM_SIZE
- ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
-# define ram_code ram
-# define ram_data ram
-#else
-# define ram_code l1_code
-# define ram_data l1_data
-#endif
- l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
- l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
- .text.pre :
- {
- arch/blackfin/cpu/start.o (.text .text.*)
-
- LDS_BOARD_TEXT
- } >ram_code
-
- .text.init :
- {
- arch/blackfin/cpu/initcode.o (.text .text.*)
- } >ram_code
- __initcode_lma = LOADADDR(.text.init);
- __initcode_len = SIZEOF(.text.init);
-
- .text :
- {
- *(.text .text.*)
- } >ram_code
-
- .rodata :
- {
- . = ALIGN(4);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- } >ram_data
-
- .data :
- {
- . = ALIGN(4);
- *(.data .data.*)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- } >ram_data
-
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- } >ram_data
-
- .text_l1 :
- {
- . = ALIGN(4);
- __stext_l1 = .;
- *(.l1.text)
- . = ALIGN(4);
- __etext_l1 = .;
- } >l1_code AT>ram_code
- __text_l1_lma = LOADADDR(.text_l1);
- __text_l1_len = SIZEOF(.text_l1);
- ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
-
- .data_l1 :
- {
- . = ALIGN(4);
- __sdata_l1 = .;
- *(.l1.data)
- *(.l1.bss)
- . = ALIGN(4);
- __edata_l1 = .;
- } >l1_data AT>ram_data
- __data_l1_lma = LOADADDR(.data_l1);
- __data_l1_len = SIZEOF(.data_l1);
- ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
-
- .bss :
- {
- . = ALIGN(4);
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss .bss.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram_data
- __bss_end = .;
- __bss_start = ADDR(.bss);
- __bss_len = SIZEOF(.bss);
- __init_end = .;
-}
diff --git a/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h b/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
deleted file mode 100644
index 3a79631fcde8..000000000000
--- a/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
+++ /dev/null
@@ -1,2377 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where: 'screen' is the pointer to the frame buffer
- * 'width' is the screen width
- * 'x' is the horizontal position
- * 'y' is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 37470
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define DEF_BFIN_LOGO_WIDTH 230
-#define DEF_BFIN_LOGO_HEIGHT 230
-#define DEF_BFIN_LOGO_PIXELS 52900
-#define DEF_BFIN_LOGO_BPP 24
-#define DEF_BFIN_LOGO_PIXEL_SIZE 3
-#define DEF_BFIN_LOGO_SIZE 158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7,
- 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86,
- 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b,
- 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b,
- 0xab, 0xd6, 0xd6, 0xb6, 0xee, 0x81, 0x5a, 0x95, 0xdb, 0xd6, 0x5d, 0x17, 0x52, 0x07, 0x60, 0xbc,
- 0xc5, 0xf5, 0xbf, 0x4f, 0x38, 0x35, 0x0d, 0x43, 0x2a, 0xdc, 0xaa, 0xb7, 0xf1, 0x3c, 0x9f, 0xa8,
- 0x90, 0x9c, 0x93, 0xf7, 0x3d, 0x9e, 0xef, 0x79, 0xde, 0xe7, 0xf7, 0xe6, 0x9c, 0x93, 0x41, 0x83,
- 0x48, 0xfd, 0x31, 0x1a, 0xdc, 0x9b, 0x9e, 0x76, 0xa7, 0x48, 0x91, 0xd2, 0x8a, 0xa0, 0x71, 0x48,
- 0xa7, 0x8c, 0x8d, 0x8d, 0x4d, 0x3a, 0x65, 0xd6, 0x43, 0xa6, 0xa6, 0xa6, 0x78, 0xde, 0xb8, 0x53,
- 0x46, 0x46, 0x46, 0x24, 0xc3, 0xa4, 0x9e, 0xa4, 0x74, 0x94, 0x82, 0x3d, 0xa0, 0x68, 0x6e, 0x6e,
- 0x6e, 0x61, 0x61, 0x61, 0x69, 0x69, 0x69, 0x6d, 0x6d, 0x6d, 0x63, 0x63, 0x63, 0x6b, 0x6b, 0x67,
- 0x6f, 0x4f, 0x77, 0xe8, 0x2a, 0x7b, 0x7b, 0x7b, 0x5b, 0x5b, 0x5b, 0xbc, 0x6a, 0x65, 0x65, 0x85,
- 0x25, 0xb1, 0x0a, 0x56, 0x24, 0xe8, 0xc5, 0xfb, 0x90, 0xf4, 0x92, 0x7a, 0x4c, 0x22, 0x40, 0x05,
- 0x69, 0xb0, 0xcd, 0xa1, 0x43, 0x87, 0x5a, 0x59, 0x59, 0x83, 0x43, 0x00, 0xc9, 0x62, 0xb1, 0x79,
- 0x3c, 0x9e, 0x48, 0x24, 0x92, 0x4a, 0xa5, 0xee, 0xee, 0xee, 0x5e, 0x5e, 0x5e, 0xde, 0xde, 0x0a,
- 0x85, 0xc2, 0x87, 0x78, 0x78, 0x7b, 0x7b, 0xcb, 0xe5, 0x9e, 0x32, 0x99, 0xcc, 0xc5, 0xc5, 0x45,
- 0x28, 0x14, 0x72, 0x38, 0x1c, 0x47, 0x47, 0x47, 0x80, 0x0d, 0xc2, 0x09, 0x7a, 0x61, 0xbf, 0x84,
- 0xf1, 0x3e, 0xed, 0xed, 0x23, 0x65, 0x38, 0x02, 0x4e, 0x80, 0x0a, 0x68, 0xc1, 0x4e, 0x41, 0x9a,
- 0x9d, 0x9d, 0x1d, 0x8b, 0xc5, 0x12, 0x08, 0x84, 0x6e, 0x6e, 0x6e, 0x00, 0x32, 0x30, 0x30, 0x30,
- 0x3c, 0x5c, 0x15, 0x13, 0x13, 0x9b, 0x9c, 0x9c, 0x9c, 0x99, 0x99, 0x99, 0x97, 0x97, 0x57, 0x58,
- 0x58, 0x58, 0xf4, 0x40, 0x05, 0x05, 0x05, 0xb9, 0xb9, 0xb9, 0x19, 0x19, 0x19, 0x89, 0x89, 0x89,
- 0x51, 0x51, 0xd1, 0x21, 0x21, 0x4a, 0x1f, 0x1f, 0x1f, 0x00, 0x0c, 0xc2, 0xd9, 0x6c, 0x36, 0x9d,
- 0x4e, 0xa7, 0x52, 0xa9, 0xe0, 0x1f, 0xae, 0x4b, 0x72, 0x4b, 0xea, 0xbf, 0x97, 0xce, 0x54, 0xe1,
- 0x87, 0x18, 0xd6, 0x99, 0x4c, 0x96, 0x50, 0x28, 0xf2, 0xf0, 0xf0, 0x08, 0x0c, 0x0c, 0x8a, 0x8e,
- 0x8e, 0x4e, 0x4d, 0x4d, 0xcd, 0xcf, 0xcf, 0x2f, 0x2f, 0x2f, 0xaf, 0xae, 0xae, 0xae, 0xa9, 0xa9,
- 0xc1, 0x0f, 0x59, 0x59, 0x59, 0x49, 0x49, 0xc9, 0xb1, 0xb1, 0xb1, 0x11, 0x11, 0x11, 0xa1, 0xa1,
- 0xa1, 0x51, 0x51, 0x51, 0x09, 0x09, 0x89, 0x19, 0x19, 0x99, 0xc5, 0xc5, 0x25, 0x58, 0xa6, 0xb6,
- 0xb6, 0x76, 0xd8, 0xb0, 0xca, 0x82, 0x82, 0xc2, 0xf4, 0xf4, 0x0c, 0x2c, 0x13, 0x12, 0x12, 0xe2,
- 0xe9, 0xe9, 0x29, 0x12, 0x39, 0x83, 0x7f, 0xd8, 0x35, 0x85, 0x42, 0x41, 0x43, 0x64, 0xd0, 0x25,
- 0x35, 0x30, 0x11, 0xac, 0x62, 0xd4, 0x46, 0xf8, 0xa4, 0xd3, 0x1d, 0x9c, 0x9c, 0x78, 0x6e, 0x6e,
- 0x32, 0x80, 0x0a, 0xd2, 0xb2, 0xb3, 0x73, 0x4a, 0x4a, 0x4a, 0x2b, 0x2a, 0x86, 0x95, 0x95, 0x95,
- 0xc5, 0xc7, 0x27, 0x20, 0x06, 0xc0, 0x2a, 0x41, 0xda, 0xef, 0xbe, 0x27, 0x98, 0x94, 0x48, 0x24,
- 0x6a, 0x75, 0x0c, 0xbc, 0xb7, 0xbc, 0xbc, 0xa2, 0xb4, 0xb4, 0x14, 0xc0, 0x27, 0x24, 0x24, 0x04,
- 0x07, 0x07, 0x23, 0x4e, 0xf0, 0xf9, 0x7c, 0x64, 0x0c, 0x78, 0xb8, 0x8e, 0xdb, 0x27, 0xb0, 0x99,
- 0xa4, 0x0c, 0x40, 0x44, 0x06, 0x00, 0x36, 0x60, 0x15, 0x08, 0x01, 0x24, 0xb9, 0x5c, 0x0e, 0xc3,
- 0x4c, 0x4e, 0x4e, 0x01, 0xa8, 0x70, 0xcb, 0xac, 0xac, 0x6c, 0x95, 0x4a, 0xe5, 0xec, 0xec, 0x8c,
- 0x9c, 0x30, 0xb0, 0x26, 0x70, 0x2c, 0x30, 0x99, 0xcc, 0x80, 0x80, 0x80, 0xf4, 0xf4, 0xf4, 0xa2,
- 0xa2, 0xe2, 0x92, 0x92, 0x92, 0xb4, 0xb4, 0xb4, 0xb0, 0xb0, 0x30, 0x34, 0x84, 0xe6, 0x50, 0xa9,
- 0xc1, 0xd2, 0x91, 0x13, 0xc8, 0xba, 0x8c, 0xd4, 0xef, 0x8a, 0xb0, 0x56, 0x04, 0x4b, 0x0c, 0xd3,
- 0xa8, 0xa7, 0x80, 0x50, 0x78, 0x78, 0x38, 0x06, 0x71, 0x8c, 0xe6, 0x30, 0xc6, 0xc8, 0xc8, 0x48,
- 0x57, 0x57, 0x57, 0x90, 0xfc, 0x47, 0x81, 0x04, 0x0f, 0x07, 0xf9, 0x88, 0x10, 0x88, 0xbe, 0x08,
- 0x15, 0x00, 0x58, 0xa9, 0x0c, 0x45, 0x13, 0xa8, 0xe6, 0x10, 0x42, 0x10, 0x9b, 0xd1, 0x19, 0x12,
- 0x5a, 0x52, 0x0f, 0x13, 0x70, 0x85, 0xb3, 0x61, 0xec, 0x86, 0xb5, 0x8a, 0xc5, 0x62, 0x0c, 0xd6,
- 0x48, 0xaa, 0x95, 0x95, 0x95, 0xa5, 0xa5, 0x65, 0xf0, 0x58, 0x00, 0x3c, 0x60, 0x53, 0xed, 0x5b,
- 0x78, 0x5b, 0x2e, 0x97, 0xab, 0x54, 0x2a, 0xcb, 0xca, 0x80, 0x6d, 0x39, 0x92, 0x86, 0xaf, 0xaf,
- 0x2f, 0x4a, 0x33, 0x74, 0x03, 0x9d, 0x21, 0xcc, 0xf6, 0x71, 0xb4, 0x4b, 0xea, 0x4f, 0x2d, 0x02,
- 0x57, 0xc4, 0x48, 0xd4, 0x41, 0xa8, 0xe5, 0x61, 0xa7, 0x18, 0xac, 0x47, 0x8d, 0x1a, 0x15, 0x1b,
- 0x1b, 0x87, 0x67, 0xf0, 0xd2, 0xe3, 0xee, 0x00, 0x9a, 0x60, 0x30, 0x18, 0x28, 0xe8, 0xd0, 0x68,
- 0x6e, 0x6e, 0x2e, 0x82, 0x07, 0xba, 0xc1, 0x66, 0xb3, 0xa9, 0x54, 0x2a, 0x99, 0x6c, 0x49, 0x75,
- 0x13, 0x81, 0x2b, 0xd8, 0x70, 0x72, 0x72, 0x52, 0x28, 0x14, 0x89, 0x89, 0x89, 0x55, 0x55, 0x55,
- 0x70, 0x3c, 0x81, 0x40, 0xf0, 0x18, 0xc7, 0xe5, 0xde, 0xde, 0x16, 0xcd, 0xc1, 0xcc, 0x8b, 0x8b,
- 0x8b, 0x87, 0x0d, 0x1b, 0x96, 0x9c, 0x9c, 0xec, 0xe7, 0xe7, 0x2f, 0x14, 0x0a, 0x11, 0x51, 0xc8,
- 0x84, 0x40, 0x4a, 0x27, 0xe0, 0x8a, 0x71, 0x19, 0xb8, 0x02, 0x15, 0x3f, 0x3f, 0x3f, 0x84, 0x49,
- 0xe0, 0x9a, 0x91, 0x91, 0x01, 0x67, 0x7b, 0x5c, 0x4d, 0xa2, 0xb8, 0x33, 0x33, 0xb3, 0xa0, 0x52,
- 0xcd, 0x29, 0x14, 0x23, 0x53, 0xd3, 0x9e, 0x1c, 0x22, 0x48, 0x87, 0x85, 0x85, 0x03, 0xda, 0xbc,
- 0xbc, 0x7c, 0x04, 0x69, 0x89, 0x44, 0x82, 0x84, 0x80, 0x72, 0x0c, 0xfd, 0x24, 0xa1, 0x7d, 0xc6,
- 0x05, 0x00, 0xe0, 0x5d, 0x88, 0x8b, 0x18, 0x7f, 0x7d, 0x7c, 0x7c, 0x80, 0x2b, 0x92, 0x24, 0xca,
- 0x76, 0xd4, 0x44, 0x8f, 0xaf, 0x51, 0x54, 0x77, 0x34, 0x16, 0x53, 0x22, 0x97, 0x4b, 0xbd, 0xbd,
- 0xb8, 0x62, 0x89, 0xb5, 0x9d, 0x9d, 0x09, 0x8e, 0x8e, 0xae, 0x28, 0xc2, 0xf3, 0x51, 0xf7, 0xa1,
- 0x22, 0x2b, 0x2d, 0x2d, 0x45, 0x69, 0x86, 0x72, 0xcc, 0xd1, 0xd1, 0x11, 0xd0, 0x92, 0xf1, 0xe0,
- 0x19, 0x17, 0x00, 0x80, 0xa1, 0xc1, 0xc1, 0x3c, 0x3c, 0x3c, 0x30, 0x0a, 0x23, 0x09, 0x04, 0x05,
- 0x05, 0x61, 0x08, 0x7e, 0xac, 0x8d, 0x9a, 0x98, 0x9b, 0xf3, 0xa4, 0xd2, 0xb0, 0x98, 0x98, 0xf8,
- 0xf4, 0xf4, 0xa8, 0xc4, 0x44, 0x45, 0x70, 0x30, 0x57, 0x2c, 0xa6, 0xd0, 0x68, 0x20, 0x59, 0x7f,
- 0x31, 0x90, 0x89, 0x94, 0x92, 0x9d, 0x9d, 0x53, 0x51, 0x51, 0x81, 0x5c, 0xed, 0xe2, 0x22, 0xb5,
- 0xb7, 0xa7, 0xa3, 0x6f, 0x8f, 0x32, 0xf7, 0x4b, 0xca, 0x20, 0x45, 0xc4, 0x57, 0xa4, 0x44, 0xb1,
- 0x58, 0xac, 0x56, 0xab, 0x4b, 0x4b, 0xcb, 0x30, 0x04, 0x03, 0xe0, 0xc7, 0xdd, 0x2e, 0xc2, 0x80,
- 0x1b, 0xfc, 0x3c, 0x37, 0xaf, 0xaa, 0xa6, 0x66, 0x04, 0xea, 0xac, 0x92, 0x92, 0xc8, 0x84, 0x04,
- 0x99, 0x8f, 0x8f, 0x1d, 0x8b, 0x65, 0xd4, 0xa3, 0xc4, 0x03, 0xa5, 0x28, 0xc4, 0xca, 0xca, 0xb4,
- 0x7d, 0x73, 0x76, 0x16, 0xa3, 0xb7, 0x88, 0x2b, 0xe4, 0xec, 0xc1, 0x33, 0x28, 0x22, 0x0f, 0x58,
- 0x59, 0x59, 0x71, 0xb9, 0xdc, 0xc0, 0xc0, 0xc0, 0xa2, 0xa2, 0xe2, 0xcc, 0xcc, 0xcc, 0x27, 0x80,
- 0x2b, 0x44, 0xb1, 0xb1, 0xf1, 0x0b, 0x0b, 0x2d, 0x19, 0x36, 0x6c, 0xca, 0xb4, 0xe9, 0xb3, 0x5e,
- 0x9d, 0x3d, 0xe1, 0xc5, 0x29, 0xc3, 0x46, 0x8c, 0x48, 0xcc, 0xc8, 0x80, 0xd9, 0x32, 0xf8, 0x3c,
- 0xa3, 0x1e, 0xf9, 0x19, 0x79, 0xa0, 0xa0, 0xa0, 0x00, 0x09, 0x21, 0x38, 0x38, 0x18, 0x61, 0x1b,
- 0x91, 0x9b, 0x0c, 0xb4, 0xcf, 0xa0, 0x60, 0x53, 0x18, 0x61, 0x01, 0x03, 0xe2, 0x62, 0x5a, 0x5a,
- 0x5a, 0x65, 0x65, 0xa5, 0x9d, 0x9d, 0xdd, 0x93, 0x68, 0x78, 0xf0, 0x60, 0xaa, 0x83, 0x03, 0x22,
- 0x41, 0xcd, 0xe8, 0xd1, 0xaf, 0xce, 0x79, 0x6d, 0xfe, 0xc2, 0x45, 0xb3, 0x5f, 0x9b, 0x3b, 0x61,
- 0xf2, 0xe4, 0x8a, 0xea, 0xea, 0xc4, 0x8c, 0x4c, 0xdf, 0x90, 0x10, 0x06, 0x9f, 0x6f, 0xd4, 0x35,
- 0x45, 0x03, 0x4e, 0x0e, 0x87, 0x53, 0x5c, 0x5c, 0x92, 0x93, 0x93, 0xe3, 0xef, 0xef, 0xcf, 0x66,
- 0x73, 0x10, 0x68, 0xc9, 0xa9, 0x83, 0x67, 0x4d, 0xd8, 0xe3, 0x30, 0x2b, 0x91, 0x48, 0x14, 0x11,
- 0x11, 0x39, 0x7c, 0x78, 0x95, 0xa7, 0xa7, 0xe7, 0x93, 0x69, 0x77, 0xf0, 0x90, 0x21, 0xf6, 0x6c,
- 0xb6, 0x3a, 0x29, 0xe9, 0xf9, 0xf1, 0xe3, 0xe7, 0xbe, 0xfe, 0xc6, 0xeb, 0xf3, 0xe6, 0xbf, 0x3c,
- 0x6b, 0xd6, 0xd8, 0x09, 0x13, 0x2b, 0x47, 0x8e, 0xcc, 0x2a, 0x28, 0x50, 0xc5, 0xc6, 0xba, 0x29,
- 0x14, 0x34, 0x16, 0x6b, 0x48, 0xd7, 0x78, 0x80, 0xe3, 0xcb, 0xdd, 0xdd, 0x1d, 0x55, 0x61, 0x4a,
- 0x4a, 0x0a, 0x22, 0x37, 0x9d, 0x4e, 0x47, 0x6d, 0x48, 0x66, 0x83, 0x67, 0x47, 0xd8, 0xd7, 0xd8,
- 0xe3, 0x30, 0x58, 0x6f, 0x6f, 0xef, 0xec, 0xec, 0xec, 0x92, 0x92, 0x92, 0x27, 0xf0, 0x19, 0xc1,
- 0xaf, 0x4d, 0x1b, 0x19, 0x39, 0xf2, 0x78, 0xf1, 0xa9, 0x69, 0xcf, 0x8f, 0x1b, 0xff, 0x97, 0x99,
- 0x33, 0x27, 0x4e, 0x99, 0x52, 0x3b, 0xe6, 0xb9, 0x92, 0xca, 0xca, 0xf4, 0xbc, 0x3c, 0x60, 0x1c,
- 0xa0, 0x52, 0x49, 0xbd, 0xbd, 0xe9, 0x3c, 0x27, 0xe3, 0x1e, 0xf9, 0x04, 0x1d, 0x8e, 0x8a, 0x8a,
- 0x2a, 0x2f, 0xd7, 0x56, 0x61, 0x42, 0xa1, 0xd0, 0xc6, 0xc6, 0xc6, 0xb4, 0xb7, 0x99, 0x31, 0x52,
- 0x06, 0x29, 0x94, 0xdb, 0x48, 0xb0, 0x7c, 0x3e, 0x5f, 0xa5, 0x52, 0x21, 0x0f, 0x78, 0x78, 0xc8,
- 0x9f, 0xd8, 0xae, 0x1f, 0x62, 0x6c, 0xcc, 0x12, 0x0a, 0xe3, 0xd3, 0xd2, 0x86, 0xd7, 0xd4, 0x54,
- 0xd5, 0xd6, 0xe6, 0x97, 0x95, 0x25, 0x65, 0x66, 0xa9, 0xe2, 0xe2, 0x7c, 0x95, 0x4a, 0xed, 0x64,
- 0x97, 0x44, 0x4c, 0x63, 0xb3, 0xcc, 0xa9, 0xd4, 0xc1, 0x5d, 0xe7, 0x0d, 0x08, 0xc1, 0x5a, 0x8b,
- 0x8a, 0x8a, 0xf2, 0xf2, 0xf2, 0x14, 0x0a, 0x05, 0x93, 0xc9, 0x44, 0xea, 0x26, 0xe7, 0x0d, 0x9e,
- 0x05, 0x01, 0x4e, 0xb8, 0x13, 0x52, 0xab, 0x4c, 0x26, 0x43, 0x82, 0xcd, 0xcf, 0x2f, 0xa0, 0xd1,
- 0x68, 0x4f, 0xac, 0x75, 0x10, 0xcb, 0x14, 0x0a, 0x22, 0xe2, 0xe3, 0xd3, 0x73, 0xf3, 0x62, 0x53,
- 0x52, 0x03, 0x23, 0x22, 0x64, 0xbe, 0x3e, 0x4e, 0x2e, 0x12, 0x5b, 0x0e, 0x7b, 0x28, 0xcd, 0xc6,
- 0xc4, 0xc2, 0x42, 0xcb, 0xea, 0x43, 0x0e, 0x1f, 0xf4, 0x1c, 0x83, 0x42, 0x75, 0x75, 0xb5, 0x5a,
- 0xad, 0x16, 0x8b, 0xc5, 0xe8, 0x36, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x51, 0x73, 0xb1, 0x58,
- 0xac, 0x80, 0x80, 0x80, 0xd2, 0xd2, 0x32, 0xa5, 0x52, 0xf9, 0xc4, 0x22, 0xc1, 0xa0, 0xce, 0x54,
- 0x40, 0x77, 0x72, 0x52, 0x84, 0x84, 0xf8, 0x84, 0x84, 0x88, 0xe5, 0x72, 0x3b, 0x27, 0xae, 0x85,
- 0x0d, 0xd5, 0x18, 0xe0, 0xc1, 0x2d, 0x1f, 0x81, 0x3d, 0x13, 0x13, 0x13, 0xe2, 0xd2, 0x06, 0x3f,
- 0x3f, 0x3f, 0x6c, 0x02, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x29, 0x14, 0x8a, 0x40, 0x20, 0x8c,
- 0x8e, 0x8e, 0x06, 0xb1, 0x02, 0x81, 0xe0, 0x49, 0xb6, 0x8e, 0xca, 0xcb, 0xd2, 0xd6, 0x96, 0x21,
- 0xe0, 0x5b, 0x3b, 0x38, 0x18, 0x0d, 0xe8, 0x93, 0x35, 0x0e, 0x87, 0x53, 0x57, 0x37, 0x3a, 0x2e,
- 0x2e, 0xce, 0xc5, 0xc5, 0x05, 0x36, 0x4b, 0xce, 0x74, 0x19, 0xb6, 0xb0, 0x73, 0xb1, 0x8b, 0x6d,
- 0x6c, 0x68, 0xae, 0xae, 0xae, 0xa9, 0x5a, 0xa5, 0x3d, 0xa1, 0x49, 0xad, 0xae, 0x3d, 0xd0, 0x4e,
- 0x05, 0x0c, 0x14, 0x33, 0x1c, 0x71, 0x59, 0x59, 0x59, 0x85, 0x85, 0x85, 0x84, 0xcd, 0x62, 0xbc,
- 0x20, 0x27, 0x0d, 0x0c, 0x58, 0x44, 0x88, 0x45, 0x09, 0xe3, 0xed, 0xad, 0x40, 0x82, 0x8d, 0x88,
- 0x88, 0x7c, 0x8c, 0x67, 0xbc, 0x3c, 0x1e, 0x61, 0x13, 0x24, 0x12, 0x49, 0x55, 0xd5, 0x08, 0x8c,
- 0x11, 0x22, 0x91, 0x88, 0x4a, 0xa5, 0x1a, 0xf7, 0x56, 0xa6, 0x91, 0x32, 0x0c, 0x11, 0xf3, 0x5a,
- 0xb0, 0xa6, 0xe0, 0xe0, 0xe0, 0xe2, 0xe2, 0x62, 0x5f, 0x5f, 0xdf, 0x3f, 0xe3, 0x90, 0x6a, 0x6d,
- 0x6d, 0x9d, 0x9d, 0x9d, 0x0d, 0xa7, 0x95, 0xcb, 0xe5, 0x38, 0xfa, 0x70, 0xd0, 0xfd, 0x19, 0xb7,
- 0x82, 0xd4, 0xa3, 0x08, 0xc4, 0x5a, 0x5a, 0x5a, 0xf2, 0x78, 0xbc, 0xc8, 0xc8, 0x28, 0x78, 0xac,
- 0x44, 0xe2, 0xf2, 0xb4, 0x7b, 0x34, 0x10, 0xc1, 0x54, 0x71, 0xac, 0x55, 0x54, 0x54, 0xe0, 0xb8,
- 0x43, 0xac, 0x45, 0xfd, 0x45, 0x06, 0x03, 0x43, 0x15, 0x31, 0x13, 0xeb, 0xec, 0xec, 0x9c, 0x90,
- 0x90, 0x90, 0x93, 0x93, 0x03, 0xb3, 0x7d, 0xda, 0x3d, 0x1a, 0xa0, 0x9c, 0x9c, 0x9c, 0x0a, 0x0b,
- 0x8b, 0x62, 0x63, 0xe3, 0x9c, 0x9d, 0xc5, 0xb0, 0x5c, 0x32, 0x18, 0x18, 0xaa, 0xb0, 0x67, 0x6d,
- 0x6c, 0x6c, 0x50, 0x76, 0xa5, 0x77, 0xca, 0xca, 0xca, 0xfa, 0x69, 0xf7, 0x68, 0x80, 0xb2, 0xb4,
- 0xa4, 0xc4, 0xc6, 0xc6, 0xe2, 0xa0, 0x23, 0x2e, 0x3f, 0x27, 0x27, 0x66, 0x0d, 0x52, 0xc4, 0x44,
- 0x81, 0xad, 0xad, 0xad, 0x87, 0x87, 0x47, 0x4e, 0x4e, 0x6e, 0x62, 0x62, 0xe2, 0x9f, 0x77, 0x32,
- 0x13, 0xdb, 0x82, 0x60, 0x80, 0x28, 0x1e, 0x12, 0x12, 0xc2, 0x66, 0xb3, 0xc9, 0x19, 0x03, 0x83,
- 0x14, 0xf6, 0x32, 0x8a, 0x14, 0x7b, 0x7b, 0x7b, 0x85, 0x42, 0x51, 0x50, 0x50, 0x10, 0x1d, 0xad,
- 0x7e, 0xda, 0x3d, 0xfa, 0xaf, 0x24, 0x14, 0x0a, 0xf3, 0xf2, 0xf2, 0x63, 0x62, 0x62, 0xf0, 0x03,
- 0x85, 0x42, 0xf9, 0xf3, 0x1e, 0x7d, 0xa4, 0x1e, 0x26, 0x10, 0x4b, 0x9c, 0x00, 0xe3, 0xef, 0xef,
- 0x0f, 0x77, 0x0a, 0x0f, 0x57, 0xfd, 0xce, 0x0a, 0x80, 0xc0, 0xc2, 0xc2, 0x94, 0x42, 0x31, 0xb6,
- 0xb0, 0x18, 0xf4, 0xc7, 0x39, 0xd8, 0x60, 0x23, 0x23, 0x1b, 0x3a, 0xdd, 0x45, 0x26, 0xf3, 0x0b,
- 0x0c, 0xf4, 0xf6, 0xf7, 0x67, 0x70, 0xb9, 0xc6, 0x03, 0xba, 0xae, 0x1c, 0xf1, 0x95, 0xc8, 0x36,
- 0x08, 0x39, 0x88, 0x3a, 0xe4, 0x47, 0x09, 0x86, 0x27, 0xe2, 0x9c, 0x58, 0x26, 0x93, 0x85, 0x91,
- 0xb4, 0xb4, 0xb4, 0x34, 0x28, 0x28, 0xa8, 0xef, 0xe5, 0x8d, 0xcd, 0xcd, 0xed, 0xb9, 0x5c, 0x81,
- 0x9b, 0x9b, 0x58, 0xee, 0x21, 0x90, 0x4a, 0x81, 0xd9, 0x1f, 0xc2, 0x2d, 0xb8, 0xa2, 0xd0, 0x68,
- 0x7e, 0xca, 0xd0, 0xca, 0xea, 0x91, 0x53, 0x67, 0xcc, 0x18, 0x3f, 0x71, 0x52, 0x4e, 0x41, 0x01,
- 0x97, 0xcf, 0x1f, 0xdc, 0xcf, 0x37, 0xc7, 0xe6, 0xc0, 0x60, 0xf3, 0xf3, 0xf3, 0x31, 0x64, 0x90,
- 0x73, 0x5c, 0x06, 0x29, 0xec, 0xe2, 0xa1, 0x43, 0x87, 0xb2, 0xd9, 0x9c, 0xb0, 0xb0, 0x30, 0x10,
- 0x8b, 0x1d, 0xfd, 0x3b, 0xcb, 0x1b, 0x19, 0xd1, 0x1c, 0x1d, 0x65, 0x3e, 0xbe, 0x11, 0x71, 0xf1,
- 0xa9, 0xd9, 0x39, 0xf1, 0x29, 0xa9, 0x52, 0x4f, 0x4f, 0xf3, 0x81, 0x5e, 0xa7, 0x40, 0xdc, 0x75,
- 0x56, 0x77, 0xe7, 0x58, 0xf8, 0x2a, 0xde, 0x4a, 0x19, 0x19, 0x39, 0x79, 0xea, 0xd4, 0xd9, 0xaf,
- 0xcd, 0x1d, 0x37, 0x61, 0x92, 0x4c, 0xee, 0x69, 0xd4, 0xcf, 0x92, 0xdf, 0xc7, 0xc7, 0x07, 0x83,
- 0x85, 0x52, 0xa9, 0x64, 0xb1, 0xd8, 0xe4, 0x1c, 0x97, 0xe1, 0x89, 0x20, 0x96, 0xc3, 0xe1, 0x22,
- 0x0f, 0x80, 0x58, 0x99, 0x4c, 0xf6, 0x28, 0x6b, 0x59, 0x52, 0xa9, 0x6e, 0x5e, 0x5e, 0x29, 0x59,
- 0x59, 0xb5, 0x63, 0xc6, 0x0c, 0x1f, 0x39, 0x32, 0x20, 0x34, 0x74, 0xa8, 0x95, 0xd5, 0xa3, 0x7f,
- 0xc6, 0x0a, 0x3e, 0xa9, 0x36, 0x36, 0x5c, 0x27, 0x27, 0x4f, 0x2f, 0x2f, 0x55, 0x44, 0x44, 0x4c,
- 0x6c, 0x6c, 0x58, 0x78, 0xb8, 0xbb, 0xbb, 0x3b, 0x8f, 0xc7, 0x83, 0x31, 0x82, 0x5b, 0x3b, 0x3a,
- 0xbd, 0xa8, 0xb4, 0x74, 0xd6, 0x9c, 0x39, 0xf5, 0x93, 0x5e, 0xe4, 0x8b, 0x44, 0xfd, 0xf2, 0x49,
- 0xbc, 0x09, 0x36, 0x44, 0xad, 0x56, 0xf3, 0xf9, 0x02, 0x2b, 0x2b, 0x2b, 0x72, 0x8e, 0xcb, 0xc0,
- 0xa4, 0x23, 0x56, 0xa5, 0x52, 0x95, 0x94, 0x94, 0xb8, 0xb8, 0x48, 0x7b, 0x5d, 0x0c, 0xcc, 0x58,
- 0x53, 0xa9, 0x60, 0x4c, 0x20, 0x10, 0xa0, 0x0c, 0xb7, 0xb2, 0xb6, 0xc6, 0x8a, 0x0e, 0x6c, 0x76,
- 0x74, 0x7c, 0xfc, 0xc8, 0xba, 0xba, 0xe1, 0x35, 0x35, 0x9e, 0xfe, 0xfe, 0x26, 0x8f, 0xf6, 0xd9,
- 0x2e, 0x9a, 0x53, 0xf8, 0xfa, 0x96, 0x95, 0x57, 0xbc, 0xfc, 0xca, 0x5f, 0x5f, 0x7f, 0x7d, 0xde,
- 0xc2, 0x85, 0x8b, 0x16, 0x2e, 0x5a, 0xbc, 0x60, 0xd1, 0xa2, 0x37, 0xe6, 0xcd, 0x7b, 0x75, 0xf6,
- 0x9c, 0xb1, 0xe3, 0xc6, 0x85, 0x28, 0x95, 0x54, 0x2a, 0xd5, 0xd6, 0xde, 0x3e, 0xaf, 0xa8, 0x68,
- 0xd6, 0xec, 0x39, 0x25, 0x95, 0x95, 0xfd, 0xf2, 0x70, 0x14, 0x5c, 0x20, 0x36, 0x25, 0x25, 0x45,
- 0x22, 0x91, 0x10, 0x51, 0xf6, 0xd1, 0xd7, 0x25, 0xf5, 0xbf, 0x2f, 0x3d, 0x62, 0x23, 0x30, 0x98,
- 0x3a, 0x3b, 0x3b, 0xf7, 0x5c, 0x06, 0x36, 0xe5, 0x21, 0x97, 0xe7, 0x17, 0x14, 0x00, 0xa7, 0x49,
- 0x93, 0x26, 0x3f, 0xf7, 0xfc, 0x0b, 0x45, 0xc5, 0x25, 0xd1, 0xd1, 0x6a, 0x1a, 0x8d, 0x66, 0x6e,
- 0x61, 0x11, 0x1c, 0x16, 0x56, 0x33, 0x7a, 0x74, 0x4e, 0x51, 0x11, 0x1b, 0xb1, 0xf3, 0xf7, 0xcc,
- 0x10, 0x6d, 0x65, 0x66, 0x65, 0x81, 0xcc, 0xbf, 0x37, 0x34, 0xac, 0x5e, 0xb5, 0x7a, 0xfd, 0xba,
- 0x0d, 0xff, 0xd4, 0xea, 0xff, 0xf0, 0x67, 0xc3, 0x86, 0x0f, 0xd7, 0xae, 0xfd, 0x60, 0xc5, 0x8a,
- 0x15, 0x00, 0x38, 0x27, 0x27, 0xc7, 0xde, 0xde, 0xde, 0x91, 0xc1, 0x2c, 0x1f, 0x3e, 0x1c, 0x09,
- 0x41, 0xda, 0x9f, 0xeb, 0x77, 0xd0, 0x87, 0xdc, 0xdc, 0xdc, 0xec, 0xec, 0x6c, 0x77, 0x77, 0x0f,
- 0x3b, 0x3b, 0x7b, 0x72, 0x56, 0xd6, 0xc0, 0x44, 0x10, 0xcb, 0xe5, 0x3a, 0x81, 0xd8, 0xa2, 0xa2,
- 0xa2, 0x9e, 0xe7, 0x19, 0x62, 0x77, 0x2b, 0x7c, 0x7c, 0xa6, 0x4e, 0x9b, 0xf6, 0xee, 0xdf, 0x1b,
- 0x56, 0xaf, 0x5e, 0xb3, 0x4e, 0xab, 0xf5, 0xab, 0xd7, 0xac, 0x05, 0x72, 0x63, 0xc6, 0x8c, 0xe1,
- 0x72, 0xb9, 0x14, 0x6b, 0x6b, 0x95, 0x5a, 0x9d, 0x55, 0x58, 0x24, 0xf7, 0xf7, 0x37, 0xea, 0xd3,
- 0xd0, 0xcc, 0xcd, 0xcd, 0x73, 0xf3, 0xf2, 0x1a, 0x1a, 0xde, 0xfb, 0xe8, 0xa3, 0x7f, 0x6e, 0xdd,
- 0xfa, 0xc5, 0xb7, 0xdf, 0x7c, 0xbb, 0x7b, 0xf7, 0xee, 0xbd, 0x7b, 0xf7, 0xee, 0xdb, 0xb7, 0x0f,
- 0x7f, 0xef, 0xd9, 0xbd, 0x7b, 0xe7, 0x8e, 0x1d, 0xdb, 0xb7, 0x6f, 0xff, 0xf4, 0xb3, 0x4d, 0x0d,
- 0x0d, 0x0d, 0x59, 0x59, 0x39, 0xe8, 0x18, 0x83, 0xc5, 0xca, 0x29, 0x2c, 0x8c, 0x4a, 0x4c, 0x34,
- 0xeb, 0x8f, 0xcd, 0xaa, 0xd5, 0x31, 0x85, 0x85, 0x45, 0x08, 0xb4, 0x8e, 0x8e, 0x8e, 0x68, 0x94,
- 0x24, 0xd6, 0x90, 0xa4, 0x4f, 0x6c, 0x01, 0xca, 0x73, 0x2e, 0xb7, 0xdb, 0x02, 0x70, 0xdd, 0x17,
- 0xa7, 0x4c, 0x59, 0xbb, 0x76, 0xed, 0xd6, 0xad, 0x5b, 0x77, 0xee, 0xdc, 0x09, 0xb6, 0xf6, 0xef,
- 0xd3, 0x6a, 0xe7, 0xae, 0x5d, 0x9b, 0x3f, 0xdf, 0x3c, 0x7d, 0xc6, 0x0c, 0x07, 0x07, 0x07, 0x3a,
- 0x83, 0xe1, 0x19, 0x10, 0xe8, 0x2c, 0x93, 0x0d, 0xe9, 0xf3, 0x3c, 0xf0, 0xb4, 0xf4, 0xf4, 0xf7,
- 0x97, 0x2f, 0xff, 0xfa, 0xeb, 0xaf, 0x0f, 0x35, 0x36, 0x36, 0x35, 0x35, 0x9d, 0x38, 0x71, 0xe2,
- 0xf4, 0xe9, 0xd3, 0x67, 0xce, 0x9c, 0x39, 0x8b, 0x3f, 0xa7, 0xcf, 0x9c, 0x3a, 0x75, 0xea, 0xc4,
- 0x89, 0x93, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0xc3, 0x87, 0x77, 0x7c, 0xfb, 0xed, 0xd2, 0x65, 0xcb,
- 0x94, 0xca, 0x50, 0xc0, 0x66, 0x4b, 0xa7, 0xfb, 0x84, 0x84, 0xd8, 0x31, 0x99, 0x8f, 0xbe, 0x51,
- 0x0a, 0x85, 0x4f, 0x59, 0x59, 0x79, 0x60, 0x60, 0x20, 0x71, 0x82, 0x37, 0x59, 0x7c, 0x19, 0x92,
- 0xba, 0x11, 0x8b, 0x8c, 0xaa, 0xff, 0xea, 0x50, 0x4b, 0xcb, 0xbc, 0xfc, 0x7c, 0x8c, 0xda, 0xfb,
- 0xf7, 0x1f, 0xf8, 0xe1, 0x87, 0x1f, 0xce, 0x9d, 0x3d, 0x77, 0xe1, 0xfc, 0x85, 0x4b, 0x17, 0x2f,
- 0x35, 0x5f, 0x6e, 0xbe, 0x74, 0xe9, 0xd2, 0xb9, 0x33, 0x67, 0x41, 0xd7, 0xcc, 0x99, 0x33, 0x11,
- 0x1d, 0x8d, 0xcd, 0xcd, 0x8d, 0x7a, 0xdc, 0x77, 0x48, 0x5f, 0x48, 0xa7, 0xcb, 0x97, 0x2f, 0xc7,
- 0xf2, 0x17, 0x2e, 0x5c, 0xb8, 0x7a, 0xf5, 0x6a, 0x6b, 0x6b, 0x6b, 0xfb, 0xcd, 0x9b, 0x37, 0x35,
- 0xd0, 0x2d, 0xfc, 0x7b, 0xb3, 0xfd, 0x66, 0x7b, 0x7b, 0x7b, 0x6b, 0x6b, 0xdb, 0xb5, 0x6b, 0xd7,
- 0x5b, 0xae, 0x5c, 0x39, 0x7b, 0xf6, 0xec, 0xc1, 0x83, 0x07, 0x17, 0x2c, 0x58, 0x88, 0xe3, 0x45,
- 0x7b, 0x17, 0x05, 0x33, 0x33, 0x53, 0x4b, 0xcb, 0x47, 0xdf, 0x28, 0x91, 0x48, 0x54, 0x55, 0x35,
- 0x22, 0x3c, 0x3c, 0xdc, 0xc9, 0xc9, 0x89, 0xb8, 0xcd, 0xd1, 0xc0, 0xff, 0x83, 0x48, 0xfd, 0x8f,
- 0xa9, 0x6f, 0x8f, 0x95, 0x48, 0x5c, 0xd6, 0xac, 0x5e, 0x7b, 0xfc, 0xd8, 0xf1, 0xcb, 0x97, 0x9b,
- 0x5b, 0xdb, 0xda, 0x6f, 0xdd, 0xba, 0xd5, 0xd1, 0xd1, 0x71, 0xfb, 0xf6, 0xed, 0x3b, 0x9d, 0xc2,
- 0x4f, 0x00, 0x0e, 0xdc, 0x8e, 0x1f, 0x37, 0xbe, 0xef, 0x1b, 0x71, 0xd0, 0x68, 0xb6, 0xd3, 0xa6,
- 0x4f, 0x87, 0xa9, 0x02, 0xcb, 0x3b, 0x77, 0xef, 0xde, 0xbb, 0x7f, 0xff, 0xff, 0x7b, 0x08, 0x4f,
- 0xdd, 0xbf, 0x7f, 0xff, 0xde, 0xbd, 0x7b, 0x78, 0xf7, 0x5b, 0x9a, 0x5b, 0x2d, 0x2d, 0x2d, 0xfb,
- 0xf7, 0xef, 0x2f, 0x29, 0x29, 0x1d, 0xc0, 0x0d, 0x94, 0xe8, 0x74, 0x7a, 0x4d, 0x4d, 0x6d, 0x74,
- 0x74, 0x34, 0x42, 0x8e, 0x95, 0x95, 0x15, 0x49, 0xac, 0x21, 0xa9, 0x8f, 0x1c, 0x8b, 0x82, 0x2b,
- 0x2d, 0x2d, 0x0d, 0xc3, 0x74, 0x7b, 0xfb, 0xcd, 0x3b, 0x77, 0xee, 0xde, 0xef, 0x0d, 0x33, 0xe8,
- 0xee, 0xbd, 0x7b, 0xf0, 0xc3, 0x90, 0x90, 0x90, 0x3e, 0x5a, 0x89, 0x8a, 0x8a, 0x3e, 0x78, 0xb0,
- 0xf1, 0x97, 0x8e, 0x8e, 0x5e, 0xdf, 0xa1, 0x57, 0x01, 0xec, 0xab, 0x57, 0xaf, 0x6d, 0xde, 0xbc,
- 0x05, 0x25, 0x7f, 0x7f, 0x37, 0xca, 0xcc, 0xcc, 0xac, 0xae, 0x6e, 0x74, 0x6c, 0x6c, 0x2c, 0x2c,
- 0xda, 0xda, 0xda, 0x9a, 0x24, 0xd6, 0x90, 0xd4, 0x07, 0xb1, 0x54, 0x2a, 0x75, 0xe9, 0xd2, 0x65,
- 0x9a, 0x5b, 0xb7, 0x08, 0x56, 0xf1, 0xf7, 0xc9, 0x93, 0x27, 0x8f, 0x1e, 0x3d, 0x8a, 0x31, 0xbd,
- 0x1b, 0xbd, 0x77, 0xef, 0xde, 0x9d, 0x30, 0x71, 0xe2, 0xc3, 0x6c, 0x16, 0x2e, 0x37, 0x79, 0xf2,
- 0xe4, 0xd6, 0xb6, 0xb6, 0x6e, 0xc4, 0xc3, 0x4e, 0x31, 0xfa, 0x6f, 0xdb, 0xb6, 0xed, 0xe3, 0x8f,
- 0x3f, 0xfe, 0xf2, 0xcb, 0x2f, 0xcf, 0x9f, 0x3f, 0x8f, 0x67, 0xba, 0x1d, 0x0b, 0x97, 0x2f, 0x5f,
- 0xae, 0xaf, 0xaf, 0x1f, 0x00, 0x72, 0xa8, 0x0a, 0xe3, 0xe3, 0xe3, 0xc5, 0x62, 0x31, 0x79, 0x3d,
- 0x82, 0x81, 0xa9, 0x0f, 0x62, 0x51, 0x52, 0x1d, 0x39, 0x72, 0x84, 0x18, 0xc1, 0x7f, 0xfe, 0xf9,
- 0xe7, 0x29, 0x53, 0xa6, 0x04, 0x05, 0x05, 0xf9, 0xf9, 0xf9, 0x25, 0x26, 0x26, 0xbe, 0xf3, 0xce,
- 0x3b, 0xd7, 0xaf, 0x5f, 0xd7, 0xa7, 0xeb, 0xd0, 0xa1, 0x43, 0x52, 0x69, 0xef, 0x73, 0xb9, 0xc0,
- 0x06, 0x56, 0x09, 0xaa, 0xf5, 0x97, 0xc7, 0xa0, 0x3f, 0x77, 0xee, 0x5c, 0x95, 0x4a, 0xe5, 0xea,
- 0xea, 0x8a, 0xd8, 0xe9, 0xea, 0xe6, 0xa6, 0x56, 0xab, 0x97, 0x2e, 0x5d, 0x8a, 0xd8, 0xd0, 0xc5,
- 0x69, 0xef, 0xdc, 0x39, 0x70, 0xe0, 0xc0, 0x00, 0xae, 0xe2, 0x19, 0x33, 0xe6, 0x39, 0x92, 0x58,
- 0x83, 0x94, 0x3e, 0xb1, 0xdd, 0xe6, 0x63, 0x99, 0x4c, 0x26, 0x40, 0x05, 0x36, 0xbf, 0xfc, 0xf2,
- 0xcb, 0xd8, 0xb1, 0x63, 0xb1, 0xeb, 0x75, 0xab, 0xd0, 0x68, 0xb4, 0x89, 0x13, 0x27, 0xa2, 0x60,
- 0xd2, 0xa1, 0x85, 0x88, 0xeb, 0xe7, 0xe7, 0xdf, 0x6b, 0x13, 0x3e, 0x3e, 0xbe, 0x27, 0x4f, 0x9c,
- 0xd4, 0xb7, 0x65, 0xa4, 0x5f, 0xe0, 0x6a, 0x6b, 0x6b, 0x4b, 0xcc, 0x3b, 0x71, 0xf9, 0xfc, 0x89,
- 0x93, 0x27, 0x97, 0x57, 0x54, 0x48, 0x5d, 0x5d, 0x97, 0x2c, 0x59, 0x82, 0x9c, 0xac, 0x0f, 0x6d,
- 0x5b, 0xdb, 0x4d, 0x77, 0x77, 0xf7, 0x7e, 0x6d, 0x14, 0x3c, 0xb9, 0x33, 0x15, 0x10, 0xa7, 0x76,
- 0x53, 0xc9, 0x54, 0x60, 0x48, 0xd2, 0x27, 0xb6, 0xf3, 0x33, 0xaf, 0xdf, 0x2e, 0x99, 0x61, 0xb3,
- 0xd9, 0x04, 0x93, 0x1b, 0x37, 0x6e, 0x84, 0x0d, 0x0e, 0xea, 0xcc, 0x09, 0x2f, 0xd4, 0x4f, 0x58,
- 0xb0, 0x70, 0x71, 0x6a, 0x7a, 0x86, 0x25, 0x85, 0xb2, 0x72, 0xe5, 0x4a, 0x7d, 0x33, 0x0c, 0x08,
- 0x08, 0x20, 0x56, 0x1c, 0xdc, 0x79, 0x86, 0x80, 0xf6, 0x86, 0x03, 0x9d, 0xd3, 0x4a, 0xc1, 0xc1,
- 0xc1, 0x3f, 0xb7, 0xb4, 0xe8, 0x96, 0x04, 0xba, 0xc8, 0x00, 0x3c, 0x1e, 0x4f, 0xd7, 0x90, 0xc8,
- 0xc5, 0x65, 0xd9, 0xfb, 0xcb, 0xd7, 0xad, 0x5f, 0x5f, 0x3f, 0x79, 0x32, 0x5f, 0x20, 0xd8, 0xb5,
- 0x6b, 0x57, 0xb7, 0xf0, 0xf0, 0xe6, 0x9b, 0x4b, 0xfa, 0xb5, 0x51, 0x36, 0x36, 0x36, 0x64, 0xe5,
- 0x65, 0xa8, 0x7a, 0x40, 0xac, 0xf6, 0x53, 0xda, 0xd2, 0xd2, 0x32, 0x7d, 0x37, 0x03, 0xb1, 0xa8,
- 0xd9, 0x01, 0xd8, 0xf4, 0xe9, 0xd3, 0x89, 0x1b, 0x74, 0xdb, 0xd9, 0xdb, 0xbf, 0x31, 0x7f, 0xc1,
- 0x86, 0x0f, 0x3f, 0x5a, 0xb9, 0x6a, 0x8d, 0x8f, 0xaf, 0x2f, 0x12, 0x02, 0xec, 0xb7, 0x1b, 0xb1,
- 0x46, 0xc6, 0xc6, 0x0c, 0x2e, 0x57, 0xee, 0xe7, 0xe7, 0x15, 0x14, 0xc4, 0x15, 0x89, 0x2c, 0x28,
- 0x94, 0xd0, 0xd0, 0xd0, 0xf6, 0xb6, 0xdf, 0xc6, 0x7a, 0x1c, 0x05, 0x33, 0x66, 0xcc, 0xd0, 0xef,
- 0x03, 0x85, 0x62, 0x55, 0x56, 0x31, 0x6c, 0xe5, 0xaa, 0xd5, 0x6b, 0xd6, 0x7e, 0x10, 0xaa, 0x52,
- 0xe5, 0xe6, 0xe6, 0xea, 0x47, 0x08, 0x74, 0x60, 0xcb, 0x96, 0x2d, 0xfd, 0xda, 0x28, 0x0e, 0x87,
- 0xa3, 0x3f, 0xbb, 0x45, 0xce, 0xc7, 0x1a, 0x92, 0xf4, 0xcf, 0x2b, 0x28, 0x2b, 0x2b, 0xd3, 0xbf,
- 0x9f, 0x21, 0xe1, 0xb1, 0x18, 0xa3, 0xeb, 0xea, 0xea, 0x88, 0x67, 0xc0, 0x6d, 0x76, 0x4e, 0x2e,
- 0xc0, 0x5a, 0xbf, 0xe1, 0xc3, 0x9a, 0x51, 0xa3, 0x30, 0xac, 0x23, 0xe8, 0x76, 0x23, 0x76, 0x28,
- 0x85, 0x12, 0x1e, 0x13, 0x53, 0x5e, 0x55, 0x35, 0xbc, 0xb6, 0xb6, 0xb0, 0xbc, 0x22, 0x28, 0x5c,
- 0x15, 0x19, 0x1d, 0xad, 0x9f, 0x4e, 0x9b, 0x9b, 0x9b, 0x93, 0x92, 0x92, 0xba, 0x75, 0x83, 0xc1,
- 0x64, 0xd6, 0x4f, 0x98, 0xf8, 0x8f, 0x7f, 0xac, 0x4a, 0xcb, 0xce, 0x41, 0x1a, 0x41, 0x89, 0xa7,
- 0x6f, 0xb3, 0xfb, 0xf6, 0xef, 0xef, 0xd7, 0x46, 0x49, 0x24, 0x2e, 0x15, 0x15, 0xc3, 0xc8, 0x4b,
- 0x14, 0x0d, 0x52, 0x7a, 0xe7, 0x6e, 0x85, 0x97, 0x97, 0x97, 0x2b, 0x14, 0x3e, 0xba, 0x97, 0x58,
- 0x2c, 0x56, 0x5b, 0x5b, 0x7b, 0x47, 0x47, 0x47, 0x6d, 0x6d, 0xad, 0xee, 0x49, 0x07, 0x07, 0xc7,
- 0xf1, 0xf5, 0x13, 0x40, 0xec, 0xe2, 0x25, 0x7f, 0xa3, 0xd3, 0xe9, 0x2b, 0x56, 0xac, 0x20, 0xa0,
- 0xea, 0xe8, 0xb8, 0x4d, 0x10, 0x8b, 0x3c, 0xc0, 0xe1, 0xf3, 0xfd, 0x42, 0x42, 0x62, 0x53, 0x52,
- 0xb2, 0x0a, 0x0b, 0xe3, 0x92, 0x53, 0xa2, 0xe2, 0xe2, 0x5a, 0x5b, 0x5b, 0x75, 0xf8, 0xfd, 0xf4,
- 0xd3, 0x4f, 0xbd, 0xde, 0xe7, 0x53, 0x20, 0x10, 0xc6, 0xc4, 0xc6, 0x71, 0x9c, 0x78, 0x70, 0xc5,
- 0x65, 0xcb, 0x96, 0xe9, 0x13, 0x7b, 0xf8, 0xf0, 0xe1, 0x7e, 0x6d, 0x94, 0xa7, 0xa7, 0x17, 0x12,
- 0x8e, 0xbf, 0xbf, 0x3f, 0xe0, 0xb7, 0xb0, 0xb0, 0x20, 0x3f, 0xa5, 0x35, 0x24, 0xe9, 0x9f, 0x1f,
- 0x5b, 0x51, 0x51, 0x11, 0x10, 0x10, 0xa8, 0x7b, 0x09, 0xbb, 0xfb, 0x4a, 0xf3, 0x15, 0x0c, 0xd0,
- 0x63, 0xc6, 0x8c, 0xd1, 0xed, 0x74, 0x2c, 0x1f, 0x9f, 0x90, 0x00, 0x9b, 0x7d, 0xeb, 0xed, 0x77,
- 0x41, 0xec, 0xbc, 0x79, 0xf3, 0x1e, 0x8c, 0xf5, 0x1a, 0x84, 0x84, 0x5f, 0xd7, 0xd4, 0x7e, 0x4a,
- 0x65, 0x6a, 0x69, 0x65, 0x45, 0xb3, 0xb3, 0xa3, 0xd2, 0x68, 0x81, 0x41, 0x41, 0x17, 0x2f, 0x5c,
- 0xd4, 0xe1, 0x77, 0xe6, 0xcc, 0x19, 0x22, 0x15, 0x77, 0x13, 0xf1, 0x5d, 0xa2, 0xc4, 0xed, 0x3e,
- 0xea, 0xeb, 0xeb, 0xf5, 0x89, 0x6d, 0x6c, 0x6c, 0xec, 0xd7, 0x46, 0xe1, 0xb8, 0x2b, 0x2c, 0x2c,
- 0x24, 0xcf, 0x2b, 0x30, 0x48, 0xe9, 0x5f, 0x83, 0x80, 0x54, 0xa0, 0x54, 0x2a, 0x75, 0x2f, 0x01,
- 0xc8, 0xc3, 0x87, 0x0e, 0x23, 0x46, 0xce, 0x9c, 0x39, 0x53, 0xff, 0x83, 0x27, 0x17, 0x37, 0xb7,
- 0x59, 0xb3, 0x67, 0x4f, 0x7f, 0xe9, 0x65, 0x1a, 0xcd, 0x76, 0xfe, 0xfc, 0xf9, 0x04, 0x54, 0x67,
- 0xcf, 0x9e, 0xf3, 0xf2, 0xf2, 0x34, 0x31, 0x1a, 0x6c, 0x6a, 0x3c, 0xc4, 0x8c, 0x78, 0x98, 0x68,
- 0x1f, 0xa6, 0xc6, 0x83, 0x79, 0x4e, 0x9c, 0x55, 0x2b, 0x57, 0xea, 0xe6, 0x0a, 0xce, 0x9d, 0x3b,
- 0xe7, 0xea, 0xea, 0xda, 0x47, 0x97, 0x8c, 0x8d, 0x8d, 0xab, 0xab, 0xab, 0xf5, 0x89, 0x45, 0x2d,
- 0xd6, 0xaf, 0x8d, 0x52, 0x28, 0x14, 0x3a, 0x62, 0xc9, 0xcb, 0x10, 0x0c, 0x4c, 0x7d, 0x5c, 0xe7,
- 0x85, 0x2a, 0xfb, 0xcd, 0x25, 0x7f, 0x43, 0xa9, 0xbe, 0x7e, 0xfd, 0x7a, 0x3e, 0x9f, 0xaf, 0xbf,
- 0x96, 0x4c, 0x2e, 0x77, 0x76, 0x75, 0xc5, 0x8a, 0x0d, 0x0d, 0x0d, 0x77, 0x7f, 0xd1, 0x68, 0x5a,
- 0x4e, 0xbc, 0xbf, 0x64, 0xea, 0xa8, 0x34, 0xe1, 0xbc, 0x0a, 0xfe, 0xba, 0x71, 0x92, 0x2f, 0xfe,
- 0xe2, 0xba, 0xe3, 0xaf, 0x6e, 0x7b, 0xe7, 0xb8, 0xef, 0x9e, 0x2d, 0xdb, 0x50, 0x2f, 0x99, 0x94,
- 0xc1, 0x9a, 0x3d, 0xa5, 0xe8, 0xe6, 0xe5, 0x63, 0x1d, 0xad, 0x57, 0xee, 0xdf, 0xbf, 0x77, 0xfe,
- 0xfc, 0xf9, 0xdf, 0xdc, 0xb8, 0x37, 0x81, 0xb1, 0x69, 0xd3, 0xa6, 0xe9, 0x57, 0x5e, 0xeb, 0xd7,
- 0xad, 0xef, 0xd7, 0x46, 0xb9, 0xbb, 0x7b, 0x60, 0x5b, 0xd0, 0x0a, 0x83, 0xc1, 0x20, 0x53, 0x81,
- 0x81, 0x89, 0xb8, 0x96, 0x16, 0x76, 0x0a, 0x5f, 0xca, 0xcf, 0x2f, 0x88, 0x8c, 0x8c, 0xd2, 0xbd,
- 0x04, 0xfb, 0x4d, 0x4e, 0x4e, 0x46, 0xe5, 0x85, 0xe4, 0x19, 0x13, 0x13, 0xd3, 0xb3, 0x7e, 0x31,
- 0x35, 0x35, 0xd9, 0xb8, 0xfa, 0x9d, 0x8b, 0x3b, 0x17, 0xfd, 0xb8, 0x2a, 0xa4, 0x79, 0xab, 0xa0,
- 0x75, 0x1f, 0xa7, 0xed, 0x20, 0xab, 0xed, 0x00, 0xab, 0x6d, 0x3f, 0x5b, 0xfb, 0x38, 0xc8, 0xd6,
- 0xfe, 0x7a, 0x90, 0x7d, 0x7d, 0x0f, 0xb7, 0x79, 0x9b, 0xe0, 0xd4, 0x5a, 0xe9, 0x4f, 0x5f, 0x54,
- 0xb5, 0xfe, 0xf8, 0xd1, 0xc5, 0x73, 0xa7, 0x7b, 0x56, 0x5e, 0xfa, 0xa2, 0x50, 0x28, 0x9f, 0x7c,
- 0xf2, 0x89, 0xfe, 0xec, 0xd6, 0x4b, 0x2f, 0xbd, 0xd4, 0xaf, 0x8d, 0x12, 0x8b, 0x25, 0xe5, 0xe5,
- 0xda, 0x9b, 0xc3, 0xa0, 0x78, 0x24, 0x2b, 0x2f, 0x03, 0x93, 0xee, 0x7e, 0x05, 0x72, 0xb9, 0x3c,
- 0x27, 0x27, 0x47, 0xad, 0xee, 0x72, 0xf5, 0x37, 0xa2, 0xc2, 0xb5, 0x6b, 0xd7, 0xe0, 0x72, 0x8b,
- 0x17, 0x2f, 0xb6, 0xb1, 0xb1, 0xe9, 0xba, 0xe2, 0xa0, 0x24, 0x2f, 0x87, 0x03, 0x0d, 0x19, 0xe7,
- 0x3e, 0x12, 0x5f, 0xdf, 0xc5, 0xbb, 0xb1, 0x87, 0xdb, 0xde, 0xc8, 0xd4, 0x7c, 0xe7, 0xa8, 0x7b,
- 0xb4, 0x1e, 0x64, 0x5d, 0xda, 0x24, 0xf8, 0x71, 0x95, 0xe8, 0xe4, 0x1a, 0x51, 0xf3, 0x36, 0xa7,
- 0xf6, 0x43, 0xcc, 0xb6, 0x83, 0xcc, 0xcb, 0x9b, 0x05, 0xe7, 0xf7, 0x4c, 0x7d, 0xa1, 0x24, 0xb6,
- 0x8f, 0x2e, 0x85, 0x86, 0x86, 0xde, 0xb8, 0x71, 0x43, 0x47, 0xec, 0xed, 0xdb, 0x77, 0xfc, 0xfc,
- 0x7b, 0xff, 0x6c, 0xe2, 0x61, 0xc2, 0x90, 0x51, 0x55, 0x55, 0xa5, 0x52, 0xa9, 0x78, 0x3c, 0x1e,
- 0xf8, 0x27, 0x89, 0x35, 0x24, 0x11, 0xc4, 0xd2, 0x68, 0x34, 0x99, 0x4c, 0x96, 0x95, 0x95, 0x15,
- 0x1b, 0xdb, 0x85, 0x25, 0x17, 0x17, 0x97, 0xaf, 0xbe, 0xda, 0x0e, 0x62, 0xaf, 0x5c, 0xb9, 0x82,
- 0x64, 0xa8, 0x7b, 0x9e, 0x6a, 0x61, 0x5c, 0x11, 0xc6, 0xfc, 0xea, 0x15, 0xb7, 0x9f, 0x3e, 0x94,
- 0x1c, 0x59, 0xe2, 0xba, 0xf7, 0x35, 0xb7, 0x43, 0x8b, 0x64, 0x2d, 0x5f, 0xf1, 0x35, 0x47, 0x7e,
- 0x23, 0xf6, 0xc6, 0x3e, 0x4e, 0xd3, 0xdb, 0xb2, 0x4d, 0xa3, 0xbd, 0x37, 0xd5, 0x79, 0xef, 0x7a,
- 0xc5, 0xfd, 0xd2, 0x16, 0x1e, 0xf1, 0x3c, 0x2c, 0x77, 0xd7, 0x7b, 0x92, 0xf2, 0x18, 0x7b, 0x5b,
- 0xcb, 0x5e, 0x4e, 0xff, 0x46, 0xfc, 0xd8, 0xbc, 0x79, 0xb3, 0x7e, 0x88, 0x6d, 0x6d, 0x6d, 0xb3,
- 0xec, 0xcf, 0xa9, 0x86, 0x83, 0x3a, 0x67, 0xe1, 0x6a, 0x6b, 0x6b, 0x31, 0x2e, 0x88, 0x44, 0xce,
- 0xe4, 0xed, 0x8c, 0x0c, 0x4f, 0x0f, 0xee, 0x62, 0xe4, 0x96, 0x99, 0x99, 0xd9, 0xed, 0x9e, 0x30,
- 0x08, 0x0c, 0xe3, 0xc7, 0xd7, 0x13, 0xf3, 0xf9, 0x67, 0xcf, 0x9e, 0xf5, 0xf0, 0xf0, 0xc0, 0x93,
- 0x5c, 0x9a, 0xf9, 0x94, 0x14, 0xde, 0xee, 0xb9, 0xb2, 0x0b, 0x9f, 0x39, 0x9f, 0xd9, 0x20, 0xfe,
- 0xb4, 0xd6, 0xfb, 0x93, 0x5a, 0xef, 0xa3, 0x6f, 0x4b, 0x6f, 0xec, 0x65, 0xff, 0x8a, 0xeb, 0x51,
- 0x86, 0xe6, 0x18, 0xeb, 0xe6, 0x77, 0xac, 0xab, 0x5f, 0x73, 0x8e, 0xbe, 0xe5, 0xbe, 0xf5, 0x05,
- 0xef, 0x2d, 0xcf, 0x7b, 0x9f, 0x5c, 0x23, 0xbe, 0x79, 0x98, 0x41, 0x2c, 0x00, 0x37, 0x3e, 0xbd,
- 0x99, 0xbd, 0x69, 0x01, 0xef, 0xc5, 0x4c, 0x8e, 0xb5, 0xc5, 0xaf, 0x38, 0xe1, 0xd8, 0x09, 0x0a,
- 0x0a, 0xda, 0xb8, 0x71, 0x63, 0x87, 0xde, 0x29, 0x5e, 0x88, 0x04, 0xab, 0x57, 0xaf, 0x31, 0x31,
- 0xe9, 0xdf, 0x0d, 0xc3, 0xf1, 0x56, 0x23, 0x47, 0x8e, 0x4c, 0x4e, 0x4e, 0x91, 0x4a, 0xa5, 0xc4,
- 0x0d, 0x90, 0xff, 0xc0, 0xff, 0x2e, 0x52, 0x4f, 0x5d, 0xc4, 0x97, 0x22, 0x75, 0xde, 0x77, 0x2b,
- 0x23, 0x25, 0x25, 0xa5, 0xdb, 0xf9, 0xa8, 0x88, 0x0a, 0x2d, 0x0f, 0x3e, 0x63, 0x3d, 0xd4, 0xd8,
- 0x58, 0x99, 0x11, 0xd5, 0x30, 0xdc, 0xf5, 0xd0, 0x22, 0xf7, 0x8b, 0x9f, 0x39, 0x23, 0xa6, 0xb6,
- 0x7c, 0xe3, 0xd4, 0x38, 0xcf, 0xe3, 0xd4, 0x07, 0xa2, 0xb6, 0x46, 0xc6, 0x03, 0x5c, 0x99, 0x9a,
- 0xe3, 0x42, 0x4d, 0x93, 0x54, 0xd3, 0x24, 0xd2, 0x7c, 0xc7, 0x6c, 0x3f, 0xc4, 0xb8, 0xb6, 0x8b,
- 0x73, 0xfe, 0x53, 0xe7, 0xab, 0xdf, 0xf0, 0x34, 0x47, 0x18, 0xfa, 0xb1, 0xe1, 0xe6, 0x61, 0xe6,
- 0xd5, 0x3d, 0xac, 0xd3, 0x9b, 0x38, 0x7b, 0x97, 0xb8, 0xac, 0x98, 0x18, 0xfe, 0xc1, 0xb2, 0x79,
- 0xe7, 0xcf, 0xfc, 0xab, 0xe3, 0x56, 0x7b, 0xe7, 0xa9, 0xb2, 0xbf, 0x0a, 0xde, 0xee, 0xed, 0xed,
- 0x3d, 0x80, 0x8d, 0x2a, 0x28, 0x28, 0xc8, 0xce, 0xce, 0x41, 0xd4, 0xb1, 0xb7, 0xb7, 0x27, 0xa7,
- 0x0b, 0x0c, 0x4c, 0x04, 0xb1, 0x52, 0xa9, 0x96, 0x58, 0x08, 0xc3, 0xa8, 0xfe, 0xab, 0xa6, 0xa6,
- 0xa6, 0xb3, 0xe7, 0xcc, 0x41, 0xfd, 0x75, 0xef, 0xce, 0xed, 0xcb, 0x8d, 0x9f, 0xef, 0x7c, 0x45,
- 0x79, 0xfc, 0x6d, 0xf7, 0x4b, 0x9b, 0xc4, 0xad, 0x07, 0xd8, 0xfa, 0xf8, 0xfd, 0xf6, 0x38, 0xca,
- 0xd6, 0x34, 0xb9, 0x6a, 0x9a, 0x64, 0x9a, 0x26, 0x89, 0x96, 0xde, 0x5e, 0x97, 0xe9, 0xf1, 0x80,
- 0xeb, 0x5e, 0xdd, 0xc1, 0x3b, 0xb5, 0x46, 0x7a, 0xfa, 0xb3, 0x51, 0xff, 0xbe, 0xb2, 0x47, 0xd3,
- 0xfc, 0xfd, 0x9d, 0x7f, 0x6b, 0x80, 0x6b, 0xf5, 0xc8, 0x91, 0x03, 0xfb, 0x4a, 0xdc, 0x88, 0x08,
- 0xed, 0x69, 0x12, 0xc4, 0x74, 0x01, 0xf9, 0x3d, 0x5f, 0x06, 0xa6, 0x07, 0xc4, 0x4a, 0xd3, 0xd3,
- 0xd3, 0xe1, 0xa8, 0x3d, 0x6f, 0x29, 0xaf, 0x8e, 0x56, 0xef, 0xdb, 0xf1, 0xf5, 0xb9, 0x1d, 0xeb,
- 0x76, 0xbc, 0xa4, 0x68, 0x7a, 0x57, 0x76, 0x69, 0x93, 0x73, 0xeb, 0x7e, 0x8e, 0x7e, 0x64, 0xed,
- 0x4a, 0x2c, 0x57, 0xd3, 0xe4, 0xd6, 0x49, 0xac, 0x73, 0x5f, 0xc4, 0x1e, 0x25, 0x1e, 0x8c, 0xce,
- 0xc7, 0x83, 0x27, 0x8f, 0x30, 0xda, 0x1b, 0x59, 0x2d, 0x5f, 0x0a, 0x4e, 0xad, 0x0f, 0x6b, 0xde,
- 0xbf, 0x70, 0xe9, 0xbc, 0x17, 0x79, 0x9c, 0x01, 0xde, 0x1a, 0x14, 0x43, 0xc6, 0x88, 0x11, 0x23,
- 0x94, 0x4a, 0x25, 0x97, 0xcb, 0x25, 0x2f, 0x9c, 0x31, 0x30, 0x11, 0xc4, 0xa2, 0xc8, 0x4a, 0x4d,
- 0x4d, 0xcd, 0xcf, 0xcf, 0x87, 0x29, 0x75, 0x5b, 0x80, 0x61, 0x6d, 0xf6, 0xd6, 0xd8, 0xb4, 0x5d,
- 0xb3, 0x82, 0xbe, 0x7f, 0xcf, 0xfd, 0xd2, 0xe7, 0xc0, 0x95, 0xdd, 0x6d, 0x7c, 0xd7, 0x7b, 0x30,
- 0x34, 0xc7, 0x05, 0x9d, 0xb8, 0xba, 0x69, 0x8e, 0xf3, 0xb4, 0xbf, 0x3e, 0x0c, 0xd7, 0x63, 0x08,
- 0x0f, 0x6c, 0xcd, 0x71, 0x8e, 0xe6, 0x38, 0x57, 0xfb, 0x03, 0x7e, 0x3d, 0xaa, 0x67, 0xb9, 0x87,
- 0x98, 0x2d, 0xdb, 0x79, 0x9b, 0x5e, 0xe3, 0x97, 0xa9, 0x1c, 0xac, 0xcc, 0x07, 0x02, 0x1b, 0x92,
- 0x79, 0x5d, 0xdd, 0xe8, 0xe8, 0x68, 0xb5, 0x50, 0x28, 0x24, 0x8b, 0x2f, 0x03, 0x53, 0xe7, 0x1d,
- 0x8f, 0xad, 0xc5, 0x62, 0x71, 0x52, 0x52, 0x52, 0xcf, 0x4b, 0xbd, 0xd8, 0x54, 0xb3, 0xfa, 0x38,
- 0xa7, 0x6d, 0xd3, 0x3d, 0x9a, 0xde, 0x73, 0xbf, 0xbc, 0xc5, 0x59, 0x1b, 0x06, 0x1e, 0xe6, 0xae,
- 0x04, 0x8a, 0x08, 0x03, 0x5a, 0x62, 0xa5, 0x9a, 0x63, 0x9c, 0x87, 0xe3, 0xca, 0xd6, 0xf2, 0x8c,
- 0xa0, 0xdb, 0x24, 0xee, 0x7c, 0x08, 0x34, 0xc7, 0xb8, 0x5a, 0xb3, 0xed, 0xba, 0x64, 0xeb, 0x3e,
- 0xf6, 0x77, 0x2b, 0x9c, 0x5f, 0x48, 0xe4, 0x18, 0x0f, 0xe9, 0x77, 0x0a, 0x45, 0x12, 0xa8, 0xaa,
- 0xaa, 0x42, 0x2c, 0x87, 0xd9, 0x92, 0xdf, 0x3e, 0x63, 0x60, 0x22, 0xbe, 0x1a, 0x09, 0x5e, 0x14,
- 0x17, 0x17, 0x57, 0x58, 0x58, 0x88, 0x1f, 0x74, 0x2f, 0x39, 0x5a, 0x9b, 0x4e, 0x4b, 0x12, 0x6c,
- 0x9f, 0x21, 0xff, 0xd7, 0x7f, 0xd8, 0xbb, 0x0e, 0xb0, 0xa8, 0xae, 0x75, 0x7b, 0xef, 0x7d, 0xc9,
- 0x0d, 0x49, 0x3e, 0x9f, 0x06, 0x91, 0x36, 0x74, 0x18, 0xca, 0x30, 0x0d, 0xa9, 0x62, 0x80, 0xa0,
- 0x51, 0xaa, 0x82, 0x80, 0x28, 0x02, 0x22, 0xd5, 0xf2, 0x14, 0xa3, 0x48, 0x50, 0x6f, 0xf4, 0x25,
- 0x7a, 0xed, 0x5e, 0x11, 0xa3, 0x80, 0x68, 0xac, 0x80, 0x05, 0xa5, 0x4a, 0x91, 0xde, 0x7b, 0x2f,
- 0x43, 0x93, 0x3e, 0x94, 0x81, 0xa1, 0xce, 0x00, 0x22, 0xe8, 0x7b, 0xff, 0xcc, 0xd1, 0x09, 0xc2,
- 0x00, 0x2a, 0x68, 0x84, 0xef, 0xac, 0xef, 0x7c, 0x80, 0x67, 0xce, 0x8c, 0x73, 0xf6, 0x59, 0x67,
- 0xed, 0xf5, 0xff, 0xfb, 0x3f, 0x7b, 0xdf, 0xc0, 0xb7, 0x45, 0xc9, 0xb2, 0xd4, 0x75, 0x7a, 0x47,
- 0x0a, 0x2c, 0x65, 0x59, 0x02, 0x10, 0x58, 0x69, 0xee, 0x96, 0xa0, 0x9c, 0x9f, 0x7d, 0x8c, 0x24,
- 0x3b, 0x34, 0xc3, 0xbd, 0x56, 0x63, 0x20, 0x2d, 0x10, 0x98, 0xdb, 0xf1, 0x70, 0x83, 0x14, 0xf9,
- 0x2a, 0x2c, 0xfe, 0xe6, 0xbd, 0x15, 0x12, 0xec, 0xf7, 0xc6, 0x8d, 0x1b, 0x37, 0x6f, 0xde, 0x4c,
- 0x26, 0x2b, 0xf1, 0xf3, 0xf3, 0xa3, 0xc1, 0xd7, 0x42, 0xc2, 0xb8, 0x75, 0x10, 0x56, 0x81, 0xc6,
- 0x72, 0x9e, 0x04, 0xfc, 0xfa, 0xcb, 0x7f, 0xec, 0xd4, 0x11, 0xc9, 0xf8, 0x8d, 0x5c, 0x79, 0x8d,
- 0x40, 0x7d, 0x22, 0xdf, 0x9b, 0x23, 0x3a, 0x9d, 0xba, 0x22, 0x5b, 0xa5, 0x04, 0x9b, 0x84, 0x72,
- 0x53, 0x0a, 0x2c, 0xa8, 0xeb, 0x6b, 0xba, 0x2a, 0x8e, 0xdb, 0xb0, 0x2c, 0x6f, 0xc0, 0xd1, 0xd8,
- 0x52, 0x81, 0x9e, 0x6c, 0xe1, 0xee, 0x6c, 0x21, 0xf8, 0x83, 0x59, 0x2a, 0x08, 0x51, 0x9e, 0xdd,
- 0xca, 0x89, 0x46, 0x65, 0x46, 0xc0, 0x6d, 0xa8, 0xa1, 0xa1, 0xe1, 0xe4, 0xe4, 0x8c, 0x8e, 0x7c,
- 0x2d, 0x3c, 0x20, 0xc5, 0x30, 0x22, 0x22, 0x22, 0x5a, 0x5a, 0xda, 0x56, 0x56, 0x5b, 0x70, 0x38,
- 0x1c, 0xb2, 0x5f, 0x62, 0xe9, 0xd7, 0x71, 0x07, 0x48, 0x25, 0x5e, 0xc4, 0x86, 0x87, 0x0a, 0x5d,
- 0x29, 0x52, 0xcc, 0xe2, 0x99, 0x02, 0x7f, 0xf0, 0xa2, 0xac, 0x8e, 0x5e, 0x8e, 0x2d, 0x98, 0xdc,
- 0x1c, 0x6c, 0x85, 0x30, 0x9b, 0xd2, 0x1c, 0x75, 0x45, 0x04, 0x56, 0x76, 0x90, 0x22, 0x36, 0x5e,
- 0x60, 0x29, 0x0f, 0xc4, 0x02, 0x1c, 0x88, 0x8f, 0x5d, 0xe5, 0x98, 0x05, 0x2c, 0xf6, 0xd2, 0xe2,
- 0xa5, 0x0f, 0x1b, 0x8a, 0x4f, 0x7f, 0x0a, 0x5c, 0x21, 0x26, 0x26, 0x86, 0x3c, 0x89, 0x20, 0x25,
- 0x25, 0x8d, 0x3e, 0x51, 0xbb, 0x90, 0x80, 0xac, 0x8e, 0x24, 0x24, 0x24, 0x04, 0x72, 0xb4, 0x65,
- 0x8b, 0x35, 0x91, 0xf8, 0xba, 0x78, 0xd5, 0x84, 0xc8, 0x9f, 0xf1, 0x2b, 0x99, 0x72, 0x8d, 0xd0,
- 0x1a, 0x25, 0xd7, 0x97, 0x37, 0x85, 0x66, 0x8e, 0xdf, 0x28, 0xec, 0xee, 0x7e, 0x8a, 0xfe, 0x9d,
- 0x1d, 0x6a, 0x49, 0xb0, 0xf8, 0xfc, 0xa7, 0xb4, 0x22, 0x74, 0xfd, 0x53, 0x5d, 0x1b, 0x63, 0x44,
- 0x73, 0xae, 0x4a, 0x9e, 0xfa, 0x81, 0x78, 0xc9, 0x80, 0x90, 0xeb, 0x2d, 0x31, 0x58, 0x20, 0x08,
- 0x1a, 0xdb, 0x16, 0x85, 0xdd, 0xaa, 0xf1, 0xde, 0x1a, 0x0b, 0xe0, 0xe3, 0x5b, 0x66, 0x67, 0x67,
- 0x67, 0x62, 0x62, 0x0a, 0xf7, 0x20, 0x2f, 0x2f, 0x2f, 0x1a, 0x7c, 0x2d, 0x18, 0x20, 0xc5, 0x30,
- 0x82, 0x82, 0x82, 0xea, 0xea, 0x1a, 0xe0, 0x63, 0x39, 0x53, 0xc8, 0xee, 0x5f, 0x25, 0x9e, 0x73,
- 0x82, 0x54, 0x73, 0x07, 0x4f, 0x8b, 0x97, 0x61, 0x14, 0x09, 0xbf, 0x13, 0x63, 0x41, 0x2d, 0x2b,
- 0xb8, 0xda, 0x57, 0x41, 0xd6, 0x4b, 0x6f, 0xd1, 0x15, 0x94, 0x56, 0x8a, 0x65, 0x1e, 0xde, 0xa4,
- 0x08, 0xaa, 0x1e, 0x89, 0xdd, 0x72, 0x50, 0x3c, 0xa1, 0x43, 0x0a, 0x76, 0xc2, 0x97, 0xdd, 0x92,
- 0x40, 0x76, 0x32, 0x4b, 0x04, 0x9b, 0x1e, 0xcb, 0x93, 0x45, 0x17, 0x7d, 0xc0, 0x79, 0x81, 0x39,
- 0x37, 0x32, 0x32, 0xb2, 0xb1, 0xb1, 0x51, 0x51, 0x51, 0x81, 0xb3, 0x43, 0xad, 0xec, 0x82, 0x01,
- 0xc2, 0x58, 0x01, 0x01, 0x41, 0x35, 0x35, 0x75, 0x5b, 0x5b, 0x56, 0xe9, 0x3e, 0xb2, 0xdf, 0xf5,
- 0x07, 0xb1, 0xdc, 0x93, 0xa4, 0x67, 0xfe, 0x8a, 0x9d, 0x29, 0x52, 0x8c, 0x92, 0x99, 0x2c, 0x01,
- 0x6b, 0x64, 0x16, 0x33, 0x58, 0x31, 0x45, 0x3a, 0x8b, 0x45, 0x57, 0xd9, 0x71, 0x66, 0x80, 0xed,
- 0x1c, 0x38, 0xdc, 0x2e, 0x16, 0xac, 0x09, 0x94, 0xbc, 0x62, 0xa6, 0x78, 0x52, 0x8b, 0x94, 0xea,
- 0x29, 0xd5, 0x19, 0x2f, 0xca, 0x79, 0x23, 0xa3, 0x50, 0xb8, 0xf2, 0x06, 0x9e, 0x33, 0x92, 0xfb,
- 0x5e, 0x80, 0xbe, 0x43, 0x59, 0x59, 0xd9, 0xc5, 0xc5, 0x45, 0x47, 0x47, 0x07, 0x5c, 0x3a, 0x9a,
- 0x95, 0x5d, 0x30, 0x78, 0xc3, 0x58, 0x01, 0x55, 0x55, 0x55, 0xa4, 0xa8, 0x1b, 0xd1, 0x22, 0x43,
- 0x1c, 0x5f, 0xe6, 0x31, 0x96, 0xc6, 0x76, 0x26, 0x4a, 0x33, 0x8a, 0x67, 0xd2, 0x58, 0x64, 0x44,
- 0x60, 0x66, 0xba, 0x22, 0x99, 0x81, 0x3f, 0xa5, 0x75, 0xa0, 0x48, 0xd0, 0xdf, 0x0e, 0xff, 0x1f,
- 0x3d, 0xc2, 0x35, 0x4b, 0x62, 0xf9, 0x1d, 0xa9, 0xfe, 0xc2, 0xb7, 0x38, 0x4f, 0x4f, 0x97, 0xc8,
- 0x3f, 0x87, 0xff, 0xea, 0xcb, 0x0f, 0x0c, 0x9a, 0xa4, 0xa5, 0xa5, 0xed, 0xed, 0xed, 0x8d, 0x8d,
- 0x8d, 0xe5, 0xe4, 0xe4, 0x91, 0x89, 0x0b, 0x50, 0x99, 0x5d, 0x00, 0x78, 0xb3, 0x2e, 0x2d, 0x3f,
- 0x32, 0x1f, 0xbb, 0xae, 0xae, 0x2e, 0x52, 0x3a, 0xc2, 0xbf, 0xe8, 0x9f, 0xd1, 0x6e, 0xa4, 0xb2,
- 0x2b, 0x44, 0xe8, 0x97, 0x7b, 0xb3, 0x44, 0x99, 0x53, 0x8e, 0x1a, 0xbc, 0x61, 0x2c, 0xf7, 0x70,
- 0x4c, 0x94, 0x9d, 0x71, 0x45, 0xb8, 0x2a, 0xc7, 0x0e, 0xb2, 0x5e, 0x7f, 0x0e, 0x3d, 0x53, 0xb8,
- 0x22, 0x50, 0xee, 0xfc, 0x5a, 0xe2, 0x45, 0x3d, 0xc2, 0xd3, 0x23, 0x32, 0x93, 0xdf, 0x3b, 0x50,
- 0x88, 0x69, 0x7c, 0x24, 0xf7, 0xdb, 0x06, 0x71, 0xae, 0xf9, 0xd8, 0x25, 0xbc, 0xbc, 0xfa, 0xeb,
- 0x4d, 0x6c, 0xec, 0xed, 0xe5, 0x89, 0x04, 0x9e, 0x29, 0x46, 0x72, 0x21, 0xe0, 0x32, 0x31, 0x31,
- 0xb1, 0xb6, 0x66, 0x19, 0x03, 0x34, 0xc7, 0xb5, 0x60, 0x80, 0x14, 0x1c, 0x2e, 0x5d, 0xca, 0x47,
- 0x26, 0x93, 0xad, 0xac, 0xac, 0xd6, 0xac, 0x59, 0x83, 0x0c, 0xe5, 0x7f, 0xfd, 0xe5, 0x7f, 0xed,
- 0xff, 0x51, 0x2c, 0xfd, 0x28, 0x39, 0xeb, 0x37, 0x72, 0xd5, 0x4d, 0x79, 0x5a, 0xa2, 0xd8, 0x0c,
- 0xa4, 0xe5, 0x9e, 0x1c, 0x10, 0x63, 0x0d, 0xd7, 0xbe, 0x1e, 0x26, 0x78, 0x2d, 0xad, 0x6c, 0xae,
- 0x4a, 0x04, 0x6e, 0xc7, 0x9d, 0x59, 0x4d, 0xba, 0xeb, 0xac, 0xd0, 0xfc, 0x40, 0x6a, 0xf2, 0x7b,
- 0xc1, 0x39, 0x77, 0xc4, 0x49, 0xe7, 0x7b, 0x2a, 0x11, 0xc4, 0xb8, 0xaf, 0x88, 0x27, 0x2a, 0x2e,
- 0xbe, 0xcb, 0xd5, 0xf5, 0xe7, 0x83, 0x07, 0xdd, 0xdc, 0xdd, 0x7f, 0xd4, 0xd7, 0x17, 0x14, 0x12,
- 0xfa, 0x62, 0xd2, 0x5c, 0xa0, 0x70, 0x6a, 0x9a, 0x9a, 0x2b, 0x1d, 0x1d, 0x9d, 0xe0, 0x36, 0x44,
- 0xe7, 0x39, 0x5c, 0x48, 0x80, 0xee, 0x12, 0xa2, 0x69, 0x3c, 0x1e, 0x6f, 0x61, 0x61, 0x61, 0x60,
- 0x60, 0xb0, 0x68, 0xd1, 0xeb, 0x48, 0x47, 0x5e, 0x78, 0x71, 0xc0, 0xff, 0xa8, 0x64, 0x1c, 0x55,
- 0x4a, 0xfa, 0x59, 0x29, 0xe3, 0x38, 0xb1, 0xee, 0x91, 0x34, 0x73, 0x46, 0x43, 0xfb, 0xa7, 0xea,
- 0xf2, 0xb3, 0xeb, 0xb8, 0x44, 0x59, 0x1b, 0x58, 0x5c, 0xb6, 0xb4, 0x32, 0xf2, 0x84, 0xb3, 0xbc,
- 0xa4, 0xc2, 0xdc, 0xe5, 0xce, 0xea, 0x92, 0xef, 0x3a, 0x29, 0xa4, 0x9c, 0xc7, 0xf6, 0xe5, 0x4f,
- 0xfc, 0x40, 0xb8, 0x2f, 0x06, 0x0a, 0x85, 0x69, 0xf1, 0x52, 0x15, 0x7e, 0xf8, 0x47, 0xc7, 0x2c,
- 0x56, 0xaa, 0x2a, 0x71, 0x15, 0x46, 0x21, 0x0c, 0xc6, 0x69, 0xc7, 0x0e, 0x60, 0x2c, 0x6c, 0x07,
- 0x3c, 0x3c, 0xb6, 0x39, 0x39, 0xad, 0xd0, 0xd6, 0x96, 0x91, 0x95, 0xfd, 0xfa, 0xed, 0xe9, 0xbf,
- 0x24, 0x25, 0x25, 0xed, 0xec, 0xb6, 0x99, 0x9a, 0x9a, 0x22, 0x95, 0x87, 0xe8, 0x94, 0xdd, 0x0b,
- 0x03, 0xac, 0xa5, 0x34, 0xd8, 0xc5, 0x30, 0xeb, 0xd7, 0xaf, 0x07, 0xd7, 0x07, 0x57, 0x16, 0xd9,
- 0x2f, 0x2c, 0xc8, 0x7f, 0x74, 0xbb, 0x79, 0xf4, 0x61, 0xed, 0xcc, 0x5f, 0xc9, 0x09, 0xee, 0x4a,
- 0x31, 0x6e, 0xe4, 0x62, 0x5f, 0xb9, 0xb6, 0x58, 0xf1, 0xf7, 0x90, 0x59, 0x20, 0x2d, 0x9b, 0xab,
- 0x1d, 0x29, 0x62, 0xc9, 0xe7, 0x64, 0x42, 0xf6, 0xc9, 0x9f, 0xd6, 0x26, 0xdd, 0xb4, 0xc1, 0xe7,
- 0xf8, 0x48, 0xb6, 0xc6, 0x4f, 0x1a, 0x41, 0x2b, 0x15, 0x04, 0xc3, 0xdc, 0x93, 0x29, 0x4e, 0x7d,
- 0x22, 0x5b, 0xea, 0x43, 0x8c, 0x3f, 0x6f, 0x79, 0xcb, 0xfb, 0xc2, 0x81, 0x03, 0xee, 0x5c, 0x13,
- 0x53, 0xff, 0xbd, 0x64, 0xc9, 0x7a, 0x73, 0x73, 0x77, 0x0f, 0x0f, 0x84, 0xb4, 0x2c, 0xb1, 0xfd,
- 0xf9, 0x67, 0x97, 0x5d, 0xbb, 0xbe, 0xd7, 0xd5, 0xfd, 0x7a, 0x5c, 0x05, 0x38, 0x0f, 0x0f, 0xcf,
- 0x86, 0x0d, 0x66, 0x48, 0x1d, 0x17, 0xf2, 0x30, 0x38, 0x3a, 0x94, 0xb0, 0x00, 0x00, 0x8c, 0x05,
- 0xcb, 0x87, 0xc5, 0x62, 0x0d, 0x0d, 0x0d, 0xc1, 0xf8, 0xf1, 0xf1, 0xf1, 0x21, 0xfb, 0x45, 0x44,
- 0x45, 0x7f, 0x39, 0x7c, 0xe8, 0xfa, 0xb1, 0xdd, 0xb1, 0xff, 0xfa, 0x3e, 0xfb, 0x38, 0x39, 0xe7,
- 0x24, 0x31, 0x7c, 0xb7, 0x52, 0xac, 0x07, 0xb1, 0xe1, 0xa1, 0x04, 0xb3, 0xe8, 0xdd, 0x18, 0x5b,
- 0x2a, 0x40, 0x8d, 0x10, 0x7b, 0xbc, 0x13, 0x77, 0xd5, 0x4a, 0xf1, 0xf4, 0x2a, 0xe2, 0x1f, 0x66,
- 0x4a, 0x55, 0x8f, 0x44, 0xa9, 0xb1, 0x13, 0xb3, 0xbb, 0xcc, 0x12, 0xc1, 0xfe, 0x7c, 0x0c, 0x3d,
- 0x55, 0xb2, 0xf5, 0x89, 0x6c, 0xf5, 0x2d, 0x7c, 0xce, 0x39, 0xb5, 0xa4, 0x2b, 0xbb, 0x9f, 0x86,
- 0xdc, 0x0b, 0x7e, 0xfc, 0xd8, 0xdb, 0xdb, 0x07, 0x33, 0x69, 0xe6, 0xf0, 0xbf, 0xb1, 0xd7, 0x69,
- 0x52, 0x51, 0x57, 0xdf, 0x77, 0xe0, 0x00, 0x87, 0xb1, 0xc8, 0xb6, 0xfb, 0xa7, 0x9f, 0x88, 0x2a,
- 0x2a, 0xff, 0x18, 0xd7, 0xfb, 0x83, 0x89, 0x75, 0x76, 0x76, 0x5e, 0xbd, 0x7a, 0x35, 0xa7, 0x2a,
- 0x06, 0x95, 0xd9, 0xf9, 0x0e, 0x90, 0x1d, 0x64, 0xf9, 0x6f, 0xb0, 0x04, 0xa6, 0xa6, 0x1b, 0x20,
- 0x48, 0x41, 0xf6, 0x8b, 0x89, 0x8b, 0x1f, 0x3f, 0x71, 0xc2, 0xcf, 0xc7, 0xe7, 0xd6, 0x69, 0x8f,
- 0xa7, 0x07, 0xbf, 0xcf, 0x3b, 0x4d, 0xca, 0x3b, 0x43, 0x8c, 0xf9, 0x89, 0x18, 0xb2, 0x8b, 0x1c,
- 0xba, 0x9b, 0x14, 0xe7, 0x41, 0x1c, 0xc8, 0xc6, 0x0c, 0x14, 0x0a, 0xb2, 0xb6, 0x22, 0x41, 0x06,
- 0x7b, 0x83, 0xbf, 0xfb, 0xd9, 0x1b, 0x35, 0x59, 0x3a, 0x74, 0x1f, 0xd1, 0x6b, 0x1d, 0xde, 0xd3,
- 0x00, 0x7f, 0x7e, 0x0d, 0x29, 0xd8, 0x95, 0x50, 0x1f, 0x26, 0x0e, 0x0e, 0x76, 0x12, 0x57, 0x85,
- 0xfa, 0x72, 0x45, 0xdb, 0xe3, 0xb0, 0x75, 0x0f, 0x70, 0x65, 0x3e, 0xe4, 0xac, 0x93, 0x6a, 0x29,
- 0x17, 0x1c, 0x72, 0x92, 0x22, 0x73, 0x32, 0xd2, 0x32, 0x33, 0x33, 0x13, 0x13, 0x13, 0x83, 0x82,
- 0x1e, 0xd9, 0xda, 0xd9, 0x71, 0xfd, 0xda, 0x18, 0x31, 0x31, 0x5b, 0x7b, 0x7b, 0xf7, 0xb7, 0x19,
- 0x0b, 0xdb, 0x8e, 0x5d, 0xbb, 0xbe, 0x5d, 0xf4, 0x67, 0x0a, 0x17, 0xec, 0xab, 0xa3, 0xa3, 0xa3,
- 0xb9, 0xb9, 0x05, 0x91, 0x48, 0x84, 0x00, 0x13, 0x2d, 0x97, 0x5d, 0x00, 0x40, 0x34, 0x56, 0x56,
- 0x56, 0xd6, 0xc8, 0xc8, 0xc8, 0xcc, 0xcc, 0x9c, 0xc3, 0x58, 0x71, 0x09, 0x89, 0x33, 0x67, 0xcf,
- 0x05, 0x04, 0x04, 0xf8, 0xfb, 0x07, 0x5c, 0xbf, 0x78, 0xfa, 0x89, 0x87, 0x0e, 0x28, 0x6d, 0xb9,
- 0x0f, 0xa1, 0xe1, 0x81, 0x62, 0xea, 0x71, 0x62, 0xf8, 0x4f, 0xc4, 0xd0, 0xbd, 0xc4, 0x20, 0x17,
- 0xb2, 0xbf, 0xed, 0xf2, 0xc0, 0xad, 0xcb, 0x83, 0x5d, 0x94, 0x82, 0x77, 0x2b, 0xf9, 0x59, 0x2a,
- 0x5d, 0x32, 0x22, 0x5f, 0x5e, 0x4f, 0xf2, 0xde, 0x48, 0xf0, 0xdd, 0x84, 0x0b, 0xda, 0xa3, 0x58,
- 0x1d, 0x28, 0xcb, 0xa5, 0xec, 0x90, 0x5d, 0x0a, 0xdb, 0x93, 0x23, 0xd6, 0xfe, 0x54, 0xa6, 0xfa,
- 0x0e, 0xbe, 0xd0, 0x4b, 0x3d, 0xe3, 0x9c, 0x69, 0x56, 0xe0, 0xf9, 0xb2, 0xc2, 0xbc, 0x4a, 0x0a,
- 0xa5, 0xaa, 0xb2, 0x12, 0xb6, 0x8a, 0xf2, 0xf2, 0xc2, 0xc2, 0xc2, 0xe4, 0xe4, 0xe4, 0x33, 0x67,
- 0xce, 0xfe, 0x73, 0x8a, 0x15, 0x16, 0x54, 0x34, 0x34, 0x5c, 0xf7, 0xed, 0x9b, 0xc0, 0x58, 0xb0,
- 0x0a, 0xca, 0x2b, 0x34, 0xc7, 0x1f, 0xa6, 0xa6, 0xa6, 0x06, 0x32, 0xab, 0xad, 0xad, 0x23, 0x21,
- 0x21, 0x81, 0x2c, 0xf2, 0x85, 0xca, 0xec, 0xbc, 0x06, 0x5c, 0x41, 0xf0, 0xae, 0x38, 0x1c, 0x0e,
- 0x04, 0xd6, 0xcc, 0xcc, 0x8c, 0xe3, 0x0a, 0xe0, 0xfa, 0x9e, 0xff, 0xcf, 0x85, 0x90, 0xd0, 0xd0,
- 0x88, 0x88, 0x27, 0xf7, 0xee, 0xdd, 0xbf, 0xee, 0x79, 0x2a, 0xe4, 0x90, 0x41, 0xc6, 0x6f, 0x4a,
- 0x65, 0x97, 0x09, 0xf5, 0x0f, 0x70, 0x9d, 0x09, 0xd2, 0xbd, 0x39, 0xa2, 0x2d, 0xe1, 0xb2, 0xf9,
- 0xbf, 0xcb, 0x27, 0x1c, 0x53, 0x88, 0xfa, 0x97, 0x7c, 0xe4, 0x61, 0xf9, 0xa8, 0xc3, 0xf2, 0x69,
- 0xa7, 0xe4, 0xab, 0x02, 0xb0, 0xf4, 0x2c, 0xee, 0xf5, 0xb1, 0x4c, 0x36, 0x57, 0x7b, 0xb3, 0xc4,
- 0x3a, 0x62, 0x65, 0xea, 0xef, 0xe3, 0x4a, 0x2e, 0x91, 0xb2, 0x3c, 0x4d, 0xb3, 0xfd, 0x4f, 0x94,
- 0xe7, 0xe7, 0xd4, 0xd6, 0xd6, 0x36, 0x34, 0x34, 0x34, 0x35, 0x35, 0x53, 0x5b, 0xa8, 0xd4, 0x96,
- 0x96, 0xc6, 0xc6, 0x46, 0xd8, 0x53, 0x54, 0x54, 0x14, 0x18, 0x78, 0x0f, 0x7a, 0x76, 0xae, 0xdf,
- 0xfc, 0x9b, 0x45, 0x8b, 0xf4, 0x8d, 0x8d, 0xf7, 0xbf, 0xed, 0x0d, 0x80, 0xb1, 0x3a, 0x6b, 0xd6,
- 0x8e, 0x3f, 0x0c, 0xec, 0x2b, 0x30, 0x16, 0xce, 0x8e, 0x40, 0x20, 0x2c, 0x5b, 0xb6, 0x0c, 0x95,
- 0xd9, 0x79, 0x8d, 0x37, 0xf9, 0xd8, 0x65, 0x4a, 0x4a, 0x4a, 0x56, 0x56, 0x56, 0x20, 0xb3, 0x9c,
- 0x5c, 0x01, 0x30, 0xf6, 0x82, 0xe7, 0xc5, 0xa8, 0xa8, 0xe8, 0xa4, 0xa4, 0xe4, 0xe8, 0xe8, 0xe8,
- 0xc0, 0x80, 0x40, 0x20, 0xed, 0xa3, 0xc3, 0x26, 0x69, 0xff, 0xbb, 0xbc, 0xf4, 0x32, 0xb1, 0xfe,
- 0x81, 0x22, 0x2d, 0x51, 0xba, 0x3f, 0x5f, 0xe4, 0x1d, 0xb3, 0x5e, 0x48, 0x12, 0x80, 0xc5, 0xd5,
- 0x38, 0x99, 0xc6, 0x20, 0x05, 0x8a, 0x2f, 0x21, 0xfb, 0x94, 0x5a, 0xf6, 0xf5, 0xfd, 0x45, 0x89,
- 0xe1, 0xb5, 0x35, 0xb5, 0x8d, 0x8d, 0x4d, 0x6d, 0xad, 0x6d, 0x9d, 0x9d, 0x9d, 0x74, 0x3a, 0xbd,
- 0xa7, 0xa7, 0x17, 0xb6, 0x6e, 0x7a, 0x77, 0x47, 0x7b, 0x47, 0x7d, 0x5d, 0x7d, 0x6a, 0x4a, 0xca,
- 0xee, 0xdd, 0x7b, 0xa6, 0x52, 0x45, 0xde, 0x65, 0xcb, 0xf4, 0xd6, 0xad, 0xdb, 0xef, 0xee, 0xce,
- 0x61, 0xec, 0x5e, 0x37, 0x37, 0x99, 0x49, 0xd3, 0xce, 0x68, 0x6a, 0x6a, 0x3a, 0x39, 0x39, 0x69,
- 0x69, 0x69, 0x89, 0x8b, 0x8b, 0xa3, 0x6b, 0x29, 0xce, 0x6b, 0x20, 0xb5, 0x5b, 0x18, 0x0c, 0x46,
- 0x53, 0x73, 0xa5, 0x83, 0x83, 0xa3, 0x8e, 0xce, 0x0f, 0x9c, 0xab, 0x29, 0x21, 0x29, 0xe9, 0x75,
- 0xe9, 0xf7, 0x84, 0xf8, 0x84, 0xdc, 0xdc, 0xdc, 0xf4, 0xf4, 0x8c, 0xc8, 0xc8, 0x28, 0xb0, 0x07,
- 0x7e, 0x9e, 0xa7, 0xef, 0x1f, 0x32, 0x4b, 0x39, 0xaa, 0x5c, 0xfa, 0x3b, 0xb1, 0xe1, 0x01, 0x8e,
- 0x16, 0x2f, 0xd3, 0x9b, 0x2b, 0x32, 0x4d, 0xd6, 0x8b, 0x25, 0xaa, 0xc5, 0x42, 0xfd, 0x05, 0x98,
- 0x9e, 0x4c, 0x71, 0x38, 0xb8, 0xf1, 0xb1, 0x42, 0xe5, 0x75, 0x42, 0xde, 0x19, 0x72, 0xfa, 0x05,
- 0x8b, 0xec, 0x20, 0xaf, 0x8a, 0xe2, 0xfc, 0xfa, 0xfa, 0xfa, 0x56, 0x6a, 0x6b, 0x67, 0x67, 0x57,
- 0x6f, 0x6f, 0x2f, 0x83, 0xc1, 0x18, 0x1a, 0x1e, 0x7e, 0x3e, 0x32, 0x02, 0xdb, 0xf0, 0xf3, 0xe7,
- 0x4c, 0x26, 0x93, 0x4e, 0xef, 0xae, 0xa4, 0x54, 0x42, 0xfc, 0x25, 0xcd, 0x6d, 0x75, 0x3c, 0x04,
- 0x8b, 0x96, 0x2c, 0xd1, 0xd2, 0xd5, 0xdd, 0xbd, 0x77, 0xaf, 0x9b, 0xbb, 0xbb, 0xeb, 0xfe, 0xfd,
- 0x6b, 0xd7, 0xad, 0x9b, 0x3c, 0xa6, 0xc0, 0xcb, 0xcb, 0xeb, 0xe8, 0xe8, 0x64, 0x6a, 0x6a, 0x8a,
- 0xc7, 0x13, 0xd0, 0x45, 0x96, 0xe7, 0x2f, 0x58, 0x6b, 0x0f, 0x7d, 0xf1, 0x05, 0x98, 0x58, 0x08,
- 0xbb, 0xf4, 0xf4, 0xf4, 0x41, 0x85, 0xc8, 0x64, 0x32, 0xe7, 0x55, 0x49, 0x49, 0xc9, 0xdf, 0x2f,
- 0x5f, 0x49, 0x4d, 0x49, 0x2d, 0x2b, 0x2d, 0x2d, 0x29, 0x2e, 0x4e, 0x4d, 0x4b, 0x03, 0x7b, 0x70,
- 0xe7, 0xce, 0x5d, 0x6f, 0xcf, 0xb3, 0x81, 0x1e, 0xe6, 0x40, 0xda, 0x32, 0x50, 0xda, 0xfb, 0xb8,
- 0xb6, 0xa7, 0xd8, 0xee, 0x0c, 0x09, 0x10, 0x5b, 0x60, 0x26, 0xa3, 0x44, 0x88, 0xf5, 0x93, 0xb5,
- 0x09, 0xf7, 0x17, 0x62, 0xfa, 0xf3, 0x44, 0x40, 0x54, 0xe9, 0x29, 0x92, 0xed, 0x31, 0xd8, 0xa6,
- 0xc7, 0x0a, 0xd5, 0xb7, 0xf0, 0x45, 0x17, 0x48, 0x69, 0xbf, 0x6a, 0xa4, 0x5e, 0x75, 0x2b, 0x4c,
- 0x8d, 0xa9, 0xa2, 0x54, 0x80, 0xb4, 0xd2, 0x3a, 0x68, 0x3d, 0x3d, 0x3d, 0x03, 0x4c, 0x26, 0xb0,
- 0xf4, 0xe5, 0xcb, 0x97, 0xaf, 0xc6, 0x01, 0xfe, 0x35, 0x32, 0x32, 0x02, 0x07, 0xa4, 0x24, 0xa7,
- 0x58, 0x5a, 0x5a, 0x4e, 0x73, 0x22, 0x5f, 0xf1, 0xf0, 0x08, 0x8b, 0x8a, 0xe2, 0x94, 0x94, 0x64,
- 0x70, 0xb8, 0x45, 0x8b, 0x17, 0x4f, 0x66, 0x23, 0x9c, 0xe6, 0x1b, 0x99, 0xd5, 0x86, 0xbe, 0x03,
- 0xa9, 0x3f, 0x44, 0x49, 0x3b, 0xef, 0x80, 0x94, 0x1a, 0x42, 0x04, 0x8d, 0x58, 0x02, 0x1b, 0x1b,
- 0x1b, 0x01, 0x01, 0x01, 0xce, 0xab, 0xc0, 0x58, 0x6f, 0x1f, 0xdf, 0xac, 0xac, 0xac, 0xda, 0xda,
- 0x67, 0x80, 0xe2, 0xa2, 0xa2, 0x94, 0x94, 0x94, 0xb0, 0xf0, 0x08, 0x20, 0xed, 0xe5, 0x4b, 0x5e,
- 0xb7, 0x0f, 0x59, 0x25, 0xff, 0xa2, 0x52, 0x78, 0x81, 0x54, 0x73, 0x13, 0xdf, 0xf8, 0x08, 0x47,
- 0x7d, 0x22, 0xd7, 0xf1, 0x54, 0x96, 0x16, 0x27, 0x43, 0x8b, 0x97, 0x86, 0x9f, 0x1d, 0xb1, 0xd8,
- 0xb6, 0x68, 0x2c, 0x35, 0x42, 0x1e, 0x5e, 0xaa, 0xf5, 0xc7, 0x53, 0xfc, 0xf0, 0x70, 0x64, 0xe6,
- 0x31, 0xd5, 0xf8, 0xe3, 0x66, 0xd9, 0x4f, 0x1f, 0x97, 0x15, 0x15, 0x82, 0x13, 0x68, 0x6e, 0x6e,
- 0x01, 0x1b, 0x30, 0xd0, 0xdf, 0x3f, 0x34, 0xfc, 0x7c, 0xec, 0xed, 0x65, 0x3b, 0xc6, 0x03, 0x48,
- 0xdb, 0xd4, 0xd8, 0x78, 0xc5, 0xdb, 0x5b, 0x06, 0x8b, 0x9d, 0xee, 0x64, 0xfe, 0xfe, 0x77, 0x38,
- 0x9d, 0x69, 0x16, 0xb8, 0x07, 0x69, 0xb5, 0xb4, 0xdc, 0x64, 0x6e, 0x6e, 0x01, 0x27, 0x8b, 0x3e,
- 0x63, 0x3b, 0x1f, 0x81, 0x8c, 0xcf, 0x82, 0xda, 0x00, 0x33, 0x57, 0xad, 0x5a, 0xb5, 0x7d, 0xfb,
- 0xf6, 0x35, 0x6b, 0xd6, 0x8e, 0x97, 0x1d, 0x49, 0x29, 0x29, 0xbf, 0x6b, 0xd7, 0x21, 0x60, 0x87,
- 0x38, 0x88, 0xd6, 0xde, 0x01, 0xa4, 0x45, 0x82, 0xf7, 0xb0, 0xd0, 0xb0, 0x3b, 0xb7, 0xef, 0x5c,
- 0xb9, 0x7c, 0xf9, 0xfa, 0x2f, 0x4e, 0xd1, 0x07, 0xbf, 0xcf, 0x3a, 0xae, 0x04, 0x6c, 0x2c, 0xbb,
- 0x42, 0xa8, 0xf0, 0x23, 0x52, 0xae, 0x11, 0x58, 0x9b, 0x1f, 0x9e, 0x72, 0x15, 0x5f, 0x7e, 0x95,
- 0x50, 0x7a, 0x99, 0x50, 0x78, 0x81, 0x98, 0x7d, 0x42, 0x29, 0xf5, 0x98, 0x56, 0xdc, 0x71, 0xd3,
- 0xa4, 0xbb, 0x9e, 0x05, 0xf9, 0xf9, 0x14, 0x0a, 0x05, 0xdc, 0x69, 0x1b, 0xb5, 0x15, 0x9c, 0x2a,
- 0xd8, 0x80, 0x91, 0x17, 0x2f, 0xa6, 0x5a, 0x7a, 0x89, 0x83, 0xa1, 0xc1, 0xa1, 0xe2, 0xa2, 0x62,
- 0x5b, 0x5b, 0x5b, 0x64, 0xb6, 0xf0, 0x0f, 0x03, 0xf0, 0x93, 0x44, 0x22, 0x39, 0x38, 0x38, 0xac,
- 0x5d, 0xbb, 0x56, 0x56, 0x56, 0x6e, 0xc9, 0x12, 0xd6, 0x10, 0x18, 0x4a, 0xda, 0x79, 0x04, 0xc4,
- 0xc1, 0x82, 0xa8, 0x92, 0x48, 0xe4, 0x8d, 0x1b, 0x2d, 0x5d, 0x5c, 0x5c, 0x26, 0x3c, 0x96, 0x28,
- 0x25, 0x25, 0x7d, 0xf3, 0xd6, 0x2d, 0x20, 0x58, 0x57, 0x17, 0x7d, 0x60, 0x60, 0xa0, 0xa3, 0xa3,
- 0xa3, 0xba, 0xba, 0x3a, 0x2f, 0x2f, 0x2f, 0x21, 0x21, 0x31, 0x24, 0x38, 0xf4, 0xce, 0xed, 0xbb,
- 0x57, 0x2e, 0xff, 0xee, 0x7b, 0xdc, 0xfd, 0xde, 0x61, 0x8b, 0x90, 0x7f, 0xe9, 0x47, 0xff, 0xa2,
- 0x1d, 0x7f, 0x64, 0x45, 0xd2, 0x11, 0xb5, 0xa4, 0x23, 0xea, 0xc9, 0x47, 0xd4, 0x92, 0x59, 0x7f,
- 0x68, 0x24, 0x1e, 0xd5, 0x8e, 0x3f, 0xb1, 0x21, 0xf6, 0xbc, 0x4b, 0xdc, 0xcd, 0xb3, 0xe9, 0x89,
- 0x71, 0x85, 0x05, 0x05, 0x95, 0x14, 0x4a, 0x43, 0x7d, 0x7d, 0x7b, 0x5b, 0x7b, 0x4f, 0x77, 0x0f,
- 0x93, 0x39, 0x38, 0x3a, 0x3a, 0x3a, 0x03, 0x59, 0xdf, 0x4c, 0x0e, 0x03, 0xf4, 0x0e, 0x7e, 0x1c,
- 0x8c, 0xc7, 0xe3, 0x67, 0xd3, 0x95, 0x2f, 0x59, 0xb2, 0xc4, 0xc4, 0xc4, 0xd4, 0xda, 0xda, 0x66,
- 0xc5, 0x8a, 0x15, 0x18, 0x8c, 0x08, 0x6b, 0xb5, 0x47, 0x34, 0xd3, 0x35, 0x4f, 0x80, 0xa4, 0x08,
- 0xe0, 0x0a, 0x82, 0x83, 0x05, 0x81, 0xdd, 0xb1, 0x63, 0xc7, 0xe4, 0x09, 0x0c, 0xe1, 0xa5, 0x7b,
- 0xf7, 0xef, 0x83, 0xd5, 0x64, 0x0e, 0xb2, 0xa8, 0x35, 0xc0, 0x60, 0xb4, 0x52, 0xa9, 0x94, 0x0a,
- 0x4a, 0x4e, 0x76, 0x4e, 0x7c, 0x7c, 0x7c, 0x48, 0x48, 0xc8, 0xed, 0xdb, 0x77, 0x7c, 0x7c, 0xaf,
- 0x7a, 0x79, 0x7a, 0x5e, 0x3c, 0x7d, 0xec, 0xf2, 0x31, 0x37, 0xbf, 0x5f, 0xf7, 0xdc, 0xf8, 0x6d,
- 0xf7, 0xed, 0x7f, 0xbb, 0x06, 0x9c, 0xdc, 0x77, 0xff, 0xec, 0x81, 0xc7, 0x9e, 0x87, 0xc2, 0xaf,
- 0x9e, 0x8a, 0x0e, 0xba, 0x9b, 0x94, 0x98, 0x90, 0x9d, 0x9d, 0x0d, 0x22, 0x59, 0x55, 0x59, 0xd9,
- 0xd8, 0xd8, 0x08, 0xcc, 0xef, 0xed, 0xe9, 0x1d, 0x1c, 0x1c, 0x1a, 0x7d, 0x7b, 0xc9, 0xa4, 0xe9,
- 0x01, 0x5f, 0x00, 0x62, 0x34, 0x37, 0xb7, 0x03, 0x40, 0xb3, 0xd9, 0x9c, 0x35, 0x0e, 0x87, 0x73,
- 0x74, 0x74, 0x64, 0x3f, 0x9b, 0xa0, 0x88, 0x66, 0xba, 0xe6, 0x0b, 0x90, 0x09, 0xb1, 0xe1, 0xd2,
- 0x8b, 0x88, 0x88, 0xa8, 0xaa, 0xaa, 0x6e, 0xde, 0x6c, 0xe5, 0xe2, 0xb2, 0x7d, 0xc2, 0xec, 0x85,
- 0x00, 0xb8, 0xb8, 0x71, 0x71, 0xf1, 0x3d, 0xbd, 0xbd, 0x88, 0xc9, 0x1c, 0x1b, 0x1b, 0xeb, 0xed,
- 0xeb, 0x6b, 0x6a, 0x6a, 0x2a, 0x2f, 0x2b, 0x03, 0x73, 0x1b, 0x17, 0x17, 0x17, 0x12, 0x1c, 0xec,
- 0xef, 0x1f, 0xf0, 0xc7, 0x1f, 0x37, 0x7c, 0x7d, 0xaf, 0xfa, 0x78, 0xfb, 0xf8, 0xf8, 0xf8, 0xfa,
- 0xf9, 0xf9, 0xfd, 0x71, 0xe3, 0xe6, 0xdd, 0xbb, 0xfe, 0x0f, 0x1f, 0x06, 0x85, 0x87, 0x85, 0xc7,
- 0xc6, 0xc6, 0xa6, 0xa6, 0xa6, 0xe6, 0xe4, 0xe6, 0x96, 0x96, 0x94, 0x54, 0x57, 0x55, 0xc3, 0x7b,
- 0x69, 0xb4, 0xce, 0xbe, 0xbe, 0xfe, 0xe1, 0x69, 0x8d, 0xeb, 0x94, 0xde, 0x60, 0x68, 0x28, 0x2d,
- 0x3d, 0x9d, 0xf3, 0x94, 0xc4, 0x87, 0x01, 0x28, 0x6a, 0x60, 0x60, 0x08, 0xa4, 0xd5, 0xd6, 0xd6,
- 0x96, 0x92, 0x92, 0x5a, 0xbc, 0x78, 0x31, 0xfa, 0x6c, 0xf8, 0xe7, 0x0f, 0xc4, 0x0f, 0xf0, 0xf3,
- 0xf3, 0x2b, 0x2a, 0xe2, 0x8d, 0x8c, 0x8c, 0x5c, 0x5d, 0xf7, 0x72, 0x9d, 0x37, 0x5b, 0x55, 0x45,
- 0x05, 0xbc, 0x2b, 0x88, 0x1b, 0x87, 0x33, 0x10, 0x04, 0xd1, 0xbb, 0xe8, 0xe0, 0x42, 0x59, 0x2b,
- 0x74, 0x67, 0x66, 0x02, 0x21, 0xc3, 0xc2, 0xc2, 0x81, 0x9c, 0xc0, 0x5b, 0x08, 0xc7, 0x80, 0xa8,
- 0x81, 0x81, 0xf7, 0x82, 0x82, 0x82, 0xc0, 0xe8, 0x46, 0x47, 0x45, 0x27, 0xc4, 0x27, 0x64, 0x64,
- 0x64, 0x80, 0x71, 0x2d, 0x2b, 0x2d, 0x43, 0x16, 0x62, 0xee, 0xa4, 0xd1, 0xfa, 0xfb, 0x07, 0x86,
- 0x9f, 0x8f, 0x70, 0x5d, 0x9a, 0x76, 0x46, 0x80, 0xdd, 0xa5, 0xd3, 0xe9, 0x3e, 0xbe, 0xbe, 0xb3,
- 0x3c, 0xfd, 0xef, 0xbe, 0xfb, 0x0e, 0x2c, 0x90, 0x85, 0xc5, 0xc6, 0xe5, 0xcb, 0x95, 0x85, 0x85,
- 0x85, 0xbf, 0xfd, 0xf6, 0x5b, 0x34, 0x3d, 0xfb, 0x39, 0x03, 0xe8, 0x0a, 0x7e, 0x60, 0xe9, 0xd2,
- 0xa5, 0xb2, 0xb2, 0xb2, 0xab, 0x57, 0xaf, 0x86, 0x6b, 0x07, 0x7e, 0x60, 0xf2, 0x04, 0x80, 0x20,
- 0xb9, 0x40, 0xc1, 0xe1, 0xe1, 0xe1, 0x09, 0x9c, 0x19, 0x1a, 0x1e, 0xa6, 0xd1, 0x68, 0xc0, 0xe4,
- 0x92, 0xe2, 0xe2, 0xcc, 0x0c, 0xd6, 0xd0, 0x7f, 0x4c, 0x74, 0x4c, 0x44, 0x78, 0x44, 0x58, 0x58,
- 0x18, 0xfc, 0x8c, 0x8a, 0x8c, 0x7c, 0x1a, 0xf3, 0x14, 0xb8, 0x9a, 0x92, 0x9a, 0xca, 0x76, 0x02,
- 0x45, 0x60, 0x83, 0xeb, 0x9e, 0xd5, 0x51, 0xa9, 0x54, 0x7a, 0x57, 0x17, 0xd0, 0xf5, 0xc5, 0x3b,
- 0xc4, 0x59, 0xd3, 0x00, 0x94, 0xb9, 0xaa, 0xaa, 0x1a, 0x3a, 0xf4, 0x59, 0x36, 0x02, 0x44, 0x5e,
- 0x7b, 0xf6, 0xb8, 0xc2, 0xdd, 0xaa, 0xa8, 0xa8, 0x08, 0x77, 0x2e, 0xdc, 0xbf, 0x68, 0xe9, 0xec,
- 0xe7, 0x09, 0x4e, 0x7e, 0x40, 0x42, 0x42, 0x62, 0xe5, 0xca, 0x95, 0x10, 0x7d, 0x5b, 0x5b, 0x5b,
- 0xf3, 0xf2, 0x4e, 0x9c, 0x6b, 0x0b, 0xa0, 0xa7, 0xa7, 0x07, 0x72, 0xca, 0x95, 0x33, 0x10, 0xe0,
- 0xb7, 0xb5, 0xb5, 0xd5, 0xd6, 0xd4, 0x02, 0x69, 0xb3, 0xb3, 0x73, 0x80, 0x9c, 0x10, 0x8b, 0x01,
- 0x4b, 0xe1, 0x67, 0x52, 0x52, 0x72, 0x5a, 0x5a, 0x1a, 0x78, 0x06, 0x96, 0xb4, 0xb2, 0x9d, 0x40,
- 0x43, 0x43, 0x63, 0x5b, 0x5b, 0x7b, 0x77, 0x77, 0xf7, 0x00, 0x83, 0x39, 0x61, 0x3d, 0xc4, 0x0f,
- 0x03, 0x18, 0x60, 0x2f, 0xaf, 0x4b, 0xb3, 0x27, 0xd8, 0xba, 0x75, 0xeb, 0x9d, 0x9c, 0x58, 0xc5,
- 0xde, 0x58, 0x2c, 0x96, 0x97, 0x97, 0x17, 0x2d, 0x9d, 0xfd, 0x0c, 0x81, 0x8c, 0x17, 0x40, 0x27,
- 0x08, 0x5d, 0xa1, 0x8a, 0x8a, 0x0a, 0x74, 0x8b, 0xdb, 0xb6, 0xd9, 0x83, 0xd2, 0x4e, 0x0e, 0x3d,
- 0xe4, 0xe5, 0xe5, 0xb3, 0x73, 0x72, 0x5e, 0x4e, 0x61, 0x35, 0x81, 0x78, 0x10, 0x3a, 0xb5, 0xb4,
- 0xb4, 0xd4, 0x54, 0x57, 0x83, 0x3d, 0xc8, 0xcf, 0xcf, 0xcf, 0xca, 0xce, 0xce, 0xcc, 0xcc, 0x04,
- 0xa2, 0xe6, 0xe6, 0xe6, 0x16, 0x14, 0x14, 0x94, 0x16, 0x97, 0x40, 0x80, 0x56, 0x53, 0x53, 0xdb,
- 0xd2, 0xdc, 0x4c, 0x63, 0xc7, 0x59, 0x10, 0xbb, 0xbd, 0x18, 0xe7, 0x2e, 0x66, 0x03, 0xf8, 0x56,
- 0x19, 0xe9, 0x19, 0x38, 0xc5, 0xd9, 0xca, 0x2c, 0x1f, 0x1f, 0x9f, 0x9d, 0x9d, 0xdd, 0x96, 0x2d,
- 0xd6, 0x1a, 0x1a, 0x1a, 0x62, 0x62, 0x62, 0x68, 0x85, 0xcc, 0x67, 0x08, 0xd0, 0x25, 0xe8, 0xfe,
- 0x20, 0x40, 0x86, 0x90, 0xca, 0xd8, 0xd8, 0xd8, 0xc1, 0xc1, 0x51, 0x5d, 0x5d, 0x7d, 0x72, 0x59,
- 0x14, 0x1c, 0xe0, 0x79, 0xf1, 0xe2, 0xf8, 0x65, 0x67, 0x27, 0x00, 0xba, 0x75, 0x08, 0x9d, 0x40,
- 0x36, 0x9b, 0x9b, 0x9b, 0xc1, 0xa0, 0x56, 0x94, 0x57, 0x94, 0x00, 0x8a, 0x8b, 0x4b, 0x8b, 0x8b,
- 0xcb, 0x4b, 0xcb, 0x28, 0x15, 0x15, 0xc0, 0x64, 0xf0, 0xba, 0xd4, 0x16, 0x6a, 0x57, 0x67, 0x17,
- 0xc4, 0x59, 0x10, 0x31, 0xbd, 0x57, 0x5a, 0x60, 0x46, 0x74, 0x76, 0x76, 0xba, 0xb9, 0x1d, 0x98,
- 0x7d, 0x6b, 0x10, 0x08, 0x04, 0x27, 0x27, 0x67, 0x13, 0x13, 0x13, 0x22, 0x91, 0x24, 0x20, 0x20,
- 0x80, 0x7a, 0x83, 0xcf, 0x0a, 0x20, 0xa4, 0x5f, 0x7d, 0xf5, 0x15, 0x74, 0x7f, 0x32, 0x32, 0x32,
- 0x3f, 0xfc, 0xa0, 0x0b, 0x74, 0x35, 0x30, 0x30, 0x98, 0x3c, 0x61, 0x3b, 0x5c, 0xb2, 0xad, 0x5b,
- 0xb7, 0x56, 0x57, 0x57, 0x4f, 0xef, 0x36, 0x41, 0xe8, 0x06, 0x07, 0x07, 0xe9, 0x9d, 0x5d, 0x40,
- 0x4b, 0x20, 0x27, 0xf0, 0x16, 0x0c, 0x00, 0xe0, 0x59, 0xed, 0xb3, 0x86, 0xfa, 0x86, 0x96, 0xe6,
- 0x96, 0x8e, 0xf6, 0xf6, 0xee, 0xae, 0xee, 0x81, 0x01, 0x76, 0x9c, 0xf5, 0xfe, 0x69, 0x81, 0xe9,
- 0x01, 0x01, 0xa0, 0xbf, 0xbf, 0x3f, 0x9c, 0xcb, 0x2c, 0xdb, 0x04, 0x28, 0x0a, 0x4e, 0x1e, 0xbc,
- 0xc1, 0x8f, 0x3f, 0xfe, 0x28, 0x23, 0x83, 0x05, 0xeb, 0x8e, 0x8e, 0x29, 0x7c, 0x26, 0x40, 0xb2,
- 0xaf, 0x8b, 0x17, 0x2f, 0x06, 0xfb, 0xba, 0x62, 0xc5, 0x0a, 0xf0, 0xae, 0x40, 0xcb, 0x09, 0x93,
- 0x1b, 0x23, 0xd0, 0xd6, 0xd1, 0x89, 0x8d, 0x8b, 0x9b, 0x10, 0x70, 0x71, 0xc5, 0xd8, 0xd8, 0xd8,
- 0x00, 0x83, 0x01, 0x5e, 0xb7, 0xbd, 0xad, 0x1d, 0x28, 0xda, 0xd4, 0xd8, 0x04, 0x3e, 0xa1, 0xb5,
- 0xb5, 0x15, 0xb8, 0x0a, 0x41, 0x16, 0xab, 0xac, 0x85, 0xbd, 0x48, 0xe8, 0x6c, 0xe2, 0xac, 0xa9,
- 0xf0, 0xf2, 0xd5, 0xab, 0xf2, 0x8a, 0x8a, 0xe9, 0xd7, 0xac, 0x79, 0x47, 0x40, 0x87, 0xb2, 0x69,
- 0xd3, 0x66, 0x1b, 0x1b, 0x5b, 0xf0, 0x06, 0x22, 0x22, 0xe8, 0x98, 0xc2, 0xe7, 0x02, 0x24, 0xda,
- 0x12, 0x15, 0x15, 0x55, 0x53, 0x53, 0xb3, 0xb4, 0xdc, 0xe4, 0xe2, 0xb2, 0x9d, 0xf3, 0x30, 0xd7,
- 0x78, 0xc8, 0x60, 0xb1, 0xbe, 0xbe, 0xbe, 0x9d, 0x5d, 0x5d, 0xef, 0x48, 0x33, 0xe8, 0xeb, 0xc1,
- 0x3c, 0x00, 0x39, 0xe9, 0x74, 0x20, 0x69, 0x17, 0xab, 0x50, 0xb0, 0xbb, 0xa7, 0xbf, 0xaf, 0x0f,
- 0x76, 0x0e, 0x3f, 0xff, 0x90, 0x8c, 0xeb, 0xbb, 0xa3, 0xbf, 0xbf, 0xff, 0xe0, 0xc1, 0x83, 0x73,
- 0xd2, 0x89, 0x43, 0xa7, 0x63, 0x6f, 0x6f, 0x6f, 0x6e, 0x6e, 0x4e, 0x22, 0x91, 0x04, 0x05, 0x05,
- 0xbf, 0xf9, 0xe6, 0x1b, 0xd4, 0x1b, 0xfc, 0xb5, 0x80, 0xf6, 0x87, 0xde, 0x5f, 0x48, 0x48, 0x88,
- 0x4c, 0x26, 0x9b, 0x98, 0x98, 0x02, 0x5d, 0x39, 0xd3, 0xc1, 0x8d, 0x07, 0x5c, 0xa9, 0x6d, 0xf6,
- 0xf6, 0x15, 0x15, 0x94, 0xf7, 0x8a, 0xe8, 0x47, 0x47, 0x47, 0x07, 0x87, 0x87, 0x07, 0x18, 0x4c,
- 0x30, 0x00, 0x8c, 0x01, 0xc6, 0xe0, 0xd0, 0x10, 0xd8, 0x00, 0x60, 0xf2, 0xc7, 0x90, 0xd6, 0x09,
- 0xff, 0xef, 0xc3, 0xa0, 0x20, 0xc9, 0x71, 0x73, 0x87, 0x7e, 0x30, 0xd8, 0x8b, 0x86, 0x68, 0xba,
- 0xb8, 0xb8, 0xe8, 0xe9, 0xe9, 0x29, 0x28, 0x28, 0xf0, 0xf1, 0x2d, 0xe3, 0xe1, 0x41, 0x1f, 0x60,
- 0xfc, 0xcb, 0x80, 0xd8, 0x57, 0x24, 0xda, 0xd2, 0xd7, 0xd7, 0x47, 0xaa, 0x9a, 0x27, 0x67, 0x5f,
- 0xe1, 0xaa, 0x41, 0x18, 0x12, 0x11, 0xf1, 0x04, 0x02, 0xa5, 0xf7, 0x25, 0x1b, 0xd8, 0xd4, 0x17,
- 0xa3, 0xa3, 0x2f, 0x58, 0x00, 0xaa, 0x7e, 0x74, 0xae, 0x22, 0x80, 0xff, 0xa5, 0xee, 0xd9, 0x33,
- 0x43, 0x43, 0xc3, 0x39, 0x69, 0x25, 0x68, 0x22, 0x88, 0xbf, 0xec, 0xed, 0x1d, 0xb4, 0xb5, 0xb5,
- 0xa5, 0xa5, 0xa5, 0x91, 0xe7, 0xc4, 0x51, 0xd2, 0x7e, 0x7a, 0x70, 0xec, 0xab, 0xb4, 0xb4, 0x0c,
- 0xb2, 0x1e, 0x3d, 0x78, 0x3f, 0xae, 0xf6, 0x15, 0x2e, 0x99, 0x87, 0x87, 0x47, 0x6d, 0x4d, 0xed,
- 0xd8, 0x9c, 0x06, 0xf5, 0x1f, 0x15, 0x20, 0xe9, 0xae, 0x7b, 0xf6, 0xc0, 0x37, 0x9f, 0x93, 0xb6,
- 0xe2, 0xe3, 0xe3, 0x83, 0x68, 0x74, 0xf3, 0xe6, 0xcd, 0x6a, 0x6a, 0xea, 0x48, 0xb2, 0x0b, 0x5d,
- 0x56, 0xe9, 0x13, 0x03, 0xc9, 0xbe, 0x42, 0x28, 0x81, 0xc1, 0x60, 0xd4, 0xd5, 0x35, 0xac, 0xac,
- 0xb6, 0x58, 0x59, 0x59, 0xc1, 0xdf, 0x5c, 0xc3, 0x0a, 0x49, 0x49, 0xc9, 0xa8, 0xa8, 0xa8, 0xf1,
- 0xcb, 0xca, 0x7f, 0xfe, 0x80, 0x9b, 0x2b, 0x3c, 0x3c, 0x5c, 0x6a, 0x2e, 0x8c, 0xc1, 0xdf, 0xde,
- 0x14, 0xc9, 0xec, 0xdc, 0xb9, 0x6b, 0xfd, 0x7a, 0x13, 0xc4, 0xd0, 0xa2, 0xc9, 0xae, 0x4f, 0x09,
- 0xa4, 0xd6, 0x05, 0xac, 0xa9, 0x80, 0x80, 0x00, 0x74, 0xf7, 0xa6, 0xa6, 0xa6, 0x0e, 0x0e, 0x0e,
- 0x8a, 0x8a, 0x78, 0xae, 0x3d, 0x1d, 0x1c, 0xec, 0xee, 0xee, 0x5e, 0x56, 0x5a, 0x36, 0x3a, 0x3a,
- 0x6f, 0x04, 0xf6, 0xff, 0xd8, 0xc6, 0x80, 0x4a, 0xa5, 0x42, 0x8c, 0x3f, 0x57, 0x8d, 0x06, 0x72,
- 0xad, 0xa3, 0xa3, 0xc3, 0xae, 0x13, 0x5e, 0x23, 0x27, 0x27, 0x87, 0x0e, 0x84, 0x7d, 0x4a, 0x20,
- 0x0f, 0x17, 0x40, 0x4f, 0x27, 0x2f, 0x2f, 0x0f, 0xed, 0xef, 0xec, 0xec, 0xc2, 0x99, 0xb4, 0x70,
- 0x32, 0x84, 0x31, 0x98, 0x1b, 0x7f, 0xdc, 0x6c, 0x6d, 0x6d, 0xfd, 0x34, 0x16, 0x74, 0x0e, 0x31,
- 0x32, 0x32, 0xb2, 0xdf, 0xcd, 0x6d, 0x36, 0x65, 0xde, 0x13, 0x00, 0x0e, 0x16, 0xee, 0x6e, 0x3b,
- 0x3b, 0x3b, 0x30, 0xb4, 0xc8, 0xc3, 0x35, 0x68, 0x65, 0xd7, 0x27, 0x00, 0xc7, 0xbe, 0x42, 0x5f,
- 0x0f, 0x44, 0x05, 0xfb, 0x6a, 0x6a, 0xba, 0x61, 0x2a, 0xbf, 0x07, 0x07, 0x5b, 0x6d, 0xd9, 0xf2,
- 0x24, 0x32, 0xaa, 0xbb, 0xbb, 0xfb, 0xaf, 0x26, 0xe0, 0x7b, 0x03, 0x82, 0xbe, 0xdc, 0xdc, 0x3c,
- 0x88, 0x2b, 0xe7, 0xb0, 0xf5, 0xa0, 0xd1, 0xb6, 0x6e, 0xdd, 0x6a, 0x69, 0x69, 0xa9, 0xac, 0xac,
- 0x2c, 0x24, 0x24, 0x84, 0x54, 0x76, 0xa1, 0xa4, 0xfd, 0xa8, 0x40, 0xd2, 0x59, 0xc2, 0xc2, 0xc2,
- 0xcb, 0x97, 0x2b, 0x5b, 0x58, 0x58, 0xb8, 0xb8, 0x6c, 0x9f, 0xe6, 0x9a, 0x82, 0xaa, 0x1c, 0x3c,
- 0x74, 0x38, 0x25, 0x25, 0xb5, 0xa7, 0xa7, 0xe7, 0xaf, 0x26, 0xe0, 0x87, 0xa0, 0xb7, 0xb7, 0x57,
- 0x57, 0x57, 0x77, 0x6e, 0x5b, 0x4f, 0x45, 0x45, 0xc5, 0xc9, 0xc9, 0xc9, 0xd0, 0xd0, 0x50, 0x41,
- 0x41, 0x01, 0x9a, 0x0e, 0x35, 0xb4, 0x1f, 0x15, 0x48, 0x3a, 0x0b, 0xfc, 0x80, 0x82, 0x02, 0x4e,
- 0x5f, 0xdf, 0x60, 0xc7, 0x8e, 0x1d, 0xd3, 0x97, 0x40, 0xaf, 0xd0, 0xd4, 0xf4, 0xf2, 0xf2, 0xca,
- 0xcc, 0xcc, 0xea, 0xea, 0xea, 0x9a, 0xf3, 0xe1, 0xd4, 0x59, 0xe3, 0xd5, 0xcb, 0x97, 0x63, 0x63,
- 0xa3, 0xac, 0xdc, 0x19, 0x18, 0x80, 0xe7, 0x6c, 0xc0, 0x2f, 0xd8, 0xc5, 0x39, 0x62, 0x74, 0x6c,
- 0xec, 0xe6, 0xcd, 0x9b, 0x73, 0xdb, 0x86, 0x40, 0x51, 0x23, 0x23, 0xa3, 0x09, 0xc9, 0x2e, 0x54,
- 0x66, 0x3f, 0x06, 0x38, 0x4f, 0x73, 0x43, 0xd7, 0xa6, 0xa5, 0xa5, 0x05, 0x6d, 0x0e, 0x42, 0x31,
- 0xcd, 0x6a, 0xef, 0x20, 0x1d, 0x66, 0xe6, 0xe6, 0x7e, 0x7e, 0xd7, 0xd2, 0x52, 0xd3, 0x9a, 0x9b,
- 0x9b, 0xc7, 0xaf, 0xbb, 0xfd, 0x57, 0x01, 0xbc, 0x34, 0x50, 0x14, 0xbe, 0xc9, 0xd0, 0xd0, 0x10,
- 0x93, 0xc9, 0xec, 0xef, 0xef, 0xef, 0xeb, 0xe9, 0x05, 0xc7, 0xd2, 0xd5, 0xd9, 0xd5, 0x49, 0xa3,
- 0xd1, 0x3a, 0x3a, 0xba, 0x68, 0x9d, 0xbd, 0x3d, 0x3d, 0xe3, 0xbf, 0x6a, 0x5d, 0x5d, 0x1d, 0xd7,
- 0x94, 0xdd, 0x6c, 0x00, 0x9e, 0xca, 0xd9, 0xd9, 0x79, 0xd3, 0xa6, 0xcd, 0xaa, 0xaa, 0xaa, 0x22,
- 0x22, 0xa2, 0xe8, 0xe8, 0xed, 0xc7, 0x00, 0x92, 0x1f, 0x00, 0x7d, 0x10, 0x14, 0x14, 0x02, 0x5d,
- 0xdd, 0xb8, 0xd1, 0xd2, 0xc6, 0xc6, 0x06, 0xbc, 0xc1, 0x34, 0x6f, 0x01, 0x9f, 0xb6, 0x7d, 0xe7,
- 0xce, 0xab, 0x7e, 0xd7, 0x62, 0xa2, 0x63, 0x28, 0x15, 0x94, 0x9e, 0xee, 0x9e, 0x77, 0xcc, 0xc7,
- 0xbe, 0x62, 0xa9, 0xdf, 0x4b, 0x64, 0x7a, 0x81, 0x09, 0x7c, 0xe3, 0xba, 0x7f, 0x46, 0x96, 0x82,
- 0x94, 0x82, 0x7a, 0x32, 0x18, 0x8c, 0xbe, 0xbe, 0x3e, 0x7a, 0x17, 0x1d, 0x98, 0xd9, 0x4a, 0xa5,
- 0x36, 0x37, 0x37, 0x35, 0x34, 0x34, 0x3c, 0x7b, 0x56, 0x57, 0x53, 0x53, 0x5b, 0x55, 0x55, 0x5d,
- 0x49, 0xa9, 0x64, 0x6d, 0x95, 0x95, 0xb5, 0xb5, 0xcf, 0xda, 0xdb, 0xdb, 0x9f, 0xbf, 0x29, 0x7e,
- 0x00, 0x6e, 0x1f, 0x39, 0x72, 0x64, 0xce, 0xdb, 0x13, 0x8b, 0xc5, 0xba, 0xba, 0xee, 0x5d, 0xb7,
- 0x6e, 0x3d, 0x81, 0x40, 0xe0, 0xe7, 0x17, 0x40, 0x67, 0xf2, 0x9c, 0x73, 0x20, 0xd5, 0xda, 0xd0,
- 0x85, 0xc9, 0xc9, 0xc9, 0xb1, 0x87, 0xb7, 0x9c, 0x21, 0x76, 0x98, 0xa6, 0x91, 0xe1, 0x78, 0x65,
- 0x15, 0x95, 0x5f, 0x8e, 0x1e, 0xf5, 0xf1, 0xf1, 0x0d, 0x09, 0x09, 0xc9, 0x64, 0xcd, 0x4b, 0x50,
- 0xdb, 0xdb, 0xd7, 0xf7, 0x2e, 0x95, 0x81, 0xd0, 0x4b, 0x77, 0xd3, 0xe9, 0xf5, 0xf5, 0xf5, 0x6d,
- 0xad, 0xad, 0x83, 0x83, 0x83, 0xc0, 0x99, 0xa1, 0xc1, 0x41, 0xe0, 0x1b, 0x9d, 0x4e, 0x6f, 0x05,
- 0x50, 0xa9, 0x7d, 0xbd, 0x7d, 0x33, 0x92, 0x9f, 0x4d, 0xef, 0x31, 0x20, 0xde, 0xc0, 0x40, 0x3f,
- 0x7c, 0x5a, 0x47, 0x47, 0x07, 0x95, 0x4a, 0x85, 0xcf, 0xac, 0xae, 0xae, 0xa9, 0xa8, 0xa8, 0x28,
- 0x66, 0x55, 0xde, 0x16, 0x40, 0x60, 0x95, 0x95, 0x95, 0x95, 0x9e, 0x91, 0x91, 0x96, 0x9e, 0x9e,
- 0x9a, 0x9a, 0x9a, 0x02, 0x48, 0x4d, 0xcd, 0xc8, 0xc8, 0x28, 0x29, 0x29, 0x69, 0x6f, 0x6b, 0x43,
- 0x94, 0x16, 0x6e, 0x90, 0xa4, 0xc4, 0xa4, 0xc9, 0x6b, 0x40, 0xcf, 0x12, 0x20, 0xaa, 0x7a, 0x7a,
- 0x7a, 0xce, 0xce, 0x2e, 0xab, 0x57, 0xaf, 0x06, 0xf6, 0x7e, 0xf7, 0x1d, 0x9a, 0xec, 0x9a, 0x4b,
- 0x70, 0x12, 0xb0, 0x20, 0xaa, 0x1a, 0x1a, 0x1a, 0xa0, 0xae, 0x66, 0x66, 0x66, 0x5c, 0xcb, 0x5d,
- 0x38, 0xe0, 0xe1, 0xe1, 0xd1, 0xd3, 0xd7, 0xff, 0xf7, 0xc9, 0x93, 0x3e, 0xde, 0xbe, 0x0f, 0x1e,
- 0x3c, 0x4c, 0x48, 0x48, 0x28, 0x28, 0x28, 0xa8, 0xab, 0xab, 0x87, 0x10, 0xec, 0x5d, 0xe6, 0x10,
- 0x18, 0x1e, 0x1a, 0x06, 0x66, 0x56, 0x52, 0x28, 0x65, 0x65, 0x65, 0xe5, 0x00, 0xf8, 0x55, 0x5a,
- 0x0a, 0x4c, 0x03, 0xca, 0x01, 0x6f, 0x47, 0x67, 0x2e, 0x4e, 0x78, 0xf5, 0xe2, 0xc5, 0x0b, 0x06,
- 0x63, 0xa0, 0x9b, 0xde, 0xdd, 0xde, 0xde, 0xd6, 0xd8, 0xd8, 0x58, 0x53, 0x53, 0x03, 0x1f, 0x53,
- 0x90, 0x5f, 0x90, 0x99, 0x91, 0x99, 0x94, 0x9c, 0x1c, 0x1b, 0x17, 0x1f, 0x1d, 0x1d, 0x13, 0x19,
- 0x19, 0x19, 0x1e, 0xf1, 0x24, 0x2c, 0x3c, 0x02, 0xd9, 0x42, 0xd9, 0x1b, 0x20, 0x2e, 0x2e, 0xbe,
- 0xa8, 0xa8, 0x08, 0x48, 0x8e, 0x3c, 0x86, 0x06, 0x92, 0x0b, 0x9d, 0xf8, 0x9c, 0xb7, 0x2a, 0x84,
- 0x5d, 0xb6, 0xb6, 0x5b, 0xad, 0xad, 0x6d, 0xa0, 0x49, 0xd1, 0x65, 0xc4, 0xe7, 0x16, 0x48, 0x46,
- 0x8b, 0x97, 0x97, 0x17, 0x04, 0xd6, 0xd8, 0xd8, 0xd8, 0xd1, 0xd1, 0x91, 0x6b, 0xb9, 0xcb, 0x78,
- 0x2c, 0xe3, 0xe7, 0xdf, 0xba, 0x6d, 0xdb, 0xa9, 0x33, 0x67, 0x7c, 0x7d, 0x7c, 0x03, 0x03, 0xef,
- 0x81, 0x31, 0x48, 0x4f, 0x4f, 0x07, 0xed, 0x02, 0xca, 0x75, 0xd1, 0xe9, 0x43, 0x43, 0xc3, 0x33,
- 0x16, 0x5f, 0xbd, 0x18, 0x79, 0x01, 0xde, 0xb2, 0xaa, 0xb2, 0xb2, 0xb4, 0xb4, 0x14, 0xe8, 0x5a,
- 0x5d, 0x5d, 0x0d, 0xe1, 0x1b, 0x04, 0x47, 0x33, 0x71, 0xf5, 0xb5, 0xc0, 0x02, 0xab, 0x99, 0x6c,
- 0x59, 0x06, 0xa1, 0xae, 0xaf, 0xab, 0x07, 0x5b, 0x52, 0x54, 0x58, 0x04, 0x72, 0x1a, 0x1f, 0x17,
- 0x1f, 0xf1, 0x24, 0x32, 0x24, 0x34, 0x3c, 0x38, 0x34, 0x2c, 0x38, 0x24, 0x94, 0xeb, 0x16, 0x12,
- 0x1a, 0x16, 0xf3, 0x34, 0x16, 0x48, 0x0b, 0x16, 0x02, 0x3e, 0x0a, 0xc4, 0x36, 0x20, 0x20, 0x40,
- 0x60, 0xd2, 0xc2, 0xe5, 0xb3, 0x04, 0xc8, 0x2c, 0x89, 0x44, 0x86, 0xde, 0x0a, 0xbc, 0x01, 0x1e,
- 0x8f, 0x87, 0x78, 0x16, 0xa2, 0x5a, 0xd4, 0x1b, 0xcc, 0x09, 0x90, 0x8c, 0x16, 0x06, 0x83, 0x61,
- 0x2f, 0xcb, 0x65, 0x0b, 0x2d, 0x3c, 0xe3, 0x80, 0xbb, 0x0c, 0x16, 0xeb, 0xee, 0xe1, 0x71, 0xee,
- 0xfc, 0xff, 0xb3, 0x77, 0x25, 0x40, 0x51, 0x9e, 0x69, 0x5a, 0x9a, 0x86, 0x96, 0xa3, 0x81, 0x06,
- 0x9b, 0xfb, 0xbe, 0x9b, 0x9b, 0x06, 0x69, 0xa0, 0x81, 0x46, 0x04, 0xb9, 0xef, 0x46, 0x6c, 0x4e,
- 0xc5, 0x08, 0x1a, 0x9d, 0x8a, 0x3b, 0x9b, 0xaa, 0x71, 0xa6, 0x6a, 0x92, 0xad, 0x49, 0x25, 0x66,
- 0x36, 0xd9, 0x35, 0xbb, 0xd9, 0x54, 0x8e, 0x29, 0x53, 0x93, 0x6c, 0x92, 0x9d, 0xac, 0x89, 0x07,
- 0x20, 0x28, 0x5e, 0x89, 0x78, 0x83, 0x47, 0x88, 0x8e, 0x20, 0x97, 0x1c, 0xa2, 0x80, 0x0a, 0x8a,
- 0x5c, 0x02, 0xba, 0x4f, 0xf7, 0x47, 0xff, 0x34, 0x88, 0xf4, 0x01, 0x6d, 0xd5, 0x2c, 0xfd, 0xd6,
- 0x5f, 0x14, 0x45, 0xff, 0xdd, 0xfc, 0xfd, 0xfd, 0xcf, 0xff, 0x7c, 0xcf, 0x7b, 0x7c, 0xef, 0xf7,
- 0x6f, 0x5f, 0xfc, 0xe5, 0x2f, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0x23, 0x47, 0x6b, 0x6b, 0x6b, 0xaf,
- 0x5e, 0xb9, 0xd2, 0xd8, 0xd8, 0xd8, 0xd5, 0xd5, 0x05, 0x4d, 0x3b, 0x3c, 0x3a, 0x26, 0x37, 0x7a,
- 0x00, 0xa8, 0x40, 0x05, 0x80, 0x69, 0xdb, 0x5a, 0x5a, 0x01, 0x3f, 0xe5, 0x72, 0x10, 0x70, 0xb2,
- 0x20, 0x5f, 0xc7, 0xc6, 0x1e, 0x3f, 0x7e, 0x7c, 0xbf, 0xbf, 0x1f, 0x92, 0xa0, 0xb5, 0xa5, 0x55,
- 0x4c, 0xb3, 0x97, 0x2f, 0x63, 0xde, 0x3f, 0x79, 0xf2, 0x27, 0x60, 0xb2, 0xf2, 0x70, 0x15, 0xa8,
- 0xf5, 0xc0, 0xa1, 0xf2, 0x03, 0x2f, 0xa0, 0x97, 0x80, 0x16, 0x04, 0x8f, 0xb7, 0xe3, 0xff, 0x42,
- 0xee, 0x0a, 0x85, 0x42, 0xd9, 0x2f, 0x48, 0xa3, 0xd3, 0x99, 0xa6, 0xa6, 0x46, 0x66, 0x66, 0xb4,
- 0x97, 0xb4, 0x9f, 0x55, 0xc4, 0x30, 0xaa, 0x89, 0x89, 0x49, 0x9b, 0x36, 0x6d, 0x22, 0xfb, 0x82,
- 0x91, 0x7a, 0x03, 0x8d, 0x36, 0x58, 0xa4, 0xc9, 0x12, 0x6c, 0x62, 0x62, 0x62, 0x69, 0x69, 0x99,
- 0x6c, 0xfb, 0xac, 0x79, 0x0d, 0xc3, 0x1e, 0xce, 0xe7, 0xbf, 0xf3, 0xee, 0xbb, 0x9f, 0x7c, 0xf2,
- 0xe9, 0x77, 0xdf, 0x7d, 0x87, 0xc9, 0x17, 0x2a, 0x11, 0x50, 0x01, 0x61, 0x76, 0xdc, 0xee, 0x00,
- 0x73, 0x02, 0x06, 0xe3, 0x4f, 0x27, 0xe4, 0x22, 0x50, 0xb2, 0x82, 0x66, 0xf4, 0xd1, 0xe0, 0xa0,
- 0x82, 0xd4, 0x3a, 0xff, 0x87, 0x4c, 0x89, 0xa1, 0x3b, 0x0e, 0xe8, 0x0e, 0x3e, 0xea, 0xef, 0xeb,
- 0x03, 0x74, 0xdb, 0xdb, 0xda, 0x9b, 0x1a, 0x9b, 0x1a, 0x7e, 0xfd, 0xb5, 0xbe, 0xbe, 0x1e, 0x02,
- 0xfb, 0xa7, 0x9f, 0x7f, 0x3e, 0x76, 0xfc, 0xf8, 0xe1, 0xaa, 0xaa, 0x83, 0x87, 0x2a, 0xe6, 0x82,
- 0xb6, 0xa6, 0xe6, 0x56, 0x73, 0x33, 0x04, 0x06, 0x2e, 0xe3, 0xf3, 0x2f, 0xbe, 0xb0, 0x94, 0xf1,
- 0x34, 0xe9, 0x0c, 0x86, 0xb3, 0xb7, 0x77, 0x4c, 0x62, 0x22, 0x3f, 0x26, 0xc6, 0xce, 0xd5, 0x95,
- 0xa6, 0x6a, 0x65, 0x0b, 0x80, 0xba, 0x71, 0xe3, 0x46, 0x3c, 0x0e, 0x7e, 0x7e, 0x7e, 0x64, 0xe1,
- 0xad, 0x86, 0x66, 0x17, 0x69, 0x84, 0x60, 0x6d, 0x6d, 0x6d, 0x21, 0xb7, 0x8a, 0x8b, 0x8b, 0x63,
- 0x63, 0xe3, 0xe4, 0xbe, 0xc5, 0xd8, 0xd8, 0xf8, 0xb5, 0xd2, 0xd2, 0xcf, 0x3e, 0xfb, 0x7c, 0xff,
- 0x8f, 0xfb, 0x4f, 0x9d, 0x3a, 0x75, 0xa5, 0xfe, 0x72, 0xf3, 0xad, 0x66, 0xf8, 0x32, 0x70, 0xd5,
- 0x47, 0x46, 0x47, 0xc5, 0x05, 0xae, 0x2a, 0xe3, 0x6f, 0x71, 0x06, 0x67, 0x0c, 0xf0, 0x23, 0x85,
- 0xe2, 0x7d, 0x12, 0xf4, 0xde, 0x6e, 0x6f, 0x6f, 0x6c, 0x6a, 0x82, 0x4c, 0xae, 0xaf, 0xab, 0x3f,
- 0x5d, 0x5b, 0x7b, 0xf4, 0xd8, 0xb1, 0x43, 0x15, 0x15, 0x14, 0xe5, 0xe2, 0x17, 0x80, 0xb9, 0xbb,
- 0xab, 0x73, 0x62, 0x62, 0xb2, 0xa3, 0xa3, 0x23, 0x2d, 0x2d, 0x4d, 0x16, 0x4e, 0x5a, 0x34, 0x9a,
- 0xa7, 0x8f, 0x4f, 0x4a, 0x56, 0x96, 0x50, 0x24, 0x12, 0xac, 0x8b, 0xb7, 0xb4, 0xb7, 0xd3, 0x56,
- 0xbe, 0x35, 0x01, 0x08, 0x41, 0x20, 0x88, 0x86, 0x0b, 0x16, 0x13, 0xb3, 0xd6, 0xc5, 0xc5, 0x85,
- 0x2c, 0xae, 0xd1, 0xd0, 0xac, 0xca, 0x46, 0x08, 0x16, 0x9e, 0x32, 0x87, 0xc3, 0x49, 0x4e, 0x4e,
- 0x2e, 0x2b, 0xdb, 0x0a, 0x34, 0xca, 0x7d, 0x17, 0x78, 0xe3, 0x3f, 0x3f, 0xfe, 0xb8, 0xbc, 0xbc,
- 0xe2, 0xe2, 0x85, 0x8b, 0xd0, 0x9f, 0xbd, 0xf7, 0x7a, 0xe1, 0xe9, 0x3f, 0x9d, 0x90, 0x4f, 0xaa,
- 0xaf, 0xcc, 0xc4, 0x42, 0x77, 0x62, 0x62, 0x6c, 0x64, 0xf4, 0xf1, 0x23, 0x68, 0x86, 0xfb, 0x3d,
- 0x3d, 0x3d, 0xed, 0x80, 0x6e, 0x63, 0xe3, 0xd5, 0xab, 0xd7, 0xa0, 0xb7, 0x8f, 0x1c, 0xa9, 0x39,
- 0x78, 0xa8, 0x9c, 0x02, 0x2d, 0xd4, 0xef, 0x7d, 0x89, 0x84, 0xde, 0xfb, 0xe5, 0x97, 0x96, 0x2f,
- 0xa8, 0x59, 0x63, 0x33, 0xb3, 0xc8, 0xd8, 0x58, 0x61, 0x5e, 0x7e, 0xfa, 0xfa, 0xf5, 0xde, 0x5c,
- 0xae, 0x9e, 0xa1, 0xe1, 0x0a, 0x25, 0xf1, 0x66, 0x64, 0x64, 0x04, 0x9a, 0x15, 0x89, 0x44, 0xc1,
- 0xc1, 0xc1, 0xa4, 0x29, 0x87, 0xc6, 0x05, 0x53, 0xd9, 0x08, 0xc1, 0xc2, 0x93, 0x0d, 0x0b, 0x0b,
- 0x2b, 0x2e, 0xde, 0xb8, 0x76, 0xed, 0xda, 0xb9, 0x73, 0x16, 0xee, 0xce, 0xec, 0x1b, 0x84, 0x13,
- 0xd2, 0x33, 0x32, 0xf6, 0xef, 0x3f, 0x50, 0x5f, 0x57, 0x07, 0x27, 0xfd, 0xd1, 0xe0, 0xa3, 0xa7,
- 0x62, 0x01, 0xb0, 0xa4, 0x78, 0x93, 0x1c, 0x52, 0xec, 0x4d, 0x1f, 0x2a, 0x7e, 0xd4, 0xd4, 0x14,
- 0x7c, 0xb4, 0x91, 0x91, 0x91, 0xc1, 0xc1, 0x01, 0xc8, 0x95, 0xce, 0x8e, 0x4e, 0x48, 0x17, 0xa8,
- 0x85, 0x93, 0x27, 0x4f, 0x96, 0x57, 0x54, 0x12, 0xd0, 0xc2, 0x53, 0xbb, 0x76, 0xed, 0xda, 0xd0,
- 0xe3, 0x21, 0x70, 0x32, 0x1e, 0xdb, 0x17, 0xe1, 0xc4, 0xd0, 0xd7, 0x0b, 0x58, 0x1d, 0x92, 0x96,
- 0x93, 0x03, 0xdc, 0x06, 0xf3, 0xf9, 0xcc, 0x17, 0x5a, 0x36, 0xc9, 0x35, 0x48, 0x82, 0xed, 0xdb,
- 0xb7, 0x27, 0x24, 0x24, 0x78, 0x7a, 0x7a, 0x42, 0x80, 0x69, 0x7a, 0x26, 0xab, 0x66, 0x24, 0x06,
- 0x8b, 0x01, 0x24, 0x04, 0x5b, 0x52, 0x52, 0x32, 0x27, 0x65, 0xa0, 0x45, 0xa7, 0xeb, 0xe8, 0xeb,
- 0x6b, 0xcd, 0x76, 0x3d, 0xf0, 0x96, 0x8f, 0x3e, 0xfa, 0x8f, 0xf3, 0xe7, 0xcf, 0x77, 0x75, 0x76,
- 0x0e, 0x3d, 0x79, 0xb2, 0x84, 0x0b, 0xb2, 0x9e, 0xcd, 0xb6, 0x29, 0x99, 0x63, 0x3e, 0x53, 0xee,
- 0x93, 0x27, 0x27, 0x27, 0xc6, 0xc7, 0xc7, 0x40, 0xb9, 0xf7, 0xee, 0xde, 0x6d, 0x6b, 0x6b, 0x6d,
- 0x68, 0x68, 0xf8, 0xf9, 0xf4, 0x69, 0x0a, 0xb4, 0x47, 0x6b, 0x8e, 0xb5, 0xb6, 0xb6, 0x0e, 0x0f,
- 0x0f, 0xef, 0xdb, 0xb7, 0x6f, 0xde, 0x34, 0x9f, 0x2e, 0x83, 0xe1, 0xe6, 0xed, 0x9d, 0x98, 0x91,
- 0x99, 0x25, 0xca, 0x03, 0x68, 0xf5, 0x98, 0xca, 0x6d, 0x29, 0x8e, 0x41, 0xcb, 0xcb, 0xcb, 0x2b,
- 0x2a, 0x2a, 0x22, 0x91, 0x2e, 0x43, 0x43, 0x43, 0x0d, 0xcd, 0xaa, 0x60, 0x54, 0x4f, 0x78, 0x1e,
- 0x8f, 0x07, 0x05, 0x4b, 0xed, 0xd1, 0x39, 0xfd, 0xaa, 0xb6, 0xb6, 0x11, 0x9b, 0xcd, 0xb6, 0xb3,
- 0xa3, 0xcf, 0xbe, 0x83, 0x41, 0xc1, 0xc1, 0x55, 0x55, 0x55, 0x6d, 0x6d, 0x6d, 0x4f, 0x86, 0x87,
- 0x97, 0xb0, 0x96, 0x60, 0x4e, 0x7b, 0x6d, 0x92, 0xfc, 0x9a, 0x9c, 0x92, 0x35, 0xc9, 0xdf, 0xe7,
- 0xc2, 0xf8, 0xb9, 0x52, 0xec, 0x8b, 0x4f, 0x19, 0x1b, 0x1b, 0x1d, 0x78, 0x38, 0xd0, 0x2d, 0x69,
- 0xb4, 0x58, 0x5b, 0x5b, 0x0b, 0x82, 0x05, 0x62, 0x21, 0x12, 0xce, 0x9e, 0x3d, 0xd7, 0xdf, 0x0f,
- 0xd7, 0xad, 0x2f, 0x2d, 0x3d, 0x7d, 0xde, 0xe1, 0xd2, 0xd1, 0xd5, 0xb5, 0x77, 0x75, 0x5d, 0x93,
- 0x98, 0x14, 0x97, 0x92, 0xea, 0x11, 0x10, 0xc0, 0x78, 0x79, 0xfe, 0x7a, 0x5e, 0x73, 0x72, 0x72,
- 0xda, 0xbe, 0x7d, 0x47, 0x72, 0x72, 0x8a, 0x97, 0x97, 0x17, 0x64, 0x98, 0x86, 0x66, 0x95, 0x35,
- 0x52, 0x45, 0x00, 0x47, 0xc0, 0xdd, 0xdd, 0x1d, 0xb3, 0xd5, 0x96, 0x2d, 0x5b, 0x3c, 0x3c, 0x3c,
- 0x66, 0xc6, 0x50, 0x4b, 0xcb, 0xc8, 0xcc, 0xcc, 0xd5, 0xd7, 0xd7, 0xc1, 0xd3, 0x83, 0x36, 0x7b,
- 0xef, 0xcb, 0x3f, 0xfd, 0xe9, 0x9d, 0x1b, 0x37, 0xfe, 0x3e, 0xa4, 0x6c, 0x30, 0x4a, 0x0e, 0x5c,
- 0x9f, 0x4f, 0x93, 0xaa, 0xd8, 0xf1, 0x9f, 0x82, 0xef, 0x26, 0x7b, 0xe0, 0x2f, 0x93, 0xe2, 0x5f,
- 0xf0, 0x93, 0x82, 0xf1, 0xb3, 0x29, 0xd9, 0x26, 0xf2, 0x4a, 0xfe, 0xb7, 0x49, 0xc9, 0x32, 0xde,
- 0x7b, 0xf7, 0x7a, 0x21, 0xc2, 0xcf, 0x9e, 0x3b, 0x07, 0x5f, 0x0c, 0xa0, 0x3d, 0x5c, 0x55, 0x7d,
- 0xfd, 0xfa, 0x75, 0xd0, 0x6c, 0x45, 0x45, 0xc5, 0xcb, 0x06, 0x0d, 0x4f, 0xb1, 0xa5, 0xbd, 0x3d,
- 0x4f, 0x20, 0xe0, 0xf2, 0x23, 0x6c, 0x9d, 0x9d, 0xe9, 0xca, 0x04, 0x10, 0x56, 0xae, 0x5c, 0x99,
- 0x92, 0x92, 0xb2, 0x69, 0xd3, 0xa6, 0xf0, 0xf0, 0x70, 0x92, 0x50, 0xd0, 0x04, 0x0d, 0x94, 0x32,
- 0x52, 0xa6, 0x65, 0x61, 0x61, 0xb9, 0x7a, 0xf5, 0xea, 0xfc, 0xfc, 0x7c, 0xb8, 0xc9, 0xb2, 0x3e,
- 0xd7, 0x4a, 0x43, 0x43, 0xc0, 0x95, 0xcb, 0xe7, 0xdb, 0xb8, 0xb9, 0xca, 0xea, 0x58, 0x8c, 0xf6,
- 0xd1, 0x9a, 0x9a, 0x47, 0x8f, 0x1e, 0x2f, 0xad, 0x93, 0x45, 0xf1, 0x2a, 0x81, 0x2b, 0x64, 0x67,
- 0x5f, 0x7f, 0x7f, 0x47, 0x67, 0xd7, 0xed, 0x0e, 0x08, 0xcf, 0xae, 0x9e, 0xbb, 0xf7, 0x1e, 0x3c,
- 0x1c, 0x10, 0x47, 0x21, 0x26, 0x26, 0x9f, 0x4e, 0x4c, 0x63, 0x78, 0x82, 0xe2, 0x5f, 0x15, 0x71,
- 0x2b, 0x4e, 0x61, 0x3c, 0x7c, 0xf0, 0xa0, 0xb5, 0xb5, 0x0d, 0xfe, 0x63, 0x55, 0x55, 0x35, 0x14,
- 0xc2, 0xe9, 0xda, 0xda, 0xee, 0xae, 0x2e, 0xc8, 0xdd, 0x8c, 0x8c, 0x8c, 0x05, 0x86, 0x8e, 0x65,
- 0x61, 0xe1, 0x19, 0x10, 0xe0, 0xe4, 0xe5, 0x65, 0x6c, 0x61, 0xa1, 0xa5, 0xcc, 0xe4, 0x0e, 0xa0,
- 0x96, 0x96, 0x96, 0xa5, 0xa7, 0xa7, 0x93, 0x84, 0x82, 0x66, 0x01, 0xa3, 0xe2, 0x46, 0x2d, 0xe3,
- 0xc2, 0x54, 0x15, 0x1b, 0x1b, 0x5b, 0x52, 0xb2, 0x19, 0x6e, 0x2c, 0x45, 0xb0, 0xda, 0x3a, 0x3a,
- 0x96, 0x4e, 0x4e, 0x80, 0xab, 0x3f, 0x2f, 0xd4, 0x48, 0xa6, 0x38, 0x16, 0x3e, 0xef, 0xfb, 0xef,
- 0xbf, 0x0f, 0x08, 0x2d, 0x6d, 0x61, 0xe1, 0xb3, 0xe7, 0xd3, 0x04, 0x0b, 0x0c, 0x02, 0x8d, 0xdd,
- 0x77, 0x7a, 0xbe, 0xfe, 0xfa, 0x6b, 0x70, 0x11, 0x24, 0x1f, 0x97, 0xcb, 0x85, 0x4b, 0x98, 0x99,
- 0x99, 0xf9, 0xdb, 0xdf, 0xfe, 0xf3, 0xde, 0xbd, 0x5f, 0xd6, 0xd6, 0x9e, 0x69, 0x69, 0x6d, 0x1b,
- 0x1a, 0x7a, 0x22, 0xe1, 0xde, 0xa9, 0x19, 0x06, 0x9e, 0xb5, 0x69, 0x87, 0x12, 0xff, 0x7a, 0x62,
- 0x62, 0xe2, 0xd1, 0xa3, 0x47, 0xed, 0xed, 0xed, 0xf5, 0x97, 0x2f, 0x9f, 0x3a, 0x75, 0xea, 0xf4,
- 0xe9, 0xd3, 0x37, 0x6e, 0xdc, 0xc0, 0x5f, 0xfe, 0xf6, 0xb7, 0xef, 0xe7, 0xe9, 0x8d, 0x2c, 0xe3,
- 0x84, 0x1a, 0x9b, 0x9b, 0x9b, 0x3b, 0x3a, 0x1a, 0x59, 0x58, 0xd0, 0x94, 0x59, 0xdb, 0x08, 0x5e,
- 0x8d, 0x8f, 0x8f, 0xc7, 0x57, 0x8b, 0x88, 0x88, 0xd0, 0xec, 0x27, 0xae, 0x94, 0x51, 0x59, 0x03,
- 0x3c, 0xec, 0xd9, 0xd9, 0x42, 0x91, 0x28, 0x6f, 0x26, 0xaa, 0xa3, 0xa5, 0x65, 0xc0, 0x62, 0x71,
- 0xb8, 0xdc, 0x90, 0xc8, 0x28, 0x27, 0x0e, 0x87, 0x2e, 0x73, 0x47, 0xe2, 0x13, 0x12, 0x80, 0x99,
- 0xc5, 0x44, 0xfb, 0x5f, 0x86, 0x58, 0xa2, 0x07, 0x00, 0xbf, 0x87, 0x0f, 0x07, 0x76, 0xef, 0xde,
- 0x6d, 0x65, 0x65, 0xc5, 0x98, 0xcf, 0x5c, 0x5d, 0xdd, 0x72, 0x72, 0x72, 0x76, 0xef, 0x7e, 0xbf,
- 0xe6, 0xd8, 0xb1, 0xde, 0xbe, 0xbe, 0xa7, 0x00, 0xdc, 0xb4, 0x72, 0x90, 0x4a, 0x05, 0xe5, 0x51,
- 0x0b, 0x5a, 0x87, 0x3b, 0xd6, 0xd1, 0xd1, 0xf1, 0x4b, 0x43, 0x43, 0x5d, 0x5d, 0x9d, 0xa4, 0x48,
- 0xe6, 0x6e, 0x53, 0xd3, 0xad, 0x94, 0xd4, 0xd4, 0x59, 0x23, 0x46, 0xa3, 0xc1, 0x09, 0xd5, 0x33,
- 0x31, 0x5e, 0xc9, 0x34, 0xd4, 0x96, 0x48, 0x50, 0x1d, 0x03, 0x03, 0x3c, 0xf3, 0xf0, 0x5d, 0xb5,
- 0x94, 0x09, 0xd2, 0x42, 0x83, 0x81, 0x1f, 0x40, 0xb3, 0xde, 0xde, 0xde, 0x9a, 0xd2, 0x59, 0xc5,
- 0x0d, 0x93, 0x11, 0xa9, 0x7b, 0x91, 0x04, 0xb5, 0x8a, 0xe3, 0xe3, 0x13, 0xa8, 0xb6, 0xbd, 0x34,
- 0x1d, 0x1d, 0x1b, 0x17, 0x97, 0x20, 0x3e, 0x3f, 0x30, 0x2c, 0x9c, 0xc5, 0x66, 0x53, 0xe3, 0x69,
- 0x6d, 0x63, 0xb3, 0x67, 0xcf, 0x1e, 0x92, 0x88, 0x5f, 0x62, 0xc4, 0x12, 0x82, 0x95, 0xc8, 0xd4,
- 0x2b, 0x57, 0xaf, 0xc6, 0xc4, 0xc4, 0xcc, 0x0b, 0x57, 0xca, 0x8c, 0x8c, 0x8c, 0xfd, 0xfd, 0xfd,
- 0x71, 0xd9, 0xdf, 0x7c, 0xfb, 0xed, 0x83, 0x07, 0x0f, 0xc5, 0x88, 0x9d, 0x10, 0x1f, 0x93, 0x52,
- 0xa1, 0x4b, 0xca, 0x15, 0x15, 0xbf, 0x4c, 0xbc, 0xe1, 0xc9, 0xd0, 0x93, 0x3b, 0xdd, 0x77, 0x20,
- 0x6b, 0x6f, 0xde, 0xbc, 0xd9, 0xd1, 0x71, 0xfb, 0xe1, 0xc3, 0x87, 0x7b, 0xfe, 0x7d, 0x8f, 0x6c,
- 0x1f, 0x3c, 0xed, 0x95, 0x2b, 0xcd, 0x6c, 0x6d, 0x1d, 0x3c, 0x3c, 0x70, 0x58, 0x38, 0x3a, 0x88,
- 0xdd, 0x2e, 0x1a, 0x0d, 0x70, 0xd5, 0x35, 0x34, 0x64, 0xae, 0x32, 0xd3, 0x56, 0x38, 0x93, 0x0b,
- 0x5e, 0x85, 0x9a, 0xdd, 0xb8, 0x71, 0x23, 0xf4, 0x95, 0x26, 0x36, 0xab, 0xa0, 0x51, 0x95, 0xdb,
- 0xce, 0xce, 0xce, 0xeb, 0xd6, 0xad, 0xdb, 0xbc, 0x79, 0xb3, 0xb7, 0x4c, 0x77, 0x4a, 0x03, 0x53,
- 0x53, 0xef, 0xe0, 0xe0, 0x90, 0x28, 0x81, 0x13, 0xc7, 0x4b, 0x87, 0x5a, 0xb5, 0xa7, 0xa5, 0x95,
- 0x94, 0x94, 0xd4, 0xd0, 0xd0, 0x30, 0xb1, 0x44, 0x5d, 0x31, 0xe7, 0x22, 0x56, 0xe2, 0x4f, 0x01,
- 0x75, 0x70, 0xd8, 0x43, 0x42, 0x42, 0x16, 0x46, 0x2c, 0x31, 0x3d, 0x3d, 0x3d, 0x48, 0x1a, 0x08,
- 0x86, 0x1f, 0x7f, 0xfc, 0xf1, 0xd1, 0xe3, 0x21, 0x02, 0x5a, 0x22, 0x12, 0x66, 0xc4, 0xad, 0x32,
- 0xd7, 0x30, 0x0a, 0xf1, 0xdc, 0xdb, 0x0b, 0xb8, 0x76, 0x75, 0x76, 0x0e, 0x3c, 0x1c, 0x80, 0xb8,
- 0xe5, 0xf3, 0xf9, 0xd4, 0xd7, 0x67, 0x18, 0x1b, 0xdb, 0x7b, 0x7a, 0x40, 0xbe, 0x72, 0x02, 0x02,
- 0x3c, 0x02, 0xfc, 0x6d, 0x5c, 0x5d, 0x75, 0x25, 0x64, 0x6b, 0x6a, 0x6d, 0x6d, 0xef, 0xe1, 0x61,
- 0x66, 0x6b, 0xa3, 0xf8, 0xf8, 0x63, 0xb4, 0x31, 0xe6, 0xc0, 0x2d, 0xf8, 0x56, 0x43, 0xb3, 0x8a,
- 0x18, 0xc6, 0x87, 0x2c, 0x8d, 0xf1, 0xf5, 0xf5, 0xc5, 0x24, 0x5b, 0x54, 0x54, 0x34, 0xb3, 0x9e,
- 0x94, 0x4e, 0xb7, 0x75, 0x71, 0x09, 0x8e, 0x88, 0x08, 0x0c, 0x0d, 0x33, 0x35, 0x67, 0x53, 0xb2,
- 0x0d, 0xd8, 0xf8, 0xef, 0x6f, 0xbe, 0x79, 0xf2, 0x64, 0x78, 0xc9, 0xe1, 0x2a, 0x45, 0xec, 0x33,
- 0x82, 0xd8, 0x86, 0x86, 0x5f, 0xa1, 0xf4, 0x14, 0x41, 0x2c, 0x85, 0x5b, 0x30, 0x95, 0x48, 0x24,
- 0xba, 0x78, 0xf1, 0x22, 0x71, 0xcd, 0x88, 0x48, 0x90, 0x11, 0xb6, 0x4a, 0x5c, 0xc6, 0xf8, 0xf8,
- 0x38, 0x49, 0xef, 0x0e, 0x0e, 0x0c, 0xf6, 0xf5, 0xf5, 0x96, 0x95, 0x96, 0x12, 0x2c, 0x41, 0x12,
- 0x18, 0xb2, 0xd9, 0xae, 0xbe, 0x3e, 0x9c, 0xc0, 0x40, 0x72, 0xb8, 0xfb, 0xfb, 0x99, 0xda, 0x58,
- 0x83, 0x63, 0xcd, 0x6d, 0x6c, 0x7c, 0x82, 0x83, 0xbd, 0x82, 0x57, 0xd3, 0x15, 0x5e, 0x93, 0x0b,
- 0x88, 0x0a, 0x85, 0x42, 0x0c, 0x3b, 0x7c, 0x07, 0xe8, 0x1f, 0x4d, 0xa5, 0x81, 0x5c, 0xa3, 0x0a,
- 0x09, 0x30, 0x31, 0xc1, 0x0b, 0x88, 0x8c, 0x8c, 0x9c, 0x7e, 0x01, 0x0a, 0xd6, 0xd4, 0xd4, 0x8b,
- 0x10, 0xac, 0xa7, 0x27, 0x35, 0xd3, 0x81, 0x90, 0x33, 0x32, 0x33, 0xbb, 0xba, 0xba, 0xd4, 0x94,
- 0x84, 0xa5, 0x10, 0x0b, 0x7a, 0x7c, 0xfc, 0x78, 0x68, 0xd7, 0xae, 0x5d, 0xb8, 0x3c, 0xc5, 0x41,
- 0x4b, 0x0c, 0x3a, 0xfc, 0xed, 0xb7, 0xff, 0xa5, 0xa5, 0xa5, 0x75, 0x5c, 0xdc, 0x0e, 0x69, 0x6a,
- 0xb6, 0x3b, 0xa6, 0x44, 0xcc, 0x76, 0x4a, 0x12, 0xa9, 0x18, 0x7e, 0xf2, 0x64, 0x74, 0x74, 0x74,
- 0xef, 0xde, 0xbd, 0x40, 0xd4, 0x0a, 0x09, 0x62, 0x99, 0x16, 0x16, 0x40, 0x29, 0x85, 0x58, 0x90,
- 0xad, 0x85, 0xa3, 0x23, 0xdc, 0x2e, 0x23, 0x16, 0x0b, 0xce, 0xe1, 0x9a, 0x84, 0x44, 0x67, 0x0e,
- 0x47, 0x71, 0xaa, 0xe4, 0x70, 0x38, 0xa5, 0xa5, 0x65, 0x92, 0x36, 0x9e, 0xae, 0x9a, 0xed, 0x3f,
- 0x16, 0x36, 0x92, 0xe7, 0x32, 0x31, 0x31, 0x71, 0x73, 0x73, 0x4b, 0x48, 0x48, 0x28, 0x2b, 0xdb,
- 0x4a, 0xed, 0xd6, 0x8d, 0xf1, 0xb7, 0x72, 0x76, 0x9e, 0x26, 0x58, 0x99, 0xf2, 0x2d, 0xdc, 0xb5,
- 0xca, 0xca, 0xc3, 0xea, 0x5b, 0xc6, 0x05, 0x44, 0x91, 0xd0, 0x16, 0x90, 0x06, 0xb4, 0x55, 0x56,
- 0x56, 0x62, 0xde, 0x54, 0x16, 0xb1, 0x30, 0xcc, 0x14, 0x09, 0x89, 0x89, 0xc7, 0x4f, 0x9c, 0x78,
- 0x3c, 0xf4, 0x64, 0x5a, 0x21, 0xc8, 0xba, 0x63, 0xca, 0x5c, 0x12, 0x09, 0xfa, 0x36, 0x37, 0x37,
- 0x47, 0x45, 0x09, 0xc8, 0xa8, 0x19, 0xac, 0x5a, 0xe5, 0xe6, 0xe7, 0x4b, 0x21, 0xd6, 0xcd, 0xcf,
- 0x0f, 0x7a, 0x80, 0xf8, 0x5c, 0x5e, 0x01, 0x01, 0xa9, 0xc2, 0x1c, 0x41, 0x5c, 0x9c, 0xbe, 0x02,
- 0x25, 0x19, 0xc4, 0x40, 0xb3, 0xe0, 0x58, 0x4c, 0x70, 0x01, 0x01, 0x01, 0xe6, 0xe6, 0xe6, 0x9a,
- 0x5d, 0x96, 0x16, 0x30, 0xd2, 0x3d, 0xc3, 0xc2, 0xc2, 0x22, 0x30, 0x30, 0x70, 0xfd, 0xfa, 0xdc,
- 0x99, 0x0d, 0x5b, 0x25, 0x04, 0xeb, 0xe1, 0xef, 0x0f, 0x82, 0xf5, 0xf0, 0xf3, 0xa3, 0xcb, 0xb8,
- 0x12, 0x79, 0x79, 0x79, 0x3d, 0x3d, 0x77, 0xd5, 0x57, 0xe5, 0x32, 0x9d, 0x3e, 0x90, 0xe6, 0x0e,
- 0x1e, 0x3c, 0x1c, 0xd8, 0xb1, 0x63, 0x07, 0x98, 0x47, 0x35, 0xd0, 0xc2, 0x29, 0xfb, 0xec, 0xf3,
- 0xcf, 0xef, 0xf5, 0xf6, 0x51, 0xb1, 0x2f, 0xe5, 0x05, 0xc2, 0xb4, 0x0d, 0x0d, 0x0d, 0x65, 0x65,
- 0x65, 0x11, 0xf6, 0xd3, 0x35, 0x30, 0x70, 0xf0, 0x70, 0xe7, 0x04, 0x06, 0x00, 0xae, 0x18, 0x25,
- 0x2b, 0x67, 0x27, 0x5d, 0x69, 0xce, 0x8b, 0x65, 0x6e, 0x9e, 0x96, 0x93, 0x93, 0x99, 0xbb, 0xc1,
- 0x85, 0xc3, 0x51, 0xbc, 0x48, 0x06, 0x58, 0x2d, 0x2b, 0x2b, 0x8b, 0x8a, 0x8a, 0xd2, 0xec, 0x27,
- 0xbe, 0xb0, 0x91, 0xad, 0xb8, 0x30, 0x4a, 0x18, 0x2b, 0x10, 0x2c, 0xe5, 0x73, 0x81, 0x60, 0x2d,
- 0x1c, 0x1c, 0x02, 0x42, 0x43, 0x57, 0x47, 0x46, 0x5a, 0x3a, 0x38, 0x50, 0xe7, 0xeb, 0xe8, 0xea,
- 0x56, 0x57, 0x1f, 0x59, 0x92, 0x5d, 0x33, 0x16, 0x30, 0x02, 0x28, 0x2a, 0xdb, 0x75, 0xf1, 0xd2,
- 0x25, 0xdc, 0x50, 0x15, 0x10, 0x4b, 0x40, 0xeb, 0xe8, 0xe8, 0x08, 0x85, 0xd0, 0xdd, 0xdd, 0x4d,
- 0xc2, 0x08, 0x93, 0x53, 0xaa, 0xf8, 0x62, 0xcf, 0x25, 0xd1, 0xda, 0x0f, 0x3f, 0xfc, 0x90, 0x6c,
- 0x55, 0x46, 0xd3, 0xd6, 0x66, 0x9a, 0x99, 0xd9, 0xb8, 0xba, 0xd8, 0xba, 0xba, 0x82, 0x5d, 0xc5,
- 0x3e, 0xa9, 0x4c, 0x7e, 0x30, 0x36, 0x29, 0x79, 0x43, 0x51, 0x51, 0x58, 0x74, 0x34, 0x63, 0x76,
- 0x7e, 0x70, 0x01, 0xc3, 0x75, 0x6e, 0xdd, 0xba, 0x2d, 0x35, 0x35, 0x95, 0xc3, 0x11, 0x27, 0x6d,
- 0x35, 0xfe, 0xd7, 0xbc, 0x46, 0x85, 0x61, 0xa1, 0xa3, 0x30, 0x56, 0x5b, 0xb6, 0x94, 0x4e, 0xc7,
- 0xc9, 0xb5, 0xb4, 0x56, 0x1a, 0x1b, 0x3b, 0x79, 0x79, 0x05, 0x47, 0x44, 0xfa, 0xf3, 0x78, 0x74,
- 0x99, 0xea, 0x02, 0x51, 0x41, 0x41, 0x6f, 0x6f, 0xaf, 0xba, 0x90, 0x2a, 0xb5, 0x67, 0xcf, 0x67,
- 0xd1, 0xec, 0xe8, 0xd8, 0xf8, 0x57, 0x5f, 0x7d, 0x8d, 0x6b, 0x53, 0x0d, 0xb4, 0x0c, 0x71, 0x2e,
- 0xcf, 0xe2, 0xf5, 0xd7, 0x5f, 0xbf, 0xd3, 0xd3, 0x23, 0x4e, 0x34, 0x4c, 0xa8, 0x28, 0x0f, 0x70,
- 0x6e, 0x5d, 0x5d, 0x1d, 0xbc, 0xce, 0xe9, 0xd1, 0xa3, 0xd1, 0x30, 0xf5, 0xe0, 0xa0, 0xbd, 0x10,
- 0x8f, 0x72, 0xf1, 0xf2, 0x12, 0x15, 0x17, 0xc7, 0xa7, 0xa5, 0xad, 0x92, 0xe8, 0x5e, 0x05, 0x2d,
- 0x21, 0x21, 0x11, 0xda, 0x80, 0xc7, 0xe3, 0xc1, 0x79, 0xd4, 0xd7, 0xd7, 0xd7, 0x08, 0x83, 0x17,
- 0x0d, 0x88, 0x25, 0xce, 0x75, 0x48, 0x48, 0x08, 0xc6, 0x2a, 0x2e, 0x2e, 0x8e, 0x4c, 0x46, 0x90,
- 0xb6, 0x2c, 0x6b, 0x6b, 0x2f, 0x6e, 0x10, 0x24, 0x81, 0x8b, 0x4c, 0xa4, 0x0b, 0x27, 0x7f, 0xf7,
- 0xdd, 0xff, 0x2c, 0xd5, 0x3e, 0x2f, 0x72, 0xe1, 0x21, 0xa6, 0x59, 0x71, 0x1e, 0x41, 0xac, 0x66,
- 0x47, 0x46, 0x46, 0xcb, 0xb6, 0x6e, 0xc5, 0x05, 0xa8, 0x0c, 0x5a, 0x00, 0x3e, 0x3b, 0x3b, 0xfb,
- 0xee, 0xdd, 0x7b, 0x54, 0xb4, 0x56, 0x05, 0x79, 0xf0, 0xe0, 0xc1, 0x03, 0x6f, 0x05, 0x36, 0xa6,
- 0xc1, 0x4c, 0xb4, 0xbe, 0xa0, 0x30, 0x3d, 0x37, 0xd7, 0xc1, 0xd5, 0x55, 0x71, 0x61, 0x80, 0x1b,
- 0xb1, 0x6d, 0xdb, 0xb6, 0xb8, 0xb8, 0x75, 0x94, 0xff, 0xa5, 0xda, 0x6d, 0xfd, 0x7f, 0x6c, 0xc0,
- 0x27, 0xe9, 0x07, 0x0b, 0xac, 0xc2, 0x57, 0xb5, 0xb7, 0xb7, 0x27, 0x33, 0x91, 0x0e, 0x60, 0xec,
- 0xe2, 0xe2, 0x0f, 0x49, 0x10, 0x15, 0x65, 0x20, 0x53, 0xfc, 0xb9, 0x3e, 0x37, 0x57, 0xbc, 0x0d,
- 0x87, 0x1a, 0x71, 0x3a, 0x63, 0x54, 0x31, 0xcc, 0xa4, 0x84, 0x15, 0x01, 0xb1, 0x8e, 0xce, 0x4e,
- 0x3e, 0x9f, 0xaf, 0x32, 0x62, 0x89, 0xa5, 0xa5, 0xa5, 0x35, 0x36, 0x35, 0x8d, 0x3f, 0x9d, 0x50,
- 0x4d, 0xd3, 0x42, 0x0e, 0x09, 0xa2, 0xa3, 0xe5, 0xce, 0xd7, 0xd0, 0x5a, 0x69, 0xc2, 0x9c, 0x9c,
- 0x82, 0x02, 0xaf, 0xc0, 0x00, 0x9a, 0xc2, 0x8a, 0xd4, 0xc0, 0xc0, 0x00, 0x3a, 0x19, 0xae, 0x04,
- 0xf1, 0xbf, 0x18, 0x9a, 0x6a, 0xae, 0xd9, 0x46, 0xc2, 0xb0, 0x6c, 0x36, 0xdb, 0xcf, 0xcf, 0x4f,
- 0x28, 0x14, 0x66, 0x67, 0x0b, 0xa7, 0x37, 0x93, 0xa5, 0xd1, 0xf4, 0x58, 0x2c, 0x07, 0x8e, 0x27,
- 0x10, 0xeb, 0x1b, 0x12, 0x42, 0xcd, 0x4d, 0x10, 0x5a, 0x7f, 0x7e, 0xff, 0xcf, 0x83, 0x83, 0x83,
- 0xea, 0x45, 0xaa, 0x8c, 0x49, 0x4b, 0x0d, 0xa7, 0x08, 0x68, 0x47, 0xc7, 0xc6, 0xf6, 0xed, 0xfb,
- 0xc1, 0xc6, 0xc6, 0x66, 0x31, 0x88, 0x05, 0x2a, 0xd2, 0xd3, 0xd3, 0x2f, 0xd5, 0xd5, 0x8d, 0x8d,
- 0x3f, 0x95, 0x56, 0x7f, 0x29, 0x01, 0x5a, 0x9c, 0xfd, 0xee, 0x7b, 0xef, 0xc9, 0x75, 0x8b, 0x30,
- 0x68, 0xfc, 0x98, 0x98, 0xf5, 0x85, 0x85, 0xdc, 0xf0, 0x70, 0x86, 0xbe, 0xde, 0xc2, 0x27, 0x53,
- 0x86, 0x8f, 0xe5, 0x72, 0x83, 0x36, 0x6f, 0x16, 0x77, 0x3e, 0xb7, 0xb3, 0xb3, 0xd7, 0x54, 0x73,
- 0xcd, 0x31, 0x92, 0x99, 0xb5, 0xb3, 0xb3, 0xe3, 0xf3, 0x23, 0x36, 0x6d, 0x2a, 0xe1, 0xf1, 0x42,
- 0xc9, 0x34, 0xa4, 0x45, 0xa7, 0x1b, 0x59, 0x58, 0x38, 0x7b, 0x7b, 0xfb, 0x04, 0x07, 0xc3, 0xf9,
- 0xa2, 0x1e, 0x73, 0x38, 0xdd, 0x55, 0x55, 0x55, 0xaf, 0xb8, 0x37, 0x11, 0x89, 0x74, 0x91, 0xd8,
- 0x2c, 0x10, 0xd6, 0xd9, 0xd5, 0xb5, 0x71, 0xe3, 0xc6, 0x45, 0xd2, 0x2c, 0x3c, 0xf1, 0x94, 0x94,
- 0x94, 0xda, 0xda, 0x33, 0xe2, 0x4d, 0x16, 0x94, 0x94, 0x07, 0x38, 0xe5, 0xe2, 0xc5, 0x8b, 0x0c,
- 0x79, 0xe5, 0x2e, 0x18, 0x34, 0x47, 0x0f, 0x0f, 0x08, 0x03, 0x5e, 0x54, 0x94, 0xbe, 0x32, 0xc5,
- 0xde, 0xb8, 0x1d, 0xf8, 0x82, 0x49, 0x49, 0x49, 0xee, 0xee, 0x1e, 0x20, 0x10, 0x4d, 0xc4, 0x80,
- 0x32, 0xaa, 0x1a, 0xd6, 0xd3, 0xd3, 0x33, 0x39, 0x39, 0xb9, 0xa0, 0xa0, 0x10, 0x0e, 0x35, 0x79,
- 0x89, 0xc6, 0x60, 0xb0, 0x6c, 0x6c, 0x1c, 0x39, 0x1c, 0x57, 0x5f, 0xdf, 0x95, 0x32, 0x55, 0xca,
- 0xb9, 0xb9, 0x1b, 0x20, 0x09, 0x5e, 0x71, 0xff, 0x37, 0x31, 0x62, 0x65, 0x52, 0x60, 0xc0, 0xd8,
- 0xb7, 0xdf, 0x7e, 0x8b, 0xdb, 0xba, 0x78, 0xd0, 0xc6, 0xc6, 0xc6, 0x9e, 0xae, 0xad, 0x1d, 0x9b,
- 0xd6, 0x07, 0x4a, 0x80, 0xf6, 0x7e, 0x7f, 0xbf, 0x6c, 0xa1, 0xfb, 0xcb, 0xcc, 0x94, 0xcd, 0xce,
- 0x16, 0x89, 0x78, 0xd1, 0x02, 0x03, 0x85, 0xa3, 0xb2, 0x2b, 0x24, 0xe5, 0x70, 0x78, 0x9a, 0x36,
- 0x6c, 0x10, 0x05, 0x06, 0x06, 0x62, 0xfa, 0xd3, 0x44, 0x0c, 0x28, 0x93, 0x86, 0x61, 0x49, 0x35,
- 0x6c, 0x41, 0x7c, 0x7c, 0x3c, 0x75, 0x17, 0xb4, 0xf5, 0xf4, 0x4c, 0xe0, 0x03, 0xb8, 0xb8, 0x98,
- 0xdb, 0xdb, 0x53, 0x25, 0xca, 0x10, 0x66, 0x6f, 0xec, 0xdc, 0xd9, 0xd7, 0xd7, 0xa7, 0x8e, 0x30,
- 0x2c, 0x99, 0xfb, 0x17, 0x78, 0x75, 0x4a, 0x1a, 0xe9, 0x02, 0xcd, 0x5e, 0xbf, 0x7e, 0x23, 0x31,
- 0x31, 0x71, 0x91, 0x88, 0x65, 0x48, 0xe4, 0x01, 0xfc, 0xcd, 0xf3, 0xe7, 0x2f, 0x4c, 0x47, 0x0f,
- 0x14, 0x06, 0xed, 0xc8, 0xc8, 0x88, 0x22, 0x88, 0x35, 0x32, 0x36, 0x4e, 0xca, 0xcc, 0x5c, 0x1d,
- 0x15, 0x69, 0xa8, 0xcc, 0x2a, 0x30, 0xdc, 0x97, 0x90, 0x10, 0x1e, 0xa6, 0xbc, 0x88, 0x88, 0x08,
- 0x5b, 0x5b, 0x5b, 0x4d, 0xc4, 0x80, 0x18, 0xb5, 0x03, 0xb2, 0x8b, 0x8b, 0x0b, 0xb0, 0x5a, 0x58,
- 0x58, 0x38, 0xb3, 0xbf, 0xbc, 0x96, 0x96, 0x38, 0x65, 0xcb, 0x66, 0xb3, 0xac, 0xad, 0x64, 0x63,
- 0x89, 0x4e, 0x4e, 0x4e, 0x7f, 0xfd, 0xeb, 0x57, 0xc3, 0xc3, 0x6a, 0x29, 0x24, 0x90, 0xf4, 0x28,
- 0x78, 0xe9, 0xa6, 0x09, 0xe2, 0xe2, 0xc3, 0x29, 0x29, 0xcd, 0x4a, 0x22, 0x5d, 0x7f, 0x7c, 0xeb,
- 0x2d, 0x5c, 0xfc, 0xe2, 0x41, 0x8b, 0x67, 0x16, 0xdf, 0xab, 0xbe, 0xbe, 0x5e, 0x29, 0xa6, 0x9d,
- 0x98, 0x98, 0x30, 0x59, 0xb0, 0xa1, 0x13, 0x31, 0x43, 0x26, 0x53, 0xb0, 0x6e, 0x5d, 0x60, 0x68,
- 0xa8, 0xa1, 0x32, 0x1c, 0xbb, 0x42, 0xb2, 0x23, 0x18, 0xee, 0x08, 0x84, 0x01, 0x7e, 0xc1, 0xd7,
- 0xd4, 0x08, 0x83, 0x15, 0xd2, 0xf5, 0x5c, 0x24, 0xcf, 0x25, 0x12, 0x89, 0x32, 0x33, 0x33, 0xf5,
- 0x65, 0xc0, 0x09, 0x7f, 0x8c, 0xce, 0x64, 0x02, 0xd0, 0xb2, 0x75, 0x9e, 0x51, 0x02, 0x41, 0x5d,
- 0x7d, 0xfd, 0xa4, 0x1a, 0xb6, 0x36, 0x00, 0x4a, 0xfa, 0xfb, 0xfb, 0x7a, 0xee, 0x74, 0x2f, 0x70,
- 0xce, 0x33, 0x69, 0x93, 0x43, 0x42, 0xb3, 0xfb, 0xf7, 0x1f, 0x70, 0x77, 0x77, 0x5f, 0x3c, 0x62,
- 0x89, 0x41, 0x9f, 0x9f, 0x38, 0x79, 0x72, 0x64, 0x64, 0x54, 0x41, 0x47, 0x0c, 0x67, 0xa4, 0xce,
- 0xae, 0x95, 0x9d, 0xd7, 0xf4, 0x0c, 0x0c, 0x82, 0x22, 0x22, 0xbc, 0xb8, 0x41, 0x06, 0x4a, 0xf6,
- 0xf6, 0x84, 0x54, 0x23, 0x11, 0x03, 0x5f, 0x5f, 0x3f, 0x53, 0x53, 0x4d, 0x2a, 0x61, 0xa6, 0x90,
- 0xc0, 0xd9, 0xd9, 0x39, 0x26, 0x66, 0x6d, 0x49, 0xc9, 0xe6, 0x80, 0x80, 0x80, 0x99, 0x97, 0xb5,
- 0xb5, 0xc5, 0x07, 0xc4, 0x00, 0x0e, 0xe9, 0x40, 0xe1, 0x2d, 0xe9, 0x19, 0x19, 0xb7, 0x6f, 0xdf,
- 0x56, 0x87, 0x24, 0x18, 0x1b, 0x1b, 0x6b, 0x69, 0x69, 0x81, 0x42, 0x5e, 0xa0, 0x80, 0x55, 0x1a,
- 0x34, 0x98, 0x8e, 0xcd, 0x36, 0x37, 0xb7, 0x08, 0x04, 0x82, 0xa5, 0x42, 0x2c, 0x1e, 0xde, 0xb0,
- 0xb0, 0xb0, 0xea, 0xea, 0xea, 0xe1, 0xe1, 0x11, 0x45, 0x40, 0x8b, 0x3f, 0xff, 0xeb, 0x07, 0x1f,
- 0xc8, 0x1d, 0x67, 0x7c, 0x2e, 0x27, 0x90, 0xeb, 0xe2, 0xe3, 0xa3, 0xc7, 0x7c, 0x61, 0xf1, 0xc2,
- 0x82, 0x06, 0x3e, 0x81, 0xc6, 0x06, 0xcd, 0xf2, 0x78, 0x3c, 0x4b, 0x4b, 0x4b, 0x4d, 0x8d, 0x01,
- 0x69, 0x5a, 0x68, 0x65, 0x65, 0x05, 0x82, 0xcd, 0xc9, 0xc1, 0xa3, 0x9c, 0x2b, 0x4b, 0xb0, 0xba,
- 0x4c, 0xa6, 0x21, 0x8b, 0xa5, 0xa3, 0xaf, 0x27, 0xbb, 0x5e, 0xc9, 0xc0, 0xc0, 0xf0, 0xcd, 0x37,
- 0xdf, 0x1c, 0x18, 0x18, 0x58, 0x72, 0xb8, 0x3e, 0x97, 0xec, 0xb0, 0x59, 0x5f, 0x57, 0x77, 0xe5,
- 0xca, 0x15, 0xf9, 0x88, 0x95, 0xc6, 0x66, 0x47, 0x47, 0xc7, 0x8a, 0x8a, 0x8a, 0x54, 0x28, 0xe8,
- 0x7a, 0x99, 0x61, 0x04, 0xa0, 0x1b, 0xab, 0xaa, 0xab, 0xc5, 0x4c, 0xab, 0x80, 0x3c, 0x38, 0x78,
- 0xf0, 0xa0, 0xdc, 0x71, 0xd6, 0x61, 0x30, 0xec, 0x3d, 0xdc, 0xad, 0x5d, 0x5d, 0x74, 0x15, 0x8e,
- 0x6e, 0x51, 0xc6, 0xe5, 0x72, 0x8b, 0x8b, 0x8b, 0xd7, 0xac, 0x59, 0xa3, 0x69, 0x81, 0x48, 0xd2,
- 0xb2, 0x2c, 0x16, 0x0b, 0xb3, 0x6a, 0x5c, 0x5c, 0xdc, 0xb6, 0x6d, 0xaf, 0xe3, 0x17, 0xd9, 0x97,
- 0x59, 0xd6, 0xd6, 0x0e, 0x9e, 0x9e, 0x16, 0x0e, 0x0e, 0xba, 0x32, 0x30, 0x76, 0x74, 0x74, 0xfc,
- 0xdf, 0x7d, 0xfb, 0xd4, 0x14, 0xd7, 0xea, 0xef, 0xef, 0x3f, 0x75, 0xea, 0xa7, 0x33, 0x67, 0xcf,
- 0x2e, 0x7c, 0xda, 0x4c, 0xd1, 0xac, 0x84, 0x66, 0xdf, 0xdb, 0xbd, 0x9b, 0xac, 0x98, 0x5e, 0x42,
- 0xd0, 0x86, 0x86, 0x86, 0x9e, 0x38, 0x71, 0x42, 0x11, 0x4d, 0x7b, 0xfe, 0xfc, 0x79, 0xb9, 0x43,
- 0x4d, 0xa3, 0xd3, 0xe1, 0xc0, 0x62, 0x3c, 0xe9, 0xca, 0xef, 0x6a, 0x07, 0x9f, 0x0b, 0x8f, 0x24,
- 0xa4, 0x2c, 0x1c, 0x0d, 0x22, 0x65, 0x97, 0xad, 0x30, 0xa0, 0x4a, 0x61, 0xe1, 0x90, 0xe6, 0x4b,
- 0x6c, 0xd6, 0xf3, 0xab, 0xad, 0x6d, 0xeb, 0xe6, 0xe6, 0xcf, 0xe3, 0x89, 0xe3, 0x5a, 0x32, 0x51,
- 0x44, 0x3f, 0x3f, 0x3f, 0x70, 0x20, 0x6e, 0xe2, 0x92, 0xc3, 0x15, 0x70, 0xe8, 0xee, 0xea, 0x3e,
- 0x7a, 0xb4, 0xe6, 0xcc, 0x99, 0x33, 0x72, 0xce, 0x9c, 0x59, 0xfc, 0x25, 0x56, 0xb3, 0x15, 0x15,
- 0x15, 0xf8, 0x16, 0x4b, 0x88, 0x58, 0x86, 0x44, 0x1e, 0xe0, 0x9b, 0x5e, 0xba, 0x74, 0x49, 0x6e,
- 0xf4, 0xe0, 0x97, 0x5f, 0x7e, 0x91, 0x3f, 0xd6, 0x50, 0x5f, 0x86, 0x86, 0xba, 0x26, 0x26, 0x4a,
- 0x2d, 0xfb, 0x22, 0x06, 0x56, 0xc1, 0xad, 0xc9, 0xce, 0x16, 0x7a, 0x79, 0x79, 0x99, 0x9a, 0x9a,
- 0x2e, 0xdb, 0x72, 0x59, 0x6a, 0xad, 0x81, 0xb7, 0xb7, 0x77, 0x4a, 0x4a, 0xca, 0xf6, 0xed, 0x3b,
- 0x6c, 0x6c, 0x66, 0x2d, 0xee, 0x80, 0x3f, 0x06, 0xac, 0x46, 0x27, 0x24, 0xf8, 0x05, 0x07, 0x53,
- 0x0b, 0x64, 0x24, 0x9d, 0xcd, 0x04, 0x3d, 0x3d, 0x3d, 0xea, 0x10, 0xb1, 0xf0, 0xbb, 0x9b, 0x9a,
- 0x6e, 0x55, 0x56, 0x56, 0x5d, 0xb8, 0x70, 0x41, 0x0e, 0x62, 0xa5, 0x52, 0x76, 0x52, 0xbc, 0x71,
- 0xed, 0x64, 0x4b, 0x6b, 0x9b, 0x9b, 0x9b, 0xdb, 0xd2, 0x22, 0x96, 0x98, 0x83, 0x83, 0xc3, 0xd9,
- 0x73, 0xe7, 0x16, 0x4e, 0x2e, 0xdc, 0xb8, 0xf1, 0x77, 0xf9, 0xa3, 0x2d, 0x09, 0x20, 0xae, 0x00,
- 0x5c, 0x55, 0x02, 0x5b, 0x4a, 0x4a, 0x6a, 0x5e, 0x5e, 0x3e, 0x94, 0xdb, 0x72, 0x4e, 0xd7, 0x82,
- 0x4e, 0x99, 0x4c, 0x26, 0xee, 0x88, 0x64, 0x5b, 0xae, 0x4d, 0xeb, 0xd6, 0xc5, 0xeb, 0xce, 0x5e,
- 0x40, 0xc7, 0x30, 0x36, 0xf6, 0x0e, 0x0e, 0x4e, 0x13, 0xe6, 0x04, 0x85, 0x87, 0x53, 0xd9, 0x70,
- 0x30, 0xcf, 0xae, 0x5d, 0xbb, 0x86, 0xd5, 0xb3, 0x40, 0x06, 0x6e, 0x17, 0xf8, 0xea, 0x50, 0x79,
- 0x05, 0xa4, 0xac, 0x3c, 0xc4, 0xce, 0x2a, 0x33, 0x18, 0x19, 0x1d, 0x5d, 0xbd, 0x7a, 0xb5, 0x3a,
- 0x10, 0x0b, 0x4f, 0x07, 0xae, 0x68, 0x4d, 0x4d, 0xcd, 0xf0, 0xcb, 0xa3, 0x07, 0x8d, 0x8d, 0x4d,
- 0x72, 0x47, 0x1b, 0xb2, 0x4a, 0x5c, 0x85, 0xa8, 0x40, 0xe4, 0x76, 0x5e, 0xe3, 0xf3, 0xf9, 0x45,
- 0x45, 0xc5, 0x70, 0xbe, 0x96, 0xed, 0x3a, 0x1a, 0xa2, 0x60, 0xd9, 0x6c, 0xb6, 0x8f, 0x8f, 0x4f,
- 0x7a, 0x7a, 0x46, 0x61, 0x61, 0x91, 0xb5, 0xf5, 0xdc, 0xd5, 0x73, 0x06, 0xab, 0x56, 0x71, 0xc3,
- 0xf9, 0xc2, 0xfc, 0x82, 0x10, 0x7e, 0x04, 0xe5, 0x79, 0x99, 0x98, 0x98, 0xfc, 0xf0, 0xc3, 0x8f,
- 0x6a, 0x2a, 0x88, 0x1d, 0x19, 0x19, 0xa9, 0xab, 0xab, 0x3b, 0x78, 0xa8, 0xfc, 0xea, 0xb5, 0x6b,
- 0x72, 0x4f, 0x7e, 0x46, 0x35, 0x31, 0x90, 0x14, 0xc6, 0x88, 0x44, 0x22, 0x75, 0x20, 0x96, 0x21,
- 0x91, 0x07, 0xe1, 0xe1, 0xe1, 0x47, 0x8e, 0x1c, 0x91, 0x84, 0xbc, 0xe6, 0x61, 0xda, 0xa6, 0xa6,
- 0xa6, 0x85, 0x49, 0x0f, 0xaf, 0x9a, 0xdb, 0xd9, 0xb9, 0xf9, 0xfa, 0x1a, 0x99, 0x99, 0xa9, 0xc6,
- 0xb1, 0x9e, 0x9e, 0x9e, 0x25, 0x25, 0xd3, 0x79, 0x84, 0xe5, 0xe9, 0x7c, 0x11, 0x05, 0x0b, 0x82,
- 0x8d, 0x8c, 0x8c, 0x84, 0xaa, 0x0f, 0x0b, 0x0b, 0xd7, 0x7d, 0x61, 0x85, 0x32, 0xcb, 0xd2, 0x92,
- 0x27, 0x10, 0xac, 0x2f, 0x28, 0x0c, 0x89, 0x88, 0xa4, 0xd4, 0x17, 0x54, 0xc4, 0xf9, 0x0b, 0x17,
- 0xd4, 0xb4, 0x8b, 0xf7, 0xd0, 0xd0, 0xd0, 0xb9, 0xf3, 0xe7, 0x0f, 0x1c, 0x2a, 0xbf, 0x7e, 0xfd,
- 0x86, 0x22, 0x88, 0x7d, 0x26, 0x6d, 0xbb, 0x81, 0x63, 0xd7, 0xae, 0xdf, 0xab, 0x09, 0xb1, 0x0c,
- 0x49, 0x46, 0x2c, 0x4a, 0x20, 0x38, 0x7e, 0xfc, 0xc4, 0xbc, 0xf2, 0xe0, 0x56, 0x73, 0xf3, 0xc2,
- 0xde, 0x10, 0x24, 0x81, 0x57, 0x70, 0x70, 0x70, 0x44, 0x84, 0x52, 0xf5, 0xb1, 0xb2, 0x06, 0x31,
- 0x50, 0x5a, 0x5a, 0x1a, 0x13, 0x13, 0x03, 0xb7, 0x77, 0x19, 0xf6, 0x91, 0xa3, 0x2a, 0xb7, 0xbd,
- 0xbd, 0x41, 0xb0, 0xe9, 0x42, 0x61, 0x8e, 0xd5, 0x8b, 0x23, 0x49, 0xa3, 0xad, 0xb2, 0xb5, 0x0d,
- 0x97, 0x54, 0x1c, 0x01, 0xb1, 0x54, 0x0f, 0x6a, 0x0c, 0xdd, 0xcd, 0x9b, 0x37, 0xd5, 0x21, 0x62,
- 0x61, 0x83, 0x83, 0x83, 0xb5, 0x67, 0xce, 0x80, 0x63, 0x6f, 0x35, 0xdd, 0x92, 0x8f, 0x58, 0x69,
- 0x2a, 0x81, 0x20, 0xf6, 0xe3, 0x8f, 0x3f, 0x56, 0x1f, 0x62, 0x09, 0x68, 0xf1, 0x74, 0xe3, 0x69,
- 0x7d, 0x4a, 0x3a, 0x77, 0xc8, 0x80, 0xb6, 0xb9, 0xa5, 0x45, 0x5f, 0x5f, 0x7f, 0x01, 0xd0, 0xd2,
- 0xb4, 0xb5, 0xa3, 0x13, 0x13, 0xe1, 0x11, 0xb0, 0xad, 0x55, 0x44, 0x2c, 0x2e, 0x60, 0xdb, 0xb6,
- 0xd7, 0xe3, 0xe3, 0xe3, 0xa9, 0x70, 0x81, 0x6a, 0x9f, 0xf3, 0x0f, 0x6a, 0xd4, 0xbe, 0x06, 0x50,
- 0x47, 0xf9, 0xf9, 0x05, 0x61, 0x61, 0x61, 0xf3, 0xe8, 0x22, 0x3a, 0x9d, 0x6d, 0x6f, 0xc7, 0x5f,
- 0xbb, 0x16, 0x88, 0x0d, 0x8d, 0x8a, 0xa2, 0x56, 0xce, 0xda, 0xda, 0xd9, 0x75, 0xab, 0x6d, 0xd9,
- 0xec, 0xfd, 0xfb, 0xf7, 0x4f, 0xfe, 0xf4, 0xd3, 0xc1, 0xf2, 0x8a, 0xb6, 0xb6, 0x76, 0x45, 0xce,
- 0xa7, 0xf2, 0x08, 0x00, 0xd0, 0x81, 0x03, 0x07, 0xd5, 0x8a, 0x58, 0x86, 0x44, 0x1e, 0x04, 0x05,
- 0x05, 0xdd, 0x6c, 0x6c, 0x7c, 0x2a, 0x53, 0x04, 0x0e, 0xd8, 0xb6, 0xb6, 0xb6, 0x5a, 0x58, 0x5a,
- 0x2e, 0x00, 0x5a, 0x6d, 0x3a, 0x3d, 0xb7, 0xa0, 0x30, 0x21, 0x35, 0xd5, 0x64, 0x11, 0xbb, 0x2c,
- 0x6d, 0xd9, 0x52, 0x9a, 0x9a, 0x9a, 0xea, 0xe1, 0xe1, 0x69, 0x62, 0xc2, 0x5a, 0x56, 0xd5, 0xdd,
- 0x54, 0x92, 0xcb, 0xdd, 0xdd, 0x1d, 0x1e, 0x28, 0x08, 0x16, 0x64, 0x3b, 0xcf, 0x69, 0x62, 0xc4,
- 0xda, 0x87, 0x46, 0xaf, 0xc9, 0xc9, 0x2f, 0x00, 0x6e, 0x19, 0x86, 0xd3, 0x55, 0x5b, 0x80, 0x77,
- 0x7f, 0x7f, 0xbf, 0x3a, 0xe0, 0x0a, 0xeb, 0xed, 0xed, 0x3d, 0x76, 0xfc, 0xc4, 0xc1, 0xf2, 0xf2,
- 0xee, 0xee, 0x85, 0xb2, 0xb4, 0x73, 0x10, 0x4b, 0xaa, 0x62, 0x2e, 0x5f, 0xbe, 0xac, 0x6e, 0xc4,
- 0x12, 0xe3, 0x72, 0xb9, 0xbf, 0x34, 0x34, 0xc8, 0xae, 0x22, 0x6f, 0xbf, 0x7d, 0xdb, 0xc7, 0xd7,
- 0x17, 0x7a, 0x09, 0x6e, 0xda, 0xbc, 0xf3, 0xb5, 0x3e, 0x93, 0x59, 0xb6, 0xe3, 0x37, 0x6b, 0x13,
- 0x12, 0x54, 0x08, 0xc6, 0x52, 0x56, 0x5c, 0xbc, 0x31, 0x2b, 0x2b, 0xcb, 0xdb, 0xdb, 0x9b, 0x04,
- 0xb8, 0x54, 0xfe, 0x9c, 0x7f, 0x38, 0x03, 0x62, 0x31, 0xb0, 0x98, 0xdc, 0xe1, 0x02, 0xe7, 0xe6,
- 0xe6, 0x46, 0x47, 0x47, 0xcf, 0x7f, 0x1e, 0x8d, 0x66, 0x6a, 0x6d, 0xb5, 0x3a, 0x32, 0x2a, 0x3b,
- 0x2f, 0x2f, 0x26, 0x31, 0xd1, 0x58, 0x8a, 0xea, 0x8c, 0xac, 0x2c, 0x35, 0x65, 0xbb, 0xc4, 0xc1,
- 0xd8, 0x3b, 0x77, 0x8e, 0x1c, 0xad, 0x39, 0x54, 0x5e, 0xde, 0xd3, 0x73, 0x47, 0x59, 0xc4, 0xde,
- 0xbb, 0x77, 0xef, 0xd5, 0x20, 0x16, 0x4c, 0x1b, 0x1b, 0x1b, 0x7b, 0xf1, 0xd2, 0xa5, 0x71, 0x71,
- 0x11, 0xb8, 0x98, 0x69, 0x3b, 0x3a, 0x3b, 0x13, 0x12, 0x13, 0xc9, 0x26, 0xb3, 0x8c, 0xf9, 0x76,
- 0x38, 0xf2, 0xe1, 0x72, 0xb7, 0xbf, 0xf1, 0x06, 0x97, 0xc7, 0x5b, 0xcc, 0x8d, 0x83, 0x77, 0x2c,
- 0x14, 0x0a, 0x7d, 0x7c, 0x7c, 0x97, 0xdb, 0x42, 0x45, 0x52, 0xb9, 0x0d, 0x49, 0x10, 0x1a, 0x1a,
- 0x9a, 0x97, 0x97, 0xe7, 0x20, 0xb3, 0x30, 0x76, 0x8e, 0x19, 0xae, 0x32, 0xf3, 0xe3, 0xf1, 0xd2,
- 0x72, 0x72, 0x12, 0x33, 0x32, 0x2d, 0xa4, 0xa1, 0xda, 0xd7, 0x4a, 0x4b, 0xd5, 0x87, 0xd8, 0x8e,
- 0x8e, 0x8e, 0xaa, 0xea, 0xea, 0x43, 0xe5, 0x15, 0x77, 0xef, 0xde, 0x55, 0x14, 0xb1, 0xd2, 0xca,
- 0xc3, 0xb1, 0xf1, 0x71, 0x4c, 0x1c, 0xaf, 0x06, 0xb4, 0x4c, 0x26, 0x13, 0x13, 0xf4, 0x85, 0x0b,
- 0x17, 0x25, 0xa0, 0x9d, 0xc2, 0x83, 0xf6, 0xda, 0x96, 0x2d, 0x92, 0x4d, 0x66, 0x6d, 0xc9, 0x26,
- 0xb3, 0x73, 0x46, 0x32, 0x5b, 0x24, 0xda, 0x5c, 0x56, 0x66, 0x65, 0xff, 0xd2, 0xa1, 0x56, 0xc4,
- 0x44, 0xa2, 0x3c, 0x4c, 0x88, 0xcb, 0x10, 0xb1, 0x12, 0x11, 0x6b, 0x68, 0x6f, 0xef, 0x20, 0x10,
- 0x08, 0x48, 0x44, 0xe8, 0x65, 0x67, 0xea, 0x18, 0x18, 0xb8, 0xf9, 0xfb, 0xc7, 0xa7, 0xa5, 0x67,
- 0xe6, 0x6e, 0x70, 0x76, 0x73, 0x23, 0x7f, 0xdc, 0xb9, 0xf3, 0x9f, 0xd4, 0xb4, 0xf5, 0x3c, 0x44,
- 0x61, 0x7b, 0x7b, 0x7b, 0xe5, 0xe1, 0xaa, 0xf2, 0x8a, 0x0a, 0x05, 0xd7, 0xe7, 0x4e, 0x2f, 0x49,
- 0x90, 0xae, 0x0a, 0x77, 0x71, 0x75, 0x7d, 0x35, 0x88, 0x65, 0x88, 0xfb, 0xd1, 0x19, 0x65, 0x64,
- 0x64, 0x5c, 0xb9, 0x7a, 0x15, 0x7e, 0xd8, 0xbd, 0xde, 0xde, 0x3f, 0xbe, 0xf5, 0x36, 0xdc, 0x22,
- 0xd2, 0x29, 0x6b, 0xce, 0x94, 0x6d, 0xc4, 0x62, 0x6d, 0xd9, 0xb6, 0x2d, 0x2b, 0x37, 0x77, 0x31,
- 0x92, 0x00, 0x06, 0x8f, 0x23, 0x3b, 0x3b, 0xdb, 0xc7, 0xc7, 0x67, 0x19, 0x22, 0xd6, 0xd0, 0x90,
- 0xe9, 0xe8, 0xe8, 0xb4, 0x66, 0x4d, 0xcc, 0x9c, 0x5d, 0xd5, 0xe6, 0x18, 0xa4, 0xac, 0x8d, 0x9b,
- 0x8b, 0x20, 0x3e, 0x5e, 0x98, 0x97, 0xef, 0x1b, 0x18, 0x48, 0xb6, 0xfe, 0x79, 0xe3, 0x8d, 0x9d,
- 0xf0, 0x8f, 0xd4, 0x84, 0xd8, 0xd6, 0xd6, 0xb6, 0x8a, 0xca, 0xc3, 0xe5, 0x95, 0x87, 0xef, 0xf7,
- 0x2b, 0xf4, 0x2f, 0xe6, 0x20, 0x16, 0x0a, 0xf3, 0x95, 0x21, 0x96, 0x80, 0x36, 0x2d, 0x2d, 0xad,
- 0xb9, 0xa5, 0x05, 0xc2, 0x7e, 0xcf, 0x9e, 0x8f, 0x40, 0x80, 0x7e, 0x7e, 0xfe, 0xec, 0x17, 0x72,
- 0x52, 0x61, 0x91, 0x91, 0xbf, 0xd9, 0xb9, 0x93, 0x1b, 0x16, 0xb6, 0xc8, 0x1b, 0x57, 0x5c, 0x5c,
- 0x8c, 0x67, 0xc4, 0xcb, 0xcb, 0x8b, 0xc5, 0x5a, 0x5e, 0x3a, 0x96, 0xa4, 0xba, 0x08, 0x62, 0x73,
- 0x72, 0x72, 0x16, 0x3e, 0x99, 0xc9, 0x5e, 0x15, 0xc4, 0xe7, 0x67, 0xe4, 0xe6, 0xc6, 0x25, 0x27,
- 0xb3, 0x24, 0x7e, 0xee, 0xf6, 0x1d, 0x3b, 0xa0, 0x18, 0xd5, 0x11, 0x2b, 0x80, 0x22, 0xbc, 0x75,
- 0xab, 0xb9, 0xbc, 0xa2, 0x12, 0x34, 0xab, 0x20, 0x8d, 0x93, 0x45, 0x34, 0x14, 0x62, 0x97, 0xb0,
- 0xe6, 0x50, 0xd6, 0x20, 0x5c, 0x01, 0x4e, 0xf8, 0x3b, 0x10, 0xff, 0xb6, 0xb6, 0x76, 0x98, 0xfd,
- 0x41, 0xa7, 0x19, 0x99, 0x99, 0x38, 0xb2, 0xb2, 0xb2, 0xdf, 0x79, 0xe7, 0x9d, 0xde, 0xbe, 0xbe,
- 0xff, 0xfa, 0xe4, 0x93, 0x0d, 0x22, 0x11, 0x97, 0x1b, 0x64, 0x69, 0x69, 0x89, 0xf3, 0x31, 0xc8,
- 0x04, 0xb4, 0x74, 0x1d, 0x9d, 0xec, 0xdc, 0xdc, 0xd7, 0xb6, 0x6e, 0xd3, 0x7b, 0xb1, 0x43, 0xb2,
- 0x32, 0x86, 0x4f, 0x2b, 0x29, 0xd9, 0x9c, 0x94, 0x94, 0x0c, 0x1a, 0x5f, 0x6e, 0x0b, 0xbe, 0xa8,
- 0xae, 0x2f, 0xf0, 0xb9, 0x0a, 0x0b, 0x0b, 0x19, 0x0b, 0x4e, 0x55, 0x34, 0x5d, 0x5d, 0x47, 0x4f,
- 0xcf, 0xb8, 0xd4, 0x54, 0x61, 0x7e, 0xbe, 0x8b, 0xbb, 0x07, 0x34, 0x70, 0xd9, 0xd6, 0xad, 0x77,
- 0xd5, 0x53, 0x54, 0x00, 0xd0, 0x35, 0x36, 0x36, 0x42, 0xc4, 0x56, 0x1e, 0xae, 0x1e, 0x18, 0x50,
- 0x68, 0x89, 0xee, 0x34, 0x62, 0xa7, 0xd3, 0x5e, 0xe2, 0xca, 0xea, 0x25, 0x04, 0x2a, 0xe9, 0xa0,
- 0xeb, 0xef, 0xef, 0x9f, 0x99, 0x99, 0xf9, 0xee, 0x7b, 0xef, 0x95, 0x97, 0x57, 0xe0, 0x81, 0x1a,
- 0x1e, 0x1e, 0x91, 0x69, 0xa4, 0x4c, 0x3a, 0x81, 0x4f, 0xf5, 0xf6, 0xf5, 0x7f, 0xf0, 0xc1, 0x87,
- 0xe0, 0x58, 0x90, 0x3c, 0x1c, 0x04, 0xc0, 0x1b, 0xbe, 0x2d, 0x68, 0x10, 0xb8, 0x72, 0xe1, 0x70,
- 0x36, 0x95, 0x96, 0x86, 0x91, 0xf6, 0x5c, 0x8b, 0x30, 0xdc, 0xb2, 0xd2, 0xd2, 0x52, 0x78, 0x7c,
- 0xce, 0xce, 0xce, 0x20, 0x9c, 0x65, 0x95, 0x41, 0x90, 0x78, 0x5e, 0xe2, 0x2d, 0xba, 0x22, 0x23,
- 0x23, 0x31, 0xd1, 0xc0, 0x59, 0x58, 0xe8, 0x6c, 0x2d, 0x2d, 0xe6, 0x2a, 0x33, 0xd0, 0x6c, 0x66,
- 0x6e, 0x6e, 0x7c, 0x5a, 0x9a, 0xa1, 0xb1, 0x71, 0x41, 0x61, 0xe1, 0x9d, 0xee, 0x3b, 0x6a, 0x2a,
- 0x83, 0xb9, 0x79, 0x93, 0x20, 0xb6, 0x4a, 0x41, 0xe7, 0x6e, 0x76, 0xa2, 0x76, 0x6a, 0xa9, 0x12,
- 0xb5, 0x80, 0x1c, 0x80, 0x8a, 0x6f, 0xfa, 0xe9, 0xa7, 0x9f, 0x35, 0xfc, 0xfa, 0x2b, 0x89, 0x09,
- 0x90, 0x96, 0x47, 0x4f, 0xa5, 0xc7, 0xc4, 0xc4, 0x4c, 0x23, 0xe5, 0xae, 0xee, 0x9e, 0xdf, 0xfd,
- 0x6e, 0x57, 0x52, 0x52, 0x12, 0x10, 0x0b, 0x44, 0x59, 0x59, 0x59, 0xb3, 0xd9, 0x6c, 0x73, 0x4b,
- 0x4b, 0x3b, 0x47, 0xa7, 0x88, 0x98, 0x98, 0x9c, 0xbc, 0x3c, 0x4b, 0x3b, 0xbb, 0x15, 0x92, 0x3c,
- 0xc2, 0x4a, 0x08, 0x32, 0x53, 0x53, 0x26, 0x3c, 0x44, 0x3d, 0x3d, 0xa5, 0x84, 0x28, 0x3e, 0x56,
- 0xd2, 0x6d, 0x3e, 0x72, 0x19, 0x96, 0xc8, 0x52, 0x8d, 0x5f, 0x78, 0x3c, 0x1e, 0x69, 0x52, 0xba,
- 0xf0, 0xf9, 0xda, 0x3a, 0x3a, 0x56, 0x4e, 0x4e, 0x51, 0xeb, 0xd6, 0x65, 0xe7, 0xe5, 0xf9, 0x70,
- 0xb9, 0x59, 0xd9, 0xd9, 0x6a, 0xca, 0x20, 0x48, 0x11, 0x5b, 0x09, 0xc8, 0x3e, 0x78, 0xf0, 0x40,
- 0x41, 0xc4, 0x3e, 0x93, 0x41, 0x6c, 0x59, 0x59, 0xd9, 0xe2, 0xe1, 0x1a, 0x14, 0x14, 0xf4, 0xfb,
- 0x3f, 0xfc, 0xa1, 0xa6, 0xa6, 0xa6, 0xaf, 0xbf, 0xff, 0xa9, 0xb4, 0x4f, 0xf2, 0xc4, 0xcc, 0x06,
- 0x37, 0x53, 0xff, 0x47, 0xde, 0x75, 0x40, 0x45, 0x91, 0x6d, 0xdb, 0xf5, 0x27, 0x3c, 0xc3, 0x8c,
- 0x3e, 0x05, 0x1c, 0x92, 0x80, 0x0a, 0x92, 0x04, 0x0c, 0x04, 0x9d, 0x51, 0x0c, 0x28, 0x20, 0x06,
- 0x90, 0x31, 0x83, 0x0a, 0x88, 0x01, 0x45, 0x31, 0x47, 0x40, 0x11, 0x45, 0x47, 0x40, 0x51, 0x4c,
- 0x38, 0x32, 0x98, 0xc5, 0x38, 0x0a, 0x88, 0x24, 0x45, 0xcc, 0x80, 0x12, 0xa5, 0x69, 0xb2, 0xb4,
- 0x48, 0x14, 0x90, 0x54, 0xd5, 0x01, 0x9d, 0xf5, 0x77, 0x55, 0x75, 0x37, 0x0d, 0x8d, 0x0c, 0x86,
- 0x79, 0x8f, 0xbf, 0xfe, 0x5d, 0x77, 0xf5, 0xc2, 0xae, 0xea, 0x6b, 0xd5, 0xb9, 0xfb, 0xee, 0xb3,
- 0xcf, 0x8d, 0xef, 0xc5, 0xf9, 0x83, 0xf0, 0x0f, 0x70, 0x2f, 0xc2, 0xa2, 0x09, 0x66, 0x66, 0x30,
- 0x29, 0x40, 0x3b, 0x6a, 0xf4, 0x98, 0x59, 0x73, 0xe7, 0x2e, 0x74, 0x72, 0x5a, 0xee, 0xba, 0x6a,
- 0xc5, 0x6a, 0x37, 0x70, 0xec, 0x10, 0x43, 0x23, 0x10, 0xc5, 0x8f, 0x7d, 0xfa, 0x18, 0x98, 0x98,
- 0x8c, 0x9b, 0x3c, 0x79, 0x9c, 0x85, 0x85, 0x89, 0xa9, 0xa9, 0xde, 0xb0, 0xe1, 0x83, 0x34, 0x35,
- 0xa1, 0x36, 0xa4, 0x77, 0x3d, 0x92, 0x4e, 0x74, 0xc7, 0x8e, 0xbd, 0x91, 0x91, 0xf1, 0xff, 0xc3,
- 0x65, 0x08, 0x4c, 0x7f, 0xac, 0xbc, 0xbc, 0x3c, 0x6c, 0xbb, 0x70, 0xe1, 0x22, 0xc9, 0x35, 0x4a,
- 0xea, 0x4a, 0xdd, 0x4f, 0xef, 0x95, 0x3d, 0xe7, 0xd7, 0xf7, 0xbc, 0x7f, 0x9f, 0x73, 0x7e, 0x7d,
- 0x82, 0x77, 0xc9, 0xfd, 0xd0, 0xe3, 0x1b, 0xfc, 0xe0, 0x5f, 0x3d, 0x7b, 0x0e, 0xd4, 0xd1, 0x31,
- 0x9f, 0x3a, 0xcd, 0x7a, 0xf6, 0xec, 0x5f, 0xc6, 0x8c, 0x29, 0x29, 0x29, 0xf9, 0xea, 0x70, 0x65,
- 0x10, 0x9b, 0xc3, 0xce, 0x05, 0xc7, 0x46, 0x74, 0x3e, 0xf2, 0x62, 0x0e, 0x8f, 0x13, 0x21, 0x76,
- 0xc3, 0x86, 0x0d, 0x5f, 0x82, 0x55, 0x10, 0xe3, 0x8a, 0x15, 0x2b, 0x9e, 0x3e, 0x7d, 0x56, 0x53,
- 0xfb, 0xae, 0x85, 0x45, 0x25, 0xf1, 0xd9, 0xe6, 0xec, 0x30, 0xd1, 0x02, 0xc9, 0x94, 0x94, 0x94,
- 0x89, 0x13, 0x27, 0x01, 0xb1, 0xe6, 0x16, 0x16, 0x0b, 0x1c, 0x1c, 0xbd, 0x7c, 0xf6, 0x06, 0x9d,
- 0x0a, 0x0e, 0x08, 0x3c, 0xb2, 0xd5, 0xd3, 0xd3, 0x69, 0xf9, 0x72, 0xeb, 0x59, 0xb3, 0x06, 0x0f,
- 0xd1, 0x83, 0x48, 0xe8, 0xd9, 0xab, 0xd7, 0x90, 0x11, 0x86, 0x93, 0x6d, 0x6d, 0x67, 0xce, 0x9f,
- 0x3f, 0x7b, 0xc1, 0x82, 0xb9, 0x0b, 0x16, 0xda, 0xce, 0x9b, 0x37, 0x71, 0xca, 0x14, 0xa3, 0x9f,
- 0x7f, 0xe9, 0x3f, 0x68, 0x50, 0x07, 0xf3, 0x66, 0xa9, 0x63, 0x28, 0xe9, 0xc1, 0xf4, 0xff, 0x5b,
- 0x1d, 0x05, 0xff, 0xf3, 0x29, 0xa9, 0xe3, 0x72, 0x50, 0x3b, 0xcc, 0x08, 0xc2, 0x82, 0x05, 0x0b,
- 0x1d, 0x1c, 0x1c, 0x7b, 0xd1, 0xb3, 0xb5, 0x0f, 0xbb, 0xcb, 0xa4, 0x87, 0xff, 0xd4, 0x94, 0xa1,
- 0x40, 0xbc, 0x94, 0xa7, 0x72, 0xa6, 0x7c, 0x63, 0xba, 0xc2, 0xd3, 0x2b, 0xfd, 0xd6, 0xce, 0x95,
- 0xa3, 0x76, 0x4d, 0xff, 0xf1, 0x47, 0x75, 0x5d, 0xdd, 0xb1, 0xe6, 0xe6, 0xc6, 0x63, 0xc6, 0x14,
- 0x17, 0x17, 0xff, 0x53, 0x88, 0xcd, 0xc9, 0x81, 0x28, 0x08, 0xbf, 0x1d, 0x59, 0x55, 0x59, 0xd5,
- 0x29, 0xc4, 0xb6, 0x9a, 0x0c, 0xf3, 0x61, 0xe7, 0xce, 0x9d, 0x9f, 0x0d, 0x57, 0xc4, 0x53, 0x57,
- 0xaf, 0x5e, 0xab, 0xa8, 0xa8, 0x14, 0x88, 0x8e, 0x58, 0x6a, 0x96, 0x40, 0xe9, 0x7b, 0x31, 0x4a,
- 0xa5, 0x4e, 0x69, 0x04, 0xaa, 0x63, 0x63, 0xe3, 0x10, 0xf4, 0x4d, 0x9f, 0x6e, 0xed, 0xba, 0xda,
- 0xed, 0xc4, 0xef, 0xa7, 0xae, 0xdf, 0xba, 0x75, 0x2a, 0x24, 0x64, 0xc7, 0x4e, 0xaf, 0x65, 0xcb,
- 0x97, 0x4f, 0x9d, 0x36, 0x7d, 0x84, 0x91, 0x91, 0x32, 0x3d, 0xe1, 0x0a, 0xa0, 0xed, 0xd6, 0xbd,
- 0xfb, 0x8f, 0xbd, 0x7b, 0xff, 0x5b, 0x4e, 0x4e, 0x49, 0x43, 0x63, 0xd8, 0xc8, 0x91, 0x16, 0x54,
- 0x80, 0xb0, 0x60, 0xbe, 0x83, 0xc3, 0x92, 0x95, 0x2b, 0xcd, 0xac, 0xa6, 0x28, 0x7c, 0x44, 0xa1,
- 0xc9, 0xc9, 0xc9, 0x41, 0xf0, 0x30, 0xcb, 0x69, 0xbb, 0xf2, 0x06, 0xc8, 0x0c, 0xf6, 0xa0, 0x58,
- 0x20, 0xe0, 0xd1, 0xac, 0x3a, 0x6f, 0x7c, 0xdc, 0xcc, 0xc8, 0x7e, 0xb4, 0x4d, 0xe9, 0x57, 0x63,
- 0x56, 0xce, 0xc2, 0xb9, 0xd0, 0xab, 0x87, 0x1c, 0x37, 0x6e, 0x58, 0xbb, 0x78, 0x96, 0x41, 0x5c,
- 0x70, 0xbf, 0x86, 0x74, 0x79, 0x21, 0x56, 0x5b, 0xe7, 0xda, 0xe7, 0x8a, 0x27, 0x3c, 0xe5, 0x7a,
- 0xfd, 0xf0, 0x0d, 0x75, 0x38, 0x85, 0xb2, 0xf2, 0x20, 0x6d, 0xed, 0x94, 0x94, 0xd4, 0x7f, 0xe2,
- 0xbc, 0x03, 0x28, 0xc2, 0x82, 0x82, 0x82, 0xdb, 0xb7, 0x23, 0xc3, 0x22, 0x6e, 0x77, 0x7e, 0xbf,
- 0x44, 0x06, 0xb1, 0xcc, 0x01, 0x5e, 0xde, 0xde, 0xde, 0x9f, 0x81, 0x55, 0xb0, 0x96, 0xd3, 0xe2,
- 0xc5, 0xd9, 0x6c, 0x36, 0x9f, 0x1e, 0x79, 0x15, 0x1f, 0x97, 0x20, 0xdc, 0xc7, 0x5b, 0x92, 0x51,
- 0xdb, 0x3b, 0x57, 0xb4, 0xbe, 0xa1, 0xe1, 0x60, 0xc0, 0x21, 0x6b, 0x6b, 0xeb, 0x55, 0x6e, 0x6e,
- 0xa0, 0xd6, 0xa8, 0x98, 0xb8, 0xa8, 0x98, 0x58, 0xf8, 0x89, 0x0b, 0x17, 0x2f, 0xf9, 0xfa, 0xfa,
- 0xad, 0x74, 0x75, 0x9d, 0x3a, 0x75, 0x1a, 0x54, 0xb1, 0x82, 0xa2, 0x22, 0xa2, 0x27, 0xd4, 0x0b,
- 0xe5, 0xd0, 0xe9, 0x73, 0x94, 0xa8, 0x39, 0xde, 0xdf, 0x7e, 0xdb, 0xa3, 0x77, 0xaf, 0x61, 0x26,
- 0x26, 0x6b, 0x36, 0x6c, 0x38, 0xf9, 0x7b, 0xf0, 0xee, 0xbd, 0x7b, 0x87, 0x19, 0x1b, 0x7f, 0xd7,
- 0xad, 0xed, 0x24, 0x3a, 0x08, 0x15, 0x70, 0x0b, 0xe2, 0x0e, 0x84, 0x75, 0x88, 0x07, 0xbb, 0xa6,
- 0x88, 0x65, 0xb0, 0xda, 0x8d, 0x9e, 0x32, 0x84, 0x66, 0x85, 0x56, 0x06, 0x56, 0x94, 0xa7, 0x92,
- 0xc2, 0xc7, 0x12, 0x2e, 0xe1, 0x32, 0xee, 0x82, 0x77, 0x93, 0x81, 0xbc, 0xef, 0xd5, 0x0b, 0xc8,
- 0x6c, 0x33, 0x37, 0x83, 0xd9, 0xfb, 0x85, 0x9e, 0xc8, 0x3d, 0x00, 0x16, 0x58, 0xe5, 0xba, 0xfc,
- 0x6a, 0xd0, 0xe2, 0x57, 0x77, 0xb5, 0xdb, 0xc5, 0xaa, 0x38, 0x37, 0xa4, 0x29, 0x1d, 0x71, 0x97,
- 0xe9, 0xd7, 0xf7, 0x5b, 0xfc, 0xbe, 0x4f, 0x9f, 0x3e, 0x67, 0xce, 0x9c, 0x29, 0x2f, 0x2f, 0xff,
- 0xea, 0xbb, 0xc1, 0xa0, 0x40, 0x0e, 0x87, 0x13, 0x15, 0x1d, 0x0d, 0x61, 0x50, 0xda, 0xe1, 0xea,
- 0x6f, 0x09, 0xb8, 0x7e, 0x29, 0x62, 0x95, 0x94, 0x95, 0x3d, 0x3c, 0x3c, 0xab, 0xab, 0x6b, 0x5a,
- 0xe2, 0x29, 0xba, 0xa8, 0xf7, 0x92, 0xbc, 0x4a, 0xbb, 0x7e, 0x49, 0x25, 0x20, 0x3e, 0x66, 0x94,
- 0xc7, 0x17, 0x64, 0x64, 0x66, 0x2e, 0x72, 0x70, 0x5c, 0xed, 0xe6, 0x16, 0x10, 0x18, 0x18, 0x71,
- 0x27, 0x2a, 0x29, 0xf9, 0x79, 0x68, 0xe8, 0x65, 0x7f, 0x7f, 0xff, 0x67, 0x89, 0x49, 0x90, 0x37,
- 0x87, 0x0f, 0x07, 0xba, 0xb9, 0xad, 0x01, 0x68, 0xf5, 0xf5, 0xf5, 0x5b, 0x81, 0xb6, 0x75, 0x52,
- 0x53, 0x57, 0x77, 0x5a, 0xb6, 0x3c, 0x38, 0x24, 0x64, 0xe3, 0xd6, 0x6d, 0xaa, 0x83, 0x07, 0x4b,
- 0x2a, 0x5b, 0x3c, 0xe4, 0xd4, 0xa9, 0x53, 0xed, 0xec, 0xec, 0xc0, 0x30, 0xa8, 0xd9, 0x6e, 0x5d,
- 0x72, 0x01, 0x02, 0x03, 0x57, 0xa8, 0xcd, 0x3e, 0x7d, 0xfb, 0x2a, 0x29, 0x29, 0x6b, 0x68, 0x0c,
- 0xc6, 0xfb, 0x0e, 0x1f, 0x31, 0xc2, 0x10, 0x61, 0x92, 0x91, 0xf1, 0xc7, 0x12, 0x2e, 0xe1, 0x32,
- 0xda, 0x23, 0x5a, 0xb4, 0x8e, 0x8e, 0x8e, 0xda, 0x80, 0x01, 0x78, 0x41, 0xc6, 0x44, 0x2d, 0x87,
- 0xc7, 0xa1, 0x51, 0xf7, 0xe8, 0x01, 0x54, 0x1b, 0x18, 0x18, 0xd8, 0xd8, 0xcc, 0x08, 0xdc, 0xbd,
- 0xb8, 0x34, 0x41, 0xab, 0x15, 0x3e, 0xb3, 0x90, 0x15, 0x5a, 0xb2, 0x18, 0xb4, 0xe9, 0x8a, 0x87,
- 0xb6, 0xf5, 0x95, 0xf9, 0xf7, 0x37, 0x28, 0x6d, 0xfc, 0xf8, 0xf1, 0xa7, 0x4e, 0x9d, 0x42, 0x60,
- 0xf2, 0x75, 0xe3, 0x2f, 0x94, 0x56, 0x5e, 0x5e, 0x11, 0x77, 0xf7, 0x6e, 0x58, 0x58, 0x78, 0x71,
- 0xf1, 0xab, 0xce, 0xff, 0xea, 0xb3, 0x11, 0xab, 0xa8, 0xa8, 0xb8, 0xdf, 0xd7, 0x17, 0x24, 0xd9,
- 0xdc, 0x46, 0xb5, 0x7e, 0x68, 0xc9, 0x1f, 0x3e, 0xb4, 0x84, 0x5a, 0x02, 0x6e, 0x1d, 0x9f, 0xe4,
- 0x08, 0xc8, 0x57, 0x02, 0xb2, 0x48, 0x40, 0x16, 0x08, 0x88, 0xdc, 0xa6, 0xda, 0x8c, 0xb4, 0xe4,
- 0xeb, 0xe7, 0xfe, 0xd8, 0x77, 0xf8, 0xc8, 0xd1, 0xeb, 0x37, 0x6f, 0x01, 0xae, 0xe9, 0xe9, 0x19,
- 0x56, 0x56, 0x53, 0x54, 0x55, 0x55, 0x03, 0x8f, 0x1c, 0x81, 0xbe, 0xbd, 0x73, 0x27, 0x0a, 0xa0,
- 0x5d, 0xb5, 0x6a, 0xb5, 0xa5, 0xe5, 0xe4, 0x21, 0x43, 0x86, 0x80, 0x58, 0x98, 0x61, 0x5c, 0x69,
- 0xd4, 0x19, 0x9b, 0x9a, 0xae, 0x5e, 0xb7, 0xde, 0x65, 0xb5, 0xdb, 0x50, 0x13, 0x93, 0xee, 0xad,
- 0x37, 0x33, 0x71, 0x74, 0x14, 0xce, 0x81, 0x61, 0x06, 0xd4, 0xba, 0x20, 0x62, 0x99, 0x13, 0x36,
- 0xf1, 0x78, 0x40, 0x1d, 0x5a, 0x16, 0x54, 0x3d, 0x1e, 0x18, 0xad, 0x6c, 0x21, 0x62, 0x7b, 0x07,
- 0x24, 0xc7, 0x76, 0x33, 0x2e, 0xe1, 0x32, 0xdc, 0xc7, 0x9c, 0x39, 0x73, 0xa6, 0x4d, 0x9b, 0x36,
- 0x7a, 0xf4, 0x68, 0x6d, 0x6d, 0x6d, 0x98, 0x08, 0x2c, 0xcd, 0x98, 0x88, 0x51, 0xb0, 0x28, 0x16,
- 0x72, 0x68, 0xc2, 0x04, 0xb3, 0xe5, 0xcb, 0x5d, 0x58, 0xb7, 0x4d, 0xa0, 0x57, 0x25, 0xe0, 0xaa,
- 0x48, 0x64, 0x2b, 0x11, 0xd9, 0xfd, 0x89, 0x6c, 0x15, 0xfa, 0x53, 0x99, 0x60, 0x29, 0xb6, 0x80,
- 0x36, 0x55, 0xe9, 0x98, 0xbb, 0xdc, 0xf7, 0xdf, 0x51, 0xad, 0x49, 0x4b, 0x4b, 0xeb, 0xc0, 0x81,
- 0x83, 0x5f, 0x7d, 0x28, 0xa1, 0xba, 0xba, 0x3a, 0x21, 0xe1, 0x01, 0x10, 0x9b, 0x9f, 0x97, 0xff,
- 0x4f, 0x23, 0x16, 0x6e, 0x6b, 0xf7, 0x9e, 0x3d, 0x0d, 0x8d, 0x8d, 0x02, 0x89, 0xd3, 0xbe, 0xde,
- 0x4b, 0xe0, 0x93, 0x29, 0x53, 0xd4, 0xaf, 0xc5, 0x17, 0xf0, 0x6a, 0x79, 0x8d, 0x85, 0xbc, 0xfa,
- 0x14, 0x7e, 0x43, 0x32, 0xbf, 0x21, 0x91, 0x57, 0xff, 0x88, 0xf7, 0xee, 0x2e, 0xaf, 0xe6, 0x0e,
- 0xb7, 0x26, 0xbc, 0xbe, 0x2c, 0x32, 0xe5, 0x79, 0x5c, 0xd2, 0xf3, 0x17, 0xf9, 0x05, 0x85, 0xfb,
- 0xf6, 0xfd, 0x26, 0x27, 0xd7, 0x0f, 0x6c, 0xa3, 0xab, 0xab, 0x1b, 0x14, 0x14, 0x94, 0x96, 0x96,
- 0x1e, 0x19, 0x79, 0x27, 0x20, 0xe0, 0xd0, 0xb2, 0x65, 0xcb, 0xcd, 0xcd, 0xcd, 0xf1, 0x25, 0x7c,
- 0x65, 0xbb, 0x9e, 0x5d, 0x55, 0x53, 0xd3, 0xca, 0x66, 0x86, 0xa5, 0xb5, 0xb5, 0xae, 0xa1, 0x61,
- 0xf7, 0x1f, 0x84, 0x88, 0x05, 0x3e, 0x27, 0x4e, 0x9c, 0xb8, 0x71, 0xe3, 0x46, 0xa8, 0x0e, 0xd4,
- 0x26, 0x1c, 0x5c, 0x17, 0x44, 0xac, 0xd8, 0x71, 0xab, 0xa8, 0xa8, 0x82, 0x36, 0xc1, 0x84, 0x2b,
- 0x57, 0xba, 0x7a, 0x79, 0x79, 0xc1, 0xd1, 0x1c, 0x42, 0x73, 0x45, 0xd3, 0xfd, 0x48, 0xc2, 0x15,
- 0x5c, 0x3e, 0x18, 0x10, 0xb0, 0x77, 0xef, 0xbe, 0x2d, 0x5b, 0xb6, 0x02, 0xde, 0x80, 0x25, 0xc8,
- 0x16, 0x4c, 0xcb, 0x8c, 0xc2, 0x88, 0x8a, 0x55, 0x31, 0x31, 0x31, 0x99, 0x3f, 0xdf, 0x2e, 0xfc,
- 0xa8, 0x79, 0x4b, 0x9c, 0x45, 0x51, 0xab, 0x12, 0x05, 0x54, 0xb6, 0x1a, 0xc1, 0x1e, 0x48, 0xb0,
- 0x07, 0x11, 0x6c, 0x75, 0x2a, 0x67, 0xab, 0x4a, 0x32, 0x6d, 0x7d, 0x8a, 0xe2, 0xde, 0x95, 0xc2,
- 0x83, 0x3c, 0x40, 0x50, 0xdb, 0xdd, 0xdd, 0x21, 0x0f, 0xbe, 0x22, 0x68, 0xeb, 0xeb, 0xeb, 0x13,
- 0x13, 0x13, 0xa1, 0x0a, 0xb2, 0x59, 0xd9, 0xff, 0x28, 0x62, 0xd1, 0x6c, 0xb7, 0x6d, 0xdf, 0x5e,
- 0x5e, 0x51, 0x21, 0x90, 0xa6, 0x56, 0x49, 0xa0, 0xd2, 0x8b, 0xc8, 0xaa, 0xaa, 0xaa, 0x1e, 0x24,
- 0xdc, 0x3b, 0xfd, 0xc7, 0x31, 0xbf, 0xfd, 0x5e, 0x3b, 0x3d, 0x37, 0x79, 0x7a, 0x6c, 0xf0, 0xdd,
- 0xbf, 0xf3, 0x74, 0x48, 0x60, 0x7c, 0xdc, 0xb5, 0x37, 0x9c, 0xe7, 0xbc, 0xa6, 0x7c, 0x3e, 0x91,
- 0x47, 0x36, 0x14, 0x55, 0xbf, 0x2d, 0xbb, 0x79, 0x2b, 0x6c, 0xf8, 0xf0, 0xe1, 0x80, 0x6b, 0x37,
- 0x7a, 0xa4, 0x0c, 0xb1, 0xed, 0xf9, 0xf3, 0xe7, 0x21, 0x1b, 0xc2, 0x23, 0x22, 0x7e, 0xdb, 0xbf,
- 0xdf, 0xd9, 0x79, 0x89, 0x99, 0x99, 0x19, 0x1a, 0x7b, 0xbb, 0xf3, 0x12, 0x11, 0x23, 0x50, 0x47,
- 0x30, 0xff, 0xf2, 0x8b, 0x92, 0xba, 0xba, 0xf8, 0x98, 0x09, 0x18, 0x79, 0xdd, 0xba, 0xf5, 0x3b,
- 0x76, 0xec, 0xa0, 0x39, 0xb6, 0x8b, 0x76, 0x14, 0x88, 0xf7, 0x71, 0xd5, 0xd3, 0xd3, 0x83, 0xfe,
- 0x59, 0xb3, 0x66, 0xed, 0x91, 0xa3, 0x47, 0xc3, 0xc2, 0xc3, 0x1f, 0x3c, 0x7c, 0xf8, 0xf4, 0xd9,
- 0xb3, 0xc4, 0xc4, 0xa4, 0x0e, 0x32, 0x2e, 0x3f, 0x7e, 0xf2, 0x24, 0x36, 0x2e, 0xee, 0xe2, 0xc5,
- 0x4b, 0x7b, 0x7c, 0x7c, 0xc0, 0xba, 0xa6, 0xa6, 0x63, 0x07, 0x0d, 0x1a, 0xf4, 0x6f, 0x7a, 0x52,
- 0x13, 0xad, 0x07, 0x7e, 0x82, 0xc0, 0x40, 0x54, 0xbb, 0x6b, 0x9d, 0x33, 0x27, 0x5e, 0xab, 0x05,
- 0xae, 0x2c, 0x06, 0xae, 0x00, 0xaa, 0x26, 0xc1, 0xd6, 0x21, 0xd8, 0xba, 0xa2, 0xac, 0x49, 0x83,
- 0x56, 0x49, 0x0c, 0xda, 0xc2, 0x38, 0x85, 0x51, 0xba, 0xc2, 0x95, 0xe0, 0x70, 0x70, 0xb6, 0xb6,
- 0xbf, 0xd6, 0xd6, 0xd6, 0x7e, 0x2d, 0xd0, 0x92, 0x04, 0x99, 0x95, 0x95, 0x15, 0x15, 0x15, 0x9d,
- 0x99, 0x99, 0xf9, 0xcf, 0x21, 0x16, 0x68, 0x81, 0xb3, 0x2a, 0x2a, 0x7a, 0x45, 0x8d, 0x5e, 0xb5,
- 0x16, 0xae, 0xc2, 0x01, 0xdf, 0x66, 0xe1, 0x60, 0x41, 0x52, 0x52, 0xf2, 0xfa, 0xf5, 0xeb, 0xf5,
- 0xf5, 0xf4, 0xd4, 0xd4, 0xd4, 0x10, 0x28, 0xc8, 0xc9, 0xca, 0xf6, 0xa5, 0x52, 0x1f, 0x20, 0x07,
- 0xff, 0x54, 0x55, 0x55, 0xd1, 0xd2, 0xd4, 0x98, 0x34, 0x71, 0x82, 0xef, 0xfe, 0x3d, 0xe9, 0x69,
- 0xc9, 0xc9, 0x49, 0xcf, 0x2c, 0x2d, 0x2d, 0x25, 0x37, 0xfa, 0xa0, 0x40, 0x3b, 0x7c, 0xf8, 0xed,
- 0xc8, 0xc8, 0xcc, 0x97, 0x59, 0xd7, 0xae, 0xdf, 0xd8, 0xe3, 0xb3, 0x97, 0xae, 0x11, 0x53, 0x75,
- 0x75, 0x0d, 0x04, 0x1a, 0x6d, 0x40, 0xfb, 0xe3, 0x4f, 0xfd, 0x20, 0xfe, 0x54, 0x34, 0x35, 0x7b,
- 0xf4, 0xed, 0x7b, 0x70, 0x8b, 0x5c, 0x7a, 0x78, 0xbf, 0xf4, 0xdb, 0x72, 0xac, 0x68, 0xc5, 0xd7,
- 0x8f, 0xb5, 0x43, 0x4f, 0xd9, 0x2f, 0x5a, 0xb4, 0x10, 0x3c, 0x03, 0x00, 0x77, 0xc1, 0xc8, 0x4b,
- 0x3c, 0x8a, 0x6a, 0x3a, 0x76, 0xec, 0x92, 0xa5, 0x4b, 0x0f, 0x1d, 0x3a, 0x1c, 0x1b, 0x1b, 0x77,
- 0xe0, 0xc0, 0x81, 0x81, 0x9d, 0x4e, 0x50, 0x4d, 0x0f, 0x1f, 0x3e, 0xba, 0x7e, 0xe3, 0x86, 0x97,
- 0xd7, 0xae, 0x79, 0xf3, 0xe6, 0x31, 0xb3, 0xe0, 0x60, 0x22, 0xb4, 0x02, 0x78, 0x16, 0x0b, 0x0b,
- 0x8b, 0x35, 0x2b, 0x97, 0x3e, 0x3b, 0x3b, 0xa6, 0x21, 0x45, 0xe4, 0xf1, 0x29, 0xb8, 0xaa, 0xd2,
- 0x70, 0xd5, 0x26, 0xd8, 0x43, 0xa4, 0xb2, 0x26, 0xc1, 0x52, 0x91, 0x64, 0xda, 0xf8, 0xf3, 0xb2,
- 0xfd, 0x64, 0x5a, 0x8c, 0xc6, 0x6c, 0x5f, 0xf0, 0x55, 0xd6, 0x2a, 0x02, 0x40, 0xaf, 0x39, 0xaf,
- 0x13, 0x9f, 0x3d, 0xeb, 0xcc, 0x3a, 0x2f, 0x69, 0xc4, 0xee, 0xdb, 0xb7, 0xef, 0x6f, 0xe1, 0x0a,
- 0x14, 0xc1, 0xcf, 0x3e, 0x7f, 0xfe, 0xa2, 0x4d, 0x17, 0x96, 0x50, 0x06, 0xd0, 0x58, 0x6d, 0x6a,
- 0x22, 0x9e, 0x3c, 0x7d, 0x66, 0x6f, 0x6f, 0xcf, 0xcc, 0x77, 0xed, 0x4c, 0x42, 0xb1, 0x1f, 0x3b,
- 0x97, 0x01, 0x36, 0x47, 0x1b, 0x04, 0xd3, 0xde, 0xb8, 0x71, 0x63, 0xcf, 0x1e, 0x1f, 0xa8, 0xba,
- 0x71, 0xe3, 0xc6, 0x0d, 0x1e, 0xac, 0x09, 0xa6, 0x65, 0x96, 0x2d, 0x30, 0x81, 0xd8, 0x77, 0x3f,
- 0xfc, 0x00, 0xd0, 0x7e, 0xdf, 0xab, 0xd7, 0xe4, 0x51, 0x7d, 0x5e, 0xde, 0x52, 0x20, 0x58, 0xca,
- 0x44, 0xf6, 0x00, 0xc6, 0xcd, 0x35, 0x65, 0x2a, 0x05, 0xf9, 0x4e, 0x9d, 0x62, 0x65, 0x49, 0xf7,
- 0x6e, 0x75, 0x2d, 0x61, 0xc0, 0x2c, 0x10, 0x80, 0xa1, 0x98, 0xb3, 0x33, 0xb6, 0x6e, 0xdb, 0x76,
- 0x29, 0x34, 0x34, 0x3d, 0x23, 0xf3, 0x93, 0xc6, 0x1f, 0x81, 0xcf, 0xcb, 0x57, 0xae, 0x80, 0x8f,
- 0x83, 0x83, 0xff, 0x80, 0x4f, 0x41, 0xa4, 0x69, 0x60, 0x30, 0x14, 0x4c, 0x0b, 0x7f, 0x84, 0xa0,
- 0xc9, 0xd9, 0x71, 0xd1, 0x79, 0x2f, 0xdb, 0xd2, 0x38, 0x4d, 0xe2, 0x25, 0x98, 0x53, 0x81, 0xd6,
- 0xae, 0x6a, 0xb4, 0x06, 0x68, 0x03, 0x57, 0x3d, 0x51, 0xc6, 0xdf, 0x1a, 0x34, 0x68, 0x81, 0x70,
- 0x2a, 0xc3, 0x80, 0xd7, 0x03, 0xfb, 0x0d, 0x54, 0xee, 0xc6, 0xf4, 0x9e, 0x21, 0x81, 0xb7, 0xef,
- 0x44, 0x45, 0x35, 0x36, 0x35, 0x7d, 0x21, 0xd5, 0x22, 0x02, 0xaf, 0xa9, 0xa9, 0x61, 0xb3, 0xd9,
- 0x85, 0x85, 0x85, 0x9f, 0x84, 0x58, 0x66, 0x09, 0x0b, 0xb4, 0xd3, 0xdf, 0x1a, 0x07, 0x76, 0x80,
- 0x49, 0x45, 0x9d, 0xae, 0x6d, 0xc5, 0x00, 0xbe, 0x7c, 0x57, 0x57, 0x17, 0x12, 0x12, 0xf2, 0xd9,
- 0x67, 0xd9, 0xb4, 0x9b, 0x46, 0x18, 0x1a, 0xde, 0xbb, 0x77, 0x2f, 0x25, 0x35, 0x2d, 0xf4, 0xf2,
- 0xe5, 0x5d, 0xde, 0xde, 0x0e, 0x8e, 0x8e, 0xe3, 0xc7, 0x4f, 0x40, 0x75, 0xc8, 0xcb, 0xcb, 0xb7,
- 0xf4, 0x1e, 0x20, 0x7f, 0xfb, 0xad, 0xa2, 0xec, 0xf7, 0xe7, 0xf6, 0xc9, 0x35, 0xa1, 0x6a, 0x28,
- 0x02, 0xd1, 0xa5, 0x8d, 0xaf, 0x4b, 0xb0, 0x06, 0x54, 0x3f, 0x51, 0x5b, 0xea, 0x68, 0xd3, 0x05,
- 0x8f, 0xf7, 0x12, 0x75, 0xef, 0xcb, 0x23, 0xe4, 0xb7, 0xb7, 0x5f, 0xb0, 0xdf, 0xd7, 0x2f, 0x3a,
- 0x26, 0x26, 0xbf, 0xa0, 0x00, 0x6f, 0xf7, 0x49, 0x26, 0x82, 0xec, 0xc9, 0xc8, 0xc8, 0x04, 0x8a,
- 0xfc, 0x0f, 0x1c, 0x58, 0xba, 0x6c, 0x99, 0x95, 0x95, 0xd5, 0x98, 0x31, 0x63, 0x26, 0x4d, 0x9a,
- 0x84, 0x08, 0x2d, 0xc0, 0xc3, 0x25, 0xfd, 0xc2, 0x84, 0xfa, 0x94, 0xc1, 0x44, 0xd6, 0x40, 0x98,
- 0x82, 0x56, 0xad, 0x1a, 0xb4, 0x12, 0x90, 0xc4, 0xaa, 0x3e, 0xc1, 0x1e, 0x4a, 0xe4, 0x0c, 0x23,
- 0x72, 0x46, 0x10, 0xb9, 0x46, 0x44, 0xee, 0x70, 0x22, 0x47, 0x87, 0xc8, 0x1e, 0x44, 0xb0, 0x06,
- 0x32, 0xb9, 0x31, 0x5d, 0x3d, 0x70, 0xbb, 0x4a, 0x7f, 0x85, 0x5e, 0xdd, 0x7b, 0xf4, 0x80, 0xb2,
- 0x02, 0x51, 0x18, 0x0c, 0x1d, 0x7a, 0xe6, 0xcc, 0x19, 0xe0, 0xed, 0x0b, 0x15, 0x02, 0x49, 0x92,
- 0xe5, 0x65, 0xe5, 0x15, 0x9d, 0x9d, 0xd1, 0x2d, 0x46, 0x2c, 0x95, 0xb7, 0x6f, 0xdf, 0xde, 0xb1,
- 0x59, 0x00, 0x0f, 0x57, 0x57, 0x57, 0x61, 0xe7, 0x40, 0xeb, 0x6e, 0x01, 0x46, 0x0c, 0xf0, 0xf8,
- 0x7c, 0x04, 0x0b, 0x5f, 0xbe, 0x85, 0x72, 0x9b, 0x04, 0x06, 0x86, 0x6b, 0x8b, 0x8a, 0x8e, 0x4e,
- 0x4c, 0x4a, 0xba, 0x74, 0x29, 0x14, 0x82, 0x6d, 0xf1, 0xe2, 0xc5, 0xa0, 0x7a, 0x84, 0xff, 0x70,
- 0xf4, 0x08, 0x2e, 0x18, 0xda, 0xfc, 0xd7, 0x77, 0xdf, 0xb8, 0xd8, 0xc8, 0xbc, 0x7d, 0xac, 0x42,
- 0xbb, 0x3c, 0x9d, 0x56, 0x6e, 0xee, 0xa5, 0xf2, 0xa6, 0x75, 0x0b, 0x51, 0x89, 0x5d, 0x6d, 0x5e,
- 0x01, 0xd3, 0xbd, 0x8f, 0xa7, 0x1a, 0x3b, 0x76, 0xec, 0x8a, 0x15, 0x2b, 0x83, 0x4e, 0x9e, 0x84,
- 0x7b, 0x7a, 0xfc, 0xf8, 0xf1, 0xa7, 0x1e, 0xb8, 0x86, 0xa0, 0xf2, 0xfc, 0x85, 0x0b, 0x08, 0x54,
- 0xaf, 0x5c, 0xbd, 0xe6, 0xe3, 0xb3, 0xd7, 0xd5, 0x75, 0x95, 0xa3, 0x93, 0x13, 0x3e, 0xfd, 0xbc,
- 0xb7, 0x25, 0x1c, 0xb7, 0xab, 0x4c, 0x30, 0x25, 0xb2, 0x0d, 0x09, 0x36, 0x70, 0x68, 0x40, 0xe5,
- 0x5c, 0x80, 0x93, 0xfe, 0x9b, 0x21, 0x55, 0xea, 0xcb, 0x11, 0x64, 0xae, 0x09, 0x91, 0x37, 0x9a,
- 0xc8, 0x1b, 0x47, 0xe6, 0x4f, 0xa4, 0xf3, 0x58, 0x32, 0x6f, 0x24, 0x99, 0x63, 0x28, 0xca, 0x23,
- 0x38, 0x0f, 0x0d, 0x6d, 0x2d, 0x07, 0x29, 0x28, 0x28, 0x32, 0x7d, 0xbf, 0x68, 0xf8, 0x70, 0x7f,
- 0x3e, 0x3e, 0x3e, 0xd5, 0x00, 0xad, 0x70, 0xfc, 0x54, 0x88, 0x28, 0xd1, 0xa7, 0x38, 0xb5, 0x73,
- 0xaa, 0xe6, 0x5f, 0x62, 0xf8, 0xbd, 0x7f, 0xdf, 0x48, 0xa7, 0x96, 0x9b, 0xff, 0x12, 0x8e, 0xc6,
- 0x4a, 0x14, 0xd8, 0x92, 0x3e, 0x48, 0x20, 0x16, 0x9a, 0xb3, 0x63, 0xb3, 0xc0, 0x73, 0x65, 0xb1,
- 0x58, 0x2d, 0xd3, 0x03, 0xe8, 0x5e, 0x56, 0xd1, 0xcf, 0x29, 0x91, 0x70, 0xe5, 0xca, 0x95, 0xaf,
- 0x0e, 0x57, 0x26, 0xc1, 0x44, 0x36, 0x36, 0x36, 0xe0, 0x1f, 0x68, 0xe3, 0xab, 0xd7, 0xae, 0xfd,
- 0xf6, 0xdb, 0xfe, 0xa5, 0x4b, 0x97, 0x59, 0x5a, 0x4e, 0xd6, 0x37, 0x30, 0x50, 0x52, 0x52, 0x62,
- 0xce, 0x98, 0xd3, 0x56, 0xe9, 0x71, 0xef, 0x98, 0x4a, 0xd3, 0x4b, 0xe8, 0x01, 0x0d, 0x11, 0xc1,
- 0x0e, 0x11, 0xd1, 0x6c, 0xff, 0xf0, 0x20, 0x33, 0xc0, 0x5e, 0x5d, 0x5d, 0x1d, 0x60, 0xe8, 0x3a,
- 0xb3, 0x0d, 0x99, 0x70, 0x1e, 0x4f, 0x35, 0x79, 0xf2, 0xe4, 0xcd, 0x9b, 0x37, 0x5f, 0xbc, 0x14,
- 0x0a, 0xaa, 0x3c, 0x76, 0xec, 0xd8, 0x67, 0x9c, 0x5d, 0x05, 0x19, 0x9c, 0x97, 0x9f, 0xff, 0xf4,
- 0xe9, 0xb3, 0xcb, 0x97, 0xaf, 0x20, 0x76, 0x83, 0x12, 0xfe, 0xfd, 0xf8, 0xb1, 0xfb, 0x21, 0x9e,
- 0x9c, 0x68, 0xc7, 0x86, 0xec, 0x59, 0x64, 0xe1, 0x0c, 0xb2, 0x60, 0x3a, 0x51, 0x68, 0x49, 0x16,
- 0x4c, 0x22, 0xf3, 0xc7, 0x91, 0x79, 0xbf, 0x50, 0x74, 0x4a, 0x61, 0x15, 0xe8, 0x35, 0x24, 0xf3,
- 0x46, 0x93, 0xf9, 0x93, 0xc8, 0x42, 0x6b, 0xe2, 0xd5, 0x5c, 0xb2, 0x78, 0x21, 0xb7, 0xd8, 0x81,
- 0x2c, 0x5e, 0x44, 0x16, 0xcf, 0x23, 0x0b, 0x7f, 0x25, 0x0b, 0x6d, 0xe9, 0x8c, 0x9f, 0xcf, 0x48,
- 0x8d, 0x9e, 0x62, 0x31, 0xd1, 0x58, 0x53, 0x53, 0x53, 0x59, 0x59, 0x59, 0x56, 0x56, 0xae, 0xaf,
- 0x8c, 0x0c, 0xfe, 0x5e, 0xbb, 0x6e, 0x1d, 0x42, 0x7e, 0xe6, 0x4c, 0x37, 0x66, 0x6b, 0xac, 0x56,
- 0xb9, 0xf5, 0x80, 0x91, 0x34, 0xfc, 0x98, 0x71, 0x4f, 0x08, 0x5a, 0xf1, 0x37, 0x1f, 0x5a, 0x5f,
- 0x95, 0x2a, 0x53, 0xa4, 0x3f, 0xdf, 0x7f, 0x00, 0x7f, 0x76, 0x6c, 0x93, 0x83, 0x07, 0x03, 0x04,
- 0xe2, 0x21, 0x2d, 0xe1, 0xa0, 0x80, 0x88, 0x60, 0xdf, 0xbf, 0x87, 0xa9, 0x8d, 0x3b, 0x77, 0xb0,
- 0xf8, 0xe7, 0x25, 0x20, 0x6d, 0xee, 0xdc, 0xb9, 0x8f, 0x1e, 0x3d, 0x4e, 0x49, 0x4d, 0xbd, 0xf1,
- 0xe7, 0x4d, 0x5f, 0x3f, 0x7f, 0x97, 0x15, 0x2b, 0x26, 0x4f, 0xb6, 0xd2, 0xd3, 0xd7, 0xa7, 0x06,
- 0x80, 0x64, 0x7a, 0x1d, 0x71, 0x19, 0x50, 0x97, 0x24, 0x4d, 0xb0, 0x74, 0xce, 0x56, 0xe1, 0xc4,
- 0x6a, 0x40, 0x28, 0xd2, 0x7d, 0x5c, 0x5d, 0x65, 0x2d, 0xad, 0x78, 0xa7, 0x41, 0x5d, 0x5d, 0xdd,
- 0x5f, 0x67, 0xce, 0x84, 0xe0, 0x09, 0x0b, 0x0b, 0xcf, 0xcb, 0xcb, 0x87, 0x56, 0xff, 0x8c, 0x83,
- 0xab, 0x64, 0x64, 0x65, 0xcf, 0x9e, 0x3d, 0x57, 0x58, 0x54, 0x94, 0x94, 0x9c, 0x7c, 0x2f, 0x3e,
- 0x1e, 0xe1, 0x5b, 0x4a, 0x74, 0x28, 0x27, 0xe1, 0x40, 0x1d, 0x7b, 0x37, 0x59, 0xe2, 0xc1, 0x7d,
- 0xb3, 0x8d, 0x5b, 0xb2, 0x89, 0x2c, 0x71, 0x25, 0x39, 0x8e, 0x64, 0xd1, 0x2c, 0xb2, 0xc0, 0x82,
- 0xcc, 0xfd, 0x99, 0x06, 0x2d, 0x0d, 0xd7, 0x02, 0x2b, 0xf2, 0x95, 0x1d, 0xf9, 0xda, 0x95, 0xfb,
- 0x66, 0x2b, 0xb7, 0x6c, 0x17, 0x59, 0xee, 0xc3, 0x2d, 0xdf, 0xcb, 0x2d, 0xdf, 0xcd, 0x2d, 0xf3,
- 0xe2, 0x96, 0x7a, 0xd0, 0xd9, 0x9d, 0xba, 0xf4, 0x7a, 0x7d, 0x46, 0xcc, 0x8a, 0x49, 0xe6, 0xe6,
- 0x23, 0x46, 0x8c, 0x00, 0x56, 0xd1, 0xd0, 0xe0, 0xe6, 0x20, 0x95, 0x77, 0xec, 0xd8, 0x59, 0x55,
- 0xf9, 0x96, 0x39, 0xd9, 0x4d, 0x3a, 0xb7, 0x0c, 0xd3, 0xb7, 0x42, 0xa0, 0xf0, 0xfb, 0x36, 0x77,
- 0x4a, 0xcc, 0x3c, 0xf9, 0xd0, 0xee, 0x3d, 0xe2, 0xed, 0xe5, 0xf1, 0xe9, 0xe4, 0xe4, 0xd4, 0x81,
- 0x41, 0xf4, 0xf4, 0xf4, 0xca, 0xca, 0xca, 0xc4, 0x88, 0x15, 0x0f, 0x66, 0x31, 0x0a, 0xb6, 0xae,
- 0xae, 0x1e, 0x9e, 0xfa, 0x4b, 0x4e, 0xb5, 0xeb, 0x4c, 0x02, 0x1d, 0xa1, 0x36, 0x53, 0xd3, 0xd2,
- 0xd3, 0xd2, 0x33, 0x6e, 0x85, 0x85, 0x1f, 0x38, 0x70, 0xd0, 0xc5, 0x65, 0x85, 0xb9, 0x85, 0x85,
- 0xde, 0x10, 0x5d, 0xb7, 0xe9, 0xba, 0xc5, 0xb7, 0xf4, 0x88, 0x2c, 0x15, 0x5a, 0xa4, 0xe9, 0xd2,
- 0xa0, 0xd5, 0x6a, 0x81, 0x2e, 0x4b, 0xb5, 0xe2, 0xe1, 0x40, 0xd1, 0x5a, 0x5a, 0xd9, 0xae, 0x83,
- 0xd8, 0x6e, 0xf4, 0x1c, 0x15, 0x43, 0x43, 0x23, 0x07, 0x07, 0xc7, 0x83, 0x01, 0x01, 0x77, 0xef,
- 0xc5, 0x67, 0xb3, 0xd9, 0xc3, 0x87, 0x7f, 0xce, 0x62, 0x10, 0x59, 0x59, 0xd9, 0xb8, 0xb8, 0xbb,
- 0xd5, 0x35, 0xb5, 0x6f, 0x4a, 0xcb, 0x5e, 0x15, 0x17, 0x97, 0xe4, 0xbd, 0xac, 0xca, 0x49, 0xa8,
- 0x7f, 0x1d, 0xc3, 0xad, 0x8e, 0xe0, 0xd5, 0xdc, 0xe2, 0xd5, 0xdc, 0xe4, 0x55, 0x5f, 0xe1, 0x56,
- 0x9d, 0x24, 0xcb, 0x77, 0x93, 0xaf, 0x57, 0x91, 0x45, 0x33, 0xc9, 0xfc, 0x09, 0x44, 0xee, 0x48,
- 0x8a, 0x6c, 0x0b, 0x26, 0x93, 0xaf, 0x16, 0x90, 0x6f, 0x36, 0x73, 0x2b, 0x02, 0xb8, 0x6f, 0x2f,
- 0x72, 0x6b, 0xc3, 0xb8, 0xb5, 0x91, 0xbc, 0xda, 0x28, 0x3a, 0xdf, 0xe6, 0xd5, 0x86, 0xd1, 0x19,
- 0x25, 0x5c, 0xe7, 0xbd, 0x3d, 0xc7, 0xad, 0x38, 0xbc, 0x6d, 0xcb, 0x4a, 0xf8, 0x3b, 0x00, 0x75,
- 0xdc, 0xf8, 0xf1, 0xd3, 0xa6, 0x4f, 0x77, 0x76, 0x76, 0xf6, 0xdc, 0xb1, 0x03, 0xde, 0xa1, 0xac,
- 0xbc, 0x5c, 0xbc, 0xda, 0x54, 0xd4, 0x21, 0x2f, 0x44, 0x8b, 0xf4, 0xd0, 0x52, 0x73, 0xeb, 0x1e,
- 0x7b, 0xc9, 0xfb, 0x25, 0x7e, 0xd5, 0x66, 0xe2, 0x9f, 0xb0, 0x63, 0x4a, 0x3c, 0xc0, 0x6a, 0x67,
- 0x6f, 0xff, 0x31, 0x6b, 0x00, 0x8a, 0xc7, 0x8f, 0x9f, 0x20, 0xb9, 0x3c, 0xc9, 0x7d, 0x06, 0xc4,
- 0x5b, 0xd3, 0xe3, 0xe7, 0xf0, 0xd4, 0xe2, 0xbd, 0xe6, 0x80, 0xab, 0x7e, 0xfd, 0xfa, 0x21, 0x80,
- 0x45, 0x98, 0x86, 0x66, 0x88, 0x4f, 0x35, 0x35, 0x35, 0x08, 0x4e, 0x90, 0x24, 0xd3, 0xd7, 0xfa,
- 0x25, 0x09, 0x25, 0x38, 0x39, 0x2d, 0x86, 0x38, 0xc9, 0xc8, 0x7c, 0x09, 0xd0, 0xfa, 0xfb, 0x1f,
- 0x70, 0x73, 0x75, 0xf1, 0x77, 0x9b, 0x93, 0x77, 0xc9, 0xaa, 0x21, 0x73, 0x88, 0x28, 0x04, 0xd6,
- 0xa0, 0x3b, 0xc6, 0x41, 0xb6, 0x08, 0x34, 0x06, 0x53, 0x00, 0xce, 0x56, 0x2d, 0x8d, 0x57, 0xef,
- 0x6a, 0x2b, 0x13, 0x45, 0x1b, 0x5f, 0xf4, 0x37, 0x35, 0x1d, 0x0b, 0x07, 0xf7, 0xfb, 0xa9, 0xe0,
- 0xc4, 0xa4, 0xe4, 0x88, 0x88, 0xdb, 0x30, 0x9a, 0xf4, 0x8b, 0x83, 0x8a, 0x55, 0xe8, 0x04, 0x4b,
- 0xb6, 0xbb, 0xd9, 0xef, 0xc0, 0x81, 0x03, 0xab, 0xde, 0xbe, 0x6d, 0x6a, 0x22, 0x1a, 0xea, 0xeb,
- 0x0b, 0x73, 0xd9, 0xf1, 0xd1, 0xe1, 0x71, 0x91, 0x57, 0xef, 0x45, 0x87, 0xc6, 0xc7, 0x5d, 0x8c,
- 0x8f, 0xbb, 0x10, 0x1f, 0x7b, 0x2e, 0x3e, 0x26, 0xa4, 0xae, 0x22, 0x9a, 0xf7, 0xf6, 0x34, 0x59,
- 0xea, 0x09, 0xa7, 0x4f, 0x14, 0x58, 0x92, 0x79, 0xa6, 0x64, 0xbe, 0x19, 0x59, 0x34, 0x9b, 0x2c,
- 0x59, 0x0b, 0x28, 0x02, 0x99, 0x65, 0xc5, 0x71, 0xd4, 0x9d, 0xd4, 0x4f, 0x42, 0xe9, 0x7c, 0x49,
- 0xf8, 0xf3, 0xb8, 0xf3, 0xf1, 0xb1, 0x67, 0x5f, 0xa6, 0x5c, 0x6b, 0xaa, 0x0a, 0x2b, 0xcf, 0x09,
- 0xf4, 0xde, 0xe1, 0xb6, 0x60, 0xc1, 0xc2, 0x45, 0x0e, 0x0e, 0x90, 0x04, 0x7e, 0x7e, 0xfe, 0xa8,
- 0xfd, 0xf8, 0xf8, 0xfb, 0xb1, 0x71, 0x71, 0x31, 0xb1, 0xb1, 0xf7, 0xef, 0x27, 0xdc, 0x4f, 0x78,
- 0x80, 0x9c, 0x40, 0x67, 0xfc, 0x91, 0x96, 0x9e, 0xce, 0xec, 0xc9, 0x2a, 0x89, 0x52, 0x92, 0xe4,
- 0xe2, 0x7b, 0xc9, 0xdb, 0x90, 0x9f, 0x25, 0x26, 0x56, 0x54, 0x54, 0x8a, 0x87, 0x50, 0xeb, 0xea,
- 0x1b, 0xf0, 0xcd, 0x7d, 0xd1, 0x55, 0x26, 0xc3, 0xc3, 0x22, 0xba, 0x17, 0x08, 0x9a, 0x81, 0x3a,
- 0x5b, 0x5b, 0xdb, 0x8f, 0xe1, 0xe4, 0xe7, 0x9f, 0x7f, 0x66, 0xb3, 0xd9, 0xc2, 0xfe, 0x81, 0x0f,
- 0xad, 0x10, 0x8b, 0x67, 0x40, 0x09, 0x3b, 0x77, 0x7a, 0x99, 0x98, 0x98, 0x98, 0x99, 0x99, 0x01,
- 0x15, 0xab, 0x56, 0xad, 0xf6, 0xf5, 0xf3, 0x43, 0x20, 0x80, 0xe7, 0x87, 0x7b, 0x8a, 0x89, 0x89,
- 0xbd, 0x79, 0xf3, 0x66, 0x50, 0x50, 0x10, 0x1a, 0x23, 0xac, 0xfd, 0x85, 0x88, 0xed, 0x46, 0x07,
- 0x62, 0x6b, 0xd7, 0xae, 0xcd, 0xce, 0x66, 0xa7, 0xa6, 0xa5, 0xdd, 0x0e, 0xfb, 0xf3, 0x6e, 0xe8,
- 0xd1, 0xbc, 0x30, 0xf7, 0xea, 0xc4, 0xd9, 0x44, 0x8e, 0x31, 0x99, 0xab, 0x27, 0xea, 0x99, 0x51,
- 0xa2, 0xb2, 0xb0, 0xe3, 0x51, 0x83, 0xc8, 0xee, 0x5f, 0x12, 0x37, 0x78, 0xf6, 0xec, 0x39, 0x06,
- 0x06, 0x06, 0x10, 0x60, 0x5d, 0x04, 0xb1, 0x10, 0xb1, 0xbd, 0x7b, 0xf7, 0x46, 0x8b, 0x86, 0x20,
- 0xdf, 0xbc, 0x65, 0x0b, 0x82, 0x4a, 0x34, 0x43, 0x98, 0x4e, 0x5e, 0x5e, 0x5e, 0xfa, 0xad, 0xe1,
- 0x5c, 0x42, 0x42, 0x4e, 0x23, 0x43, 0xee, 0xb6, 0x1b, 0x2c, 0x80, 0xf7, 0xf8, 0x02, 0x01, 0x97,
- 0xc7, 0xe3, 0x91, 0xe4, 0xc9, 0xa0, 0x13, 0xc6, 0x46, 0x46, 0x3a, 0xda, 0xda, 0x3a, 0xda, 0x5a,
- 0x3a, 0x3a, 0x74, 0xd6, 0xd6, 0xd2, 0xd7, 0xd7, 0xad, 0x7c, 0x93, 0xc8, 0xab, 0xbd, 0xc9, 0x2d,
- 0xff, 0x8d, 0xe4, 0x2c, 0x25, 0x0a, 0xa6, 0x12, 0x80, 0x6b, 0xc1, 0x54, 0x92, 0xb3, 0x98, 0x5b,
- 0xb6, 0x9b, 0x5b, 0x7d, 0x99, 0xdf, 0xf8, 0xe2, 0x64, 0x90, 0x7f, 0xcb, 0x4f, 0x24, 0xb3, 0x36,
- 0x95, 0x77, 0x78, 0x6e, 0xac, 0x2e, 0x4b, 0x20, 0xab, 0x42, 0x5f, 0x3c, 0x38, 0xe8, 0xe1, 0xb1,
- 0xdd, 0x6b, 0xd7, 0xae, 0xa3, 0xc7, 0x8e, 0x85, 0x47, 0x44, 0xa0, 0x22, 0xc2, 0xc2, 0xc3, 0x67,
- 0xce, 0x9c, 0x89, 0x48, 0x07, 0xba, 0x4b, 0xa7, 0x75, 0x02, 0x2a, 0x8a, 0x39, 0x9c, 0x96, 0x49,
- 0x7d, 0x34, 0x1a, 0x4b, 0xde, 0x94, 0x5a, 0xdb, 0xd8, 0xb4, 0xb9, 0x73, 0xda, 0xb4, 0x69, 0x4f,
- 0x9e, 0x3c, 0x65, 0xee, 0xe4, 0xf1, 0xf8, 0x91, 0x77, 0xa2, 0x8c, 0xf0, 0x16, 0x12, 0x49, 0x5f,
- 0x5f, 0x7f, 0xd3, 0xa6, 0x4d, 0x65, 0xe5, 0x15, 0x7c, 0x1a, 0xb1, 0x10, 0xff, 0xed, 0x22, 0xa4,
- 0x67, 0xcf, 0x9e, 0xde, 0xde, 0xde, 0xef, 0xea, 0xea, 0xc5, 0x27, 0xd4, 0x8b, 0x13, 0x83, 0xd8,
- 0x9a, 0x9a, 0xda, 0x87, 0x8f, 0x1e, 0x27, 0x3c, 0x78, 0x90, 0x93, 0x93, 0xdb, 0xd0, 0xd0, 0x28,
- 0x90, 0x58, 0x6b, 0xc0, 0x64, 0x40, 0x1a, 0xb2, 0x6a, 0xdd, 0xba, 0x75, 0xaa, 0xaa, 0xaa, 0x5f,
- 0x8e, 0xd8, 0x6e, 0x74, 0x68, 0xec, 0xee, 0xee, 0xce, 0xce, 0x66, 0xbd, 0xc9, 0xcf, 0xa8, 0x78,
- 0x19, 0xf9, 0x36, 0xfd, 0x48, 0x63, 0xde, 0x72, 0xca, 0xbb, 0xe5, 0x19, 0x53, 0x61, 0x57, 0x96,
- 0x32, 0xd5, 0xf1, 0x28, 0x1c, 0xdc, 0x51, 0xa4, 0x06, 0x77, 0x58, 0x4a, 0x45, 0x91, 0x3a, 0x90,
- 0xc1, 0x06, 0x06, 0x43, 0xe5, 0xe4, 0xba, 0x04, 0x62, 0xc5, 0x3d, 0xb1, 0xa8, 0xe1, 0x19, 0xb6,
- 0xb6, 0xde, 0xde, 0xbb, 0x51, 0xe9, 0x30, 0xe0, 0x62, 0x67, 0xe7, 0x76, 0xc5, 0x15, 0x48, 0x8c,
- 0x31, 0xe6, 0x1f, 0x7f, 0x84, 0xb4, 0x8b, 0x58, 0x5f, 0x5f, 0x3f, 0x30, 0x0f, 0x9f, 0xcf, 0x27,
- 0x49, 0x72, 0xc9, 0x92, 0x25, 0xd2, 0x3c, 0x6c, 0x60, 0xa0, 0xc7, 0x6b, 0xca, 0xe5, 0xd5, 0x46,
- 0x70, 0xcb, 0x7d, 0x49, 0xce, 0x32, 0x02, 0x71, 0x56, 0xbe, 0x05, 0x08, 0x96, 0x5b, 0xb2, 0x8e,
- 0x5b, 0x79, 0x8c, 0x1a, 0x34, 0x6f, 0x2c, 0x9c, 0x68, 0xd6, 0xd1, 0x5a, 0x3f, 0xef, 0x5d, 0xdb,
- 0xdf, 0x55, 0xbd, 0x80, 0x5a, 0xa8, 0xe6, 0x5c, 0x8c, 0x8e, 0x38, 0x75, 0xee, 0xdc, 0xf9, 0xe8,
- 0xe8, 0x98, 0xac, 0x2c, 0x16, 0x9e, 0x1c, 0x22, 0xe1, 0x63, 0x9a, 0x10, 0x6e, 0xd1, 0xc3, 0xc3,
- 0x83, 0x7e, 0xf8, 0x66, 0x21, 0x24, 0x04, 0xcd, 0xa0, 0x4a, 0x19, 0x19, 0x99, 0x36, 0x77, 0x4e,
- 0x9a, 0x34, 0x29, 0xbf, 0xa0, 0x80, 0xe2, 0x4f, 0x41, 0x33, 0x40, 0x05, 0x00, 0xb7, 0xb9, 0x01,
- 0xe2, 0xf9, 0xe6, 0xad, 0x5b, 0x3c, 0xbe, 0x80, 0x41, 0xec, 0xa8, 0x51, 0xa3, 0xda, 0xfd, 0x1f,
- 0x35, 0xb5, 0xb4, 0xee, 0x44, 0x45, 0x09, 0xc4, 0xe7, 0x7c, 0x4b, 0xc6, 0x7a, 0x12, 0xc2, 0xa0,
- 0x65, 0x51, 0x8c, 0xa0, 0x19, 0x65, 0x0a, 0x8b, 0x15, 0x34, 0xb3, 0x58, 0xac, 0xf5, 0xeb, 0xd7,
- 0x0f, 0x1b, 0x36, 0x0c, 0x6a, 0x41, 0xba, 0x70, 0xe8, 0x87, 0xcf, 0xdb, 0x1e, 0x1c, 0xe1, 0xea,
- 0x9e, 0xdd, 0xbb, 0xca, 0x39, 0xb9, 0x8d, 0xe5, 0xa9, 0x8d, 0x25, 0xd7, 0xb8, 0x25, 0x5e, 0x24,
- 0x22, 0xdc, 0xbc, 0x89, 0x24, 0xdb, 0x80, 0x60, 0x0d, 0x6a, 0x01, 0x2d, 0x35, 0xc4, 0xa3, 0x00,
- 0xdc, 0xe6, 0x47, 0xe8, 0xdb, 0xd9, 0xd9, 0x75, 0x9d, 0x2d, 0x64, 0x45, 0xfb, 0x0f, 0xf7, 0x1b,
- 0x3a, 0x74, 0xd8, 0x7c, 0x3b, 0x3b, 0xc8, 0x9b, 0xbb, 0xf7, 0xee, 0x25, 0x27, 0x3f, 0xb7, 0xb0,
- 0xb0, 0x90, 0x7e, 0x59, 0xb4, 0x50, 0x44, 0x0a, 0xa8, 0x02, 0x1e, 0x9f, 0xbf, 0x69, 0xf3, 0xe6,
- 0x76, 0x2d, 0x49, 0xb1, 0x13, 0x10, 0x2b, 0x68, 0x2e, 0x2a, 0x7a, 0x65, 0x69, 0x69, 0x29, 0x7d,
- 0xc3, 0xb2, 0x65, 0xce, 0x7c, 0x82, 0x0d, 0x41, 0xcb, 0x2d, 0xdb, 0x4b, 0x72, 0x96, 0x90, 0x85,
- 0xd6, 0x14, 0xc1, 0x16, 0x3b, 0x72, 0x4b, 0xbd, 0xb8, 0x6f, 0x2f, 0xf1, 0x1b, 0x5e, 0xa4, 0xbe,
- 0xb8, 0x8f, 0x18, 0xb6, 0x03, 0x9b, 0x07, 0x07, 0x1f, 0x23, 0xea, 0xf3, 0x78, 0xf5, 0x4f, 0x79,
- 0xb5, 0xb1, 0x6f, 0x5f, 0xc7, 0xa5, 0xa7, 0x3c, 0x61, 0xe7, 0xe4, 0x42, 0xc6, 0x80, 0xfa, 0x3a,
- 0x0e, 0x15, 0x35, 0x34, 0x34, 0xa8, 0x2d, 0xd7, 0xa8, 0xf9, 0x25, 0xcd, 0x0c, 0xd8, 0xe0, 0x2c,
- 0xda, 0xdc, 0x03, 0x62, 0x44, 0x24, 0x45, 0x72, 0xb9, 0xcc, 0x0d, 0xf0, 0xd1, 0x6d, 0x8e, 0x40,
- 0xc2, 0x5b, 0xaf, 0x5a, 0xb5, 0xaa, 0xbe, 0xbe, 0x41, 0x5c, 0x08, 0xd8, 0xbc, 0xdd, 0xff, 0x6e,
- 0xfe, 0xfc, 0xf9, 0xc5, 0xc5, 0x1c, 0x31, 0xc1, 0xb6, 0x42, 0x6c, 0xcb, 0xae, 0x32, 0x42, 0x79,
- 0x8c, 0x72, 0x50, 0x1a, 0x28, 0x9d, 0x47, 0x4d, 0x97, 0x6d, 0x4e, 0x4c, 0x4a, 0x1a, 0x3d, 0x7a,
- 0xb4, 0xf4, 0xde, 0x1d, 0x68, 0x8f, 0xa6, 0xa6, 0xa6, 0x47, 0x8f, 0x1e, 0x7d, 0xf2, 0xe4, 0x09,
- 0x64, 0x83, 0xc9, 0xa7, 0x77, 0x32, 0xa0, 0xe5, 0xaa, 0xa9, 0xa9, 0x1e, 0x0e, 0xf0, 0xab, 0xad,
- 0xcc, 0xe3, 0xbe, 0x7b, 0xca, 0xad, 0x0a, 0x41, 0x38, 0x4c, 0x16, 0xcd, 0x23, 0xf3, 0xc6, 0x52,
- 0x7d, 0x8c, 0xac, 0x01, 0xf4, 0xe0, 0x78, 0xcb, 0xc4, 0x8f, 0x37, 0x77, 0x07, 0x3b, 0x3a, 0x3a,
- 0xa1, 0x55, 0x32, 0xb3, 0x64, 0xff, 0xeb, 0x83, 0x08, 0x54, 0x4f, 0x6c, 0xcf, 0x9e, 0x8a, 0xf4,
- 0xf2, 0x2b, 0x67, 0xe7, 0x25, 0xc7, 0x4f, 0x9c, 0x00, 0xe4, 0xae, 0x5d, 0xbf, 0x31, 0x74, 0xe8,
- 0x50, 0xe9, 0x97, 0x35, 0x37, 0x37, 0x67, 0x0c, 0x5b, 0xcc, 0x79, 0x3d, 0x73, 0xe6, 0x2c, 0xe9,
- 0x1b, 0x20, 0x2d, 0x2a, 0xab, 0xde, 0x32, 0x55, 0x09, 0x31, 0x06, 0xf1, 0x23, 0x7d, 0xcf, 0xc5,
- 0x0b, 0xc1, 0xfc, 0xc6, 0x54, 0x6e, 0xf5, 0x25, 0x6e, 0xe9, 0x4e, 0xaa, 0x75, 0x17, 0xda, 0x90,
- 0x45, 0xbf, 0x72, 0x11, 0x85, 0x55, 0x1c, 0xe2, 0xd5, 0xde, 0xe1, 0x37, 0xe5, 0xed, 0xf2, 0xda,
- 0xde, 0x6e, 0x5b, 0x10, 0x57, 0xd9, 0xed, 0x88, 0x1b, 0x02, 0x6e, 0x19, 0xaf, 0x89, 0xc5, 0x6b,
- 0x4c, 0xe3, 0x35, 0x66, 0x95, 0x97, 0xe6, 0x9f, 0x3d, 0x7b, 0x16, 0xff, 0xf5, 0xdf, 0x56, 0x16,
- 0x0c, 0x3e, 0x6f, 0xde, 0xbc, 0xda, 0x77, 0xef, 0xc4, 0x60, 0x43, 0x5d, 0xb4, 0xb9, 0x07, 0x4c,
- 0x72, 0xe8, 0xd0, 0x21, 0x86, 0xf4, 0xe0, 0xf7, 0xd1, 0x0a, 0xda, 0xdc, 0x80, 0xa8, 0xb9, 0xa8,
- 0xa8, 0x88, 0xb1, 0x03, 0x53, 0x48, 0x1b, 0xf9, 0x84, 0x87, 0x87, 0xec, 0x44, 0x6b, 0x8d, 0x8a,
- 0x8a, 0x16, 0x08, 0x19, 0xf6, 0xaf, 0x0f, 0xad, 0x3b, 0xd7, 0xc4, 0x1d, 0x5c, 0x62, 0xd0, 0xf2,
- 0x19, 0x82, 0xe5, 0xf1, 0x09, 0x92, 0xbc, 0x15, 0x16, 0x86, 0x70, 0xac, 0x4d, 0xb4, 0x85, 0x17,
- 0x1f, 0x39, 0xd2, 0x24, 0x34, 0x34, 0xb4, 0xaa, 0xaa, 0x8a, 0x20, 0x09, 0x81, 0x40, 0x50, 0x57,
- 0x57, 0xf7, 0xb7, 0x5d, 0xc1, 0xed, 0x26, 0x94, 0x0c, 0xf8, 0xfd, 0x7e, 0x32, 0xb0, 0xae, 0x9a,
- 0xc5, 0xab, 0xbb, 0xcb, 0xad, 0x0c, 0x22, 0xdf, 0x6c, 0x22, 0x8b, 0xe6, 0x10, 0x79, 0xa6, 0x14,
- 0x68, 0xb3, 0x07, 0x12, 0xac, 0xfe, 0xf4, 0x38, 0x23, 0x85, 0xdb, 0x9a, 0x64, 0x15, 0x37, 0x37,
- 0x37, 0xf8, 0x1d, 0xb4, 0x77, 0xb4, 0xa0, 0xff, 0xba, 0x30, 0x10, 0x6d, 0x7c, 0x31, 0x00, 0x11,
- 0xb7, 0xdb, 0x9a, 0x35, 0x67, 0xcf, 0x9d, 0x4f, 0x4d, 0x4b, 0xf7, 0xf7, 0xf7, 0x6f, 0x97, 0xe5,
- 0xf6, 0xec, 0xd9, 0xc3, 0xd4, 0x14, 0x42, 0x0f, 0xa3, 0xf6, 0xf6, 0xa6, 0xb6, 0xb7, 0xb7, 0xaf,
- 0x13, 0x92, 0x8f, 0xe0, 0xc8, 0x91, 0x23, 0x8c, 0x1f, 0x91, 0x4c, 0xf0, 0x65, 0xac, 0x97, 0x4f,
- 0x78, 0xf5, 0x8f, 0x79, 0x55, 0xa7, 0xb8, 0x6f, 0x36, 0x53, 0x7d, 0x59, 0x85, 0x36, 0x04, 0x3e,
- 0x4b, 0xb6, 0xa2, 0xb1, 0xe3, 0xfb, 0xca, 0x32, 0xd6, 0x58, 0xd3, 0xd1, 0x1d, 0x84, 0xc6, 0x88,
- 0xec, 0x12, 0x12, 0xee, 0xf2, 0x79, 0x35, 0x7c, 0xa2, 0x94, 0x4f, 0xbe, 0x6e, 0x6a, 0x28, 0x09,
- 0x0e, 0x3e, 0x8e, 0x98, 0xba, 0x93, 0x95, 0x85, 0x37, 0xbd, 0x70, 0xf1, 0x22, 0xe3, 0x05, 0x00,
- 0x0f, 0xe9, 0x03, 0xb9, 0x50, 0x2f, 0x08, 0xc1, 0xf0, 0x9a, 0x04, 0x41, 0x42, 0x45, 0xb4, 0x69,
- 0x3b, 0xe0, 0xdb, 0xb3, 0x67, 0xcf, 0x89, 0xe1, 0xca, 0x14, 0xc2, 0x10, 0x3b, 0x3e, 0x01, 0x54,
- 0x93, 0x91, 0x23, 0x3d, 0x3d, 0x3d, 0xd3, 0xd2, 0x33, 0x60, 0x01, 0x46, 0x30, 0xb7, 0x11, 0x04,
- 0x12, 0xdd, 0xc5, 0x12, 0xf3, 0x0a, 0xde, 0x0b, 0x09, 0x96, 0x20, 0xb9, 0xe1, 0xe1, 0x11, 0x3a,
- 0x52, 0xa4, 0x0d, 0x01, 0xe0, 0xe2, 0xb2, 0xbc, 0xb2, 0xb2, 0x82, 0xcf, 0xe7, 0xd2, 0x99, 0xd2,
- 0x0e, 0x88, 0x70, 0x6d, 0x66, 0xcc, 0xe8, 0xe4, 0x8b, 0x4b, 0x27, 0x3c, 0xed, 0xe9, 0x90, 0x13,
- 0x4d, 0x75, 0x59, 0xfc, 0x77, 0x31, 0xdc, 0xca, 0xe3, 0x64, 0xe9, 0x36, 0x92, 0xe3, 0x40, 0x14,
- 0x4c, 0xa1, 0x46, 0x70, 0x72, 0x47, 0x10, 0x39, 0xba, 0xd4, 0x88, 0x2d, 0x4b, 0xb9, 0x21, 0x5d,
- 0x39, 0x70, 0xbf, 0x0b, 0x5a, 0x3a, 0xc4, 0x3c, 0x70, 0xfe, 0xb1, 0x79, 0xb6, 0xff, 0xb1, 0xc4,
- 0x88, 0x58, 0x2d, 0x2d, 0xea, 0x58, 0x58, 0x77, 0x77, 0x8f, 0x1b, 0x7f, 0xfe, 0x09, 0x6b, 0xaf,
- 0x5e, 0xed, 0x26, 0xed, 0x5e, 0xa1, 0x48, 0x21, 0x18, 0x98, 0xca, 0x3a, 0x73, 0xf6, 0x6c, 0xbb,
- 0xd1, 0xeb, 0xe1, 0xc3, 0x81, 0xb0, 0x39, 0x6e, 0x40, 0xc8, 0x80, 0xb0, 0x54, 0x1a, 0x78, 0x13,
- 0x26, 0x8c, 0x7f, 0x5d, 0x9c, 0x4a, 0xb5, 0xeb, 0x8a, 0x40, 0xb2, 0x64, 0x0d, 0x59, 0x34, 0x97,
- 0x1a, 0x17, 0xe0, 0x38, 0x71, 0xcb, 0x7c, 0xb8, 0xd5, 0xd7, 0xf8, 0x4d, 0x19, 0xb7, 0x6e, 0x5e,
- 0x54, 0x57, 0xef, 0x88, 0x2d, 0x8d, 0x8d, 0x8d, 0x9f, 0x3f, 0x4f, 0xe2, 0xf3, 0x1b, 0x79, 0xdc,
- 0x77, 0x7c, 0x5e, 0x2d, 0x8b, 0x95, 0x66, 0x65, 0xd5, 0x7e, 0xe0, 0xd3, 0x6e, 0x52, 0x52, 0x52,
- 0x82, 0x1f, 0xa1, 0x63, 0xfc, 0xe6, 0x82, 0xc2, 0x42, 0xe9, 0x27, 0x44, 0xf9, 0x95, 0x95, 0x55,
- 0x78, 0xcd, 0x47, 0x8f, 0x1e, 0xeb, 0xe9, 0xe9, 0xb5, 0xb9, 0x6a, 0x6d, 0x6d, 0x83, 0x26, 0x29,
- 0x10, 0x88, 0x75, 0x45, 0x73, 0xd5, 0xff, 0x12, 0x77, 0xa5, 0x41, 0x51, 0x5c, 0xed, 0xfa, 0x67,
- 0xee, 0xad, 0xa4, 0xea, 0xab, 0xfa, 0x72, 0xab, 0x72, 0x73, 0x5d, 0xbe, 0xba, 0x31, 0x1a, 0xaf,
- 0x89, 0x0b, 0x5a, 0x51, 0xf3, 0x89, 0x1a, 0x35, 0x5e, 0x83, 0x71, 0x41, 0xa2, 0x46, 0x13, 0x8d,
- 0x6b, 0xdc, 0x89, 0x1b, 0x0a, 0xa2, 0xc1, 0x2d, 0x8a, 0xb8, 0xc6, 0x25, 0xc6, 0x0d, 0x41, 0x11,
- 0x05, 0x5c, 0x40, 0x04, 0x11, 0x86, 0x5d, 0x51, 0x01, 0x05, 0x91, 0x7d, 0x9b, 0x61, 0x99, 0x7d,
- 0x5f, 0xfb, 0x74, 0x0f, 0x5a, 0x75, 0x9f, 0xd3, 0xad, 0xed, 0xd0, 0x33, 0xf1, 0xc3, 0x84, 0xd4,
- 0x3d, 0x35, 0x65, 0x8d, 0x43, 0x4f, 0x4f, 0xf7, 0x39, 0xcf, 0x79, 0xdf, 0xe7, 0x79, 0xdf, 0xf7,
- 0x9c, 0xd6, 0x1b, 0xde, 0xe2, 0x67, 0xe2, 0xe4, 0xc9, 0x93, 0x8f, 0x1e, 0x3b, 0xd6, 0xd4, 0x2c,
- 0xe7, 0x17, 0xc1, 0xbc, 0x2a, 0x26, 0xf4, 0x34, 0xb0, 0x9e, 0xa1, 0x5e, 0x49, 0xf0, 0x8d, 0x9e,
- 0x90, 0x73, 0x57, 0x55, 0x57, 0x4f, 0x99, 0x32, 0x55, 0xd2, 0xf9, 0xd0, 0x0b, 0xa1, 0xa1, 0xa1,
- 0x26, 0x93, 0x1e, 0xe2, 0x80, 0xe3, 0x5c, 0xfc, 0x0b, 0x9d, 0xcc, 0x95, 0x95, 0x95, 0xfd, 0xc9,
- 0xe7, 0x86, 0xe0, 0xcc, 0x37, 0x93, 0xe3, 0x19, 0x5b, 0x15, 0x6b, 0xc9, 0x22, 0xfa, 0xb3, 0x8c,
- 0x2a, 0xc2, 0xd5, 0xba, 0xd4, 0xd5, 0x34, 0x85, 0x1a, 0xdb, 0xfa, 0x61, 0xae, 0xba, 0x81, 0x34,
- 0xe4, 0x55, 0xdd, 0xb3, 0xfd, 0xde, 0x87, 0x91, 0xdb, 0xbe, 0x01, 0x42, 0xd0, 0x21, 0x70, 0x28,
- 0x42, 0x1d, 0xd7, 0xff, 0x0b, 0x68, 0xc5, 0xf5, 0xad, 0xe0, 0xd5, 0x98, 0x44, 0xfb, 0xa2, 0xa2,
- 0x64, 0xb2, 0x6c, 0xa8, 0xd7, 0xe9, 0xd3, 0x7d, 0xcc, 0x5c, 0x98, 0x23, 0x0c, 0x31, 0x46, 0x03,
- 0x14, 0x6e, 0xfb, 0xf6, 0xed, 0xde, 0x90, 0x86, 0x84, 0x81, 0x2e, 0xc3, 0x78, 0xa1, 0xf3, 0x6b,
- 0xeb, 0xea, 0xa0, 0xc1, 0xbd, 0x4f, 0xb2, 0x7e, 0x7d, 0xb0, 0x51, 0xf7, 0x94, 0x35, 0xa7, 0x11,
- 0xed, 0x01, 0xa6, 0x6d, 0x15, 0x45, 0xac, 0x7c, 0x36, 0x4d, 0x19, 0x68, 0x8f, 0xb1, 0x96, 0x3b,
- 0x2e, 0x5b, 0xed, 0xa6, 0x90, 0x1f, 0xc5, 0xd4, 0x30, 0xec, 0x3c, 0x94, 0x14, 0x18, 0xb5, 0xa7,
- 0x38, 0x0a, 0x08, 0x08, 0xa8, 0xae, 0xa9, 0xe6, 0xed, 0x0c, 0x06, 0x8e, 0xb9, 0x73, 0xe7, 0xf6,
- 0xa0, 0x41, 0x9d, 0x1c, 0x37, 0xbe, 0x1e, 0x14, 0x14, 0xb4, 0x89, 0x6f, 0xf3, 0xe6, 0xcd, 0x43,
- 0xf7, 0x7a, 0xfe, 0x15, 0x3e, 0x3d, 0x3b, 0x27, 0x57, 0xe4, 0xa8, 0x92, 0xcb, 0xc3, 0x4d, 0xcd,
- 0x9f, 0x3f, 0x9f, 0xd6, 0xa6, 0x1a, 0x0c, 0xab, 0x56, 0xad, 0x92, 0x30, 0x58, 0x10, 0x0f, 0x99,
- 0x4c, 0x26, 0x18, 0x4f, 0x51, 0xc1, 0xd5, 0x37, 0x34, 0x60, 0xdc, 0x77, 0xee, 0xdc, 0x59, 0x5d,
- 0x53, 0x4b, 0xf8, 0x67, 0xcf, 0xbf, 0xaa, 0x7d, 0x15, 0xf2, 0x11, 0x9d, 0x13, 0x16, 0x2f, 0x69,
- 0x80, 0xe4, 0x45, 0xbf, 0xe5, 0x70, 0x3a, 0xbd, 0x1d, 0x53, 0x9f, 0x3e, 0x7d, 0xf6, 0xed, 0xdb,
- 0xc7, 0x5b, 0x57, 0xc0, 0xd5, 0xc9, 0xbf, 0xe8, 0x8d, 0x13, 0xc2, 0xac, 0x5c, 0xb9, 0xd2, 0x27,
- 0x0e, 0xdf, 0xa8, 0xf9, 0xf9, 0x0d, 0xbe, 0x9d, 0x96, 0xc8, 0x81, 0x62, 0x51, 0xd0, 0x9e, 0x63,
- 0xd4, 0xa0, 0x6a, 0x8b, 0xa0, 0x2c, 0x5c, 0x0d, 0xfe, 0xae, 0xba, 0x61, 0x7c, 0xa5, 0x47, 0x3f,
- 0xe7, 0xd3, 0x1e, 0x15, 0x37, 0xfd, 0xb6, 0xac, 0x9d, 0x0d, 0x5a, 0x28, 0x56, 0x3e, 0xd3, 0x05,
- 0x8f, 0x3c, 0xc1, 0x90, 0xb4, 0xbf, 0xb4, 0xc4, 0x4b, 0x88, 0xc4, 0xa2, 0xc3, 0xfd, 0xfd, 0xfd,
- 0x7f, 0xf8, 0x61, 0xd9, 0x6f, 0xa7, 0x4e, 0x3d, 0x78, 0xf0, 0x10, 0x8a, 0x7b, 0xc8, 0x10, 0x3f,
- 0xef, 0x5b, 0x9b, 0xfd, 0xcd, 0x37, 0x1a, 0x2d, 0x8d, 0xe7, 0x34, 0xcb, 0x15, 0x80, 0xb7, 0xf7,
- 0x01, 0x50, 0x01, 0xd5, 0x35, 0x35, 0x82, 0xf1, 0x01, 0x74, 0xbd, 0x19, 0x20, 0x6e, 0x33, 0x36,
- 0xe6, 0xb4, 0xcb, 0x5a, 0xc5, 0x9a, 0xae, 0x12, 0xcd, 0xcf, 0x4c, 0xeb, 0x32, 0x46, 0x31, 0x87,
- 0x51, 0x2c, 0x60, 0x94, 0x61, 0xc4, 0x10, 0x03, 0x25, 0x55, 0x53, 0x75, 0x77, 0xd2, 0xa4, 0x2f,
- 0xc4, 0xe3, 0x03, 0x02, 0x26, 0xe3, 0x7a, 0xd2, 0xd3, 0x6f, 0x7f, 0xe8, 0xb1, 0x15, 0x1b, 0x10,
- 0xd5, 0xd2, 0xda, 0x02, 0x0b, 0xc3, 0xbf, 0xdc, 0x67, 0xcf, 0x9e, 0x95, 0x48, 0xe6, 0x01, 0x03,
- 0x06, 0xa4, 0xa7, 0xa7, 0x83, 0xe3, 0x99, 0xcc, 0x96, 0x4b, 0x97, 0x2e, 0x49, 0x66, 0x16, 0xee,
- 0xb4, 0x5d, 0xa9, 0x12, 0x10, 0xeb, 0x3d, 0xe2, 0xe8, 0x8d, 0x5f, 0x7f, 0xfd, 0x15, 0x50, 0xbc,
- 0x71, 0x23, 0x59, 0x52, 0x05, 0x04, 0xe4, 0x87, 0x87, 0x6f, 0x35, 0x99, 0xcc, 0x22, 0x26, 0x05,
- 0xd0, 0x56, 0x55, 0x55, 0x45, 0x9f, 0x3f, 0x6f, 0x30, 0x9a, 0x84, 0xd8, 0xac, 0x58, 0x9d, 0xf5,
- 0x22, 0x00, 0xeb, 0x03, 0xae, 0xf4, 0x99, 0xb6, 0x75, 0xf5, 0xf5, 0xf7, 0xef, 0x3f, 0xc8, 0x92,
- 0xc9, 0xd0, 0xdb, 0x19, 0x19, 0x19, 0x78, 0x83, 0x57, 0xd2, 0xd5, 0xab, 0xd3, 0xa6, 0x4d, 0xf3,
- 0xfc, 0x51, 0x78, 0xe1, 0xbd, 0x7b, 0xf7, 0xea, 0x0d, 0x7a, 0x1a, 0x42, 0x78, 0x61, 0x60, 0x29,
- 0x62, 0xdd, 0x6e, 0xf6, 0xea, 0xd5, 0x24, 0x9f, 0xe1, 0xc7, 0x37, 0x6d, 0xb8, 0xaf, 0xcf, 0xc7,
- 0x8e, 0x2e, 0xc8, 0xbb, 0xc5, 0x39, 0x6b, 0x58, 0xb3, 0x8c, 0x82, 0x56, 0x19, 0x0e, 0x21, 0x0c,
- 0x7a, 0xc0, 0x80, 0x1e, 0xd4, 0xf9, 0xf1, 0xcc, 0xb6, 0x8f, 0xe5, 0xf1, 0x3f, 0x6e, 0x45, 0x4f,
- 0xfe, 0x61, 0xf1, 0xa2, 0x71, 0xe3, 0xc6, 0xc1, 0x76, 0xc1, 0x98, 0x80, 0x5f, 0x41, 0xfb, 0x4c,
- 0x98, 0x30, 0x61, 0xe2, 0xcb, 0x06, 0xae, 0x8b, 0xbf, 0x42, 0x01, 0xc1, 0xc2, 0xfc, 0x45, 0x02,
- 0x8d, 0x46, 0x62, 0xff, 0xf6, 0xb7, 0x0f, 0xfb, 0xf6, 0x85, 0x4c, 0xd8, 0x18, 0x12, 0x12, 0x7f,
- 0xf9, 0x72, 0xc5, 0xd3, 0xca, 0xe8, 0xe8, 0xf3, 0xde, 0x01, 0x1f, 0xb4, 0x7d, 0xfb, 0xa2, 0x84,
- 0x98, 0x61, 0x71, 0x71, 0x89, 0xcf, 0xa2, 0xb8, 0xa5, 0x4b, 0x97, 0xaa, 0x54, 0x6a, 0x41, 0x41,
- 0xc4, 0xc5, 0xc5, 0x79, 0x57, 0xd1, 0xe0, 0x1e, 0xf3, 0x72, 0x6e, 0x71, 0xf6, 0x72, 0x62, 0x88,
- 0xa3, 0xe9, 0x83, 0xd6, 0xa5, 0x34, 0xc9, 0xd5, 0xba, 0x8a, 0x68, 0x22, 0x89, 0x39, 0x99, 0x75,
- 0x56, 0x25, 0x5c, 0x89, 0xfe, 0xe0, 0x83, 0xff, 0x16, 0x0e, 0x06, 0x57, 0xd9, 0xba, 0x6d, 0x1b,
- 0x40, 0x79, 0xfb, 0xf6, 0x6d, 0x70, 0x57, 0xf1, 0x24, 0x1b, 0x36, 0x6c, 0x04, 0x3c, 0x84, 0x79,
- 0x61, 0xb6, 0x58, 0xb7, 0x6c, 0xd9, 0x22, 0xf1, 0xec, 0x53, 0xa6, 0x4c, 0xa9, 0xaa, 0xa6, 0x13,
- 0xc7, 0xe1, 0x74, 0x49, 0xaa, 0xaa, 0x30, 0x3a, 0xf3, 0xe6, 0xcd, 0x67, 0x79, 0x2b, 0xe9, 0x74,
- 0xb9, 0xbc, 0x1f, 0x13, 0x03, 0xa3, 0xfa, 0xf8, 0xf1, 0x63, 0x45, 0x4b, 0xcb, 0xf7, 0xdf, 0x7f,
- 0x2f, 0x31, 0xce, 0x63, 0xc6, 0x8e, 0x2d, 0x29, 0x2d, 0x15, 0xa0, 0xde, 0xe1, 0x11, 0x92, 0x72,
- 0x3a, 0x5d, 0xf8, 0x21, 0x91, 0x24, 0x88, 0xf1, 0xde, 0x17, 0xd9, 0x5e, 0x8f, 0x58, 0x96, 0x10,
- 0xce, 0x02, 0x59, 0xc5, 0x4c, 0x81, 0xa9, 0xef, 0xdb, 0xb7, 0x1f, 0x8c, 0x36, 0xfa, 0x04, 0x77,
- 0xf7, 0x01, 0xdf, 0xc0, 0xc6, 0x3d, 0x83, 0x03, 0x60, 0x8c, 0xb8, 0x0c, 0xad, 0x4e, 0x47, 0xdd,
- 0x16, 0x88, 0x2b, 0x75, 0x2b, 0x00, 0x2d, 0xe3, 0x76, 0x93, 0xdc, 0xdc, 0x9c, 0xa1, 0x43, 0x87,
- 0xfe, 0xf9, 0x44, 0x98, 0xf8, 0x43, 0x5f, 0x7d, 0xf5, 0xe5, 0xa3, 0x92, 0x3c, 0xce, 0x59, 0x4b,
- 0xcc, 0x59, 0xac, 0xee, 0x24, 0x51, 0x86, 0x31, 0x8a, 0xf9, 0x34, 0x4e, 0x4b, 0x73, 0xe8, 0x7e,
- 0x7c, 0x81, 0xc1, 0x07, 0x86, 0xd2, 0x3e, 0xe7, 0x8f, 0x7f, 0xb7, 0x70, 0xe1, 0x42, 0xc0, 0x72,
- 0xcc, 0x98, 0x31, 0xcb, 0x97, 0x2f, 0x8f, 0x8e, 0x8e, 0x86, 0x71, 0xb8, 0xe3, 0xd1, 0x52, 0x53,
- 0x53, 0xa1, 0x5b, 0xc1, 0x1f, 0x70, 0x23, 0xdd, 0x0e, 0x5a, 0xf1, 0xb9, 0x5a, 0x03, 0x07, 0x0e,
- 0x9a, 0x39, 0x73, 0xe6, 0xae, 0x5d, 0xbb, 0xd2, 0xd2, 0xd2, 0x2a, 0x2b, 0xab, 0x80, 0x01, 0x9f,
- 0xf7, 0x85, 0x49, 0xb4, 0x78, 0x09, 0xda, 0x52, 0x5c, 0x8f, 0x44, 0x8f, 0xe0, 0x96, 0xa7, 0x4e,
- 0x9d, 0x5a, 0x56, 0x5e, 0xce, 0x53, 0x02, 0xb7, 0xd1, 0x68, 0x0a, 0x0d, 0x0d, 0xf3, 0x3e, 0x43,
- 0x40, 0xc0, 0xa4, 0xea, 0xca, 0xbb, 0xac, 0xbd, 0x88, 0x17, 0xa7, 0xa1, 0x4c, 0xeb, 0x12, 0xa6,
- 0x65, 0x09, 0x69, 0xdf, 0x8c, 0xff, 0xb2, 0xd6, 0x02, 0x93, 0xbe, 0x66, 0xe3, 0xc6, 0xb5, 0xe2,
- 0x28, 0xc0, 0xae, 0xa6, 0xa5, 0xa5, 0x03, 0x18, 0x87, 0x0e, 0x1d, 0x12, 0x1d, 0x25, 0xfe, 0x0a,
- 0x17, 0x29, 0x84, 0x9e, 0xf0, 0xaa, 0xaf, 0x6f, 0x98, 0xde, 0x99, 0x7b, 0xe0, 0x00, 0xf0, 0x67,
- 0xb0, 0x68, 0x8a, 0x67, 0xb3, 0x45, 0xb2, 0x87, 0x1b, 0x66, 0xe2, 0x91, 0x97, 0x71, 0x80, 0x87,
- 0xc5, 0x25, 0x9e, 0x13, 0x41, 0x68, 0x70, 0xc1, 0x0e, 0x87, 0x33, 0x26, 0x26, 0x46, 0x32, 0x67,
- 0xa9, 0xb2, 0x3e, 0x73, 0x06, 0x60, 0xf3, 0xdc, 0xa1, 0x45, 0x70, 0xe5, 0x22, 0xa7, 0xe5, 0x3a,
- 0xdb, 0x58, 0xcf, 0x9c, 0xc1, 0xab, 0x42, 0x82, 0x8e, 0x67, 0x18, 0xe2, 0xae, 0x84, 0x35, 0x84,
- 0x8b, 0xc9, 0xe1, 0x09, 0x0c, 0xdf, 0xab, 0x1c, 0x0f, 0x5a, 0xd6, 0x66, 0xb3, 0x5e, 0xbd, 0x7a,
- 0x15, 0x76, 0xac, 0xbb, 0xe0, 0x2a, 0x34, 0x78, 0xa2, 0xa0, 0xa0, 0xc0, 0xca, 0xa7, 0xf7, 0x59,
- 0x67, 0x2d, 0x6b, 0x4e, 0x27, 0xda, 0x5f, 0x31, 0x2e, 0x8c, 0xe2, 0x3b, 0x1a, 0x2a, 0xaf, 0x1f,
- 0x49, 0xeb, 0x3f, 0x79, 0x4b, 0x6b, 0xaf, 0xe8, 0x75, 0xe1, 0xe4, 0xa2, 0x4d, 0x21, 0x1b, 0x0f,
- 0x1c, 0x38, 0x50, 0x58, 0x58, 0x68, 0x30, 0x18, 0x6c, 0x36, 0x9b, 0x46, 0xa3, 0x69, 0x6b, 0x6b,
- 0x53, 0xa9, 0x54, 0xf0, 0x6b, 0x2e, 0x97, 0x0b, 0xef, 0x13, 0x13, 0x13, 0xc1, 0xe5, 0x60, 0xb2,
- 0xba, 0x97, 0x1e, 0x08, 0xdb, 0x0a, 0x51, 0x79, 0x3b, 0x7c, 0xf8, 0x82, 0x85, 0xb4, 0x9c, 0x20,
- 0x2f, 0x3f, 0xbf, 0xb4, 0xb4, 0xd4, 0x27, 0x89, 0x7d, 0x4d, 0xc3, 0x85, 0x81, 0x24, 0x54, 0x54,
- 0x54, 0x60, 0xc4, 0x04, 0x67, 0x0d, 0xba, 0x0b, 0x19, 0xe2, 0x7d, 0xe4, 0xba, 0x75, 0x6b, 0x74,
- 0xea, 0x27, 0x94, 0x2f, 0x69, 0x8e, 0x30, 0xed, 0xeb, 0x28, 0x62, 0x5b, 0x57, 0x31, 0xea, 0xdd,
- 0x2c, 0xcd, 0x73, 0x95, 0x3f, 0x2e, 0xc9, 0x1b, 0x33, 0x66, 0xb4, 0x70, 0x24, 0x86, 0x03, 0xee,
- 0x5b, 0xa3, 0x01, 0x79, 0x73, 0xaf, 0x58, 0xb1, 0x42, 0x4c, 0x0a, 0x00, 0x48, 0x67, 0xce, 0x9c,
- 0x15, 0x41, 0x72, 0xaf, 0xa8, 0x48, 0x22, 0xab, 0x81, 0xed, 0xe3, 0xc7, 0x4f, 0x08, 0xc1, 0x7f,
- 0xb9, 0x42, 0x21, 0x29, 0xe6, 0x87, 0xec, 0x02, 0x4b, 0x17, 0x40, 0x75, 0xea, 0xf4, 0x69, 0xef,
- 0x50, 0x06, 0x28, 0x07, 0x88, 0x0d, 0x0c, 0x88, 0xe7, 0x87, 0xf8, 0xf5, 0xf9, 0xf3, 0xbf, 0x57,
- 0x2a, 0x55, 0x9d, 0xd6, 0x12, 0x8a, 0x88, 0xed, 0x78, 0x85, 0x58, 0x40, 0x0a, 0xaa, 0x0d, 0x96,
- 0xff, 0x95, 0xe6, 0xea, 0x14, 0x7a, 0xa5, 0x39, 0xac, 0xae, 0xd7, 0xbd, 0x00, 0x96, 0xe8, 0x81,
- 0x97, 0x37, 0x4b, 0x21, 0xab, 0x68, 0x51, 0x44, 0xee, 0x8b, 0xec, 0x7a, 0x60, 0xe4, 0x8d, 0x1a,
- 0xfa, 0xfc, 0xbb, 0xef, 0xe6, 0x36, 0xd4, 0x3d, 0xe6, 0x1c, 0x15, 0xac, 0xf9, 0x26, 0xd1, 0x1d,
- 0x25, 0xca, 0x8d, 0xa0, 0x6d, 0xae, 0xc6, 0x2f, 0x98, 0xfa, 0x11, 0x3c, 0x68, 0xf9, 0x8a, 0xd9,
- 0x3a, 0xbf, 0x7c, 0x59, 0x74, 0x65, 0x65, 0x25, 0xb0, 0xaa, 0x54, 0x2a, 0x01, 0xce, 0xad, 0x5b,
- 0xb7, 0xae, 0x5e, 0xbd, 0x1a, 0xaa, 0x21, 0x36, 0x36, 0xb6, 0xa9, 0xa9, 0x89, 0x10, 0x82, 0xcf,
- 0xa3, 0xa2, 0xa2, 0xe0, 0x47, 0xba, 0xb7, 0x72, 0x06, 0x46, 0x1b, 0xb4, 0xad, 0x77, 0xef, 0xde,
- 0xf0, 0x77, 0x50, 0x19, 0x40, 0x42, 0x71, 0x49, 0x69, 0x41, 0x41, 0xe1, 0x1b, 0x55, 0x71, 0xa3,
- 0xf3, 0x97, 0x2c, 0x59, 0x5c, 0x53, 0x5b, 0xed, 0x76, 0xb3, 0x62, 0xd4, 0x05, 0xb0, 0x87, 0xb3,
- 0x93, 0x1c, 0x09, 0x37, 0x71, 0xe2, 0xf8, 0x41, 0xe2, 0x00, 0x59, 0x4a, 0x25, 0xea, 0x48, 0xa6,
- 0x7d, 0x0d, 0x65, 0x05, 0x6d, 0xeb, 0x69, 0xdd, 0x0b, 0x26, 0xb5, 0xbd, 0xee, 0x72, 0x7c, 0x0c,
- 0x0c, 0xbe, 0x70, 0xf0, 0xdb, 0xef, 0xbc, 0xb3, 0x26, 0x38, 0x18, 0x78, 0xd0, 0xe9, 0x0d, 0x53,
- 0xa7, 0xbe, 0xa2, 0x76, 0xb0, 0x8a, 0xf4, 0xd1, 0xb4, 0xfc, 0x20, 0x12, 0x96, 0x4d, 0x4c, 0x4c,
- 0x92, 0x58, 0x7b, 0x61, 0x55, 0x02, 0xcb, 0xcf, 0x9c, 0x1b, 0xc9, 0xc9, 0x92, 0x6b, 0xf8, 0xa8,
- 0x7f, 0x7f, 0x81, 0x70, 0xe2, 0x00, 0xb8, 0x66, 0xef, 0xa8, 0x2f, 0x48, 0xec, 0x9e, 0x3d, 0x7b,
- 0x24, 0xd4, 0xf7, 0x7f, 0x06, 0x0c, 0xb8, 0x93, 0x99, 0xf9, 0xaa, 0x5c, 0xf0, 0x59, 0xa7, 0xda,
- 0x2d, 0x21, 0x78, 0x62, 0xb1, 0x58, 0x4b, 0x4b, 0x1f, 0x5d, 0xbc, 0x18, 0xb7, 0x7e, 0xfd, 0x86,
- 0xf2, 0x27, 0x4f, 0x7c, 0xd6, 0xbd, 0xe0, 0xc3, 0xcc, 0x4c, 0xdf, 0x31, 0x6a, 0x9f, 0x0d, 0xc2,
- 0xbc, 0xa9, 0xa9, 0x99, 0x32, 0x0d, 0xca, 0x61, 0x98, 0xec, 0xec, 0xec, 0x45, 0x8b, 0x16, 0xf9,
- 0x24, 0x6c, 0x5d, 0x69, 0x3d, 0x7b, 0xf6, 0x9c, 0x30, 0x61, 0x7c, 0x60, 0xe0, 0x74, 0x00, 0xe9,
- 0xf7, 0xec, 0x33, 0x88, 0xd0, 0x8a, 0x15, 0x3f, 0x68, 0xd5, 0xd5, 0xac, 0xe3, 0x11, 0x31, 0x5d,
- 0x23, 0x9a, 0x43, 0x4c, 0xdb, 0x5a, 0x46, 0x3e, 0xcb, 0x45, 0xab, 0x95, 0x86, 0xf3, 0x95, 0xf6,
- 0xc3, 0x48, 0xcb, 0x1c, 0xb7, 0x25, 0x99, 0x71, 0xd9, 0xd5, 0x6a, 0x35, 0xdc, 0x1f, 0x5c, 0x33,
- 0x6c, 0x7e, 0x41, 0x41, 0xc1, 0xdd, 0xbb, 0x77, 0x4f, 0x9d, 0x3a, 0x05, 0x05, 0xda, 0xdc, 0xdc,
- 0xcc, 0x30, 0x50, 0xc4, 0x77, 0x40, 0xcf, 0xde, 0xf9, 0x73, 0x7b, 0x81, 0x4a, 0x1a, 0x64, 0x17,
- 0x68, 0x1b, 0x9c, 0x2f, 0x48, 0x6c, 0x48, 0xc8, 0xa6, 0x4b, 0xf1, 0xf1, 0x15, 0x4f, 0x9f, 0x26,
- 0x25, 0x25, 0x75, 0xbd, 0xf2, 0x0d, 0x47, 0x82, 0xcc, 0x28, 0x14, 0x72, 0x1e, 0xae, 0x2e, 0x51,
- 0xc3, 0x26, 0x5d, 0x4d, 0x92, 0x90, 0xc0, 0xb7, 0x68, 0x55, 0x73, 0xff, 0x5b, 0xa9, 0x57, 0x38,
- 0x67, 0x39, 0x2c, 0x2a, 0xa3, 0xda, 0x4e, 0xad, 0x6b, 0xeb, 0x0a, 0xa2, 0x0c, 0x27, 0xfa, 0x33,
- 0xc4, 0x56, 0xa0, 0x53, 0x57, 0x07, 0x07, 0xaf, 0x12, 0x0f, 0xc6, 0xb8, 0x40, 0xfb, 0x00, 0x0c,
- 0x8f, 0x1f, 0x97, 0x8d, 0x1a, 0x35, 0x4a, 0xfc, 0x1c, 0xfc, 0x59, 0x26, 0xcb, 0x16, 0x10, 0x6b,
- 0xb1, 0xda, 0x22, 0x22, 0xa4, 0xdb, 0x07, 0x41, 0x08, 0x34, 0x34, 0xd4, 0x03, 0xcc, 0x0c, 0x61,
- 0xbd, 0xb7, 0xc3, 0x0a, 0x0c, 0x0c, 0xe4, 0x8d, 0x95, 0x5b, 0xad, 0xd6, 0xe0, 0xae, 0x25, 0x03,
- 0x07, 0x00, 0x27, 0x24, 0x24, 0x48, 0x5c, 0x36, 0x3e, 0x04, 0x4d, 0x02, 0xe9, 0x15, 0x17, 0x67,
- 0x89, 0xc5, 0x87, 0x02, 0x43, 0x78, 0xf8, 0xb0, 0xf8, 0xdc, 0xb9, 0x68, 0xcc, 0xaf, 0xcf, 0x3f,
- 0xff, 0x1c, 0x7a, 0x04, 0x78, 0x68, 0x69, 0x6d, 0xeb, 0x78, 0x45, 0x65, 0x5f, 0x56, 0x6e, 0x77,
- 0x3c, 0x33, 0x99, 0xcd, 0x9b, 0x37, 0x6f, 0x96, 0xc4, 0x1f, 0x5e, 0xd3, 0x20, 0xc9, 0xd7, 0xae,
- 0x5d, 0x9b, 0x98, 0x94, 0x74, 0xe1, 0xc2, 0xc5, 0xb0, 0xb0, 0x2d, 0x7f, 0x78, 0x5f, 0x65, 0x38,
- 0x1a, 0x10, 0xb9, 0x73, 0xe7, 0xce, 0x94, 0x97, 0x3f, 0x6a, 0x6e, 0x6e, 0xbc, 0x7e, 0xe3, 0x3a,
- 0x5c, 0xf6, 0xef, 0x81, 0x16, 0xf7, 0x1b, 0x1e, 0x1e, 0x62, 0xd4, 0xd7, 0xb0, 0xf6, 0x87, 0xb4,
- 0xca, 0x4e, 0xb3, 0x9f, 0x96, 0xd8, 0x35, 0xcf, 0x70, 0x09, 0x25, 0x76, 0x8d, 0x63, 0x39, 0x75,
- 0xf8, 0x33, 0xa6, 0xf2, 0x59, 0x07, 0xb9, 0x79, 0xf3, 0x66, 0x44, 0x44, 0xc4, 0x93, 0x27, 0x4f,
- 0x40, 0xc3, 0xa0, 0x70, 0xa1, 0x10, 0x81, 0x5b, 0xb0, 0x85, 0xcb, 0x97, 0x2f, 0x3b, 0x9d, 0x4e,
- 0x7c, 0x0e, 0x06, 0x09, 0x51, 0xdc, 0x5d, 0xc4, 0x40, 0x28, 0x27, 0x00, 0x30, 0xa0, 0xac, 0x31,
- 0x8e, 0x3f, 0x45, 0x6c, 0x07, 0x42, 0x20, 0x58, 0xb6, 0x6d, 0xdb, 0xd6, 0xf5, 0xae, 0x00, 0x1f,
- 0x80, 0x2c, 0xa2, 0x64, 0xc0, 0x23, 0xf0, 0xe2, 0x70, 0xd8, 0x42, 0x43, 0x43, 0xbd, 0x0f, 0xfe,
- 0xe2, 0x8b, 0xf1, 0x15, 0x65, 0xf9, 0xac, 0xed, 0x21, 0x31, 0xc4, 0x00, 0xa8, 0x14, 0xb1, 0x6d,
- 0xc1, 0x44, 0xfd, 0x33, 0x31, 0x5e, 0x66, 0xed, 0x8f, 0x6a, 0xab, 0x8b, 0x3f, 0xf9, 0xe4, 0x63,
- 0xf1, 0x60, 0x98, 0x68, 0x28, 0x0e, 0x20, 0x36, 0x25, 0xe5, 0xa6, 0xa7, 0xdf, 0x07, 0x2f, 0x85,
- 0x29, 0x13, 0x10, 0xab, 0x52, 0x6b, 0x02, 0x3b, 0xc7, 0xcf, 0x31, 0x4d, 0x16, 0x2e, 0x5c, 0xe0,
- 0x72, 0xd9, 0x59, 0xd6, 0x01, 0x9f, 0xf5, 0xdb, 0xa9, 0x53, 0x21, 0x2f, 0x1b, 0x0d, 0x75, 0x6d,
- 0xde, 0x7c, 0x23, 0x39, 0xc5, 0x05, 0x28, 0xb3, 0x5c, 0x61, 0xe1, 0x5d, 0x3f, 0x3f, 0x69, 0x3c,
- 0xe4, 0x83, 0x3e, 0x7d, 0x82, 0x82, 0x82, 0x24, 0x1f, 0x62, 0x8e, 0x40, 0x88, 0x89, 0xdc, 0x55,
- 0xac, 0xeb, 0x16, 0x37, 0xdd, 0x9a, 0x33, 0x67, 0x6e, 0xaf, 0x5e, 0xbd, 0xc4, 0x19, 0x1a, 0x1c,
- 0xfc, 0xa3, 0x55, 0x28, 0x7d, 0x79, 0x26, 0xad, 0xa4, 0x05, 0x87, 0x79, 0xd3, 0x47, 0x82, 0x62,
- 0x80, 0x60, 0x52, 0x40, 0x03, 0x5e, 0x93, 0x04, 0x7c, 0x7d, 0x03, 0x66, 0xd6, 0xad, 0x0b, 0xae,
- 0xaa, 0x7c, 0xe4, 0x72, 0xe8, 0x39, 0xd6, 0xc2, 0x71, 0x76, 0x86, 0xb1, 0x03, 0x54, 0xde, 0x4e,
- 0x50, 0x6c, 0xef, 0xbf, 0xff, 0x9f, 0x91, 0x7b, 0xb6, 0x5b, 0x8d, 0x35, 0x9c, 0xad, 0x88, 0xa6,
- 0x26, 0x35, 0x91, 0x4c, 0xdb, 0x0a, 0x17, 0x05, 0xed, 0x78, 0x46, 0x3e, 0x83, 0x33, 0x9c, 0x7e,
- 0xee, 0x56, 0x83, 0x4e, 0x1f, 0x3f, 0x7e, 0xfc, 0xc2, 0x85, 0x0b, 0x0a, 0x85, 0x02, 0x96, 0x1f,
- 0x76, 0x15, 0xf3, 0x3a, 0x25, 0x25, 0x25, 0x37, 0x37, 0x17, 0x4e, 0x0a, 0xfc, 0x56, 0x2e, 0x97,
- 0x03, 0xcf, 0x98, 0xfe, 0xdd, 0xb5, 0xd0, 0x46, 0x7c, 0xda, 0xe6, 0x90, 0x21, 0x7e, 0xe8, 0xf3,
- 0x7d, 0xfb, 0xa2, 0xe0, 0xf8, 0x6a, 0xeb, 0xea, 0x02, 0x02, 0x02, 0xba, 0xde, 0x1b, 0x02, 0xdb,
- 0x34, 0x99, 0xe1, 0x67, 0x89, 0x88, 0x58, 0xb3, 0xd9, 0x08, 0x6b, 0xe3, 0x7d, 0xf0, 0xa2, 0x85,
- 0xf3, 0xcc, 0x86, 0x1a, 0xd6, 0x9a, 0x47, 0xf4, 0xa7, 0x68, 0xb6, 0xab, 0x75, 0x35, 0xd3, 0x1e,
- 0x02, 0x4a, 0x40, 0x4b, 0x62, 0x1c, 0xb5, 0x09, 0x97, 0x63, 0x3d, 0xcd, 0xf2, 0xec, 0xd9, 0xb3,
- 0x85, 0x60, 0xd1, 0x89, 0x13, 0x27, 0x3c, 0xd9, 0x26, 0x18, 0x42, 0x63, 0x63, 0x93, 0x80, 0x58,
- 0x78, 0x4c, 0x49, 0xb7, 0xe3, 0x76, 0xf6, 0xef, 0x8f, 0xc2, 0xa0, 0x70, 0xc4, 0xa0, 0x56, 0xb7,
- 0x63, 0x02, 0x3e, 0x79, 0x52, 0x51, 0x0e, 0x27, 0x5d, 0xf1, 0x14, 0xef, 0x1b, 0x1a, 0x1a, 0x60,
- 0x5a, 0x61, 0x99, 0x01, 0xda, 0x73, 0xe7, 0xce, 0x79, 0x97, 0xf1, 0xc0, 0x65, 0x48, 0x80, 0x81,
- 0x1b, 0x8c, 0x8f, 0x8f, 0x17, 0xc5, 0x94, 0x67, 0x35, 0xb8, 0xb0, 0xb1, 0x21, 0x8c, 0x89, 0x67,
- 0x96, 0x01, 0x5f, 0xc7, 0x14, 0xe3, 0x5e, 0x3e, 0x68, 0x5e, 0x4c, 0x69, 0xe1, 0xeb, 0x36, 0xbb,
- 0x1d, 0x9d, 0xec, 0xb3, 0x3e, 0xf3, 0xaf, 0x6b, 0x30, 0x29, 0x27, 0x8e, 0x1f, 0x36, 0xea, 0x9a,
- 0x38, 0x57, 0x1b, 0xe7, 0x6a, 0xe5, 0x18, 0x25, 0x7a, 0xc6, 0xcd, 0x39, 0x65, 0xb2, 0x2c, 0x58,
- 0xaa, 0xdf, 0xfb, 0x96, 0x50, 0x78, 0x00, 0x0a, 0xe7, 0xb4, 0x35, 0xb2, 0x14, 0xb4, 0xf1, 0x44,
- 0xbd, 0x9b, 0xd6, 0x2c, 0xc9, 0x83, 0x48, 0xcb, 0x77, 0x6e, 0x63, 0xec, 0x73, 0xb7, 0xce, 0x68,
- 0x34, 0x1c, 0x3e, 0x7c, 0x18, 0x10, 0x05, 0x62, 0xc7, 0x8d, 0x1b, 0x37, 0x6b, 0xd6, 0xac, 0x79,
- 0xf3, 0xe6, 0x01, 0xa8, 0x30, 0xad, 0xe1, 0xe1, 0xe1, 0xd0, 0x62, 0x78, 0x7f, 0xf6, 0xec, 0x59,
- 0xf8, 0x85, 0xee, 0xa2, 0xb2, 0xfc, 0x13, 0xa1, 0xff, 0x0d, 0x4a, 0x64, 0xe4, 0xc8, 0x91, 0x8b,
- 0x97, 0x2c, 0x39, 0x76, 0xfc, 0x38, 0x24, 0xc9, 0xd3, 0xca, 0xaa, 0x37, 0x2d, 0x07, 0x02, 0xe5,
- 0x9b, 0x35, 0x6b, 0xa6, 0x56, 0xab, 0xe1, 0x41, 0xcb, 0x80, 0x1e, 0x34, 0xcb, 0x9b, 0xbd, 0x1d,
- 0x1f, 0xc5, 0x52, 0xd4, 0x2e, 0xce, 0x55, 0xcf, 0xe7, 0x0e, 0x8e, 0x90, 0xf6, 0x10, 0xa6, 0x6d,
- 0x1d, 0x51, 0x6d, 0x67, 0x69, 0x66, 0xb6, 0xd0, 0x69, 0x93, 0x07, 0x06, 0x76, 0x8a, 0x43, 0x26,
- 0x24, 0x26, 0x0a, 0x11, 0xf5, 0x8d, 0x21, 0x21, 0x9e, 0xfe, 0x6b, 0xc1, 0x82, 0x05, 0x26, 0x93,
- 0x59, 0x88, 0x23, 0xdd, 0x4a, 0x4b, 0x93, 0xfc, 0x0a, 0xc4, 0x75, 0x6e, 0x4e, 0x26, 0x06, 0x85,
- 0x73, 0x35, 0xb3, 0xf6, 0xca, 0xd2, 0x92, 0x22, 0x59, 0x76, 0x4e, 0x66, 0x96, 0x0c, 0x8a, 0xfb,
- 0x5e, 0xd1, 0xfd, 0xf2, 0x27, 0x15, 0xcd, 0x72, 0x85, 0xde, 0x60, 0x04, 0x68, 0x37, 0x6c, 0xdc,
- 0xe8, 0xcd, 0x5b, 0xbc, 0x07, 0x8e, 0x4f, 0x3a, 0xdb, 0x5e, 0x45, 0xab, 0x24, 0x8b, 0xbc, 0x3a,
- 0xe8, 0x76, 0xf4, 0x9e, 0xb1, 0xe2, 0xf1, 0xe3, 0xc7, 0xd7, 0xd4, 0xd4, 0xbe, 0x12, 0x68, 0x1e,
- 0x06, 0x16, 0x13, 0xa7, 0x7b, 0xd7, 0xc9, 0xbe, 0xbe, 0x61, 0xf6, 0x0d, 0x1e, 0x3c, 0x28, 0x47,
- 0x96, 0xea, 0x66, 0x14, 0x9c, 0xe3, 0x29, 0x6b, 0x2f, 0x65, 0xed, 0xe5, 0x9c, 0xb3, 0x9e, 0x65,
- 0xd4, 0x84, 0xb1, 0xc4, 0xc5, 0x5d, 0x90, 0xf0, 0x61, 0x8c, 0x23, 0xa6, 0x1b, 0xbe, 0x25, 0xf6,
- 0x36, 0x40, 0x7b, 0xf6, 0xcc, 0x09, 0x9b, 0x99, 0xaf, 0x38, 0x32, 0x5c, 0x82, 0x37, 0x04, 0x8b,
- 0x63, 0x14, 0xf3, 0x39, 0xed, 0xde, 0x67, 0xa4, 0xd6, 0xe5, 0xb4, 0x9f, 0x3e, 0x7d, 0xfa, 0xe4,
- 0xc9, 0x93, 0xb0, 0xae, 0x4b, 0x97, 0x2e, 0xd5, 0xe9, 0x74, 0x60, 0xb0, 0xe0, 0xae, 0xc0, 0x30,
- 0x90, 0x6c, 0x36, 0x9b, 0xdb, 0xdb, 0xdb, 0x0f, 0x1e, 0x3c, 0x88, 0x79, 0xd1, 0x5d, 0x4b, 0xc3,
- 0x84, 0x67, 0x15, 0x09, 0x7b, 0xbc, 0xaf, 0x5e, 0x13, 0x7c, 0x2e, 0xfa, 0x3c, 0xbc, 0xed, 0xb5,
- 0xeb, 0xd7, 0xff, 0x40, 0xe7, 0x00, 0xe4, 0x61, 0x61, 0x61, 0x3a, 0x1d, 0x54, 0x2d, 0x0b, 0x92,
- 0x08, 0x1e, 0xee, 0x7d, 0xcc, 0x47, 0xfd, 0xfa, 0xa5, 0xa6, 0x5c, 0x61, 0xd1, 0x75, 0xc6, 0x6b,
- 0x94, 0x1a, 0x01, 0xb1, 0xed, 0x9b, 0x88, 0x26, 0x8a, 0x35, 0x26, 0x71, 0xf6, 0x32, 0x79, 0x53,
- 0xc5, 0xbb, 0xef, 0xbe, 0xea, 0x40, 0x18, 0x55, 0x50, 0x41, 0x8c, 0xb2, 0xa2, 0xa5, 0x75, 0xee,
- 0xb7, 0xdf, 0x8a, 0x9f, 0xe3, 0x82, 0xd7, 0xae, 0x5d, 0x27, 0xd6, 0xf8, 0x85, 0x87, 0x6f, 0x95,
- 0xfc, 0xca, 0xb0, 0x61, 0xc3, 0x34, 0x9a, 0x16, 0x8e, 0x2f, 0x92, 0xe1, 0xac, 0x45, 0x9a, 0xe6,
- 0xcc, 0x84, 0x84, 0xc4, 0xcb, 0x57, 0xae, 0x40, 0xac, 0xa5, 0xa5, 0xa5, 0x63, 0x4a, 0x56, 0xd7,
- 0xd4, 0xaa, 0x35, 0x9a, 0x9a, 0xda, 0x3a, 0x9f, 0x65, 0x3c, 0x92, 0x86, 0x11, 0xcc, 0x92, 0xc9,
- 0x84, 0xdd, 0x30, 0x04, 0x3e, 0xe0, 0xb5, 0x2c, 0xf1, 0x59, 0x41, 0x61, 0xa1, 0xa8, 0xdc, 0x31,
- 0xe8, 0x34, 0xc5, 0xc0, 0xef, 0x01, 0x2b, 0x0a, 0x34, 0x81, 0xc1, 0x32, 0x0c, 0x39, 0x78, 0xf0,
- 0x50, 0xd7, 0xe3, 0x51, 0x38, 0x12, 0xe0, 0xf9, 0x03, 0x4b, 0x96, 0x84, 0x06, 0x34, 0xce, 0x98,
- 0x31, 0xbd, 0xa4, 0x38, 0x97, 0x38, 0xea, 0x38, 0xe0, 0xcd, 0x92, 0xc5, 0x5a, 0xb3, 0x60, 0x19,
- 0xd0, 0xff, 0x1c, 0xa3, 0x52, 0x29, 0x29, 0xc6, 0xc4, 0x83, 0xd1, 0xdb, 0x9f, 0x7d, 0x36, 0x72,
- 0xe6, 0xcc, 0xa0, 0xd5, 0xab, 0x56, 0xac, 0x58, 0xb1, 0x6c, 0xda, 0xb4, 0xa9, 0xe2, 0x1c, 0xec,
- 0xd7, 0xaf, 0x5f, 0xc2, 0x95, 0x0b, 0x4e, 0x5b, 0x13, 0x6b, 0x2b, 0x20, 0x86, 0x58, 0x5a, 0x5c,
- 0xd7, 0xba, 0x82, 0x55, 0x85, 0x76, 0xd8, 0x73, 0x9e, 0x77, 0xd8, 0xee, 0xde, 0x2d, 0x04, 0x13,
- 0xc8, 0xcc, 0xcc, 0x8c, 0x8a, 0x8a, 0x82, 0xaf, 0xc1, 0x1b, 0x38, 0x44, 0xb0, 0x4a, 0xe0, 0x96,
- 0x10, 0x02, 0x63, 0x0b, 0x6d, 0xfb, 0xde, 0x7b, 0xef, 0x75, 0x17, 0x8f, 0x15, 0x9e, 0xa3, 0xf1,
- 0x61, 0xdf, 0xbe, 0x5f, 0x06, 0x04, 0x40, 0x0e, 0x60, 0x58, 0xab, 0x6b, 0x6a, 0x7c, 0xf2, 0x4f,
- 0xdc, 0xfe, 0xe4, 0xc9, 0x93, 0x83, 0x83, 0x83, 0x21, 0x2e, 0x3c, 0x65, 0xbb, 0x67, 0xeb, 0xdf,
- 0xbf, 0x7f, 0x72, 0x72, 0x32, 0x1f, 0x3f, 0x77, 0x43, 0x2c, 0x78, 0x1f, 0x30, 0x72, 0xe4, 0xf0,
- 0x86, 0xba, 0x62, 0xd6, 0x56, 0x4c, 0x97, 0xc3, 0xa8, 0xf7, 0x12, 0xc0, 0x55, 0xf5, 0x13, 0xd1,
- 0xfd, 0x4a, 0x2c, 0x19, 0x9c, 0xab, 0xe1, 0xe4, 0xc9, 0xa3, 0x9e, 0x07, 0x4f, 0x9f, 0x3e, 0xdd,
- 0xc2, 0xd7, 0x34, 0x96, 0x3e, 0x7a, 0xe4, 0x19, 0x50, 0xc5, 0x95, 0xd0, 0x52, 0x9c, 0x97, 0x91,
- 0x4f, 0x38, 0x23, 0xcf, 0x6f, 0x61, 0x7c, 0xe7, 0xce, 0x9d, 0xe3, 0xe6, 0x6c, 0x1c, 0xd3, 0xce,
- 0x3a, 0x2a, 0x59, 0x6b, 0xa1, 0x53, 0x9f, 0x9e, 0x27, 0x4b, 0xb8, 0x18, 0x17, 0x77, 0x25, 0x21,
- 0xe1, 0x66, 0x6a, 0x6a, 0x7e, 0x41, 0x21, 0xb8, 0x81, 0x46, 0xa3, 0xcd, 0xce, 0xc9, 0xe9, 0xca,
- 0x4a, 0x40, 0x78, 0xf0, 0xbc, 0xfc, 0xfc, 0x17, 0x0f, 0x83, 0xed, 0x8c, 0x58, 0x71, 0x19, 0x2c,
- 0x66, 0x04, 0xfc, 0x94, 0x70, 0x7c, 0xef, 0xde, 0xbd, 0x31, 0x5b, 0xc5, 0xa7, 0xc7, 0x7a, 0xee,
- 0xa0, 0xa5, 0x54, 0xa9, 0xbc, 0x69, 0xb3, 0xcf, 0x86, 0x41, 0x19, 0x3e, 0x7c, 0xf8, 0xb2, 0x65,
- 0xcb, 0xb6, 0x84, 0x87, 0xa3, 0x27, 0x47, 0x8f, 0x1e, 0xdd, 0x75, 0xa5, 0x26, 0x34, 0x20, 0x70,
- 0xe5, 0xca, 0xe5, 0xd5, 0x95, 0xc5, 0xac, 0xab, 0x91, 0x6e, 0xd2, 0x65, 0x4e, 0x26, 0xa6, 0x04,
- 0x62, 0xbe, 0xce, 0x5a, 0xb3, 0x81, 0x58, 0xc2, 0xa8, 0x33, 0x32, 0x6e, 0x09, 0x81, 0x68, 0xdc,
- 0xe0, 0x67, 0x23, 0x47, 0x1c, 0x3c, 0xb0, 0xf7, 0x49, 0x59, 0x91, 0xd3, 0xa6, 0xa2, 0xbe, 0x89,
- 0x35, 0xdb, 0x6c, 0xfa, 0x98, 0xf3, 0xe7, 0x44, 0xf9, 0xe9, 0xe7, 0x37, 0xe4, 0x76, 0xfa, 0x0d,
- 0x37, 0x4e, 0x65, 0x91, 0x11, 0xfd, 0x69, 0xa2, 0xdc, 0x4a, 0xda, 0xd7, 0x72, 0xfa, 0x93, 0xcf,
- 0x48, 0x9d, 0xc3, 0x6e, 0x02, 0x1f, 0x86, 0x69, 0x8d, 0x8e, 0x8e, 0xce, 0xcf, 0xcf, 0xbf, 0x76,
- 0xed, 0x1a, 0xde, 0x83, 0x6e, 0xc1, 0xde, 0x9a, 0x4c, 0xa6, 0xc4, 0xc4, 0xc4, 0x2f, 0xbf, 0xfc,
- 0x12, 0x17, 0xdf, 0x2d, 0x88, 0x15, 0x1f, 0xb8, 0x09, 0x61, 0x3b, 0x63, 0x46, 0xd0, 0x8e, 0x1d,
- 0x3b, 0x52, 0x6e, 0xde, 0x6c, 0x96, 0xcb, 0xc7, 0xfa, 0xe2, 0x9f, 0x03, 0x3e, 0xfe, 0x18, 0xd3,
- 0xc7, 0xe9, 0x62, 0xf0, 0x3a, 0x72, 0xe4, 0x17, 0x9f, 0xbd, 0x84, 0x59, 0x99, 0x94, 0x94, 0xc4,
- 0x47, 0x26, 0xdd, 0x23, 0x46, 0x8c, 0x90, 0xfc, 0x15, 0xb6, 0x71, 0xd6, 0xac, 0x20, 0x97, 0x5d,
- 0x8e, 0x69, 0x4e, 0x65, 0x97, 0x7a, 0x37, 0x5d, 0x9f, 0xa8, 0x8e, 0x24, 0x86, 0x8b, 0xa0, 0x49,
- 0x2e, 0x47, 0xcb, 0xa4, 0x49, 0x13, 0x3d, 0x8f, 0xff, 0xe5, 0x97, 0xa3, 0x42, 0x39, 0x4d, 0x46,
- 0xc6, 0x1d, 0x71, 0x0d, 0xd4, 0x5b, 0x7c, 0x7c, 0xe6, 0xcc, 0x99, 0x33, 0xee, 0x97, 0xd9, 0x2e,
- 0x09, 0x81, 0x41, 0xff, 0x1f, 0x3d, 0xfa, 0x8b, 0x1b, 0x24, 0x96, 0x81, 0x8d, 0x6d, 0x80, 0x9a,
- 0x63, 0x2d, 0x05, 0x86, 0xb6, 0x2c, 0x59, 0x66, 0x5a, 0xfa, 0xed, 0xdb, 0xb9, 0x79, 0x79, 0x25,
- 0xfc, 0x8e, 0x6a, 0x06, 0xa3, 0x31, 0x2e, 0xee, 0xd2, 0xeb, 0xeb, 0x6f, 0xc5, 0x76, 0xe5, 0x4a,
- 0x02, 0xcb, 0x71, 0x12, 0xc4, 0x3e, 0xf7, 0xd8, 0xeb, 0xf8, 0xf0, 0x91, 0x23, 0x62, 0x44, 0x6e,
- 0xd2, 0xa4, 0x49, 0xa0, 0x55, 0x9d, 0xb6, 0x81, 0x7d, 0x59, 0xe5, 0x12, 0x17, 0x17, 0xd7, 0x15,
- 0x83, 0x89, 0x29, 0x39, 0x77, 0xee, 0xb7, 0x19, 0x19, 0x19, 0xed, 0x4a, 0x15, 0x6e, 0xd0, 0x66,
- 0x31, 0x17, 0x16, 0x16, 0x4c, 0xf7, 0x55, 0x9e, 0xf1, 0x7b, 0x0d, 0x70, 0x8d, 0x88, 0xd8, 0xda,
- 0xdc, 0x54, 0xc5, 0x31, 0xad, 0xac, 0xbd, 0x84, 0xae, 0x95, 0x83, 0x6d, 0x34, 0xc4, 0xb0, 0xa6,
- 0x24, 0x28, 0x08, 0xce, 0x59, 0x67, 0xd0, 0x2b, 0x02, 0x03, 0xe9, 0x09, 0x71, 0xd9, 0x4b, 0x97,
- 0x2e, 0xca, 0xcf, 0xbb, 0xcd, 0x38, 0x5a, 0xc1, 0xd6, 0x38, 0x47, 0x25, 0xe7, 0xa8, 0x66, 0x5d,
- 0x4d, 0xf0, 0x50, 0x46, 0x83, 0x72, 0xdd, 0xba, 0x1f, 0xc5, 0x73, 0x0e, 0x1f, 0xfe, 0x69, 0x69,
- 0x71, 0x0e, 0xe7, 0xac, 0xe2, 0x19, 0xdd, 0x09, 0x8c, 0x1d, 0xab, 0xda, 0xda, 0x61, 0xbd, 0xf9,
- 0x9c, 0x53, 0x39, 0x1c, 0x96, 0xc2, 0xc2, 0xc2, 0x4b, 0x97, 0x2e, 0xc5, 0xc6, 0xc6, 0xe2, 0xdf,
- 0xec, 0x6c, 0x99, 0xc9, 0xa8, 0x73, 0x33, 0xfa, 0x87, 0x0f, 0x8b, 0x60, 0xe2, 0x60, 0xc7, 0xfe,
- 0xfd, 0x0d, 0x1f, 0xbb, 0xf0, 0x1a, 0xc4, 0x42, 0x76, 0xe1, 0x9a, 0x85, 0xfd, 0x34, 0xf6, 0xef,
- 0x3f, 0x20, 0xcb, 0xce, 0x7e, 0x52, 0x51, 0xd1, 0xa3, 0x47, 0x0f, 0xef, 0x4e, 0x18, 0x3d, 0x66,
- 0x8c, 0x8a, 0x2e, 0x05, 0xa5, 0x96, 0x03, 0x07, 0xfb, 0xec, 0xa8, 0x51, 0xa3, 0xfc, 0xcb, 0xca,
- 0xca, 0x61, 0xf7, 0x00, 0x09, 0xef, 0x9a, 0x2e, 0x4c, 0x8d, 0xdd, 0xbb, 0x23, 0xc0, 0x2d, 0x09,
- 0xe6, 0xa9, 0xee, 0x34, 0xa3, 0xda, 0xc5, 0xa8, 0xb6, 0x13, 0xed, 0x31, 0x62, 0xba, 0x09, 0x8a,
- 0x55, 0x5a, 0x9c, 0xd7, 0xbb, 0xf7, 0x2b, 0x11, 0x84, 0xaf, 0xdf, 0xbb, 0x77, 0x4f, 0x48, 0xf5,
- 0x42, 0x8a, 0x7a, 0x4a, 0x21, 0xa0, 0x37, 0x39, 0x25, 0x45, 0x50, 0x64, 0x05, 0x05, 0x85, 0x92,
- 0x5f, 0xc1, 0x74, 0x2e, 0x2e, 0x7e, 0x08, 0x59, 0xc1, 0x11, 0x13, 0x47, 0x34, 0x1c, 0xd3, 0xc2,
- 0x39, 0x1b, 0x88, 0xad, 0x46, 0xd9, 0x06, 0x2e, 0x50, 0xd7, 0xd2, 0xd2, 0xaa, 0xd1, 0x6a, 0x2d,
- 0x16, 0x2b, 0x68, 0x30, 0x0c, 0x75, 0x17, 0x1d, 0xee, 0x81, 0x03, 0x07, 0x5c, 0x0c, 0x23, 0x20,
- 0xb0, 0xd3, 0xf2, 0x81, 0x17, 0x50, 0x7c, 0xbe, 0x71, 0x63, 0x88, 0x90, 0x8c, 0x86, 0x13, 0x0f,
- 0x09, 0x09, 0x01, 0xf1, 0xf6, 0x7c, 0x66, 0x81, 0xb0, 0x7a, 0xd1, 0xe9, 0x72, 0x49, 0x52, 0x12,
- 0x3e, 0x1b, 0xe0, 0xba, 0x76, 0xdd, 0xba, 0x47, 0x8f, 0x1f, 0xcb, 0xe5, 0x0a, 0x88, 0xca, 0x96,
- 0x96, 0x16, 0xa7, 0xd5, 0xe8, 0x72, 0xd8, 0x22, 0x23, 0xf7, 0x76, 0x51, 0xaf, 0xe1, 0x4a, 0x7e,
- 0xfb, 0xed, 0xa4, 0x56, 0xdb, 0xce, 0x11, 0x1d, 0xe7, 0xa8, 0x61, 0x2d, 0x39, 0x2c, 0x94, 0xbe,
- 0xee, 0x34, 0xd1, 0x47, 0xc3, 0xd2, 0x72, 0xf6, 0x62, 0x37, 0x69, 0x3f, 0x7d, 0xea, 0x04, 0x3a,
- 0x0a, 0x73, 0x7f, 0xe7, 0xce, 0xed, 0x0a, 0x79, 0x25, 0x71, 0xc2, 0xe3, 0x97, 0x52, 0xf3, 0x6b,
- 0xce, 0xa0, 0x99, 0x1d, 0x50, 0x08, 0x67, 0x3d, 0x61, 0xf4, 0xd7, 0xae, 0x25, 0x8a, 0x3d, 0x0f,
- 0x8a, 0x12, 0x10, 0xf0, 0xbf, 0x15, 0xe5, 0x05, 0x9c, 0xa3, 0x9c, 0x98, 0x52, 0x88, 0xe6, 0x17,
- 0xa2, 0x0c, 0x67, 0xb5, 0xfb, 0x3a, 0x6c, 0x99, 0xcf, 0xb9, 0xf6, 0xe7, 0xcf, 0x1c, 0x8c, 0xd3,
- 0x64, 0x32, 0x28, 0x1d, 0x76, 0xc3, 0xf3, 0x0e, 0xc7, 0x73, 0x4e, 0xed, 0xb6, 0xa4, 0x47, 0x9f,
- 0x3d, 0x3a, 0x71, 0xe2, 0x44, 0xfc, 0x0a, 0xfa, 0xb9, 0x5b, 0x72, 0xb5, 0x02, 0x89, 0xfd, 0xaf,
- 0x1e, 0x3d, 0x46, 0xf9, 0xfb, 0x2f, 0x5b, 0xb6, 0xfc, 0xe4, 0x6f, 0xb4, 0x00, 0x06, 0xc4, 0xc0,
- 0x3b, 0x3a, 0x8d, 0xbe, 0x5a, 0xbc, 0x78, 0x09, 0xc7, 0x27, 0xe2, 0xc1, 0xd0, 0xbc, 0x8b, 0x5b,
- 0x84, 0x3b, 0x82, 0x54, 0x14, 0x14, 0x0a, 0x4e, 0xe2, 0xbd, 0x67, 0x14, 0x0c, 0x5a, 0x46, 0xc6,
- 0x0d, 0xce, 0x59, 0x49, 0x73, 0x07, 0xba, 0xe3, 0x44, 0xb5, 0x93, 0x51, 0xef, 0xa1, 0xdd, 0x68,
- 0xcd, 0xe5, 0x5c, 0xf2, 0xdd, 0xbb, 0x7e, 0xf2, 0x4c, 0xa6, 0x07, 0x4c, 0x9e, 0x0c, 0xd8, 0x0b,
- 0xe1, 0x56, 0x78, 0x19, 0xcf, 0xf3, 0x0c, 0x1e, 0x3c, 0xf8, 0xfe, 0xfd, 0x07, 0x02, 0x25, 0xd8,
- 0xeb, 0xb5, 0xd5, 0x15, 0x9c, 0xb2, 0xd3, 0xe5, 0x14, 0x6a, 0xba, 0x22, 0x23, 0x77, 0x7f, 0xfa,
- 0xe9, 0xd0, 0x21, 0x43, 0x06, 0x0e, 0x19, 0xf2, 0xc9, 0xe0, 0xc1, 0x9f, 0x0c, 0x1a, 0x34, 0x30,
- 0x2c, 0x6c, 0x8b, 0x46, 0xab, 0x83, 0xbd, 0x6c, 0x69, 0x6d, 0x85, 0xaa, 0xf5, 0x46, 0x8b, 0xb0,
- 0xef, 0x9f, 0xe4, 0x73, 0xf8, 0x65, 0x0a, 0x42, 0x0f, 0xdd, 0xe5, 0x99, 0x11, 0x80, 0xf9, 0xc5,
- 0x8d, 0x0b, 0xdf, 0x82, 0xe8, 0x83, 0x1f, 0x14, 0x1f, 0xb7, 0xe1, 0xb1, 0xb8, 0xe0, 0x79, 0x72,
- 0x72, 0xca, 0xbb, 0xef, 0xfe, 0xc7, 0xef, 0x03, 0x8d, 0x36, 0xf4, 0xc0, 0xb1, 0x63, 0xc7, 0xeb,
- 0xeb, 0x1b, 0x20, 0x0f, 0xc1, 0xb7, 0xf3, 0xf2, 0xf2, 0xcb, 0x1e, 0x95, 0x58, 0x35, 0x0a, 0xc6,
- 0x6e, 0xde, 0x1f, 0x15, 0xf9, 0x2f, 0x11, 0x8b, 0x6b, 0x00, 0x3c, 0x2e, 0x5d, 0x8a, 0x77, 0x38,
- 0x1d, 0xb4, 0x0e, 0x93, 0x51, 0xd3, 0xbc, 0x95, 0x25, 0x83, 0x35, 0x5c, 0xa0, 0x88, 0x35, 0x5c,
- 0x24, 0x96, 0x3b, 0xac, 0xb3, 0xa6, 0xb1, 0xa1, 0xfc, 0xa3, 0x8f, 0xfa, 0x61, 0xe2, 0xc7, 0xc4,
- 0x44, 0x5b, 0x2d, 0x6a, 0xd6, 0xd5, 0xf2, 0xd2, 0x0e, 0xe3, 0xb0, 0x33, 0x44, 0x1f, 0xcb, 0x9a,
- 0x52, 0xe1, 0x9b, 0xdc, 0x44, 0x93, 0x97, 0x9b, 0xe5, 0x99, 0x59, 0x7b, 0xe7, 0xed, 0xb7, 0xbf,
- 0x0e, 0x9a, 0x5e, 0x5f, 0xfb, 0x80, 0xcf, 0x2c, 0x5c, 0x67, 0xb5, 0x07, 0x18, 0x65, 0x28, 0xab,
- 0xd9, 0xed, 0x36, 0xc5, 0xb9, 0xad, 0xb7, 0xdc, 0xd6, 0x34, 0xfe, 0xdf, 0x54, 0xb7, 0x25, 0xc5,
- 0x6d, 0x8c, 0x66, 0xdb, 0x97, 0xef, 0xde, 0xb1, 0x06, 0x7c, 0x06, 0x97, 0xd4, 0x2d, 0xfb, 0xcb,
- 0x89, 0xbb, 0x6e, 0x82, 0xab, 0x80, 0x69, 0x84, 0x6c, 0xda, 0x14, 0x1f, 0x7f, 0x19, 0xee, 0x0c,
- 0xf2, 0xd9, 0x3b, 0xe8, 0x87, 0x71, 0x3c, 0x73, 0xf6, 0xac, 0x60, 0xd6, 0x72, 0xf3, 0xf2, 0x7b,
- 0xf7, 0xf6, 0x91, 0x1f, 0xc4, 0x70, 0xef, 0xd8, 0xb9, 0x53, 0xc8, 0x57, 0xae, 0x59, 0xb3, 0xc6,
- 0xbb, 0x7b, 0xfb, 0xf6, 0xfd, 0x50, 0xaf, 0x6b, 0xe0, 0xec, 0xa5, 0xc4, 0x98, 0x48, 0xb4, 0x87,
- 0xa9, 0x8d, 0xd5, 0x1e, 0x22, 0xc6, 0x04, 0x74, 0x97, 0x46, 0x55, 0x3d, 0x7e, 0xdc, 0x58, 0x4f,
- 0xa8, 0x6c, 0xda, 0xbc, 0xb9, 0xb1, 0xb1, 0x49, 0xa5, 0xd6, 0xc0, 0xe6, 0xcf, 0x9a, 0x3d, 0xdb,
- 0xf3, 0x3c, 0x9f, 0xfd, 0xf3, 0x9f, 0xa0, 0x2e, 0x7c, 0xc6, 0x8a, 0x0b, 0xf0, 0xca, 0x02, 0xcf,
- 0x99, 0x33, 0xd7, 0xcd, 0xe7, 0xdf, 0xd5, 0x6a, 0x95, 0x64, 0x71, 0x2b, 0xce, 0x0f, 0x6b, 0x69,
- 0xb3, 0x3b, 0x80, 0xf6, 0xc7, 0x8f, 0xcb, 0x24, 0x9a, 0x1d, 0x7f, 0x5d, 0xbc, 0x78, 0x71, 0xf8,
- 0xd6, 0xad, 0xc2, 0x4e, 0xd4, 0x9e, 0x2d, 0x70, 0xc6, 0x0c, 0xcc, 0x44, 0x2f, 0xc4, 0xbe, 0x48,
- 0x1f, 0x28, 0x95, 0xca, 0x09, 0x13, 0x26, 0x08, 0x67, 0x80, 0x49, 0x69, 0x6d, 0x6b, 0xeb, 0x5c,
- 0x75, 0x40, 0x8f, 0xb1, 0xd9, 0xec, 0x81, 0x81, 0x81, 0xaf, 0x31, 0xe9, 0xf8, 0x13, 0x04, 0xf5,
- 0xf5, 0xeb, 0xd7, 0x61, 0x5a, 0x8b, 0xee, 0x3f, 0xb8, 0x76, 0xed, 0x7a, 0x74, 0xf4, 0x79, 0x08,
- 0xe1, 0xdc, 0xdb, 0xa9, 0x46, 0x79, 0x85, 0x4d, 0xdf, 0x16, 0xb1, 0xed, 0x5f, 0x6f, 0x91, 0x34,
- 0x62, 0xc4, 0xc8, 0xac, 0x2c, 0x19, 0x21, 0xfc, 0x2a, 0x31, 0xca, 0x8b, 0xb4, 0x9c, 0x83, 0x2f,
- 0x79, 0x35, 0x5c, 0x26, 0xfa, 0x18, 0xd6, 0x98, 0x48, 0x59, 0xbd, 0xb5, 0x21, 0x38, 0x78, 0x25,
- 0xac, 0xfd, 0xfd, 0xfb, 0x45, 0x6e, 0xb7, 0x8b, 0x25, 0x7a, 0xd6, 0x59, 0xc7, 0x5a, 0xf3, 0x89,
- 0x21, 0x8e, 0x68, 0x0f, 0xd2, 0xad, 0x21, 0xb4, 0x87, 0x69, 0x20, 0xcb, 0x7a, 0xd7, 0xcd, 0xb4,
- 0x17, 0xe4, 0xcb, 0x24, 0x2b, 0xa9, 0x31, 0xac, 0xf3, 0xe6, 0xcd, 0xa9, 0xaf, 0xb9, 0x4f, 0xec,
- 0xa5, 0xac, 0x29, 0x91, 0xd1, 0x44, 0x32, 0xed, 0xeb, 0x49, 0xdb, 0x72, 0xd2, 0xba, 0x80, 0x28,
- 0x66, 0x13, 0xc5, 0x0c, 0x22, 0x9f, 0x46, 0x9a, 0xa7, 0xd2, 0x8d, 0x53, 0xea, 0x06, 0x46, 0x84,
- 0x2f, 0x1c, 0x3d, 0x7a, 0x4c, 0xaf, 0x5e, 0xbd, 0xbb, 0x65, 0xe3, 0x23, 0x81, 0x12, 0xfc, 0xfd,
- 0xef, 0xef, 0x82, 0xc4, 0xce, 0x9c, 0x39, 0x6b, 0xd7, 0xee, 0x9f, 0x53, 0x6f, 0xa5, 0xd5, 0xd6,
- 0xd6, 0xf9, 0xcc, 0x83, 0x60, 0x9a, 0x08, 0xee, 0x1e, 0x2f, 0xd0, 0x4b, 0xef, 0x31, 0x7d, 0x8b,
- 0x86, 0x41, 0xfe, 0x01, 0x33, 0x22, 0x2c, 0xfc, 0xfc, 0x7c, 0xdc, 0x38, 0xef, 0x93, 0x4c, 0x9f,
- 0x36, 0x05, 0xfe, 0x08, 0x2a, 0xe0, 0x45, 0xe7, 0xc0, 0xc0, 0xea, 0x4e, 0xb2, 0xe6, 0x5b, 0x9c,
- 0xb3, 0x3a, 0x25, 0x39, 0xbe, 0x9f, 0x07, 0x53, 0xc5, 0x77, 0x31, 0x37, 0xe7, 0xcf, 0xa7, 0x5b,
- 0x2c, 0x7f, 0xfd, 0xf5, 0xd7, 0x92, 0x09, 0xf2, 0xc5, 0xc4, 0x89, 0x36, 0xbb, 0x1d, 0xf3, 0xa2,
- 0xad, 0x5d, 0xe9, 0x9d, 0x4a, 0xa6, 0xe5, 0x04, 0x3c, 0x91, 0x2e, 0xba, 0x5f, 0x24, 0x59, 0x2a,
- 0x88, 0xcb, 0xa6, 0x61, 0x52, 0x9a, 0x99, 0x73, 0xa7, 0xa7, 0xdf, 0x96, 0x14, 0x95, 0xc1, 0xbe,
- 0xfd, 0xfc, 0xf3, 0x1e, 0xc8, 0x07, 0xef, 0x08, 0x2d, 0x44, 0x90, 0xd9, 0x6c, 0x91, 0xa4, 0x5c,
- 0x45, 0x56, 0x50, 0x52, 0x5a, 0xfa, 0xe9, 0xa7, 0x54, 0xc1, 0xe1, 0x84, 0x50, 0xaf, 0x42, 0xe1,
- 0x96, 0xb8, 0xb3, 0x81, 0xd0, 0x69, 0x10, 0x08, 0x3e, 0x17, 0xd1, 0x0b, 0x0d, 0x60, 0xf3, 0xf7,
- 0x1f, 0x7d, 0xeb, 0x56, 0x5a, 0x4b, 0x6b, 0xdb, 0xc3, 0xe2, 0x92, 0xc4, 0xc4, 0xa4, 0x43, 0x87,
- 0x0e, 0xff, 0x14, 0xb1, 0x7d, 0xfb, 0x8e, 0x1d, 0x99, 0x49, 0xb1, 0xba, 0xda, 0x07, 0xda, 0x96,
- 0xda, 0x0d, 0x1e, 0x94, 0xd2, 0xbb, 0xe1, 0xa7, 0xbf, 0xfa, 0xea, 0x2b, 0x08, 0x1f, 0xa0, 0x95,
- 0xa7, 0x52, 0x44, 0xa3, 0x69, 0x6f, 0x6a, 0xac, 0xb0, 0x1a, 0xab, 0x58, 0xeb, 0x5d, 0x62, 0xba,
- 0xca, 0x1a, 0x2e, 0xb1, 0xa6, 0x1b, 0x9c, 0xed, 0xfe, 0xd3, 0xf2, 0x9c, 0xb0, 0xd0, 0x90, 0xaa,
- 0xaa, 0xa7, 0x7c, 0x82, 0xd2, 0x01, 0xe6, 0xc0, 0x23, 0x36, 0x8f, 0x1a, 0x58, 0xcd, 0x7e, 0x46,
- 0xb5, 0x13, 0xff, 0xb2, 0x86, 0x38, 0xd6, 0x5a, 0x40, 0x9c, 0xad, 0xc9, 0x37, 0x12, 0xbd, 0xe3,
- 0x9c, 0x30, 0x68, 0xab, 0x57, 0x2d, 0x6b, 0x6f, 0x29, 0x83, 0xfa, 0x60, 0xf5, 0x17, 0x19, 0x1a,
- 0xa4, 0x5d, 0xc9, 0xc8, 0xbf, 0x76, 0x35, 0x4e, 0x70, 0xd1, 0xc2, 0x03, 0x3f, 0xba, 0xb1, 0x0f,
- 0xdd, 0xf8, 0xa8, 0x77, 0xf8, 0xe6, 0x6f, 0xfd, 0xfd, 0xfd, 0x7b, 0xf6, 0xec, 0x9e, 0xad, 0xba,
- 0x5e, 0x3e, 0x41, 0xe3, 0x7d, 0xe8, 0x65, 0x78, 0xfc, 0xa3, 0x47, 0x8f, 0xe5, 0xe5, 0x83, 0x15,
- 0x16, 0xfa, 0xcc, 0x77, 0x0f, 0x1d, 0x3a, 0xd4, 0xe1, 0x70, 0xba, 0x69, 0x12, 0x9f, 0x5b, 0xbc,
- 0x64, 0x89, 0x4f, 0xf7, 0xf4, 0xc9, 0xc0, 0x81, 0xb4, 0xd2, 0xbb, 0xe3, 0x59, 0x49, 0x49, 0x89,
- 0x77, 0xd1, 0x3e, 0xda, 0xfe, 0xa8, 0x3d, 0x1c, 0x23, 0x07, 0x07, 0xa0, 0x9d, 0xa3, 0x3d, 0x42,
- 0xe7, 0x32, 0xfc, 0x94, 0x35, 0xdf, 0x69, 0x6b, 0x08, 0x0b, 0xdd, 0xd0, 0xc5, 0xad, 0xbd, 0xe8,
- 0x12, 0xad, 0xff, 0x6b, 0xef, 0x3b, 0xc0, 0xa2, 0xba, 0xd6, 0x76, 0xef, 0xf3, 0xdf, 0xfb, 0x9f,
- 0xfc, 0xf7, 0x9c, 0x93, 0xe4, 0xc4, 0xc4, 0x24, 0xf6, 0xae, 0x51, 0xda, 0x0c, 0x88, 0x80, 0x18,
- 0xb1, 0xc6, 0xde, 0x42, 0x11, 0x1b, 0x22, 0x22, 0x28, 0x4d, 0x69, 0x02, 0xa2, 0xc4, 0x8a, 0x20,
- 0x60, 0x17, 0x1b, 0x52, 0x14, 0x05, 0x11, 0x91, 0x5e, 0xa5, 0xf7, 0xde, 0x19, 0x7a, 0xef, 0x33,
- 0xc0, 0x30, 0xc3, 0x34, 0x92, 0xe7, 0x3e, 0xf7, 0xdd, 0x7b, 0xcb, 0x88, 0x33, 0x68, 0x6c, 0x49,
- 0x4e, 0x9e, 0x93, 0xef, 0x59, 0x31, 0xcc, 0xec, 0x32, 0x7b, 0xaf, 0xf5, 0xae, 0xf7, 0x7b, 0xbf,
- 0x55, 0x77, 0xec, 0x20, 0x91, 0x40, 0xb4, 0xc4, 0x4a, 0x8c, 0xbd, 0x47, 0xd1, 0xe7, 0xe6, 0xe5,
- 0x51, 0x41, 0x99, 0xff, 0xc3, 0x87, 0x12, 0x63, 0x45, 0x00, 0xbc, 0x9c, 0x9c, 0x1c, 0x1c, 0xe2,
- 0x70, 0x87, 0x5c, 0x5d, 0x5d, 0x25, 0xee, 0x8c, 0xb0, 0x11, 0x50, 0x81, 0x42, 0x1e, 0x1d, 0xe5,
- 0x51, 0x06, 0x61, 0x8f, 0x48, 0xed, 0x15, 0xc4, 0xbe, 0x5c, 0x84, 0xf3, 0x97, 0xf0, 0xf0, 0x08,
- 0x04, 0x17, 0x9f, 0x90, 0x23, 0xf9, 0xe3, 0xe2, 0xe3, 0x47, 0xd6, 0x87, 0xff, 0x45, 0x0c, 0x57,
- 0xe8, 0xa8, 0x31, 0x47, 0x2f, 0x50, 0x06, 0x3d, 0xb9, 0x7e, 0xfd, 0xfa, 0xe7, 0xcf, 0x13, 0x7b,
- 0x7a, 0x7b, 0x6b, 0xeb, 0xea, 0x63, 0xe3, 0xe2, 0x3d, 0x3d, 0x6f, 0xda, 0xd9, 0xdb, 0x1b, 0x1b,
- 0x1f, 0x34, 0x35, 0x33, 0x4b, 0x7c, 0xe8, 0xd9, 0x5d, 0x91, 0xda, 0x5c, 0x5d, 0x78, 0xc0, 0xf0,
- 0xb5, 0x0b, 0xce, 0xe0, 0x0e, 0xa8, 0xdb, 0xe4, 0x18, 0xc8, 0x61, 0xf2, 0xdd, 0x87, 0x23, 0x22,
- 0x22, 0x0e, 0x1d, 0x3a, 0xa8, 0xa3, 0xa3, 0x15, 0xfc, 0xe4, 0x1e, 0x87, 0x95, 0x45, 0xc8, 0x4e,
- 0x48, 0x59, 0xf8, 0xf1, 0xc1, 0xf4, 0xa6, 0xba, 0xcc, 0xee, 0xae, 0x46, 0xb2, 0x27, 0x9d, 0xec,
- 0x52, 0x17, 0xf6, 0x11, 0x52, 0x9f, 0x93, 0x47, 0xb4, 0x37, 0x42, 0xaa, 0x75, 0x5d, 0x20, 0x06,
- 0xd5, 0x23, 0x40, 0x1b, 0xcc, 0xe9, 0x63, 0xd6, 0xd9, 0xda, 0x8e, 0xb1, 0xdf, 0x13, 0xf8, 0x64,
- 0xc5, 0x8a, 0xe5, 0x15, 0xe5, 0xf9, 0x08, 0x10, 0x20, 0x92, 0x11, 0xd3, 0xf1, 0x3b, 0x4f, 0xf3,
- 0x5b, 0x8c, 0xf9, 0x0d, 0x5b, 0x79, 0xb5, 0x1a, 0xc4, 0xca, 0x7e, 0x04, 0x62, 0xe7, 0x0d, 0x55,
- 0x4c, 0xb2, 0x32, 0xdf, 0xb6, 0x70, 0xe1, 0x42, 0x84, 0x24, 0x1f, 0x45, 0xc7, 0x8e, 0xde, 0x6d,
- 0xf3, 0xc8, 0x11, 0x4b, 0x5f, 0x5f, 0xbf, 0xfc, 0x82, 0x02, 0xaf, 0x7b, 0xf7, 0xc6, 0xec, 0xb6,
- 0x33, 0x32, 0x32, 0xa2, 0x06, 0xd4, 0xb5, 0xb6, 0xb6, 0x51, 0x1e, 0x50, 0xfa, 0x2d, 0x36, 0x6e,
- 0xdc, 0x08, 0x7f, 0x04, 0x20, 0x79, 0x7b, 0x7b, 0x8f, 0x39, 0x89, 0x23, 0x33, 0x23, 0x51, 0xc4,
- 0xab, 0x17, 0x0e, 0x24, 0x0b, 0x99, 0x54, 0x20, 0xe0, 0x45, 0xc4, 0x5c, 0x9c, 0xa2, 0xaa, 0x8a,
- 0xac, 0xf5, 0xeb, 0xdf, 0x76, 0xc2, 0x0b, 0x4a, 0xc7, 0xda, 0xda, 0x9a, 0x7a, 0x18, 0x50, 0xa2,
- 0x84, 0xe4, 0x86, 0xbf, 0x68, 0xef, 0x20, 0xc6, 0x69, 0xf3, 0x78, 0xfc, 0x33, 0x67, 0xce, 0x48,
- 0x0c, 0x8d, 0x40, 0x00, 0xde, 0xd8, 0xd4, 0x8c, 0xa3, 0x4c, 0x56, 0xdf, 0xf6, 0xed, 0xdb, 0x25,
- 0xee, 0x0c, 0x42, 0x2e, 0x2e, 0x2e, 0x49, 0x4b, 0x4f, 0x97, 0x93, 0xaa, 0xb3, 0xa8, 0x26, 0x0d,
- 0xe4, 0x24, 0x44, 0xf1, 0x74, 0xad, 0x11, 0x49, 0x40, 0x84, 0x54, 0xb7, 0xef, 0xdc, 0xa1, 0x62,
- 0x55, 0x75, 0x75, 0xf5, 0x7e, 0x6a, 0x2b, 0xae, 0x57, 0xb7, 0x38, 0x4c, 0x4a, 0x4e, 0x46, 0x6c,
- 0x3b, 0xe6, 0xeb, 0xe0, 0x09, 0xb5, 0xb4, 0xb4, 0x72, 0x73, 0xf3, 0x38, 0x1c, 0x6e, 0x2f, 0x93,
- 0x49, 0xcc, 0x05, 0x8e, 0x8c, 0x82, 0x17, 0x83, 0x72, 0x86, 0x7f, 0x81, 0x4a, 0xc9, 0x0c, 0xbc,
- 0xda, 0x5d, 0x9e, 0x58, 0x53, 0x9a, 0xb5, 0x43, 0x57, 0x67, 0xcc, 0x3b, 0xe0, 0xd9, 0x8e, 0x58,
- 0x5a, 0xd6, 0xd6, 0xd6, 0x91, 0xdc, 0xfe, 0x33, 0x8f, 0x2f, 0xf0, 0xf1, 0xf5, 0x05, 0x63, 0x50,
- 0x3e, 0xce, 0xc1, 0xfe, 0x08, 0xab, 0x33, 0x03, 0xf9, 0x4c, 0x70, 0x2c, 0x2b, 0x50, 0x40, 0xcc,
- 0xa9, 0xaf, 0x22, 0x22, 0x32, 0x21, 0xa4, 0x3e, 0x4c, 0xd0, 0xd8, 0x50, 0xf3, 0xe8, 0xa1, 0x57,
- 0x69, 0x61, 0x34, 0xbf, 0xff, 0xb9, 0x80, 0xe9, 0x4f, 0x14, 0x0a, 0x21, 0x77, 0x63, 0x84, 0xdc,
- 0xf2, 0x86, 0xfa, 0x52, 0x05, 0x05, 0xc9, 0xac, 0x00, 0x59, 0x11, 0xcb, 0x24, 0xc6, 0x44, 0x73,
- 0x38, 0x2c, 0x91, 0x80, 0x54, 0x1d, 0x6c, 0x5c, 0xe8, 0x33, 0x02, 0xda, 0xcd, 0xbc, 0xda, 0xa5,
- 0xc4, 0x44, 0x1b, 0xc6, 0xdc, 0x8c, 0xa7, 0xea, 0x3b, 0xb7, 0x6f, 0x80, 0xd4, 0xf9, 0x28, 0x6b,
- 0xc8, 0x88, 0xdb, 0xb5, 0xe0, 0x55, 0x37, 0x6c, 0xdc, 0x78, 0xc2, 0xc9, 0xe9, 0x69, 0x48, 0x08,
- 0x42, 0x69, 0x3b, 0x3b, 0xbb, 0x31, 0x57, 0xd9, 0xf5, 0xbb, 0x7f, 0xff, 0xe7, 0x91, 0xcc, 0x1f,
- 0x73, 0x76, 0x2d, 0xf2, 0x4d, 0x2c, 0x62, 0xad, 0x6d, 0x6c, 0xa4, 0x1b, 0x0f, 0x51, 0xd1, 0x58,
- 0xcc, 0x36, 0xa2, 0x13, 0x8a, 0x98, 0xac, 0x1d, 0x0e, 0x29, 0x0b, 0x27, 0x25, 0x24, 0xc4, 0x52,
- 0xfd, 0x93, 0xa0, 0xfb, 0x33, 0xa5, 0x46, 0xa8, 0xbe, 0xce, 0x00, 0x51, 0x6a, 0xbd, 0x35, 0x3e,
- 0x5f, 0x00, 0xb2, 0x95, 0x50, 0x86, 0x10, 0x12, 0x2c, 0xb2, 0x2f, 0x0c, 0x82, 0x41, 0x5f, 0x5f,
- 0x7f, 0xf4, 0x21, 0x72, 0x99, 0x82, 0x13, 0xf0, 0x14, 0x38, 0x0a, 0x54, 0xcf, 0x7e, 0x75, 0x67,
- 0x79, 0x1c, 0xdd, 0xb2, 0x65, 0x0b, 0xc4, 0x46, 0x45, 0x65, 0xd5, 0x98, 0x8d, 0xb4, 0xf0, 0x3e,
- 0xa3, 0x46, 0x68, 0xff, 0xbf, 0xd1, 0x23, 0x5b, 0xe0, 0xbb, 0x29, 0xfe, 0x44, 0x84, 0x48, 0x61,
- 0x78, 0x34, 0xc1, 0x72, 0xb8, 0x5c, 0x7c, 0xff, 0xba, 0xd6, 0xd4, 0xdd, 0xbb, 0xf7, 0x20, 0xc0,
- 0x14, 0x08, 0x85, 0x43, 0x3c, 0x3e, 0x9e, 0xbc, 0xbe, 0xa1, 0x31, 0xe1, 0x79, 0xa2, 0xe7, 0xcd,
- 0x9b, 0x08, 0x2b, 0xf6, 0xed, 0xdb, 0x77, 0xc8, 0xd8, 0xa8, 0x20, 0xf8, 0x5a, 0x4f, 0x45, 0x62,
- 0x45, 0x61, 0xda, 0xb6, 0xad, 0x63, 0xb4, 0x6e, 0xc1, 0x31, 0x1d, 0x3f, 0x71, 0xa2, 0xb3, 0xb3,
- 0x8b, 0x82, 0x2b, 0x7b, 0x90, 0xe3, 0xe6, 0xe6, 0x2e, 0x96, 0x1f, 0x08, 0x75, 0x7d, 0x7d, 0xae,
- 0xf1, 0xd8, 0x79, 0x44, 0x56, 0x43, 0xc7, 0x42, 0x8c, 0xf5, 0x47, 0x0b, 0xb9, 0x25, 0x22, 0x7e,
- 0xc7, 0xb0, 0x08, 0xa1, 0x24, 0x37, 0x34, 0x34, 0x74, 0xcd, 0x9a, 0x35, 0x60, 0xad, 0x6b, 0x57,
- 0x5c, 0xf8, 0xec, 0x7c, 0xe1, 0x40, 0x34, 0xc1, 0xc3, 0xfd, 0x11, 0x28, 0x23, 0x11, 0xbf, 0x29,
- 0x28, 0xc8, 0x5f, 0xc2, 0x99, 0xa2, 0x7e, 0xfd, 0xf8, 0xe3, 0x8f, 0x05, 0x85, 0x05, 0xe4, 0x1c,
- 0x5e, 0xc1, 0xb0, 0x68, 0x90, 0x3f, 0xd4, 0x81, 0x2a, 0x20, 0x64, 0x27, 0x92, 0xa0, 0x3d, 0x45,
- 0xce, 0xe2, 0xdf, 0xc4, 0xab, 0x55, 0x1d, 0x28, 0x9a, 0x7f, 0xe1, 0xc4, 0xfa, 0x65, 0xcb, 0x34,
- 0x10, 0x08, 0x53, 0x0b, 0x27, 0x7e, 0x20, 0xc1, 0x8a, 0x47, 0x71, 0x43, 0x03, 0xe8, 0xe8, 0x6c,
- 0xbf, 0x70, 0xc1, 0x2d, 0x2e, 0x2e, 0xbe, 0xac, 0xac, 0x0c, 0xf5, 0x5d, 0x5a, 0x7f, 0xe2, 0x9b,
- 0xd2, 0xd2, 0xb2, 0xbe, 0xbe, 0x7e, 0xa4, 0xcb, 0x57, 0xae, 0x88, 0x9b, 0xca, 0x47, 0x1b, 0x9e,
- 0x2a, 0x31, 0x31, 0x69, 0x98, 0x5c, 0x5c, 0x65, 0xeb, 0x58, 0x8b, 0xf9, 0x00, 0x0f, 0x43, 0x43,
- 0x2c, 0x11, 0xbf, 0x5d, 0x88, 0x5a, 0x39, 0x98, 0x25, 0x60, 0xa7, 0x12, 0xd0, 0x1d, 0x62, 0xf4,
- 0x31, 0x1b, 0xec, 0xec, 0x6c, 0xde, 0xbe, 0x1b, 0xe8, 0xeb, 0xaf, 0xbf, 0x26, 0xda, 0xe7, 0x7f,
- 0xfe, 0xa5, 0xba, 0xba, 0x06, 0x5a, 0x57, 0xe2, 0xe8, 0xd5, 0x6b, 0xd7, 0x50, 0xf4, 0xc0, 0x64,
- 0x5e, 0x7e, 0xc1, 0xe2, 0x51, 0x63, 0xbd, 0x3e, 0x21, 0x3d, 0x3b, 0xc8, 0x87, 0x6a, 0x61, 0x00,
- 0x91, 0x4a, 0xfc, 0x22, 0xb9, 0x46, 0x0a, 0xb1, 0xec, 0x46, 0x77, 0x4f, 0xcf, 0x98, 0x6d, 0x50,
- 0x7e, 0x7e, 0xf7, 0x29, 0xda, 0x1c, 0x99, 0x54, 0xf0, 0x22, 0xec, 0x62, 0xb1, 0xfa, 0xa8, 0x9e,
- 0x23, 0xd4, 0xd9, 0x4a, 0x72, 0xa5, 0x4d, 0xf1, 0x52, 0x33, 0x14, 0x62, 0x8b, 0x4b, 0x4a, 0x56,
- 0xac, 0x58, 0x21, 0x7d, 0x43, 0x80, 0x0d, 0xf1, 0x29, 0x55, 0xbf, 0x20, 0x3d, 0xb9, 0x43, 0x3c,
- 0x68, 0x2a, 0xd4, 0x0b, 0x9c, 0x1f, 0x14, 0xf4, 0xc4, 0xd9, 0xf9, 0x3c, 0x1c, 0xdf, 0x99, 0x63,
- 0x36, 0x65, 0xe1, 0xb7, 0x7a, 0xab, 0x92, 0x8a, 0x73, 0x13, 0xd7, 0xbf, 0x3a, 0xef, 0x12, 0x55,
- 0x75, 0xea, 0xb4, 0x69, 0xd7, 0xaf, 0xdf, 0x20, 0xe7, 0xef, 0x10, 0x4a, 0xa0, 0xbd, 0xbd, 0xc3,
- 0xd6, 0xf6, 0xe8, 0x37, 0xdf, 0x7c, 0x23, 0xde, 0x07, 0x41, 0x57, 0x57, 0xab, 0xb1, 0x2e, 0x97,
- 0x1c, 0x12, 0xf0, 0x98, 0x68, 0x93, 0x01, 0x62, 0x07, 0x08, 0xc4, 0x0e, 0xf3, 0xbb, 0x7a, 0xba,
- 0xdb, 0xec, 0xed, 0xed, 0x71, 0x32, 0x4e, 0xc3, 0x93, 0xc7, 0x44, 0x05, 0x0b, 0xb9, 0x0c, 0xc1,
- 0x60, 0x86, 0x70, 0x20, 0x89, 0x98, 0xe0, 0x3c, 0x54, 0x39, 0x2c, 0xe8, 0xd1, 0xd4, 0x7c, 0x65,
- 0x38, 0x10, 0xb2, 0xc8, 0xc4, 0xc4, 0xa4, 0xb3, 0xab, 0x9b, 0xec, 0x6d, 0x1c, 0x16, 0x08, 0x05,
- 0x95, 0x95, 0xe5, 0x9a, 0x9a, 0xdb, 0x7c, 0xee, 0xdd, 0xe0, 0x0f, 0x32, 0x88, 0xd8, 0x8d, 0xe5,
- 0xc7, 0xef, 0x3c, 0xc9, 0x6f, 0xde, 0xd7, 0x5f, 0xbe, 0xe6, 0xc1, 0x75, 0x44, 0xbd, 0x9b, 0xe5,
- 0xe4, 0xe4, 0x28, 0x19, 0xfc, 0xe1, 0x92, 0x80, 0x9a, 0x8a, 0x48, 0x89, 0x58, 0x7d, 0xfd, 0x7d,
- 0x37, 0x6e, 0x78, 0xa6, 0x67, 0x64, 0xc4, 0xc6, 0xc6, 0x2d, 0x5e, 0xbc, 0x58, 0x3a, 0x6f, 0xf1,
- 0x52, 0xb2, 0x10, 0xa9, 0x72, 0xf2, 0x48, 0x28, 0xf7, 0x31, 0xd1, 0x05, 0x0a, 0xa5, 0xfa, 0xa7,
- 0x20, 0x85, 0xc7, 0x1c, 0x98, 0x74, 0xe1, 0xc2, 0x05, 0x81, 0x80, 0x4b, 0xaa, 0xa6, 0x0e, 0x11,
- 0xaf, 0x49, 0x08, 0x79, 0xc0, 0x6b, 0x44, 0x7c, 0x50, 0x5c, 0x9c, 0xf3, 0x36, 0xad, 0x94, 0x62,
- 0x9b, 0x38, 0x71, 0x52, 0x4e, 0x4e, 0x2e, 0x35, 0x9a, 0x8b, 0x52, 0x8f, 0x62, 0x43, 0x05, 0x84,
- 0x0b, 0xa0, 0xc6, 0x91, 0x86, 0x87, 0x87, 0x4b, 0xf4, 0x0e, 0x40, 0xc4, 0xa6, 0xa5, 0x67, 0x50,
- 0x88, 0x95, 0x5e, 0xfe, 0x1d, 0xef, 0x15, 0x42, 0x86, 0x8d, 0x54, 0xfb, 0x83, 0xf4, 0x3b, 0x9e,
- 0x3a, 0x7d, 0xfa, 0xe5, 0xc8, 0xd8, 0x91, 0x39, 0xb0, 0xf8, 0x58, 0x51, 0x59, 0x49, 0x8d, 0x1a,
- 0x42, 0xd6, 0xfd, 0x32, 0xb2, 0xb4, 0x8b, 0x18, 0xb1, 0xb8, 0x5b, 0x40, 0x60, 0xa0, 0x74, 0xdf,
- 0xfd, 0xdc, 0xb9, 0x73, 0x2f, 0x5d, 0xbe, 0x3c, 0x30, 0xc0, 0xa6, 0x46, 0xd5, 0x42, 0xa5, 0x3c,
- 0x7d, 0xfa, 0x54, 0x45, 0x45, 0x05, 0xe5, 0x5b, 0x58, 0x58, 0x08, 0xdc, 0xde, 0xf3, 0xf6, 0x3e,
- 0x73, 0xf6, 0xac, 0xef, 0x15, 0xe7, 0x9a, 0x78, 0x1f, 0x26, 0x23, 0xb9, 0x34, 0x3f, 0x69, 0xd3,
- 0xc6, 0x97, 0xad, 0x22, 0x60, 0x6c, 0x64, 0xda, 0xd3, 0xa7, 0x21, 0x43, 0xe4, 0x56, 0xe0, 0xa0,
- 0x68, 0xc4, 0xc5, 0xfb, 0x0c, 0x0c, 0x46, 0xb7, 0x9d, 0xca, 0xc8, 0x2c, 0x08, 0x0b, 0x0d, 0x18,
- 0xe6, 0xd5, 0x12, 0x81, 0x03, 0x3c, 0x1a, 0xd3, 0x8f, 0x6c, 0x2b, 0x48, 0x12, 0xf1, 0xaa, 0x9b,
- 0x1b, 0x2b, 0x76, 0xec, 0x78, 0x39, 0x41, 0x4f, 0x45, 0x65, 0x51, 0x6d, 0x4d, 0xb1, 0x90, 0x47,
- 0xf6, 0xb6, 0x0c, 0xe6, 0x09, 0xb9, 0xa5, 0x22, 0x7e, 0x4b, 0x53, 0x13, 0x43, 0xec, 0x17, 0x70,
- 0xb7, 0x19, 0x33, 0x66, 0x9c, 0x73, 0x76, 0xa6, 0x66, 0x5c, 0x8a, 0xc8, 0x49, 0xa9, 0x50, 0xec,
- 0xd4, 0x28, 0x1a, 0x59, 0x59, 0x99, 0xa0, 0x40, 0x5f, 0x6e, 0x7f, 0x25, 0x82, 0x35, 0x7e, 0x8f,
- 0x57, 0x7b, 0xc5, 0xc9, 0x10, 0xbf, 0xa3, 0x86, 0x86, 0x07, 0x34, 0x34, 0x34, 0xa0, 0x30, 0x3f,
- 0xd6, 0x24, 0x71, 0x6a, 0x14, 0x37, 0x39, 0x15, 0xf1, 0x7b, 0x04, 0x05, 0xde, 0xde, 0x3e, 0xf9,
- 0x05, 0x85, 0xc8, 0xa5, 0x37, 0xc4, 0xb3, 0x6f, 0xb6, 0x75, 0xeb, 0xd6, 0x53, 0xf4, 0xe2, 0xeb,
- 0xeb, 0x3b, 0x66, 0x07, 0x84, 0xa5, 0x25, 0xa4, 0xb2, 0xb7, 0xaf, 0x8f, 0x97, 0xaf, 0xcf, 0x9d,
- 0xfb, 0x7e, 0xb7, 0x1b, 0x1b, 0xca, 0x45, 0x82, 0x3e, 0x3e, 0x7f, 0x20, 0x28, 0x28, 0x60, 0xf4,
- 0x58, 0x02, 0x94, 0x26, 0x9e, 0x61, 0xe5, 0xca, 0x55, 0x64, 0x5a, 0xa9, 0xfe, 0x2a, 0x4f, 0x7e,
- 0x42, 0xb6, 0x48, 0xb4, 0xb5, 0xb5, 0x03, 0x93, 0x70, 0x7f, 0xe2, 0x6e, 0x26, 0xf1, 0xa1, 0x33,
- 0x67, 0xce, 0xfa, 0xf9, 0xf9, 0x79, 0xfb, 0xf8, 0x40, 0x78, 0x4b, 0x5c, 0x08, 0x92, 0x87, 0x08,
- 0xa7, 0x10, 0x2b, 0xbd, 0x1e, 0x11, 0xd4, 0x51, 0x43, 0x43, 0x23, 0xd5, 0x7c, 0x07, 0x01, 0x29,
- 0x1d, 0x5a, 0x82, 0x48, 0xa9, 0x17, 0xfc, 0xe5, 0xd5, 0x7e, 0x01, 0xd4, 0x11, 0xaa, 0xe3, 0xf5,
- 0xbc, 0x8b, 0xcb, 0xcf, 0x2f, 0xe7, 0xcf, 0xbe, 0x20, 0x58, 0x48, 0x53, 0x0b, 0x8b, 0x57, 0x7a,
- 0xab, 0x71, 0x67, 0xd4, 0x9d, 0x87, 0x0f, 0x1f, 0xa1, 0xd0, 0x89, 0x45, 0x75, 0x84, 0xa2, 0xca,
- 0xaa, 0x2a, 0xe8, 0x0a, 0x71, 0xce, 0x7b, 0x7a, 0x7a, 0x96, 0x95, 0x57, 0xa0, 0x3e, 0x5e, 0xbf,
- 0xe1, 0x19, 0xe7, 0xef, 0xd9, 0x98, 0xec, 0xcf, 0xac, 0x4e, 0x6c, 0xad, 0xc9, 0x33, 0x33, 0x31,
- 0xc6, 0xb5, 0xe0, 0xc3, 0xf9, 0xf3, 0xe7, 0x83, 0x9c, 0xa9, 0xc1, 0x96, 0xc3, 0xa4, 0x62, 0x47,
- 0xf5, 0x5c, 0xb5, 0x6a, 0xd5, 0xe8, 0x5a, 0x36, 0x6e, 0xdc, 0x17, 0x27, 0x4e, 0x1c, 0x1b, 0x64,
- 0xb7, 0x88, 0xb8, 0xe5, 0xc2, 0x81, 0xe7, 0x82, 0xbe, 0x10, 0x41, 0x5f, 0xb0, 0x70, 0x20, 0x56,
- 0xc8, 0x29, 0xaa, 0x2c, 0x4b, 0xd3, 0xd3, 0xdb, 0x29, 0x7e, 0x41, 0x5c, 0x75, 0xcc, 0xc1, 0x0e,
- 0x9e, 0x8e, 0x58, 0x51, 0x8a, 0x53, 0x4c, 0x24, 0x5e, 0xad, 0x48, 0xd8, 0xe3, 0xee, 0xee, 0x42,
- 0x9d, 0x00, 0xc8, 0x2d, 0x5e, 0xac, 0xfe, 0x28, 0x20, 0x60, 0x68, 0x88, 0x47, 0x85, 0x0f, 0x3d,
- 0x3d, 0xbd, 0x77, 0xef, 0x7a, 0xe1, 0x31, 0xc4, 0xbf, 0xa8, 0xb2, 0x48, 0x39, 0x3a, 0xf2, 0x09,
- 0xb7, 0xbf, 0xaa, 0xbb, 0x2d, 0x25, 0x36, 0x9a, 0x58, 0x2f, 0x71, 0xdf, 0x3e, 0x03, 0x94, 0x1d,
- 0xb5, 0xa0, 0xf7, 0x47, 0x41, 0x2c, 0x35, 0x9c, 0x60, 0xe6, 0xcc, 0x99, 0x00, 0x86, 0xa5, 0x95,
- 0x55, 0x40, 0x40, 0x20, 0x82, 0x0e, 0xe4, 0xdb, 0xbb, 0x76, 0x5e, 0x53, 0x86, 0x0a, 0xf8, 0xf0,
- 0xd1, 0x23, 0xe4, 0x3f, 0x54, 0xa2, 0x93, 0x93, 0xd3, 0xaf, 0x8e, 0x86, 0x82, 0xae, 0x88, 0x8b,
- 0x8b, 0x11, 0x89, 0xf8, 0x4c, 0x66, 0x8f, 0xb9, 0xb9, 0xf9, 0xe8, 0x43, 0x00, 0xa1, 0xe3, 0xf1,
- 0xe3, 0x15, 0x15, 0x95, 0xe5, 0xe5, 0x15, 0xe5, 0x15, 0x95, 0xf0, 0x8f, 0x12, 0xd7, 0xa2, 0x5e,
- 0xf3, 0x05, 0x82, 0xfe, 0x01, 0x36, 0x2a, 0xda, 0xdb, 0x6b, 0x09, 0xbc, 0xac, 0xc5, 0xe1, 0xc3,
- 0x7c, 0x04, 0x86, 0x64, 0x97, 0x84, 0x74, 0xfb, 0x15, 0xe4, 0x9c, 0x90, 0x6c, 0x17, 0xc2, 0x5b,
- 0xd8, 0x8e, 0x35, 0xdc, 0x1a, 0xe1, 0xc6, 0x88, 0xc7, 0x7f, 0xb9, 0xcb, 0x06, 0x3e, 0x06, 0x06,
- 0x06, 0xc2, 0xbf, 0xe0, 0xb1, 0xb3, 0xb3, 0x73, 0x5e, 0xce, 0xf8, 0x1e, 0x91, 0x04, 0x55, 0x0c,
- 0xc6, 0xe8, 0xb6, 0x17, 0xe4, 0x0c, 0xaa, 0x61, 0x74, 0x74, 0x0c, 0x55, 0xfa, 0x60, 0xc8, 0xa0,
- 0x27, 0x4f, 0x50, 0x95, 0x46, 0xc7, 0x0e, 0x08, 0x09, 0x9b, 0x9b, 0x5b, 0x52, 0x52, 0xd3, 0x1e,
- 0xf8, 0xfb, 0xe7, 0x84, 0xf9, 0x35, 0xa7, 0x05, 0x30, 0xab, 0xe2, 0x06, 0x3b, 0x4b, 0xd3, 0x53,
- 0xa2, 0x4f, 0x9d, 0x3c, 0x71, 0xf6, 0xec, 0xe9, 0xb0, 0xf0, 0x30, 0x32, 0xbe, 0xfb, 0x99, 0xd4,
- 0x30, 0xbd, 0xd7, 0xaf, 0x5f, 0x97, 0x5e, 0x88, 0x63, 0xdd, 0xba, 0xb5, 0x8d, 0x8d, 0x0c, 0x72,
- 0x64, 0x45, 0x09, 0xfc, 0x35, 0x81, 0x55, 0x76, 0xa2, 0x88, 0x53, 0x50, 0x52, 0x98, 0xb0, 0x67,
- 0xb7, 0xee, 0x17, 0xa3, 0x7a, 0x6a, 0xa6, 0x4e, 0x9d, 0x12, 0x1e, 0x16, 0x24, 0xe0, 0xb5, 0x12,
- 0x63, 0x30, 0xc0, 0xb1, 0x20, 0x58, 0x5e, 0x63, 0x1f, 0xab, 0x05, 0x12, 0xf4, 0x13, 0x32, 0x6a,
- 0xd0, 0xd1, 0xd1, 0x49, 0x49, 0x49, 0xa5, 0xb4, 0x16, 0x52, 0x4b, 0x6b, 0xdb, 0xa9, 0x53, 0xa7,
- 0x25, 0x86, 0xbb, 0xa3, 0x20, 0x96, 0x2f, 0x5f, 0x96, 0x9e, 0x96, 0x84, 0xc0, 0x36, 0x31, 0x29,
- 0xf9, 0x86, 0xa7, 0xa7, 0xa9, 0xa9, 0xd9, 0xea, 0xd5, 0xab, 0xe7, 0xcc, 0x99, 0x43, 0xf5, 0x0a,
- 0x7d, 0xb8, 0x2a, 0x20, 0xc2, 0x2e, 0x62, 0x3d, 0x8d, 0x79, 0x1b, 0x36, 0x6c, 0x38, 0x76, 0xcc,
- 0x11, 0x35, 0x1a, 0x19, 0x2e, 0x11, 0xaa, 0xbc, 0xa5, 0x21, 0x3c, 0xbf, 0x77, 0xcf, 0x6b, 0x80,
- 0x0d, 0x3d, 0x36, 0xdc, 0xd8, 0xd4, 0xb4, 0x73, 0xd4, 0x20, 0xab, 0xd7, 0x19, 0xf4, 0x67, 0x71,
- 0x71, 0x31, 0xd0, 0x51, 0x57, 0x5f, 0x2f, 0x91, 0xdb, 0x78, 0xc7, 0x8c, 0xcc, 0x4c, 0x4a, 0x98,
- 0xe1, 0x5f, 0xe0, 0x41, 0xe2, 0x5a, 0x72, 0x01, 0x25, 0x62, 0x39, 0x8b, 0x03, 0x07, 0x0e, 0xbc,
- 0x65, 0x1f, 0x2b, 0xb1, 0x1d, 0x9b, 0xcc, 0x82, 0xc8, 0xa8, 0x48, 0xea, 0x9e, 0x99, 0x99, 0x59,
- 0xd2, 0x80, 0x74, 0x72, 0xfa, 0x49, 0xbc, 0xc0, 0x0b, 0x28, 0xe2, 0x8b, 0x2f, 0x24, 0x7b, 0xfd,
- 0xa0, 0x40, 0x46, 0x35, 0xb4, 0xbe, 0xf0, 0xfb, 0xe0, 0x37, 0x0f, 0x0f, 0x0f, 0xe0, 0x70, 0xd5,
- 0xea, 0xd5, 0xd4, 0xfc, 0xaf, 0x17, 0x53, 0x14, 0x45, 0x90, 0x79, 0x22, 0x94, 0x72, 0x40, 0x40,
- 0xc0, 0x68, 0xba, 0x06, 0xb7, 0x83, 0x1b, 0x49, 0xdf, 0xfa, 0x33, 0x88, 0xd4, 0xda, 0xda, 0x5a,
- 0xba, 0x3d, 0x19, 0x61, 0x3e, 0x94, 0x46, 0x61, 0x51, 0x71, 0x44, 0x78, 0x78, 0x69, 0xfc, 0xe3,
- 0xd6, 0xcc, 0xc0, 0xde, 0x8a, 0xc8, 0xc1, 0xf6, 0x5c, 0xde, 0x40, 0x13, 0x87, 0xdd, 0xcd, 0xe7,
- 0x73, 0xc9, 0x99, 0x40, 0x44, 0xcd, 0x2a, 0xaf, 0xa8, 0x00, 0xd9, 0x4a, 0x7b, 0x34, 0x48, 0x8b,
- 0xb4, 0xb4, 0x14, 0x91, 0x68, 0x80, 0x18, 0x54, 0x80, 0xa8, 0x81, 0x93, 0x27, 0x1c, 0xcc, 0x11,
- 0x72, 0xcb, 0xca, 0x8a, 0x93, 0x76, 0xe8, 0x6a, 0x49, 0x44, 0xd6, 0xdb, 0xb6, 0x6d, 0xa9, 0x61,
- 0xe4, 0x93, 0x04, 0x9b, 0x43, 0x44, 0x16, 0x9c, 0x22, 0x11, 0xbf, 0x39, 0x3e, 0x2e, 0x02, 0x48,
- 0xc6, 0x7d, 0x6c, 0x6d, 0x6d, 0x19, 0x8c, 0x6a, 0xaa, 0x8d, 0x97, 0x9a, 0xef, 0x6f, 0x6c, 0x6c,
- 0x3c, 0xe6, 0x9a, 0x2a, 0x28, 0x0b, 0x14, 0x0d, 0x78, 0xa6, 0x88, 0xdc, 0x4a, 0x00, 0x61, 0x38,
- 0x90, 0xa0, 0xaa, 0xaa, 0x0a, 0x72, 0xf8, 0xec, 0xf3, 0xcf, 0xff, 0xf6, 0xb7, 0xbf, 0x7d, 0x08,
- 0x68, 0xc5, 0xc3, 0x09, 0xa0, 0x4b, 0x35, 0x35, 0x35, 0xe1, 0x49, 0xa1, 0x49, 0x62, 0x62, 0xe3,
- 0xc6, 0x1c, 0x80, 0xfd, 0x66, 0x53, 0x54, 0xa4, 0x3f, 0x7d, 0x1a, 0xc4, 0x19, 0x64, 0x89, 0x84,
- 0xc8, 0x49, 0x41, 0x4e, 0x4e, 0xb6, 0xf4, 0x00, 0x18, 0x69, 0x33, 0x30, 0x30, 0x40, 0x2c, 0x8f,
- 0xc2, 0x05, 0xb7, 0x8f, 0x26, 0x64, 0xb2, 0xaa, 0x2e, 0xe7, 0x70, 0x39, 0xd4, 0xc4, 0x46, 0x14,
- 0xcb, 0x4f, 0x52, 0xbb, 0xb7, 0x00, 0xa8, 0xf8, 0x1e, 0xb2, 0x3f, 0x26, 0x26, 0x66, 0xcc, 0xce,
- 0x62, 0x69, 0x9b, 0x3d, 0x7b, 0x76, 0x5c, 0x5c, 0x2c, 0x87, 0xc3, 0x16, 0x89, 0x04, 0xc3, 0xc3,
- 0xa2, 0x8b, 0x17, 0x2f, 0x4a, 0x3b, 0xfd, 0x98, 0xd8, 0x58, 0xf1, 0xf0, 0xc5, 0x07, 0x0f, 0x1e,
- 0x48, 0x77, 0x91, 0xa0, 0x98, 0x98, 0x2c, 0xd6, 0xf0, 0xab, 0x6d, 0xad, 0x08, 0x43, 0x0e, 0x1e,
- 0x24, 0xd6, 0x3a, 0x80, 0xca, 0x05, 0xed, 0x83, 0xc3, 0x41, 0xe0, 0x88, 0xdc, 0x6b, 0x6b, 0xeb,
- 0xaa, 0x6b, 0x6a, 0xdb, 0x3b, 0x3a, 0x47, 0x0f, 0xc0, 0xd8, 0xb4, 0x79, 0x73, 0x75, 0x4d, 0x0d,
- 0xb5, 0x4c, 0xe2, 0xdd, 0xbb, 0x77, 0x55, 0xd5, 0xd4, 0xc6, 0x6c, 0x82, 0x86, 0x03, 0x82, 0x66,
- 0xa8, 0xa9, 0xad, 0xcd, 0x48, 0x4b, 0xae, 0xc9, 0x08, 0x6f, 0xcf, 0x7d, 0xca, 0xac, 0x8c, 0x18,
- 0x6c, 0xcd, 0xe4, 0xf5, 0xd7, 0x0a, 0x79, 0xbd, 0x22, 0xd1, 0x10, 0x5e, 0x81, 0xcf, 0x17, 0xc4,
- 0xc7, 0x27, 0x00, 0x21, 0xd2, 0x2b, 0xc8, 0x7d, 0x42, 0xd4, 0x3e, 0x27, 0x84, 0x0c, 0x42, 0x61,
- 0xbf, 0x90, 0xdf, 0x41, 0xc4, 0x0b, 0x43, 0xd5, 0x22, 0x5e, 0x7d, 0x6b, 0x53, 0x09, 0xe0, 0xfa,
- 0xf9, 0xab, 0x55, 0x15, 0x97, 0xbb, 0xba, 0x9e, 0xe1, 0x71, 0x1a, 0x88, 0x71, 0xb3, 0x03, 0x09,
- 0x44, 0x1a, 0xcc, 0x19, 0xe6, 0x37, 0x3a, 0x39, 0xd9, 0x43, 0x62, 0xf9, 0xf8, 0xf8, 0x40, 0xd5,
- 0x88, 0x67, 0x07, 0x43, 0x53, 0x41, 0xb1, 0x8f, 0xf9, 0x8b, 0x94, 0xa1, 0x28, 0x41, 0xc8, 0x8c,
- 0xea, 0x6a, 0xc4, 0x44, 0xf7, 0xee, 0x79, 0xdb, 0xd9, 0xdb, 0x6b, 0x6a, 0x6a, 0xd1, 0x15, 0x15,
- 0x27, 0x4f, 0x9e, 0x0c, 0x8a, 0xf8, 0x90, 0x06, 0x2e, 0x6a, 0x14, 0x37, 0xe2, 0x44, 0x45, 0x45,
- 0xa5, 0x9d, 0xe4, 0x32, 0x86, 0x90, 0xfa, 0xfe, 0x0f, 0x1f, 0xbe, 0xd3, 0x4a, 0x38, 0x28, 0xf4,
- 0x95, 0x2b, 0x97, 0x67, 0x66, 0x24, 0x09, 0xf9, 0x3d, 0x22, 0x7e, 0x17, 0xd1, 0xd9, 0x27, 0x64,
- 0x07, 0x07, 0x3f, 0xfe, 0xd5, 0x2d, 0xa8, 0xf0, 0x5e, 0xae, 0x17, 0x5c, 0xe1, 0xd9, 0x41, 0x78,
- 0x12, 0xeb, 0x48, 0xe0, 0x9e, 0x2e, 0x2e, 0x2e, 0x23, 0x73, 0x1b, 0x05, 0xa0, 0x34, 0x2d, 0x2d,
- 0xc9, 0xf1, 0xab, 0xce, 0xce, 0xce, 0xd4, 0x6c, 0x32, 0xa1, 0x90, 0xe7, 0xe9, 0x79, 0x7d, 0xe2,
- 0xc4, 0x37, 0xad, 0x00, 0x4c, 0x68, 0x30, 0x35, 0xd5, 0xb2, 0xb2, 0x42, 0xa1, 0x60, 0x40, 0x28,
- 0x1c, 0x10, 0x09, 0x39, 0x90, 0x22, 0x08, 0x81, 0x25, 0xe4, 0x04, 0x90, 0xc3, 0xea, 0xeb, 0xe3,
- 0x70, 0x87, 0x06, 0xf1, 0x1f, 0x8f, 0x9f, 0x90, 0x90, 0x20, 0x4d, 0x23, 0xc0, 0x70, 0x51, 0x51,
- 0x11, 0x50, 0xcd, 0xe7, 0x0b, 0xe1, 0xd3, 0x89, 0xc4, 0xe3, 0x23, 0xae, 0x87, 0x5a, 0xc3, 0xa1,
- 0xb0, 0xf0, 0x70, 0x00, 0x35, 0x2b, 0x27, 0x37, 0x32, 0x32, 0x2a, 0x22, 0x22, 0x32, 0x29, 0x39,
- 0xa5, 0xa2, 0xb2, 0xaa, 0xba, 0xba, 0x46, 0xdc, 0x61, 0xb4, 0x71, 0xd3, 0xa6, 0x9a, 0xda, 0x3a,
- 0xdc, 0x1f, 0x1e, 0x04, 0x6f, 0x4d, 0x6d, 0x35, 0x32, 0xe6, 0x33, 0xe3, 0xd0, 0xc1, 0x43, 0x87,
- 0x5a, 0x5a, 0x5b, 0x19, 0xe5, 0xc5, 0xad, 0x25, 0x29, 0xdd, 0x65, 0x31, 0x7d, 0xb5, 0x09, 0x9c,
- 0x8e, 0x5c, 0xfe, 0x40, 0xbd, 0x90, 0xcf, 0x04, 0x14, 0x5b, 0x5a, 0x9a, 0x8f, 0x1e, 0x3d, 0x4a,
- 0xed, 0x52, 0x24, 0x71, 0x2d, 0x88, 0x0e, 0x21, 0x7a, 0x5b, 0x7b, 0xdb, 0xf0, 0x30, 0x5f, 0x24,
- 0x1c, 0x14, 0x0a, 0x98, 0x88, 0x6d, 0x87, 0x05, 0xdd, 0xac, 0xde, 0xa6, 0xbd, 0x7b, 0x77, 0x4b,
- 0xbb, 0x24, 0x3a, 0x9d, 0xf6, 0x3c, 0x21, 0x94, 0x58, 0x52, 0x63, 0x20, 0x51, 0xd0, 0xf7, 0x54,
- 0x40, 0xb4, 0x37, 0x26, 0x0a, 0x87, 0x18, 0x8c, 0xca, 0xbc, 0xd6, 0xd6, 0x46, 0xa1, 0x50, 0x48,
- 0xf6, 0x77, 0x13, 0x6d, 0xbc, 0xb9, 0x79, 0xf9, 0x08, 0xa8, 0x7f, 0x55, 0x86, 0x01, 0x99, 0xa0,
- 0xa3, 0x92, 0x92, 0x52, 0x20, 0xca, 0xeb, 0xde, 0x3d, 0x80, 0x76, 0xcb, 0xd6, 0xad, 0x8a, 0x24,
- 0x68, 0x3f, 0xfd, 0xec, 0xb3, 0xf7, 0x5e, 0x25, 0x86, 0x42, 0x2c, 0x42, 0xe9, 0x85, 0x0b, 0x17,
- 0xee, 0xde, 0xbd, 0xe7, 0xd2, 0xa5, 0xcb, 0xc9, 0x29, 0xa9, 0x08, 0x9f, 0xdf, 0x5e, 0x16, 0x02,
- 0x5a, 0x5a, 0x9a, 0xdb, 0x2a, 0xca, 0xb3, 0x89, 0x91, 0xed, 0xc4, 0xd2, 0x82, 0xe5, 0xa2, 0xa1,
- 0x9a, 0x81, 0xfe, 0xc6, 0xb3, 0x67, 0x7e, 0x7d, 0x43, 0x2b, 0xc4, 0x8f, 0x41, 0x41, 0x81, 0x40,
- 0x5d, 0x4b, 0x4b, 0x8b, 0x04, 0xc9, 0x00, 0xed, 0x25, 0xc5, 0xf9, 0xc8, 0x6a, 0x62, 0x22, 0x12,
- 0x32, 0x5c, 0xc8, 0x95, 0x93, 0x93, 0xec, 0x3b, 0x0b, 0x08, 0x78, 0x30, 0x2c, 0x64, 0x0b, 0x05,
- 0x2c, 0x91, 0x80, 0xc5, 0xe5, 0x30, 0xcd, 0xcd, 0x4c, 0x5e, 0xa7, 0x0d, 0x10, 0xd0, 0xe9, 0x68,
- 0x6b, 0x56, 0x56, 0xe4, 0x13, 0x93, 0x44, 0x88, 0xd6, 0x89, 0x16, 0x91, 0xa0, 0xbb, 0xad, 0xb5,
- 0x4e, 0x62, 0xb1, 0x23, 0x18, 0x9c, 0xcb, 0x00, 0x9b, 0x0d, 0x4d, 0xd8, 0xd5, 0xd5, 0xdd, 0xcb,
- 0x64, 0x15, 0x8e, 0xb5, 0x8c, 0x15, 0x14, 0x1d, 0xc2, 0x79, 0x90, 0x6a, 0x5d, 0x7d, 0x03, 0xd0,
- 0x58, 0x59, 0xc5, 0x80, 0xda, 0x04, 0x38, 0x01, 0x57, 0x5c, 0x9e, 0x96, 0x9e, 0x01, 0xd5, 0x1d,
- 0x9f, 0xf0, 0x1c, 0xfa, 0x0a, 0xa0, 0x85, 0xf0, 0x68, 0x68, 0x6c, 0xbc, 0x7e, 0xfd, 0x86, 0xf8,
- 0x72, 0x08, 0x80, 0xd4, 0xd4, 0xb4, 0xb3, 0x67, 0xcf, 0xbe, 0x0d, 0x2d, 0xa8, 0xa9, 0xa9, 0xe5,
- 0xe4, 0xe4, 0x76, 0xb5, 0x36, 0x31, 0x1b, 0x4a, 0xfb, 0x1a, 0x72, 0xd9, 0xad, 0xf9, 0x43, 0x4c,
- 0x86, 0x80, 0xd3, 0xd1, 0xd5, 0xd1, 0x14, 0x11, 0x11, 0xa6, 0xae, 0x3e, 0x46, 0x7b, 0x0e, 0x65,
- 0x0a, 0x0a, 0x0a, 0x29, 0xa9, 0xa9, 0x42, 0xb2, 0x6b, 0x80, 0x98, 0xbb, 0x44, 0xd4, 0xd0, 0x41,
- 0x16, 0xb3, 0xd3, 0xd1, 0x71, 0xec, 0xa5, 0x27, 0x36, 0x6d, 0xda, 0xd0, 0xdc, 0x88, 0x68, 0xab,
- 0x48, 0xd0, 0x1f, 0x41, 0x2c, 0xd1, 0xcf, 0xf4, 0x17, 0xf4, 0x47, 0x0a, 0xb9, 0x85, 0x44, 0x8e,
- 0xa1, 0x14, 0x44, 0x42, 0x90, 0x2b, 0x7b, 0x70, 0x30, 0x34, 0x34, 0x54, 0xbc, 0x79, 0xe8, 0xaf,
- 0x1a, 0x32, 0xc4, 0xc6, 0xc6, 0x06, 0x79, 0x88, 0x27, 0x41, 0x80, 0x76, 0xc4, 0xd2, 0x12, 0xce,
- 0x45, 0x81, 0x46, 0x9b, 0x30, 0x61, 0x22, 0x15, 0x85, 0xbd, 0x37, 0x62, 0x51, 0x49, 0xe9, 0x74,
- 0xc5, 0xed, 0xba, 0xba, 0xa0, 0xb5, 0x67, 0xa1, 0xa1, 0x86, 0x86, 0x07, 0x40, 0x08, 0x5f, 0x7e,
- 0xf5, 0xeb, 0x06, 0xfe, 0xd9, 0xbd, 0x7b, 0x7b, 0x73, 0x63, 0xe1, 0x30, 0xb7, 0x52, 0xc8, 0x4e,
- 0x23, 0xb7, 0x27, 0x88, 0xc6, 0x1f, 0xed, 0xcd, 0x99, 0xfb, 0xf4, 0x77, 0x7d, 0xf5, 0x95, 0xf8,
- 0x1e, 0x5f, 0x7e, 0x26, 0x69, 0xc4, 0x74, 0x0c, 0x75, 0x75, 0xb5, 0xec, 0xac, 0xe4, 0x61, 0xd1,
- 0xc0, 0x8d, 0x1b, 0x57, 0x25, 0x5e, 0x56, 0x59, 0x59, 0x49, 0xc0, 0xeb, 0x16, 0x22, 0x5e, 0xe0,
- 0xb5, 0x08, 0x05, 0xed, 0xed, 0x6d, 0x35, 0xd2, 0xeb, 0xf3, 0x64, 0x65, 0xc4, 0x91, 0x03, 0x08,
- 0x6b, 0x88, 0xc4, 0x6f, 0x6a, 0x6b, 0x29, 0xff, 0x7e, 0xc9, 0x18, 0x25, 0x88, 0xfa, 0x68, 0x66,
- 0x66, 0x5c, 0x5d, 0x99, 0x25, 0x1a, 0xaa, 0x26, 0x85, 0x5c, 0x86, 0x70, 0x30, 0x57, 0x34, 0xc4,
- 0x88, 0x8a, 0x0c, 0x98, 0x31, 0x43, 0xb2, 0x53, 0xcf, 0xc1, 0xce, 0xb6, 0xa3, 0xad, 0xb5, 0xaa,
- 0x8a, 0x81, 0x88, 0xaf, 0xb6, 0xae, 0x1e, 0xbe, 0x5b, 0x7a, 0x29, 0x6c, 0x54, 0x2e, 0x37, 0x37,
- 0x37, 0x60, 0x35, 0x27, 0x37, 0x0f, 0x09, 0xf8, 0x04, 0x62, 0xaf, 0x5c, 0x21, 0x5e, 0x01, 0x31,
- 0x20, 0xf4, 0x5b, 0x7e, 0x01, 0xb1, 0xd1, 0x76, 0x58, 0x58, 0x38, 0xb1, 0x47, 0x49, 0x51, 0x31,
- 0xe5, 0x43, 0xc5, 0x97, 0x23, 0xd3, 0xe0, 0x67, 0xdf, 0x52, 0x78, 0x43, 0x9a, 0x42, 0x1e, 0x33,
- 0xbb, 0x3b, 0x39, 0xcc, 0x76, 0x6e, 0x6f, 0x13, 0xaf, 0xaf, 0x69, 0x90, 0xd5, 0x92, 0x97, 0x9d,
- 0x76, 0xf4, 0xa8, 0xcd, 0x1b, 0xf6, 0x4e, 0xc2, 0x4f, 0x5c, 0xba, 0x74, 0x89, 0xcd, 0x1e, 0x14,
- 0x2f, 0xc4, 0x31, 0x3c, 0x2c, 0x60, 0x32, 0xbb, 0x3d, 0x3c, 0x24, 0x1b, 0x55, 0xc4, 0xb6, 0x6b,
- 0x97, 0x2e, 0x87, 0xdd, 0x08, 0x49, 0x20, 0xe8, 0x0f, 0x17, 0xf6, 0xfa, 0x12, 0x63, 0x68, 0xfb,
- 0x42, 0x09, 0xd1, 0xcb, 0x6b, 0x86, 0xa8, 0x10, 0x0d, 0x0b, 0x21, 0x84, 0xee, 0x7a, 0x79, 0x21,
- 0x78, 0x7c, 0xa7, 0x75, 0x3c, 0xf0, 0xa6, 0x20, 0x40, 0x30, 0x6d, 0x52, 0x72, 0xf2, 0xd5, 0x6b,
- 0xd7, 0x4c, 0xcd, 0xcc, 0xd6, 0xac, 0x59, 0xbb, 0x60, 0x81, 0x0c, 0x20, 0x47, 0xed, 0x50, 0xfc,
- 0xae, 0x4c, 0x4b, 0xe9, 0x58, 0xc0, 0x73, 0x81, 0x8c, 0xcc, 0xa6, 0x4d, 0x9b, 0x40, 0xdd, 0x3e,
- 0x3e, 0xbe, 0x17, 0x2f, 0x5d, 0x82, 0x68, 0x3c, 0x03, 0x51, 0x3b, 0x86, 0x9d, 0x3b, 0x77, 0xce,
- 0xf9, 0xfc, 0x79, 0x97, 0x0b, 0x6e, 0x6e, 0x37, 0xae, 0x5d, 0xf0, 0xf3, 0x76, 0x6b, 0xaa, 0x4b,
- 0x21, 0x66, 0x61, 0xf4, 0x85, 0x09, 0x7b, 0xbd, 0x89, 0xc1, 0xbd, 0x3d, 0x37, 0x50, 0x43, 0xfb,
- 0xda, 0xc3, 0xc3, 0x83, 0x2f, 0x7b, 0xdd, 0x3a, 0xe3, 0x75, 0xdb, 0xd9, 0xeb, 0xf6, 0xf9, 0xbb,
- 0xb7, 0x9c, 0x6f, 0x5c, 0x3d, 0x29, 0x91, 0xae, 0x5d, 0x76, 0x7a, 0x12, 0x70, 0xbd, 0xa7, 0xa3,
- 0x40, 0xc4, 0xab, 0x89, 0x8b, 0xf6, 0xf3, 0x70, 0x73, 0xa0, 0xd2, 0x45, 0x22, 0xd9, 0x87, 0x85,
- 0xdc, 0x14, 0x0e, 0x95, 0x12, 0x9a, 0x6a, 0x30, 0x57, 0xc8, 0x2d, 0xea, 0x6a, 0xcb, 0xbe, 0x7e,
- 0xc5, 0xc9, 0xc3, 0xcd, 0xf1, 0x22, 0x99, 0x3c, 0xdc, 0x8e, 0x79, 0x5c, 0xb0, 0xeb, 0x69, 0x4b,
- 0x27, 0x9a, 0xc4, 0xd9, 0x89, 0x02, 0xf6, 0x73, 0xe1, 0x60, 0x9a, 0x88, 0x5b, 0x9c, 0x91, 0x1c,
- 0x48, 0xde, 0xc4, 0x51, 0x9c, 0x70, 0xb2, 0xaf, 0xb7, 0x5b, 0x23, 0x1e, 0x92, 0x9b, 0x47, 0xf4,
- 0xe3, 0xb0, 0x02, 0x05, 0xcc, 0x07, 0x42, 0x56, 0x90, 0x70, 0x20, 0xae, 0x24, 0x2f, 0xd0, 0xf3,
- 0xea, 0x09, 0x0f, 0x57, 0x07, 0x77, 0x97, 0x63, 0xee, 0xe7, 0x1d, 0xdd, 0xce, 0x39, 0xba, 0x9e,
- 0x39, 0x96, 0x9d, 0x18, 0x5e, 0x5f, 0x96, 0x17, 0x1b, 0x17, 0x1f, 0x15, 0x1d, 0xf3, 0x3c, 0x31,
- 0x09, 0x1e, 0xf0, 0x84, 0x93, 0x13, 0x31, 0xe7, 0x96, 0x30, 0xbb, 0x17, 0xff, 0xb3, 0xb3, 0x87,
- 0x70, 0x02, 0xf5, 0x65, 0x66, 0x65, 0x01, 0x9c, 0x70, 0xf1, 0x4d, 0x4d, 0x4d, 0x88, 0x55, 0xc1,
- 0xbd, 0x40, 0x57, 0x6d, 0x5d, 0x5d, 0x46, 0x66, 0x16, 0x28, 0x17, 0x09, 0x0e, 0x0b, 0x0c, 0x9c,
- 0x9e, 0x91, 0xf9, 0xde, 0x2b, 0xc0, 0xa3, 0x58, 0xe1, 0x82, 0x5d, 0x5d, 0xce, 0x87, 0x85, 0x3c,
- 0x8d, 0x8d, 0x0a, 0xbf, 0xef, 0x7b, 0xd7, 0xde, 0xce, 0x66, 0x99, 0x86, 0xc6, 0x1b, 0x34, 0x24,
- 0xa8, 0x60, 0xe7, 0xae, 0x5d, 0x54, 0x03, 0x1d, 0xb5, 0x10, 0x07, 0xb5, 0xae, 0xec, 0x8d, 0x1b,
- 0x37, 0xa4, 0x57, 0xbc, 0x11, 0x9b, 0xae, 0xae, 0x76, 0x3f, 0xab, 0x41, 0xc4, 0x2d, 0x11, 0x0e,
- 0xc4, 0x10, 0xe3, 0xb5, 0x58, 0xfe, 0x44, 0x87, 0x17, 0x27, 0x17, 0x88, 0x85, 0x9b, 0x63, 0xb1,
- 0x7a, 0x9d, 0xcf, 0x3b, 0xcf, 0x91, 0x5a, 0xa7, 0xf4, 0x6d, 0x6c, 0xee, 0xdc, 0xb9, 0xb7, 0x6e,
- 0xdd, 0xaa, 0xac, 0xac, 0x8c, 0x88, 0x8c, 0x74, 0x73, 0x73, 0x37, 0x34, 0x34, 0x44, 0x84, 0x32,
- 0x67, 0xce, 0xdc, 0x71, 0xa4, 0x4c, 0x7a, 0x8f, 0x51, 0x31, 0xd4, 0x96, 0x07, 0xd3, 0x67, 0xcc,
- 0x58, 0xb2, 0x64, 0x89, 0x9e, 0x9e, 0xde, 0xa9, 0x53, 0xa7, 0x6f, 0xdf, 0xb9, 0x13, 0x10, 0x18,
- 0xf8, 0xf4, 0x69, 0x48, 0x48, 0xc8, 0x33, 0x29, 0x0b, 0x25, 0xd6, 0x31, 0x8b, 0x8d, 0x45, 0x59,
- 0x94, 0x15, 0x67, 0xb1, 0xbb, 0x62, 0x89, 0x7d, 0x5e, 0x7a, 0xee, 0x0a, 0xbb, 0x5c, 0x88, 0x49,
- 0x04, 0xad, 0x47, 0xf8, 0x6d, 0x56, 0x82, 0x76, 0x27, 0x02, 0xba, 0xcc, 0x47, 0xc4, 0x2e, 0x30,
- 0xfd, 0x51, 0xc0, 0xc9, 0xeb, 0x53, 0x14, 0xb9, 0x65, 0x4c, 0x04, 0xf1, 0xc7, 0x40, 0xcc, 0xcb,
- 0x2f, 0x07, 0x22, 0x05, 0xfd, 0xcf, 0x04, 0xac, 0x00, 0x21, 0xf2, 0x0d, 0xa9, 0x2f, 0x48, 0x88,
- 0x8a, 0x8f, 0x13, 0x80, 0x4c, 0x22, 0x25, 0x10, 0xa3, 0xe6, 0x70, 0x1a, 0xeb, 0x09, 0x41, 0x05,
- 0xbd, 0xb7, 0x89, 0xa9, 0xb8, 0xbd, 0xf7, 0x88, 0xc1, 0x8a, 0x7d, 0xb8, 0x55, 0xdc, 0xc8, 0x69,
- 0x89, 0x64, 0x4a, 0x20, 0x2e, 0xec, 0x0f, 0x11, 0xb2, 0x7c, 0x05, 0xdd, 0x1e, 0xc4, 0x40, 0xdc,
- 0x8e, 0x13, 0xc4, 0x04, 0xf3, 0xee, 0xab, 0x24, 0x74, 0x43, 0xf9, 0xcc, 0x98, 0xa1, 0xae, 0x78,
- 0x4e, 0xeb, 0xf3, 0x81, 0xc6, 0xe7, 0x4c, 0x46, 0x7c, 0x67, 0x51, 0x54, 0x51, 0x6c, 0xe0, 0xe5,
- 0xcb, 0x57, 0x2e, 0x5e, 0xba, 0x7c, 0xed, 0xfa, 0xf5, 0x7b, 0xde, 0xde, 0xc8, 0x8a, 0x60, 0x22,
- 0x2f, 0x5e, 0xbc, 0x7f, 0x08, 0x91, 0x42, 0xe1, 0x89, 0xc2, 0xc3, 0x23, 0xe0, 0xfa, 0x01, 0x69,
- 0x60, 0x03, 0x54, 0x8c, 0x72, 0x41, 0x68, 0xff, 0x24, 0x38, 0x18, 0x10, 0x4d, 0x4c, 0x4a, 0xc6,
- 0x51, 0xd0, 0x6c, 0x56, 0x76, 0x4e, 0x63, 0x53, 0x33, 0x6a, 0xf9, 0xdb, 0xef, 0x2a, 0x2b, 0x6d,
- 0x54, 0xa0, 0x41, 0x6c, 0xb5, 0x20, 0x2b, 0x0b, 0xa7, 0xf0, 0xab, 0xad, 0x8e, 0xf3, 0xe6, 0xcd,
- 0x43, 0x19, 0x51, 0xc1, 0x23, 0xd5, 0x4e, 0x0b, 0xb8, 0x22, 0xbe, 0xc3, 0xf7, 0x6f, 0xa0, 0xc7,
- 0xa5, 0x4b, 0xbf, 0x2f, 0x2c, 0x48, 0x23, 0x06, 0x7b, 0x70, 0xb2, 0xc8, 0xb2, 0x88, 0x12, 0x0e,
- 0xa6, 0x0a, 0x87, 0x2a, 0xa0, 0x7e, 0x07, 0xd9, 0x2c, 0x0b, 0x0b, 0x8b, 0x31, 0xfb, 0x37, 0xdf,
- 0xd2, 0xbe, 0xfb, 0xee, 0xbb, 0x00, 0x62, 0x8b, 0xd8, 0xd2, 0xa0, 0x27, 0x4f, 0x4e, 0x9f, 0x39,
- 0xb3, 0x67, 0xcf, 0x1e, 0x75, 0xf5, 0x25, 0x33, 0x66, 0xce, 0x7c, 0xbf, 0xf6, 0x2e, 0x6a, 0x2c,
- 0x37, 0x58, 0x1a, 0x79, 0x02, 0xf0, 0xeb, 0xee, 0xd8, 0x01, 0xd7, 0x66, 0x65, 0x65, 0x0d, 0x2a,
- 0x01, 0xe5, 0xda, 0x3b, 0x38, 0x8c, 0x4e, 0x0e, 0xc7, 0x8e, 0x1d, 0x3f, 0x71, 0xe2, 0xcc, 0xd9,
- 0x73, 0x97, 0x2f, 0x5f, 0xbd, 0xff, 0xe0, 0x41, 0x5d, 0xfe, 0x15, 0x7e, 0xeb, 0x09, 0x02, 0xa8,
- 0xcd, 0x06, 0x82, 0x46, 0x6d, 0x62, 0x35, 0xf8, 0x86, 0xad, 0xe4, 0x52, 0x6f, 0xa6, 0x82, 0x36,
- 0x7b, 0x7e, 0xfb, 0x49, 0x41, 0xc7, 0x59, 0x02, 0x1e, 0x9d, 0xe7, 0xde, 0x3a, 0x51, 0xe7, 0x9f,
- 0xe2, 0x03, 0xf6, 0xed, 0xf6, 0x82, 0x76, 0x3b, 0x41, 0x87, 0x83, 0xa0, 0xf3, 0xb8, 0xa0, 0xeb,
- 0x14, 0xbf, 0xfb, 0x3c, 0xbf, 0xdb, 0x8d, 0x18, 0xe5, 0xd5, 0x7d, 0x91, 0xdf, 0xed, 0x2e, 0x40,
- 0x1d, 0xe9, 0x3c, 0xcd, 0x6f, 0x77, 0x20, 0xa7, 0x34, 0x5a, 0xf3, 0x89, 0x33, 0x7f, 0xe2, 0x77,
- 0x9e, 0xe7, 0x77, 0xb9, 0x93, 0xe7, 0x5c, 0x7a, 0x91, 0xba, 0xdc, 0xf9, 0x5d, 0xce, 0x82, 0x0e,
- 0x27, 0x01, 0xce, 0x69, 0x39, 0xc0, 0x6f, 0xda, 0x25, 0x20, 0xd7, 0x4e, 0x14, 0xb4, 0x98, 0xf0,
- 0xdb, 0x8e, 0xf2, 0xda, 0x4e, 0x72, 0x1a, 0x5d, 0x06, 0x18, 0xee, 0xcc, 0x92, 0x8b, 0x5d, 0xb9,
- 0x97, 0x5a, 0x93, 0x2e, 0xd6, 0x45, 0xb8, 0xa5, 0x78, 0x9d, 0x34, 0xdc, 0x6f, 0x68, 0x60, 0xb0,
- 0xff, 0x80, 0x91, 0x91, 0x99, 0x99, 0x99, 0x95, 0x95, 0x15, 0x28, 0x96, 0xca, 0x0a, 0x22, 0x03,
- 0x1c, 0x1d, 0xe1, 0x80, 0x5c, 0x5d, 0x2f, 0xdc, 0xbe, 0x73, 0x17, 0x30, 0xce, 0xce, 0xce, 0x81,
- 0x24, 0x40, 0x45, 0x06, 0x19, 0xc2, 0xf5, 0x67, 0xe7, 0xe4, 0x14, 0x97, 0x94, 0xc6, 0xc5, 0x27,
- 0x10, 0x78, 0x26, 0x25, 0x41, 0x5d, 0x5d, 0xfd, 0xda, 0xb5, 0x6b, 0x3f, 0xee, 0x8a, 0x58, 0x6f,
- 0x30, 0x3c, 0x06, 0x7c, 0x25, 0x04, 0xa7, 0x18, 0xae, 0x5c, 0xee, 0xd0, 0xcd, 0x9b, 0x37, 0x41,
- 0xf2, 0x6f, 0x7e, 0x06, 0xa8, 0x85, 0xcb, 0x97, 0xdc, 0xf9, 0x43, 0x9d, 0xc4, 0x96, 0xf7, 0x9c,
- 0x22, 0xb2, 0x3d, 0xb6, 0x4a, 0xc4, 0xef, 0x68, 0x6f, 0xab, 0xd7, 0xdf, 0xab, 0xf7, 0xae, 0x1b,
- 0x65, 0x4a, 0xdb, 0xac, 0x59, 0xb3, 0xd2, 0xd3, 0xd3, 0x73, 0x73, 0xf3, 0xee, 0x3f, 0xf0, 0x3f,
- 0x7e, 0xfc, 0x04, 0x24, 0xa8, 0x8a, 0x8a, 0x0a, 0xd1, 0xde, 0x45, 0x46, 0x61, 0xef, 0x04, 0x5a,
- 0x6a, 0x24, 0x0c, 0x5c, 0x09, 0x40, 0x8b, 0xdb, 0x42, 0x57, 0x2f, 0x56, 0x57, 0xd7, 0x58, 0xb6,
- 0x6c, 0xc5, 0x8a, 0x95, 0x23, 0xfd, 0x4d, 0x2f, 0xd3, 0xaa, 0x55, 0xab, 0xa1, 0x43, 0x36, 0x6f,
- 0xde, 0xb2, 0x6b, 0xd7, 0x6e, 0x0b, 0x8b, 0xc3, 0x2e, 0xe7, 0x5d, 0x8a, 0xc2, 0x4c, 0xfb, 0x8b,
- 0x36, 0x71, 0xca, 0x96, 0x71, 0xcb, 0xd4, 0x38, 0x65, 0xca, 0x9c, 0x32, 0x15, 0x4e, 0xb9, 0x06,
- 0xb7, 0x62, 0x1d, 0xb7, 0x72, 0x1b, 0xa7, 0x4a, 0x67, 0xb0, 0x6a, 0xc7, 0x60, 0xe5, 0xce, 0xc1,
- 0x2a, 0x32, 0x31, 0x76, 0x72, 0xab, 0x77, 0x10, 0xa9, 0x46, 0x97, 0x5b, 0xab, 0x3b, 0x54, 0xbb,
- 0x1d, 0x89, 0x57, 0xa7, 0xc3, 0xab, 0xd7, 0xe1, 0x37, 0x68, 0x8f, 0x4a, 0x5a, 0xfc, 0x06, 0x4d,
- 0x72, 0x27, 0xc4, 0x8d, 0xc4, 0xea, 0xd0, 0xf5, 0xeb, 0xf9, 0x0d, 0x1b, 0xf9, 0x8d, 0xdb, 0xf8,
- 0x4d, 0xda, 0xc4, 0x42, 0x9d, 0xcd, 0xbb, 0xf8, 0xcd, 0x7b, 0xc8, 0x6d, 0x13, 0x77, 0xf3, 0xf0,
- 0xb1, 0x91, 0xdc, 0x72, 0x11, 0xa9, 0x51, 0x93, 0xf8, 0x48, 0x1c, 0xd2, 0xe7, 0x37, 0xef, 0x27,
- 0xd3, 0x3e, 0x9c, 0x26, 0x68, 0xde, 0xc9, 0x6f, 0xda, 0xce, 0x6b, 0xdc, 0xc2, 0x27, 0x76, 0x5c,
- 0xd2, 0xe0, 0xd7, 0xa8, 0xf1, 0xab, 0x55, 0xf8, 0x35, 0x4b, 0xf8, 0xb5, 0xab, 0x86, 0x6a, 0x37,
- 0x0e, 0x32, 0xb4, 0xfb, 0x4b, 0x76, 0x33, 0xb3, 0xf5, 0x3b, 0x92, 0xf6, 0x37, 0x47, 0x1a, 0x56,
- 0x07, 0x1a, 0x16, 0xdf, 0xd9, 0x1f, 0x7e, 0x72, 0xe7, 0xd2, 0x25, 0x6a, 0xca, 0x8b, 0x16, 0xa9,
- 0xa8, 0xaa, 0xaa, 0x2f, 0x59, 0x42, 0x66, 0xc5, 0x0a, 0xea, 0xdd, 0x57, 0xaf, 0xfe, 0x61, 0xfd,
- 0xfa, 0x0d, 0xda, 0xda, 0x3a, 0x87, 0x4c, 0x4c, 0xce, 0x39, 0x3b, 0x3f, 0x7c, 0xf8, 0x28, 0x2b,
- 0x3b, 0xbb, 0xad, 0xbd, 0x63, 0xdf, 0x3e, 0x03, 0x84, 0x12, 0xe6, 0xe6, 0xe6, 0x60, 0x54, 0xb0,
- 0x6e, 0x6c, 0x6c, 0x5c, 0x54, 0x54, 0x34, 0xc2, 0x2b, 0x46, 0x75, 0x35, 0x58, 0xe5, 0x5d, 0x77,
- 0xf2, 0xfd, 0x10, 0x03, 0x00, 0x6c, 0x5f, 0x8c, 0xcb, 0x25, 0x26, 0x19, 0xf5, 0xf4, 0xf4, 0x22,
- 0xf6, 0xf9, 0xd5, 0x7e, 0x1c, 0xca, 0xf0, 0x9c, 0xc1, 0x4f, 0x02, 0xd8, 0xec, 0xce, 0x61, 0x41,
- 0xb7, 0x80, 0xd7, 0xc9, 0xec, 0x69, 0x8a, 0x8a, 0x0c, 0x5d, 0xbc, 0x58, 0xed, 0xbd, 0x27, 0xf0,
- 0x4a, 0x18, 0x34, 0xf0, 0xf3, 0xe7, 0x89, 0xf0, 0x3b, 0x0f, 0x08, 0xd0, 0x1e, 0xd7, 0xd1, 0xd1,
- 0x51, 0x52, 0x52, 0x9a, 0x3c, 0x79, 0xca, 0xa7, 0x9f, 0xbe, 0x33, 0x68, 0x71, 0x32, 0xd4, 0x2c,
- 0xde, 0xeb, 0x5f, 0xff, 0xfa, 0xe2, 0x9b, 0x6f, 0xbf, 0xc5, 0x4d, 0xa6, 0x4d, 0x9b, 0x3e, 0xb2,
- 0xe1, 0xfc, 0x4c, 0x89, 0x34, 0x7b, 0xf6, 0x6c, 0xb0, 0x31, 0x7e, 0x0b, 0x80, 0xde, 0xb9, 0x73,
- 0x97, 0xbd, 0x8d, 0x75, 0xac, 0x87, 0x56, 0x85, 0xdf, 0xf2, 0xa6, 0x27, 0x2a, 0xad, 0xa1, 0xca,
- 0xed, 0x11, 0x0b, 0x3b, 0xa2, 0x54, 0x3b, 0x63, 0x97, 0x74, 0xc6, 0x6b, 0x74, 0x25, 0xae, 0xe8,
- 0x4a, 0x5a, 0xd9, 0x9d, 0xbc, 0xb2, 0x27, 0x65, 0x65, 0x4f, 0xea, 0xca, 0xde, 0xb4, 0x95, 0xcc,
- 0x8c, 0x15, 0xac, 0xac, 0x15, 0x7d, 0xd9, 0xcb, 0xfb, 0x73, 0x97, 0xf5, 0xe7, 0x2d, 0x1b, 0xc8,
- 0x5f, 0x3a, 0x50, 0xf8, 0x3d, 0xbb, 0x78, 0x09, 0xa7, 0x54, 0x9d, 0x5b, 0xbe, 0x98, 0x5b, 0xa1,
- 0x36, 0x54, 0xa9, 0xc2, 0x63, 0x2c, 0xe2, 0x31, 0x94, 0x79, 0x0c, 0x25, 0x72, 0xc9, 0x47, 0x05,
- 0x1e, 0x83, 0x46, 0xfe, 0xa1, 0xc4, 0xaf, 0x5e, 0xc8, 0xaf, 0x51, 0xe6, 0xd7, 0xa8, 0xf2, 0x6b,
- 0xd5, 0xf8, 0x75, 0x6a, 0x3c, 0xa4, 0x5a, 0xfc, 0xab, 0xc2, 0xab, 0x55, 0x46, 0xe2, 0xd7, 0xaa,
- 0xf2, 0xea, 0xd4, 0x79, 0x75, 0x1a, 0xfc, 0xba, 0x65, 0xc4, 0x56, 0xa1, 0x75, 0x4b, 0xc9, 0xa4,
- 0x8e, 0xef, 0x89, 0x6d, 0x6d, 0xab, 0x15, 0x79, 0x0c, 0x79, 0x3e, 0x31, 0xb4, 0x78, 0x1e, 0xaf,
- 0x72, 0x2e, 0xaf, 0x6a, 0xfe, 0x50, 0xb9, 0x02, 0xa7, 0x44, 0x79, 0xa0, 0x60, 0x31, 0x33, 0x6b,
- 0x59, 0x57, 0xe2, 0xea, 0x96, 0xb0, 0x1f, 0xea, 0x1e, 0xad, 0x2d, 0xbf, 0xbd, 0x3e, 0xd7, 0x75,
- 0x5d, 0xa0, 0xd9, 0xf2, 0x79, 0x33, 0xa6, 0x4c, 0x80, 0x17, 0x9c, 0x34, 0x09, 0x24, 0x30, 0x92,
- 0x15, 0xc4, 0x06, 0x70, 0x70, 0xfd, 0xf2, 0x0a, 0x0a, 0xcb, 0x96, 0x2d, 0xdb, 0xb3, 0x47, 0xef,
- 0xe4, 0xc9, 0x53, 0x8f, 0x02, 0x02, 0xa0, 0x63, 0x1b, 0x1a, 0x1b, 0x71, 0x08, 0x67, 0x42, 0x28,
- 0x42, 0x21, 0xa0, 0x44, 0xc0, 0xb1, 0x10, 0x0c, 0x79, 0xf9, 0x05, 0x0d, 0x8d, 0x4d, 0xa0, 0xe6,
- 0x0f, 0x91, 0x04, 0xef, 0x6a, 0x28, 0xc4, 0x0d, 0x1b, 0x36, 0x24, 0xa7, 0xa4, 0xe4, 0xe4, 0xe4,
- 0x84, 0x85, 0x47, 0x48, 0xef, 0xe9, 0xf0, 0x66, 0x83, 0xfb, 0xbe, 0x70, 0xc1, 0x25, 0x3e, 0x2e,
- 0x3a, 0xe4, 0x69, 0x90, 0xa9, 0xc9, 0xa1, 0x29, 0x53, 0x3e, 0x68, 0xb9, 0x6f, 0x09, 0x43, 0xa5,
- 0x5e, 0xb3, 0x76, 0x6d, 0xc2, 0xf3, 0x44, 0xe8, 0x7c, 0x6f, 0x1f, 0x1f, 0x44, 0x07, 0xa0, 0x3e,
- 0x1a, 0x8d, 0x86, 0x7c, 0x16, 0xef, 0xe0, 0xfc, 0x4e, 0x4c, 0x0b, 0x0d, 0x0c, 0xdc, 0xa2, 0x42,
- 0xe1, 0xce, 0xff, 0x24, 0xed, 0xd3, 0xd7, 0x18, 0x8a, 0x00, 0xca, 0x0a, 0xc5, 0xb4, 0x70, 0xe1,
- 0xc2, 0xf5, 0xeb, 0xd7, 0x1f, 0x32, 0xdc, 0x77, 0xc3, 0x46, 0x27, 0xec, 0xd4, 0xfa, 0x0c, 0x67,
- 0xb5, 0x02, 0x77, 0xa5, 0xb2, 0xab, 0x4a, 0x95, 0xb7, 0x94, 0x19, 0xf7, 0x16, 0xd5, 0xf8, 0xaa,
- 0xd4, 0x3e, 0x50, 0xa9, 0xf3, 0x57, 0x69, 0x08, 0x50, 0x69, 0x7c, 0xbc, 0xa8, 0xe9, 0xc9, 0xa2,
- 0x96, 0x10, 0xe5, 0xd6, 0x67, 0xca, 0x6d, 0xe1, 0xca, 0xed, 0x51, 0x0b, 0x3b, 0x62, 0x94, 0xba,
- 0xe2, 0x14, 0xbb, 0x9f, 0xd3, 0x7b, 0x92, 0x69, 0xcc, 0x34, 0x79, 0x56, 0x86, 0x5c, 0x5f, 0xb6,
- 0x6c, 0x7f, 0xce, 0x02, 0x76, 0xfe, 0xfc, 0xc1, 0xc2, 0x79, 0x9c, 0xe2, 0x39, 0xdc, 0xd2, 0x59,
- 0x43, 0xe5, 0x33, 0x78, 0x15, 0x33, 0xf8, 0x95, 0x54, 0x9a, 0xf9, 0x22, 0x55, 0x21, 0xcd, 0x42,
- 0x22, 0x37, 0xf9, 0x9d, 0x45, 0xee, 0xa5, 0x3e, 0x8b, 0x57, 0x3d, 0x9b, 0x57, 0x3d, 0x97, 0x5f,
- 0x3d, 0x8f, 0x5f, 0xfd, 0x1d, 0xf1, 0x2f, 0x63, 0x2e, 0x99, 0x66, 0x13, 0x27, 0x57, 0x52, 0x1b,
- 0x85, 0x4f, 0xe7, 0x55, 0x4e, 0xe5, 0x55, 0x4c, 0x1e, 0x2a, 0x9f, 0xc2, 0x29, 0x99, 0xce, 0x2e,
- 0x98, 0xd3, 0x9f, 0x3d, 0x9f, 0x95, 0x2a, 0xd7, 0x95, 0x40, 0xc7, 0xf3, 0x34, 0x04, 0x2e, 0x62,
- 0xdc, 0x53, 0x29, 0xbe, 0xac, 0x96, 0x71, 0x72, 0xb1, 0x9f, 0x81, 0xe2, 0x37, 0x5f, 0x7c, 0xfa,
- 0x7f, 0x49, 0xfb, 0xfb, 0xdf, 0xff, 0x41, 0xe5, 0x03, 0xb8, 0x4b, 0xfc, 0xd6, 0x10, 0xfc, 0x7b,
- 0xf5, 0xf5, 0x11, 0x7e, 0x86, 0x86, 0x86, 0x41, 0xb5, 0x3e, 0xf0, 0xf7, 0x27, 0x17, 0xaf, 0x50,
- 0x48, 0x4a, 0x4a, 0xaa, 0xad, 0xab, 0xcf, 0xce, 0xc9, 0x4d, 0x4a, 0x4e, 0x41, 0xb4, 0x55, 0x59,
- 0x55, 0x55, 0x58, 0x54, 0x04, 0x1f, 0xfd, 0x11, 0x0b, 0xfd, 0x6d, 0x0c, 0x0f, 0x03, 0x56, 0xc1,
- 0xf3, 0x8c, 0x1f, 0x3f, 0xfe, 0x3d, 0xd4, 0x08, 0xd5, 0x76, 0xf4, 0x86, 0xc8, 0xee, 0x43, 0x0c,
- 0xb7, 0xdd, 0xb5, 0x6b, 0x57, 0x4a, 0x6a, 0x2a, 0xd2, 0xcd, 0x5b, 0xb7, 0xcc, 0x2d, 0x2c, 0xe0,
- 0xb3, 0xc0, 0xbd, 0x13, 0x26, 0x4c, 0x78, 0xbf, 0x71, 0x32, 0x38, 0x1f, 0x7c, 0xfb, 0xbf, 0x49,
- 0xfb, 0x3f, 0xaf, 0x37, 0x54, 0x07, 0x94, 0x26, 0xb4, 0x0d, 0x78, 0x08, 0x7c, 0xbb, 0x74, 0xa9,
- 0x86, 0xb6, 0x96, 0xd6, 0x91, 0x03, 0x7a, 0xae, 0x47, 0x76, 0xf9, 0x38, 0x6c, 0x8f, 0x3a, 0xb6,
- 0x2a, 0xc5, 0x61, 0x61, 0xba, 0x93, 0x52, 0xf6, 0x19, 0xa5, 0x3c, 0x17, 0xa5, 0x42, 0x77, 0xc5,
- 0x92, 0xcb, 0x8a, 0x65, 0x57, 0xe9, 0xe5, 0x37, 0xe8, 0x95, 0xb7, 0x69, 0x55, 0x77, 0xe9, 0xd5,
- 0xde, 0xb4, 0x1a, 0x3f, 0x5a, 0x9d, 0xbf, 0x42, 0xc3, 0x23, 0xf9, 0xa6, 0xc7, 0xf2, 0xcd, 0x4f,
- 0xe5, 0x5b, 0x43, 0xe5, 0xda, 0xc2, 0x65, 0x3b, 0xa2, 0x65, 0xba, 0xe2, 0xe6, 0x77, 0x3f, 0xff,
- 0xae, 0x37, 0x79, 0x2e, 0x2b, 0x7d, 0x76, 0x7f, 0xe6, 0x4c, 0x76, 0xee, 0xf4, 0xc1, 0xc2, 0xa9,
- 0x9c, 0x92, 0x29, 0x43, 0xa5, 0x93, 0x86, 0xca, 0x27, 0xf2, 0x5e, 0x49, 0x13, 0xc8, 0xbd, 0xfc,
- 0x26, 0x8c, 0x24, 0x72, 0x5f, 0xbf, 0x8a, 0x49, 0xa3, 0x12, 0xf9, 0x8d, 0xf8, 0x64, 0x72, 0x9f,
- 0x94, 0xa1, 0xb2, 0x09, 0x9c, 0xe2, 0x49, 0x03, 0xb9, 0xd3, 0xfa, 0x32, 0x66, 0xf6, 0x26, 0xcd,
- 0xe9, 0x8a, 0x9d, 0xdf, 0x1a, 0x26, 0xd7, 0xf8, 0x58, 0xa1, 0xd6, 0x57, 0xa1, 0xdc, 0x93, 0x5e,
- 0xe0, 0xaa, 0x98, 0xea, 0xa8, 0xe4, 0xb5, 0x5b, 0xf6, 0x9f, 0xff, 0x43, 0x38, 0x29, 0x2a, 0x2b,
- 0xa8, 0xf7, 0xfd, 0x84, 0x6c, 0xcf, 0x87, 0x03, 0x5a, 0xb0, 0x60, 0x01, 0xf4, 0xea, 0x11, 0x4b,
- 0xcb, 0xdb, 0xb7, 0xef, 0xa4, 0xa4, 0xa6, 0x01, 0xa2, 0xdb, 0xb6, 0x6d, 0x03, 0xb3, 0xfd, 0xb0,
- 0x66, 0x4d, 0x53, 0x53, 0x73, 0x75, 0x4d, 0x2d, 0xa8, 0x15, 0x1c, 0x52, 0x50, 0x58, 0x04, 0x85,
- 0xf0, 0xf8, 0xf1, 0xe3, 0xdf, 0x53, 0x12, 0xfc, 0x29, 0x0c, 0x82, 0xd9, 0xc4, 0xc4, 0x04, 0xf5,
- 0x3a, 0x2e, 0x3e, 0xfe, 0xd2, 0xa5, 0xcb, 0xd0, 0x57, 0xd0, 0xf9, 0x32, 0xa3, 0x36, 0x53, 0x78,
- 0x27, 0xc4, 0x4a, 0xa0, 0xf7, 0x0d, 0x86, 0xd2, 0x44, 0x39, 0x82, 0x8d, 0xbf, 0xfc, 0xf2, 0x4b,
- 0xb8, 0x4c, 0x70, 0x3b, 0xa2, 0x36, 0x94, 0x9d, 0xa1, 0xbe, 0x9e, 0xbd, 0xa9, 0x81, 0xab, 0xed,
- 0x81, 0xbb, 0x8e, 0xfa, 0xc1, 0x76, 0x1b, 0xa3, 0xad, 0xd4, 0x12, 0xac, 0xe8, 0xc9, 0xf6, 0xf4,
- 0xf4, 0x13, 0xf4, 0xac, 0x53, 0xb4, 0x9c, 0x73, 0xb4, 0x7c, 0x17, 0x5a, 0x91, 0xbb, 0x42, 0xc9,
- 0x25, 0x85, 0xb2, 0xab, 0x0a, 0xe5, 0x37, 0xe4, 0x2b, 0x6f, 0xc9, 0x31, 0xee, 0xca, 0xd5, 0xf8,
- 0xc8, 0xd5, 0xf9, 0xc9, 0x36, 0xf8, 0xcb, 0x36, 0x06, 0xca, 0x36, 0x07, 0xcb, 0xb4, 0x86, 0x2e,
- 0x68, 0x8b, 0x9c, 0xdf, 0x19, 0x3b, 0xaf, 0x27, 0x71, 0x0e, 0x2b, 0x75, 0x66, 0x7f, 0xe6, 0xf4,
- 0x81, 0xdc, 0xa9, 0x83, 0x85, 0x93, 0xb9, 0x25, 0x93, 0x86, 0xca, 0xbe, 0x7d, 0xb9, 0xb1, 0xd4,
- 0x6b, 0xd3, 0xb7, 0xaf, 0xa6, 0x17, 0xdf, 0x0f, 0x95, 0x7e, 0xcb, 0x29, 0x02, 0x5c, 0xa7, 0xb2,
- 0xd2, 0xa7, 0xf7, 0x24, 0xce, 0xea, 0x8c, 0xfe, 0xae, 0xed, 0x99, 0x4c, 0x63, 0xa0, 0x5c, 0xad,
- 0x9f, 0x6c, 0xd5, 0x1d, 0xb9, 0x92, 0xcb, 0x0a, 0xb9, 0xe7, 0x68, 0x49, 0x76, 0xf4, 0x5b, 0xdb,
- 0xe7, 0xff, 0xd7, 0xa8, 0x9a, 0x4e, 0x4d, 0xdb, 0x44, 0x0d, 0xc5, 0x9b, 0x82, 0xbb, 0xbe, 0xff,
- 0xfe, 0xfb, 0x7d, 0x06, 0x06, 0x17, 0xdc, 0xdc, 0x11, 0x8f, 0x57, 0x54, 0x56, 0x45, 0x44, 0x46,
- 0xce, 0x99, 0x33, 0x07, 0x0c, 0x7c, 0xe4, 0x88, 0x65, 0x57, 0x77, 0x37, 0x10, 0x5b, 0x54, 0x5c,
- 0x02, 0xb8, 0x32, 0xaa, 0x6b, 0x80, 0x58, 0xa7, 0x9f, 0x7e, 0xfa, 0xad, 0x37, 0x44, 0xfe, 0x33,
- 0x1a, 0x38, 0xdc, 0xf1, 0xf8, 0x71, 0x72, 0x3b, 0xcb, 0x08, 0x77, 0x77, 0x0f, 0x23, 0x23, 0x63,
- 0xc4, 0x08, 0x10, 0x24, 0x54, 0x5b, 0xf1, 0x6f, 0xb7, 0x3b, 0x98, 0x58, 0x48, 0xa0, 0xbc, 0x50,
- 0x41, 0xa6, 0x4f, 0x9f, 0x2e, 0x23, 0x23, 0x83, 0x00, 0x10, 0xf1, 0x89, 0xa6, 0xa6, 0xe6, 0xbe,
- 0xbd, 0x7a, 0x16, 0x87, 0x0e, 0x38, 0x58, 0x99, 0xb9, 0x38, 0x98, 0x7b, 0xd9, 0xeb, 0x05, 0x5b,
- 0xad, 0x89, 0x30, 0x57, 0x8d, 0x39, 0xa2, 0x94, 0x60, 0xa3, 0x94, 0x64, 0xa7, 0x98, 0xee, 0x48,
- 0xcf, 0xfa, 0x89, 0x96, 0x7b, 0x86, 0x96, 0xef, 0xac, 0x50, 0x70, 0x41, 0xa1, 0xc8, 0x43, 0xa1,
- 0xf4, 0x8a, 0x7c, 0xc5, 0x75, 0xf9, 0xca, 0x9b, 0x72, 0x0c, 0x2f, 0xd9, 0x5a, 0x1f, 0xd9, 0xba,
- 0x07, 0x2f, 0xd0, 0xdb, 0x16, 0x36, 0x1f, 0xd0, 0xea, 0x4e, 0x98, 0xcd, 0x24, 0xa1, 0xcb, 0xce,
- 0x9b, 0xca, 0x29, 0x9c, 0x34, 0x54, 0x32, 0x81, 0x57, 0xf6, 0xab, 0xb8, 0x7d, 0x99, 0x80, 0x73,
- 0x6e, 0xc9, 0x04, 0x02, 0xae, 0x39, 0xd3, 0xfa, 0xd2, 0x66, 0xf4, 0x26, 0xcc, 0xe9, 0x88, 0xfa,
- 0xae, 0xe5, 0xa9, 0x4c, 0xc3, 0x23, 0xfc, 0x96, 0x4c, 0xe5, 0x6d, 0x39, 0xfc, 0x7a, 0xa1, 0xab,
- 0x42, 0xd6, 0x4f, 0xf4, 0x04, 0x2b, 0x9a, 0xf3, 0xc6, 0xd9, 0xa3, 0x5f, 0x93, 0xea, 0x64, 0x19,
- 0x37, 0x6e, 0x1c, 0xa5, 0x07, 0x10, 0x72, 0x9e, 0x3e, 0x7d, 0x26, 0x28, 0xe8, 0x49, 0x7e, 0x7e,
- 0x41, 0x53, 0x73, 0x8b, 0x91, 0xf1, 0x41, 0x6a, 0xb3, 0xe3, 0xfb, 0x0f, 0x1e, 0x00, 0xb1, 0x75,
- 0xf5, 0xf5, 0x54, 0x2f, 0x58, 0x4b, 0x4b, 0x6b, 0x61, 0x61, 0xa1, 0xf4, 0x50, 0xc6, 0xbf, 0x8c,
- 0x32, 0xe4, 0x27, 0x54, 0x41, 0x59, 0x59, 0x39, 0x94, 0x95, 0x8b, 0xeb, 0x05, 0x03, 0x83, 0xfd,
- 0x88, 0x0e, 0x40, 0x08, 0x94, 0xe6, 0xff, 0x4d, 0x41, 0x8b, 0x9b, 0x83, 0x82, 0xa8, 0x55, 0xa1,
- 0xf0, 0x18, 0x10, 0x24, 0xa0, 0x5c, 0xb8, 0x4e, 0x48, 0x5c, 0xd0, 0xd1, 0x0f, 0x3f, 0xfc, 0xb0,
- 0x75, 0xeb, 0xd6, 0x1d, 0x3b, 0x76, 0x1a, 0x1a, 0x1e, 0x38, 0x6c, 0x61, 0x71, 0xd2, 0xc6, 0xe2,
- 0xaa, 0xad, 0x81, 0xaf, 0xe5, 0xd6, 0xc7, 0xe6, 0xcb, 0x9e, 0x1d, 0x5e, 0x12, 0x65, 0xb5, 0x38,
- 0xde, 0x46, 0x39, 0xe9, 0xa8, 0x62, 0x9a, 0x03, 0x2d, 0xc3, 0x89, 0x96, 0x7d, 0x8a, 0x60, 0xb9,
- 0xfc, 0x0b, 0xb4, 0xa2, 0x8b, 0x0a, 0xa5, 0x57, 0xe5, 0x2b, 0x3d, 0x49, 0xf4, 0xfa, 0xca, 0xd6,
- 0x3f, 0x94, 0x6d, 0x0a, 0x22, 0xa0, 0xdb, 0x11, 0x3d, 0xaf, 0x27, 0x61, 0x0e, 0x2b, 0x65, 0x66,
- 0x1f, 0x58, 0x37, 0x67, 0xda, 0x60, 0xc1, 0x64, 0x6e, 0xd1, 0x24, 0x6e, 0xc9, 0x44, 0x6e, 0xe9,
- 0x04, 0xf0, 0x27, 0x91, 0xca, 0x5e, 0x4d, 0x25, 0x13, 0x70, 0x88, 0x5b, 0x3c, 0x11, 0x58, 0x65,
- 0xe7, 0x4d, 0xe9, 0xcb, 0x9e, 0x0e, 0xd8, 0xf7, 0xc4, 0xcf, 0x6d, 0x8f, 0x9c, 0xdf, 0xfc, 0x44,
- 0x06, 0xb7, 0xad, 0xf1, 0x96, 0xad, 0xb8, 0x29, 0x07, 0xc2, 0x07, 0xf3, 0xc3, 0x05, 0x24, 0xdb,
- 0xd1, 0x63, 0xcc, 0x68, 0xdb, 0xe4, 0xbf, 0x16, 0x63, 0x15, 0x4e, 0x04, 0x95, 0x11, 0x2c, 0xaa,
- 0xac, 0xac, 0xbc, 0x69, 0xd3, 0x66, 0xe8, 0xae, 0xcb, 0x57, 0xae, 0x44, 0x46, 0x46, 0x95, 0x95,
- 0x57, 0xb4, 0xb7, 0x77, 0xf8, 0xfb, 0x3f, 0xa4, 0x9c, 0xfe, 0xb4, 0x69, 0xd3, 0x18, 0x8c, 0x6a,
- 0x16, 0xab, 0xaf, 0xb3, 0xab, 0xbb, 0xa3, 0xb3, 0xb3, 0xbb, 0xa7, 0xa7, 0xbf, 0x7f, 0x20, 0x2c,
- 0x2c, 0x4c, 0x7a, 0xc5, 0xef, 0xbf, 0x4c, 0x6c, 0x60, 0xd4, 0xc0, 0xc7, 0x8f, 0x8b, 0x8b, 0x4b,
- 0x42, 0x9e, 0x85, 0x3a, 0x3b, 0x9f, 0x47, 0x68, 0x00, 0x42, 0x00, 0x78, 0x00, 0x5a, 0xc0, 0xe9,
- 0x63, 0xad, 0xd8, 0xf9, 0x06, 0xdc, 0x8a, 0x03, 0x37, 0x70, 0xce, 0xb8, 0x71, 0x5f, 0x7e, 0xf3,
- 0xcd, 0xb7, 0x08, 0x9f, 0xc1, 0x4b, 0x40, 0x2f, 0x9d, 0x4e, 0x57, 0x53, 0x53, 0x5b, 0xb1, 0x62,
- 0xe5, 0xc6, 0x8d, 0x9b, 0x74, 0x74, 0x74, 0xf6, 0xee, 0xdd, 0x6b, 0x6a, 0x62, 0xe2, 0x68, 0x69,
- 0xea, 0x66, 0x6d, 0x70, 0xcb, 0x52, 0xc7, 0xf7, 0xf0, 0xc6, 0x40, 0xab, 0x35, 0xe1, 0xd6, 0xcb,
- 0x62, 0xad, 0x55, 0x13, 0x6d, 0x14, 0x01, 0x9b, 0xb4, 0xe3, 0x40, 0x2f, 0x2d, 0xcf, 0x99, 0x56,
- 0xe4, 0xa6, 0x50, 0x7a, 0x59, 0xbe, 0xc2, 0x53, 0x9e, 0x71, 0x57, 0x16, 0xbe, 0xbb, 0x21, 0x40,
- 0xb6, 0x25, 0x58, 0xa6, 0x3d, 0x7c, 0x7e, 0x67, 0xcc, 0xbc, 0xee, 0x84, 0x39, 0xcc, 0x94, 0x99,
- 0xac, 0xf4, 0x19, 0x7d, 0x59, 0x04, 0x7a, 0x07, 0xf2, 0xa6, 0x02, 0x93, 0x83, 0xf9, 0x53, 0xd8,
- 0xa3, 0x53, 0xde, 0x14, 0xe2, 0xfb, 0xdc, 0x69, 0xfd, 0xd9, 0xd3, 0xfa, 0xd2, 0x67, 0x30, 0x53,
- 0x66, 0x75, 0xc5, 0xcd, 0xc5, 0xe5, 0x4d, 0x80, 0xeb, 0x03, 0xd9, 0xea, 0x7b, 0xb2, 0xb8, 0x73,
- 0x31, 0xe0, 0x7a, 0x9e, 0x06, 0x76, 0xc5, 0xef, 0xc6, 0x1d, 0xa6, 0xdd, 0xd6, 0x9d, 0x3f, 0xee,
- 0xef, 0xff, 0x8d, 0x3a, 0x08, 0xa0, 0xca, 0xc9, 0xc9, 0x81, 0x24, 0x8d, 0x8c, 0x8c, 0x8e, 0x1f,
- 0x3f, 0xee, 0xe6, 0xe6, 0x7e, 0xcf, 0xdb, 0x07, 0x5e, 0x2c, 0x3b, 0x27, 0xa7, 0xbe, 0xa1, 0xb1,
- 0xbb, 0xbb, 0x27, 0x39, 0x39, 0x45, 0x3c, 0x3b, 0x5e, 0x5d, 0x5d, 0x9d, 0x3d, 0xc8, 0xe9, 0x65,
- 0x32, 0x01, 0x57, 0xa4, 0x9e, 0x9e, 0x5e, 0x40, 0x57, 0x7a, 0xd9, 0xba, 0xbf, 0x4c, 0xc2, 0x64,
- 0x65, 0x65, 0x83, 0x83, 0x83, 0xf3, 0x0b, 0x0a, 0x03, 0x03, 0x1f, 0xff, 0x74, 0xf2, 0xe4, 0x8e,
- 0x1d, 0x3b, 0xe0, 0xa3, 0xe1, 0xac, 0xff, 0x45, 0x82, 0xf6, 0x77, 0xd8, 0x3c, 0x54, 0x4c, 0xb9,
- 0x80, 0x2e, 0x7e, 0x11, 0x04, 0x85, 0xe8, 0x0c, 0xc4, 0x0b, 0xaa, 0x99, 0x34, 0x69, 0x12, 0xaa,
- 0x0f, 0xb4, 0x0a, 0x62, 0xd8, 0x45, 0x8b, 0x16, 0x69, 0x68, 0x68, 0x40, 0x6f, 0xff, 0xf8, 0xe3,
- 0x8f, 0xbb, 0x77, 0xef, 0x01, 0x24, 0x6c, 0xcc, 0x0f, 0x9d, 0xb5, 0x34, 0xbc, 0x6c, 0xb9, 0xeb,
- 0x8e, 0xb5, 0xf6, 0x43, 0xdb, 0xad, 0xa1, 0xd6, 0x2b, 0xe3, 0x2c, 0x95, 0x13, 0x6d, 0xe8, 0x69,
- 0xc7, 0x80, 0x25, 0x5a, 0xde, 0x39, 0x5a, 0xa1, 0x1b, 0x21, 0x1b, 0xa0, 0x19, 0xaa, 0xbd, 0xe4,
- 0xea, 0xee, 0xcb, 0x36, 0x06, 0xc8, 0x34, 0x53, 0xd0, 0x8d, 0x9e, 0xd7, 0x1d, 0x3f, 0xa7, 0x27,
- 0x71, 0x76, 0x6f, 0xf2, 0x2c, 0x02, 0xc0, 0xa9, 0x33, 0x59, 0x69, 0x33, 0x88, 0x94, 0x8e, 0x7f,
- 0xc9, 0x8f, 0x48, 0x29, 0x33, 0x99, 0x49, 0xb3, 0x7a, 0x9e, 0x23, 0xce, 0x9a, 0x07, 0xa2, 0x06,
- 0x5d, 0x43, 0x72, 0x80, 0xbd, 0xa1, 0xa2, 0x8b, 0x2f, 0x2a, 0xa0, 0x5e, 0x64, 0x3a, 0xd1, 0x93,
- 0x6c, 0xe9, 0xb1, 0xe6, 0xb4, 0xeb, 0xda, 0xdf, 0x2d, 0x99, 0x35, 0x0e, 0x39, 0x86, 0xca, 0xbe,
- 0x7d, 0xbb, 0x2e, 0x02, 0x84, 0x43, 0x87, 0x0e, 0xe1, 0xf1, 0x0e, 0x1f, 0x3e, 0x02, 0x25, 0x70,
- 0xf7, 0xae, 0x57, 0x4c, 0x6c, 0x1c, 0xd8, 0x15, 0x7e, 0xff, 0xe6, 0xcd, 0x9b, 0x10, 0x3f, 0xe2,
- 0x91, 0x8a, 0x96, 0x96, 0x96, 0x03, 0x6c, 0x36, 0x50, 0xda, 0xd6, 0x06, 0xea, 0xed, 0xe8, 0xed,
- 0x65, 0xd6, 0xd4, 0xd6, 0xbd, 0xcd, 0x60, 0xcb, 0xff, 0x70, 0x43, 0xa8, 0x85, 0xf0, 0x27, 0x2a,
- 0x2a, 0x2a, 0x3b, 0x3b, 0xc7, 0xcf, 0xef, 0xbe, 0xc3, 0xb1, 0x63, 0x5a, 0x5a, 0xda, 0x2f, 0x40,
- 0xfb, 0x91, 0x86, 0x7f, 0xbf, 0x25, 0x6e, 0xc5, 0xac, 0x4b, 0xa1, 0x97, 0x7a, 0x36, 0xaa, 0x59,
- 0x0c, 0x92, 0x0f, 0xca, 0x61, 0xea, 0xd4, 0xa9, 0x70, 0xb5, 0x32, 0x32, 0xb2, 0x4a, 0x4a, 0x4a,
- 0x20, 0xa8, 0x55, 0xab, 0x56, 0x6d, 0xde, 0xbc, 0x59, 0x57, 0x57, 0x77, 0xbf, 0xc1, 0x3e, 0x4b,
- 0x13, 0xa3, 0x93, 0x87, 0xf7, 0x7b, 0x58, 0xeb, 0x7b, 0xdb, 0xed, 0x0c, 0xb1, 0x5e, 0x13, 0x7b,
- 0x58, 0xf9, 0xb9, 0x35, 0x3d, 0x15, 0xd0, 0x3d, 0x49, 0x2f, 0x38, 0xaf, 0x50, 0xec, 0x21, 0x5f,
- 0x76, 0x95, 0x88, 0xd7, 0xaa, 0xbd, 0xe5, 0xea, 0x09, 0xad, 0x2b, 0x43, 0x45, 0x6a, 0xed, 0x11,
- 0xf3, 0xdb, 0xa3, 0xbe, 0x83, 0xe2, 0xed, 0x8a, 0x9d, 0x0b, 0x64, 0x8a, 0x13, 0xc2, 0x37, 0x10,
- 0x32, 0x54, 0x6b, 0x5b, 0xf8, 0xfc, 0x96, 0x10, 0xc4, 0x59, 0x32, 0x08, 0xf1, 0x10, 0xeb, 0x95,
- 0x5d, 0x97, 0x47, 0x00, 0x88, 0xba, 0x90, 0x71, 0x9c, 0x86, 0xaa, 0x11, 0x65, 0x4a, 0x73, 0xd7,
- 0x92, 0xd1, 0x5d, 0xa1, 0xb4, 0x61, 0xdd, 0xda, 0x9d, 0x3b, 0x77, 0xea, 0xeb, 0xeb, 0x6b, 0x6b,
- 0xeb, 0xac, 0x5f, 0xbf, 0x01, 0xd5, 0x0a, 0xaa, 0xc6, 0xd8, 0xf8, 0x20, 0xdc, 0x16, 0x5c, 0x58,
- 0x5e, 0x5e, 0x7e, 0x46, 0x66, 0x26, 0xa4, 0xec, 0x94, 0x29, 0xaf, 0x8c, 0x13, 0x08, 0x0c, 0x0c,
- 0xec, 0xeb, 0xef, 0xef, 0xe8, 0xec, 0x6a, 0x05, 0x64, 0x3b, 0x3a, 0x21, 0x0f, 0x22, 0x22, 0x22,
- 0x3f, 0xfd, 0xf4, 0x7d, 0x26, 0x71, 0xfc, 0xa7, 0x19, 0x38, 0x4d, 0x53, 0x4b, 0x2b, 0x31, 0x31,
- 0x29, 0x3d, 0x3d, 0xc3, 0xeb, 0xde, 0x3d, 0xdb, 0xa3, 0x47, 0xf1, 0x51, 0x79, 0xd1, 0x22, 0x20,
- 0x04, 0x87, 0x7e, 0xd3, 0xad, 0xeb, 0xde, 0x06, 0xc0, 0xe2, 0x3d, 0xf5, 0xc4, 0xf4, 0x0b, 0xe7,
- 0x3b, 0x79, 0xf2, 0x64, 0x31, 0xfd, 0xaa, 0xaa, 0xaa, 0xae, 0x58, 0xb1, 0x02, 0xbe, 0x18, 0xe8,
- 0x3d, 0x68, 0xb8, 0xdf, 0xde, 0xdc, 0xc8, 0xd5, 0xf6, 0xa0, 0xb7, 0x83, 0x5e, 0xa8, 0xe5, 0xf2,
- 0x38, 0x0b, 0x7a, 0xd2, 0x51, 0x7a, 0xfa, 0x71, 0x5a, 0xce, 0x19, 0x5a, 0x81, 0x0b, 0x0d, 0xf4,
- 0x08, 0xd4, 0x21, 0xc6, 0xaf, 0xf1, 0x26, 0x58, 0xb7, 0xe1, 0x91, 0x4c, 0x43, 0x20, 0x21, 0x77,
- 0x01, 0x60, 0xa9, 0x84, 0xef, 0x89, 0x38, 0xae, 0xfe, 0xa1, 0x0c, 0x54, 0x31, 0x2e, 0x01, 0xe6,
- 0xa1, 0x37, 0x72, 0xcf, 0xd2, 0xd2, 0x8f, 0x23, 0xd4, 0xa2, 0x47, 0x99, 0x2d, 0x0c, 0xb0, 0xfd,
- 0xf1, 0x94, 0xb5, 0xa9, 0xe1, 0x7e, 0x83, 0xdd, 0xbb, 0x77, 0x6f, 0xd8, 0xb0, 0x11, 0x0a, 0x5c,
- 0x51, 0x51, 0x51, 0x5e, 0x5e, 0x01, 0x59, 0x87, 0x87, 0x01, 0xc7, 0x7a, 0xde, 0xbc, 0x09, 0x19,
- 0x90, 0x97, 0x9f, 0xaf, 0xa5, 0xad, 0x2d, 0xb1, 0x3e, 0x06, 0xde, 0xa5, 0xae, 0xae, 0x9e, 0xc9,
- 0xea, 0x03, 0x62, 0xc1, 0xb0, 0x5d, 0xdd, 0x3d, 0x03, 0xec, 0xc1, 0x43, 0x87, 0x4c, 0x5e, 0x53,
- 0x44, 0x7f, 0x99, 0xa4, 0x81, 0x4e, 0xf7, 0xef, 0xdf, 0x8f, 0x48, 0x36, 0x39, 0x25, 0xf5, 0xf6,
- 0xed, 0x3b, 0x36, 0x36, 0xb6, 0xdb, 0xb6, 0xfd, 0xa8, 0xa8, 0xa8, 0x04, 0x60, 0xfc, 0xe1, 0x3b,
- 0xde, 0xfe, 0xaf, 0x11, 0xe5, 0x40, 0x89, 0x07, 0x00, 0x18, 0xe8, 0x05, 0xfd, 0xe2, 0xc1, 0xf0,
- 0xd8, 0x5f, 0x7d, 0x35, 0x9e, 0x1a, 0x89, 0x37, 0x77, 0xee, 0x5c, 0xa0, 0x77, 0xf1, 0xe2, 0xc5,
- 0x10, 0x8a, 0x9a, 0x9a, 0x9a, 0x06, 0xfa, 0xfa, 0x56, 0x16, 0xa6, 0x17, 0xec, 0x4d, 0xfd, 0xad,
- 0xb7, 0x86, 0x99, 0xab, 0xc5, 0x5a, 0x2e, 0x4c, 0xb2, 0x53, 0xcc, 0x38, 0x41, 0x03, 0xe4, 0x0a,
- 0x2f, 0x90, 0x0d, 0x65, 0xd7, 0xe4, 0x2a, 0x6e, 0xca, 0x33, 0xee, 0x80, 0x78, 0x89, 0x60, 0xaa,
- 0xd6, 0x87, 0x10, 0xbd, 0xe0, 0xd2, 0x5a, 0x3f, 0x99, 0xda, 0xfb, 0xe4, 0x1f, 0x3e, 0x32, 0x35,
- 0xde, 0x32, 0x55, 0x77, 0xe5, 0xca, 0x3d, 0xe5, 0x21, 0x8c, 0x0b, 0x5c, 0x09, 0xd8, 0xa7, 0x1d,
- 0x23, 0xe0, 0x1a, 0x69, 0xb6, 0xc8, 0xc7, 0x76, 0x87, 0x83, 0xad, 0x95, 0x9e, 0x9e, 0x1e, 0x18,
- 0x15, 0x8a, 0x05, 0xbf, 0x8e, 0x0a, 0x3e, 0x69, 0x12, 0xea, 0xd1, 0x4c, 0xc4, 0x8f, 0x20, 0x5b,
- 0x48, 0x82, 0x90, 0x90, 0x67, 0xa5, 0xa5, 0x65, 0xb6, 0xb6, 0xb6, 0xd2, 0x2b, 0xf9, 0x00, 0xdb,
- 0x88, 0xb3, 0xfa, 0x07, 0xd8, 0xbd, 0x4c, 0x56, 0x4f, 0x2f, 0xb3, 0xaf, 0xaf, 0x9f, 0xd5, 0xd7,
- 0xf7, 0x21, 0xe3, 0x46, 0xfe, 0x03, 0x0d, 0x00, 0xb0, 0xb3, 0xb3, 0xaf, 0xac, 0x62, 0x24, 0x25,
- 0x25, 0xdf, 0xba, 0x75, 0xdb, 0xca, 0xca, 0x9a, 0xea, 0x0e, 0xfb, 0xf6, 0xdb, 0x6f, 0x01, 0x8f,
- 0x3f, 0x1c, 0xb4, 0xa3, 0x6d, 0x34, 0x80, 0xc5, 0xea, 0xf7, 0xb3, 0xcf, 0x3e, 0x43, 0x20, 0x89,
- 0x42, 0x07, 0xf7, 0x52, 0x2d, 0x66, 0x2b, 0x57, 0xae, 0x44, 0xbd, 0x33, 0x30, 0x30, 0x38, 0x7a,
- 0xc4, 0xec, 0x8a, 0xcd, 0x5e, 0xff, 0xc3, 0x6b, 0x9f, 0x1d, 0xd1, 0x88, 0xb7, 0x56, 0x46, 0xb8,
- 0x94, 0xe1, 0x04, 0xf8, 0x21, 0x7a, 0x52, 0x28, 0x24, 0x9a, 0x79, 0xe5, 0xcb, 0xae, 0xc8, 0x97,
- 0x5d, 0x93, 0x2f, 0xbf, 0x2e, 0x0f, 0x99, 0x8a, 0xc0, 0x8a, 0x4a, 0xf8, 0x08, 0x5e, 0x2d, 0xbd,
- 0x44, 0x50, 0x6b, 0xbe, 0x33, 0x04, 0x06, 0x2d, 0xc5, 0x9e, 0x1e, 0x7f, 0x84, 0x16, 0x66, 0xa6,
- 0x7a, 0xd3, 0x66, 0x8f, 0xa9, 0xa9, 0x09, 0xf2, 0x07, 0xbf, 0x02, 0xac, 0xa2, 0xca, 0xa0, 0xee,
- 0x50, 0x02, 0x66, 0xfa, 0x74, 0x62, 0x3c, 0xdb, 0x01, 0x23, 0x23, 0xe4, 0x61, 0x66, 0x66, 0x56,
- 0x78, 0x78, 0xf8, 0x98, 0x93, 0xd9, 0xf7, 0xed, 0xdb, 0xc7, 0xe1, 0x70, 0x07, 0x39, 0x5c, 0x62,
- 0x79, 0x57, 0x36, 0x31, 0x77, 0x21, 0x68, 0xac, 0x35, 0xc9, 0xff, 0xb2, 0x37, 0x1b, 0xca, 0xdd,
- 0xc3, 0xc3, 0x83, 0x51, 0x5d, 0x9d, 0x98, 0x94, 0xe4, 0xe9, 0xe9, 0x69, 0x41, 0x74, 0x87, 0xad,
- 0x9f, 0x3f, 0x7f, 0x3e, 0x90, 0x40, 0x8d, 0xa4, 0xfd, 0xa3, 0xa1, 0x3a, 0x86, 0x49, 0xa0, 0x17,
- 0x95, 0x0b, 0xd0, 0x05, 0xa7, 0x01, 0xba, 0x33, 0x67, 0xce, 0x44, 0xe4, 0xae, 0xa6, 0xb6, 0x78,
- 0xcd, 0x9a, 0xb5, 0x88, 0x89, 0x0e, 0x19, 0x1b, 0x9f, 0xb4, 0x3c, 0x78, 0xeb, 0x88, 0x76, 0x80,
- 0xe5, 0xfa, 0x48, 0xeb, 0xa5, 0x09, 0xd6, 0x4a, 0x80, 0x6e, 0x3a, 0xd9, 0xc2, 0x00, 0xe2, 0x45,
- 0xec, 0x5f, 0xe0, 0xa2, 0x50, 0xe0, 0xaa, 0x00, 0x06, 0x16, 0xa7, 0x7c, 0x17, 0x22, 0x82, 0xcb,
- 0x39, 0x4d, 0x4b, 0x3f, 0x41, 0xa8, 0x8b, 0x58, 0x0b, 0x7a, 0x88, 0xc5, 0xd2, 0xeb, 0x36, 0x7a,
- 0x46, 0x07, 0x0c, 0xd7, 0xac, 0x59, 0x03, 0x4a, 0x9f, 0x32, 0x65, 0x0a, 0x50, 0x8a, 0x1f, 0xa5,
- 0xa4, 0x0b, 0x70, 0x3b, 0x87, 0xdc, 0xea, 0xd4, 0xc6, 0xd6, 0x36, 0x28, 0xe8, 0x49, 0x41, 0x61,
- 0x91, 0xa3, 0xe3, 0xf1, 0x31, 0xfb, 0x2e, 0x2f, 0x5e, 0xbc, 0x48, 0x2d, 0xfe, 0xcc, 0x25, 0x37,
- 0xf7, 0xe4, 0x0e, 0x0d, 0x49, 0xaf, 0xed, 0xf9, 0x97, 0xbd, 0x8d, 0x81, 0x2e, 0xbc, 0xbc, 0xbc,
- 0x10, 0xda, 0x46, 0x45, 0x47, 0xbb, 0x7b, 0x5c, 0x3c, 0x70, 0xc0, 0xe8, 0xfb, 0xa5, 0x4b, 0xc1,
- 0x5a, 0xc8, 0xf6, 0x3f, 0x44, 0xd0, 0xbe, 0x93, 0x8d, 0x6e, 0x76, 0x20, 0x5b, 0xcc, 0x08, 0xd6,
- 0x85, 0xb0, 0x01, 0x0d, 0xd2, 0xe9, 0xf4, 0xa5, 0x4b, 0x97, 0x6e, 0xda, 0xb4, 0x69, 0xaf, 0x9e,
- 0x9e, 0xb5, 0xa9, 0xb1, 0xab, 0xe5, 0xbe, 0x3b, 0x36, 0xba, 0x41, 0xb6, 0x1b, 0xa2, 0x0f, 0xab,
- 0x24, 0x58, 0x12, 0x51, 0x7f, 0x8a, 0x03, 0x3d, 0xcd, 0x91, 0x0e, 0xd9, 0x90, 0xe9, 0x44, 0xcb,
- 0xfc, 0x89, 0x4e, 0xa5, 0x8c, 0x13, 0x74, 0xc8, 0x00, 0x00, 0x1b, 0xe7, 0x44, 0x9b, 0x29, 0x3e,
- 0xb6, 0x58, 0xe5, 0x66, 0xa5, 0x7f, 0xc0, 0x40, 0x1f, 0xec, 0xbd, 0x60, 0xc1, 0x02, 0xe4, 0x15,
- 0x15, 0x28, 0x51, 0xa3, 0xe2, 0xc9, 0x95, 0x1e, 0xc7, 0x81, 0xde, 0x11, 0x76, 0x9d, 0x3c, 0x79,
- 0x2a, 0x3a, 0x26, 0x36, 0x2e, 0x2e, 0x7e, 0xcc, 0x45, 0xc6, 0x60, 0xd1, 0xd1, 0xd1, 0x00, 0x2a,
- 0xa8, 0x15, 0x09, 0xb8, 0xad, 0xaa, 0x62, 0x48, 0x4f, 0xc1, 0xfe, 0xcb, 0xde, 0xc6, 0xe0, 0x61,
- 0xc1, 0x4b, 0x0f, 0x1f, 0x3e, 0x2c, 0x2c, 0x2a, 0x86, 0x9f, 0x42, 0xce, 0x23, 0x0a, 0xa3, 0xd1,
- 0xe9, 0xd0, 0x06, 0xff, 0xb6, 0x34, 0x2b, 0x6d, 0x62, 0xe8, 0x7e, 0x42, 0x3a, 0x0e, 0x54, 0x37,
- 0x04, 0x6b, 0xd0, 0xba, 0x40, 0x05, 0x34, 0xe7, 0xaa, 0x55, 0xab, 0xb4, 0xb4, 0xb4, 0x0e, 0xec,
- 0x37, 0x70, 0xb0, 0x30, 0x76, 0xb3, 0x36, 0xf4, 0xb1, 0xdf, 0xf5, 0xd4, 0x7a, 0x5d, 0xa4, 0xb9,
- 0x4a, 0x8c, 0x19, 0xd1, 0xb8, 0x1a, 0x6f, 0x29, 0x4e, 0xd0, 0x00, 0xe0, 0x55, 0x5a, 0xb4, 0x29,
- 0x3d, 0xd4, 0x6c, 0xb1, 0x97, 0x95, 0xf6, 0x09, 0x73, 0x83, 0xdd, 0x3b, 0x77, 0x2c, 0x5f, 0xbe,
- 0x7c, 0xde, 0xbc, 0x79, 0x5f, 0x7f, 0xfd, 0xf5, 0x3f, 0xfe, 0xf1, 0x4f, 0xf1, 0x80, 0xb7, 0x91,
- 0x79, 0x19, 0x5f, 0xc9, 0xc9, 0x13, 0x9b, 0xf3, 0x9e, 0x3b, 0xe7, 0x9c, 0xf0, 0xfc, 0xf9, 0xed,
- 0x3b, 0x77, 0xc6, 0xec, 0x0e, 0x00, 0x2d, 0xe7, 0xe4, 0xe6, 0xf6, 0x0f, 0x0c, 0x40, 0xc4, 0x22,
- 0xf8, 0x1a, 0x20, 0x86, 0xfa, 0x7b, 0xfe, 0xd5, 0x71, 0xf0, 0xde, 0x86, 0x22, 0x06, 0x1d, 0x3d,
- 0x09, 0x0e, 0x4e, 0x4d, 0x4d, 0xbb, 0x79, 0xeb, 0x96, 0x91, 0x91, 0xd1, 0xf7, 0xdf, 0x2f, 0x9d,
- 0x3e, 0x7d, 0xfa, 0x47, 0x59, 0xb0, 0xeb, 0x77, 0x36, 0xf1, 0x60, 0x06, 0x71, 0xff, 0x1a, 0xd4,
- 0xc2, 0xac, 0x59, 0xb3, 0xe4, 0xe5, 0xe5, 0xd5, 0xd5, 0xd5, 0xd7, 0xad, 0x5b, 0xa7, 0xbb, 0x5d,
- 0xf7, 0xe0, 0x81, 0xfd, 0x76, 0x16, 0x07, 0xcf, 0xda, 0x98, 0x5c, 0xb3, 0x3b, 0xe0, 0x6b, 0xb7,
- 0xeb, 0xb1, 0xcd, 0xe6, 0x10, 0x8b, 0x15, 0xa1, 0x16, 0x1a, 0xa1, 0x16, 0xcb, 0x42, 0x8e, 0xac,
- 0x0e, 0xb0, 0xd9, 0x7a, 0xcb, 0x4e, 0xdf, 0xe9, 0x88, 0x91, 0xf1, 0x7e, 0xfd, 0x2d, 0x5b, 0xb6,
- 0xa8, 0xaa, 0xaa, 0xc1, 0xef, 0x83, 0xba, 0x25, 0xb4, 0xbd, 0x78, 0x26, 0x91, 0xac, 0xac, 0x2c,
- 0xb9, 0x25, 0xc4, 0xa9, 0xe0, 0xa7, 0x21, 0xe6, 0xe6, 0xe6, 0xe3, 0xc7, 0x8f, 0x97, 0x9e, 0xe9,
- 0x86, 0xe8, 0x20, 0x27, 0x37, 0xaf, 0xb1, 0xa9, 0xa9, 0xba, 0xa6, 0xb6, 0xa6, 0xb6, 0xae, 0xbe,
- 0xbe, 0x01, 0x92, 0x00, 0x75, 0xea, 0x2d, 0x26, 0xc9, 0xbd, 0xd6, 0x50, 0x2b, 0x3f, 0xd6, 0x90,
- 0xd4, 0x3f, 0xa3, 0xa1, 0x70, 0x21, 0xc6, 0x1e, 0x3f, 0x0e, 0xba, 0x7f, 0xff, 0x81, 0xc5, 0xe1,
- 0xc3, 0x2b, 0x57, 0xae, 0x9a, 0x3d, 0x7b, 0x36, 0x25, 0x0c, 0xfe, 0x58, 0x04, 0xbe, 0xb7, 0x89,
- 0x1b, 0xca, 0x00, 0x5d, 0x54, 0x3d, 0x4a, 0xe8, 0x02, 0xba, 0xa4, 0xd0, 0x55, 0x83, 0xef, 0x26,
- 0x7a, 0xd6, 0xb4, 0x75, 0xf4, 0xf6, 0xec, 0x3e, 0x60, 0xb8, 0xdf, 0xe4, 0xa0, 0xb1, 0xb9, 0xe9,
- 0x21, 0x73, 0x93, 0x43, 0x26, 0x07, 0x8d, 0x0c, 0x0d, 0xf6, 0xed, 0xd0, 0xd5, 0x85, 0x9e, 0x5f,
- 0xbc, 0x78, 0x31, 0x94, 0x00, 0x34, 0x06, 0xf2, 0x81, 0xea, 0x10, 0x94, 0xd0, 0x48, 0xd4, 0x62,
- 0x8f, 0x73, 0xe7, 0xcd, 0xfb, 0xe1, 0x87, 0x35, 0x87, 0x8f, 0x1c, 0xb9, 0x77, 0xcf, 0x3b, 0x2e,
- 0x3e, 0x3e, 0x2b, 0x2b, 0x3b, 0xbf, 0xa0, 0xb0, 0xb0, 0xa8, 0x08, 0x3e, 0x8b, 0x48, 0x85, 0x45,
- 0x05, 0x05, 0x85, 0x79, 0x79, 0xf9, 0x59, 0xd9, 0x39, 0xf1, 0x09, 0xcf, 0xa3, 0xa0, 0xbd, 0x62,
- 0x62, 0x93, 0x93, 0x53, 0x10, 0xa3, 0xe1, 0x4b, 0x1c, 0x7d, 0x71, 0xda, 0xfb, 0xa4, 0x22, 0xc8,
- 0x66, 0x89, 0x84, 0x2f, 0x8b, 0x8a, 0x8a, 0x8b, 0x8a, 0x4b, 0x88, 0xcd, 0xf3, 0xca, 0xca, 0xc9,
- 0x7e, 0x0c, 0x08, 0x90, 0xea, 0xea, 0xea, 0x1a, 0xd4, 0x14, 0xd4, 0x95, 0xba, 0xfa, 0x06, 0xa4,
- 0xfa, 0x86, 0x17, 0x89, 0xf8, 0x58, 0x57, 0x5f, 0x43, 0xae, 0x96, 0x80, 0xb3, 0xaa, 0x18, 0x8c,
- 0x8a, 0xca, 0xca, 0xb2, 0xf2, 0x8a, 0xd2, 0xd2, 0xb2, 0xe2, 0x92, 0x52, 0xdc, 0xa7, 0xe8, 0x35,
- 0x3f, 0xf4, 0x1e, 0x09, 0x5e, 0x26, 0x35, 0x2d, 0x8d, 0x1a, 0x43, 0xf8, 0xa1, 0x29, 0x25, 0x35,
- 0x31, 0x31, 0x09, 0x1a, 0x2c, 0x3c, 0x22, 0xe2, 0x86, 0xa7, 0xe7, 0xc1, 0x43, 0x87, 0x96, 0x2d,
- 0x5b, 0x8e, 0x28, 0xe6, 0xf3, 0xcf, 0x3f, 0xff, 0xd3, 0x71, 0xac, 0x84, 0x8d, 0x16, 0xba, 0x20,
- 0x49, 0xbc, 0x11, 0xfc, 0x38, 0xa0, 0x0b, 0x0f, 0x02, 0x47, 0x0f, 0xe2, 0x5d, 0xb8, 0x70, 0x21,
- 0x00, 0x8c, 0x60, 0x7f, 0xe9, 0x52, 0x0d, 0x38, 0x1a, 0xfc, 0xa1, 0xa2, 0xa2, 0x02, 0x4a, 0x84,
- 0x12, 0x46, 0x90, 0x05, 0x2a, 0x43, 0x5d, 0xa6, 0xd6, 0x27, 0x91, 0x96, 0xf4, 0xd4, 0x82, 0xba,
- 0x38, 0x0d, 0xc2, 0x43, 0x5b, 0x5b, 0xdb, 0xf6, 0xe8, 0x51, 0x77, 0x77, 0x8f, 0xdb, 0xb7, 0x6f,
- 0x7b, 0xfb, 0xf8, 0xf8, 0xfa, 0xfa, 0x51, 0xe6, 0xeb, 0xeb, 0x8b, 0x4f, 0x77, 0xef, 0x7a, 0x5d,
- 0xbf, 0x71, 0x03, 0x61, 0xc2, 0x79, 0x17, 0x57, 0xd7, 0x0b, 0x6e, 0x97, 0x2e, 0x5f, 0xf6, 0xf4,
- 0xbc, 0x79, 0xd7, 0xcb, 0x0b, 0xe7, 0x8d, 0x9c, 0xf8, 0xf1, 0xec, 0x3e, 0x58, 0xe7, 0xc1, 0x03,
- 0x7f, 0xff, 0x87, 0x8f, 0x1e, 0x05, 0x04, 0x06, 0x3e, 0x46, 0x40, 0x18, 0x1c, 0x1c, 0xf2, 0xec,
- 0x59, 0x58, 0x58, 0x18, 0xca, 0x37, 0x22, 0x32, 0x32, 0x32, 0x8a, 0xa8, 0x37, 0x54, 0xc2, 0x47,
- 0x7c, 0x19, 0x16, 0x1e, 0x8e, 0x13, 0x82, 0x9f, 0x3e, 0x85, 0x2c, 0xa4, 0x36, 0x32, 0xf3, 0x7f,
- 0xf8, 0x10, 0x37, 0xc1, 0xad, 0x3e, 0xfa, 0xd3, 0x7d, 0x14, 0x43, 0xae, 0x79, 0x7b, 0x7b, 0x43,
- 0x0f, 0x20, 0x33, 0xad, 0x6d, 0x6c, 0x7e, 0xd4, 0xd4, 0x54, 0x5a, 0xb8, 0x90, 0x6a, 0x98, 0xfd,
- 0xb3, 0xe8, 0xd8, 0x37, 0x1b, 0xd5, 0x3d, 0x41, 0x75, 0xae, 0x7d, 0x32, 0xd2, 0xb3, 0x46, 0x36,
- 0xed, 0x7e, 0x05, 0xd7, 0x3c, 0x71, 0x22, 0x31, 0x89, 0x60, 0x2a, 0x69, 0x93, 0x27, 0x4f, 0x01,
- 0x9e, 0xc9, 0xb1, 0xca, 0x5f, 0x50, 0x23, 0x00, 0xdf, 0xd0, 0xca, 0x47, 0x8d, 0xd7, 0x42, 0x15,
- 0x80, 0x3f, 0x02, 0xec, 0x37, 0x6f, 0xd9, 0xb2, 0x67, 0x8f, 0x9e, 0x91, 0x91, 0xb1, 0x89, 0x89,
- 0xa9, 0xa9, 0xa9, 0x99, 0xa9, 0x19, 0x99, 0x4c, 0xcd, 0xf0, 0xd1, 0xc8, 0xd8, 0xd8, 0xc0, 0x60,
- 0xff, 0x1e, 0x3d, 0xbd, 0x9d, 0xbb, 0x76, 0xed, 0xda, 0xbd, 0x5b, 0x6f, 0xef, 0xde, 0xfd, 0x86,
- 0x86, 0x07, 0x0f, 0x1e, 0x7a, 0x79, 0xda, 0xc7, 0x4b, 0x66, 0x66, 0xc4, 0x06, 0x6a, 0xe6, 0x16,
- 0xb0, 0xc3, 0x87, 0x41, 0xfd, 0x96, 0x96, 0xd6, 0xd6, 0x36, 0xb6, 0xb6, 0xc4, 0xdc, 0x5e, 0x7b,
- 0x87, 0x63, 0xc7, 0x8e, 0x39, 0x3a, 0x3a, 0x1e, 0x3f, 0x7e, 0xfc, 0x04, 0x12, 0xfe, 0x8f, 0x4f,
- 0xf8, 0x0e, 0x07, 0x50, 0xdd, 0x50, 0xf4, 0x96, 0x56, 0x56, 0x38, 0x1f, 0xd7, 0xe1, 0x62, 0xdc,
- 0x02, 0xb7, 0xfa, 0xe8, 0x8f, 0xf7, 0x71, 0x12, 0x95, 0xab, 0x46, 0x46, 0x7b, 0xf6, 0xec, 0xd9,
- 0xbc, 0x79, 0xb3, 0xaa, 0x9a, 0x1a, 0x8a, 0x00, 0x6e, 0xf4, 0xf7, 0x19, 0x66, 0xf0, 0x7b, 0x9a,
- 0x44, 0xcf, 0x1a, 0xd5, 0xb4, 0x4b, 0x2d, 0x88, 0xfa, 0x0f, 0xd2, 0xf0, 0x07, 0x25, 0x0e, 0x71,
- 0x14, 0xe7, 0x8c, 0x49, 0xad, 0xa3, 0xef, 0x06, 0x3c, 0xe3, 0xaa, 0xaf, 0xc6, 0x8f, 0x9f, 0x3e,
- 0x7d, 0x06, 0xf4, 0x06, 0xc8, 0x56, 0x5d, 0x7d, 0x09, 0xa2, 0x00, 0x98, 0x86, 0x86, 0x06, 0xc5,
- 0xdb, 0xf8, 0xa8, 0xbe, 0x64, 0x89, 0xaa, 0xaa, 0xaa, 0xb2, 0xb2, 0xb2, 0xa2, 0x12, 0x61, 0xca,
- 0x8b, 0x16, 0x8d, 0x10, 0x3b, 0x75, 0xe2, 0x6f, 0x67, 0xcb, 0x60, 0xcb, 0x97, 0xaf, 0xa0, 0xa6,
- 0xe3, 0xad, 0x26, 0xec, 0x07, 0x68, 0x18, 0xca, 0xf0, 0x07, 0x3e, 0xe0, 0x2b, 0x44, 0xa6, 0x38,
- 0x8c, 0x93, 0x70, 0x2e, 0xce, 0xc7, 0x55, 0xbf, 0xe9, 0x33, 0x7d, 0xb8, 0xbd, 0xc8, 0x55, 0xf5,
- 0x25, 0xc8, 0x70, 0x64, 0x3b, 0x32, 0xff, 0xab, 0xaf, 0xc6, 0x7f, 0xac, 0x45, 0x11, 0xff, 0x9d,
- 0x4d, 0x0c, 0x60, 0xf1, 0x94, 0x0a, 0xea, 0x6f, 0xea, 0xfb, 0xb7, 0xbc, 0x83, 0x78, 0xaa, 0xc5,
- 0xf8, 0xf1, 0x5f, 0x4f, 0x98, 0x30, 0x11, 0xbe, 0x09, 0x84, 0x3d, 0xc2, 0xd9, 0x53, 0xa9, 0xbf,
- 0xf1, 0x25, 0x98, 0xfc, 0xdb, 0x09, 0x13, 0xbe, 0x21, 0x6d, 0x02, 0xce, 0x23, 0x89, 0x7d, 0xf4,
- 0x99, 0xbf, 0xa9, 0x4d, 0x23, 0x6d, 0xfa, 0x88, 0x8d, 0xcc, 0xce, 0x9b, 0x41, 0x7d, 0x9c, 0x36,
- 0x62, 0xbf, 0xc7, 0xa3, 0x7c, 0x0c, 0x13, 0xe7, 0x2a, 0x32, 0x12, 0xd9, 0x8e, 0xcc, 0x47, 0x11,
- 0xfc, 0xfb, 0x37, 0xc6, 0xfe, 0x9b, 0x18, 0xa5, 0x37, 0xa8, 0x0e, 0x05, 0x8a, 0xae, 0xc7, 0x34,
- 0x1c, 0xfa, 0x9f, 0x51, 0xf6, 0x86, 0x33, 0x7f, 0x07, 0x13, 0x3b, 0x94, 0x3f, 0xbb, 0x8d, 0x76,
- 0x88, 0xa3, 0xe1, 0xfa, 0xff, 0x01, 0x00, 0x07, 0xdb, 0x50, 0xec, 0x6b, 0x02, 0x00
-};
-
-fastimage_t bfin_logo = {
- DEF_BFIN_LOGO_DATA,
- DEF_BFIN_LOGO_WIDTH,
- DEF_BFIN_LOGO_HEIGHT,
- DEF_BFIN_LOGO_BPP,
- DEF_BFIN_LOGO_PIXEL_SIZE,
- DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
deleted file mode 100644
index ae9554f89e1b..000000000000
--- a/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
+++ /dev/null
@@ -1,1819 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where: 'screen' is the pointer to the frame buffer
- * 'width' is the screen width
- * 'x' is the horizontal position
- * 'y' is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 28532
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define DEF_BFIN_LOGO_WIDTH 230
-#define DEF_BFIN_LOGO_HEIGHT 230
-#define DEF_BFIN_LOGO_PIXELS 52900
-#define DEF_BFIN_LOGO_BPP 24
-#define DEF_BFIN_LOGO_PIXEL_SIZE 3
-#define DEF_BFIN_LOGO_SIZE 158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xf8, 0xb8, 0x51, 0x47, 0x76, 0x83, 0x1a, 0x36, 0xff, 0xdf, 0x25, 0x3b, 0x9e, 0x1e, 0xfc,
- 0x17, 0x17, 0x7c, 0x3f, 0x4c, 0x3f, 0x42, 0x00, 0x19, 0xe1, 0x7c, 0x13, 0xce, 0xa1, 0xb5, 0xdf,
- 0x06, 0x70, 0x2e, 0xb6, 0x6c, 0xe0, 0xcb, 0x11, 0xf6, 0x92, 0x94, 0x8a, 0x99, 0x3e, 0x21, 0xb2,
- 0x27, 0xe8, 0x4c, 0x5d, 0x4c, 0x45, 0x6d, 0xfa, 0x0d, 0x07, 0x51, 0x9c, 0xc1, 0xf2, 0x53, 0x6d,
- 0x9e, 0x57, 0xb5, 0x3a, 0x93, 0x8c, 0x7e, 0x3d, 0x18, 0x78, 0x1a, 0x13, 0x72, 0x7a, 0xa6, 0x0f,
- 0x90, 0x31, 0x39, 0xfe, 0xe1, 0x4c, 0x12, 0xda, 0x4f, 0xe8, 0xe7, 0x3f, 0x68, 0xe5, 0xc3, 0x2e,
- 0x8c, 0xeb, 0x62, 0x9a, 0x99, 0x26, 0xf6, 0x64, 0x2e, 0x15, 0x1f, 0xd6, 0xa2, 0xbd, 0xe9, 0xa2,
- 0x87, 0x70, 0xd8, 0x35, 0x60, 0x6d, 0x05, 0x11, 0x97, 0x62, 0x11, 0x11, 0x31, 0x08, 0xb8, 0xe5,
- 0xe1, 0x76, 0x47, 0x2d, 0x42, 0x5d, 0x06, 0xa1, 0x5c, 0x30, 0xf0, 0x11, 0x9d, 0xf7, 0x13, 0x4d,
- 0xbd, 0x5f, 0x8f, 0x2b, 0xb2, 0x2e, 0x47, 0x7e, 0x21, 0x1e, 0xce, 0x05, 0x29, 0x0d, 0x38, 0xcb,
- 0x05, 0xc9, 0x55, 0xde, 0xc9, 0x66, 0xb3, 0xf9, 0x0b, 0xbb, 0x76, 0x6b, 0x36, 0x81, 0x16, 0x59,
- 0xce, 0xbf, 0x02, 0x66, 0x52, 0xa1, 0x75, 0xff, 0xb0, 0xb7, 0x8e, 0x5b, 0x56, 0xaf, 0xdc, 0x62,
- 0x7a, 0xc5, 0xf0, 0xa8, 0xc3, 0xf8, 0xf5, 0x32, 0xef, 0xd7, 0x65, 0xdf, 0x2b, 0x64, 0x9d, 0x1b,
- 0x99, 0x63, 0x0d, 0x11, 0xb2, 0xc8, 0x4a, 0xf6, 0x27, 0xb7, 0xa1, 0xfb, 0x25, 0x7a, 0xfd, 0x69,
- 0x01, 0xfa, 0xc8, 0x2b, 0xe8, 0x44, 0x83, 0x66, 0x72, 0xb6, 0xa9, 0x8a, 0xb2, 0x2a, 0x6f, 0xfe,
- 0xe8, 0xca, 0x85, 0x21, 0x83, 0x77, 0x08, 0x03, 0xc2, 0xd5, 0xd0, 0x68, 0xc4, 0xb3, 0xca, 0x54,
- 0x9b, 0xa9, 0x2b, 0x3e, 0x59, 0xf7, 0x99, 0xa6, 0xed, 0x02, 0xb3, 0x37, 0x4f, 0x2c, 0x2f, 0x79,
- 0x09, 0x6e, 0x68, 0x64, 0xe4, 0xee, 0x3e, 0x25, 0x59, 0x6c, 0x19, 0xfa, 0x8e, 0x03, 0xb1, 0x1a,
- 0x47, 0xc6, 0x7f, 0xea, 0xe9, 0x6a, 0x5b, 0xff, 0x94, 0x8d, 0x93, 0xfd, 0x7e, 0x45, 0x39, 0x81,
- 0xe5, 0xbe, 0xe0, 0xa1, 0x9f, 0x08, 0xd6, 0x71, 0x5f, 0xd9, 0xa8, 0x99, 0x3b, 0xae, 0x4e, 0x03,
- 0xc9, 0x2c, 0x86, 0x61, 0xae, 0xe4, 0x33, 0x72, 0xed, 0xac, 0x53, 0x49, 0x7e, 0xb2, 0xc1, 0xab,
- 0xad, 0x71, 0x70, 0xff, 0x22, 0xff, 0xe6, 0x4f, 0x55, 0x3c, 0xf8, 0xb2, 0xc5, 0x55, 0x2a, 0x7e,
- 0x0f, 0x34, 0x9f, 0x64, 0x54, 0x2c, 0x91, 0x9e, 0xeb, 0x31, 0xa7, 0x83, 0x5f, 0x69, 0x97, 0xee,
- 0xc5, 0x24, 0x62, 0x3a, 0xa3, 0x69, 0x47, 0x06, 0x59, 0x56, 0x60, 0x5f, 0x74, 0xb3, 0x8f, 0x4f,
- 0xf5, 0x8e, 0xbe, 0xaa, 0x9d, 0xba, 0x6c, 0x27, 0xf7, 0x0b, 0x7b, 0xd6, 0x94, 0x73, 0x34, 0xc5,
- 0xa5, 0x3c, 0xbf, 0x4a, 0xde, 0x3f, 0x04, 0x74, 0x67, 0xeb, 0xc9, 0x9f, 0x93, 0x0e, 0xa0, 0xed,
- 0x1c, 0x17, 0x23, 0xb6, 0xac, 0x37, 0x41, 0xdc, 0x24, 0xc4, 0x10, 0xab, 0x0a, 0x14, 0x2c, 0xe8,
- 0x00, 0x34, 0x71, 0xe5, 0x21, 0x22, 0x84, 0x4b, 0x26, 0xf5, 0x59, 0x87, 0x39, 0xda, 0x59, 0x9d,
- 0xbb, 0x22, 0x63, 0x1b, 0x34, 0xfe, 0xb8, 0xba, 0xdf, 0x3c, 0x58, 0x68, 0xa1, 0x73, 0xab, 0x68,
- 0x3f, 0xba, 0xad, 0x30, 0x0d, 0x35, 0x75, 0xca, 0xa7, 0x54, 0xda, 0x8e, 0xdf, 0x43, 0x98, 0xc7,
- 0x72, 0xa3, 0x3b, 0x96, 0x93, 0x5d, 0x86, 0x1f, 0xa7, 0xe0, 0x97, 0x2c, 0xc7, 0x59, 0x30, 0x88,
- 0xec, 0xc2, 0x89, 0x56, 0x1d, 0xda, 0x76, 0xed, 0xf3, 0x53, 0xd5, 0x38, 0x63, 0x70, 0x36, 0x5d,
- 0x89, 0xb1, 0xa9, 0x1f, 0x99, 0x2d, 0x95, 0x89, 0xf3, 0x3f, 0xa7, 0x1a, 0x6b, 0x6a, 0xda, 0xb8,
- 0xba, 0x62, 0x87, 0x28, 0xac, 0x21, 0x7b, 0x47, 0xc2, 0x17, 0xb1, 0x1c, 0x97, 0x63, 0xf6, 0x43,
- 0xb2, 0x62, 0x28, 0x26, 0x0e, 0x76, 0x8c, 0x48, 0x92, 0x1a, 0xde, 0xa7, 0x54, 0xb7, 0xba, 0x4b,
- 0x87, 0xf1, 0xdf, 0xae, 0x4d, 0x72, 0xd4, 0x5d, 0x55, 0x60, 0x39, 0x04, 0x2c, 0xe6, 0x61, 0x09,
- 0x04, 0x74, 0xf9, 0x64, 0x40, 0x52, 0x40, 0xca, 0x04, 0xbb, 0xec, 0x1f, 0xe0, 0x65, 0x21, 0x6f,
- 0x11, 0x69, 0xe5, 0xca, 0xc1, 0xce, 0x70, 0xe0, 0x56, 0x2e, 0x40, 0x38, 0xeb, 0x74, 0x1b, 0x2e,
- 0xef, 0x4f, 0x2b, 0x6b, 0x9b, 0xa9, 0xbe, 0xa1, 0x83, 0x7e, 0x6c, 0x08, 0x1f, 0xc9, 0x2e, 0xf9,
- 0xc7, 0x41, 0xc5, 0xa4, 0xe4, 0x76, 0x0d, 0xca, 0x44, 0x23, 0x4f, 0x60, 0xb5, 0x11, 0x2d, 0xa0,
- 0x6d, 0x28, 0xf2, 0xc5, 0x46, 0x52, 0xe9, 0xfd, 0xa9, 0x9a, 0xf8, 0x5b, 0x9d, 0x60, 0x06, 0x0c,
- 0x25, 0x6c, 0xb6, 0x61, 0x86, 0x56, 0xf5, 0x07, 0x8d, 0xaa, 0xd7, 0x88, 0x9d, 0xc4, 0x40, 0x4a,
- 0x53, 0xd5, 0xe6, 0x3d, 0x06, 0xae, 0x77, 0xf4, 0x27, 0xa5, 0x65, 0x74, 0x98, 0xc7, 0xfe, 0x79,
- 0xca, 0x55, 0xce, 0x49, 0x26, 0x72, 0xd3, 0x54, 0xa9, 0x12, 0xac, 0xa0, 0xf1, 0xe6, 0x73, 0x17,
- 0xc2, 0xfa, 0x9b, 0x0f, 0x0c, 0xcc, 0x92, 0x0a, 0x53, 0x56, 0x4d, 0x8f, 0x58, 0x2d, 0xcb, 0xc0,
- 0x8c, 0xf9, 0x65, 0x24, 0xa4, 0xf0, 0xd4, 0x37, 0xa4, 0x3f, 0xd7, 0x46, 0xe7, 0x16, 0xcc, 0xf1,
- 0x52, 0x3f, 0xf8, 0xa0, 0x7a, 0xb3, 0x21, 0x39, 0x31, 0xfa, 0x6c, 0x23, 0xb2, 0xf8, 0x81, 0xf1,
- 0xc5, 0x53, 0xa5, 0x06, 0xaf, 0x01, 0x10, 0x7e, 0x80, 0xed, 0xe6, 0x04, 0xac, 0x32, 0x28, 0xb2,
- 0xaa, 0x9b, 0x8e, 0x58, 0xfa, 0x54, 0x43, 0xeb, 0x6c, 0x6e, 0xf9, 0x6d, 0x9a, 0x6b, 0x8c, 0xb1,
- 0x98, 0x6d, 0xf4, 0xd9, 0xd0, 0x0c, 0xba, 0x29, 0x01, 0x06, 0x7c, 0x8c, 0xb6, 0x55, 0xe1, 0x06,
- 0xa1, 0xed, 0x96, 0x13, 0x53, 0x33, 0x9e, 0x2a, 0xb3, 0x91, 0xc4, 0xbd, 0x1a, 0x86, 0xea, 0xaf,
- 0xa3, 0xb4, 0xf2, 0xa2, 0xc3, 0xe4, 0x09, 0x70, 0xe1, 0x2d, 0xd1, 0xf2, 0xf1, 0x32, 0xbd, 0x97,
- 0x7f, 0xfd, 0x80, 0x33, 0xa5, 0x5c, 0xf4, 0xf0, 0xba, 0x25, 0xb2, 0x6a, 0x7f, 0xe7, 0x1f, 0x22,
- 0x42, 0xa9, 0x0e, 0xa5, 0x1f, 0x12, 0x11, 0xe9, 0xa2, 0x1e, 0x53, 0x82, 0x64, 0x1b, 0x06, 0x3e,
- 0x69, 0x00, 0xb3, 0x7b, 0x82, 0xfa, 0x53, 0xc2, 0xab, 0x2c, 0xb0, 0x56, 0xda, 0xe9, 0x64, 0x25,
- 0x08, 0x8e, 0x85, 0x48, 0xd4, 0xd7, 0x7e, 0x0f, 0xa6, 0x59, 0xf3, 0xdf, 0x0f, 0x95, 0x88, 0x3f,
- 0x4f, 0xbd, 0xa6, 0x0e, 0x87, 0x53, 0xd0, 0x8c, 0x4f, 0x92, 0xe7, 0x80, 0xaf, 0x1e, 0x89, 0x83,
- 0x6c, 0x69, 0x5c, 0xe7, 0xc6, 0x19, 0x12, 0x31, 0xe8, 0x3a, 0x2c, 0x55, 0x9b, 0x40, 0xaf, 0xb3,
- 0xaf, 0x47, 0xcb, 0x1a, 0x66, 0x60, 0x79, 0x4c, 0x1b, 0x93, 0xbd, 0xf9, 0x03, 0x75, 0xce, 0xa1,
- 0xc1, 0x0c, 0x52, 0xd5, 0x82, 0x9f, 0xb3, 0x5c, 0xaf, 0x4c, 0x15, 0xef, 0x38, 0x00, 0xdc, 0x4b,
- 0x1d, 0x93, 0x7c, 0xc1, 0xa0, 0xe9, 0x0a, 0x2f, 0xa6, 0xf1, 0x0f, 0x3a, 0xfb, 0xe3, 0x31, 0xf8,
- 0x7d, 0x79, 0x83, 0xde, 0x23, 0x14, 0xfc, 0x74, 0x28, 0x7d, 0xad, 0x02, 0x53, 0x37, 0x50, 0x63,
- 0xc5, 0xa9, 0x80, 0x4c, 0x26, 0xf8, 0x30, 0xa7, 0xa5, 0x0d, 0xcf, 0x91, 0xd5, 0x7b, 0x82, 0x1e,
- 0xcd, 0x8c, 0x49, 0xde, 0x02, 0x9c, 0x95, 0x8f, 0xd0, 0x5b, 0x80, 0xaf, 0xd9, 0xc6, 0x62, 0x70,
- 0x1e, 0x41, 0x19, 0xe5, 0x36, 0xce, 0x06, 0x34, 0xc5, 0xe6, 0x16, 0x4b, 0x42, 0xfa, 0xca, 0x73,
- 0xdc, 0x1c, 0x74, 0xd5, 0x23, 0xcc, 0xde, 0x96, 0x57, 0x88, 0x8f, 0x12, 0x47, 0x24, 0xa3, 0x4e,
- 0x50, 0x17, 0xb0, 0x31, 0xe2, 0x89, 0x68, 0xd0, 0x29, 0xb4, 0x25, 0x01, 0xf7, 0x9d, 0x1b, 0xa1,
- 0x0d, 0xcf, 0xa3, 0x46, 0x83, 0xd0, 0x41, 0x00, 0x84, 0xd3, 0x6a, 0xe6, 0xd4, 0xff, 0x0a, 0x88,
- 0x9e, 0x4a, 0xd5, 0x57, 0xa0, 0x86, 0xe3, 0x35, 0x75, 0x95, 0x2a, 0x35, 0xaf, 0x93, 0x8c, 0x63,
- 0x14, 0x40, 0xc5, 0xe9, 0x74, 0xe7, 0xf6, 0x55, 0x38, 0xe1, 0x26, 0xb1, 0xc9, 0x03, 0x97, 0x5b,
- 0x23, 0xd5, 0xe8, 0x7b, 0xfe, 0xe5, 0xdd, 0x4d, 0x1b, 0x1a, 0x37, 0xb6, 0x12, 0x3a, 0xb4, 0x74,
- 0x9c, 0x08, 0xc1, 0x76, 0x77, 0xb7, 0x2f, 0xd7, 0xa7, 0x48, 0x1d, 0xa2, 0x3d, 0x68, 0x6b, 0x5d,
- 0xf1, 0xba, 0x82, 0x50, 0xe4, 0x80, 0x63, 0xdd, 0x47, 0xe8, 0xdf, 0x19, 0xb7, 0x26, 0x9b, 0x1a,
- 0xdf, 0x6a, 0x81, 0x3f, 0x0d, 0xe1, 0xa7, 0x9f, 0x7e, 0x1c, 0x5e, 0xbb, 0xe7, 0x9d, 0xff, 0x9d,
- 0x66, 0x82, 0xaf, 0x12, 0x49, 0xb2, 0xaa, 0xdb, 0xd1, 0x82, 0xe2, 0x22, 0xcb, 0xbc, 0xbf, 0x3f,
- 0xd2, 0xa7, 0x5f, 0xb7, 0x0e, 0x57, 0x5a, 0x24, 0xb2, 0xe8, 0x8c, 0x0f, 0x7f, 0xd6, 0x70, 0x50,
- 0x2c, 0x40, 0x5a, 0x8d, 0x97, 0x01, 0xe7, 0x21, 0x1c, 0xab, 0xa7, 0x55, 0x3e, 0x4e, 0xe2, 0x70,
- 0xf9, 0xb4, 0x69, 0x5b, 0xe1, 0x64, 0x12, 0xd3, 0x23, 0x26, 0x78, 0x2c, 0x60, 0xb4, 0xb1, 0xba,
- 0x1a, 0xff, 0x59, 0x26, 0x7a, 0x54, 0xa8, 0x8f, 0x4b, 0x2c, 0x6d, 0xe4, 0xeb, 0xb2, 0x12, 0xc6,
- 0x3d, 0x7b, 0xa8, 0x6d, 0x70, 0xd3, 0xcf, 0x73, 0x38, 0xf4, 0xab, 0x50, 0x1d, 0x49, 0xe0, 0xb0,
- 0x85, 0xd1, 0x9a, 0x8e, 0x14, 0x3e, 0x0c, 0x2b, 0x26, 0x61, 0x50, 0x48, 0x3d, 0xbe, 0xae, 0x53,
- 0xd8, 0xc1, 0x49, 0xe3, 0x58, 0x06, 0x9c, 0xd0, 0xdc, 0x4e, 0xc7, 0x8e, 0x43, 0xd1, 0x76, 0x0b,
- 0x27, 0xbe, 0x89, 0x96, 0x46, 0xdc, 0x66, 0x2f, 0x6c, 0xbf, 0xd9, 0x08, 0xf9, 0x04, 0xf8, 0x7e,
- 0x6b, 0x63, 0xb5, 0x2c, 0x4d, 0x4c, 0x91, 0x89, 0x62, 0xb2, 0x2e, 0x85, 0x95, 0x52, 0x38, 0x1a,
- 0xea, 0xac, 0x50, 0x2a, 0x33, 0x03, 0xe4, 0x0b, 0x78, 0x97, 0xaa, 0x35, 0xf5, 0x04, 0x6e, 0xf4,
- 0x5b, 0xf8, 0xb6, 0x1b, 0x3b, 0xf3, 0xf6, 0x99, 0xf5, 0x31, 0xf2, 0x96, 0xe4, 0x26, 0x7b, 0x00,
- 0x3a, 0x08, 0x7a, 0x94, 0xeb, 0xce, 0x61, 0xd4, 0x3b, 0x93, 0x4f, 0x86, 0x84, 0xaf, 0xee, 0x23,
- 0x8a, 0x8d, 0x7d, 0xab, 0x2d, 0xc0, 0xc6, 0x8d, 0x27, 0x0b, 0x80, 0x96, 0xb0, 0x6e, 0x86, 0xa7,
- 0xf1, 0xbc, 0x48, 0x3e, 0x74, 0x25, 0x8c, 0x5b, 0x74, 0xa1, 0xc4, 0xeb, 0xab, 0x09, 0xb8, 0xd2,
- 0x15, 0xa0, 0x7f, 0x20, 0x91, 0x6b, 0x09, 0xda, 0xbc, 0x98, 0x06, 0xec, 0xea, 0xdd, 0xae, 0xcd,
- 0xe8, 0xb6, 0x85, 0x26, 0x61, 0xb9, 0xa5, 0xc5, 0x4e, 0xae, 0xfc, 0x0f, 0x2b, 0x9c, 0x42, 0xc6,
- 0x8b, 0x28, 0x60, 0x04, 0x7d, 0x67, 0x23, 0x6a, 0xfd, 0xa3, 0x60, 0x19, 0x97, 0x50, 0x04, 0xd1,
- 0xb1, 0x7b, 0x6a, 0xa7, 0x0a, 0x44, 0x61, 0xfe, 0xeb, 0xe6, 0xcf, 0x42, 0x7c, 0x3b, 0x82, 0xcc,
- 0x41, 0x52, 0x82, 0xe0, 0xbd, 0xa2, 0x05, 0xf3, 0x98, 0xd3, 0xdc, 0x95, 0x6c, 0x59, 0x4b, 0x31,
- 0xdc, 0x5e, 0x1e, 0x4e, 0x3d, 0x18, 0x95, 0xe6, 0xc3, 0xcd, 0xa9, 0x9e, 0xf4, 0xfe, 0xf0, 0x85,
- 0xf8, 0xb1, 0xd0, 0x2f, 0x7d, 0x9c, 0xb5, 0x83, 0xde, 0xd7, 0x80, 0x0a, 0x56, 0xcd, 0xe8, 0x5b,
- 0xbd, 0xdc, 0x60, 0xce, 0x26, 0xf7, 0xc9, 0x11, 0xd7, 0x2a, 0x69, 0xf0, 0xa3, 0x62, 0x83, 0x2c,
- 0xe8, 0x9a, 0xec, 0x43, 0x91, 0x12, 0x2b, 0x2a, 0x41, 0x50, 0x67, 0x02, 0x30, 0xc0, 0x4d, 0xb4,
- 0xc8, 0x6c, 0x40, 0x25, 0x55, 0xf1, 0x67, 0x7a, 0x11, 0x05, 0x3b, 0x9f, 0x55, 0xce, 0xec, 0x69,
- 0x13, 0x68, 0x1a, 0x8c, 0x7d, 0xba, 0x3f, 0x98, 0x4a, 0xf7, 0x9a, 0x44, 0x31, 0x2a, 0x3d, 0x3b,
- 0xe6, 0x0e, 0x6a, 0x71, 0x1b, 0xea, 0xf9, 0x19, 0x9a, 0x09, 0x1a, 0x4d, 0xe9, 0xef, 0x39, 0xf2,
- 0x80, 0x77, 0x0e, 0x4e, 0x54, 0x0f, 0xc4, 0x8f, 0xdc, 0xa4, 0xb7, 0xb5, 0x63, 0xdd, 0x3a, 0x4f,
- 0xdc, 0xd2, 0x17, 0x3b, 0x1c, 0xbc, 0xfa, 0xa2, 0x15, 0x69, 0x26, 0x8c, 0x1e, 0x68, 0xc9, 0x14,
- 0xc5, 0x4e, 0x69, 0x98, 0xc1, 0x3c, 0x5d, 0x8b, 0x02, 0x70, 0xb5, 0x94, 0x90, 0x71, 0x1e, 0xb6,
- 0xd9, 0x10, 0x5d, 0x67, 0x37, 0x75, 0x38, 0x8e, 0x0e, 0x75, 0xf8, 0xcd, 0x67, 0x94, 0xdd, 0x82,
- 0xd6, 0xec, 0xc2, 0x91, 0xf6, 0x10, 0x5d, 0x9c, 0xf7, 0x28, 0xed, 0x5d, 0x70, 0x4c, 0x92, 0x45,
- 0xd8, 0x86, 0xbe, 0x9a, 0x3c, 0x31, 0x76, 0x18, 0x80, 0x0a, 0xdd, 0x7e, 0x06, 0x95, 0xc6, 0x14,
- 0x7e, 0x7d, 0xce, 0x1f, 0xd1, 0x66, 0xc6, 0xef, 0xc5, 0x63, 0x25, 0x95, 0x39, 0x64, 0x14, 0x28,
- 0xae, 0x51, 0x6d, 0x0d, 0x9c, 0xc0, 0x5a, 0x3a, 0xdb, 0x02, 0xae, 0x50, 0x43, 0x34, 0x3b, 0x49,
- 0x31, 0xf4, 0x6b, 0x4f, 0x85, 0xf6, 0x1d, 0x53, 0x88, 0x76, 0xd3, 0x01, 0x71, 0xfc, 0x23, 0x06,
- 0x63, 0x9f, 0x3d, 0xd2, 0x00, 0x8d, 0xc7, 0x5a, 0x2f, 0x8a, 0x54, 0xfc, 0x76, 0x0f, 0x7a, 0x76,
- 0x0f, 0xfb, 0x2f, 0x1c, 0x0a, 0x3b, 0x3f, 0xd6, 0xad, 0xfc, 0xcf, 0x68, 0x6b, 0x0b, 0xae, 0x9c,
- 0xda, 0xeb, 0x8d, 0x8f, 0x7f, 0x7d, 0x1a, 0x55, 0x28, 0x90, 0xa8, 0xc0, 0x04, 0x25, 0xa2, 0x7b,
- 0xb3, 0x3b, 0xd0, 0x9d, 0x79, 0xc0, 0xb5, 0x7f, 0x84, 0x7c, 0x85, 0xda, 0x59, 0xda, 0xfb, 0xb3,
- 0xab, 0x26, 0x51, 0x9e, 0x92, 0x6f, 0xce, 0x53, 0x8c, 0xf8, 0x72, 0x1b, 0xcf, 0x31, 0x41, 0x04,
- 0x9f, 0x7e, 0x8f, 0x9e, 0xc4, 0xfe, 0x56, 0xd3, 0x54, 0x1e, 0x1d, 0xe8, 0x3e, 0x49, 0xd3, 0x41,
- 0xf1, 0x37, 0x1e, 0xb1, 0xa9, 0x5d, 0x59, 0x5f, 0x17, 0x34, 0x0a, 0x86, 0x01, 0xb5, 0x71, 0xa0,
- 0x22, 0xe7, 0x35, 0x6f, 0xf1, 0x50, 0x55, 0x38, 0xa6, 0x4e, 0x80, 0x8a, 0xd4, 0x25, 0x67, 0x81,
- 0xa5, 0xc6, 0x3c, 0x45, 0x31, 0xf4, 0x1d, 0x31, 0x69, 0xf3, 0x25, 0xe2, 0xde, 0x0f, 0xb3, 0xc6,
- 0x44, 0x73, 0x7a, 0xd0, 0xf2, 0xac, 0x2e, 0xbf, 0xf7, 0xad, 0x8c, 0xe1, 0x33, 0x66, 0xf2, 0x03,
- 0x67, 0xbe, 0x4a, 0xbf, 0x4e, 0x3a, 0xf5, 0x99, 0x15, 0x55, 0x8f, 0xac, 0xe2, 0xa4, 0x82, 0x4e,
- 0x44, 0xbb, 0xd8, 0xa1, 0x26, 0x32, 0x5f, 0xf8, 0x54, 0x16, 0x96, 0x43, 0x37, 0x3d, 0x98, 0x6e,
- 0xec, 0x3a, 0xa4, 0x66, 0x65, 0x6a, 0xbc, 0x1e, 0xd1, 0xe8, 0xde, 0x44, 0x74, 0x1f, 0x32, 0x12,
- 0x3c, 0xe7, 0x4c, 0x1c, 0x15, 0x46, 0x9c, 0xa2, 0x27, 0x54, 0x64, 0x48, 0xe4, 0x36, 0xc2, 0x7d,
- 0xb4, 0xd7, 0xc9, 0xf7, 0xd2, 0x5c, 0x80, 0x0b, 0xe6, 0x52, 0x96, 0x42, 0x9e, 0xb3, 0x03, 0x60,
- 0x67, 0x29, 0x4f, 0x6a, 0xab, 0x62, 0x32, 0x0d, 0x9c, 0x20, 0x9e, 0xa9, 0x6c, 0x48, 0x51, 0x70,
- 0xe6, 0x17, 0x83, 0xfc, 0x56, 0xf4, 0xcc, 0xba, 0x06, 0x9d, 0x37, 0x7a, 0x55, 0xe3, 0xf0, 0xda,
- 0xe7, 0x27, 0x57, 0x3b, 0x35, 0x32, 0x9e, 0x13, 0xa5, 0x14, 0x2e, 0x1f, 0x88, 0xe5, 0xb8, 0x2c,
- 0x45, 0x16, 0x24, 0x7d, 0x1e, 0x28, 0x63, 0xdb, 0x67, 0x43, 0xcf, 0xda, 0x19, 0x99, 0x96, 0x3d,
- 0x6d, 0x06, 0x65, 0x8c, 0xce, 0x73, 0x51, 0x8c, 0x4f, 0xaf, 0x5c, 0xa8, 0x85, 0xce, 0x12, 0xe6,
- 0xf0, 0xfe, 0x20, 0x09, 0x08, 0xd0, 0x18, 0xdb, 0x61, 0x0e, 0x95, 0x5f, 0xa0, 0x48, 0xb9, 0xbb,
- 0xfe, 0x45, 0x15, 0x7d, 0x2f, 0x74, 0x88, 0x24, 0x14, 0xb3, 0x60, 0x39, 0x7b, 0x86, 0x3c, 0x8a,
- 0x3c, 0x81, 0x01, 0xc7, 0xbf, 0xc6, 0xd3, 0xf8, 0x36, 0xc7, 0x8b, 0x52, 0xec, 0x86, 0x9c, 0x01,
- 0x5b, 0xb6, 0x1a, 0x97, 0xc9, 0xc9, 0x5d, 0x26, 0x35, 0xb1, 0x33, 0x5b, 0x7b, 0xd3, 0x94, 0xb8,
- 0xe6, 0x32, 0xb6, 0x8c, 0x92, 0x95, 0x10, 0x8f, 0x20, 0xe9, 0x07, 0xf8, 0x4b, 0xb6, 0x45, 0xd0,
- 0x39, 0xed, 0xdb, 0xe5, 0x51, 0xf7, 0xa4, 0x02, 0x91, 0x29, 0x7c, 0xe6, 0x14, 0x52, 0x2a, 0x79,
- 0xcf, 0xe0, 0xcf, 0x16, 0x48, 0x90, 0x44, 0xcd, 0x34, 0x65, 0xef, 0x1f, 0xea, 0x26, 0xfd, 0x19,
- 0x0c, 0xea, 0x4b, 0x34, 0x2d, 0x39, 0x08, 0xd5, 0x48, 0xbf, 0xdc, 0x41, 0x7d, 0xb6, 0xa5, 0x92,
- 0x2a, 0xde, 0xf9, 0x99, 0xbe, 0xc8, 0x36, 0xd3, 0x31, 0x77, 0x3c, 0x2b, 0x2f, 0xa9, 0x1c, 0x80,
- 0x5b, 0xc9, 0x40, 0x21, 0xb8, 0x3e, 0xa4, 0x2f, 0x01, 0xe7, 0x2c, 0xce, 0x64, 0xdc, 0x1b, 0xfb,
- 0x10, 0xc5, 0x08, 0x18, 0x3a, 0x3b, 0x0d, 0x41, 0x32, 0xd3, 0x7c, 0x13, 0xb9, 0x85, 0x59, 0x94,
- 0x5e, 0x27, 0x0b, 0x77, 0x34, 0x33, 0xd7, 0x59, 0xee, 0x65, 0xab, 0xc3, 0xaf, 0xd2, 0xd3, 0x19,
- 0x6e, 0xcb, 0x09, 0x30, 0x46, 0x14, 0x69, 0x91, 0xb5, 0x0b, 0x61, 0x40, 0x55, 0xce, 0x49, 0x5d,
- 0x95, 0xfe, 0x81, 0xcb, 0xbe, 0x20, 0x59, 0x11, 0xa8, 0x89, 0xc1, 0xab, 0xf2, 0xcf, 0x8f, 0xf5,
- 0xe1, 0x67, 0x03, 0xb0, 0xf8, 0x5b, 0x23, 0x5b, 0x9c, 0x73, 0xb3, 0xb4, 0xb3, 0x71, 0x6e, 0xd7,
- 0x46, 0xed, 0x61, 0x1d, 0xd2, 0x37, 0x99, 0xa4, 0xe9, 0x3b, 0x60, 0xf1, 0x33, 0x7d, 0x6b, 0xda,
- 0xb7, 0xd9, 0x7c, 0xc6, 0x5d, 0x89, 0xbd, 0xcf, 0xc4, 0x94, 0x51, 0xc2, 0x94, 0xed, 0x09, 0x04,
- 0x4a, 0x98, 0x96, 0xd5, 0x96, 0xc5, 0xcc, 0x14, 0xc4, 0x37, 0xae, 0x61, 0x04, 0xe4, 0x20, 0xef,
- 0x75, 0x90, 0x84, 0xcb, 0x9f, 0xca, 0x6a, 0xb0, 0x00, 0xfb, 0x37, 0xfb, 0x95, 0xe1, 0xe1, 0xbc,
- 0xee, 0x71, 0xd1, 0xdb, 0xa9, 0x53, 0xf7, 0x5c, 0x81, 0x27, 0x72, 0x90, 0x2f, 0x06, 0x2c, 0xbf,
- 0x7a, 0x0a, 0xf0, 0x10, 0xb7, 0xd2, 0x31, 0xbd, 0xc8, 0x80, 0x90, 0x27, 0x87, 0x0a, 0x61, 0x67,
- 0x76, 0x4d, 0xeb, 0x96, 0xb7, 0x83, 0xfe, 0xf0, 0xac, 0x70, 0x59, 0xf8, 0xd6, 0x51, 0xe3, 0xb9,
- 0x02, 0x3e, 0xbc, 0xef, 0xdf, 0xc2, 0x08, 0x17, 0x72, 0x2c, 0xa5, 0xf8, 0xf8, 0xb6, 0xfb, 0x1b,
- 0x58, 0x47, 0x03, 0x92, 0xb0, 0xa9, 0xfd, 0x18, 0xd1, 0x6d, 0xad, 0x1d, 0xca, 0x71, 0xff, 0x3c,
- 0x1b, 0xa8, 0x61, 0xa8, 0x18, 0xad, 0x4a, 0xe8, 0xbb, 0xb9, 0x34, 0xda, 0xa3, 0x30, 0x2e, 0xd9,
- 0x30, 0x6b, 0x4d, 0xc9, 0xb7, 0xc8, 0x76, 0xd1, 0xe5, 0x51, 0x14, 0x1c, 0x17, 0x3e, 0x52, 0xf6,
- 0xd7, 0x70, 0xde, 0xe7, 0x25, 0xa6, 0x27, 0x6f, 0xba, 0x13, 0xc3, 0x91, 0x99, 0xaa, 0x42, 0x3d,
- 0xb2, 0xa3, 0x0b, 0xbe, 0x9a, 0xa7, 0x51, 0x75, 0xcf, 0x54, 0x4f, 0x39, 0x62, 0xe0, 0x72, 0x82,
- 0x24, 0x19, 0x69, 0x6e, 0x23, 0x2d, 0x7c, 0xfb, 0xd6, 0xf9, 0x68, 0xa3, 0x5d, 0x71, 0x5d, 0x21,
- 0x47, 0x05, 0x08, 0x0f, 0xed, 0x47, 0xa1, 0xd9, 0x6b, 0x42, 0xcf, 0x8e, 0xb8, 0x73, 0x12, 0x58,
- 0x90, 0x71, 0x0f, 0xf6, 0xfc, 0x4a, 0x33, 0xc9, 0xc9, 0xd6, 0xc6, 0xd7, 0x71, 0x3b, 0xfb, 0xd4,
- 0xbf, 0x87, 0x43, 0x37, 0xf6, 0x18, 0xe6, 0x5c, 0xaa, 0x0f, 0x33, 0x02, 0x9e, 0x34, 0xd4, 0xb0,
- 0xa8, 0x7c, 0xdb, 0x37, 0x2d, 0x8a, 0xf3, 0xba, 0x57, 0xb8, 0xc1, 0xcb, 0xea, 0x40, 0x26, 0x28,
- 0xae, 0xda, 0xe4, 0x96, 0x09, 0xea, 0x78, 0xe3, 0x70, 0xc6, 0x61, 0x17, 0x47, 0x9f, 0xd4, 0xd8,
- 0x01, 0x0c, 0x78, 0xc6, 0xba, 0x5a, 0xc2, 0x20, 0x33, 0x60, 0xe1, 0x4f, 0x59, 0x45, 0x41, 0xda,
- 0x75, 0xcb, 0x5f, 0x46, 0x1c, 0xdd, 0xa2, 0x2e, 0xd5, 0x5d, 0xba, 0x49, 0x7a, 0x34, 0x6b, 0x02,
- 0x7e, 0xe6, 0xaa, 0x08, 0x74, 0x60, 0xa9, 0x6d, 0xab, 0x9f, 0xfe, 0x72, 0xbf, 0x98, 0x1a, 0xec,
- 0x7a, 0x4d, 0x3b, 0xf9, 0x98, 0x6f, 0x58, 0x2c, 0xc9, 0x9c, 0xe2, 0xcc, 0xc0, 0x06, 0x2a, 0x4a,
- 0x57, 0x29, 0xdc, 0x83, 0xc9, 0xbd, 0x99, 0x67, 0xcb, 0x97, 0x1c, 0x6a, 0xd6, 0xf2, 0xbe, 0x95,
- 0xeb, 0xa4, 0xab, 0xae, 0xb3, 0xb3, 0x0d, 0x3a, 0xfb, 0x63, 0xfe, 0x57, 0xa3, 0xcb, 0x37, 0x3c,
- 0x7b, 0xc0, 0xd4, 0xf8, 0x3b, 0x1e, 0x66, 0x1a, 0xa4, 0xb0, 0xa6, 0x2f, 0x1b, 0x2f, 0x8a, 0xfd,
- 0x5e, 0xe7, 0x91, 0x5b, 0x38, 0x32, 0x08, 0xab, 0xad, 0xa0, 0x39, 0xab, 0xe7, 0xb1, 0x25, 0xfb,
- 0x57, 0x5e, 0xff, 0xc8, 0x98, 0xe2, 0xde, 0xd7, 0x82, 0x21, 0x86, 0x66, 0x04, 0xf3, 0x73, 0x82,
- 0x7b, 0x10, 0x11, 0x33, 0x7d, 0x44, 0x6e, 0xc4, 0x67, 0xf8, 0xca, 0x4d, 0x30, 0x29, 0xfe, 0x24,
- 0xa3, 0x2d, 0xd5, 0xfa, 0x48, 0x25, 0x9e, 0xa4, 0x1f, 0xc0, 0x43, 0xdb, 0x9c, 0x7e, 0x89, 0xe9,
- 0xf9, 0x9a, 0x5c, 0x16, 0xf3, 0xef, 0x59, 0xe9, 0xdf, 0x0f, 0x5d, 0xda, 0x61, 0x8d, 0x4c, 0xc1,
- 0x0e, 0xb4, 0xa2, 0x4d, 0x0d, 0xb3, 0x55, 0x31, 0x95, 0xa2, 0xf9, 0xaa, 0xee, 0xa8, 0xa6, 0xc9,
- 0x47, 0xec, 0x97, 0xe6, 0x10, 0xb5, 0x3f, 0xc5, 0xcf, 0x90, 0x46, 0xf6, 0xb0, 0xb5, 0xa3, 0x24,
- 0x35, 0xa5, 0x9a, 0xde, 0xe0, 0xda, 0x18, 0xd6, 0xdb, 0x47, 0x8b, 0xa0, 0x5c, 0x43, 0x6c, 0x9d,
- 0x44, 0x3d, 0xb5, 0xb5, 0x26, 0x13, 0xda, 0xe8, 0x60, 0x42, 0xa5, 0x85, 0x5b, 0x7e, 0x3a, 0x34,
- 0xb1, 0x28, 0x83, 0x8c, 0x09, 0x34, 0xd8, 0x2c, 0x74, 0xa9, 0x42, 0x9b, 0xa8, 0xd4, 0xb7, 0xa9,
- 0x4b, 0xdf, 0xa6, 0x6e, 0x2b, 0x44, 0xae, 0xb9, 0x36, 0xb8, 0xc9, 0x22, 0x03, 0xd7, 0x20, 0x59,
- 0x90, 0x8a, 0x92, 0xab, 0x88, 0x18, 0x8c, 0xeb, 0x72, 0x88, 0xa1, 0x96, 0x46, 0xad, 0x94, 0x92,
- 0xb6, 0x69, 0x73, 0x93, 0xe0, 0xd9, 0x79, 0x7b, 0x48, 0xb0, 0xa1, 0x28, 0x2d, 0x2d, 0x92, 0x84,
- 0x60, 0x37, 0x8b, 0xc6, 0x35, 0x8d, 0x70, 0x6a, 0x18, 0x12, 0xd6, 0xce, 0x58, 0x58, 0x6e, 0x67,
- 0xea, 0xb0, 0xdc, 0x79, 0x86, 0xe2, 0x5c, 0x6a, 0x39, 0x08, 0x38, 0x01, 0x31, 0x78, 0xcc, 0x18,
- 0x88, 0xde, 0x36, 0xbc, 0x82, 0xd2, 0xb4, 0x21, 0x67, 0x4e, 0x8d, 0x5a, 0x4a, 0x53, 0xbf, 0x77,
- 0x86, 0xf7, 0xf5, 0x6c, 0x47, 0x18, 0xee, 0xe6, 0xd3, 0xde, 0x2b, 0xcf, 0x1d, 0x39, 0x79, 0x7c,
- 0xd5, 0x52, 0xaf, 0x58, 0xbf, 0x6f, 0xfd, 0x62, 0x36, 0x33, 0xf2, 0xb1, 0x08, 0x7d, 0x67, 0x64,
- 0xea, 0x96, 0x48, 0x5f, 0xf6, 0x9e, 0x63, 0x51, 0xdc, 0x14, 0xae, 0x76, 0xbc, 0x8e, 0x89, 0x37,
- 0x9e, 0x1e, 0xae, 0xaa, 0x11, 0x9c, 0x11, 0xc2, 0x7e, 0xab, 0x32, 0x90, 0xdf, 0xb4, 0x02, 0x93,
- 0x45, 0x33, 0x81, 0x83, 0x00, 0x28, 0x78, 0xf6, 0x17, 0xad, 0x0c, 0x73, 0x19, 0x7b, 0x32, 0x5b,
- 0xe6, 0x9a, 0x35, 0x3d, 0x12, 0xe0, 0x29, 0xdd, 0xb4, 0xb5, 0xce, 0xcf, 0xc1, 0x75, 0xe9, 0x24,
- 0x8b, 0x02, 0x91, 0xdb, 0x1c, 0xb5, 0x03, 0xc7, 0xf0, 0xfd, 0xc5, 0xa0, 0x5e, 0xea, 0xa2, 0xfb,
- 0x80, 0xd2, 0xc4, 0x78, 0xd8, 0xb8, 0x85, 0x42, 0xc1, 0x3b, 0xf2, 0x46, 0x61, 0x32, 0xdb, 0xec,
- 0x57, 0x68, 0x56, 0x6d, 0x8e, 0x35, 0x56, 0x37, 0x92, 0x36, 0x73, 0x6c, 0xcd, 0x63, 0x82, 0x4f,
- 0xda, 0x29, 0xd7, 0x75, 0x8f, 0xef, 0x9a, 0xe3, 0x3d, 0x5c, 0xf5, 0x37, 0xf3, 0xd1, 0x82, 0x55,
- 0xeb, 0xcc, 0xa4, 0x22, 0x5e, 0x72, 0x9b, 0xcd, 0xdb, 0x9d, 0x49, 0x00, 0xeb, 0xe1, 0x43, 0x93,
- 0xdc, 0x5c, 0x18, 0x0a, 0xbb, 0xfb, 0x78, 0x26, 0xaf, 0x0a, 0x6a, 0x11, 0x52, 0xe0, 0xf5, 0xd3,
- 0xbc, 0x5d, 0x32, 0xbe, 0x69, 0xa6, 0x13, 0x67, 0xae, 0xf1, 0x7f, 0x00, 0x0d, 0x5a, 0xaa, 0x8c,
- 0x4a, 0xee, 0x44, 0x27, 0xa3, 0x02, 0x25, 0x7e, 0x5b, 0xb6, 0xcd, 0xd2, 0xea, 0x15, 0x2b, 0x6b,
- 0x9e, 0x66, 0x23, 0x31, 0x80, 0xb7, 0xee, 0x01, 0x80, 0x0d, 0x85, 0x51, 0xd7, 0x10, 0x6d, 0x0e,
- 0x64, 0x38, 0x3e, 0x3b, 0x87, 0x9c, 0x5e, 0xfc, 0xea, 0xb6, 0xd1, 0x9a, 0x46, 0x83, 0x53, 0x14,
- 0x85, 0x13, 0xce, 0x8f, 0x96, 0xf5, 0xa1, 0x6a, 0x2f, 0x68, 0x3f, 0xd4, 0xd7, 0xb2, 0x22, 0x3d,
- 0x3c, 0xf7, 0x0f, 0x90, 0x52, 0x73, 0xbb, 0x17, 0x7c, 0x76, 0xe1, 0x4f, 0x21, 0xed, 0x7a, 0xce,
- 0x0c, 0xf7, 0x7d, 0x38, 0x7f, 0xa3, 0x7b, 0x11, 0xbb, 0x0f, 0x81, 0xbe, 0xde, 0x98, 0x99, 0x0e,
- 0x7e, 0xeb, 0x0a, 0x21, 0x09, 0x32, 0xcf, 0xc2, 0x53, 0x47, 0x45, 0xfa, 0x16, 0x84, 0x3f, 0xf5,
- 0x8b, 0x11, 0x4a, 0x46, 0xa9, 0xbb, 0x5d, 0x2d, 0xa4, 0xeb, 0x6a, 0x8b, 0x5f, 0xc8, 0xab, 0xb1,
- 0xe1, 0xe4, 0x3d, 0x2b, 0xdd, 0x34, 0xd3, 0x35, 0x2a, 0x86, 0xf5, 0x5f, 0xf0, 0xd3, 0xc1, 0x6d,
- 0xd3, 0x6a, 0xec, 0x1d, 0x79, 0x4c, 0xdd, 0xa0, 0x3d, 0x8a, 0x8b, 0xa1, 0xc7, 0x4b, 0x3a, 0x94,
- 0x48, 0x9e, 0x88, 0xfe, 0xfd, 0x1c, 0x32, 0x75, 0xae, 0x7b, 0xaa, 0xe4, 0x06, 0xc8, 0x5a, 0x00,
- 0xc0, 0x66, 0x69, 0x46, 0xd2, 0x45, 0xd7, 0xc0, 0x9b, 0xe7, 0xb5, 0xd6, 0x45, 0x4f, 0xd5, 0x04,
- 0xd1, 0xa3, 0x33, 0xbb, 0x9b, 0x6d, 0xc2, 0xa1, 0xb1, 0x83, 0x5e, 0x9f, 0xd7, 0x94, 0xca, 0xe2,
- 0x7a, 0x00, 0x60, 0xf2, 0x8b, 0x68, 0xe2, 0xb2, 0x4e, 0x83, 0x7a, 0x5b, 0xa0, 0x68, 0xa1, 0xa8,
- 0x51, 0x3d, 0x52, 0x71, 0xe5, 0x04, 0x0e, 0x07, 0x26, 0xec, 0x5e, 0x71, 0xfa, 0x0b, 0x31, 0xbc,
- 0xbb, 0xc2, 0xf7, 0x7e, 0x2b, 0xca, 0xb7, 0xe7, 0x17, 0x24, 0x47, 0x5e, 0x78, 0x86, 0xf7, 0xd7,
- 0xe6, 0x9b, 0x7f, 0x6a, 0x72, 0xb0, 0x36, 0xf0, 0xdd, 0x86, 0x92, 0x01, 0x0e, 0xf3, 0xa0, 0x09,
- 0x4f, 0xd6, 0xbb, 0x68, 0x28, 0x3d, 0x5e, 0x93, 0x09, 0x59, 0x64, 0xa3, 0xa0, 0xad, 0x42, 0x4d,
- 0x65, 0xf7, 0xf4, 0x29, 0xea, 0x4f, 0x67, 0x23, 0xf3, 0x92, 0x3a, 0x08, 0x29, 0xe4, 0xdc, 0x73,
- 0x26, 0xa1, 0xd6, 0x4c, 0x13, 0x82, 0x3d, 0xe1, 0x9b, 0x8f, 0x5e, 0x5c, 0x9e, 0x49, 0xe5, 0x0e,
- 0x63, 0xd4, 0x7e, 0xd5, 0x46, 0x6f, 0xfd, 0xc1, 0x0f, 0x35, 0x3d, 0x37, 0xf8, 0xe3, 0x19, 0xe7,
- 0x7d, 0x3a, 0x79, 0x42, 0x9e, 0xc8, 0xff, 0x91, 0xbd, 0xdc, 0x62, 0xe5, 0xc8, 0x7a, 0xd2, 0x2f,
- 0xd0, 0xbf, 0x01, 0xad, 0x0f, 0x69, 0x54, 0x2e, 0x06, 0x41, 0xd0, 0x2b, 0x12, 0x4f, 0x4a, 0x13,
- 0xcd, 0xe7, 0x04, 0x49, 0x1b, 0x0a, 0x09, 0x11, 0xcc, 0x35, 0x33, 0xb6, 0xb9, 0xec, 0xc9, 0x39,
- 0xf5, 0x5f, 0x30, 0x7a, 0x9d, 0x2f, 0xbf, 0xee, 0xf8, 0xf0, 0x5e, 0x27, 0x3c, 0x82, 0xee, 0xbc,
- 0xc9, 0xa6, 0xec, 0x42, 0x1c, 0x5a, 0x57, 0x50, 0x47, 0xa6, 0x17, 0x2f, 0x68, 0x0a, 0xba, 0xe1,
- 0x8e, 0x39, 0x15, 0xf2, 0x33, 0x41, 0x2d, 0x6c, 0xe2, 0xac, 0x49, 0x81, 0x35, 0x4d, 0xb9, 0xf3,
- 0x0b, 0xf1, 0x49, 0xda, 0x68, 0x91, 0xf5, 0x9a, 0x09, 0x6b, 0x14, 0x49, 0x59, 0x60, 0x64, 0x43,
- 0x71, 0xa3, 0xff, 0xff, 0x82, 0xa7, 0xb9, 0x8d, 0x7d, 0x0d, 0x91, 0x9f, 0x05, 0xb0, 0xdd, 0xa8,
- 0x4b, 0xf5, 0xb7, 0xbd, 0x68, 0xed, 0xce, 0xa9, 0x66, 0x16, 0x67, 0x82, 0xc9, 0x7c, 0x22, 0xe4,
- 0x34, 0xab, 0xb9, 0x34, 0x5a, 0x5f, 0x67, 0x89, 0x34, 0x6b, 0x53, 0x4c, 0x2f, 0xb9, 0xf6, 0x11,
- 0x1e, 0x2f, 0xe3, 0xa6, 0x26, 0x42, 0x45, 0xe1, 0x62, 0x68, 0xbd, 0x16, 0xe1, 0xed, 0x74, 0xfa,
- 0x0c, 0xa5, 0x87, 0xd9, 0xbc, 0x80, 0xe2, 0xb8, 0xc1, 0x53, 0xe7, 0x66, 0x7f, 0x7c, 0x67, 0x1d,
- 0x43, 0x74, 0x9b, 0x94, 0x57, 0xd9, 0xb1, 0x86, 0x0d, 0xa1, 0xcf, 0x07, 0x87, 0x94, 0x0d, 0xca,
- 0xac, 0x01, 0xa5, 0x81, 0x09, 0xfc, 0x0a, 0x62, 0x7a, 0xe5, 0x31, 0xcc, 0xb9, 0x9f, 0xc2, 0x40,
- 0xd3, 0x33, 0xbc, 0x95, 0xce, 0x9f, 0x85, 0xf6, 0xf4, 0xbc, 0x44, 0xe5, 0x20, 0xa8, 0xba, 0x9b,
- 0x5c, 0x7d, 0x58, 0x8c, 0x9f, 0x35, 0xe7, 0x91, 0x64, 0xb8, 0x1f, 0x86, 0xe6, 0xca, 0xe5, 0x73,
- 0x08, 0xe5, 0x0b, 0xd2, 0x7b, 0x98, 0xe1, 0xb8, 0x6d, 0x19, 0x9e, 0xe5, 0xa7, 0x54, 0x7b, 0xdd,
- 0x24, 0x80, 0xd5, 0x6c, 0x27, 0x36, 0x75, 0x0b, 0x57, 0xc7, 0xd8, 0xde, 0xa6, 0xee, 0x02, 0xeb,
- 0xa2, 0x9d, 0xa3, 0xa2, 0x35, 0x5f, 0x65, 0xca, 0x24, 0x9a, 0xe1, 0xe0, 0x99, 0x6a, 0xd1, 0x25,
- 0x50, 0xd6, 0xed, 0x3e, 0x20, 0x52, 0xe6, 0xec, 0x14, 0x41, 0xf7, 0xbb, 0x2c, 0x53, 0x95, 0x70,
- 0x08, 0x02, 0xd3, 0x3c, 0xd2, 0x21, 0xa4, 0x8d, 0xaa, 0xc9, 0x31, 0x8e, 0x9e, 0xc9, 0x9d, 0x40,
- 0x8b, 0x8b, 0xc0, 0x63, 0x5a, 0xeb, 0xcb, 0x71, 0xa9, 0x7b, 0x30, 0xc3, 0xc0, 0xd6, 0x57, 0x00,
- 0x4b, 0x58, 0x9a, 0xce, 0x36, 0xd1, 0x06, 0xfb, 0xc2, 0xcd, 0x34, 0x2f, 0x6d, 0x14, 0x75, 0x46,
- 0xa0, 0xe2, 0x68, 0x9c, 0x5e, 0xcd, 0x13, 0xaf, 0xb4, 0xb3, 0xa3, 0xec, 0x48, 0x3a, 0x17, 0x8d,
- 0x98, 0xe3, 0xdc, 0x41, 0x62, 0x14, 0x17, 0xcc, 0x55, 0x7d, 0xdb, 0xd8, 0x96, 0x07, 0x02, 0xb0,
- 0x2a, 0xb8, 0x71, 0xc2, 0x79, 0x50, 0x5b, 0x7a, 0x84, 0x43, 0x4a, 0xc4, 0x14, 0xd3, 0x18, 0x7e,
- 0x5e, 0x4a, 0x9f, 0x90, 0x0e, 0x37, 0xbf, 0xcf, 0x15, 0xcd, 0xfd, 0x33, 0x91, 0x58, 0xdc, 0x78,
- 0x9e, 0x7f, 0x9a, 0xbc, 0xb5, 0x6e, 0x66, 0xa4, 0xed, 0x7d, 0xd7, 0x51, 0x7b, 0x21, 0x3b, 0x5b,
- 0x2c, 0xc3, 0xa3, 0x4f, 0x33, 0x5c, 0x49, 0xc2, 0x81, 0xf7, 0xc6, 0x78, 0x89, 0x93, 0x2b, 0xd2,
- 0xbf, 0x4b, 0x40, 0x26, 0xf5, 0x39, 0x18, 0xc9, 0x2c, 0xc1, 0xae, 0xb4, 0xa9, 0x20, 0xab, 0x6f,
- 0x89, 0x46, 0x56, 0xb7, 0xc6, 0xfc, 0xbb, 0x3a, 0x15, 0x73, 0x68, 0x12, 0xab, 0xfa, 0x76, 0x1d,
- 0x9f, 0x80, 0x78, 0xdf, 0x1e, 0x52, 0xc5, 0xa1, 0x73, 0xc4, 0x88, 0xf6, 0xb3, 0xe4, 0x94, 0x10,
- 0x1c, 0xe5, 0x70, 0x3f, 0x26, 0xf5, 0x46, 0x78, 0x97, 0xb6, 0xaf, 0x75, 0xf9, 0x2d, 0x5f, 0x13,
- 0x56, 0xb5, 0x27, 0x2e, 0x3c, 0x36, 0x18, 0xad, 0x10, 0x8e, 0xa9, 0x92, 0x39, 0x7d, 0x8b, 0x81,
- 0x43, 0x03, 0xbd, 0x65, 0x22, 0xd3, 0x1b, 0x80, 0xc6, 0xbc, 0xbd, 0x90, 0x1f, 0x59, 0xf8, 0xd7,
- 0xa4, 0xdc, 0x29, 0xfc, 0xd2, 0xb2, 0x73, 0x6b, 0x60, 0xd6, 0x2e, 0xe1, 0x1e, 0xc7, 0x1e, 0xf7,
- 0xea, 0xd1, 0x19, 0xfb, 0x5a, 0x23, 0x57, 0x9d, 0xbf, 0xdb, 0x41, 0xb9, 0x44, 0xe0, 0x8e, 0xe1,
- 0xc9, 0x9b, 0x6c, 0x0b, 0x33, 0xf5, 0x92, 0xe7, 0x33, 0xbc, 0x3b, 0x00, 0x00, 0x3f, 0x22, 0xd5,
- 0x27, 0xf0, 0xf7, 0x9f, 0x9a, 0x88, 0xc3, 0x3f, 0x0d, 0x5c, 0xff, 0x7b, 0x30, 0xd0, 0x58, 0x8d,
- 0xea, 0x52, 0xac, 0x57, 0xa8, 0x7f, 0x19, 0x84, 0x80, 0x70, 0x18, 0x6d, 0xb5, 0x8c, 0xfa, 0x03,
- 0x1c, 0xad, 0x0b, 0x75, 0x3f, 0xe9, 0x19, 0xf0, 0xb2, 0xb9, 0x64, 0xb4, 0xfe, 0xd8, 0x93, 0x09,
- 0xd9, 0x52, 0xde, 0x8a, 0x8d, 0x33, 0xf6, 0xfe, 0x03, 0xd6, 0x6f, 0x4a, 0x57, 0xcb, 0xc7, 0x80,
- 0x2b, 0x10, 0xed, 0xe7, 0x2d, 0x32, 0xf4, 0x15, 0x06, 0xf6, 0xf9, 0xa4, 0x70, 0x69, 0xd2, 0x74,
- 0x91, 0x33, 0xa0, 0xb6, 0xc9, 0x31, 0x8a, 0x46, 0xe3, 0xa9, 0x15, 0x04, 0xc5, 0xc4, 0xec, 0x04,
- 0x53, 0x1b, 0x0e, 0xe0, 0xf2, 0x8d, 0x78, 0x1c, 0xdc, 0x49, 0x91, 0x6f, 0x36, 0xd3, 0xf7, 0xe3,
- 0x3b, 0x69, 0x2a, 0xdb, 0x53, 0xdf, 0x2f, 0xb8, 0xe2, 0xdc, 0x20, 0x67, 0x09, 0x10, 0x81, 0xcf,
- 0xde, 0x25, 0xdd, 0xcf, 0x2d, 0x3c, 0x62, 0xff, 0xaf, 0x7d, 0xb0, 0xbe, 0x1b, 0x09, 0x62, 0xdb,
- 0x45, 0xc9, 0x2c, 0x56, 0x58, 0xe6, 0x2b, 0xed, 0x28, 0x12, 0xe6, 0x92, 0x7d, 0x77, 0x9c, 0x61,
- 0xe7, 0xbc, 0xa7, 0x4b, 0x2d, 0xb1, 0x79, 0xf8, 0x09, 0x6a, 0x7e, 0x9f, 0xf1, 0x68, 0x2c, 0x58,
- 0x4b, 0xa9, 0x28, 0x70, 0x3e, 0x17, 0xa3, 0x5b, 0xaf, 0xc0, 0x1d, 0x9c, 0x12, 0xa5, 0xd5, 0x77,
- 0x20, 0x24, 0x52, 0xcb, 0xd4, 0xbb, 0xd2, 0x1f, 0x6b, 0x0a, 0x60, 0x9c, 0x21, 0xa0, 0x3e, 0xd3,
- 0x1e, 0xf2, 0xae, 0x47, 0xe3, 0xf3, 0x70, 0x6f, 0x02, 0x1b, 0x35, 0xd4, 0xf6, 0x5a, 0xad, 0x94,
- 0xd6, 0xab, 0x1f, 0x52, 0x3f, 0x34, 0xfc, 0x9d, 0x4b, 0x65, 0x1c, 0x23, 0xaa, 0x7a, 0x5a, 0x65,
- 0x15, 0x0e, 0x71, 0xa4, 0x06, 0x18, 0xfc, 0xa6, 0xa4, 0xc3, 0x7f, 0x7c, 0x58, 0x3a, 0xbd, 0x91,
- 0x20, 0xe0, 0xdd, 0xf9, 0x35, 0xe4, 0x2b, 0x06, 0x1c, 0x60, 0x91, 0x1d, 0x8a, 0x3b, 0xea, 0x00,
- 0xb4, 0x2f, 0xcb, 0xd5, 0x92, 0xa4, 0x66, 0xc6, 0x54, 0x60, 0x15, 0x76, 0xbf, 0x9c, 0x73, 0xaf,
- 0x64, 0xab, 0x41, 0xc7, 0x54, 0xbf, 0xca, 0x97, 0xef, 0x1f, 0xc5, 0x55, 0xaf, 0x08, 0x52, 0x36,
- 0x64, 0xf4, 0x29, 0x9f, 0xa8, 0x53, 0xd6, 0x7e, 0x91, 0xd2, 0x17, 0xfa, 0x9e, 0xf7, 0x37, 0x09,
- 0x7d, 0x01, 0xf6, 0xd4, 0x29, 0x8c, 0xfd, 0x56, 0x56, 0x2f, 0x5f, 0xf5, 0xbe, 0x6f, 0xe1, 0xb9,
- 0x82, 0x00, 0x15, 0x1d, 0xdb, 0x4a, 0xde, 0xa1, 0x34, 0x80, 0x2e, 0x4a, 0xc9, 0xc5, 0x06, 0x60,
- 0xd2, 0x80, 0x3a, 0x71, 0x6a, 0x9f, 0x5a, 0x54, 0xa2, 0x2b, 0xf2, 0x0d, 0xcc, 0x46, 0x3e, 0x7c,
- 0x0c, 0x6c, 0x15, 0xe1, 0xe1, 0x5b, 0x3f, 0xe9, 0x76, 0x01, 0x00, 0x60, 0xc2, 0x61, 0x4f, 0xa1,
- 0x0e, 0x50, 0xc4, 0x28, 0xd4, 0xe6, 0x11, 0x2e, 0xcc, 0x8f, 0xf8, 0x40, 0x7a, 0x69, 0x47, 0x58,
- 0xd4, 0x31, 0xb9, 0xe7, 0x85, 0x76, 0xe3, 0x6c, 0x7a, 0x4b, 0xe6, 0x4b, 0x75, 0xe1, 0x6a, 0xa0,
- 0x7c, 0x30, 0xa5, 0x18, 0xc1, 0xb4, 0xf8, 0xc1, 0x3e, 0x13, 0x69, 0x0f, 0xc1, 0xef, 0xe2, 0x8c,
- 0x13, 0x0d, 0xbe, 0x09, 0x1c, 0x00, 0x8d, 0xc8, 0x95, 0x79, 0xe7, 0x18, 0xb2, 0x59, 0xc4, 0x0d,
- 0xba, 0xbe, 0x06, 0x3a, 0x97, 0x42, 0xd7, 0x00, 0x53, 0x49, 0x85, 0xf6, 0xb5, 0x4f, 0x6a, 0x9f,
- 0x81, 0xca, 0x49, 0x2d, 0xb3, 0x28, 0x81, 0x27, 0x8d, 0xec, 0x0a, 0x62, 0x95, 0xce, 0x1d, 0xf9,
- 0x24, 0xd5, 0x87, 0xb1, 0x82, 0x2f, 0xd5, 0x27, 0xb9, 0xbb, 0xb7, 0x36, 0x2d, 0xbc, 0xe7, 0xa7,
- 0xca, 0xf2, 0xaf, 0x61, 0x82, 0x3d, 0x1f, 0x05, 0x3e, 0x0b, 0x61, 0xf0, 0xd6, 0x37, 0x65, 0x61,
- 0xad, 0x5d, 0x4c, 0x4b, 0x3e, 0xee, 0x1e, 0xed, 0xaa, 0x28, 0x27, 0x4c, 0x89, 0x76, 0x84, 0x88,
- 0x46, 0xee, 0x7a, 0x9a, 0x7c, 0x66, 0x80, 0xa9, 0x0c, 0x90, 0xc9, 0x6e, 0x51, 0x33, 0x49, 0xdb,
- 0x2d, 0xde, 0x20, 0x03, 0xc0, 0x07, 0x31, 0x6f, 0xc6, 0x30, 0xd8, 0x3b, 0xdd, 0xe1, 0x51, 0x22,
- 0xb6, 0x73, 0x2a, 0x02, 0x49, 0x5e, 0xa9, 0x63, 0x4f, 0xbd, 0xb6, 0x40, 0x45, 0x79, 0x2f, 0x98,
- 0xd3, 0x72, 0xbd, 0x16, 0xed, 0xa0, 0x29, 0xcb, 0x08, 0xf3, 0x01, 0x48, 0x20, 0xb2, 0x9a, 0x94,
- 0x87, 0xf8, 0x1c, 0x26, 0x76, 0xa5, 0x96, 0x39, 0xd4, 0x12, 0xe2, 0xae, 0x8b, 0x32, 0xde, 0xcc,
- 0x05, 0x02, 0x76, 0x8f, 0x2b, 0x06, 0xc8, 0xfa, 0xe6, 0xd5, 0xbd, 0x79, 0x8d, 0xc3, 0x4d, 0xb4,
- 0x29, 0x9e, 0x24, 0x20, 0x13, 0x5c, 0xc2, 0xec, 0xc4, 0x53, 0x89, 0x6c, 0x25, 0xc0, 0xa9, 0xcc,
- 0xab, 0x09, 0x45, 0x6e, 0x78, 0x50, 0x2d, 0xae, 0xdd, 0x2b, 0xc7, 0xe6, 0x03, 0x15, 0xdc, 0xd6,
- 0x51, 0x58, 0x21, 0x50, 0xc2, 0x32, 0x98, 0x80, 0x7c, 0x37, 0x37, 0x10, 0x3f, 0x08, 0x93, 0x63,
- 0x5c, 0x91, 0x41, 0xe1, 0xd4, 0x6e, 0xaa, 0xaa, 0x37, 0x02, 0x42, 0xc9, 0x81, 0xad, 0x74, 0x34,
- 0x2e, 0x9c, 0xd3, 0x33, 0xf1, 0xe2, 0x28, 0xce, 0x9e, 0x26, 0x66, 0xdf, 0x19, 0x93, 0xea, 0x51,
- 0x51, 0x4f, 0x49, 0x70, 0xc2, 0x77, 0x0d, 0x28, 0xe2, 0x91, 0xf1, 0xf0, 0xe3, 0x54, 0x71, 0x42,
- 0x4b, 0xa7, 0xd1, 0x91, 0x15, 0x0e, 0x4e, 0x3c, 0x6f, 0x13, 0xd5, 0xc9, 0xae, 0xd4, 0x38, 0xef,
- 0xb1, 0x9d, 0x71, 0x58, 0x44, 0xa8, 0xdf, 0xd3, 0x2e, 0x7e, 0x2d, 0x59, 0xc2, 0x4f, 0x07, 0x6c,
- 0xc1, 0xc0, 0x5e, 0xcd, 0x14, 0x49, 0x88, 0x58, 0xc3, 0xa7, 0x55, 0x06, 0xed, 0x40, 0xab, 0xfc,
- 0x31, 0x71, 0xf3, 0x21, 0xad, 0xf4, 0xe9, 0x56, 0x59, 0x16, 0xc2, 0x19, 0xf9, 0x69, 0x67, 0x2c,
- 0xfa, 0xff, 0x36, 0x40, 0x79, 0x9c, 0x8f, 0xf7, 0xd8, 0xae, 0x03, 0x0b, 0x4b, 0x90, 0xad, 0x46,
- 0xbb, 0x90, 0x17, 0xad, 0xfb, 0xd8, 0xed, 0x87, 0xa8, 0xad, 0x9b, 0x20, 0x2d, 0xc0, 0x1f, 0x87,
- 0xe3, 0x8c, 0x7a, 0x34, 0x36, 0xc1, 0x33, 0x66, 0xad, 0x37, 0xd9, 0x94, 0xe0, 0x82, 0xbd, 0xca,
- 0xa9, 0xf5, 0xcc, 0xc0, 0xf5, 0x9a, 0xbf, 0xfa, 0x1b, 0x92, 0x39, 0x94, 0x29, 0x58, 0xd3, 0x87,
- 0x7c, 0x02, 0x54, 0xe0, 0x07, 0xbc, 0x3a, 0xb9, 0xd4, 0x16, 0x5a, 0x66, 0x96, 0x45, 0xe8, 0xed,
- 0x20, 0x2e, 0xf3, 0x60, 0x3e, 0x28, 0x1c, 0xfb, 0xd9, 0x20, 0xf2, 0x6b, 0x8c, 0x3b, 0x3e, 0x19,
- 0x3d, 0x3a, 0xad, 0xe5, 0xe6, 0x3d, 0x14, 0x04, 0x46, 0x39, 0xef, 0xba, 0x6f, 0x90, 0x9c, 0x3a,
- 0x2d, 0x34, 0x80, 0xbb, 0x8a, 0xbe, 0xe2, 0xd0, 0x9e, 0x06, 0xfb, 0xc8, 0xd6, 0x10, 0x19, 0xd3,
- 0x16, 0xd0, 0x3e, 0xa9, 0x7a, 0x54, 0xec, 0xa4, 0x11, 0x61, 0xbb, 0xc1, 0x16, 0x30, 0xa5, 0xe8,
- 0x70, 0xfb, 0x7d, 0xaf, 0x16, 0x36, 0x4e, 0xd7, 0x90, 0x2e, 0xc3, 0x80, 0x4b, 0xa0, 0xf0, 0x64,
- 0x4b, 0xa2, 0x6f, 0x19, 0x1a, 0x8a, 0x53, 0x86, 0xf5, 0x58, 0x81, 0xe1, 0x85, 0xc6, 0xe0, 0x7e,
- 0x1e, 0xf0, 0x53, 0x45, 0x52, 0x08, 0xbc, 0x42, 0xc2, 0x99, 0x4b, 0xc8, 0x7f, 0xbe, 0xb6, 0xdc,
- 0x80, 0xd9, 0xe7, 0x4d, 0x4f, 0x29, 0x24, 0xca, 0x5f, 0x32, 0xf7, 0x65, 0xad, 0x66, 0xf6, 0x24,
- 0x7e, 0x91, 0xae, 0xbc, 0xfb, 0xea, 0x8b, 0x1a, 0x8a, 0x37, 0xc2, 0x47, 0x4f, 0xe9, 0xdd, 0xcd,
- 0x4b, 0x10, 0x23, 0x7b, 0xee, 0x0f, 0x54, 0x09, 0x77, 0xd3, 0x67, 0xe1, 0x54, 0x20, 0x51, 0x2b,
- 0xfa, 0xc7, 0x9a, 0xec, 0xfe, 0x28, 0x1c, 0xc7, 0x96, 0x75, 0x8c, 0x6d, 0x07, 0xf5, 0xa2, 0xb9,
- 0x55, 0x74, 0xd1, 0x43, 0x5e, 0x52, 0x6c, 0xfb, 0xf1, 0xcb, 0x4a, 0x47, 0x2a, 0xe8, 0xf9, 0x5e,
- 0x89, 0x43, 0x51, 0x3c, 0x3e, 0xe1, 0xd2, 0xa4, 0x6e, 0xe2, 0x3f, 0x4c, 0x52, 0x17, 0x93, 0xd1,
- 0x2e, 0x63, 0xd4, 0x4e, 0x59, 0xd6, 0x9f, 0xa8, 0x9d, 0x2e, 0x04, 0x76, 0x06, 0x40, 0x9f, 0xe4,
- 0xc8, 0x11, 0xcb, 0x78, 0xf3, 0xf5, 0x66, 0xd9, 0xce, 0xe7, 0x1f, 0x43, 0x93, 0x7a, 0xca, 0xe5,
- 0x6d, 0x00, 0xfc, 0x18, 0xf6, 0xc4, 0xe3, 0x92, 0x2d, 0x46, 0xd4, 0x95, 0x70, 0x95, 0xae, 0x70,
- 0x8a, 0x78, 0xf4, 0x94, 0x74, 0x8f, 0x39, 0x8e, 0x7e, 0xdd, 0xc7, 0x69, 0x1a, 0x55, 0x77, 0xde,
- 0xff, 0xbb, 0x9a, 0x86, 0x43, 0x19, 0x78, 0xca, 0xbd, 0xff, 0x26, 0x88, 0xd9, 0xf7, 0x9f, 0x01,
- 0x37, 0xc4, 0x5c, 0xfc, 0xe6, 0x3f, 0x02, 0x01, 0x94, 0x90, 0xa4, 0xd2, 0xa2, 0xb4, 0xc0, 0x1a,
- 0xe5, 0x2e, 0xcf, 0x3a, 0x2e, 0x20, 0xb5, 0x40, 0xf7, 0x93, 0x82, 0x41, 0x9e, 0xfc, 0xeb, 0x02,
- 0xc6, 0x92, 0x07, 0xdb, 0x07, 0x3e, 0xe7, 0x8f, 0x9d, 0x2d, 0xff, 0x6d, 0x5f, 0x20, 0xee, 0x61,
- 0x15, 0xd8, 0xc1, 0xcc, 0xf0, 0x43, 0xdc, 0xe6, 0x70, 0xfd, 0x63, 0x76, 0xae, 0x09, 0xcb, 0x4d,
- 0x0a, 0x2c, 0x3c, 0x9f, 0xfe, 0xca, 0xb2, 0x5f, 0x1d, 0x37, 0xe9, 0x52, 0xcd, 0x90, 0x79, 0x45,
- 0x0f, 0x87, 0x3a, 0xb4, 0xd7, 0x90, 0xdd, 0x3e, 0x94, 0xf9, 0x51, 0x75, 0xdc, 0xff, 0xd9, 0xec,
- 0x4b, 0x6f, 0x61, 0x4d, 0xcb, 0x88, 0xf6, 0xaa, 0x78, 0xb1, 0xa1, 0xd4, 0xb1, 0xa6, 0x41, 0xdf,
- 0x96, 0xef, 0x16, 0x31, 0x49, 0x58, 0x7b, 0xdc, 0x94, 0x18, 0x8d, 0x15, 0xad, 0xff, 0x81, 0xa9,
- 0x66, 0x22, 0x12, 0x84, 0x9e, 0x59, 0xd3, 0x13, 0xcb, 0xad, 0x27, 0x3b, 0xbe, 0x2b, 0x2b, 0xaf,
- 0x2e, 0xfe, 0x6f, 0x73, 0x5f, 0x8c, 0xd2, 0x83, 0x5d, 0x60, 0xbc, 0x3b, 0xf5, 0x77, 0xdc, 0xe4,
- 0x03, 0xbe, 0xce, 0x8b, 0xf4, 0x28, 0x56, 0x53, 0x20, 0x2d, 0x7c, 0x8e, 0x66, 0x69, 0x4b, 0x12,
- 0xc4, 0x6e, 0xff, 0x6b, 0x6a, 0x0e, 0xba, 0x0a, 0x99, 0x43, 0xe3, 0x74, 0xf0, 0xe8, 0x5d, 0x3c,
- 0x32, 0x01, 0x3d, 0xf4, 0x96, 0xcd, 0x37, 0x69, 0xd3, 0x86, 0x71, 0xce, 0x58, 0xd9, 0xf2, 0x3d,
- 0xd8, 0x1b, 0xa0, 0x27, 0xcd, 0xd7, 0xb1, 0xcf, 0xac, 0xf1, 0x1f, 0x00, 0x8a, 0x84, 0x57, 0x1c,
- 0x47, 0xac, 0x31, 0x14, 0xf7, 0x06, 0x86, 0xcc, 0x4e, 0x00, 0x3e, 0x5b, 0xdf, 0x87, 0xe7, 0x98,
- 0x26, 0xd6, 0x90, 0xd5, 0x89, 0xa0, 0xcb, 0xa9, 0x58, 0x60, 0xfb, 0xd5, 0xc8, 0x1c, 0x85, 0x54,
- 0x5b, 0xf7, 0x2c, 0xde, 0xd9, 0x3c, 0xd1, 0xca, 0xfb, 0xc2, 0x71, 0x51, 0xe7, 0x91, 0xb0, 0x6d,
- 0x65, 0xea, 0x84, 0xd1, 0x3b, 0x4b, 0xb0, 0xd4, 0x2e, 0xe5, 0xc8, 0xcc, 0x4a, 0x0e, 0xc1, 0x73,
- 0x4d, 0x3b, 0x55, 0xfc, 0x96, 0xeb, 0xfa, 0x79, 0xd2, 0xe9, 0xe3, 0xfa, 0xef, 0x2c, 0x6f, 0xbf,
- 0x1a, 0x27, 0x4d, 0x3e, 0x35, 0x3a, 0x76, 0xbe, 0xde, 0xe7, 0x4a, 0x00, 0x5e, 0xf9, 0x7b, 0xcf,
- 0xb4, 0x17, 0x1e, 0xc6, 0x67, 0x5e, 0xb1, 0x65, 0xb5, 0x49, 0xba, 0xdc, 0xd3, 0x39, 0x7d, 0xab,
- 0x47, 0x42, 0x0a, 0xfa, 0x73, 0xb4, 0x25, 0x41, 0xbc, 0xb4, 0xfe, 0x38, 0xd1, 0xed, 0xc6, 0x64,
- 0x96, 0xe6, 0x61, 0x41, 0xfd, 0xfc, 0x6f, 0xd0, 0x03, 0xe9, 0x2d, 0x02, 0x06, 0xdc, 0x67, 0xf4,
- 0xbf, 0x8a, 0xaf, 0x0d, 0x47, 0x66, 0x77, 0xed, 0x12, 0x4c, 0x85, 0x23, 0xf7, 0xc4, 0x91, 0x8a,
- 0x9a, 0x18, 0xd2, 0x38, 0x8f, 0x16, 0xb4, 0xe5, 0xc1, 0xff, 0x72, 0xa6, 0x05, 0x3a, 0xa0, 0x30,
- 0x83, 0x78, 0x2f, 0xe4, 0x68, 0xbd, 0xbe, 0x6e, 0xce, 0x11, 0x82, 0x3c, 0x43, 0x66, 0xa0, 0xf4,
- 0x25, 0x59, 0xdd, 0xd5, 0x85, 0xd6, 0x0a, 0xdc, 0x0a, 0x51, 0x3c, 0xe7, 0xb4, 0x66, 0x87, 0xfe,
- 0x69, 0x75, 0xc1, 0x33, 0x5b, 0xce, 0x89, 0x76, 0xa8, 0x51, 0xd2, 0x6d, 0x6f, 0x07, 0x88, 0x7f,
- 0xe0, 0xfa, 0xbf, 0x1b, 0x00, 0x64, 0x19, 0xc1, 0x48, 0x35, 0x6f, 0x8d, 0x64, 0x9e, 0xc1, 0x5d,
- 0xee, 0x1b, 0xa7, 0xf3, 0xcd, 0xff, 0x40, 0x1a, 0xac, 0xd0, 0xc9, 0x76, 0xfe, 0xdf, 0xca, 0x49,
- 0x9b, 0xb0, 0xdd, 0x2f, 0x7d, 0x1f, 0x3c, 0x7c, 0x85, 0xf9, 0x49, 0x9c, 0x01, 0x28, 0x1c, 0xfe,
- 0x73, 0x5c, 0xc7, 0x3c, 0xa0, 0xeb, 0xd8, 0xc6, 0x2b, 0x80, 0xe7, 0x66, 0x57, 0xa2, 0x2c, 0xd1,
- 0x5c, 0x34, 0x3e, 0x66, 0xeb, 0xee, 0xca, 0x78, 0x4f, 0x96, 0xeb, 0x00, 0x5c, 0x42, 0x21, 0x7f,
- 0x9e, 0xee, 0xdd, 0xca, 0x5f, 0x4f, 0x46, 0x6c, 0x68, 0x5f, 0xbf, 0x6e, 0xa7, 0x38, 0x9b, 0x3a,
- 0xa1, 0xfd, 0xf8, 0xdd, 0xa1, 0x66, 0x12, 0x36, 0x3c, 0x81, 0xc5, 0x80, 0x9b, 0xf2, 0x52, 0x0e,
- 0xac, 0xf4, 0xbc, 0xc2, 0x6d, 0x48, 0x0c, 0x90, 0x41, 0xab, 0xa8, 0xce, 0xdd, 0x72, 0x3a, 0x59,
- 0x3a, 0x5c, 0xd4, 0xff, 0x76, 0xef, 0x05, 0x8e, 0x33, 0xf9, 0x63, 0x5c, 0x32, 0x52, 0x8a, 0xf0,
- 0xd3, 0x09, 0x77, 0x02, 0x34, 0x25, 0x23, 0x3c, 0x90, 0x01, 0x74, 0xdc, 0x6e, 0x78, 0x58, 0x90,
- 0x63, 0x4b, 0x8d, 0x38, 0x7a, 0x4a, 0x3f, 0x19, 0x4f, 0xfb, 0xdb, 0x31, 0x2c, 0xac, 0xd9, 0x84,
- 0x4d, 0x27, 0x4f, 0x9b, 0xdc, 0x97, 0xdd, 0xae, 0x6a, 0x97, 0xf3, 0x9e, 0xe6, 0xf2, 0xf9, 0x68,
- 0x68, 0xd1, 0x68, 0x4e, 0x1b, 0x78, 0xdd, 0xa6, 0xec, 0xf2, 0xe0, 0xf2, 0xa0, 0xc2, 0x74, 0xff,
- 0x62, 0xdd, 0xdf, 0xa0, 0x56, 0x86, 0x09, 0x89, 0x4b, 0x14, 0x61, 0x9a, 0x5a, 0x08, 0x14, 0xb2,
- 0xad, 0x6e, 0x5e, 0x4b, 0x55, 0x95, 0x11, 0x21, 0x8f, 0xbb, 0x01, 0xe7, 0x76, 0x18, 0x7a, 0x88,
- 0x0d, 0x36, 0xa4, 0x84, 0x0d, 0xbd, 0xa9, 0x1f, 0xf4, 0x78, 0x82, 0x72, 0xc2, 0x0c, 0x4c, 0xa2,
- 0x9b, 0x9a, 0xbe, 0xf7, 0x8e, 0xc4, 0xf1, 0xe3, 0xfe, 0xf8, 0x1a, 0x8f, 0xb8, 0xca, 0x2f, 0xb3,
- 0xf3, 0xb3, 0xc7, 0xfd, 0x05, 0x30, 0x1a, 0xc9, 0x03, 0x0c, 0xe2, 0x9e, 0xa3, 0x86, 0x45, 0x20,
- 0x78, 0x3a, 0xa4, 0xd6, 0xfb, 0xd7, 0xda, 0xe0, 0x1c, 0xe9, 0x85, 0x42, 0xa5, 0xab, 0xdf, 0x69,
- 0x8e, 0x45, 0xe6, 0x67, 0x0f, 0xc9, 0xd0, 0x20, 0xfd, 0xf5, 0x84, 0x00, 0xd3, 0x9c, 0xb9, 0x08,
- 0xe9, 0x75, 0xfe, 0xe9, 0x69, 0x79, 0x08, 0xb9, 0xc1, 0x3c, 0x46, 0x87, 0x02, 0xfc, 0x72, 0x65,
- 0x22, 0x2a, 0x76, 0x59, 0xcb, 0xd0, 0x70, 0xcf, 0xc7, 0xae, 0xd2, 0x34, 0x1d, 0x43, 0x8d, 0x47,
- 0x76, 0x10, 0x73, 0xf1, 0x84, 0x4c, 0x8d, 0x61, 0x5b, 0x42, 0x96, 0xdd, 0xa9, 0x1e, 0x47, 0x68,
- 0x22, 0xca, 0x3f, 0xfe, 0xb4, 0xfe, 0x80, 0xec, 0xcb, 0x1e, 0xa3, 0xbf, 0x77, 0x84, 0x04, 0x72,
- 0x48, 0x7a, 0xcf, 0x0a, 0xda, 0xe8, 0x24, 0xab, 0x58, 0x79, 0x3a, 0x9f, 0x33, 0x02, 0x82, 0xe7,
- 0x38, 0xe9, 0x31, 0x2e, 0x7a, 0x65, 0x25, 0x70, 0xfc, 0xe6, 0x93, 0x94, 0xf4, 0xfa, 0x20, 0x2a,
- 0xaa, 0x64, 0x85, 0xf7, 0xac, 0x7f, 0xdc, 0xc0, 0x0b, 0xa4, 0x34, 0x94, 0x33, 0xd9, 0x35, 0x35,
- 0x4c, 0x84, 0x55, 0x87, 0x7b, 0xa3, 0xb8, 0x55, 0x26, 0xec, 0x1d, 0x8e, 0xf6, 0x5d, 0x0b, 0x52,
- 0x37, 0x29, 0x69, 0x18, 0x2d, 0xcf, 0x37, 0xf9, 0x9d, 0x3d, 0x85, 0x4a, 0x81, 0xab, 0xd0, 0x2b,
- 0x2a, 0x0a, 0x8e, 0x17, 0xf9, 0x91, 0xfe, 0x91, 0x07, 0xfd, 0xe6, 0x2a, 0x07, 0xa1, 0x53, 0x06,
- 0xdf, 0x8f, 0x90, 0xb4, 0xbd, 0xfe, 0x8b, 0x93, 0xd8, 0xa2, 0x4c, 0x6a, 0xba, 0x0a, 0x6d, 0x09,
- 0x93, 0xb3, 0xaf, 0xd5, 0x5a, 0xad, 0xac, 0x97, 0x03, 0x1d, 0xea, 0x00, 0x1a, 0x60, 0x24, 0x6a,
- 0x5d, 0xcb, 0xa3, 0xd9, 0xd7, 0x67, 0xb3, 0xea, 0x21, 0x49, 0xc7, 0x14, 0x5a, 0x43, 0x68, 0xa6,
- 0x2e, 0xd7, 0xbf, 0x42, 0x95, 0x4c, 0x2e, 0xa6, 0x9e, 0xac, 0xf6, 0xf6, 0xb2, 0xb7, 0xe6, 0xa9,
- 0x3c, 0x7d, 0xd6, 0x74, 0x31, 0x7b, 0x9c, 0xab, 0x31, 0x33, 0xfc, 0xce, 0x39, 0x9b, 0x28, 0xd6,
- 0xd2, 0x97, 0x6c, 0xb4, 0xb4, 0x16, 0xd1, 0x9d, 0xff, 0x17, 0x0b, 0x49, 0x33, 0xec, 0x74, 0x49,
- 0x44, 0xa5, 0xa1, 0x24, 0x9a, 0x34, 0x77, 0x50, 0x2c, 0x4a, 0x25, 0x40, 0x64, 0xb3, 0x1a, 0x50,
- 0x0d, 0x0b, 0x1e, 0xca, 0xb5, 0x55, 0x68, 0x84, 0x9c, 0x4f, 0xdc, 0x68, 0xea, 0x9b, 0x58, 0x9a,
- 0x8d, 0x73, 0x9e, 0x82, 0xff, 0x39, 0xca, 0x76, 0x57, 0x7a, 0x7d, 0x3a, 0x71, 0x8c, 0x61, 0x5e,
- 0x20, 0x03, 0x58, 0xd5, 0x9f, 0x75, 0x1a, 0xec, 0xfb, 0x00, 0x81, 0x38, 0xdf, 0x0e, 0x43, 0x80,
- 0x05, 0xe0, 0xc9, 0xa0, 0xec, 0xe2, 0x6a, 0x5d, 0xbc, 0x46, 0xb4, 0xce, 0xf2, 0xdc, 0x3e, 0x99,
- 0x32, 0xd1, 0x3e, 0xf6, 0xd7, 0x88, 0x1f, 0xb8, 0x6a, 0x10, 0x2e, 0x7a, 0xd1, 0x51, 0xcb, 0xe4,
- 0x72, 0xd8, 0x12, 0x5d, 0x81, 0xf8, 0x66, 0x76, 0x94, 0x9f, 0x15, 0xce, 0x62, 0xa6, 0x63, 0x15,
- 0x85, 0x89, 0x6c, 0xbb, 0x18, 0x5d, 0xdf, 0x67, 0xdc, 0xc6, 0x23, 0xae, 0xb9, 0xa6, 0x0b, 0x65,
- 0xf4, 0xb0, 0xd6, 0x16, 0xf4, 0xae, 0xbe, 0x03, 0x04, 0xc6, 0xfa, 0x2a, 0x67, 0x07, 0x53, 0x0d,
- 0xb3, 0x9b, 0x73, 0x59, 0xa5, 0x17, 0x0c, 0x0b, 0x15, 0x25, 0xda, 0x3f, 0xe1, 0x89, 0x89, 0x09,
- 0xe6, 0x50, 0xec, 0x38, 0xc5, 0x4e, 0xae, 0xbd, 0xe7, 0x09, 0x7a, 0xc5, 0x3a, 0x09, 0xa5, 0xac,
- 0x22, 0x78, 0xca, 0x7b, 0xca, 0xe0, 0xee, 0x74, 0x61, 0xdb, 0xf5, 0xaf, 0xfb, 0x31, 0x08, 0x84,
- 0xb7, 0x63, 0xa6, 0x25, 0xc2, 0x0f, 0x2a, 0x6d, 0xf4, 0x4c, 0xf4, 0xae, 0x71, 0xe5, 0x9b, 0x1f,
- 0xd5, 0x1b, 0x76, 0x7b, 0xc7, 0xa1, 0x84, 0xdb, 0xa6, 0x4a, 0x82, 0xbe, 0x0c, 0x5d, 0xb4, 0x3a,
- 0x81, 0xb8, 0x75, 0x76, 0x72, 0xd8, 0xd4, 0x51, 0x86, 0x90, 0x28, 0x0f, 0xe6, 0xc8, 0xe3, 0xc3,
- 0xaf, 0x92, 0xa8, 0x36, 0xb2, 0x17, 0x65, 0x27, 0x87, 0xca, 0xe5, 0xdd, 0xea, 0x9a, 0x56, 0xaf,
- 0xf3, 0x1b, 0xa6, 0xd3, 0xbc, 0xb1, 0x60, 0xb4, 0x1c, 0xd1, 0xff, 0x6f, 0x25, 0x3e, 0x4d, 0x62,
- 0x14, 0x25, 0x27, 0xbd, 0x41, 0x76, 0xea, 0xeb, 0xb0, 0x01, 0xaa, 0xce, 0x4f, 0xe4, 0xd9, 0x0c,
- 0x6e, 0x4d, 0xe8, 0x83, 0x19, 0xf3, 0x34, 0x65, 0x47, 0x4b, 0x74, 0x91, 0x6b, 0xac, 0xcc, 0x2c,
- 0xe3, 0x6e, 0xef, 0x22, 0x74, 0x29, 0x9a, 0xc9, 0xe3, 0x58, 0xfa, 0xe0, 0x92, 0x0e, 0x65, 0x74,
- 0x58, 0x98, 0x2f, 0x61, 0x72, 0x29, 0xd3, 0x2e, 0x6d, 0x72, 0x5b, 0xc4, 0x45, 0x15, 0xd9, 0xca,
- 0xfe, 0x35, 0x3c, 0xf0, 0x18, 0xfc, 0xa5, 0xa9, 0x56, 0x4d, 0x80, 0xc9, 0xcd, 0xb5, 0x2c, 0x7c,
- 0x02, 0xff, 0x22, 0x4a, 0x1b, 0xef, 0x03, 0xe6, 0xd8, 0xfd, 0x68, 0x9d, 0x32, 0xdc, 0x92, 0x9f,
- 0x83, 0xef, 0xfb, 0xcc, 0xad, 0xfa, 0x27, 0x40, 0x2f, 0x17, 0x70, 0x5c, 0x0b, 0x78, 0xac, 0x5f,
- 0x9f, 0x72, 0xdb, 0x02, 0x24, 0xe6, 0x15, 0x1c, 0x35, 0xa3, 0xff, 0xff, 0x5c, 0xaf, 0x2e, 0x80,
- 0x03, 0x6f, 0x1f, 0x68, 0x35, 0x5d, 0x5a, 0xf3, 0x9e, 0x1e, 0xa5, 0x72, 0x50, 0x45, 0x43, 0x4e,
- 0x4a, 0x1e, 0x7f, 0x29, 0x39, 0xf7, 0xa8, 0x6d, 0x44, 0x40, 0x7e, 0x09, 0x53, 0x25, 0xb8, 0x82,
- 0xec, 0xa6, 0x79, 0x73, 0xf2, 0x9c, 0x57, 0xd8, 0xd6, 0x1b, 0x80, 0x84, 0x63, 0x47, 0xcb, 0xa8,
- 0x76, 0xd4, 0x4f, 0x18, 0xeb, 0xa0, 0xc8, 0xdd, 0xb4, 0x1d, 0xc5, 0xb0, 0x4d, 0x11, 0xaa, 0xdc,
- 0x94, 0x73, 0xf9, 0x33, 0x68, 0x43, 0x77, 0x71, 0x08, 0xde, 0xa1, 0x80, 0xeb, 0x42, 0xad, 0x44,
- 0x34, 0xf3, 0x13, 0x05, 0x7c, 0x1c, 0x9c, 0x34, 0xc6, 0xb5, 0x8f, 0xe7, 0xb3, 0xf8, 0x75, 0x0a,
- 0x28, 0x8b, 0x6b, 0x5f, 0xc8, 0xd5, 0x4e, 0x40, 0xfc, 0xc1, 0x20, 0xf4, 0xe9, 0x90, 0x74, 0x4c,
- 0x84, 0x4b, 0x10, 0xd8, 0x6f, 0xbf, 0xc7, 0x3c, 0xab, 0x3f, 0xec, 0xa2, 0xbf, 0x09, 0xf4, 0xf4,
- 0x35, 0xaa, 0xbb, 0x02, 0x21, 0x86, 0x83, 0xc6, 0x06, 0x9c, 0x10, 0x5c, 0x65, 0xc6, 0x06, 0x7a,
- 0xa7, 0xd5, 0x71, 0x2d, 0x5b, 0xc4, 0xdf, 0x70, 0xe3, 0x46, 0x81, 0x2c, 0x98, 0xd0, 0xb3, 0x72,
- 0x9c, 0xe4, 0xfd, 0xec, 0x69, 0x49, 0x57, 0x9c, 0xf0, 0x49, 0x55, 0x31, 0x19, 0xaa, 0xf7, 0xc8,
- 0x53, 0xe5, 0xb6, 0xc4, 0xd7, 0x3c, 0xab, 0xc7, 0x98, 0x4b, 0x63, 0x3b, 0xd6, 0x7f, 0x98, 0xef,
- 0x1e, 0x0d, 0xa8, 0xaa, 0xca, 0x79, 0xb4, 0xb0, 0x89, 0x50, 0xbf, 0x6f, 0x42, 0x9b, 0x16, 0x66,
- 0x86, 0xf6, 0x6a, 0x4a, 0x64, 0x9b, 0x1a, 0x9d, 0x33, 0x17, 0x2e, 0x4e, 0xdc, 0xa2, 0x7a, 0xfa,
- 0x17, 0xca, 0x33, 0x9e, 0xe7, 0xdd, 0x0c, 0x13, 0x3b, 0xf2, 0xc9, 0x8d, 0xc6, 0xae, 0x2d, 0x6f,
- 0x3e, 0xdc, 0xcb, 0x7f, 0xdd, 0xf0, 0x1e, 0x1b, 0xa3, 0xc7, 0x8f, 0x61, 0x94, 0xfb, 0x8c, 0xdf,
- 0xce, 0x5a, 0xac, 0x2b, 0x40, 0x98, 0x55, 0x93, 0xe8, 0xb5, 0x2a, 0x4c, 0xa0, 0x20, 0x00, 0x36,
- 0x2f, 0x17, 0x7f, 0x63, 0x48, 0xf6, 0xbc, 0x3b, 0xc2, 0x20, 0x17, 0x1a, 0x56, 0x3d, 0x68, 0x6d,
- 0xd7, 0x75, 0xd1, 0x9b, 0xf1, 0x62, 0x2d, 0xf9, 0x98, 0xe8, 0x7f, 0xf8, 0x63, 0xf8, 0x9f, 0x3c,
- 0x76, 0xd4, 0x91, 0x1a, 0x9b, 0x73, 0x30, 0xd8, 0xf6, 0xf5, 0x58, 0xac, 0xb4, 0x29, 0xda, 0xa1,
- 0x66, 0xfe, 0x1f, 0x49, 0x0f, 0x66, 0xa1, 0x4f, 0x31, 0x3b, 0x65, 0x93, 0xf8, 0x19, 0x2d, 0xe0,
- 0x8b, 0x79, 0xcf, 0x4a, 0x20, 0x2c, 0x52, 0x61, 0x37, 0x7c, 0xae, 0x8a, 0x52, 0xd4, 0x66, 0x50,
- 0xa7, 0xd9, 0x20, 0x96, 0x3f, 0xa5, 0x17, 0x31, 0x93, 0x29, 0xbc, 0xdb, 0x18, 0x6f, 0xdb, 0xc6,
- 0x0a, 0xa6, 0xb0, 0x0d, 0x41, 0xc1, 0x37, 0xab, 0x1e, 0xa4, 0x75, 0xe7, 0x33, 0x9d, 0x1a, 0x90,
- 0x29, 0x6e, 0x4e, 0x85, 0x57, 0x4b, 0x64, 0x0d, 0x7e, 0x98, 0x19, 0xa8, 0x1a, 0x84, 0xc9, 0x2b,
- 0xac, 0x83, 0x66, 0x28, 0x09, 0x2c, 0x8e, 0x16, 0x91, 0x13, 0xf5, 0x1a, 0x5e, 0xcc, 0xc7, 0x60,
- 0xfb, 0xea, 0x8f, 0xa5, 0x77, 0xf4, 0xa3, 0x31, 0xb8, 0x5f, 0x7a, 0x0a, 0xd7, 0x19, 0x13, 0x17,
- 0x5c, 0xc3, 0x64, 0x21, 0xba, 0x27, 0xef, 0xc9, 0xf9, 0xab, 0x51, 0x8d, 0x5a, 0x44, 0x4c, 0x79,
- 0x34, 0x05, 0xe0, 0xf7, 0x5b, 0xc8, 0x8e, 0xe7, 0xcf, 0x91, 0xe9, 0x35, 0x75, 0x0b, 0xc5, 0x5b,
- 0xad, 0xbd, 0x2e, 0xe6, 0xe2, 0x42, 0x70, 0x3d, 0x6d, 0xc4, 0x4b, 0xe1, 0x9c, 0x9c, 0x22, 0x9b,
- 0x9e, 0x85, 0x66, 0x85, 0x81, 0xf7, 0x3e, 0xf5, 0x59, 0x79, 0x6d, 0x2e, 0xc8, 0x80, 0x12, 0xd5,
- 0x53, 0xc7, 0x56, 0x61, 0xb2, 0xf9, 0x94, 0x86, 0xe3, 0xfd, 0x2b, 0x99, 0xdc, 0xeb, 0xb8, 0xeb,
- 0x73, 0xe0, 0xd7, 0xe2, 0xdc, 0xe8, 0x5d, 0x9e, 0x13, 0x5f, 0x66, 0x4e, 0x89, 0x4b, 0x41, 0x3d,
- 0xdf, 0xb8, 0x70, 0xe6, 0xce, 0xb3, 0x54, 0x91, 0xec, 0x53, 0x97, 0x6c, 0x01, 0xb2, 0xc8, 0x89,
- 0x9d, 0xad, 0x24, 0xfc, 0x58, 0x63, 0xc8, 0x4b, 0x39, 0xfb, 0xe4, 0x6a, 0x76, 0x9c, 0x11, 0x06,
- 0x37, 0x73, 0xc0, 0x35, 0x9a, 0x36, 0x62, 0x70, 0xe9, 0xb6, 0xc6, 0x9f, 0x53, 0xcf, 0x5d, 0x39,
- 0x13, 0x48, 0x49, 0x5c, 0xbb, 0xfd, 0x05, 0x2f, 0xb5, 0x00, 0x16, 0xe6, 0x59, 0x8c, 0x05, 0x86,
- 0xaf, 0x25, 0xe5, 0x4d, 0x64, 0x6f, 0x73, 0x6b, 0x8e, 0xad, 0x06, 0x37, 0x03, 0xaa, 0xa9, 0x0e,
- 0x39, 0x73, 0xac, 0xdd, 0x52, 0x5c, 0xea, 0x1e, 0x07, 0x6a, 0x7a, 0x58, 0x32, 0x84, 0xbb, 0x78,
- 0xa4, 0xa9, 0x7c, 0xfa, 0xcc, 0xa8, 0xa0, 0x10, 0xcf, 0x8c, 0xbd, 0x36, 0x34, 0x03, 0x6d, 0xe8,
- 0xba, 0xd5, 0x17, 0x88, 0x51, 0xb1, 0x8f, 0xd8, 0x8d, 0x4a, 0xa4, 0xf8, 0x19, 0xb6, 0x69, 0x68,
- 0xa8, 0x03, 0x89, 0x18, 0x99, 0xdb, 0x82, 0xd9, 0x78, 0x97, 0x6e, 0x31, 0xcb, 0xc3, 0x18, 0x8b,
- 0xc9, 0x2a, 0x3c, 0x4d, 0x64, 0x95, 0x88, 0x86, 0x4a, 0xca, 0xc3, 0xa5, 0x9a, 0x9b, 0xf4, 0xcf,
- 0x73, 0x0a, 0xb2, 0xd8, 0x33, 0x5a, 0x02, 0x84, 0xaa, 0xdd, 0x4f, 0xc6, 0xdf, 0x68, 0xca, 0xe0,
- 0x29, 0x73, 0x30, 0xd0, 0xe6, 0x9e, 0x5a, 0xb6, 0xb4, 0x4f, 0x09, 0xa8, 0x19, 0x3f, 0x90, 0xba,
- 0x73, 0x8c, 0xa5, 0xb8, 0x7d, 0xc4, 0x82, 0xb5, 0xfa, 0x3c, 0x00, 0x1b, 0xac, 0x94, 0x28, 0x89,
- 0x43, 0x0d, 0xbd, 0x88, 0x9d, 0xc7, 0xe4, 0xd9, 0xdc, 0x62, 0x8a, 0x5d, 0x39, 0x45, 0xa1, 0x12,
- 0xc9, 0xb0, 0x2f, 0x53, 0xf6, 0xd9, 0xee, 0xd6, 0x7a, 0xcf, 0x2f, 0xab, 0xdb, 0xa3, 0xec, 0x4a,
- 0x69, 0xa3, 0x77, 0x73, 0x84, 0x9f, 0x4b, 0x27, 0xfc, 0x01, 0xe1, 0x95, 0x92, 0xc7, 0x0c, 0x88,
- 0x88, 0xaa, 0x6f, 0xcf, 0x75, 0xd7, 0x1f, 0xb5, 0xb5, 0xaf, 0xca, 0x77, 0x28, 0x6e, 0xa8, 0xd1,
- 0x06, 0x25, 0x04, 0x32, 0xe9, 0x47, 0x28, 0x35, 0xab, 0xaf, 0x7b, 0x0b, 0x24, 0x0f, 0xbf, 0x58,
- 0xde, 0xb8, 0x24, 0x12, 0xeb, 0x74, 0xf9, 0x40, 0xc6, 0xcd, 0x24, 0x2d, 0x62, 0x7b, 0xbf, 0x35,
- 0x76, 0xf2, 0x6a, 0x62, 0xe2, 0x5a, 0x25, 0x13, 0x63, 0x52, 0x4d, 0x28, 0x55, 0x59, 0x6e, 0x14,
- 0x5c, 0x77, 0x0d, 0x39, 0xfd, 0x5d, 0xbe, 0xe4, 0x0f, 0x51, 0x2a, 0xc1, 0xe2, 0x04, 0x9a, 0x83,
- 0x6f, 0x78, 0x4b, 0x44, 0x70, 0xc2, 0x4b, 0x97, 0xae, 0xfe, 0x87, 0x85, 0xc0, 0xb8, 0x82, 0x95,
- 0xc3, 0x8e, 0x2a, 0x63, 0x05, 0x1a, 0x30, 0x9f, 0xcd, 0x95, 0x66, 0xc0, 0x1d, 0x37, 0x80, 0x41,
- 0x61, 0xe7, 0xea, 0xb8, 0x37, 0x61, 0x9b, 0x4b, 0xe8, 0xec, 0x01, 0x48, 0x3f, 0xbd, 0xfb, 0x3a,
- 0x0d, 0x7a, 0x2c, 0x5c, 0x27, 0xed, 0x8e, 0x14, 0xa1, 0x43, 0xd7, 0x22, 0x5e, 0xe4, 0x76, 0xe0,
- 0x78, 0xb3, 0x09, 0xeb, 0xf3, 0x10, 0xcf, 0x60, 0x9a, 0x88, 0xb0, 0xaa, 0xa8, 0x87, 0x0a, 0xf5,
- 0xd6, 0xf5, 0x42, 0xbc, 0x82, 0x89, 0x55, 0xd1, 0x03, 0x98, 0xa6, 0x47, 0x76, 0x03, 0x62, 0x5d,
- 0x19, 0xa5, 0x21, 0x99, 0x46, 0x12, 0x5d, 0x26, 0x17, 0xc4, 0xbe, 0x3c, 0x86, 0xac, 0xe3, 0x17,
- 0xc7, 0xf5, 0x5d, 0x88, 0x0f, 0x45, 0x0b, 0xf2, 0x71, 0x31, 0xe3, 0x7b, 0x15, 0xc1, 0x98, 0x51,
- 0xb0, 0xd2, 0xe3, 0x78, 0x50, 0x3d, 0x97, 0x55, 0x9d, 0x74, 0xc3, 0x1c, 0x47, 0x54, 0xb4, 0xb2,
- 0xfd, 0xe6, 0x7d, 0xa1, 0x09, 0x58, 0xe6, 0x1e, 0x99, 0xb3, 0x2d, 0xe3, 0xe7, 0x84, 0xdc, 0xd2,
- 0xa0, 0x92, 0x58, 0x00, 0x6c, 0x1f, 0x0c, 0xd5, 0xe1, 0x3e, 0x75, 0x77, 0x92, 0x34, 0x94, 0xac,
- 0x2f, 0x0c, 0xfb, 0xf8, 0x66, 0x52, 0x86, 0x61, 0xcf, 0x64, 0x13, 0xf8, 0xa0, 0x3e, 0x0e, 0xc8,
- 0xf0, 0xed, 0xeb, 0xa0, 0x60, 0x9f, 0x19, 0xdc, 0x3c, 0x79, 0xfe, 0x79, 0x6a, 0x96, 0x5b, 0x2e,
- 0x24, 0x12, 0x56, 0xc9, 0xf3, 0x66, 0x81, 0x8f, 0x50, 0xd7, 0x5c, 0x5f, 0x7a, 0x42, 0xec, 0x5a,
- 0xa0, 0x22, 0xc3, 0x07, 0xb5, 0x95, 0xdc, 0x3f, 0x2b, 0xca, 0x40, 0x3a, 0x23, 0xac, 0xdd, 0x1d,
- 0x44, 0x2b, 0xb4, 0x09, 0x3c, 0x1b, 0xd5, 0xee, 0xe0, 0xc4, 0x19, 0x57, 0x36, 0x13, 0xf2, 0x2e,
- 0xb8, 0xf4, 0xfd, 0xc5, 0x76, 0x69, 0xa8, 0xc9, 0x4f, 0x52, 0x40, 0x8a, 0x86, 0x71, 0xf4, 0xc1,
- 0x8d, 0x11, 0xcf, 0xba, 0xc7, 0x60, 0x7e, 0xc4, 0xb1, 0x96, 0xa3, 0x0d, 0xc4, 0x71, 0x69, 0x07,
- 0x66, 0x13, 0xa1, 0x10, 0x73, 0x98, 0xb4, 0xe8, 0xf4, 0x77, 0x39, 0xe6, 0xe2, 0x00, 0x1b, 0x1d,
- 0x09, 0x4a, 0x74, 0xaa, 0x62, 0xba, 0x36, 0x60, 0x83, 0xa5, 0xad, 0xfa, 0xfb, 0xac, 0xde, 0x25,
- 0x0f, 0x7d, 0x63, 0xc6, 0x8f, 0xa5, 0xd3, 0x52, 0xec, 0xc6, 0xde, 0x56, 0x18, 0x95, 0x3d, 0x3b,
- 0xdf, 0xd8, 0x0e, 0x0e, 0x89, 0xa1, 0xb0, 0xc6, 0x94, 0x02, 0x5a, 0x7f, 0x83, 0x32, 0x02, 0x1e,
- 0x31, 0x2e, 0x96, 0x5f, 0xb6, 0xb7, 0x39, 0x65, 0x94, 0xbc, 0xf2, 0x81, 0x7b, 0xd6, 0xc6, 0xcc,
- 0x7f, 0x0a, 0x26, 0x26, 0x0a, 0x9b, 0xbe, 0xa8, 0x39, 0x7d, 0xc3, 0x76, 0x33, 0x82, 0x83, 0x57,
- 0x8b, 0x5c, 0x25, 0xf7, 0x3b, 0xb1, 0x93, 0xa8, 0xd7, 0x72, 0x2d, 0x8e, 0xf2, 0xdc, 0x16, 0xb4,
- 0x37, 0x1f, 0x24, 0x2b, 0x27, 0xe2, 0x6d, 0x7c, 0xed, 0x4c, 0xde, 0x1e, 0xe7, 0x61, 0xd9, 0x1b,
- 0xc4, 0x78, 0xc9, 0xa2, 0x87, 0x5e, 0xed, 0xfa, 0x76, 0x5e, 0x25, 0x17, 0xd6, 0x5c, 0x61, 0xc6,
- 0x2c, 0x0a, 0x33, 0xfe, 0xc7, 0x47, 0xa3, 0x23, 0xa8, 0x07, 0x00, 0x0a, 0x52, 0x8a, 0xca, 0xd4,
- 0x7c, 0xc5, 0xe4, 0xf9, 0x79, 0x8d, 0xd8, 0x69, 0x79, 0x5a, 0x32, 0x6e, 0x19, 0x06, 0x5c, 0x22,
- 0xfe, 0x6e, 0xb9, 0x95, 0x07, 0x7b, 0x04, 0xdd, 0xbd, 0x09, 0x07, 0xa4, 0x86, 0x02, 0xd5, 0xcc,
- 0xdb, 0xef, 0xd4, 0xcb, 0x33, 0xce, 0xfd, 0x88, 0xc2, 0x36, 0x15, 0x76, 0xed, 0xe2, 0xa9, 0x23,
- 0xee, 0x23, 0x3e, 0xaf, 0x69, 0x0f, 0xb6, 0x43, 0x5e, 0x44, 0x3c, 0x37, 0x60, 0xe6, 0xe6, 0xe8,
- 0xed, 0x2b, 0x08, 0xf9, 0x63, 0x50, 0x0b, 0x86, 0x96, 0x07, 0xaa, 0xee, 0xa7, 0xae, 0x92, 0x8a,
- 0x5c, 0x4f, 0xdc, 0x74, 0x0f, 0xa2, 0xbd, 0x82, 0x46, 0x11, 0xbb, 0x36, 0x7d, 0x66, 0xf6, 0x88,
- 0x9b, 0x6c, 0x0d, 0x59, 0xcb, 0x99, 0x0b, 0xc2, 0x81, 0x88, 0xc7, 0xf3, 0x97, 0x2c, 0xae, 0x3a,
- 0x74, 0x3e, 0x32, 0x2b, 0x36, 0xd8, 0x43, 0xdc, 0x36, 0x07, 0x07, 0x49, 0xae, 0x36, 0x48, 0xad,
- 0x81, 0x76, 0xcd, 0xd4, 0xde, 0x8f, 0xb6, 0x8e, 0x8b, 0xf3, 0x3c, 0x22, 0xbf, 0xad, 0xad, 0x26,
- 0x9d, 0x37, 0xd7, 0xb3, 0x1c, 0x22, 0x9e, 0x4f, 0xaf, 0x86, 0x4b, 0xa6, 0x66, 0xe4, 0x3e, 0x91,
- 0xdb, 0xfe, 0xf0, 0x60, 0x49, 0x92, 0x83, 0x8b, 0xa2, 0x56, 0xb7, 0xac, 0x62, 0x2b, 0xfd, 0x0c,
- 0xde, 0x51, 0x26, 0x81, 0xf6, 0x8a, 0x8b, 0x5e, 0x41, 0xd1, 0x86, 0x48, 0x8c, 0x69, 0x44, 0x28,
- 0xc8, 0xdd, 0x74, 0xe6, 0xbf, 0xdf, 0x69, 0x5a, 0xcb, 0xd2, 0x0b, 0xcc, 0x84, 0x45, 0x17, 0xc7,
- 0x2c, 0x14, 0xf6, 0x79, 0x9d, 0xac, 0x03, 0x8f, 0x11, 0x8d, 0xf3, 0xef, 0x79, 0xa3, 0x00, 0xaf,
- 0xcd, 0x8c, 0x57, 0xe2, 0x0f, 0x31, 0x77, 0x9f, 0x5e, 0x59, 0xcb, 0x50, 0xd2, 0xdf, 0x36, 0x90,
- 0xb0, 0x9e, 0xbe, 0xf8, 0xc0, 0xac, 0xea, 0xa2, 0x8f, 0xae, 0xfd, 0x06, 0xe8, 0x19, 0x0b, 0x06,
- 0xec, 0x86, 0x6c, 0xd2, 0x41, 0xab, 0x60, 0x7f, 0x76, 0xb7, 0x88, 0x1e, 0xcc, 0xab, 0x5a, 0x46,
- 0x43, 0x4b, 0x94, 0x33, 0xa6, 0x5b, 0x5d, 0x6e, 0xb6, 0xa0, 0x78, 0x99, 0xf6, 0x15, 0xb4, 0x07,
- 0x71, 0xbc, 0xd1, 0x9f, 0x0e, 0xa8, 0x1e, 0xa9, 0x73, 0x60, 0x8e, 0x76, 0xe8, 0x8d, 0x01, 0x91,
- 0x4f, 0x18, 0x43, 0xab, 0x11, 0xe8, 0x6b, 0xa6, 0x02, 0xe3, 0x8e, 0xe4, 0xca, 0x7f, 0x79, 0x52,
- 0x44, 0x47, 0x05, 0x1e, 0x75, 0x72, 0x00, 0xdf, 0x0c, 0x25, 0x4d, 0xaf, 0xc7, 0x61, 0x2f, 0x76,
- 0x29, 0x95, 0x5c, 0x0d, 0x92, 0x67, 0xd9, 0xc7, 0x8a, 0xe8, 0x30, 0x68, 0x3e, 0x48, 0x0d, 0x17,
- 0x5a, 0x65, 0x70, 0xce, 0x84, 0xba, 0x23, 0x81, 0x42, 0xd2, 0x01, 0x23, 0x02, 0xf0, 0xb8, 0x2a,
- 0x6f, 0xa3, 0xc3, 0x97, 0x42, 0x18, 0xcd, 0xab, 0x37, 0x48, 0x55, 0x4b, 0x5a, 0x1a, 0xd5, 0x23,
- 0xf8, 0xe8, 0x2e, 0xc7, 0xb1, 0x05, 0x37, 0xac, 0xb7, 0x4a, 0xe9, 0xfb, 0xc2, 0xb6, 0x80, 0x82,
- 0x48, 0xd6, 0x71, 0xaa, 0xe8, 0x78, 0xca, 0x8b, 0x5e, 0x69, 0x5a, 0x02, 0x89, 0x5b, 0x0c, 0x67,
- 0x7a, 0x93, 0x05, 0x31, 0x23, 0x82, 0x4e, 0xf5, 0x59, 0xf3, 0xf4, 0xc2, 0xb1, 0x47, 0xc6, 0xd8,
- 0xc1, 0xcd, 0x2b, 0x4b, 0x59, 0x1a, 0xcd, 0xdd, 0x03, 0x52, 0x14, 0x28, 0x94, 0xf6, 0xdc, 0xb2,
- 0xfd, 0x4e, 0xa5, 0x5e, 0xeb, 0x03, 0x4e, 0x7c, 0x4b, 0x9a, 0x23, 0x4f, 0x8c, 0xb4, 0xf3, 0x7f,
- 0x3e, 0x84, 0x04, 0x70, 0x6f, 0x04, 0x35, 0x2a, 0x66, 0xcf, 0xab, 0x51, 0x3f, 0xef, 0xb2, 0x5c,
- 0xba, 0xaa, 0x88, 0xf4, 0x80, 0xb1, 0x35, 0x83, 0xdc, 0xe4, 0xb7, 0xa8, 0xe9, 0x5e, 0x08, 0x91,
- 0x10, 0xf9, 0x7b, 0x97, 0x54, 0x60, 0x40, 0x83, 0xc8, 0xb8, 0xa8, 0x6c, 0xc3, 0x19, 0xf2, 0xbb,
- 0xc6, 0xea, 0xa2, 0x5e, 0x5f, 0x56, 0xba, 0xfc, 0x46, 0x32, 0xa7, 0x78, 0x0a, 0x8e, 0x0d, 0x2f,
- 0x74, 0xc4, 0x76, 0x01, 0x7f, 0x01, 0x83, 0xac, 0xa6, 0x96, 0x39, 0xff, 0xe3, 0x1f, 0x63, 0x26,
- 0x8d, 0x33, 0xb2, 0x22, 0xab, 0x97, 0x7d, 0xcf, 0x6b, 0x88, 0x41, 0x3c, 0x70, 0x5a, 0x73, 0x70,
- 0x2d, 0x72, 0x9a, 0xcf, 0x0d, 0xc1, 0x03, 0x8b, 0x81, 0x43, 0xa0, 0xd5, 0xac, 0xa7, 0xab, 0xfb,
- 0xc4, 0x6b, 0xf7, 0x06, 0xf6, 0x4a, 0xff, 0x2f, 0xad, 0x42, 0x50, 0xa9, 0x88, 0x02, 0x98, 0xf3,
- 0xd2, 0x6e, 0xc6, 0xe0, 0x2b, 0xf9, 0x2b, 0x8e, 0x6f, 0x4e, 0x47, 0x85, 0xe2, 0x67, 0xfb, 0xd7,
- 0xb9, 0x17, 0x6c, 0x9e, 0x26, 0xde, 0x56, 0xce, 0xf0, 0x77, 0xaa, 0xe8, 0xfd, 0x9c, 0x60, 0x34,
- 0x92, 0x36, 0x3d, 0xfc, 0xf6, 0xc6, 0xf0, 0xbd, 0xb7, 0x59, 0x96, 0x3d, 0xdd, 0xcf, 0x93, 0x30,
- 0xf3, 0xed, 0x3c, 0x69, 0xa0, 0x4e, 0xa8, 0x02, 0xcf, 0x87, 0xde, 0x94, 0x23, 0x1e, 0x68, 0xe6,
- 0xb6, 0x4f, 0xee, 0x59, 0xdc, 0xfe, 0x1f, 0xc9, 0xff, 0x02, 0x02, 0x0b, 0x10, 0x23, 0xee, 0xde,
- 0xe0, 0x18, 0x79, 0x78, 0x6f, 0x0f, 0x19, 0x8c, 0x8c, 0x8e, 0x2f, 0x7f, 0x22, 0xab, 0xab, 0x37,
- 0x89, 0xc7, 0x4b, 0x85, 0x68, 0x66, 0xd8, 0x37, 0x23, 0x17, 0x71, 0xc5, 0x4b, 0x6d, 0xe6, 0x92,
- 0xe5, 0xbf, 0xbc, 0x1f, 0xa4, 0x34, 0x19, 0x70, 0x59, 0x0b, 0x47, 0x4f, 0xa5, 0x60, 0x75, 0xb2,
- 0xc8, 0x11, 0x28, 0x22, 0x53, 0xfd, 0x6f, 0xf0, 0x22, 0xb0, 0x5b, 0xed, 0x8b, 0xd0, 0xbd, 0x54,
- 0xd3, 0x0f, 0x89, 0xf7, 0xd8, 0xde, 0x14, 0x15, 0x57, 0x2e, 0xf8, 0xe9, 0x54, 0xd9, 0xde, 0x5e,
- 0xa8, 0x3f, 0x0e, 0xf1, 0xbe, 0x16, 0x35, 0x37, 0x11, 0xab, 0xc2, 0xaa, 0x2e, 0x29, 0x5f, 0xb2,
- 0x93, 0x70, 0x73, 0x10, 0x03, 0xa1, 0x4c, 0x79, 0x0d, 0xd7, 0x62, 0x18, 0x41, 0xcc, 0x6d, 0x17,
- 0x03, 0x5f, 0x75, 0xb0, 0x7d, 0x11, 0x18, 0x46, 0x4f, 0x3c, 0xf0, 0xdc, 0x1b, 0x28, 0xc9, 0xbb,
- 0x62, 0x49, 0x4d, 0xfc, 0xba, 0xae, 0xff, 0xf3, 0x12, 0x9e, 0x4c, 0x86, 0x17, 0x38, 0x2e, 0x45,
- 0x48, 0xc0, 0x9b, 0x27, 0x3e, 0x7b, 0x91, 0xd2, 0xa0, 0xad, 0x77, 0x69, 0x22, 0x56, 0xad, 0x0b,
- 0xd3, 0xc6, 0x50, 0x57, 0xd5, 0xc7, 0x57, 0x35, 0xff, 0xb5, 0x5d, 0xb4, 0xa0, 0x05, 0x31, 0xf2,
- 0x55, 0x50, 0x98, 0xf3, 0x99, 0xbc, 0x23, 0x66, 0x64, 0x20, 0x1b, 0xaf, 0xa3, 0xdb, 0xc7, 0xe3,
- 0xdc, 0xd4, 0xb3, 0x73, 0x1a, 0xf1, 0x9d, 0xd9, 0x8a, 0xab, 0x85, 0x26, 0xf9, 0xab, 0xf4, 0xec,
- 0xca, 0x35, 0x08, 0x0e, 0x7b, 0xca, 0xf9, 0xa9, 0xb0, 0x42, 0xca, 0x1c, 0x33, 0xec, 0x97, 0x15,
- 0xad, 0x28, 0x8f, 0x01, 0x50, 0xc1, 0xdd, 0xb5, 0xcc, 0xd2, 0xf9, 0xb6, 0x03, 0xf8, 0x5b, 0x41,
- 0xf6, 0x98, 0x55, 0xf6, 0xfe, 0xe9, 0x4a, 0x11, 0xac, 0xed, 0xc1, 0x18, 0x95, 0xeb, 0x7b, 0x7c,
- 0xf6, 0xc8, 0x10, 0xe5, 0xfd, 0x0d, 0x78, 0xcf, 0x73, 0x20, 0xab, 0xed, 0xad, 0x89, 0x29, 0x58,
- 0x7e, 0x47, 0x0d, 0x0e, 0x19, 0x2b, 0xc6, 0x93, 0x46, 0x5d, 0xb0, 0xd1, 0x73, 0x8c, 0x41, 0x0a,
- 0xb4, 0x38, 0x04, 0x1b, 0x14, 0x02, 0xf5, 0x23, 0x08, 0xea, 0xac, 0x2f, 0x50, 0xfd, 0x13, 0xe8,
- 0xb7, 0xbc, 0x4c, 0x57, 0xfa, 0x12, 0xc1, 0x47, 0x48, 0x9d, 0xe3, 0xff, 0x69, 0x35, 0x22, 0xc0,
- 0x47, 0x83, 0x1d, 0x25, 0x6c, 0x2c, 0x16, 0xe4, 0x0f, 0x43, 0x69, 0x7b, 0xa0, 0x4d, 0x5e, 0x53,
- 0x6f, 0x35, 0xcd, 0x3c, 0xcb, 0x89, 0x2f, 0x9e, 0xdf, 0x88, 0x6d, 0xeb, 0xda, 0xcd, 0x91, 0x22,
- 0xf9, 0xd3, 0x13, 0xb1, 0xd4, 0xfe, 0x15, 0xe2, 0xcb, 0x14, 0x5d, 0x41, 0x79, 0xce, 0xbb, 0x71,
- 0xb0, 0x96, 0xba, 0x07, 0x36, 0xa6, 0xe2, 0x91, 0xda, 0x19, 0xe0, 0x8d, 0x0b, 0xcb, 0x42, 0xd0,
- 0x6c, 0xcf, 0x44, 0xa6, 0x8e, 0x1b, 0x9c, 0x2b, 0x02, 0xdb, 0xec, 0xd0, 0x5b, 0xbe, 0x30, 0x8a,
- 0xd0, 0x1c, 0x61, 0x02, 0x2a, 0x9c, 0x1a, 0xc8, 0x71, 0x47, 0xa3, 0x49, 0x45, 0x92, 0x4c, 0xea,
- 0xd4, 0x9c, 0x96, 0xf2, 0x6c, 0xf0, 0x53, 0x63, 0xcc, 0x70, 0xe2, 0x38, 0x0f, 0xc3, 0x22, 0xd5,
- 0x91, 0x27, 0xc3, 0x98, 0x16, 0xb8, 0x1d, 0xbf, 0x13, 0x69, 0x77, 0x97, 0x87, 0x87, 0x23, 0xc5,
- 0xe1, 0x66, 0x94, 0x4c, 0x9f, 0x27, 0x32, 0x88, 0x3d, 0xef, 0xfb, 0xcc, 0x71, 0x4f, 0x24, 0xb1,
- 0x06, 0xdb, 0xc3, 0x88, 0x33, 0xc5, 0x47, 0xca, 0xbc, 0x16, 0x6e, 0xdc, 0x55, 0x75, 0x2a, 0xa1,
- 0x28, 0x73, 0xb3, 0x7e, 0xe8, 0x1c, 0x23, 0x2a, 0xee, 0x69, 0x5f, 0xf8, 0x5c, 0x79, 0x73, 0x87,
- 0x7f, 0x4d, 0x72, 0xba, 0x7e, 0x5e, 0xdc, 0x47, 0xba, 0xc4, 0x83, 0xd7, 0x62, 0x9c, 0x89, 0x62,
- 0xea, 0xbe, 0xc5, 0x45, 0xee, 0xa3, 0xde, 0x89, 0x03, 0x16, 0x1f, 0xee, 0x48, 0x94, 0x9e, 0x5a,
- 0xb4, 0x06, 0x70, 0x3d, 0xe0, 0x58, 0xe4, 0xd6, 0xc7, 0xf3, 0xdc, 0x31, 0xa1, 0xa2, 0x9f, 0x93,
- 0x41, 0x45, 0x98, 0x23, 0xc8, 0x69, 0x34, 0x9e, 0x8e, 0xf5, 0x01, 0x61, 0x4a, 0xbc, 0x94, 0xa9,
- 0x69, 0x40, 0xea, 0x9f, 0xa0, 0xd8, 0xb4, 0x96, 0x0d, 0xf7, 0x78, 0xd6, 0xdf, 0xdc, 0x45, 0x26,
- 0xfc, 0x39, 0x83, 0xde, 0xa3, 0x94, 0x27, 0xf9, 0xed, 0x72, 0xae, 0xd9, 0x40, 0x27, 0xe3, 0xc6,
- 0x3c, 0x69, 0x98, 0x6a, 0xd9, 0x8f, 0x4d, 0x7d, 0x71, 0xd4, 0xc8, 0x42, 0xfa, 0x37, 0xaa, 0x68,
- 0x7e, 0x7d, 0xab, 0x40, 0xfd, 0x8b, 0x88, 0xae, 0x4d, 0xe4, 0x0f, 0x20, 0x3e, 0x61, 0x35, 0x62,
- 0xe2, 0xf0, 0x19, 0x84, 0xf8, 0x77, 0x85, 0x9d, 0x9f, 0xb7, 0x5c, 0x07, 0x89, 0x80, 0x7f, 0xa6,
- 0x64, 0xf3, 0x33, 0xdc, 0x27, 0x8b, 0x08, 0xe6, 0xf0, 0xb2, 0xc7, 0xd1, 0x30, 0xe5, 0x72, 0xb1,
- 0x24, 0x6d, 0x5d, 0xcb, 0x45, 0x77, 0x7a, 0xbf, 0x61, 0x8b, 0xaf, 0xd1, 0x80, 0xf2, 0x6a, 0x63,
- 0xb5, 0x15, 0xe4, 0x86, 0xc5, 0xa7, 0x82, 0x28, 0x99, 0x78, 0x03, 0xcb, 0x53, 0x80, 0xf4, 0xb4,
- 0x7d, 0x5a, 0x26, 0x2a, 0x04, 0xb5, 0x57, 0xdf, 0x02, 0x16, 0x3b, 0xa0, 0x24, 0x39, 0xdd, 0x9b,
- 0xd4, 0x27, 0x3a, 0x3b, 0xd6, 0x0d, 0x6f, 0xa6, 0x8d, 0x36, 0xc5, 0x20, 0x6b, 0x5b, 0xc0, 0x68,
- 0xd6, 0x32, 0x29, 0x91, 0x0c, 0xbe, 0xf4, 0x50, 0xeb, 0xbf, 0xb2, 0x72, 0xa4, 0xcc, 0xcd, 0x90,
- 0x36, 0x56, 0xee, 0x4e, 0xd3, 0x2f, 0x22, 0x27, 0x97, 0x7f, 0xd1, 0xb2, 0x8a, 0x84, 0xce, 0xee,
- 0xd0, 0x57, 0xb6, 0xea, 0xf6, 0x01, 0x7e, 0x69, 0xd8, 0xcb, 0xe0, 0x91, 0xfa, 0x8d, 0xed, 0xee,
- 0x5f, 0xdb, 0x2d, 0xb3, 0xc8, 0x78, 0x69, 0x93, 0x35, 0x0c, 0x2a, 0x26, 0x22, 0xa8, 0x4d, 0xea,
- 0x95, 0x8c, 0x94, 0x84, 0x70, 0xd1, 0xfc, 0x4c, 0xbb, 0xf7, 0xca, 0xce, 0x47, 0x16, 0xa2, 0x9e,
- 0x49, 0x3b, 0x3e, 0x13, 0xd3, 0xf0, 0xa3, 0xc2, 0x56, 0x29, 0xb2, 0xa3, 0xee, 0x55, 0x7a, 0x42,
- 0x9b, 0x01, 0xd7, 0x59, 0xe8, 0x34, 0xa5, 0x6b, 0xb0, 0xf0, 0x76, 0xff, 0x59, 0xb5, 0x09, 0x47,
- 0x1c, 0x88, 0xd4, 0xb8, 0xec, 0x3b, 0x75, 0xf7, 0xbc, 0x13, 0x80, 0x95, 0x0c, 0x9b, 0x5d, 0x43,
- 0xa4, 0x59, 0xa5, 0xd9, 0x08, 0xe3, 0x39, 0x23, 0xf9, 0xb7, 0xdb, 0x60, 0xbe, 0x4d, 0xd9, 0x8a,
- 0x94, 0xb7, 0xb6, 0x5c, 0x5f, 0x2d, 0x02, 0xeb, 0x90, 0x31, 0x91, 0x22, 0xc2, 0x9d, 0xcf, 0xaa,
- 0x41, 0x31, 0xf9, 0x8b, 0x91, 0x18, 0x70, 0x36, 0xbe, 0x50, 0x10, 0x02, 0xf1, 0x56, 0x15, 0x7c,
- 0x18, 0x28, 0x31, 0x70, 0xed, 0x29, 0x69, 0xde, 0xb4, 0xf5, 0x35, 0x6d, 0x99, 0x38, 0xcf, 0x20,
- 0x18, 0xc3, 0xf4, 0x1d, 0xde, 0xdc, 0x90, 0x67, 0x61, 0xba, 0x8a, 0x45, 0xc2, 0xf9, 0xad, 0x6e,
- 0x41, 0x4f, 0x07, 0x75, 0xe3, 0x18, 0xb0, 0xe7, 0x4a, 0xe3, 0x03, 0xf7, 0xfe, 0x69, 0x69, 0x3b,
- 0xea, 0x74, 0x4c, 0xc8, 0x47, 0x9f, 0x70, 0xe9, 0x00, 0xc4, 0xce, 0xcc, 0x90, 0x73, 0x45, 0xb1,
- 0xe6, 0xee, 0xd5, 0x74, 0xce, 0xca, 0x39, 0x5c, 0xcd, 0x9a, 0xe3, 0x70, 0x70, 0x91, 0x5b, 0xc3,
- 0x49, 0x99, 0x71, 0x67, 0x7e, 0x4f, 0x37, 0xf3, 0x92, 0x75, 0xc8, 0x2b, 0x1a, 0x33, 0xf7, 0xd7,
- 0x6b, 0x83, 0x35, 0xac, 0xba, 0x36, 0x1b, 0x66, 0x30, 0xee, 0x66, 0x8b, 0xeb, 0x82, 0xc7, 0x1d,
- 0x9c, 0xdf, 0xeb, 0x2c, 0x60, 0x4c, 0xb5, 0x41, 0xe0, 0x3e, 0xe3, 0xeb, 0x79, 0x57, 0x0a, 0x1c,
- 0x02, 0x05, 0xba, 0xc0, 0xcd, 0x78, 0x60, 0xa3, 0x87, 0x99, 0x65, 0x04, 0x3b, 0x62, 0x01, 0x06,
- 0x7f, 0xe0, 0xe9, 0x36, 0x25, 0xf9, 0x97, 0x1b, 0x77, 0x33, 0x97, 0xdc, 0x12, 0x42, 0x50, 0xe5,
- 0x95, 0xb5, 0x7e, 0xf2, 0x70, 0xb3, 0x06, 0x60, 0x7f, 0xd7, 0x5e, 0xc6, 0xff, 0x73, 0x22, 0x03,
- 0x6b, 0xc7, 0x05, 0x98, 0x5b, 0x7e, 0xc5, 0x54, 0xaf, 0x9d, 0xe5, 0xa1, 0xc9, 0x64, 0xca, 0x43,
- 0xca, 0xec, 0xfa, 0x74, 0xaa, 0x50, 0x82, 0x68, 0x8c, 0xd1, 0x01, 0x60, 0x02, 0xce, 0x97, 0x09,
- 0x7e, 0x3a, 0xc3, 0x6b, 0x8a, 0x67, 0x91, 0x34, 0x06, 0xbc, 0xc5, 0x3e, 0xf9, 0x7e, 0xe6, 0xdd,
- 0x84, 0xa8, 0xbc, 0xc4, 0x5c, 0xcc, 0xb4, 0xaa, 0xd0, 0xe1, 0x06, 0xc1, 0x9d, 0x06, 0xdd, 0x4a,
- 0xa1, 0x39, 0x30, 0x02, 0xe8, 0xfc, 0x40, 0x85, 0x96, 0x10, 0x14, 0x14, 0x54, 0xc9, 0x9e, 0x9c,
- 0x5b, 0xe8, 0x13, 0x2e, 0xaa, 0x93, 0x71, 0xde, 0xb3, 0x71, 0xbf, 0x6a, 0x12, 0xac, 0x26, 0x70,
- 0x55, 0x62, 0x04, 0x49, 0x2e, 0x05, 0xbc, 0x57, 0x1c, 0xa9, 0xe6, 0x57, 0xdc, 0x9a, 0xea, 0x92,
- 0x76, 0xe9, 0x4a, 0x5e, 0x09, 0x0f, 0x2e, 0xd1, 0x0d, 0xc2, 0x54, 0xf3, 0x14, 0xcb, 0x8b, 0xe3,
- 0x05, 0x0a, 0xdd, 0x2e, 0xeb, 0x7e, 0x2b, 0x2c, 0xb0, 0x53, 0xf1, 0xd2, 0x2c, 0x76, 0x6a, 0xa9,
- 0x06, 0x77, 0x15, 0x70, 0x9a, 0x71, 0x0d, 0x3a, 0x27, 0x1b, 0x00, 0x09, 0x35, 0xeb, 0x07, 0x74,
- 0xb3, 0x1c, 0x77, 0x77, 0x5c, 0xc8, 0xe3, 0xe5, 0xb1, 0xa9, 0x35, 0x69, 0xc9, 0x49, 0xad, 0xeb,
- 0xbb, 0x52, 0x50, 0x8c, 0x03, 0x6f, 0x40, 0x20, 0xc0, 0xdd, 0xbe, 0xe8, 0x60, 0x23, 0xdc, 0x2c,
- 0x69, 0x35, 0x8a, 0xfa, 0x4a, 0x40, 0xee, 0xf6, 0xc0, 0xd7, 0xce, 0x54, 0x4a, 0x99, 0x81, 0x81,
- 0xef, 0x95, 0xec, 0x1b, 0x1d, 0xd5, 0xcf, 0xf2, 0xf2, 0xd3, 0xa2, 0x93, 0x84, 0xa9, 0x36, 0xd9,
- 0x1a, 0x41, 0xff, 0xe8, 0x25, 0xfd, 0xf8, 0x49, 0xef, 0xb1, 0x1a, 0xf3, 0x54, 0x31, 0xcf, 0x4e,
- 0xc7, 0x12, 0xbc, 0xac, 0xa2, 0x98, 0xa9, 0x7a, 0xa9, 0x47, 0x65, 0x0e, 0xf0, 0x29, 0xc5, 0xf3,
- 0x2c, 0x90, 0x20, 0x29, 0xcc, 0x28, 0x9c, 0x02, 0x22, 0x2d, 0x07, 0xab, 0x30, 0xfd, 0x52, 0x0b,
- 0xde, 0x85, 0x00, 0x01, 0xdf, 0x8a, 0x2d, 0x22, 0xcb, 0x7e, 0xce, 0xe0, 0xf3, 0x12, 0x19, 0x14,
- 0x78, 0x88, 0x19, 0x3e, 0x11, 0x66, 0x22, 0x00, 0x20, 0x85, 0x98, 0xa2, 0xd3, 0x92, 0x56, 0x68,
- 0x6e, 0x44, 0xc2, 0xc2, 0x2e, 0x56, 0x1c, 0x3e, 0x47, 0x87, 0x95, 0x6c, 0xe4, 0x11, 0xea, 0xf6,
- 0x0b, 0x84, 0x2f, 0xce, 0x0f, 0x62, 0x00, 0xa5, 0x4a, 0x5d, 0xda, 0x68, 0x66, 0x20, 0xe5, 0x24,
- 0xaf, 0x08, 0xe0, 0x6f, 0xdd, 0xa5, 0xc1, 0x62, 0x11, 0x27, 0x0f, 0xd4, 0x88, 0x8f, 0x4e, 0x9c,
- 0xfc, 0x52, 0x41, 0x93, 0x93, 0x43, 0xcf, 0xec, 0x73, 0x0a, 0x26, 0x7d, 0x9e, 0x1d, 0x16, 0xc5,
- 0xf6, 0x4d, 0x24, 0x3c, 0xdd, 0x5f, 0x4d, 0x14, 0xb7, 0x90, 0x63, 0xa9, 0x59, 0x57, 0x66, 0x81,
- 0xd5, 0x29, 0x09, 0x8d, 0x9d, 0x08, 0xf2, 0xbe, 0xb2, 0xe2, 0xed, 0x09, 0xda, 0x2b, 0x4a, 0x86,
- 0xbf, 0x85, 0xb7, 0x5c, 0x91, 0x38, 0x32, 0x4c, 0xcc, 0x26, 0x72, 0x97, 0xa9, 0xcb, 0x50, 0x75,
- 0x52, 0xc4, 0x99, 0x75, 0xef, 0x04, 0x9e, 0xf0, 0xff, 0xe8, 0x11, 0xcd, 0x85, 0x3b, 0xfb, 0x98,
- 0xcb, 0x65, 0x4a, 0xe3, 0x3d, 0xf6, 0x05, 0x67, 0x72, 0x5e, 0x24, 0xb2, 0x89, 0x0e, 0x19, 0xc9,
- 0xeb, 0x4e, 0x34, 0xc6, 0xc6, 0xe5, 0xc2, 0x93, 0xca, 0x1c, 0xc4, 0x47, 0x2b, 0x21, 0xe6, 0x5b,
- 0x0d, 0x0d, 0x38, 0xb1, 0xbd, 0xd4, 0xe1, 0x38, 0xce, 0x53, 0xcc, 0xa8, 0xf3, 0x2a, 0x16, 0x55,
- 0x10, 0x77, 0xe1, 0xe9, 0x63, 0xdd, 0xe0, 0xd0, 0xd2, 0xff, 0x87, 0x21, 0xca, 0x09, 0xd9, 0xd1,
- 0xc6, 0x35, 0x24, 0x26, 0x22, 0xdf, 0xc0, 0xe6, 0x7f, 0xe7, 0x33, 0xbf, 0x7b, 0x54, 0x98, 0x7b,
- 0x88, 0x3c, 0x3a, 0x0c, 0x1e, 0x9f, 0x39, 0x02, 0xc1, 0xce, 0x06, 0xbe, 0x2e, 0xb7, 0xb6, 0x21,
- 0xe6, 0x4b, 0xb4, 0x65, 0x3a, 0x77, 0xe3, 0xca, 0xe0, 0x83, 0x75, 0xd4, 0x5d, 0xbc, 0x77, 0x24,
- 0x69, 0x9b, 0xd4, 0x77, 0x23, 0x49, 0x0e, 0x9a, 0xf3, 0x26, 0x9d, 0xa9, 0x31, 0x81, 0x0d, 0xba,
- 0x94, 0x58, 0x9a, 0x82, 0x8a, 0x4e, 0x6a, 0x65, 0x90, 0xbf, 0x4a, 0x85, 0x51, 0x65, 0x3a, 0x1d,
- 0xac, 0xbf, 0x39, 0x11, 0xf6, 0xe2, 0x1f, 0x6c, 0xeb, 0x96, 0xde, 0x7a, 0x59, 0x83, 0x6d, 0x8f,
- 0x3b, 0xd5, 0xb9, 0x54, 0x5a, 0x05, 0xe7, 0x11, 0xd8, 0x52, 0x12, 0x2e, 0xf5, 0x44, 0x99, 0x55,
- 0xf7, 0xcd, 0xb8, 0x37, 0x16, 0xa7, 0xaa, 0xc0, 0x9a, 0x64, 0x44, 0x1e, 0xd7, 0x48, 0x40, 0x52,
- 0xdd, 0xcc, 0x99, 0x98, 0x33, 0x06, 0xe7, 0xec, 0x00, 0x91, 0x81, 0x48, 0x27, 0xdf, 0xb2, 0xe1,
- 0xfd, 0x87, 0x22, 0x66, 0x81, 0xde, 0x0b, 0xcd, 0xb2, 0xaf, 0x8c, 0xaf, 0xd4, 0xe6, 0xc9, 0xb9,
- 0xd9, 0xb9, 0x16, 0x84, 0xcb, 0xb3, 0x65, 0xb9, 0x6c, 0x00, 0xcb, 0x31, 0x22, 0x36, 0xa9, 0x1a,
- 0xfb, 0xf7, 0x3a, 0xd2, 0x70, 0xf7, 0x97, 0x63, 0xbf, 0x35, 0x8c, 0x17, 0xd7, 0x10, 0x05, 0x32,
- 0xfe, 0x80, 0xd9, 0x04, 0x02, 0x1a, 0xc9, 0xb1, 0xcf, 0xa6, 0x26, 0x0e, 0x99, 0xf8, 0x6c, 0x32,
- 0x27, 0x2f, 0xac, 0xf2, 0x17, 0x95, 0xcf, 0x11, 0x97, 0x10, 0x26, 0x17, 0xe8, 0x78, 0xc2, 0xaf,
- 0x3a, 0x53, 0x71, 0x96, 0x41, 0x55, 0x6a, 0xdc, 0x9a, 0xbc, 0x57, 0x5c, 0x5a, 0x10, 0x97, 0x50,
- 0xa4, 0x08, 0x4c, 0x21, 0x6c, 0x95, 0xfa, 0xff, 0xdd, 0xf8, 0xd2, 0xf0, 0x6d, 0x6d, 0x24, 0x19,
- 0x9a, 0x42, 0x0a, 0xe8, 0xef, 0x90, 0xf7, 0xb0, 0xe0, 0xfa, 0xbe, 0xf8, 0xf1, 0x47, 0xff, 0xe6,
- 0x23, 0x23, 0x97, 0x42, 0xde, 0x35, 0x89, 0xf0, 0xd2, 0x1b, 0xee, 0x1f, 0x2c, 0xd1, 0xb1, 0x85,
- 0xbf, 0x1a, 0x08, 0x15, 0xc1, 0x7e, 0xcc, 0x85, 0xc2, 0xec, 0x50, 0x8c, 0x97, 0xe4, 0xf7, 0x5d,
- 0x0a, 0x39, 0x00, 0x57, 0x56, 0x0f, 0x35, 0x0b, 0x7d, 0x8d, 0x68, 0x32, 0x85, 0x70, 0x55, 0x83,
- 0x9a, 0x31, 0x62, 0x25, 0x01, 0xb2, 0xc6, 0x54, 0xbc, 0xf0, 0x98, 0xdd, 0x78, 0xe9, 0xa1, 0x6c,
- 0x8e, 0x2c, 0x74, 0x17, 0xe9, 0xec, 0x0e, 0x7b, 0x64, 0xa0, 0x70, 0xe7, 0xab, 0x12, 0xf0, 0x5f,
- 0xa6, 0x7d, 0x9b, 0xa6, 0x86, 0xbc, 0x4c, 0x22, 0x88, 0x11, 0x54, 0x53, 0x6a, 0x55, 0x09, 0x7f,
- 0xd9, 0xab, 0xaf, 0x2e, 0x29, 0xa3, 0xc0, 0x75, 0xbe, 0x67, 0x8e, 0x49, 0x1c, 0xb5, 0x59, 0x85,
- 0xbf, 0xfe, 0x68, 0x84, 0x75, 0xf5, 0xa6, 0xd1, 0xe5, 0x29, 0xd9, 0x43, 0xf6, 0xc2, 0x8a, 0xd8,
- 0xe8, 0xfa, 0x14, 0x4f, 0x71, 0xa7, 0x24, 0x5a, 0xff, 0xe8, 0x01, 0x50, 0x5e, 0x37, 0x00, 0x96,
- 0xbf, 0x17, 0xf6, 0x17, 0xce, 0x18, 0xd0, 0x25, 0x07, 0x6a, 0x8a, 0x51, 0xd4, 0x4a, 0xde, 0x16,
- 0x10, 0x83, 0x1f, 0x68, 0xcf, 0xe6, 0xcb, 0xea, 0xe0, 0x8d, 0x43, 0x46, 0x41, 0x7c, 0xf2, 0x40,
- 0xcb, 0xa8, 0x79, 0x00, 0xe5, 0xec, 0xb3, 0x4d, 0x74, 0x7f, 0x3e, 0xee, 0xee, 0x70, 0x33, 0xfc,
- 0x94, 0x6c, 0x08, 0x8a, 0xb2, 0x75, 0x74, 0x3e, 0xc7, 0x90, 0xd2, 0xdd, 0x4a, 0x5d, 0x51, 0x5b,
- 0xa5, 0x3a, 0xb4, 0x4b, 0xd9, 0xf4, 0xf0, 0xe5, 0xc5, 0x54, 0x74, 0x16, 0x03, 0x99, 0x0b, 0x92,
- 0x4a, 0x91, 0x93, 0x29, 0x83, 0x9c, 0x89, 0x41, 0xb0, 0x88, 0x5c, 0x10, 0x55, 0xda, 0x32, 0x2c,
- 0x07, 0x37, 0x4a, 0xee, 0x4b, 0xc2, 0xaf, 0x42, 0x7b, 0x68, 0x7e, 0xc3, 0xe1, 0x2c, 0x1f, 0x81,
- 0xf2, 0xee, 0xea, 0x89, 0x4a, 0xf4, 0x9c, 0x60, 0x75, 0xea, 0x90, 0x0a, 0x7f, 0x89, 0x7e, 0xbd,
- 0x05, 0x6e, 0x81, 0xc1, 0x9c, 0x8d, 0x65, 0xa0, 0x52, 0xb5, 0xc4, 0x74, 0x97, 0x47, 0xff, 0x55,
- 0x85, 0x8c, 0x78, 0x99, 0xb7, 0x32, 0xda, 0x11, 0x7a, 0xf4, 0x4f, 0x29, 0xd9, 0x3f, 0x51, 0x82,
- 0xac, 0xdb, 0x5e, 0x1a, 0xef, 0x9b, 0xbf, 0x97, 0xad, 0x0c, 0x42, 0x2e, 0xe2, 0x17, 0x52, 0x25,
- 0xa9, 0x2d, 0xcb, 0xa4, 0x0a, 0x2f, 0xb7, 0xe0, 0xe4, 0xdc, 0xab, 0xe0, 0x4d, 0x88, 0xf3, 0x00,
- 0x15, 0x52, 0x2e, 0x4d, 0x52, 0xe1, 0xe0, 0x84, 0x61, 0xcd, 0x78, 0x42, 0x38, 0x2e, 0xa2, 0x57,
- 0xc5, 0x56, 0x7c, 0x5e, 0x90, 0xfa, 0x77, 0xa3, 0x0c, 0x86, 0xc1, 0x2b, 0x8e, 0x2a, 0x80, 0x64,
- 0x69, 0x10, 0xcb, 0x0e, 0x09, 0xd6, 0x40, 0x60, 0x28, 0x76, 0x01, 0x18, 0xb0, 0x7f, 0xf6, 0x30,
- 0x5f, 0x04, 0x2c, 0x51, 0x01, 0xfa, 0xc1, 0x3a, 0x07, 0x60, 0x52, 0x44, 0xfe, 0xc9, 0x69, 0xcd,
- 0x52, 0x5a, 0xa8, 0x1d, 0x67, 0xc6, 0xee, 0x79, 0x98, 0x5a, 0xff, 0x80, 0x5b, 0x3a, 0x57, 0x49,
- 0xfa, 0x18, 0xf6, 0x6d, 0x51, 0x15, 0xc6, 0x0e, 0xb9, 0x35, 0xff, 0x88, 0xef, 0xa9, 0x4f, 0xf5,
- 0x0f, 0x87, 0x5a, 0x58, 0x30, 0x3e, 0xde, 0xee, 0xff, 0x06, 0x7b, 0xa6, 0x20, 0x24, 0xd6, 0x12,
- 0x4c, 0x3f, 0x1d, 0x3d, 0x4d, 0xc9, 0xd9, 0x23, 0x4d, 0x18, 0x92, 0xf7, 0xa8, 0x45, 0xb0, 0x18,
- 0x47, 0x66, 0xd1, 0x30, 0x0d, 0x8d, 0x14, 0x6c, 0xdd, 0xf8, 0x34, 0x05, 0x25, 0x11, 0x1e, 0x3b,
- 0xf6, 0xb2, 0xe1, 0xdf, 0x77, 0xba, 0xd1, 0x82, 0x2d, 0xe7, 0xc2, 0x92, 0x38, 0x6e, 0xda, 0x53,
- 0xa3, 0xba, 0x92, 0x3e, 0x55, 0xd8, 0x6a, 0xf0, 0xfa, 0x88, 0x4c, 0x1f, 0xaf, 0x73, 0x59, 0x33,
- 0x88, 0xa5, 0xe8, 0xe5, 0x85, 0x4f, 0x4d, 0x93, 0x1c, 0x89, 0x88, 0x71, 0xff, 0x47, 0x0b, 0xf8,
- 0xfb, 0x20, 0x44, 0x26, 0x57, 0x01, 0x45, 0x08, 0xf5, 0x4a, 0x51, 0x67, 0x4a, 0xc7, 0xe4, 0x4d,
- 0xd6, 0x93, 0x42, 0x6b, 0x90, 0x0b, 0x09, 0x18, 0x02, 0x23, 0x5b, 0x05, 0x45, 0x0e, 0xda, 0x57,
- 0xc1, 0xa8, 0x7b, 0xe4, 0x98, 0x80, 0x12, 0x2d, 0x11, 0xaf, 0x8c, 0x0c, 0xb9, 0xb2, 0x2f, 0xf5,
- 0xad, 0xce, 0x4c, 0x3a, 0x0a, 0x32, 0x67, 0x87, 0x1c, 0x85, 0x57, 0x1d, 0x4a, 0x26, 0x52, 0xe6,
- 0x89, 0xef, 0x75, 0x19, 0x08, 0x9d, 0x05, 0x9d, 0x08, 0xa9, 0xc0, 0x15, 0x39, 0x98, 0x44, 0x71,
- 0x35, 0xa3, 0xe2, 0x94, 0x37, 0x00, 0x11, 0x6d, 0xed, 0x20, 0x83, 0x51, 0x21, 0xd1, 0x60, 0x94,
- 0xe8, 0x41, 0x91, 0x8a, 0x4b, 0xc7, 0x80, 0x2d, 0x46, 0xfe, 0x57, 0xed, 0x5c, 0x37, 0xeb, 0xaa,
- 0x8a, 0x73, 0x64, 0xd6, 0xa3, 0x9d, 0x6b, 0x7f, 0x57, 0xf0, 0x2d, 0xae, 0xfb, 0x11, 0x62, 0x6a,
- 0x61, 0x5a, 0x48, 0xa5, 0x07, 0xb1, 0x4d, 0x79, 0x40, 0x5c, 0x34, 0x2d, 0xcc, 0x87, 0xbb, 0xcd,
- 0xe5, 0x7f, 0xa6, 0x09, 0xcd, 0x90, 0xdb, 0xf6, 0xdc, 0x3a, 0xa7, 0xa4, 0x20, 0x9c, 0x3f, 0x4c,
- 0x24, 0x10, 0x7c, 0x75, 0x35, 0x10, 0x4a, 0xc5, 0x6f, 0x2e, 0xc4, 0x98, 0x84, 0x0d, 0x86, 0xf3,
- 0xc6, 0xb1, 0x4a, 0x54, 0xac, 0x08, 0x6e, 0x13, 0xd2, 0xbe, 0x14, 0x39, 0xb9, 0xa9, 0x4f, 0xb9,
- 0x85, 0xbf, 0xf5, 0x18, 0x4b, 0x4f, 0x26, 0x2a, 0x39, 0x50, 0xf5, 0x01, 0x58, 0x8a, 0xbd, 0x22,
- 0xd0, 0x29, 0xa6, 0x53, 0x40, 0xc0, 0x73, 0xdc, 0xd9, 0x03, 0x6a, 0xfd, 0x57, 0xdc, 0x2b, 0x4b,
- 0xd0, 0xe7, 0x4c, 0xed, 0xa7, 0x2a, 0x88, 0x37, 0x4f, 0x75, 0x43, 0x8b, 0x5e, 0xae, 0x1c, 0xc5,
- 0xad, 0xbb, 0xbe, 0x43, 0x59, 0xc4, 0x5d, 0xa1, 0x1f, 0xb0, 0xbb, 0x71, 0xb5, 0x13, 0x74, 0xce,
- 0x0b, 0x62, 0x36, 0x66, 0x9d, 0x0d, 0xe5, 0x5a, 0x34, 0xd1, 0x6d, 0xec, 0xab, 0x92, 0x7c, 0xf1,
- 0xed, 0x5c, 0xe5, 0x61, 0x14, 0xf5, 0x72, 0xe5, 0xbf, 0x92, 0xc2, 0xb3, 0x3a, 0x82, 0xcb, 0xef,
- 0xa0, 0xbf, 0xa7, 0x88, 0x06, 0x6a, 0x20, 0x9d, 0xb8, 0x04, 0xb1, 0x52, 0x5f, 0x7f, 0x16, 0x74,
- 0x98, 0xbe, 0xf6, 0x02, 0x0c, 0x42, 0x91, 0xaf, 0x8d, 0x1e, 0x24, 0x19, 0x04, 0x27, 0x2b, 0x8a,
- 0x73, 0xb5, 0x7a, 0x61, 0x86, 0x4b, 0x1d, 0xa2, 0xff, 0xe9, 0xe9, 0x04, 0x50, 0x04, 0x22, 0xa6,
- 0xe1, 0xa2, 0xa6, 0xfd, 0xc5, 0x87, 0xbf, 0x2e, 0xab, 0x92, 0xc4, 0xf1, 0xf5, 0x9d, 0xe8, 0xfa,
- 0x67, 0x3a, 0xb1, 0x75, 0x38, 0x76, 0x2c, 0xce, 0x4a, 0x55, 0xc5, 0xa9, 0x0b, 0x91, 0x72, 0x40,
- 0x78, 0x61, 0x87, 0xb1, 0x3d, 0x85, 0xfc, 0x59, 0x5f, 0x80, 0x9b, 0x9d, 0xc8, 0x07, 0x93, 0x4a,
- 0x61, 0x7f, 0xed, 0xaa, 0x01, 0x2d, 0x2d, 0x5b, 0x49, 0xf6, 0xa9, 0x91, 0x6c, 0xda, 0x67, 0xe5,
- 0xcb, 0x64, 0xc5, 0x12, 0x14, 0xa4, 0x6e, 0x04, 0x68, 0xa9, 0xe2, 0xc2, 0x58, 0xe8, 0x95, 0xe5,
- 0x35, 0x73, 0xbf, 0x85, 0x09, 0x21, 0xb9, 0xd3, 0x57, 0xda, 0xb7, 0xa5, 0xfe, 0x12, 0x7f, 0xf4,
- 0xa5, 0x75, 0x03, 0xe5, 0x6b, 0x1a, 0x4e, 0x10, 0xcc, 0x06, 0x6e, 0x7f, 0xac, 0x14, 0x8b, 0xdd,
- 0xa7, 0x52, 0xa5, 0xfb, 0xc7, 0x5c, 0xe5, 0x3c, 0x6d, 0xd8, 0xf4, 0xaa, 0x28, 0x42, 0xb3, 0x78,
- 0x2c, 0x37, 0x00, 0x3e, 0xb2, 0x12, 0x44, 0x91, 0x43, 0xa0, 0xe4, 0xcc, 0x3a, 0x46, 0xa4, 0x69,
- 0xe8, 0x41, 0xb5, 0xee, 0x1e, 0xbb, 0x24, 0xa3, 0x2f, 0xf8, 0x8c, 0x02, 0x90, 0xae, 0x05, 0xb4,
- 0xd5, 0xaa, 0x76, 0x5b, 0x66, 0x5e, 0x3e, 0x45, 0x0e, 0x6a, 0xd6, 0xbd, 0x5c, 0xab, 0x7a, 0xb8,
- 0x71, 0xa1, 0xf5, 0xf0, 0x96, 0xc7, 0xa6, 0x1b, 0xf7, 0x71, 0xbc, 0xa6, 0x71, 0x10, 0x9f, 0x35,
- 0xca, 0x1d, 0xf6, 0x24, 0x22, 0x49, 0xd5, 0xdc, 0xbf, 0x35, 0x01, 0xc4, 0x69, 0xce, 0x31, 0x72,
- 0x38, 0xee, 0x05, 0x18, 0x75, 0xcd, 0xed, 0x40, 0xd7, 0x14, 0xa3, 0x53, 0x74, 0x47, 0xc6, 0x40,
- 0x60, 0x5c, 0x34, 0x1a, 0x98, 0x31, 0x37, 0xa7, 0x5e, 0x21, 0x20, 0xaf, 0x9e, 0xc8, 0x59, 0x54,
- 0x2a, 0xde, 0x34, 0xc4, 0x3a, 0x9d, 0x66, 0x64, 0x8b, 0x1f, 0x1d, 0x4a, 0xad, 0x6b, 0xb1, 0x7e,
- 0x8c, 0x17, 0x18, 0x4d, 0x41, 0x32, 0x68, 0xf8, 0x44, 0x0d, 0x7f, 0x21, 0x77, 0x95, 0x09, 0x70,
- 0xc3, 0xe3, 0xe3, 0xf8, 0x01, 0xe3, 0xa4, 0xdd, 0x53, 0x96, 0x1b, 0x2e, 0xcd, 0xd3, 0xc3, 0xf1,
- 0x5c, 0xdf, 0xf9, 0x78, 0xd5, 0x2b, 0xfc, 0x6f, 0xbe, 0xe8, 0x3f, 0x64, 0x2b, 0xc1, 0xd9, 0xf7,
- 0xc3, 0xad, 0xad, 0x44, 0x55, 0xa4, 0xac, 0xab, 0xfa, 0xe8, 0x39, 0xd7, 0xd3, 0xfa, 0x28, 0x7f,
- 0x7f, 0xca, 0x98, 0xbf, 0x2a, 0xe6, 0xef, 0xd0, 0x4d, 0xb4, 0x52, 0x5b, 0x34, 0x38, 0x8f, 0x96,
- 0xa3, 0x76, 0x4d, 0x73, 0x43, 0xe9, 0x1d, 0x36, 0x2b, 0xc4, 0xb3, 0x0b, 0xe8, 0x4c, 0xb2, 0xca,
- 0x5a, 0x00, 0xdf, 0x84, 0x83, 0xaf, 0x74, 0xfe, 0xe4, 0x17, 0x00, 0x28, 0xe8, 0xb4, 0x51, 0x0d,
- 0xc0, 0xb8, 0x32, 0xbb, 0xc0, 0xb0, 0xd7, 0x8b, 0x95, 0x82, 0xe4, 0xf2, 0x30, 0xac, 0x80, 0x5e,
- 0x07, 0xe5, 0xe7, 0x33, 0x6c, 0xc4, 0xd2, 0x25, 0xe7, 0x73, 0x7c, 0x33, 0xe8, 0x2e, 0x47, 0xca,
- 0x90, 0x72, 0x4d, 0x58, 0xad, 0x09, 0xbb, 0x69, 0x19, 0x64, 0x08, 0xd9, 0x0c, 0xdc, 0x13, 0x47,
- 0x8b, 0xe3, 0x0d, 0x83, 0xcc, 0x32, 0x8f, 0xf5, 0x53, 0xec, 0x6f, 0xe9, 0xa7, 0xa3, 0x48, 0x92,
- 0x91, 0x4b, 0xe2, 0xc0, 0x5f, 0x0e, 0xe2, 0x4b, 0xd0, 0xaa, 0x33, 0x05, 0x5f, 0x88, 0x77, 0xc0,
- 0x5c, 0x06, 0xa3, 0x2f, 0x4e, 0x7d, 0x9e, 0xbf, 0x10, 0x18, 0x68, 0x74, 0x54, 0x09, 0xb0, 0x52,
- 0x21, 0x72, 0x1c, 0x6b, 0x6f, 0x22, 0x9c, 0x7c, 0xe8, 0x0b, 0x98, 0x1a, 0x96, 0x0a, 0xd4, 0xd4,
- 0x5a, 0x08, 0x3c, 0xf9, 0x93, 0x2c, 0xde, 0x49, 0x3d, 0xed, 0xe4, 0x7a, 0xeb, 0x31, 0x51, 0x47,
- 0xa9, 0xcd, 0xd5, 0x1d, 0xaa, 0x8e, 0x95, 0x03, 0x2c, 0x7e, 0xd3, 0x24, 0x1c, 0x4d, 0xeb, 0x5d,
- 0xda, 0x57, 0x6e, 0xb0, 0x5a, 0xf2, 0x1a, 0x2a, 0x78, 0x5c, 0xcf, 0x3c, 0xc0, 0xe1, 0x2d, 0x2b,
- 0xb3, 0xe6, 0xde, 0x25, 0x0f, 0x61, 0x5a, 0x9a, 0x88, 0xba, 0x91, 0x0d, 0xd1, 0x63, 0x96, 0x20,
- 0x59, 0xa0, 0xe8, 0x14, 0x40, 0x42, 0x3f, 0xa5, 0x4b, 0xf1, 0x0e, 0xc0, 0xa1, 0x7f, 0x92, 0xd6,
- 0x89, 0xd6, 0x64, 0x12, 0x31, 0x75, 0xb5, 0x82, 0x82, 0xab, 0xba, 0xbd, 0xdf, 0x0d, 0x7e, 0x53,
- 0x39, 0x84, 0x8d, 0x8c, 0x2e, 0xa6, 0xc3, 0xa4, 0x3c, 0x68, 0x5a, 0x8c, 0xff, 0x47, 0xca, 0xca,
- 0x27, 0x43, 0x5a, 0x7b, 0x0b, 0xbe, 0xff, 0x02, 0x7d, 0x42, 0xe6, 0x44, 0xb5, 0x73, 0xdc, 0xa9,
- 0x6d, 0x54, 0x0e, 0x4e, 0x04, 0x24, 0x01, 0x87, 0x6f, 0x10, 0x2b, 0x43, 0x08, 0xf2, 0x8a, 0xe7,
- 0x60, 0xb9, 0xd4, 0x09, 0xce, 0x66, 0x42, 0xde, 0xa7, 0xa6, 0xaa, 0x4a, 0xc7, 0x81, 0x5b, 0xdc,
- 0x66, 0xd0, 0x7a, 0x90, 0x24, 0xf5, 0x6a, 0xf1, 0x7e, 0xe8, 0x35, 0x0d, 0x66, 0x15, 0x9b, 0x54,
- 0xe8, 0xbe, 0x99, 0xcf, 0x59, 0x0f, 0x30, 0x43, 0x36, 0x6c, 0xb0, 0xb9, 0xf5, 0xcc, 0x32, 0x19,
- 0x11, 0x06, 0x6c, 0x7f, 0xec, 0x34, 0x0c, 0xf6, 0xab, 0x31, 0xaa, 0xe0, 0xd5, 0xd4, 0x99, 0xd7,
- 0x39, 0x22, 0x3f, 0xa8, 0x7e, 0x79, 0xf1, 0x0e, 0x33, 0x0b, 0xe2, 0x28, 0xbf, 0xfb, 0x94, 0x3c,
- 0x58, 0xf8, 0x79, 0xb3, 0x4b, 0xbc, 0x1c, 0x50, 0xe9, 0x39, 0x41, 0xd5, 0xe3, 0x6c, 0x5c, 0x07,
- 0x9a, 0x12, 0x74, 0x71, 0x54, 0xaf, 0x14, 0x3a, 0x67, 0x0b, 0xb8, 0x40, 0xe1, 0x64, 0x96, 0x2a,
- 0x28, 0x9a, 0x86, 0xe6, 0x0f, 0x48, 0x57, 0x60, 0xd9, 0xf4, 0x95, 0xd5, 0x02, 0xa7, 0x80, 0x2c,
- 0xfd, 0x33, 0xf5, 0xb7, 0xc6, 0x30, 0xf4, 0x1f, 0xee, 0xdc, 0x60, 0xcc, 0x8a, 0xfa, 0x85, 0x23,
- 0x00, 0x3a, 0x04, 0xc0, 0xf3, 0x8f, 0xd6, 0x59, 0xf5, 0x1a, 0xcf, 0x07, 0xaf, 0xac, 0xab, 0x01,
- 0x5b, 0xf7, 0x3d, 0x5b, 0xeb, 0xf4, 0x01, 0xf3, 0xa3, 0x1f, 0xb9, 0xea, 0xf1, 0xcc, 0xb4, 0x10,
- 0x46, 0x2f, 0x46, 0xb3, 0xd2, 0x36, 0x40, 0x9c, 0x8c, 0xa4, 0xdc, 0xb3, 0x8c, 0xfc, 0xa8, 0xdd,
- 0xce, 0x82, 0xe3, 0x4c, 0x08, 0xf7, 0x94, 0x0a, 0x4d, 0x92, 0x1e, 0x62, 0xfb, 0xfa, 0x90, 0xf4,
- 0x10, 0x4e, 0x65, 0x04, 0x7b, 0x8e, 0xd7, 0x18, 0x02, 0x24, 0xf5, 0xf3, 0x93, 0xe8, 0x5b, 0x00,
- 0x94, 0xc8, 0xbb, 0x7e, 0xd6, 0x7b, 0xa5, 0x85, 0x3f, 0x56, 0xe1, 0x37, 0xb0, 0x47, 0x98, 0x5d,
- 0x9e, 0x22, 0x7e, 0x25, 0x3a, 0x7c, 0x44, 0xb1, 0xbf, 0xfd, 0x09, 0x61, 0xbb, 0x86, 0x45, 0xa4,
- 0xbc, 0x7c, 0x6c, 0xb3, 0x25, 0xb1, 0x45, 0x5c, 0x92, 0x3e, 0x4b, 0xf4, 0xa3, 0x7f, 0x5d, 0x0a,
- 0x58, 0xee, 0x28, 0xbc, 0xac, 0x77, 0x4f, 0xcf, 0xb8, 0x72, 0x1d, 0x2c, 0x2c, 0x2e, 0x3d, 0x41,
- 0xb7, 0xe3, 0x77, 0xe4, 0x31, 0xdd, 0x6e, 0xf2, 0x6a, 0x20, 0x0b, 0x2a, 0x55, 0xdf, 0x29, 0x9a,
- 0xfd, 0xf9, 0x15, 0x2b, 0x3e, 0xe9, 0xa8, 0xb3, 0xff, 0x85, 0x4c, 0x53, 0xb7, 0x8a, 0xb8, 0x99,
- 0xde, 0x88, 0x27, 0xa6, 0xa9, 0xd2, 0x4a, 0xe1, 0xac, 0xb4, 0xff, 0x12, 0xc8, 0x55, 0xe2, 0x58,
- 0x95, 0xf5, 0xdd, 0x3d, 0xcf, 0xa0, 0xba, 0x8a, 0x20, 0xb7, 0xe8, 0x2b, 0x7e, 0xd9, 0x5a, 0x07,
- 0xa0, 0x1f, 0xec, 0x0f, 0x89, 0x1c, 0xc4, 0xae, 0xcd, 0xdd, 0x97, 0x08, 0x02, 0xca, 0x02, 0x70,
- 0x24, 0xc4, 0x83, 0xcb, 0xc8, 0x19, 0x52, 0x6f, 0xe7, 0x9a, 0x05, 0xa7, 0x89, 0xa4, 0xc1, 0xc4,
- 0x15, 0x12, 0x95, 0x04, 0x16, 0xc8, 0x07, 0xe2, 0xb2, 0x76, 0x5c, 0x67, 0x96, 0x35, 0x23, 0xda,
- 0x1a, 0xd7, 0xe8, 0xb5, 0xa9, 0x98, 0x31, 0x5f, 0x6d, 0xfd, 0xae, 0xf1, 0xc2, 0x44, 0x49, 0x7f,
- 0x58, 0x9b, 0x07, 0x4c, 0x84, 0xf4, 0x24, 0x70, 0x1e, 0xe0, 0xfb, 0xa3, 0xa1, 0xfc, 0x6c, 0x8d,
- 0xaa, 0x2f, 0xef, 0xa7, 0x2d, 0x2f, 0x01, 0x2b, 0xed, 0x73, 0xf6, 0xc6, 0x89, 0x52, 0x2e, 0xf5,
- 0x91, 0x87, 0x00, 0x79, 0x3a, 0xec, 0xb9, 0xe9, 0x71, 0x98, 0xdf, 0x7b, 0x01, 0x8e, 0x21, 0x1f,
- 0x50, 0xab, 0xd4, 0x2a, 0x82, 0x62, 0xbf, 0x8a, 0x8d, 0x24, 0x13, 0x95, 0xd0, 0xe9, 0x93, 0x39,
- 0x3e, 0x73, 0x1a, 0x4e, 0xb4, 0x41, 0xca, 0x08, 0x79, 0xea, 0x14, 0x29, 0xaa, 0x0d, 0xff, 0x12,
- 0x85, 0x5c, 0xc2, 0x5e, 0xea, 0x54, 0xa2, 0x4c, 0xf1, 0x3f, 0xdc, 0x73, 0x38, 0x12, 0xec, 0x02,
- 0x67, 0x8e, 0x7b, 0xca, 0x41, 0x15, 0xfe, 0xa1, 0x59, 0x12, 0x5d, 0xd4, 0x23, 0x12, 0x19, 0x81,
- 0x2c, 0x58, 0x5b, 0x1a, 0x78, 0x51, 0xe3, 0xb7, 0xb2, 0xdc, 0xbd, 0x9b, 0xa4, 0x74, 0x6d, 0xa5,
- 0xda, 0x5d, 0x6c, 0xbf, 0x0c, 0x50, 0xd4, 0xf9, 0x34, 0xab, 0x9f, 0x2f, 0xc2, 0x81, 0x48, 0x2f,
- 0x09, 0x23, 0x0f, 0xbf, 0x58, 0x07, 0x20, 0x53, 0x88, 0xe1, 0x54, 0x1e, 0x17, 0xe9, 0x04, 0xdf,
- 0x48, 0xc3, 0x04, 0x89, 0xa9, 0x5e, 0x4f, 0x0e, 0xb8, 0xc4, 0x67, 0x0d, 0x7e, 0x55, 0xe6, 0x1b,
- 0x1a, 0x3e, 0xd4, 0x1f, 0x94, 0xf4, 0x56, 0x2f, 0x70, 0x68, 0x6d, 0xa0, 0xaa, 0xa0, 0x5b, 0xf2,
- 0x97, 0xa7, 0x0a, 0x56, 0x7a, 0xa3, 0x4b, 0x9d, 0x48, 0xce, 0xe0, 0xac, 0xe2, 0x1e, 0xb4, 0x73,
- 0x55, 0xdd, 0xad, 0x09, 0xb0, 0x5a, 0x6d, 0x8c, 0x34, 0xd0, 0x20, 0x6b, 0x71, 0x18, 0x4c, 0xb9,
- 0x7f, 0x8e, 0xdc, 0x05, 0x2d, 0xea, 0x77, 0xe5, 0xa4, 0xab, 0xbb, 0x33, 0xb9, 0x03, 0x87, 0x62,
- 0x60, 0x13, 0xfd, 0x3b, 0x4e, 0x3f, 0x20, 0x1c, 0xb2, 0x11, 0x42, 0xda, 0xc7, 0xe5, 0x1c, 0x4e,
- 0x40, 0xfd, 0x61, 0xa6, 0x07, 0x51, 0x97, 0x91, 0x31, 0xd1, 0xf6, 0xe7, 0xed, 0xaa, 0x56, 0xcf,
- 0x91, 0x17, 0xa5, 0x7f, 0x7e, 0xce, 0xd2, 0x31, 0x54, 0xb7, 0xca, 0xf8, 0xdd, 0x05, 0x4a, 0xf5,
- 0x81, 0xd3, 0x6b, 0x49, 0x18, 0x57, 0xfa, 0x0e, 0x9b, 0xdb, 0xf5, 0x16, 0x51, 0xc4, 0xa4, 0x4a,
- 0xe6, 0x64, 0x86, 0xe7, 0x2b, 0x66, 0x53, 0x1e, 0x71, 0xe7, 0x37, 0xf3, 0xb6, 0x06, 0x0e, 0x3e,
- 0x98, 0x09, 0x9e, 0x97, 0xc6, 0x26, 0xc8, 0x3f, 0x4a, 0x27, 0xbc, 0xd5, 0x32, 0x0b, 0x9c, 0xba,
- 0xe1, 0xc7, 0xaf, 0x1f, 0x30, 0x3d, 0xf2, 0xf0, 0x4f, 0x34, 0x45, 0x88, 0x3f, 0xb5, 0x7c, 0x44,
- 0xc2, 0x68, 0x5e, 0xe0, 0x36, 0x3a, 0x82, 0x93, 0xd7, 0x89, 0xb6, 0xbd, 0x2b, 0xb9, 0x02, 0x9d,
- 0x31, 0x55, 0x30, 0xf6, 0xe2, 0x7f, 0x1e, 0x65, 0x70, 0xf6, 0x41, 0x7f, 0x33, 0x3c, 0xa2, 0x31,
- 0x35, 0x66, 0x1b, 0x51, 0xb2, 0xa0, 0xf8, 0x9a, 0x8a, 0xa9, 0xa8, 0x48, 0x6d, 0x8b, 0xeb, 0x70,
- 0x46, 0x55, 0xd5, 0x81, 0x0b, 0xdf, 0x3f, 0xe5, 0xf7, 0xb4, 0xd1, 0x58, 0xe5, 0x7e, 0xc3, 0xc5,
- 0x69, 0x19, 0xa7, 0xdf, 0xc0, 0x4c, 0xf0, 0x05, 0x2c, 0x8b, 0xbb, 0x01, 0xe2, 0x21, 0x96, 0x57,
- 0x06, 0x22, 0xe1, 0xcf, 0x59, 0x61, 0x8a, 0x7f, 0x9c, 0x30, 0xf1, 0x63, 0xca, 0x47, 0xfd, 0x77,
- 0xf0, 0x00, 0xff, 0xa0, 0xe8, 0xd4, 0xc1, 0x9c, 0xb9, 0xba, 0x48, 0xb9, 0x3d, 0xef, 0x54, 0xd7,
- 0xe3, 0x8c, 0x25, 0x3a, 0x2b, 0x8d, 0x1c, 0x67, 0xc7, 0xe9, 0xf4, 0x22, 0x37, 0xa9, 0xa7, 0x9f,
- 0xd9, 0x0c, 0x4d, 0xea, 0x84, 0x70, 0xfb, 0x7f, 0x8c, 0x7d, 0xbe, 0x28, 0x88, 0x50, 0xff, 0x87,
- 0xcd, 0x85, 0x5f, 0x15, 0xac, 0xc2, 0x97, 0xb0, 0x6e, 0x83, 0x9b, 0xe5, 0x7e, 0xc2, 0x54, 0x38,
- 0x0b, 0xeb, 0x7a, 0x22, 0xb2, 0xe7, 0x1f, 0x3d, 0xe6, 0x7f, 0x2e, 0x34, 0x5f, 0xea, 0x27, 0x7e,
- 0x17, 0xd5, 0xf1, 0xcc, 0x25, 0x90, 0x9d, 0xa3, 0x87, 0xf8, 0x3b, 0xf3, 0x3e, 0x55, 0x3a, 0xbd,
- 0xdd, 0x76, 0x26, 0x30, 0x45, 0xa1, 0x2c, 0x1f, 0x2b, 0x64, 0xd2, 0xf1, 0x1a, 0x6d, 0x54, 0x53,
- 0x55, 0x5e, 0xde, 0x63, 0x86, 0x90, 0x6b, 0x37, 0x29, 0xc2, 0xb1, 0x75, 0x82, 0xf6, 0x59, 0xc2,
- 0x40, 0xc1, 0x95, 0x6f, 0x85, 0xbc, 0x22, 0x64, 0x97, 0xba, 0x56, 0x63, 0x9b, 0x3f, 0xe8, 0xda,
- 0x68, 0xe1, 0xed, 0x4c, 0x53, 0xb8, 0x8f, 0x12, 0x59, 0x12, 0xf1, 0x52, 0x91, 0x06, 0x17, 0x01,
- 0x64, 0xa8, 0xe2, 0xa7, 0x48, 0xb7, 0x99, 0x00, 0x6f, 0x67, 0x59, 0x3d, 0x82, 0x34, 0xfe, 0x7d,
- 0x82, 0xd9, 0x79, 0x4a, 0xbd, 0xad, 0x91, 0x3c, 0xb2, 0xd2, 0xde, 0x1e, 0x46, 0xae, 0xd0, 0x2b,
- 0xe7, 0x2f, 0x60, 0x72, 0x0b, 0x07, 0xc8, 0x05, 0x4b, 0xed, 0xeb, 0x31, 0x83, 0x9d, 0x48, 0x06,
- 0x24, 0x4f, 0x9c, 0xcb, 0x35, 0x63, 0x1c, 0x01, 0x8f, 0x75, 0xa1, 0x65, 0xd1, 0xac, 0xe1, 0x26,
- 0x92, 0x43, 0xb8, 0x2d, 0x1a, 0x30, 0xf9, 0x9f, 0x82, 0xdc, 0xbf, 0x84, 0xc4, 0x72, 0x2b, 0x42,
- 0x9e, 0xc9, 0x55, 0x14, 0x35, 0xf3, 0x40, 0xbb, 0x20, 0x8a, 0xbf, 0x2c, 0x3a, 0x2f, 0x80, 0x00,
- 0xe3, 0x80, 0x0f, 0x91, 0x7a, 0xfd, 0xf6, 0xf2, 0x36, 0x24, 0x42, 0x36, 0xdd, 0xdd, 0xf3, 0x68,
- 0x7a, 0xf3, 0x75, 0x63, 0x50, 0x0b, 0x34, 0x22, 0x70, 0xa3, 0x51, 0x9a, 0x2f, 0x47, 0xbf, 0x76,
- 0x26, 0x74, 0x3e, 0xf2, 0x9b, 0x4b, 0x7a, 0x82, 0x2b, 0x48, 0x99, 0x90, 0x91, 0xd4, 0xb4, 0xc4,
- 0xcd, 0x09, 0xe0, 0x56, 0x1f, 0x0b, 0x88, 0x2f, 0xfb, 0xc7, 0x41, 0x39, 0x2e, 0x98, 0xd3, 0xc1,
- 0x9b, 0xd2, 0xba, 0x9d, 0xd3, 0xf3, 0x08, 0xce, 0x64, 0x0f, 0x85, 0xd1, 0x17, 0x6d, 0x11, 0xbf,
- 0x1b, 0x07, 0x07, 0x6d, 0x1d, 0x4b, 0x71, 0xd0, 0x86, 0xa6, 0x30, 0x0f, 0x44, 0xa5, 0x6b, 0x41,
- 0x78, 0x9e, 0xe8, 0xc9, 0x1c, 0xa0, 0x54, 0x04, 0x4a, 0x8b, 0x7f, 0x1b, 0x41, 0xe3, 0x13, 0xe3,
- 0xca, 0xf1, 0x4b, 0x6a, 0xa4, 0x16, 0x77, 0x02, 0xe2, 0x69, 0x8d, 0x02, 0x5a, 0xe2, 0x46, 0x29,
- 0x3e, 0xee, 0x14, 0x59, 0xd0, 0x05, 0x9a, 0x67, 0xda, 0x01, 0x0a, 0xce, 0x95, 0xb3, 0x90, 0xef,
- 0x47, 0x3d, 0x86, 0xab, 0xa3, 0xed, 0x71, 0xa7, 0xb7, 0x3e, 0xfd, 0x88, 0x6a, 0xe8, 0xf1, 0x1e,
- 0x65, 0x63, 0x39, 0x3f, 0x06, 0x9b, 0x81, 0x6c, 0x22, 0x69, 0x67, 0xb9, 0x02, 0x1b, 0x16, 0x5e,
- 0xe8, 0x7b, 0xf7, 0x5c, 0x37, 0x78, 0x0c, 0x84, 0x43, 0xef, 0x4d, 0xf7, 0xf0, 0xe6, 0x3d, 0xde,
- 0x8c, 0xbb, 0x7d, 0xcc, 0xe3, 0x3a, 0xf8, 0x97, 0xab, 0xe8, 0xed, 0xdf, 0x67, 0x46, 0xfc, 0x6f,
- 0x07, 0x02, 0xaa, 0x83, 0xbe, 0xd0, 0x0b, 0xe3, 0x7d, 0x4f, 0xaa, 0xf1, 0x1d, 0x70, 0x5b, 0x7b,
- 0xb4, 0xab, 0x35, 0xc3, 0x3e, 0x36, 0x8b, 0xb0, 0x18, 0x3d, 0x3c, 0x89, 0x3d, 0x3b, 0xdf, 0x89,
- 0xed, 0x6c, 0x21, 0xc3, 0xc9, 0x57, 0x11, 0x42, 0x55, 0xb2, 0x51, 0x7b, 0x5e, 0x04, 0x8c, 0x20,
- 0xea, 0xa0, 0xfd, 0x57, 0xf4, 0x2e, 0x5f, 0xee, 0x07, 0x10, 0xd5, 0xa9, 0x89, 0x23, 0x84, 0x5c,
- 0x7d, 0x12, 0x8b, 0x83, 0x70, 0x77, 0x40, 0x5a, 0x60, 0xa3, 0x13, 0x9d, 0x14, 0x5f, 0xaf, 0x74,
- 0x83, 0xfe, 0xda, 0xcc, 0xf7, 0xfb, 0x7d, 0x62, 0xbd, 0x42, 0x55, 0x44, 0xc5, 0xde, 0x55, 0xd3,
- 0xb0, 0x0b, 0xd3, 0xea, 0x7d, 0x96, 0xe5, 0xee, 0xe1, 0x45, 0x6d, 0xe0, 0x3d, 0x9e, 0x62, 0xd4,
- 0xef, 0xb5, 0x0a, 0x32, 0x05, 0xcd, 0x38, 0x99, 0x61, 0xdd, 0xf6, 0xf3, 0x85, 0xce, 0x1a, 0xb3,
- 0x57, 0xfc, 0xd1, 0x63, 0x7c, 0x84, 0xb6, 0xa2, 0x84, 0xf4, 0x3e, 0x34, 0xb9, 0x3f, 0xb9, 0x8e,
- 0xd0, 0x30, 0x23, 0x0a, 0x27, 0x3c, 0x19, 0xc6, 0xd2, 0x8e, 0xb9, 0x55, 0xb7, 0x34, 0xab, 0x60,
- 0x52, 0xd3, 0x45, 0x09, 0xde, 0x0b, 0x41, 0x66, 0x04, 0x71, 0x1e, 0x4e, 0xba, 0x09, 0x7b, 0xab,
- 0x3a, 0x85, 0x7d, 0xfc, 0x95, 0x9b, 0x71, 0xb9, 0x78, 0x3f, 0x41, 0x44, 0x5c, 0xd2, 0x5f, 0x9f,
- 0xe7, 0xc7, 0xf4, 0x6c, 0x52, 0x07, 0xda, 0xb2, 0x39, 0xc8, 0xd9, 0x77, 0x60, 0x12, 0xd3, 0x7b,
- 0x70, 0x5a, 0x7e, 0x66, 0xb1, 0x0b, 0x4e, 0x86, 0xa4, 0x31, 0x47, 0x1c, 0x72, 0x8a, 0x89, 0x96,
- 0x8e, 0x24, 0xa4, 0x1f, 0x07, 0x11, 0x50, 0xc3, 0x05, 0x77, 0x82, 0xfa, 0x98, 0xba, 0xec, 0xa0,
- 0x71, 0x59, 0x95, 0x6f, 0xa3, 0x2d, 0x1f, 0x26, 0xc0, 0x73, 0x2e, 0x13, 0x38, 0xdc, 0x57, 0x46,
- 0xec, 0x4d, 0x4f, 0x11, 0xa4, 0x35, 0x5e, 0x37, 0x0e, 0x1b, 0xe7, 0x32, 0x02, 0xf8, 0x81, 0x67,
- 0xb1, 0x51, 0x1f, 0x34, 0xe5, 0xad, 0xa0, 0x07, 0xd8, 0xc0, 0xae, 0x52, 0xed, 0x4e, 0xbe, 0x6e,
- 0xe8, 0x92, 0x85, 0x76, 0x8d, 0x71, 0xd6, 0xac, 0x21, 0x61, 0x14, 0x75, 0xf3, 0xb7, 0x66, 0x8e,
- 0xf5, 0xd1, 0x8b, 0x7a, 0xfd, 0xc6, 0x39, 0x2d, 0x0a, 0x0e, 0x63, 0x86, 0x1e, 0x0c, 0x55, 0xbc,
- 0xf3, 0x52, 0xf8, 0x8e, 0x9e, 0x94, 0xae, 0xa9, 0x29, 0x28, 0x98, 0x8c, 0x64, 0x2a, 0x8c, 0x87,
- 0x21, 0x01, 0x5d, 0xd3, 0x79, 0xbf, 0x09, 0x1f, 0x8c, 0xe4, 0xa2, 0xf7, 0xc6, 0x49, 0xa9, 0xe1,
- 0xea, 0x6d, 0x6d, 0xc6, 0x40, 0x4a, 0x02, 0x25, 0x2a, 0xb2, 0xc5, 0x29, 0x87, 0x00, 0x21, 0x40,
- 0x88, 0x6b, 0x18, 0xea, 0x19, 0x09, 0xec, 0x39, 0x54, 0x33, 0xea, 0x10, 0x6b, 0x5a, 0x10, 0x50,
- 0x3b, 0x5a, 0xd6, 0x1e, 0x12, 0x02, 0xc4, 0x09, 0x12, 0x01, 0xc1, 0x2a, 0x31, 0xd1, 0x73, 0xa3,
- 0xf8, 0xcf, 0x28, 0x05, 0xe5, 0xb3, 0x46, 0x90, 0x35, 0xf2, 0x7f, 0xd5, 0x1b, 0x5f, 0xe5, 0x11,
- 0x5a, 0x47, 0x6f, 0xa0, 0xf8, 0x59, 0x94, 0xeb, 0xd7, 0x08, 0x64, 0x6f, 0x3a, 0x97, 0x86, 0xeb,
- 0xad, 0xa0, 0x72, 0x8d, 0xac, 0x55, 0xc5, 0xd1, 0xd4, 0xa0, 0xb9, 0x0e, 0xc0, 0x9b, 0x03, 0xd3,
- 0x01, 0xef, 0xdd, 0xa9, 0x2a, 0x98, 0x11, 0xfa, 0xd6, 0x2b, 0xc2, 0x51, 0xe8, 0xed, 0x0e, 0x34,
- 0x2a, 0x16, 0x04, 0xbf, 0x6f, 0x46, 0x15, 0x57, 0x26, 0xee, 0xd1, 0x6b, 0xd9, 0x06, 0x1d, 0x8c,
- 0x52, 0xf3, 0xa0, 0x56, 0xe8, 0x5d, 0xb2, 0xbd, 0x95, 0x0f, 0x08, 0x14, 0xa0, 0x5b, 0x08, 0xd9,
- 0x89, 0x21, 0x38, 0x39, 0x5f, 0x1a, 0x22, 0xc1, 0x20, 0x00, 0x8f, 0x98, 0x8d, 0xd1, 0x5e, 0xc7,
- 0xc0, 0x97, 0x59, 0xb4, 0xe4, 0xe5, 0x69, 0xbd, 0x33, 0x75, 0xbe, 0x86, 0x0d, 0xbb, 0x28, 0xe0,
- 0x3e, 0xf5, 0x09, 0xb7, 0x8f, 0xbd, 0xca, 0x27, 0x5d, 0x1d, 0x9b, 0x80, 0x89, 0x44, 0xc2, 0xc6,
- 0xc6, 0x93, 0x9c, 0x3f, 0x1e, 0x5d, 0x41, 0xc4, 0xb3, 0x73, 0x1f, 0x22, 0x0d, 0x49, 0x6b, 0x68,
- 0x5d, 0xb2, 0x4a, 0xba, 0x9e, 0xe8, 0x63, 0x3c, 0xa3, 0x67, 0x59, 0x5e, 0xea, 0x88, 0x35, 0xbf,
- 0xc4, 0xfe, 0xb4, 0xa5, 0x93, 0x1f, 0x1e, 0x8e, 0x79, 0x5e, 0x0c, 0x64, 0x12, 0x9e, 0xf5, 0x04,
- 0xf2, 0x9c, 0x29, 0x01, 0xb9, 0xf3, 0xc2, 0x33, 0xa5, 0xbb, 0xc5, 0x1f, 0x72, 0x1c, 0x73, 0x78,
- 0xc1, 0x21, 0x50, 0x1d, 0x41, 0x47, 0xad, 0x5c, 0x0e, 0x7b, 0x55, 0xb9, 0x75, 0x8f, 0x56, 0xd3,
- 0x0d, 0xb2, 0x4c, 0x61, 0x40, 0x83, 0xe8, 0xd7, 0xa6, 0x7b, 0x67, 0xd6, 0xac, 0x60, 0xb2, 0x04,
- 0x6d, 0x1c, 0x3a, 0x59, 0x28, 0x20, 0x23, 0x6a, 0xdc, 0x1c, 0x59, 0xc2, 0x0f, 0xc4, 0xb4, 0xe9,
- 0x31, 0xec, 0x91, 0xa8, 0x31, 0xb9, 0x28, 0x86, 0xb4, 0xe4, 0x15, 0xf2, 0x71, 0x71, 0xcc, 0xfc,
- 0x7d, 0xf7, 0x6d, 0x6a, 0x21, 0x1b, 0x36, 0x35, 0x3e, 0xe9, 0x81, 0x3b, 0x65, 0xdd, 0x2b, 0x59,
- 0xd6, 0x26, 0xf3, 0xb0, 0x02, 0xc8, 0x89, 0x4a, 0xf8, 0x12, 0x87, 0x97, 0xb8, 0x05, 0x8d, 0xea,
- 0xff, 0x07, 0xe6, 0x22, 0x58, 0x34, 0x4c, 0x13, 0xf1, 0x9e, 0xf4, 0x39, 0x49, 0x60, 0x92, 0x63,
- 0x21, 0x53, 0x17, 0x2d, 0x48, 0x18, 0xf4, 0x19, 0x71, 0xf1, 0xae, 0x18, 0x67, 0x33, 0xbc, 0x97,
- 0xcf, 0x83, 0x5f, 0x05, 0xf1, 0xe6, 0x61, 0x07, 0x1d, 0x8c, 0xd6, 0x6e, 0x5a, 0xb9, 0xdd, 0xdc,
- 0xa7, 0x58, 0x25, 0xa2, 0x32, 0xee, 0x48, 0x49, 0x86, 0x1b, 0x15, 0x5e, 0x56, 0x31, 0x91, 0x28,
- 0x94, 0xf8, 0xde, 0x07, 0x70, 0x30, 0x98, 0x67, 0xa9, 0x47, 0xc0, 0x19, 0x82, 0xcf, 0x0b, 0x55,
- 0x2a, 0xe6, 0x7f, 0xd2, 0x96, 0x14, 0x2a, 0xbe, 0xb5, 0x4b, 0x82, 0xe7, 0x80, 0x4b, 0x11, 0xeb,
- 0x25, 0xfe, 0xdd, 0xc8, 0xdc, 0xb6, 0xa2, 0x74, 0x8c, 0x61, 0xab, 0xc5, 0x08, 0x4a, 0xcd, 0x51,
- 0x94, 0x2b, 0xf6, 0xcc, 0x1c, 0x09, 0xc7, 0x84, 0xb5, 0x96, 0x24, 0xdf, 0x5a, 0x2d, 0x73, 0xb0,
- 0xe1, 0xaa, 0x19, 0xca, 0x0f, 0x31, 0x28, 0xd1, 0xea, 0xe4, 0x48, 0x12, 0x0b, 0xe0, 0xb5, 0x31,
- 0x70, 0x58, 0xd9, 0x80, 0xf1, 0x31, 0xff, 0xa3, 0x60, 0x0c, 0x58, 0x7d, 0x18, 0x06, 0x4d, 0x54,
- 0x04, 0x3e, 0x8d, 0xb1, 0x5b, 0x4c, 0xde, 0x1c, 0x35, 0xf7, 0xab, 0x5a, 0x5e, 0x1e, 0x25, 0x41,
- 0x22, 0xc4, 0xd7, 0x46, 0x52, 0x6c, 0xe3, 0xbf, 0xd6, 0xc0, 0x4a, 0x9a, 0x66, 0x0f, 0xe0, 0xa9,
- 0xcb, 0x0f, 0x7b, 0xcb, 0x3e, 0xa2, 0x8f, 0xd3, 0x93, 0x2c, 0xec, 0x92, 0xf1, 0x51, 0x51, 0x6f,
- 0x5e, 0x84, 0x4c, 0x41, 0x07, 0x8c, 0xa6, 0x82, 0x63, 0x80, 0x7e, 0x95, 0x94, 0xaf, 0x63, 0xc6,
- 0x2a, 0x26, 0x0d, 0x01, 0x8d, 0x6a, 0x86, 0x7c, 0xaf, 0x55, 0x3b, 0x6b, 0xc6, 0x81, 0xfb, 0xe8,
- 0x64, 0x12, 0xef, 0x81, 0x38, 0x2b, 0xaf, 0xd9, 0x57, 0x56, 0xb6, 0xe2, 0x83, 0x7e, 0x7d, 0x19,
- 0x63, 0xd5, 0x10, 0x4f, 0x14, 0xfe, 0xb0, 0x57, 0x87, 0x5e, 0x6e, 0xe7, 0xb3, 0xb6, 0xd3, 0x0d,
- 0x6e, 0x18, 0xcf, 0xa5, 0x0f, 0x5d, 0x71, 0x8d, 0x6b, 0xc7, 0xb4, 0xb1, 0x54, 0x0e, 0xe4, 0x2d,
- 0xf2, 0xff, 0x0a, 0xa0, 0x75, 0xee, 0xc7, 0x37, 0xd0, 0xbd, 0xba, 0xd7, 0x35, 0x89, 0xf8, 0x7d,
- 0x4b, 0x32, 0x83, 0x4f, 0x41, 0xca, 0xd9, 0xc7, 0x4b, 0xee, 0x1d, 0x95, 0xf7, 0xab, 0xdf, 0x8f,
- 0x53, 0xaf, 0xac, 0x77, 0x47, 0xea, 0x92, 0x47, 0xa4, 0x25, 0xd7, 0x19, 0x8c, 0x99, 0xf7, 0x59,
- 0x74, 0xb4, 0x9b, 0xe2, 0xcc, 0x6c, 0x56, 0xdc, 0xc1, 0x30, 0xa1, 0x85, 0x5b, 0xdd, 0xfa, 0x91,
- 0x59, 0x2d, 0xd9, 0xce, 0x93, 0x0c, 0x31, 0xa8, 0x85, 0xcf, 0xb3, 0xb4, 0x64, 0x32, 0xa3, 0x7b,
- 0xc7, 0xd4, 0x16, 0xc2, 0x57, 0x20, 0x60, 0x9b, 0x5b, 0x79, 0x4a, 0xab, 0xe1, 0xc3, 0x41, 0x30,
- 0xc9, 0xe2, 0x4d, 0x60, 0x8f, 0xab, 0x0a, 0xbf, 0x42, 0x80, 0xc2, 0xc6, 0x51, 0xa2, 0xa2, 0x6a,
- 0x9d, 0x5f, 0xab, 0x69, 0x7f, 0x5c, 0x7d, 0x3a, 0x13, 0xce, 0x99, 0x31, 0x55, 0x59, 0x09, 0x89,
- 0xda, 0x17, 0x7d, 0x1e, 0xea, 0x7a, 0xe0, 0x75, 0x4b, 0xba, 0xb1, 0x93, 0xbc, 0xc7, 0xc5, 0x84,
- 0xc7, 0x15, 0xb0, 0x9e, 0xc1, 0xd5, 0x36, 0x67, 0xe6, 0x27, 0xb4, 0xb2, 0xcc, 0xd8, 0x9b, 0x8d,
- 0x58, 0x62, 0x90, 0x3b, 0x89, 0x3c, 0x84, 0x0a, 0x69, 0x7a, 0xc9, 0x24, 0x52, 0xf3, 0x50, 0x51,
- 0x23, 0x52, 0x0d, 0x3d, 0xbf, 0x12, 0x0a, 0x92, 0x50, 0xae, 0xb1, 0xb5, 0xa9, 0xc9, 0x46, 0x0c,
- 0xf6, 0x09, 0xdc, 0x86, 0x6b, 0x67, 0x2e, 0x8d, 0x8d, 0x93, 0x21, 0x85, 0x34, 0xdb, 0x98, 0x21,
- 0x6a, 0x32, 0xa1, 0x9d, 0xec, 0x09, 0xc0, 0x92, 0x60, 0x65, 0xd8, 0xad, 0xad, 0x7b, 0xda, 0xd6,
- 0xb2, 0xe5, 0xe5, 0x33, 0xd0, 0xe6, 0x85, 0x9e, 0xf6, 0x34, 0xba, 0x5e, 0xf2, 0x9f, 0x05, 0x6e,
- 0x95, 0xd6, 0xfd, 0xc6, 0x18, 0x22, 0x74, 0x1a, 0x33, 0xa6, 0xad, 0x68, 0x13, 0x85, 0x05, 0xdc,
- 0xb3, 0xc1, 0x76, 0xee, 0xf5, 0x6f, 0xd9, 0x27, 0x82, 0xa5, 0x28, 0x80, 0xf7, 0x0d, 0xf9, 0x80,
- 0xeb, 0x41, 0x66, 0xe9, 0x7f, 0x53, 0x1c, 0x1d, 0x1c, 0x53, 0xfa, 0x55, 0xe6, 0xc0, 0x2b, 0x80,
- 0xe1, 0x47, 0x5a, 0xce, 0x4b, 0x6e, 0xab, 0x20, 0xa5, 0x43, 0x34, 0xec, 0x24, 0x12, 0xc8, 0x40,
- 0x86, 0x54, 0x82, 0x46, 0xe4, 0x1f, 0x8b, 0x0b, 0x5f, 0x54, 0xa1, 0xfc, 0xfd, 0xee, 0x71, 0x64,
- 0x49, 0xc8, 0xd7, 0x38, 0x89, 0xea, 0x6e, 0xf4, 0x66, 0x8d, 0x1c, 0xee, 0x8d, 0xa8, 0xa0, 0x6c,
- 0x15, 0xdc, 0xe6, 0x41, 0xac, 0x6b, 0x9a, 0xbb, 0x9e, 0xe7, 0x10, 0xea, 0x6e, 0x37, 0xe1, 0x9f,
- 0x3d, 0x17, 0xa5, 0x93, 0x54, 0x92, 0xc2, 0x2e, 0xe9, 0x08, 0x57, 0x6c, 0x46, 0xff, 0x2e, 0xd9,
- 0x80, 0x03, 0xdf, 0x99, 0xa4, 0xf4, 0xde, 0x11, 0xc6, 0x5b, 0xe0, 0x88, 0x0f, 0x87, 0x6b, 0x20,
- 0x61, 0xf5, 0x37, 0x74, 0x64, 0x35, 0x62, 0xb9, 0x36, 0xcc, 0x95, 0x2a, 0xaf, 0x0e, 0x95, 0x09,
- 0xe2, 0x61, 0xb2, 0xa3, 0x85, 0x21, 0x24, 0xd6, 0x5d, 0xeb, 0x7d, 0x13, 0xe4, 0xd9, 0x2e, 0xec,
- 0x64, 0x24, 0x2d, 0x01, 0x07, 0xc2, 0xba, 0x5c, 0xc1, 0x2a, 0x77, 0x88, 0xf0, 0x01, 0x75, 0xf1,
- 0x7b, 0xe3, 0x63, 0x67, 0x5a, 0x7c, 0x97, 0x61, 0x43, 0x36, 0x40, 0x43, 0x31, 0x40, 0x76, 0x2c,
- 0x26, 0x62, 0xb1, 0xc3, 0x82, 0xc3, 0xc1, 0xec, 0xe4, 0xd6, 0x3f, 0x57, 0x41, 0xfb, 0xbc, 0x00,
- 0xa4, 0x49, 0xf5, 0xd1, 0x16, 0x3a, 0x2b, 0x7c, 0x67, 0x52, 0x7a, 0x03, 0xa7, 0xf3, 0xb2, 0xa1,
- 0x31, 0x18, 0x67, 0x41, 0x26, 0x59, 0x26, 0xc9, 0x1f, 0x94, 0x37, 0x72, 0xfd, 0xf8, 0x75, 0xae,
- 0x63, 0xe2, 0x6b, 0xb0, 0x33, 0x6d, 0x14, 0x15, 0xf3, 0x63, 0xc4, 0xe0, 0x10, 0x77, 0xf8, 0xc8,
- 0x3b, 0xc2, 0xd5, 0x5a, 0x8a, 0x6f, 0xea, 0x2a, 0xa2, 0xa0, 0xcf, 0x2f, 0xd2, 0xaf, 0x03, 0x51,
- 0x97, 0x31, 0x55, 0x75, 0x4e, 0xa3, 0xa5, 0xe7, 0x2b, 0xb9, 0x1f, 0x31, 0x23, 0x78, 0x7f, 0xff,
- 0x63, 0x63, 0x77, 0x5b, 0x28, 0x2d, 0xe1, 0x12, 0x6a, 0xe7, 0xf3, 0xca, 0xd0, 0x20, 0x18, 0x86,
- 0x9e, 0x1b, 0xbc, 0xb4, 0x0e, 0x94, 0xbb, 0x64, 0xf3, 0x38, 0x70, 0x55, 0x6b, 0xf4, 0x5f, 0xfb,
- 0x1c, 0x66, 0x4c, 0xb1, 0xe4, 0x7c, 0xea, 0x26, 0x39, 0x24, 0xe6, 0xda, 0x1f, 0x7e, 0x7f, 0x13,
- 0x18, 0xf1, 0x8b, 0x5d, 0x53, 0xd3, 0xc1, 0xf9, 0xe9, 0x7c, 0x4d, 0x62, 0xeb, 0x21, 0x63, 0x90,
- 0xe0, 0x5b, 0x14, 0x63, 0xed, 0xa6, 0xfc, 0x69, 0xd4, 0x29, 0x03, 0xb8, 0xfd, 0x14, 0x30, 0xd3,
- 0x45, 0x18, 0x40, 0x58, 0xb5, 0x93, 0xe7, 0x5e, 0x97, 0xcf, 0x77, 0x7a, 0x14, 0x5a, 0x9c, 0x92,
- 0xb5, 0xe0, 0x63, 0xa0, 0x89, 0x41, 0xf2, 0xfe, 0xe2, 0x96, 0x7e, 0x63, 0x70, 0xec, 0x72, 0x91,
- 0x57, 0x6b, 0xe1, 0x3e, 0x44, 0x87, 0xdd, 0x42, 0xd2, 0x41, 0x4e, 0x9e, 0x6d, 0x6f, 0x75, 0x87,
- 0xca, 0x35, 0xab, 0x46, 0xe3, 0xa4, 0x69, 0x55, 0x92, 0x60, 0x66, 0x26, 0x33, 0x66, 0xbd, 0x52,
- 0x64, 0x44, 0xcf, 0x67, 0x12, 0xaa, 0x65, 0x90, 0x39, 0xe6, 0x3b, 0x7d, 0xdf, 0x77, 0xb3, 0xaa,
- 0x4b, 0x31, 0x0f, 0x90, 0x76, 0x55, 0x7b, 0xd0, 0xfc, 0x6c, 0x44, 0x96, 0xd7, 0xf1, 0xd0, 0x4e,
- 0xa3, 0x6c, 0xf4, 0xf5, 0xdd, 0xa9, 0xb2, 0x79, 0x32, 0x9a, 0xc7, 0x71, 0xac, 0xd1, 0x88, 0x91,
- 0x11, 0x1b, 0x87, 0x08, 0x46, 0xca, 0x53, 0xed, 0x3c, 0x06, 0xed, 0x5f, 0xd7, 0xd5, 0xe9, 0x5b,
- 0xdb, 0xb9, 0xfa, 0xc1, 0x90, 0x2a, 0xb2, 0x75, 0xbb, 0xb4, 0xd3, 0xf7, 0xa2, 0xd7, 0x28, 0xbe,
- 0x5d, 0xa6, 0x1d, 0x02, 0x33, 0x6b, 0x43, 0x82, 0x08, 0x49, 0xe0, 0x62, 0x1c, 0x9d, 0x54, 0x1b,
- 0x6b, 0xa9, 0x75, 0xe5, 0xf8, 0x17, 0xf4, 0x0f, 0x1f, 0x8b, 0x5d, 0x02, 0x6c, 0xca, 0x2a, 0x99,
- 0x88, 0xa7, 0xcf, 0x05, 0xe9, 0x40, 0xe6, 0x46, 0xa5, 0xf6, 0x8a, 0x1c, 0x84, 0x1f, 0x2a, 0x17,
- 0x01, 0xc8, 0xd0, 0x9d, 0x9f, 0xd2, 0x41, 0x91, 0xe6, 0xdb, 0xd2, 0xc0, 0x9c, 0xf3, 0x27, 0xe1,
- 0x45, 0x75, 0x7d, 0x31, 0x25, 0x14, 0x8c, 0xc5, 0xb0, 0x76, 0x35, 0xa3, 0x93, 0xf4, 0xcc, 0xd8,
- 0xa1, 0x1e, 0x10, 0x5c, 0x17, 0x9d, 0x7d, 0xc1, 0x37, 0xb7, 0xa1, 0xd7, 0xbf, 0x3a, 0x58, 0x7e,
- 0x30, 0x3b, 0x24, 0xbd, 0x4d, 0xa7, 0x96, 0xa7, 0x5a, 0x48, 0xc6, 0x91, 0x7b, 0x03, 0x05, 0xf1,
- 0xa8, 0xd8, 0x1b, 0xd4, 0xf1, 0x3d, 0xc0, 0x02, 0x2d, 0xc8, 0xec, 0x74, 0x18, 0xc9, 0x77, 0xd0,
- 0x18, 0x2f, 0xba, 0x2e, 0x1b, 0x5b, 0xe8, 0x68, 0x7b, 0xec, 0xe7, 0xde, 0x59, 0xe0, 0x10, 0x9e,
- 0x9d, 0xd8, 0x7e, 0x41, 0x6d, 0xc3, 0x23, 0x21, 0x84, 0xa5, 0x90, 0xb9, 0x35, 0x69, 0x43, 0x0c,
- 0x03, 0xc2, 0x82, 0x52, 0xbe, 0x69, 0x2f, 0x25, 0x4c, 0x8b, 0x1b, 0x6f, 0xe9, 0xf4, 0x51, 0xce,
- 0xe7, 0xe4, 0x96, 0x57, 0x6b, 0x51, 0x6c, 0x2f, 0x1e, 0xd5, 0x4d, 0xea, 0xdf, 0xbf, 0x06, 0x12,
- 0x84, 0x9d, 0xe5, 0x7e, 0x98, 0x49, 0xff, 0xa5, 0x1b, 0x3c, 0x72, 0x30, 0xac, 0xe3, 0xf4, 0xba,
- 0xe4, 0x07, 0x59, 0xba, 0x57, 0x41, 0x21, 0x5f, 0xc2, 0x4d, 0x2c, 0x3f, 0xcf, 0x74, 0xdf, 0xc9,
- 0xf4, 0x50, 0x0a, 0x20, 0x24, 0x56, 0xec, 0xec, 0xd3, 0xfd, 0x3c, 0xdb, 0x46, 0x86, 0x4d, 0x0b,
- 0x8c, 0xc0, 0xe0, 0x67, 0x4c, 0x78, 0x25, 0x9a, 0xc8, 0xfc, 0x77, 0xa8, 0xf4, 0xf8, 0x43, 0x87,
- 0xdc, 0x66, 0xbd, 0x34, 0x26, 0x06, 0xc8, 0x5d, 0x66, 0x63, 0x80, 0x45, 0x09, 0x8f, 0x57, 0xfd,
- 0xd9, 0x80, 0x67, 0x8e, 0x62, 0xf1, 0x70, 0xee, 0x7e, 0x43, 0xd5, 0x3d, 0x11, 0x35, 0x5b, 0xf9,
- 0xb9, 0xb7, 0x56, 0x4c, 0x9c, 0x59, 0x71, 0x80, 0xfb, 0x35, 0xcb, 0x58, 0xb3, 0xdb, 0x0c, 0xf3,
- 0x29, 0xe6, 0x38, 0x93, 0x72, 0xef, 0x19, 0x24, 0x71, 0xa4, 0x7e, 0xc2, 0x0f, 0xa7, 0x88, 0x60,
- 0xa7, 0x0e, 0x65, 0x7f, 0xd7, 0x60, 0x30, 0x7a, 0xe8, 0xf0, 0x37, 0xee, 0x68, 0x87, 0x31, 0xc8,
- 0x32, 0xe4, 0xa1, 0x71, 0xd2, 0xdb, 0x86, 0x9b, 0xe2, 0xf5, 0x63, 0xe6, 0x70, 0x79, 0x79, 0xa6,
- 0x79, 0xab, 0x44, 0xdc, 0xe5, 0xe7, 0xe2, 0x95, 0x9a, 0x07, 0x50, 0x4a, 0xc9, 0x95, 0xa7, 0x39,
- 0x8b, 0xcb, 0xb7, 0xa2, 0xf1, 0xc5, 0x37, 0x96, 0x58, 0x29, 0xd7, 0x05, 0x9b, 0xf7, 0x39, 0x9c,
- 0xef, 0xbb, 0x0d, 0xde, 0xb7, 0xb1, 0xab, 0xa1, 0x31, 0xc2, 0xe1, 0x01, 0xfb, 0x76, 0xfe, 0x2a,
- 0x61, 0x35, 0x8f, 0x50, 0x93, 0x48, 0xbb, 0x44, 0xb0, 0xfc, 0x78, 0xd7, 0xef, 0x34, 0x98, 0x49,
- 0xbb, 0x96, 0x59, 0x25, 0x37, 0x26, 0x04, 0x86, 0x97, 0x0c, 0x0f, 0xd4, 0x20, 0xb1, 0x80, 0x23,
- 0xd2, 0x33, 0x98, 0xad, 0x1d, 0xb5, 0xc4, 0x7d, 0x74, 0x69, 0xa8, 0x73, 0xba, 0xb5, 0x71, 0xfe,
- 0xd9, 0x5c, 0xfe, 0xd2, 0x4b, 0x6a, 0xa9, 0x0d, 0xfc, 0x19, 0x2f, 0x7c, 0x6e, 0x73, 0xab, 0xa9,
- 0xbb, 0x1e, 0xe4, 0x50, 0xc0, 0x58, 0xab, 0xef, 0xf6, 0xe8, 0x48, 0x04, 0x8a, 0x97, 0xbb, 0x0d,
- 0x8c, 0x10, 0x9c, 0x68, 0xed, 0xe7, 0x18, 0x8b, 0xcd, 0x6d, 0xcb, 0x14, 0x5b, 0xba, 0x08, 0x61,
- 0x0d, 0xbb, 0x4a, 0xe1, 0x13, 0x67, 0xca, 0x68, 0x4d, 0x36, 0x69, 0xe3, 0xab, 0x01, 0x00, 0x97,
- 0x1e, 0x7e, 0xb0, 0x09, 0x24, 0x13, 0xf2, 0xce, 0xda, 0x34, 0xdf, 0x91, 0x60, 0x2b, 0xdc, 0x58,
- 0xe2, 0xf1, 0x39, 0xe0, 0x6c, 0x7d, 0x38, 0xd0, 0x6a, 0xeb, 0xa7, 0xb1, 0x6e, 0xa6, 0x2a, 0x62,
- 0x25, 0x41, 0xb3, 0x30, 0x96, 0x34, 0xb0, 0x46, 0x0d, 0x37, 0x4c, 0x28, 0x66, 0x49, 0x5a, 0x5e,
- 0x86, 0x3b, 0x3d, 0x02, 0xa3, 0x4a, 0x08, 0xd8, 0xb1, 0xdd, 0x64, 0x61, 0xaa, 0xb9, 0x41, 0xdb,
- 0x60, 0xe7, 0xc1, 0x40, 0x90, 0xe1, 0xce, 0x48, 0x5a, 0x13, 0x58, 0xd2, 0x55, 0x07, 0x08, 0xa4,
- 0xeb, 0x7c, 0x43, 0x17, 0x31, 0x5c, 0xb2, 0x28, 0x76, 0x37, 0x81, 0x50, 0x94, 0xf8, 0xa3, 0x3a,
- 0x0f, 0xe1, 0x36, 0x01, 0x68, 0xe5, 0x0d, 0x27, 0x88, 0xeb, 0xec, 0x56, 0x69, 0x31, 0xd7, 0x18,
- 0xb9, 0x02, 0x95, 0xb0, 0xe9, 0xca, 0x32, 0x69, 0xd1, 0x27, 0x3a, 0x9b, 0x07, 0xdc, 0x2f, 0xc4,
- 0x70, 0x68, 0x5d, 0xbd, 0x11, 0x83, 0x4c, 0x71, 0x1a, 0x5d, 0x0a, 0xde, 0xc2, 0x14, 0x52, 0xc6,
- 0x7a, 0xa5, 0x73, 0x3e, 0x78, 0x16, 0xaa, 0x76, 0x77, 0xeb, 0x99, 0x13, 0xfe, 0x9b, 0x2b, 0x7b,
- 0x4d, 0x86, 0xc7, 0x1e, 0x4e, 0x05, 0x10, 0x6a, 0xc9, 0x29, 0xb0, 0xa9, 0xbe, 0x20, 0x01, 0x87,
- 0x21, 0x70, 0xf8, 0xe1, 0x69, 0xe9, 0xd0, 0x96, 0x4f, 0x03, 0xd3, 0x76, 0xa8, 0x0b, 0x71, 0x6d,
- 0x9b, 0x5e, 0x9f, 0xd0, 0x50, 0x19, 0x8a, 0x39, 0x71, 0x78, 0xab, 0x7f, 0xbf, 0x3d, 0xae, 0x8a,
- 0xb7, 0xfe, 0xe8, 0x38, 0x53, 0xab, 0xfb, 0x2f, 0x04, 0xc5, 0x2e, 0x72, 0xde, 0x74, 0x7f, 0x01,
- 0x50, 0x01, 0xf9, 0x8f, 0x8b, 0x34, 0x41, 0xe6, 0x6f, 0x9f, 0x98, 0xa4, 0xb1, 0x7d, 0x2e, 0x78,
- 0xbc, 0x8e, 0xce, 0x8f, 0xe2, 0x28, 0xbd, 0x24, 0x8b, 0x3e, 0x6b, 0x9c, 0xad, 0x16, 0x85, 0x48,
- 0x34, 0x52, 0xeb, 0x5e, 0x32, 0x79, 0x42, 0xaa, 0x97, 0xd8, 0x32, 0x46, 0x38, 0x22, 0x69, 0x81,
- 0x11, 0xdc, 0xf3, 0x65, 0x03, 0xa7, 0x98, 0xdf, 0xd3, 0x1b, 0xfd, 0x89, 0x45, 0x89, 0x60, 0xb4,
- 0x53, 0xd4, 0xb8, 0xec, 0xae, 0x33, 0x41, 0x56, 0x62, 0x57, 0x7c, 0x55, 0x2f, 0x2b, 0x31, 0x20,
- 0xef, 0xc1, 0x23, 0x55, 0x01, 0xc5, 0xf3, 0x99, 0x41, 0x05, 0xc1, 0x12, 0x02, 0x02, 0x27, 0xcb,
- 0x63, 0x41, 0x5f, 0x66, 0x3c, 0xce, 0x2a, 0x1f, 0xe8, 0xc4, 0x82, 0x8e, 0xf7, 0x06, 0xa8, 0x17,
- 0xc6, 0xf7, 0x13, 0xca, 0xf0, 0x10, 0x92, 0xec, 0xa9, 0xf3, 0x74, 0x9d, 0xf7, 0xdb, 0x71, 0xb5,
- 0x51, 0x9d, 0xe0, 0xfd, 0x76, 0x90, 0x3f, 0x05, 0x22, 0xf4, 0xf2, 0x21, 0x81, 0x75, 0xdb, 0x5c,
- 0x2b, 0xd1, 0x08, 0xbe, 0x9c, 0x5b, 0x7b, 0x28, 0xc5, 0xf9, 0xe9, 0xb2, 0xd2, 0x12, 0xaa, 0x74,
- 0xad, 0xde, 0xfb, 0xbe, 0xc0, 0x1c, 0x96, 0xce, 0x7d, 0xef, 0xf4, 0xf8, 0x5f, 0xf6, 0x75, 0xa9,
- 0x2f, 0x5d, 0xa4, 0x7d, 0xb0, 0xb3, 0xbc, 0x95, 0x23, 0xd4, 0x19, 0xfd, 0x00, 0xed, 0xf7, 0x05,
- 0x0a, 0x66, 0x36, 0x58, 0x0f, 0x83, 0xdb, 0x9e, 0x33, 0x35, 0x52, 0x7d, 0x7f, 0xe5, 0xa9, 0x76,
- 0xe2, 0x6b, 0x67, 0x41, 0xf9, 0x1f, 0x37, 0x8e, 0xd2, 0x16, 0x08, 0x64, 0x3f, 0xff, 0xd5, 0x09,
- 0x21, 0xa9, 0xf5, 0xcc, 0xd6, 0x33, 0x97, 0x17, 0xfd, 0x01, 0x2b, 0xf8, 0xf6, 0xe7, 0xd6, 0xfd,
- 0xa6, 0xcc, 0x7a, 0xcc, 0xac, 0x69, 0x6e, 0x03, 0x02, 0x32, 0xd1, 0x24, 0xfa, 0x6e, 0xd5, 0xbc,
- 0x0b, 0x38, 0x9b, 0x46, 0xdc, 0x88, 0x84, 0x55, 0x5c, 0x44, 0x4d, 0x87, 0xac, 0xb4, 0xc4, 0x23,
- 0xda, 0x69, 0x74, 0x85, 0xb6, 0xca, 0xce, 0xec, 0x0a, 0x0e, 0x74, 0x2d, 0xff, 0x87, 0x6f, 0xa6,
- 0xf3, 0xc2, 0xcb, 0x64, 0x5e, 0x5c, 0x4f, 0xde, 0xb0, 0x2b, 0xb7, 0x16, 0x0f, 0x4c, 0xea, 0x5f,
- 0x45, 0x6f, 0x50, 0x9c, 0xc8, 0x3c, 0x4e, 0xb4, 0x0a, 0xb2, 0xbb, 0xf7, 0xf4, 0xa3, 0x28, 0x72,
- 0xe3, 0x0b, 0xed, 0x4e, 0x9d, 0x06, 0x95, 0xbd, 0xc5, 0x14, 0x29, 0x0a, 0x34, 0x97, 0xdb, 0x2e,
- 0xa7, 0x85, 0xcd, 0xa5, 0x95, 0xdc, 0x05, 0x0d, 0xea, 0xaa, 0x2f, 0x25, 0x48, 0xca, 0x69, 0xa4,
- 0xaa, 0xec, 0x34, 0xae, 0x68, 0x1a, 0x93, 0x2f, 0x84, 0x96, 0xa8, 0x50, 0x48, 0x89, 0x44, 0x62,
- 0xa9, 0xcf, 0x20, 0x8d, 0xfa, 0x38, 0x41, 0x56, 0xf4, 0xb8, 0x86, 0xce, 0x15, 0xcc, 0x25, 0xfb,
- 0xe1, 0xa2, 0x1a, 0x4b, 0x49, 0x80, 0x64, 0x37, 0x60, 0x3c, 0xb3, 0x67, 0xee, 0x48, 0xf0, 0xfd,
- 0x0e, 0x92, 0x57, 0x68, 0xf4, 0xf1, 0x57, 0x9c, 0x73, 0x9c, 0xe7, 0xc8, 0x1d, 0xa0, 0x10, 0xf4,
- 0x0d, 0x38, 0x06, 0x41, 0x7a, 0x60, 0x6e, 0x37, 0xc5, 0x50, 0x62, 0xbe, 0x4e, 0x59, 0x3a, 0xba,
- 0x70, 0x43, 0xc5, 0x51, 0xec, 0x7b, 0xb5, 0xa2, 0xb8, 0x88, 0x4d, 0xb2, 0xf7, 0x11, 0xe0, 0xa3,
- 0x04, 0xd0, 0xe7, 0x0b, 0x37, 0xa4, 0xf3, 0xa1, 0xb1, 0x15, 0xa0, 0x1f, 0x03, 0x8f, 0xeb, 0xa2,
- 0x50, 0x58, 0x93, 0x49, 0xa8, 0x0b, 0x20, 0x23, 0x3c, 0x3f, 0xd7, 0xc3, 0xf1, 0xac, 0x40, 0x46,
- 0x9e, 0xf6, 0xa7, 0x34, 0x22, 0xd8, 0x39, 0x2e, 0x7b, 0xb2, 0x1d, 0x81, 0x36, 0x63, 0x4b, 0x37,
- 0x5d, 0x22, 0x6a, 0x74, 0x21, 0x7a, 0x9a, 0xc9, 0x96, 0x2d, 0xaa, 0x6a, 0xa3, 0x42, 0x23, 0x63,
- 0xfc, 0xe1, 0x2c, 0xba, 0x79, 0x9c, 0x9f, 0xf6, 0x07, 0x04, 0xdd, 0xcc, 0xed, 0xf5, 0x21, 0x54,
- 0xf9, 0xf4, 0x4d, 0xb6, 0xe7, 0x78, 0xd5, 0x0a, 0xc7, 0x16, 0x93, 0x00, 0x7b, 0x30, 0xc9, 0x33,
- 0xa6, 0x39, 0xa8, 0x07, 0x32, 0xeb, 0xf9, 0x3c, 0x6a, 0xee, 0x85, 0xbe, 0x6e, 0x27, 0xd2, 0x15,
- 0xa0, 0xbd, 0x14, 0xac, 0x7a, 0x14, 0xf6, 0xea, 0xcd, 0xda, 0xdd, 0x75, 0xf2, 0x66, 0xbf, 0xef,
- 0x56, 0x06, 0x09, 0xbc, 0xab, 0x64, 0x6b, 0xf6, 0x7e, 0x14, 0x9f, 0x84, 0x4d, 0x63, 0xd3, 0xc9,
- 0x85, 0x94, 0x44, 0x84, 0xeb, 0xae, 0x5f, 0xd2, 0xba, 0xfa, 0xd7, 0xf5, 0x60, 0x17, 0x84, 0xd9,
- 0x15, 0xc8, 0x54, 0x6c, 0x57, 0x69, 0x82, 0xc1, 0xe7, 0xd8, 0xfa, 0xcd, 0x67, 0x2a, 0x3c, 0xbe,
- 0x5d, 0xd4, 0x4a, 0xfd, 0xa6, 0x0a, 0xa6, 0x8a, 0xfa, 0xbb, 0x2e, 0x3b, 0x05, 0xaa, 0xc2, 0xd9,
- 0x9a, 0x54, 0x7a, 0xc0, 0x27, 0x15, 0x97, 0xda, 0x59, 0xd7, 0x24, 0x08, 0x6a, 0x92, 0xd4, 0xee,
- 0x31, 0xf2, 0x6c, 0x1f, 0x19, 0xe6, 0x9d, 0x3e, 0xab, 0xa6, 0x47, 0xb3, 0xab, 0x66, 0x81, 0xa3,
- 0x2a, 0xda, 0x66, 0xf4, 0x4e, 0x54, 0xe5, 0xcc, 0x58, 0x8c, 0x56, 0x74, 0xc3, 0xb4, 0x96, 0x43,
- 0x9f, 0x3d, 0x2a, 0x73, 0x97, 0xcb, 0x75, 0xf1, 0x54, 0x75, 0x0b, 0x7a, 0xce, 0x12, 0xb2, 0x3f,
- 0x22, 0xfe, 0xc3, 0x99, 0x14, 0xd4, 0x8b, 0x52, 0x8d, 0xc2, 0x33, 0xe2, 0xfb, 0x28, 0xfd, 0xc0,
- 0xec, 0x55, 0x88, 0x09, 0xd8, 0x3a, 0x70, 0xf4, 0x13, 0x46, 0xe6, 0x39, 0x65, 0x25, 0x19, 0xbb,
- 0x2a, 0xc4, 0x9e, 0x79, 0x11, 0xac, 0x58, 0xd3, 0x43, 0x12, 0x2b, 0x58, 0xe6, 0xad, 0x70, 0x6f,
- 0x03, 0xfc, 0xf2, 0xd0, 0x13, 0x69, 0xd6, 0xe2, 0x97, 0x49, 0xbd, 0xe9, 0x76, 0x3d, 0x5e, 0xd7,
- 0xf1, 0xae, 0x3a, 0xab, 0xa3, 0xa9, 0xbe, 0x25, 0x4f, 0xdd, 0xf3, 0xdd, 0x85, 0xd8, 0xad, 0x3c,
- 0x86, 0xe2, 0x32, 0x1d, 0xd9, 0x42, 0x04, 0x66, 0x48, 0x90, 0xfb, 0x69, 0x3d, 0x84, 0x03, 0xa0,
- 0xc2, 0x1d, 0x35, 0xcb, 0xd9, 0xf3, 0xc7, 0xa6, 0x4a, 0x49, 0x68, 0x5e, 0x6e, 0xa6, 0x09, 0x89,
- 0xa6, 0x3f, 0xb5, 0xc4, 0x15, 0x9a, 0xb5, 0x9b, 0xa8, 0x7c, 0xe8, 0x23, 0x8e, 0x1c, 0x9a, 0xaa,
- 0xf5, 0x2b, 0xf2, 0xfa, 0x74, 0x54, 0x8d, 0xe7, 0xfa, 0x23, 0x70, 0x31, 0x0e, 0x42, 0xfc, 0xad,
- 0x55, 0x68, 0x97, 0x79, 0xf0, 0xf4, 0xa7, 0xed, 0x91, 0x78, 0xac, 0xe6, 0x84, 0x55, 0xf8, 0x27,
- 0x22, 0x3d, 0xcb, 0x44, 0xb7, 0x44, 0xe9, 0xa8, 0xe4, 0x68, 0xc2, 0xa1, 0xbd, 0x8d, 0xec, 0x48,
- 0xa1, 0x07, 0x23, 0x66, 0xbd, 0x2b, 0x4b, 0x32, 0x49, 0xb2, 0x61, 0x84, 0x6b, 0xb3, 0x46, 0xbf,
- 0xbb, 0x5d, 0x21, 0xe0, 0x84, 0x1c, 0x43, 0x35, 0xb9, 0x45, 0x58, 0x24, 0xa0, 0x83, 0xac, 0xb8,
- 0x9d, 0xa3, 0x1d, 0xa4, 0xd5, 0x2c, 0x67, 0x2a, 0x6a, 0x44, 0x57, 0xc4, 0x12, 0x64, 0x5f, 0xb2,
- 0xa6, 0xa9, 0x53, 0x24, 0xa0, 0x19, 0x37, 0x08, 0x33, 0x1e, 0x91, 0x5f, 0x8f, 0x44, 0x55, 0xf2,
- 0xb8, 0x0b, 0x39, 0xac, 0x26, 0x4a, 0x4e, 0x8d, 0xbc, 0xbf, 0x59, 0x85, 0xa9, 0x5e, 0x04, 0x4f,
- 0x30, 0x48, 0x7f, 0xac, 0x37, 0x1b, 0x44, 0x2b, 0xac, 0x48, 0xc1, 0x07, 0xec, 0xc8, 0x9d, 0xc6,
- 0x59, 0x6f, 0x4b, 0xa2, 0x56, 0x0a, 0xba, 0x77, 0xbe, 0x84, 0xba, 0x63, 0x43, 0xb4, 0xd9, 0xa7,
- 0xa8, 0xaf, 0x17, 0xc9, 0x3e, 0xa1, 0xfc, 0xc9, 0xf1, 0x86, 0x85, 0x25, 0x0e, 0x81, 0x1c, 0x25,
- 0x1a, 0x6d, 0x36, 0x89, 0x7e, 0xe8, 0x63, 0x46, 0x55, 0x3a, 0x99, 0x50, 0xa6, 0xbf, 0xef, 0x72,
- 0x5f, 0xb6, 0x48, 0x7d, 0x5e, 0x40, 0x7f, 0x21, 0x81, 0xbc, 0x0d, 0x0b, 0xad, 0x57, 0xdc, 0x4d,
- 0xbe, 0x7c, 0x7d, 0x54, 0x18, 0x34, 0xf3, 0x40, 0xc2, 0xc9, 0x93, 0xf1, 0x50, 0x23, 0xcd, 0x18,
- 0x68, 0xf0, 0xad, 0x52, 0x9d, 0x90, 0x07, 0x8d, 0x5f, 0x60, 0xca, 0xb2, 0xb6, 0x35, 0x3a, 0xe5,
- 0xe7, 0x80, 0x44, 0xd3, 0x62, 0x12, 0x25, 0x0d, 0x0c, 0xc5, 0x8c, 0x39, 0x3e, 0x59, 0x1c, 0x70,
- 0x76, 0x99, 0x8a, 0x29, 0x4b, 0xbe, 0x09, 0x58, 0x19, 0x99, 0xaa, 0x7f, 0x78, 0x2b, 0xc8, 0x55,
- 0x9e, 0xd6, 0xef, 0x18, 0xb9, 0xd7, 0xd2, 0x47, 0x8c, 0xdd, 0xbd, 0x80, 0xed, 0x9b, 0x79, 0x80,
- 0x46, 0x35, 0x1c, 0xbb, 0x4b, 0xbd, 0x14, 0x6f, 0x68, 0x87, 0x26, 0x34, 0xf6, 0x76, 0x3f, 0x47,
- 0x67, 0xa1, 0x19, 0x4e, 0x46, 0x91, 0xc0, 0x37, 0xa3, 0xd3, 0x4d, 0xdd, 0x54, 0xd4, 0x5a, 0x2b,
- 0x7d, 0xad, 0x42, 0x0d, 0x35, 0x9a, 0xca, 0xd9, 0x61, 0x9a, 0xf4, 0x52, 0x51, 0x94, 0x4b, 0xa2,
- 0x08, 0xde, 0xa8, 0x4b, 0xe9, 0xe6, 0x7f, 0x93, 0xa0, 0x7c, 0x7b, 0x39, 0x59, 0xc8, 0xc2, 0xa3,
- 0xc7, 0x46, 0xf0, 0x99, 0xdb, 0x62, 0x57, 0x01, 0x91, 0x20, 0xe6, 0x8d, 0x14, 0xc1, 0x13, 0xfd,
- 0xd1, 0x5d, 0x84, 0xb7, 0xf5, 0xd3, 0x56, 0x49, 0x6d, 0x32, 0x24, 0x1a, 0x4e, 0xbd, 0x19, 0xb0,
- 0x90, 0x12, 0x32, 0x2f, 0x89, 0x72, 0x66, 0xc3, 0x2a, 0x18, 0x44, 0xea, 0x6e, 0x6c, 0x28, 0x20,
- 0x8e, 0x59, 0x93, 0xc2, 0x9b, 0x94, 0xea, 0x6f, 0x85, 0x32, 0xff, 0x4a, 0xce, 0xd6, 0x20, 0x8d,
- 0x43, 0x24, 0x8c, 0xf1, 0x48, 0xec, 0x63, 0x95, 0xd3, 0x26, 0xb5, 0xc0, 0xc4, 0xe9, 0xdc, 0x95,
- 0x66, 0xef, 0xd8, 0xf3, 0x82, 0x1c, 0xf0, 0x5b, 0xb5, 0xf0, 0xd9, 0x8e, 0x8b, 0x62, 0xd8, 0x81,
- 0xd1, 0xd6, 0x17, 0xca, 0x22, 0x79, 0x11, 0xcd, 0x09, 0x1d, 0x66, 0x80, 0xdf, 0xe4, 0xc3, 0x17,
- 0x30, 0x27, 0x15, 0x7a, 0x22, 0x42, 0xa2, 0x21, 0x24, 0x6f, 0x63, 0xb3, 0xb1, 0x18, 0x03, 0x30,
- 0xb1, 0x5e, 0x9d, 0x79, 0xeb, 0xaf, 0x24, 0x3c, 0xc7, 0xaf, 0x3b, 0x5b, 0xac, 0xf1, 0xdf, 0x9f,
- 0x3d, 0xfa, 0x52, 0xae, 0x91, 0x0b, 0xe0, 0x2e, 0x93, 0x6f, 0x6b, 0xac, 0x5b, 0xe3, 0x3c, 0x0d,
- 0x2a, 0x95, 0x89, 0x12, 0xa5, 0x6b, 0xb7, 0xdc, 0xc7, 0x22, 0xac, 0xce, 0xe9, 0xf6, 0x08, 0xe9,
- 0x16, 0xcf, 0x03, 0x4a, 0xdb, 0x43, 0x47, 0x82, 0x4e, 0x55, 0x46, 0x20, 0x4b, 0xeb, 0xc4, 0xd6,
- 0x0e, 0xc1, 0xff, 0xb7, 0x40, 0x4d, 0xfb, 0x49, 0xc0, 0xbb, 0xdb, 0x4e, 0xa3, 0x64, 0x36, 0x7c,
- 0x69, 0xe6, 0xf4, 0x1b, 0xad, 0x4f, 0xa5, 0xcf, 0x68, 0xd2, 0xbc, 0x71, 0x18, 0xad, 0xbc, 0x35,
- 0xab, 0x4e, 0xd2, 0xcd, 0x26, 0xe8, 0x27, 0x82, 0xc5, 0x37, 0xeb, 0x90, 0xa1, 0x4d, 0x2a, 0xf7,
- 0xf5, 0x40, 0xf9, 0x28, 0xc8, 0x96, 0x9b, 0xa4, 0xff, 0x4f, 0x6f, 0x1e, 0x6b, 0x51, 0xa5, 0xc1,
- 0xe1, 0x11, 0xba, 0x00, 0xa8, 0x63, 0xc6, 0xd1, 0xaa, 0x97, 0x61, 0x6d, 0xb2, 0xf1, 0x2f, 0x9b,
- 0x90, 0x32, 0xd8, 0x6b, 0xba, 0x00, 0xa7, 0xcb, 0xe1, 0xcd, 0xb7, 0xb8, 0x80, 0x5b, 0x60, 0x9a,
- 0x04, 0xb1, 0x59, 0x00, 0x1f, 0x45, 0xc7, 0x2a, 0x08, 0xcb, 0xc1, 0xee, 0x0d, 0xb4, 0x71, 0xdf,
- 0x7a, 0xdc, 0xa6, 0xbb, 0xfe, 0xa0, 0x4d, 0x49, 0xbb, 0x2c, 0x13, 0x25, 0x2e, 0x9f, 0x55, 0xaa,
- 0x73, 0x16, 0x39, 0xd5, 0x83, 0x35, 0x2f, 0xb4, 0xef, 0x69, 0x9e, 0x3e, 0x4c, 0x67, 0x00, 0x05,
- 0x59, 0xc3, 0x38, 0x77, 0x1e, 0x9d, 0x93, 0xfa, 0x3f, 0x49, 0x9f, 0x58, 0x1d, 0xa3, 0x05, 0xec,
- 0xd7, 0x51, 0x30, 0xe1, 0x34, 0x83, 0xb3, 0xd1, 0x54, 0x84, 0x63, 0xd6, 0xb7, 0x0c, 0x61, 0xa5,
- 0x36, 0x12, 0xf8, 0x6d, 0xc6, 0xb8, 0xdc, 0x5d, 0x97, 0x9a, 0x7a, 0x81, 0xaa, 0x39, 0xfa, 0xef,
- 0x46, 0x82, 0x7c, 0xc0, 0x5b, 0xbe, 0x66, 0xd9, 0x06, 0xe5, 0xe1, 0x91, 0xdb, 0xa6, 0x33, 0x80,
- 0x69, 0x8c, 0xcd, 0x9d, 0x52, 0x59, 0x95, 0x06, 0xa5, 0x26, 0x62, 0x38, 0xa0, 0x20, 0x6b, 0x98,
- 0x14, 0xed, 0xf2, 0xda, 0x70, 0x10, 0x6c, 0x79, 0x6b, 0x4c, 0x18, 0xa4, 0x72, 0x08, 0x27, 0x8b,
- 0x42, 0x27, 0x4f, 0x0a, 0x0c, 0xf1, 0xe6, 0x5d, 0x0b, 0xda, 0x6c, 0x2c, 0x18, 0x91, 0xbe, 0x62,
- 0xfe, 0x2f, 0xee, 0xdf, 0x12, 0xcb, 0x16, 0xcc, 0x73, 0x4a, 0x13, 0xe9, 0x31, 0x3b, 0xbe, 0x68,
- 0x2d, 0x1c, 0xa0, 0xfc, 0x70, 0x11, 0x45, 0xcd, 0x47, 0x6c, 0x3e, 0x6f, 0xdc, 0xc6, 0xa3, 0x25,
- 0x0e, 0xa5, 0xff, 0xff, 0x3d, 0x55, 0x04, 0xbc, 0xfe, 0x60, 0x3d, 0xbd, 0x31, 0x95, 0xa5, 0x02,
- 0xdc, 0x42, 0x26, 0x15, 0x6f, 0x33, 0x77, 0x67, 0xb2, 0x36, 0x46, 0x1d, 0x1c, 0x3e, 0x2b, 0x80,
- 0x59, 0xac, 0x12, 0xa8, 0x0f, 0x64, 0xb3, 0xa9, 0x8b, 0x58, 0xef, 0x27, 0x43, 0xcc, 0x99, 0x7e,
- 0x38, 0x61, 0xcb, 0x47, 0xbe, 0x1f, 0x00, 0xe5, 0x2a, 0xb2, 0x1b, 0x56, 0x56, 0x7c, 0xfe, 0xcb,
- 0x0a, 0x89, 0xf6, 0xfc, 0x83, 0xe8, 0x82, 0xf2, 0xbe, 0xc8, 0xca, 0x32, 0xf0, 0x9c, 0x7a, 0x84,
- 0x4f, 0xef, 0xc0, 0xdf, 0x99, 0xf5, 0x7b, 0x51, 0xd6, 0x4f, 0x9d, 0xac, 0xb0, 0x28, 0x6b, 0x0c,
- 0x47, 0x12, 0xc0, 0xf8, 0x79, 0xec, 0x6f, 0x7a, 0x7c, 0xa6, 0x37, 0xd2, 0xe2, 0x8a, 0x74, 0x45,
- 0x5a, 0x49, 0x7b, 0xb2, 0x74, 0x96, 0xb4, 0x9f, 0xeb, 0x3d, 0x45, 0x8e, 0x4d, 0x7e, 0x67, 0x97,
- 0x06, 0x9a, 0x8c, 0xac, 0x43, 0x55, 0xa1, 0x9a, 0x60, 0xb9, 0xa1, 0x79, 0xcd, 0xa2, 0xef, 0x72,
- 0x45, 0xe3, 0x79, 0xab, 0x6f, 0x7a, 0xa1, 0x9e, 0x11, 0x88, 0x14, 0xe8, 0xce, 0xd1, 0xce, 0x52,
- 0x5c, 0x4d, 0xa6, 0xf8, 0x78, 0x71, 0x26, 0xb0, 0x56, 0xcf, 0xdc, 0x87, 0xb9, 0xc1, 0xf0, 0xdf,
- 0x71, 0x4b, 0xfb, 0x9c, 0x9e, 0xce, 0x2d, 0x32, 0x85, 0xd4, 0x89, 0x1f, 0x1e, 0x42, 0x3f, 0xd4,
- 0x75, 0xfa, 0x41, 0x1d, 0x9f, 0x47, 0x9e, 0x4b, 0x3a, 0x71, 0xdf, 0x8d, 0x5a, 0x9a, 0x3a, 0x94,
- 0x46, 0xe0, 0xe6, 0x10, 0xcf, 0x6b, 0xe1, 0x37, 0x94, 0x2b, 0x18, 0xbd, 0x41, 0x18, 0x06, 0xdd,
- 0x1d, 0x3c, 0x57, 0x9f, 0x42, 0xcc, 0x1b, 0xfa, 0x0b, 0x2b, 0xc8, 0xb4, 0x14, 0x3c, 0x2d, 0x4b,
- 0x90, 0x23, 0xf3, 0xcf, 0xca, 0x8d, 0x14, 0x2d, 0xcd, 0x3a, 0x5d, 0x4e, 0x30, 0x72, 0x87, 0x4b,
- 0xd7, 0xe0, 0xf1, 0x2d, 0x0c, 0x20, 0xd4, 0x9d, 0x58, 0xa2, 0xf2, 0x1b, 0x7b, 0xa5, 0x99, 0x55,
- 0x4a, 0x1a, 0xe8, 0x56, 0xf6, 0xa8, 0x2a, 0x79, 0xc9, 0xb5, 0x6a, 0x35, 0x41, 0x0a, 0x74, 0x84,
- 0xca, 0x13, 0xdc, 0x9d, 0x6f, 0xae, 0x69, 0x4a, 0x11, 0xa2, 0x51, 0x65, 0x26, 0x80, 0x8f, 0x7a,
- 0x24, 0xd4, 0x4f, 0x51, 0xe1, 0x4e, 0xa9, 0x1c, 0xe5, 0x2a, 0x5e, 0x64, 0x0e, 0x8b, 0x8d, 0xf9,
- 0xa9, 0x8b, 0x5d, 0x65, 0x05, 0xe1, 0xf6, 0xc4, 0x8d, 0x47, 0x3d, 0x9a, 0xc8, 0xdc, 0x58, 0xb6,
- 0x8a, 0x68, 0x30, 0x9b, 0x03, 0x8d, 0x21, 0x3c, 0xa8, 0x40, 0x7b, 0x57, 0x69, 0xec, 0xbc, 0xcf,
- 0x5e, 0x20, 0x3d, 0x30, 0xd7, 0x55, 0x5c, 0x51, 0xd4, 0x39, 0x4e, 0xf0, 0x01, 0xca, 0x68, 0x20,
- 0xec, 0x78, 0x8a, 0xf0, 0x54, 0x56, 0xe3, 0xa7, 0x87, 0x58, 0xcc, 0x1d, 0x15, 0xe5, 0x3d, 0x0b,
- 0x76, 0x21, 0x05, 0xd8, 0xcd, 0x60, 0x38, 0x3f, 0x6c, 0x20, 0xc7, 0x56, 0xe8, 0x3c, 0x9c, 0x54,
- 0xc4, 0xd1, 0x17, 0x36, 0xce, 0xaa, 0x69, 0xbc, 0x4d, 0x43, 0x90, 0x80, 0x7d, 0xf9, 0xd3, 0x2c,
- 0x46, 0x0c, 0x9e, 0x02, 0x91, 0xbb, 0x51, 0x9b, 0x45, 0x3f, 0xe2, 0xc0, 0x8c, 0x35, 0xc7, 0x98,
- 0xb9, 0xe1, 0xc6, 0x5f, 0x26, 0x40, 0xa7, 0x4e, 0x01, 0xa9, 0xae, 0x28, 0xd1, 0x05, 0xaa, 0xe9,
- 0x8e, 0xc4, 0x68, 0xb6, 0xe4, 0x01, 0x9a, 0x3c, 0x6c, 0x55, 0x3e, 0x39, 0x2c, 0x7e, 0xee, 0x48,
- 0xda, 0x2d, 0x4e, 0xb1, 0xd6, 0x3e, 0xb9, 0xfc, 0x91, 0x36, 0x77, 0xb1, 0xaf, 0x8d, 0x92, 0xca,
- 0xb3, 0xbc, 0xc6, 0x88, 0xfc, 0xe8, 0x2e, 0xa5, 0x6b, 0x63, 0xc3, 0xe4, 0xd3, 0xbf, 0xd0, 0xe9,
- 0x55, 0x3d, 0x97, 0x69, 0x7a, 0xf7, 0xa6, 0x4d, 0x96, 0xb7, 0x37, 0x22, 0x86, 0x39, 0x72, 0x2a,
- 0x4f, 0x96, 0xf7, 0x9e, 0x99, 0xf6, 0x8f, 0x71, 0xec, 0xee, 0x0e, 0xe7, 0x85, 0x04, 0xd3, 0x06,
- 0xd5, 0xe8, 0x13, 0xe0, 0x9c, 0x2a, 0xef, 0x3e, 0x2d, 0xdd, 0x08, 0x89, 0x43, 0x3e, 0x93, 0xe2,
- 0x9e, 0x17, 0xbc, 0xd6, 0x0f, 0xbd, 0x72, 0x93, 0xd0, 0x79, 0xcf, 0xd8, 0xce, 0x3c, 0x28, 0x45,
- 0x73, 0x49, 0x1c, 0x89, 0x76, 0xeb, 0x1c, 0xc9, 0x1f, 0xb9, 0x4c, 0xf2, 0x2b, 0x22, 0x40, 0xef,
- 0xe1, 0x03, 0xd0, 0x5b, 0xb4, 0x60, 0xb4, 0x39, 0x7b, 0x63, 0x24, 0xba, 0x1a, 0x32, 0xc8, 0x50,
- 0xbb, 0x39, 0x10, 0xe6, 0x26, 0x36, 0x82, 0x37, 0x04, 0xd1, 0x33, 0x32, 0x4e, 0x01, 0x02, 0x1e,
- 0x6b, 0x15, 0xc9, 0x6a, 0xf9, 0x59, 0x28, 0x90, 0x3b, 0xa9, 0xb0, 0xf8, 0x31, 0x00, 0xbd, 0xa8,
- 0xe3, 0x26, 0x42, 0x89, 0xfe, 0x84, 0xfb, 0xab, 0xb9, 0xc1, 0x31, 0xca, 0x04, 0xcf, 0x72, 0x9b,
- 0x44, 0xa7, 0xd5, 0x5b, 0x43, 0x93, 0x51, 0x17, 0x73, 0x02, 0x64, 0x98, 0xd0, 0xfd, 0x23, 0x0f,
- 0x6d, 0x50, 0x30, 0x9f, 0xaa, 0xaf, 0xc7, 0x7b, 0x7c, 0x4b, 0xa1, 0x94, 0xd4, 0x0e, 0xa3, 0x8f,
- 0xe5, 0x1c, 0xf9, 0x2a, 0xf8, 0xe4, 0x7f, 0xd2, 0x75, 0x31, 0xfa, 0x7d, 0x50, 0x4d, 0x1c, 0x47,
- 0x8d, 0x50, 0x31, 0xd4, 0x97, 0x08, 0xb2, 0x57, 0x83, 0xaf, 0x99, 0x6c, 0x54, 0xb0, 0x6a, 0x91,
- 0xf1, 0x3d, 0xf3, 0x99, 0x7e, 0x6d, 0x35, 0xc7, 0xee, 0x09, 0xa2, 0xf7, 0x5e, 0xba, 0x4a, 0x50,
- 0x8c, 0xbe, 0xd0, 0x74, 0x66, 0x18, 0xcb, 0x94, 0x44, 0xbf, 0x48, 0x9f, 0x35, 0xde, 0xe8, 0x68,
- 0x2b, 0x4c, 0x1e, 0x2a, 0x27, 0x33, 0x0c, 0x1c, 0x12, 0x27, 0xd3, 0x54, 0x77, 0xc3, 0xba, 0x51,
- 0xfe, 0xf9, 0x22, 0xcb, 0x11, 0x6d, 0x03, 0xbe, 0xad, 0x35, 0x3d, 0x8c, 0x8a, 0x9a, 0x18, 0x0a,
- 0xbb, 0x97, 0xf5, 0xa3, 0x77, 0x10, 0xa1, 0x8a, 0x65, 0x9c, 0x50, 0x41, 0xdf, 0xcf, 0x41, 0xf0,
- 0x26, 0xb5, 0x40, 0xa7, 0x87, 0xbe, 0xdb, 0x61, 0xce, 0x19, 0x75, 0x8d, 0xa3, 0x25, 0x14, 0x70,
- 0x40, 0x2a, 0x51, 0x7c, 0x4b, 0x40, 0x05, 0x48, 0x90, 0x65, 0xcc, 0x52, 0x40, 0x9f, 0xe6, 0x66,
- 0x0c, 0xa7, 0x35, 0xe3, 0xc3, 0x74, 0x10, 0x60, 0x45, 0x9e, 0xef, 0x1b, 0x10, 0xf0, 0x00, 0x76,
- 0x8f, 0xf0, 0x4d, 0x7e, 0x11, 0x49, 0x1b, 0x6a, 0x4e, 0xcf, 0xc9, 0xde, 0x0e, 0x53, 0x99, 0x24,
- 0x26, 0x77, 0xaf, 0x74, 0x0d, 0x9c, 0x22, 0xd8, 0x49, 0x8c, 0x7b, 0x8b, 0x99, 0x45, 0xfe, 0x03,
- 0xf4, 0x63, 0xe0, 0xf0, 0x15, 0xf9, 0x94, 0xd4, 0x4a, 0xc0, 0xcd, 0x06, 0xaf, 0xee, 0x6d, 0x27,
- 0xae, 0xcc, 0xa7, 0x30, 0xae, 0x04, 0x63, 0xca, 0x32, 0x35, 0x92, 0x4c, 0xed, 0xcb, 0x61, 0x9b,
- 0xfe, 0x3e, 0x6d, 0x05, 0x33, 0x26, 0xee, 0xaa, 0x90, 0xb1, 0x43, 0x70, 0x38, 0x98, 0x94, 0x46,
- 0xfd, 0x10, 0x1e, 0xdf, 0xe8, 0x8e, 0x25, 0x63, 0x90, 0x6f, 0x73, 0xc3, 0xc8, 0x91, 0x17, 0xad,
- 0x75, 0xf4, 0x0e, 0x98, 0x81, 0x40, 0x63, 0xb8, 0x30, 0xae, 0x1b, 0xc4, 0x07, 0xe6, 0x61, 0x23,
- 0xc1, 0x99, 0x18, 0x73, 0xd6, 0xa8, 0xee, 0x69, 0xa3, 0xec, 0x03, 0x8a, 0x46, 0x44, 0x52, 0x9a,
- 0x24, 0xe2, 0xc7, 0x50, 0xe4, 0xf4, 0xe2, 0xbd, 0x35, 0x41, 0xd7, 0x52, 0x6d, 0xb3, 0x49, 0xcf,
- 0x14, 0xc0, 0x73, 0xc8, 0x8e, 0xf6, 0x49, 0xf3, 0x35, 0xf9, 0x76, 0x20, 0x27, 0x82, 0x77, 0xae,
- 0xba, 0x6e, 0xc6, 0xba, 0x9d, 0xe1, 0x1e, 0xee, 0x87, 0x50, 0x56, 0x6a, 0x38, 0xfb, 0xc6, 0x0b,
- 0xd2, 0x8a, 0x17, 0x48, 0x28, 0x51, 0x5a, 0xa4, 0xbb, 0x7f, 0x4e, 0xb8, 0xc3, 0x26, 0x07, 0x24,
- 0xa6, 0x4a, 0x41, 0xf2, 0x5f, 0x75, 0xa1, 0x2b, 0x86, 0xc7, 0x29, 0xba, 0xac, 0x5f, 0x02, 0xec,
- 0xac, 0x9b, 0xa9, 0x7f, 0x89, 0xea, 0x53, 0xc1, 0x12, 0xe1, 0x34, 0xde, 0xe5, 0xd3, 0x7f, 0x5d,
- 0x16, 0x51, 0xba, 0xed, 0xda, 0xf8, 0x3a, 0xe8, 0x84, 0xfe, 0xde, 0xf0, 0x83, 0xbd, 0x10, 0xa3,
- 0xcf, 0xdc, 0x2f, 0x25, 0xe0, 0x94, 0x0a, 0x30, 0xda, 0x62, 0x31, 0xd5, 0x7e, 0xa3, 0xfb, 0xe0,
- 0xe0, 0x2d, 0x26, 0xe9, 0x14, 0xa2, 0x6f, 0x4e, 0x19, 0xf5, 0x09, 0xba, 0x67, 0x89, 0x79, 0x6f,
- 0x14, 0xe0, 0xd6, 0xac, 0x94, 0x2d, 0x65, 0x10, 0x76, 0x62, 0xb9, 0xa3, 0xcd, 0x20, 0xfe, 0xeb,
- 0x10, 0x5c, 0xe0, 0x75, 0xd3, 0x5d, 0xad, 0x39, 0x07, 0xd9, 0x1d, 0x6e, 0xb0, 0xe5, 0xa5, 0x79,
- 0x0d, 0xc3, 0xb9, 0xdd, 0xca, 0xbb, 0xa0, 0x5d, 0xa0, 0x16, 0xb6, 0xb9, 0xd6, 0x4c, 0xdb, 0x6f,
- 0xb2, 0x5a, 0xa9, 0x55, 0x00, 0x96, 0x14, 0xec, 0x31, 0xe6, 0x79, 0x0f, 0xd1, 0x9d, 0xde, 0xbb,
- 0x27, 0x8d, 0x44, 0xee, 0xec, 0xf2, 0xa3, 0x80, 0xbb, 0x21, 0xd3, 0xe7, 0xd3, 0xbe, 0xb3, 0x86,
- 0x6c, 0xa8, 0x7a, 0xab, 0xbf, 0xa7, 0x22, 0xcd, 0x4c, 0x25, 0x36, 0x03, 0x02, 0xe4, 0x11, 0xbf,
- 0xed, 0x06, 0x90, 0x0c, 0xf0, 0x30, 0xc7, 0x86, 0x7e, 0xaa, 0xc5, 0x84, 0x14, 0x54, 0xf7, 0x56,
- 0x17, 0x02, 0x88, 0xf5, 0xe1, 0xe7, 0xa7, 0xef, 0xe6, 0x71, 0xbc, 0x65, 0x65, 0x1e, 0x40, 0x97,
- 0x86, 0x5f, 0x8c, 0x44, 0xda, 0xa1, 0x38, 0x54, 0x1e, 0xdd, 0x39, 0xaa, 0x9e, 0x9e, 0xa6, 0x41,
- 0x4a, 0xf3, 0xb6, 0xde, 0x19, 0x74, 0x00, 0xfc, 0x2f, 0xf6, 0x0c, 0x00, 0x95, 0xfb, 0x50, 0x66,
- 0xa9, 0xc2, 0x3f, 0xaa, 0x48, 0x00, 0xa1, 0x4d, 0x6a, 0x80, 0x03, 0x00, 0x96, 0xcf, 0x1b, 0x9a,
- 0xb8, 0x9f, 0xde, 0x10, 0x98, 0x3e, 0x37, 0xf4, 0xc3, 0x30, 0xe6, 0xed, 0x7c, 0x2e, 0x53, 0x0e,
- 0xf4, 0xbe, 0xe2, 0x7e, 0xf6, 0x7d, 0xa7, 0x50, 0x43, 0xd7, 0x33, 0x15, 0xc5, 0x62, 0xae, 0xe5,
- 0xe2, 0xc5, 0x40, 0xe6, 0xa3, 0x63, 0x0f, 0x85, 0xd2, 0x33, 0xe6, 0x8d, 0xdc, 0x80, 0x3d, 0x79,
- 0x27, 0x21, 0x9c, 0x4f, 0xae, 0x14, 0x36, 0x4d, 0x36, 0x30, 0xa1, 0x1e, 0xf5, 0x8e, 0xb5, 0xbd,
- 0xa8, 0xc5, 0xe4, 0xb7, 0x96, 0xed, 0x10, 0x5b, 0x8c, 0xee, 0xc6, 0x8c, 0x93, 0xe9, 0xd9, 0x72,
- 0xb3, 0x10, 0xd1, 0x3e, 0x5b, 0x31, 0xc1, 0x27, 0xa4, 0x84, 0xe3, 0xc0, 0xf0, 0x1f, 0x27, 0xb7,
- 0x1f, 0x05, 0xed, 0x7c, 0xcd, 0x65, 0x01, 0xbf, 0x8d, 0x56, 0xe9, 0xfe, 0x9e, 0x53, 0x71, 0x93,
- 0x6c, 0xe0, 0x9c, 0x6e, 0x99, 0x56, 0xbb, 0x45, 0x87, 0x1f, 0x6a, 0x96, 0xac, 0x24, 0xf9, 0x7f,
- 0xbf, 0x10, 0x8c, 0x5e, 0x08, 0x12, 0x07, 0xcf, 0x8b, 0x4b, 0xcb, 0xd1, 0x6a, 0xce, 0x3d, 0x92,
- 0x81, 0x5d, 0x1d, 0x96, 0x72, 0xa8, 0xef, 0xdd, 0xb2, 0x13, 0xa8, 0xc6, 0xea, 0x07, 0x64, 0x8b,
- 0xd2, 0xe1, 0x79, 0x24, 0x0a, 0xf2, 0x92, 0xa8, 0x37, 0xe2, 0x5c, 0x89, 0xd3, 0x09, 0x60, 0x7d,
- 0xbf, 0xac, 0xff, 0xde, 0xe6, 0x8b, 0x1b, 0x38, 0x33, 0xd7, 0xa1, 0x9d, 0x05, 0xe8, 0x69, 0x27,
- 0xd9, 0xb7, 0xae, 0x72, 0xbb, 0x05, 0xee, 0x77, 0x96, 0x48, 0xa2, 0x02, 0x0d, 0x88, 0x1c, 0x4f,
- 0x22, 0xf9, 0xcd, 0xd3, 0xe1, 0x50, 0x08, 0xb6, 0xea, 0x2a, 0x96, 0x43, 0xf3, 0x8a, 0x92, 0x3b,
- 0x2b, 0x5e, 0xbc, 0xa0, 0x4f, 0xd3, 0xf1, 0xcc, 0x1c, 0xde, 0xc4, 0x91, 0x35, 0x33, 0x51, 0xe5,
- 0xe0, 0xa9, 0x75, 0xfe, 0x0a, 0x5d, 0xc8, 0x8b, 0x63, 0x33, 0xd9, 0xe0, 0x73, 0xcb, 0xdb, 0x70,
- 0x0a, 0x82, 0xb7, 0x7a, 0x5c, 0x27, 0xbf, 0xd1, 0xdc, 0x62, 0xa3, 0x20, 0x63, 0x5f, 0x54, 0x4a,
- 0xaf, 0xa3, 0xe0, 0x77, 0xbb, 0xcd, 0xab, 0x62, 0x73, 0x31, 0x72, 0x2a, 0x1d, 0x02, 0x87, 0x88,
- 0x02, 0x24, 0x10, 0x9c, 0x35, 0x5c, 0x72, 0x04, 0x1c, 0x1a, 0xea, 0x44, 0xf4, 0x41, 0xc6, 0x20,
- 0xde, 0x91, 0xf7, 0x0c, 0x4a, 0xae, 0xca, 0xb7, 0x73, 0x59, 0xf6, 0xdd, 0x8e, 0x58, 0xae, 0x8a,
- 0xcd, 0x62, 0xa6, 0x22, 0xef, 0x79, 0xbb, 0xf9, 0x4b, 0xf9, 0x71, 0x6b, 0xab, 0xe5, 0x02, 0x13,
- 0xe3, 0x35, 0xd9, 0xea, 0x95, 0x33, 0x1a, 0x22, 0x1c, 0x45, 0xe6, 0x9b, 0xfb, 0x61, 0xaf, 0x3d,
- 0xbe, 0xbe, 0x9f, 0xb8, 0x83, 0x33, 0x31, 0x5b, 0x14, 0x38, 0x2d, 0xcf, 0xe7, 0xce, 0xd3, 0xab,
- 0xca, 0xbc, 0xec, 0x30, 0x17, 0x36, 0x1d, 0x1a, 0xb7, 0x2b, 0xee, 0x53, 0x34, 0xfc, 0x63, 0x9f,
- 0x95, 0xe1, 0xf0, 0x8b, 0xdb, 0x74, 0x0c, 0x44, 0xd3, 0x04, 0x76, 0x3a, 0x41, 0xdf, 0xd0, 0x8f,
- 0xa9, 0x93, 0xd6, 0x14, 0x73, 0xc7, 0x7f, 0x2b, 0xa6, 0xb2, 0x79, 0xe4, 0x4a, 0xc8, 0xb0, 0x5e,
- 0x9a, 0xce, 0xc4, 0xf6, 0x8a, 0xeb, 0x8c, 0xa7, 0x86, 0xa6, 0x4f, 0x5f, 0x48, 0xff, 0xb4, 0x05,
- 0xf3, 0xc8, 0x81, 0x75, 0x37, 0xd5, 0x8b, 0x40, 0xdf, 0x3e, 0x20, 0x37, 0xf5, 0x5a, 0xcf, 0xbe,
- 0x6f, 0x7e, 0x22, 0xc4, 0xf7, 0xfa, 0x34, 0x4a, 0x81, 0x0a, 0x44, 0x3d, 0x1d, 0xe9, 0x6c, 0xb1,
- 0xe1, 0xd6, 0x81, 0xd4, 0x98, 0x7c, 0x65, 0xa2, 0x26, 0x97, 0x84, 0x80, 0x76, 0x58, 0x53, 0x0b,
- 0x94, 0x82, 0x08, 0x66, 0x80, 0x63, 0xf9, 0x01, 0x4a, 0xee, 0xb5, 0xe2, 0x8a, 0xfa, 0xce, 0xee,
- 0x7c, 0x97, 0xb6, 0x91, 0xe9, 0xb3, 0x5e, 0x14, 0x50, 0xd5, 0xf1, 0xdf, 0x8f, 0x5d, 0x0e, 0x78,
- 0x2f, 0xdd, 0xb2, 0x82, 0x98, 0x73, 0xc5, 0xf4, 0x32, 0x1c, 0x65, 0x6d, 0xa4, 0xe3, 0xba, 0xdb,
- 0xfa, 0x65, 0x37, 0xee, 0x57, 0x2b, 0xfa, 0x38, 0x2f, 0x14, 0x2d, 0xf6, 0x19, 0x0b, 0xe0, 0x59,
- 0xb9, 0x95, 0x02, 0xfa, 0x2f, 0x84, 0x56, 0x41, 0x76, 0xa3, 0xca, 0x30, 0xf5, 0x4b, 0x97, 0x2d,
- 0x33, 0x3b, 0x71, 0x09, 0x49, 0x48, 0x46, 0xa0, 0x79, 0xd3, 0xce, 0x32, 0x35, 0xa4, 0xb2, 0x05,
- 0x5d, 0xaf, 0x1f, 0x22, 0x48, 0xcb, 0xca, 0x5b, 0xaa, 0x69, 0x6e, 0x6f, 0x23, 0x6f, 0xcd, 0x67,
- 0x06, 0x71, 0xf1, 0x6a, 0x5f, 0x65, 0xbe, 0xb0, 0x5f, 0x7b, 0xec, 0x9e, 0x1d, 0xa4, 0xf2, 0x4b,
- 0xbc, 0xde, 0xc0, 0x84, 0x87, 0xa3, 0x2f, 0x97, 0x12, 0xc5, 0xf9, 0x34, 0x54, 0x0a, 0xf1, 0x7c,
- 0x95, 0x16, 0xe7, 0xf9, 0x83, 0x40, 0xcf, 0x42, 0xc9, 0x5b, 0xff, 0x0e, 0x01, 0xf0, 0x1b, 0xe5,
- 0x75, 0xee, 0x7c, 0x33, 0x1f, 0x00, 0x03, 0x2f, 0x92, 0xa7, 0x3d, 0x51, 0xac, 0x43, 0x67, 0xb8,
- 0x45, 0x4f, 0xde, 0x10, 0xee, 0xeb, 0x5b, 0x62, 0x65, 0x6b, 0x70, 0xc3, 0x3d, 0x46, 0x1f, 0x00,
- 0x0f, 0x08, 0xeb, 0xca, 0x33, 0xd5, 0x7d, 0x97, 0x84, 0x88, 0x8a, 0x24, 0x4d, 0x02, 0xcd, 0xee,
- 0xa0, 0x11, 0xb1, 0x2d, 0xb6, 0xf5, 0x18, 0x68, 0xb5, 0x79, 0x15, 0x5b, 0x44, 0xb3, 0xba, 0x8b,
- 0x78, 0x28, 0x08, 0x32, 0xf1, 0x25, 0x4f, 0xde, 0x48, 0x80, 0x5e, 0x9f, 0x1b, 0xc9, 0x39, 0xd3,
- 0x87, 0x9f, 0xae, 0x66, 0xf2, 0x12, 0x92, 0x17, 0xec, 0xaa, 0xbd, 0x00, 0x93, 0x00, 0x09, 0x76,
- 0xab, 0xfb, 0x2a, 0xda, 0x34, 0xe5, 0xa6, 0x2a, 0xfa, 0x9a, 0x88, 0x39, 0x66, 0xa2, 0x47, 0x2f,
- 0x71, 0x40, 0xa6, 0x7e, 0x7d, 0x52, 0x1d, 0x12, 0x21, 0x5f, 0xca, 0xe8, 0xba, 0x5a, 0x80, 0x88,
- 0x5f, 0xb0, 0x1f, 0xc1, 0x12, 0x58, 0xbd, 0x35, 0x13, 0xfb, 0x7d, 0x38, 0xea, 0x5a, 0x79, 0x4f,
- 0x37, 0x87, 0xd0, 0xbe, 0x92, 0xe1, 0x5b, 0xbe, 0x84, 0x2a, 0x40, 0x13, 0xd1, 0xe1, 0xdf, 0x39,
- 0x0b, 0x11, 0x45, 0xe9, 0x0e, 0x09, 0x9d, 0xfc, 0xeb, 0xc4, 0xc3, 0xf8, 0x26, 0xbd, 0x80, 0x38,
- 0xf7, 0x04, 0x13, 0x4f, 0x3c, 0x3d, 0x7e, 0xa3, 0xbe, 0x54, 0x1b, 0x1f, 0xf6, 0xc2, 0x11, 0x93,
- 0xd9, 0x41, 0x0f, 0x64, 0x3a, 0x1c, 0x6e, 0x19, 0x6e, 0xbf, 0x79, 0x3b, 0xbd, 0xa8, 0x03, 0xae,
- 0xf2, 0x62, 0x7f, 0xda, 0xf6, 0xe8, 0x84, 0xd9, 0xd9, 0xdb, 0xfd, 0xa2, 0x6a, 0x38, 0x60, 0x2a,
- 0x30, 0xf2, 0x1f, 0x1f, 0x63, 0xb1, 0x46, 0x7e, 0x78, 0x3e, 0x2c, 0xd9, 0xf4, 0x56, 0xdb, 0xa7,
- 0x5e, 0x67, 0x8a, 0x16, 0x9b, 0xc8, 0xea, 0x78, 0x35, 0xc2, 0xef, 0x1a, 0xb5, 0x17, 0x4e, 0xba,
- 0x17, 0x04, 0xb8, 0xd7, 0x70, 0x30, 0xb4, 0x4f, 0xb0, 0x91, 0x92, 0x73, 0x2f, 0x0a, 0xff, 0xd7,
- 0x8b, 0xcf, 0x43, 0x7d, 0xfe, 0x9e, 0xca, 0xfa, 0x69, 0x12, 0x0f, 0x51, 0xe9, 0xa4, 0x13, 0x6a,
- 0x2a, 0x4f, 0xaa, 0x5f, 0x13, 0xef, 0x45, 0x05, 0xd9, 0xaa, 0xc8, 0x28, 0x84, 0x7e, 0xc9, 0xca,
- 0xba, 0x3d, 0x93, 0xb1, 0x38, 0x16, 0x3f, 0xf1, 0x18, 0x1b, 0x32, 0xa8, 0xc2, 0xdf, 0xe3, 0x21,
- 0x8e, 0x8b, 0x70, 0x6e, 0x58, 0x65, 0x70, 0x93, 0xa5, 0xcc, 0x15, 0x2a, 0xd6, 0xb0, 0xc3, 0xcf,
- 0x6b, 0xf5, 0x09, 0xa4, 0x6c, 0x29, 0xc7, 0xcd, 0x19, 0xf6, 0x4d, 0x15, 0xb1, 0x77, 0x65, 0xdb,
- 0x7e, 0x55, 0x24, 0x05, 0x39, 0xa7, 0xf8, 0xdc, 0x16, 0x44, 0xf5, 0xf2, 0x69, 0x9f, 0x6f, 0x8e,
- 0xaf, 0x6e, 0xfc, 0x9a, 0x75, 0x57, 0x22, 0x2f, 0x33, 0xf8, 0xaa, 0x3d, 0x4e, 0x70, 0x2d, 0x74,
- 0x33, 0xbc, 0xea, 0xcf, 0x48, 0xe7, 0xb8, 0xd0, 0xf5, 0xda, 0xd3, 0xe3, 0xa7, 0x43, 0x4f, 0xdd,
- 0x7c, 0x80, 0x07, 0x69, 0xc9, 0x2d, 0x2c, 0x58, 0xa1, 0x4d, 0x9c, 0xd7, 0x20, 0xb6, 0xaf, 0xb0,
- 0x5f, 0x3d, 0x5b, 0x35, 0x3f, 0xf4, 0x51, 0x52, 0x47, 0xc5, 0xaa, 0x9c, 0x4d, 0x9c, 0xa4, 0x73,
- 0x35, 0xd9, 0xa0, 0xa4, 0x52, 0x0a, 0x7b, 0xcb, 0x6c, 0xef, 0xb4, 0x65, 0x06, 0xc4, 0x95, 0x3b,
- 0x59, 0xf2, 0xd1, 0x09, 0x0b, 0x22, 0x9c, 0x72, 0xac, 0x4d, 0xb1, 0xb6, 0x3b, 0x72, 0xcd, 0xad,
- 0x91, 0x95, 0x49, 0x30, 0x43, 0x54, 0x0e, 0xf3, 0x53, 0x89, 0xd2, 0x13, 0x40, 0xca, 0x44, 0x90,
- 0x37, 0x11, 0xf8, 0x9a, 0xbf, 0xf5, 0x6f, 0x0b, 0xa4, 0x47, 0x03, 0x59, 0x6a, 0x48, 0xdc, 0x11,
- 0xeb, 0x51, 0x1b, 0x56, 0x42, 0x03, 0xc9, 0x4e, 0xbc, 0x4c, 0x3f, 0x05, 0x48, 0x32, 0x48, 0x7d,
- 0x5b, 0x77, 0x4b, 0x75, 0xbf, 0x14, 0x72, 0x31, 0x86, 0x10, 0x99, 0x87, 0x33, 0x4c, 0x3c, 0xc2,
- 0x8a, 0x76, 0x36, 0xfc, 0x44, 0x19, 0xe4, 0xd1, 0x9d, 0x29, 0x7c, 0x17, 0xea, 0xa6, 0x3a, 0x90,
- 0x4b, 0x01, 0x5b, 0x37, 0x45, 0xc6, 0x4f, 0x59, 0xb0, 0x6a, 0xeb, 0xe4, 0x2c, 0x0c, 0x87, 0x91,
- 0x06, 0x6d, 0xeb, 0xea, 0x3b, 0x3d, 0xbc, 0x1a, 0x0a, 0xd8, 0x1b, 0xd6, 0x71, 0xa5, 0x6c, 0x4c,
- 0x1c, 0xde, 0x46, 0xb4, 0x2c, 0x15, 0xc3, 0xe8, 0x7d, 0x70, 0x96, 0x85, 0x1d, 0xc3, 0x53, 0x3c,
- 0xdc, 0x1b, 0x4f, 0xe2, 0x79, 0x39, 0x74, 0xe5, 0x49, 0x8e, 0xd4, 0xb5, 0x59, 0x19, 0xc1, 0xe9,
- 0x37, 0xbd, 0xad, 0x90, 0x33, 0x9f, 0xaf, 0x46, 0xfe, 0xd8, 0xcd, 0x30, 0x04, 0x1d, 0x96, 0xf8,
- 0x2d, 0xe6, 0xc4, 0xfb, 0xac, 0x56, 0xb1, 0x26, 0x33, 0xc0, 0x38, 0x19, 0x3b, 0xe3, 0xf4, 0xaf,
- 0x4f, 0x77, 0x5c, 0xe3, 0xc0, 0x0b, 0x81, 0x29, 0x7f, 0xd4, 0x43, 0x4d, 0x7b, 0x87, 0xd4, 0x28,
- 0x37, 0x22, 0xbb, 0x16, 0x54, 0xe6, 0xe2, 0x55, 0x11, 0xda, 0xf4, 0xc5, 0xe1, 0xbb, 0xdb, 0xf9,
- 0xb4, 0xd7, 0x25, 0x27, 0x09, 0x4d, 0x37, 0x82, 0x9b, 0x64, 0x31, 0xbc, 0x3d, 0x2c, 0x66, 0xcd,
- 0x60, 0x3a, 0x74, 0x7d, 0xfd, 0xdb, 0x74, 0x31, 0x4e, 0x35, 0x98, 0x76, 0x84, 0x87, 0x49, 0x2d,
- 0xce, 0x50, 0x57, 0xbd, 0x12, 0x65, 0xfb, 0xa4, 0x7b, 0x4e, 0xb6, 0x8a, 0x4d, 0x73, 0xf2, 0xfb,
- 0xc0, 0x35, 0xcf, 0xf7, 0x79, 0xb2, 0x5d, 0x8d, 0xbc, 0xd3, 0x7d, 0x0c, 0xa7, 0xd1, 0xf1, 0xdb,
- 0x10, 0xa3, 0x91, 0xae, 0x99, 0xc5, 0xed, 0x80, 0x15, 0xb7, 0x5e, 0xea, 0x11, 0xa7, 0xb1, 0x64,
- 0x7c, 0x3b, 0x08, 0xfd, 0xf0, 0xa1, 0x2a, 0x9f, 0xaf, 0xf0, 0x9b, 0x43, 0x43, 0x4f, 0xc1, 0xd5,
- 0x39, 0xba, 0xda, 0x3f, 0x49, 0x5d, 0x13, 0x53, 0xa1, 0x3d, 0x34, 0xc4, 0xd2, 0xdb, 0xf5, 0x76,
- 0x42, 0x37, 0x07, 0x2e, 0xd6, 0x0a, 0x3d, 0x12, 0xe4, 0x6f, 0x68, 0x4e, 0x70, 0x0d, 0x29, 0x9e,
- 0x54, 0x07, 0x48, 0xba, 0xc7, 0xfa, 0xfd, 0x73, 0x7d, 0x6d, 0x0d, 0x07, 0x98, 0xeb, 0x5e, 0x67,
- 0xa5, 0x6a, 0x6a, 0x91, 0x87, 0x23, 0x59, 0xf6, 0x9c, 0x90, 0xa2, 0xd7, 0x07, 0x93, 0xb6, 0xed,
- 0xe2, 0x38, 0x2b, 0xc0, 0x2d, 0x08, 0x98, 0x6c, 0x11, 0x45, 0x05, 0x8d, 0xa8, 0x17, 0xf1, 0x10,
- 0xcb, 0xca, 0xf5, 0x90, 0x41, 0x15, 0x75, 0x22, 0x62, 0xd2, 0x0c, 0xc2, 0xf7, 0x5a, 0xb0, 0x64,
- 0xbe, 0xf7, 0x6d, 0x57, 0xa6, 0x64, 0x28, 0x12, 0x1d, 0x98, 0x93, 0x2b, 0xf5, 0xd7, 0xa2, 0x3f,
- 0x35, 0x1b, 0xd4, 0x49, 0x68, 0x15, 0xa9, 0x19, 0xa1, 0x8c, 0x03, 0xe7, 0x83, 0x4d, 0x2d, 0xf3,
- 0xe8, 0xc3, 0xbd, 0xec, 0x1d, 0x7e, 0x3f, 0x68, 0x3a, 0x66, 0xac, 0xbe, 0xb5, 0xcc, 0xd3, 0x57,
- 0xf7, 0x84, 0xac, 0xd4, 0x32, 0x21, 0xed, 0xb1, 0x2b, 0xe7, 0x4c, 0x8d, 0x5a, 0xeb, 0xf6, 0x06,
- 0xcd, 0xa7, 0xad, 0x7e, 0x78, 0xc5, 0x1f, 0xce, 0x35, 0x02, 0x47, 0xd3, 0x20, 0x73, 0x0f, 0x26,
- 0xfc, 0x23, 0xa8, 0x84, 0xf5, 0x58, 0xc0, 0xc1, 0x43, 0x60, 0x47, 0x61, 0x1f, 0x8a, 0xe7, 0xe9,
- 0x9a, 0x6e, 0x7f, 0xba, 0xb4, 0x06, 0xc3, 0x9b, 0x1e, 0x5b, 0x98, 0xbc, 0x0e, 0x52, 0x3f, 0x4c,
- 0x40, 0xd9, 0xbc, 0x7b, 0x85, 0x9e, 0x39, 0x36, 0xba, 0x2a, 0x63, 0xa5, 0xe4, 0x97, 0xad, 0xfc,
- 0xbd, 0xa2, 0xd1, 0x80, 0x3b, 0x0c, 0xe6, 0xc8, 0x08, 0x62, 0xe1, 0x24, 0x9a, 0x90, 0x7e, 0xb2,
- 0x6f, 0x09, 0xac, 0xbc, 0x89, 0xc2, 0x8b, 0xc5, 0x07, 0xc7, 0x4e, 0x20, 0xf1, 0xe8, 0x81, 0x61,
- 0x67, 0xf1, 0x7d, 0x93, 0xdb, 0xb8, 0x31, 0xde, 0xd4, 0x90, 0x8e, 0x49, 0x30, 0xeb, 0xc1, 0xff,
- 0x9f, 0x73, 0xd6, 0x75, 0x0e, 0x2f, 0x38, 0xe5, 0x86, 0xb6, 0x5f, 0x35, 0x35, 0x0e, 0xd9, 0xea,
- 0x73, 0xe8, 0xf3, 0xe2, 0x7a, 0x08, 0xe0, 0x9c, 0x9a, 0xbd, 0xc8, 0x5d, 0xd3, 0xda, 0x4c, 0x7b,
- 0x13, 0xac, 0x71, 0x28, 0xf6, 0x8f, 0xcf, 0xcb, 0x4d, 0x70, 0x7e, 0x8f, 0x02, 0x44, 0xfa, 0xdf,
- 0x41, 0x18, 0x02, 0xa4, 0x3f, 0xed, 0xdc, 0x0a, 0x5c, 0x84, 0x45, 0xaa, 0x2c, 0x35, 0x97, 0x4d,
- 0x29, 0x7d, 0x78, 0xc8, 0x04, 0xe4, 0x8c, 0xb5, 0xa9, 0xed, 0xd9, 0x54, 0x25, 0xca, 0x9a, 0x91,
- 0xb4, 0x98, 0xd9, 0x5e, 0xba, 0x54, 0x3b, 0x8b, 0xec, 0x3c, 0xa3, 0xcc, 0xfa, 0x08, 0xa0, 0x2e,
- 0xe3, 0x0d, 0xa3, 0x21, 0xaa, 0x9a, 0x3d, 0x7f, 0xdd, 0x09, 0xfc, 0xae, 0xa8, 0x4f, 0xd1, 0x4d,
- 0xd2, 0xc6, 0x8b, 0x17, 0xae, 0x3c, 0xb7, 0x38, 0xcc, 0xd0, 0xa1, 0x21, 0x98, 0x20, 0xbd, 0xbb,
- 0x03, 0xa4, 0x47, 0x24, 0x37, 0x7f, 0xd5, 0xdb, 0xdf, 0x84, 0x5d, 0xd9, 0x19, 0x17, 0xde, 0xb8,
- 0x51, 0x09, 0xed, 0x02, 0xc6, 0x72, 0x9a, 0xd2, 0xfa, 0x01, 0x81, 0xe6, 0xbd, 0x7a, 0x58, 0x17,
- 0xed, 0x88, 0xb1, 0x83, 0x16, 0x82, 0x73, 0xf0, 0xa7, 0xc2, 0xe6, 0x67, 0x8e, 0x4a, 0xb1, 0xac,
- 0x76, 0x66, 0xa8, 0xe2, 0x35, 0xcc, 0x13, 0xfe, 0x5b, 0xed, 0x9d, 0x60, 0x24, 0x5b, 0x74, 0x3c,
- 0x81, 0xd6, 0x1c, 0x31, 0xdf, 0xc8, 0xd5, 0x74, 0xbf, 0xcb, 0x4f, 0x53, 0x68, 0x05, 0x90, 0xa5,
- 0xba, 0xd5, 0x4f, 0x80, 0x43, 0x50, 0x65, 0x29, 0x42, 0xf2, 0x1a, 0x88, 0xb8, 0x61, 0xbf, 0x65,
- 0x59, 0xad, 0x2f, 0x2e, 0xf1, 0x4f, 0xef, 0xe4, 0xc0, 0xde, 0x37, 0xb5, 0xfb, 0xd9, 0x2e, 0x50,
- 0x2a, 0x3e, 0xac, 0xe4, 0x45, 0xa4, 0xd5, 0x2f, 0xac, 0x9a, 0xc1, 0x7c, 0xd4, 0x95, 0xe1, 0x86,
- 0x4d, 0xae, 0x2b, 0x5e, 0x11, 0x7b, 0xe7, 0x38, 0x5e, 0x93, 0x53, 0x95, 0x9c, 0x65, 0xcc, 0x8b,
- 0x78, 0x6a, 0x0e, 0x28, 0x68, 0xba, 0x50, 0xd0, 0x74, 0x5d, 0x7c, 0x62, 0x2b, 0xa3, 0xb4, 0xe0,
- 0x96, 0x8e, 0x2b, 0x0b, 0xcc, 0xbc, 0x0c, 0x4f, 0xcb, 0xe6, 0x89, 0x4e, 0xd0, 0x2e, 0x17, 0x9a,
- 0x37, 0x13, 0x55, 0x68, 0x2c, 0x67, 0xf2, 0x12, 0x92, 0x35, 0x08, 0x93, 0x17, 0xaf, 0x70, 0x8b,
- 0x08, 0x8e, 0x4e, 0x5e, 0x91, 0x1d, 0x8e, 0x8e, 0x5a, 0xb3, 0xf8, 0xa0, 0x11, 0x1f, 0xe0, 0xfb,
- 0xf3, 0xf1, 0xb2, 0x1c, 0x56, 0x97, 0x6d, 0xd4, 0x6d, 0xa3, 0x19, 0x50, 0x00, 0xf4, 0xef, 0x7c,
- 0x90, 0xe8, 0x89, 0x33, 0x6d, 0xf9, 0x90, 0x44, 0xa0, 0x7d, 0xa2, 0x6e, 0xab, 0x87, 0xe5, 0xc9,
- 0xe8, 0xc5, 0x28, 0x64, 0xf6, 0x29, 0x95, 0xf4, 0x69, 0xb3, 0xa1, 0xbc, 0x14, 0xc2, 0x2f, 0x30,
- 0x50, 0x80, 0x08, 0x58, 0xae, 0x0d, 0x72, 0x66, 0x2c, 0x30, 0x43, 0xfe, 0x07, 0x0d, 0xa3, 0x1d,
- 0x58, 0x1c, 0x16, 0x5e, 0x1d, 0x80, 0xf6, 0x99, 0x53, 0x92, 0xd6, 0x57, 0x6c, 0x83, 0xae, 0x80,
- 0x83, 0x69, 0xa9, 0x22, 0x7b, 0xbc, 0x6f, 0x11, 0x94, 0x8c, 0xab, 0xa5, 0x25, 0x8d, 0x52, 0x66,
- 0x33, 0x09, 0xb6, 0x67, 0x93, 0x9d, 0x44, 0x09, 0xf8, 0xf0, 0xdc, 0x06, 0x5d, 0xb3, 0x49, 0x50,
- 0xcc, 0x9a, 0xf8, 0x85, 0xc1, 0x5f, 0xf7, 0x43, 0xa4, 0x72, 0xb9, 0x05, 0xad, 0xcd, 0x5e, 0x29,
- 0x1c, 0x37, 0xd2, 0x0b, 0xac, 0x73, 0xd4, 0x75, 0x4f, 0x26, 0x06, 0x1e, 0x4b, 0x9f, 0xef, 0xea,
- 0xb0, 0xee, 0x3f, 0xd9, 0xb4, 0x11, 0xd0, 0x25, 0x18, 0x00, 0x09, 0x21, 0xe2, 0x60, 0x67, 0x18,
- 0x7e, 0x87, 0x87, 0xb0, 0x14, 0xaf, 0x4d, 0xa2, 0x88, 0x81, 0x77, 0x71, 0x33, 0x5c, 0xb8, 0x0d,
- 0x12, 0x3c, 0x5e, 0xb0, 0x52, 0xb0, 0x29, 0x39, 0xf2, 0xed, 0x6a, 0xe0, 0x94, 0x58, 0xd7, 0x23,
- 0x4b, 0xa7, 0x3d, 0x93, 0xc9, 0x05, 0x06, 0xba, 0x32, 0x73, 0x00, 0x1e, 0xeb, 0x6f, 0x64, 0xd5,
- 0x89, 0x17, 0x45, 0xcd, 0x91, 0x13, 0x42, 0xb5, 0xd3, 0x6f, 0x9d, 0xa2, 0xde, 0xbc, 0x07, 0x23,
- 0x4f, 0x1d, 0xf9, 0x89, 0x99, 0x8c, 0x9e, 0xde, 0xa4, 0x7f, 0xab, 0xfc, 0x54, 0x04, 0x0f, 0x11,
- 0x5c, 0xbc, 0xd6, 0xd3, 0x54, 0x13, 0xe9, 0x7a, 0x99, 0x04, 0x57, 0xf2, 0xf0, 0x7c, 0xb7, 0x56,
- 0x5c, 0x9c, 0x37, 0xbd, 0xfc, 0xa5, 0xb0, 0x8d, 0x3d, 0x02, 0x0e, 0x61, 0xdd, 0x20, 0xd6, 0x44,
- 0x8a, 0x0b, 0x58, 0xd8, 0x33, 0x17, 0x2d, 0x85, 0x0c, 0xb1, 0x7f, 0x6a, 0xb1, 0xca, 0x37, 0xb8,
- 0xba, 0x10, 0x09, 0x12, 0x28, 0xac, 0x00, 0x2b, 0x3e, 0x5e, 0x0e, 0x92, 0xe3, 0x6b, 0xef, 0xe6,
- 0xc6, 0x8e, 0x28, 0xfa, 0xc2, 0x58, 0x55, 0x09, 0x94, 0xe9, 0xaa, 0xad, 0x4e, 0x2d, 0x93, 0xd7,
- 0x2d, 0xdb, 0xfb, 0xce, 0x3b, 0x7d, 0x47, 0x4c, 0xa7, 0x1f, 0x07, 0x8d, 0x6b, 0x09, 0x81, 0xf8,
- 0x72, 0x76, 0x84, 0xc8, 0xc1, 0xf9, 0x95, 0x4b, 0x8e, 0xb0, 0xaa, 0xe6, 0x37, 0xad, 0xcd, 0x21,
- 0x92, 0xd8, 0x45, 0x2d, 0xda, 0xda, 0xa1, 0x2f, 0x85, 0x89, 0x16, 0x68, 0x5d, 0x41, 0x8a, 0x98,
- 0x09, 0x8c, 0xcc, 0x32, 0xa2, 0xc8, 0xfc, 0xea, 0x3d, 0x55, 0xda, 0x4d, 0x53, 0x17, 0x93, 0xbc,
- 0x5b, 0x59, 0x9f, 0x50, 0x5c, 0xcf, 0x03, 0x6b, 0x94, 0x5d, 0xbc, 0x6d, 0xe7, 0x9c, 0x6d, 0x62,
- 0x95, 0xaa, 0x35, 0xa3, 0x23, 0x42, 0x9f, 0xfb, 0x5e, 0xc1, 0xd7, 0x49, 0x89, 0xbd, 0xc4, 0xe8,
- 0xcf, 0x22, 0xd3, 0xcf, 0x3d, 0x2f, 0x6d, 0x08, 0x0c, 0x4c, 0x17, 0x5b, 0x87, 0x44, 0x9f, 0x8b,
- 0x73, 0xe0, 0xe9, 0x36, 0xb7, 0x92, 0x5b, 0xfd, 0x62, 0x76, 0x7b, 0x67, 0xc0, 0x47, 0xff, 0x68,
- 0x01, 0x91, 0x85, 0x3a, 0x95, 0xc7, 0x19, 0xf7, 0xb0, 0x72, 0x83, 0x88, 0x5a, 0xdc, 0x58, 0x14,
- 0xe8, 0xa7, 0x53, 0x9e, 0x69, 0xe4, 0x6c, 0x39, 0x3d, 0xbe, 0x5f, 0x72, 0x6b, 0xb4, 0xd5, 0x80,
- 0xfb, 0x44, 0x24, 0x88, 0x08, 0x14, 0xf6, 0xe8, 0xd8, 0x2c, 0x1a, 0x5c, 0xf0, 0x86, 0x79, 0xc4,
- 0x40, 0x5c, 0xc8, 0xab, 0x53, 0x27, 0xd3, 0xce, 0x00, 0x99, 0x7f, 0x6a, 0x91, 0x35, 0x81, 0x90,
- 0x8a, 0x5f, 0x2d, 0xf6, 0x12, 0x06, 0xa5, 0x75, 0x04, 0x85, 0x35, 0x66, 0x23, 0x5f, 0xc6, 0x00,
- 0x69, 0x67, 0xf6, 0x5e, 0x7b, 0x18, 0x92, 0x80, 0x26, 0x03, 0xb0, 0x73, 0xcb, 0x8e, 0xba, 0xf7,
- 0xda, 0x6f, 0xee, 0x8f, 0x6c, 0x3f, 0xcd, 0xc6, 0x73, 0x51, 0x5d, 0xdc, 0x55, 0x69, 0xcd, 0x02,
- 0x24, 0x52, 0x62, 0x83, 0xba, 0x27, 0xaa, 0x73, 0x15, 0xe7, 0xd4, 0x7a, 0xc1, 0xd5, 0x8e, 0xad,
- 0xb4, 0x68, 0xb9, 0x40, 0xcb, 0x5d, 0x9e, 0x67, 0x84, 0x2b, 0x14, 0x78, 0xcd, 0xa5, 0xc2, 0x81,
- 0x91, 0x3b, 0x0f, 0x70, 0x43, 0x26, 0xba, 0x24, 0x3d, 0x14, 0x08, 0x13, 0xba, 0xf9, 0x7c, 0x38,
- 0x55, 0x51, 0x57, 0x6e, 0xef, 0xf0, 0x92, 0xd1, 0x06, 0xb4, 0x06, 0xd5, 0xf1, 0xf5, 0xb4, 0xda,
- 0x1b, 0xad, 0x52, 0xc2, 0x6d, 0x1e, 0x82, 0xb0, 0x04, 0x5f, 0x5d, 0x92, 0x8d, 0x98, 0x9d, 0x30,
- 0x24, 0x5f, 0x47, 0x9f, 0x34, 0x02, 0x9a, 0x83, 0x82, 0x5e, 0xcd, 0xeb, 0x13, 0x40, 0x15, 0xa5,
- 0x13, 0xd3, 0xff, 0x19, 0x1c, 0x67, 0x74, 0xf5, 0xf3, 0x50, 0xb9, 0xbf, 0xa9, 0x64, 0x8a, 0x90,
- 0x69, 0xc2, 0x93, 0xf9, 0xfc, 0xca, 0xa5, 0x2a, 0xb7, 0x99, 0x70, 0x93, 0x2a, 0x4b, 0x57, 0x77,
- 0x8f, 0xc9, 0x58, 0xc5, 0x18, 0xff, 0x8d, 0xdc, 0x02, 0x41, 0xac, 0x93, 0xee, 0x5b, 0x14, 0xd8,
- 0xfe, 0x92, 0x49, 0x61, 0xc3, 0xda, 0xfe, 0xf9, 0x70, 0x17, 0x87, 0xe2, 0x34, 0xd6, 0xac, 0x96,
- 0x49, 0xfc, 0x61, 0xf0, 0x72, 0x44, 0x95, 0x88, 0x34, 0x2c, 0x68, 0x0d, 0x42, 0x62, 0xb2, 0x0a,
- 0x53, 0x58, 0xb1, 0x56, 0x14, 0x08, 0x66, 0x86, 0x39, 0x0a, 0xd5, 0x41, 0xb6, 0x24, 0x52, 0xd2,
- 0xfb, 0x68, 0x77, 0xac, 0x63, 0xfb, 0x60, 0xe4, 0x31, 0x24, 0xdd, 0x5d, 0x35, 0xc2, 0x64, 0x8a,
- 0xd2, 0x2f, 0xe8, 0xd4, 0x22, 0xc2, 0xcc, 0x7e, 0x7d, 0x83, 0x05, 0x58, 0x62, 0xe6, 0xc9, 0x9b,
- 0xf9, 0xd4, 0x60, 0xa2, 0x38, 0x4b, 0x6c, 0x3b, 0x50, 0xe3, 0x02, 0x4e, 0xa3, 0x7c, 0x2c, 0x7f,
- 0x50, 0xd8, 0x53, 0xa5, 0x88, 0x42, 0x4a, 0x67, 0x76, 0x94, 0x44, 0x08, 0x89, 0x23, 0x1f, 0x99,
- 0x5d, 0x53, 0xec, 0x25, 0x38, 0x73, 0x85, 0xd2, 0xe2, 0x15, 0x6a, 0xd6, 0x5d, 0x93, 0xf2, 0xca,
- 0x9d, 0x2a, 0x51, 0x39, 0xae, 0xad, 0xe4, 0xb7, 0xf2, 0x44, 0x1c, 0x1f, 0xcf, 0x98, 0xb5, 0x13,
- 0x7d, 0xa5, 0x2f, 0xf7, 0x4b, 0x14, 0xab, 0x4d, 0xa7, 0x0c, 0x6c, 0x32, 0x13, 0x86, 0xcf, 0x04,
- 0x26, 0x2d, 0xe6, 0x35, 0xef, 0x50, 0xc5, 0x48, 0x7d, 0x72, 0x08, 0x46, 0xc5, 0xa8, 0xdf, 0x0e,
- 0x54, 0xe7, 0x19, 0xd2, 0xbc, 0xbf, 0x45, 0x3b, 0x23, 0xed, 0xbb, 0xdd, 0x0d, 0x33, 0x2c, 0x92,
- 0x4d, 0x55, 0x80, 0x13, 0xaa, 0xf7, 0x0c, 0xd0, 0x2d, 0xf7, 0x65, 0xaa, 0xac, 0xa5, 0x32, 0xc1,
- 0xaa, 0xf4, 0xae, 0x79, 0xc7, 0x57, 0x32, 0xa0, 0x5e, 0xf0, 0x75, 0x87, 0x54, 0xb9, 0x42, 0x6a,
- 0xe3, 0x27, 0x52, 0xd9, 0x40, 0x01, 0x0e, 0x86, 0x70, 0x43, 0xd9, 0x47, 0x0a, 0xd4, 0x4a, 0x8a,
- 0xd4, 0xd8, 0x57, 0x65, 0x6c, 0x19, 0x5d, 0x4b, 0x87, 0x7e, 0xb3, 0x6e, 0x7c, 0xc6, 0xd6, 0x05,
- 0x56, 0xef, 0x34, 0x2c, 0x38, 0xa5, 0x4d, 0xec, 0x30, 0x8f, 0x46, 0x7b, 0x07, 0x7a, 0x6e, 0xdf,
- 0x05, 0xfe, 0xeb, 0x1d, 0xe1, 0xae, 0x9e, 0xa4, 0xbd, 0x9d, 0x51, 0x08, 0xd3, 0xf2, 0xa7, 0x3e,
- 0x68, 0x33, 0x63, 0xd6, 0x0f, 0xf0, 0xd8, 0x07, 0x4f, 0x52, 0x98, 0x43, 0xb0, 0x2e, 0x95, 0x50,
- 0x89, 0x1c, 0x1e, 0x2f, 0xb2, 0xcd, 0xbd, 0x4c, 0xbb, 0x67, 0x35, 0x86, 0x38, 0xa9, 0xd7, 0x38,
- 0xa0, 0x19, 0x9c, 0x1f, 0xfd, 0x7d, 0xde, 0x03, 0xab, 0x46, 0xec, 0xf5, 0x62, 0x22, 0xc5, 0xaa,
- 0x87, 0xd4, 0x59, 0x57, 0x1a, 0xdb, 0xd4, 0xfa, 0xe3, 0x24, 0xa7, 0x35, 0xa3, 0xf0, 0x35, 0xe6,
- 0x8b, 0x95, 0xc2, 0x84, 0xe5, 0x9a, 0x01, 0xc1, 0x1b, 0x31, 0x63, 0x32, 0xa7, 0x6b, 0xeb, 0x89,
- 0x1f, 0xab, 0xdd, 0x3f, 0xb9, 0x34, 0xda, 0x2d, 0x3b, 0x5b, 0xb4, 0xf8, 0x04, 0xc8, 0xed, 0x60,
- 0xc3, 0x2e, 0x11, 0x38, 0x8b, 0x7a, 0xcd, 0x28, 0xab, 0xee, 0x6b, 0x0c, 0xd0, 0x13, 0x2a, 0x65,
- 0xee, 0xc8, 0xfb, 0x6b, 0x87, 0xd3, 0xe5, 0x39, 0x8b, 0xf7, 0xef, 0xab, 0x46, 0xac, 0x56, 0xf9,
- 0x4d, 0xc9, 0x2d, 0xa7, 0x69, 0x8b, 0x5f, 0x8e, 0x4d, 0xa4, 0xda, 0xeb, 0x57, 0x44, 0xb2, 0xef,
- 0x97, 0xd8, 0xea, 0xed, 0x86, 0x8b, 0xdc, 0x44, 0x83, 0xcc, 0xa3, 0xdf, 0xea, 0xd8, 0xdc, 0x74,
- 0xf2, 0x8e, 0xe6, 0x65, 0x26, 0x74, 0x0a, 0x2a, 0x17, 0x11, 0xee, 0x21, 0xc5, 0x0a, 0x06, 0xbb,
- 0xc9, 0xaa, 0xee, 0x40, 0x01, 0x12, 0x86, 0x93, 0xdb, 0x90, 0x24, 0x10, 0xad, 0xbf, 0x8d, 0x19,
- 0x34, 0x0f, 0xf9, 0xe9, 0xb7, 0x7f, 0xb9, 0xab, 0x9a, 0xf3, 0x71, 0x13, 0x1d, 0x79, 0xcf, 0xe8,
- 0xe7, 0x69, 0x67, 0x0f, 0xfe, 0xea, 0x69, 0x4e, 0xb6, 0x2d, 0x36, 0x49, 0x75, 0x45, 0x7e, 0x85,
- 0xd2, 0x4c, 0x4f, 0xb3, 0xc9, 0x21, 0xed, 0xb3, 0x17, 0x33, 0xba, 0x40, 0x6f, 0x14, 0x36, 0x49,
- 0x84, 0x4b, 0xa7, 0x21, 0x2e, 0x40, 0xd4, 0xb8, 0x05, 0x3a, 0x2e, 0x4f, 0x43, 0xa5, 0x69, 0xdf,
- 0xc3, 0x2d, 0x62, 0x41, 0xec, 0x86, 0xcc, 0xd1, 0x81, 0x93, 0x03, 0xb4, 0x5e, 0x2a, 0xed, 0xfa,
- 0x77, 0xa4, 0x4e, 0xdd, 0x71, 0xce, 0x7a, 0xe4, 0x45, 0x56, 0x48, 0x08, 0x1b, 0x13, 0xef, 0xc2,
- 0x19, 0x53, 0x69, 0xb4, 0xf6, 0xd8, 0x95, 0x9b, 0x46, 0x9d, 0x04, 0x23, 0xbd, 0x9a, 0xf0, 0xe9,
- 0x31, 0xe2, 0xa4, 0x93, 0x6b, 0xed, 0xe2, 0x22, 0x81, 0x6e, 0xdb, 0x5e, 0x1a, 0xe9, 0x9a, 0x58,
- 0xcb, 0xa7, 0x86, 0x73, 0x3d, 0x5b, 0xed, 0xc4, 0x44, 0x83, 0x4c, 0x0e, 0x9b, 0x8e, 0x82, 0x5d,
- 0x5e, 0xae, 0x2a, 0xf5, 0x5b, 0xe5, 0x91, 0xef, 0x53, 0xd9, 0x7e, 0x93, 0xe5, 0x66, 0x9a, 0x63,
- 0x78, 0x78, 0x58, 0x8a, 0x63, 0x5f, 0x8c, 0xf6, 0x8a, 0xd9, 0x2d, 0xaa, 0xbe, 0x67, 0x56, 0x67,
- 0x20, 0x9d, 0x39, 0xfd, 0x4c, 0xae, 0xd3, 0x70, 0x86, 0x7e, 0x20, 0x78, 0x6d, 0xe2, 0x44, 0x13,
- 0x90, 0x62, 0x7f, 0x02, 0xcc, 0xde, 0x97, 0xf4, 0x4e, 0x76, 0xb5, 0xd2, 0xb4, 0x4d, 0x9b, 0x74,
- 0x8a, 0xb4, 0x80, 0x83, 0x40, 0xc2, 0x94, 0x02, 0x9a, 0x71, 0xe0, 0x79, 0x3d, 0x77, 0xb5, 0x3d,
- 0xb2, 0xea, 0x12, 0x98, 0x05, 0x47, 0x1d, 0x5c, 0x79, 0x94, 0xdc, 0x55, 0xa7, 0x6f, 0x30, 0x7f,
- 0x83, 0x50, 0xd1, 0x95, 0x21, 0x87, 0x0b, 0x89, 0x86, 0x15, 0x25, 0x35, 0x74, 0xcd, 0x1d, 0x38,
- 0x48, 0x2a, 0xcf, 0xb3, 0x97, 0xbc, 0x2b, 0xb7, 0xab, 0x10, 0x8d, 0x17, 0x5d, 0xef, 0xad, 0xf2,
- 0xe3, 0x1b, 0x56, 0x23, 0x8d, 0x2c, 0x33, 0x59, 0x3a, 0x99, 0x86, 0x6e, 0xd6, 0xcb, 0xc5, 0x8c,
- 0x43, 0x1b, 0x5e, 0x26, 0x88, 0xf1, 0x3e, 0xf8, 0x3e, 0xa7, 0xb9, 0xc6, 0xb5, 0xac, 0x3b, 0xb7,
- 0x38, 0x0d, 0xb2, 0xc5, 0x15, 0xb4, 0x55, 0x97, 0xc3, 0x14, 0x0c, 0x19, 0x93, 0x21, 0xba, 0xb9,
- 0xd6, 0x1f, 0x28, 0x8b, 0x87, 0xfe, 0x20, 0x21, 0x08, 0xfb, 0x32, 0x16, 0xf7, 0xa4, 0xa7, 0x30,
- 0x6a, 0x02, 0xd5, 0x67, 0xf6, 0xff, 0x37, 0xee, 0xd7, 0x1b, 0x34, 0x6f, 0x0b, 0xc2, 0x94, 0x91,
- 0xa6, 0x78, 0x50, 0xf2, 0x9e, 0x58, 0x44, 0x11, 0xe4, 0x8b, 0x23, 0x3c, 0xe6, 0xa2, 0x8c, 0x1e,
- 0x96, 0xdf, 0x41, 0x11, 0x47, 0x89, 0x2a, 0x2a, 0xe4, 0xc8, 0xd2, 0x12, 0x98, 0xb0, 0x37, 0x02,
- 0xf6, 0xa6, 0x3b, 0xa1, 0xf3, 0x30, 0x9c, 0xda, 0x35, 0x0c, 0xef, 0xc2, 0x36, 0xaf, 0xb7, 0x2c,
- 0xe9, 0xf6, 0x64, 0x0d, 0x05, 0x84, 0xf6, 0x8d, 0x61, 0xeb, 0xda, 0x36, 0x05, 0x42, 0x56, 0xde,
- 0xfe, 0x36, 0x7c, 0x42, 0x1c, 0x5e, 0xfb, 0x9b, 0xe2, 0x22, 0xcc, 0x42, 0xff, 0xb1, 0xe6, 0xfd,
- 0x02, 0x4a, 0x1c, 0x44, 0xa8, 0x78, 0x87, 0xc5, 0x58, 0xed, 0x55, 0x0f, 0x29, 0x3b, 0x50, 0xf8,
- 0x93, 0x05, 0xa5, 0x3c, 0x1a, 0xd5, 0x7c, 0xcd, 0x5f, 0xab, 0x8a, 0x95, 0xb0, 0x65, 0x86, 0x86,
- 0x3d, 0x8c, 0x05, 0x21, 0x46, 0xfa, 0xf7, 0x7a, 0x2a, 0xa6, 0x09, 0x0f, 0xf4, 0xaa, 0x2d, 0x3d,
- 0xf9, 0x63, 0x66, 0x22, 0x9b, 0xc7, 0x74, 0x3f, 0xbc, 0x97, 0x58, 0xbb, 0x41, 0x02, 0x60, 0xd1,
- 0xe2, 0xfe, 0x26, 0x22, 0x91, 0x76, 0x44, 0xce, 0x94, 0x2c, 0xd1, 0x13, 0x56, 0x06, 0xc0, 0xa4,
- 0xc4, 0x36, 0xe9, 0x84, 0x78, 0xa0, 0xc6, 0x02, 0x97, 0xa5, 0x27, 0xd4, 0x9e, 0x78, 0x51, 0xca,
- 0x7e, 0x55, 0x94, 0xcd, 0xf3, 0x64, 0xe9, 0x0f, 0xf5, 0x37, 0xe6, 0x15, 0x09, 0xed, 0x72, 0xd2,
- 0x25, 0xd6, 0xf2, 0xde, 0x93, 0xbc, 0xc3, 0x7c, 0x27, 0x63, 0x5e, 0x50, 0x2b, 0xf4, 0x17, 0xd0,
- 0x09, 0x3a, 0xca, 0xb5, 0xad, 0x92, 0xf8, 0x9a, 0x52, 0x5d, 0x74, 0x24, 0x6a, 0x3b, 0x59, 0x2a,
- 0x88, 0x17, 0xc7, 0xee, 0x78, 0xfb, 0x78, 0x06, 0x16, 0x6a, 0xad, 0x0b, 0xa5, 0x9c, 0xab, 0x5c,
- 0x78, 0x3a, 0xc5, 0x7d, 0x9e, 0x1e, 0xb7, 0x82, 0x57, 0x6f, 0xe5, 0xd0, 0x43, 0x2d, 0x71, 0x20,
- 0xd7, 0x16, 0x54, 0x59, 0x75, 0x15, 0x8f, 0x47, 0x90, 0x31, 0xb9, 0x9a, 0x0d, 0x85, 0x7d, 0x01,
- 0x58, 0x67, 0x40, 0x07, 0xec, 0x72, 0xaf, 0x41, 0x01, 0x3e, 0x61, 0x0c, 0xe4, 0x12, 0x1c, 0x30,
- 0xd3, 0x37, 0xf7, 0xdf, 0xf4, 0x2e, 0xa0, 0x62, 0xd5, 0xba, 0x1c, 0xc9, 0x70, 0x31, 0x2e, 0x10,
- 0xa9, 0xf0, 0x31, 0x53, 0x69, 0xea, 0x2b, 0xbc, 0xbe, 0x5d, 0xbb, 0xa7, 0xdf, 0x62, 0xf0, 0x28,
- 0x18, 0x66, 0xa6, 0xd3, 0x74, 0x86, 0x11, 0x4c, 0x6e, 0x57, 0xdd, 0x0c, 0x86, 0xc2, 0xa5, 0x3b,
- 0x0f, 0x92, 0x19, 0x24, 0x90, 0x82, 0xdd, 0xc5, 0x48, 0xdb, 0x72, 0xb8, 0xda, 0x38, 0x95, 0xa8,
- 0xa0, 0x80, 0xe2, 0x4e, 0x93, 0x44, 0xb8, 0x4f, 0xe9, 0xc1, 0xd9, 0x2c, 0x90, 0x4e, 0xed, 0x6f,
- 0x9d, 0x3e, 0x7b, 0x66, 0x53, 0xa9, 0xd3, 0xc5, 0x18, 0x95, 0x05, 0xbe, 0xfe, 0xbd, 0xee, 0xb6,
- 0x2a, 0x1e, 0x29, 0x23, 0xff, 0x44, 0x6b, 0x02, 0x3c, 0xbe, 0xac, 0x12, 0x1f, 0xed, 0x0d, 0x3b,
- 0x3b, 0xc9, 0x3e, 0x84, 0xa7, 0x3c, 0x00, 0x0d, 0x15, 0x07, 0x83, 0xa1, 0x7f, 0x4f, 0xc1, 0x13,
- 0x51, 0x67, 0x1e, 0x7c, 0xf8, 0xe2, 0xac, 0xb4, 0xd1, 0x49, 0x78, 0xd4, 0x01, 0xb1, 0x55, 0xba,
- 0xa5, 0xa4, 0xf8, 0x85, 0x95, 0x7f, 0xf6, 0x4d, 0xda, 0xd3, 0x44, 0x46, 0xfd, 0xac, 0xa5, 0xc1,
- 0xd5, 0xfc, 0x87, 0xea, 0x9e, 0xdd, 0xbe, 0xf5, 0x52, 0x58, 0xed, 0xfd, 0xde, 0x80, 0x3a, 0x07,
- 0x77, 0x05, 0xcd, 0xd8, 0x29, 0x4e, 0x28, 0x22, 0x66, 0x39, 0x17, 0xcd, 0x56, 0x6b, 0x52, 0x6c,
- 0x1c, 0xe8, 0x22, 0x74, 0xa2, 0xcf, 0xc8, 0x72, 0x11, 0x36, 0x4f, 0xe1, 0xf6, 0x52, 0x31, 0xfb,
- 0x8b, 0x06, 0x11, 0xf7, 0x89, 0xb9, 0x96, 0x9b, 0x1c, 0x99, 0x7a, 0xd4, 0xa0, 0x8f, 0x2c, 0x26,
- 0x62, 0xe7, 0x4e, 0xaf, 0x0e, 0xbd, 0xc3, 0xce, 0x2e, 0x67, 0xd1, 0x86, 0x3b, 0xe9, 0xc4, 0x39,
- 0x75, 0x5e, 0xbd, 0x0a, 0x06, 0xac, 0xd9, 0x0d, 0xe4, 0xb0, 0x86, 0xaa, 0x1f, 0xb7, 0x9a, 0x26,
- 0x7a, 0xac, 0x5b, 0x38, 0x30, 0x6e, 0x4e, 0xb9, 0xe3, 0xa6, 0x23, 0xe1, 0xa4, 0x73, 0x1d, 0x50,
- 0xcc, 0x1c, 0xef, 0xe6, 0x73, 0xf7, 0x8b, 0xeb, 0xbe, 0x69, 0x81, 0xeb, 0x74, 0x87, 0x68, 0x4e,
- 0x4a, 0x2b, 0xfc, 0xa0, 0x0b, 0x30, 0x6d, 0x5e, 0x81, 0xe2, 0xd9, 0xa6, 0xba, 0x1e, 0x5b, 0x09,
- 0x2e, 0xe3, 0x67, 0x0d, 0x75, 0x65, 0x76, 0x5c, 0x61, 0xf4, 0x19, 0xd8, 0x6d, 0xfa, 0xfe, 0xa6,
- 0x11, 0x1a, 0xaf, 0xca, 0x1c, 0xff, 0x74, 0xe7, 0x85, 0xb3, 0x3d, 0xb9, 0x67, 0x7c, 0xf7, 0x16,
- 0xf8, 0xf6, 0x6b, 0xac, 0xb8, 0x85, 0x7c, 0x1e, 0x02, 0x53, 0x67, 0xac, 0x29, 0xd2, 0x72, 0x97,
- 0x91, 0x43, 0x81, 0xc2, 0xde, 0xc6, 0x41, 0x3c, 0x96, 0xd6, 0xdf, 0x19, 0x3e, 0x18, 0x2e, 0xbf,
- 0xcb, 0xb4, 0xec, 0x20, 0xd8, 0xa7, 0x48, 0x46, 0x62, 0x9d, 0x44, 0x23, 0x0e, 0x72, 0x3b, 0xec,
- 0x4e, 0x7d, 0x2e, 0x92, 0x71, 0xd7, 0xa8, 0x4b, 0x3c, 0x6c, 0x39, 0x72, 0xb0, 0xc2, 0x97, 0x67,
- 0xde, 0x80, 0x30, 0x0a, 0x36, 0x49, 0xe2, 0x31, 0xa3, 0x70, 0x7d, 0xe3, 0x28, 0xf7, 0xa5, 0xe6,
- 0xb0, 0xe4, 0xc6, 0x65, 0x43, 0xd3, 0x12, 0x77, 0xa4, 0x1a, 0x92, 0xa6, 0x1c, 0xd7, 0x7d, 0x6d,
- 0xc9, 0x49, 0xdb, 0x55, 0x45, 0xf4, 0xae, 0x67, 0x69, 0xc1, 0xf0, 0xe4, 0xa4, 0x3e, 0x18, 0xae,
- 0x08, 0x18, 0xc0, 0xf8, 0xa6, 0x87, 0xa8, 0x71, 0xa9, 0xd2, 0x12, 0x3c, 0xa3, 0xd8, 0x9f, 0xe2,
- 0x28, 0x30, 0x46, 0xb7, 0x92, 0x33, 0x2d, 0x4b, 0x1a, 0xc7, 0x3e, 0x1f, 0x19, 0x66, 0xd8, 0xd5,
- 0x03, 0x34, 0x39, 0x6b, 0xe5, 0x0e, 0xea, 0x0d, 0x90, 0xba, 0x26, 0xbd, 0x53, 0xc3, 0x44, 0xe7,
- 0x6c, 0x51, 0x38, 0xc4, 0x73, 0x85, 0xa6, 0x10, 0xa8, 0x36, 0xbe, 0x75, 0x26, 0xe2, 0xfd, 0xd0,
- 0x59, 0x8d, 0xf7, 0xb5, 0x81, 0xcd, 0x2b, 0x25, 0x16, 0x7c, 0x0b, 0x5f, 0x24, 0x07, 0x9b, 0x77,
- 0x45, 0x63, 0x5a, 0x15, 0x62, 0xaa, 0xa1, 0x44, 0x66, 0x72, 0xda, 0x35, 0x94, 0x6a, 0xe6, 0xa8,
- 0x69, 0xcd, 0xe0, 0x64, 0x6b, 0xde, 0xbb, 0xde, 0xae, 0x82, 0x89, 0x36, 0x16, 0xf0, 0x13, 0x41,
- 0xa7, 0x42, 0x2e, 0xaf, 0x8a, 0xed, 0x22, 0xd2, 0xc6, 0x91, 0x5f, 0x2a, 0x25, 0x06, 0x52, 0x03,
- 0xc5, 0xcb, 0x78, 0xe4, 0x7a, 0xef, 0x1c, 0xb3, 0x3f, 0xbc, 0xfa, 0x29, 0xfc, 0xc6, 0x73, 0x68,
- 0x9e, 0x80, 0x0c, 0xc2, 0xfa, 0x11, 0xdc, 0xde, 0xa0, 0x8f, 0x5b, 0x53, 0x80, 0xcd, 0x4e, 0x4c,
- 0xd2, 0x15, 0x40, 0xa4, 0x18, 0x4e, 0x70, 0xf7, 0x0c, 0xc5, 0xe8, 0xc4, 0xbd, 0x6f, 0xc4, 0x46,
- 0x12, 0x45, 0xfe, 0xa8, 0x11, 0xd0, 0xd1, 0x4c, 0x1a, 0x99, 0x99, 0xf1, 0x3c, 0xdc, 0xb5, 0x8a,
- 0xef, 0xa6, 0x22, 0xd4, 0x9e, 0x75, 0x3f, 0x37, 0x73, 0x3c, 0x62, 0xb3, 0xc3, 0xa5, 0x87, 0xdd,
- 0xc2, 0x96, 0x8b, 0x02, 0xf1, 0x10, 0xf8, 0xed, 0x8b, 0x56, 0x29, 0x5b, 0xdc, 0x67, 0xbf, 0x39,
- 0x8d, 0x01, 0xc8, 0x8a, 0x89, 0x2e, 0xf2, 0x05, 0x43, 0xf6, 0x2b, 0x9b, 0x4e, 0xca, 0xd4, 0xca,
- 0x4c, 0xf8, 0xc1, 0xf7, 0xc2, 0x4a, 0x55, 0x87, 0xc0, 0xb4, 0xd4, 0xc6, 0xdf, 0xc5, 0xaf, 0xc0,
- 0x23, 0x90, 0x6f, 0x93, 0x25, 0x17, 0x52, 0xa2, 0xed, 0x90, 0x14, 0x8f, 0xdc, 0x74, 0xb1, 0x71,
- 0x3c, 0xaa, 0xfb, 0x60, 0x76, 0xd6, 0xc8, 0x17, 0x15, 0x5e, 0xae, 0xa3, 0xb7, 0xdd, 0x2e, 0x10,
- 0xe9, 0x3d, 0x33, 0x00, 0x7a, 0xd4, 0x8f, 0xda, 0x3a, 0x03, 0xeb, 0x2e, 0x01, 0x7c, 0xf8, 0xed,
- 0x50, 0x01, 0x65, 0x29, 0x94, 0x77, 0xf8, 0x97, 0x20, 0xca, 0xa2, 0xa9, 0x6a, 0xee, 0xbf, 0x4e,
- 0x74, 0x52, 0x5f, 0x5f, 0xc4, 0xc1, 0xb7, 0x43, 0x4c, 0x06, 0xd0, 0x2b, 0x77, 0x9a, 0x82, 0x01,
- 0x3b, 0x5a, 0x15, 0x6a, 0x40, 0x99, 0x50, 0xdb, 0x0c, 0x95, 0xa4, 0x97, 0xbf, 0x8a, 0x63, 0xd2,
- 0xd8, 0x06, 0xf1, 0x2c, 0xe0, 0x5a, 0xe2, 0x0e, 0x9a, 0xca, 0x1a, 0x9f, 0x71, 0xe1, 0x41, 0x86,
- 0x92, 0xd2, 0x0d, 0x6c, 0x40, 0xa9, 0x0b, 0xd9, 0x33, 0x0d, 0xaf, 0x6c, 0xdb, 0x69, 0xeb, 0x26,
- 0x8e, 0x29, 0xb3, 0xd0, 0x9f, 0x9c, 0xce, 0xb8, 0x95, 0x2f, 0xd0, 0x2b, 0x56, 0x94, 0xf1, 0xe7,
- 0x46, 0xff, 0x88, 0xd1, 0x93, 0x65, 0x79, 0x92, 0x57, 0x62, 0x12, 0x1d, 0x82, 0x4f, 0x80, 0xef,
- 0x98, 0x45, 0x09, 0xea, 0x7d, 0x04, 0xf1, 0xce, 0x03, 0xe3, 0x6a, 0x22, 0xdd, 0x3b, 0x80, 0x95,
- 0x87, 0x7e, 0x8b, 0xfc, 0xd8, 0xf6, 0x32, 0xeb, 0x45, 0xd8, 0x7d, 0xeb, 0x81, 0x11, 0xcb, 0x5d,
- 0x10, 0x35, 0x6b, 0xbe, 0x9c, 0x01, 0x7c, 0xfb, 0xb5, 0xc6, 0xb5, 0x9c, 0x87, 0x1b, 0xd9, 0xe0,
- 0xe4, 0x45, 0x67, 0xca, 0xd8, 0xf9, 0x18, 0x05, 0xea, 0x48, 0x8b, 0x45, 0x19, 0x03, 0xda, 0x5b,
- 0x68, 0x45, 0x23, 0xaf, 0xf7, 0xce, 0xae, 0x4e, 0xd8, 0xf8, 0xd3, 0x7c, 0xde, 0x41, 0x61, 0x01,
- 0xbe, 0xcf, 0x2b, 0x11, 0x6c, 0x40, 0xb3, 0x50, 0x0e, 0x77, 0xf5, 0xd8, 0x59, 0xac, 0x18, 0x95,
- 0xb5, 0x92, 0xa1, 0xce, 0x5c, 0x4b, 0xe5, 0xd2, 0x95, 0xef, 0xf4, 0x31, 0x6d, 0x45, 0x50, 0xe1,
- 0xbf, 0x43, 0x24, 0xbb, 0xe5, 0xb7, 0x1e, 0x92, 0x25, 0x7b, 0x39, 0x1d, 0x34, 0xd1, 0xdd, 0xf5,
- 0x25, 0xb8, 0x4b, 0x4e, 0x1e, 0xe5, 0xce, 0xb1, 0xb2, 0x5b, 0x8e, 0x7e, 0xbf, 0xad, 0xae, 0x61,
- 0xf9, 0xdc, 0xc1, 0xc7, 0x92, 0x86, 0xea, 0x2d, 0x2a, 0x1c, 0x07, 0xad, 0x94, 0xf2, 0x15, 0x6d,
- 0x61, 0xb0, 0xf1, 0xe8, 0x23, 0xdf, 0x0b, 0x79, 0x7b, 0x43, 0xda, 0x88, 0x74, 0xd4, 0xaf, 0x37,
- 0x16, 0xdb, 0x81, 0x1b, 0xf8, 0x0f, 0x3b, 0x7b, 0x2a, 0x0b, 0xbe, 0x7c, 0xd0, 0x92, 0x8c, 0x43,
- 0xc8, 0x95, 0xf8, 0x7f, 0xc0, 0x2a, 0x6d, 0xf5, 0xbc, 0xaf, 0x2e, 0x7f, 0xdb, 0xa2, 0xfe, 0x37,
- 0xc6, 0xe1, 0x6b, 0x8a, 0x38, 0xea, 0x60, 0x94, 0x2f, 0xb7, 0xdd, 0x14, 0x5a, 0x9a, 0xf6, 0x21,
- 0xda, 0x30, 0xbe, 0x1f, 0xe4, 0xa2, 0xc1, 0x3b, 0xfa, 0x5d, 0x98, 0xf3, 0x56, 0x7f, 0xe8, 0xb2,
- 0x33, 0x25, 0xce, 0xff, 0x64, 0xeb, 0xd8, 0x4c, 0xb9, 0x0c, 0x5d, 0xae, 0xc8, 0x43, 0x8e, 0x4c,
- 0x4c, 0x09, 0x7a, 0x42, 0x06, 0xe0, 0x04, 0xcc, 0x09, 0xe5, 0x68, 0x1a, 0x55, 0x5c, 0xfc, 0x15,
- 0x86, 0xe3, 0xe7, 0xf2, 0xb6, 0x15, 0x31, 0x56, 0xaf, 0xa7, 0x13, 0x35, 0x90, 0xe7, 0xec, 0xfa,
- 0x82, 0xea, 0x54, 0x22, 0xfc, 0x08, 0x1a, 0xb0, 0x55, 0xf3, 0x75, 0x08, 0x94, 0x33, 0x08, 0x6f,
- 0xfd, 0x1d, 0x69, 0x8c, 0x63, 0xb3, 0x4a, 0xd5, 0x50, 0xe9, 0xca, 0xeb, 0x42, 0xf1, 0x7c, 0x39,
- 0x1c, 0xcd, 0x95, 0x0a, 0xd3, 0xa0, 0xcd, 0xed, 0x43, 0x35, 0x05, 0x3e, 0x35, 0x21, 0x01, 0x6d,
- 0x23, 0x11, 0xd7, 0x49, 0xdb, 0xf2, 0xb7, 0xbe, 0x33, 0x38, 0x85, 0x74, 0xa6, 0x2c, 0x0b, 0x17,
- 0x4e, 0xd4, 0x12, 0x0d, 0xcb, 0xd7, 0x91, 0xad, 0x4f, 0xab, 0x53, 0x43, 0x50, 0x10, 0xf7, 0xc3,
- 0x02, 0x4e, 0xe8, 0x72, 0xef, 0x00, 0xd2, 0x9a, 0xd7, 0x9e, 0x3f, 0x2b, 0x33, 0x6a, 0x71, 0xc4,
- 0x6b, 0x21, 0x10, 0x1a, 0x0b, 0x8e, 0xe8, 0xcb, 0x34, 0x07, 0xa9, 0xf4, 0xb2, 0x55, 0x0b, 0x44,
- 0x35, 0x08, 0xbd, 0x21, 0xe6, 0x7a, 0x6f, 0xd2, 0xda, 0xc0, 0x09, 0x04, 0xda, 0xeb, 0x99, 0x35,
- 0x0c, 0xd4, 0x5f, 0xca, 0x32, 0x4f, 0xad, 0x5c, 0xe3, 0x1c, 0x4b, 0x10, 0x48, 0xf7, 0xa7, 0x1d,
- 0x30, 0xa2, 0x5b, 0xba, 0x2c, 0x36, 0x77, 0x99, 0x15, 0x18, 0xe2, 0xe0, 0x14, 0x30, 0x77, 0xb1,
- 0xed, 0xee, 0x1f, 0x28, 0x91, 0xf8, 0x55, 0xbe, 0xd7, 0xe4, 0x76, 0x04, 0x5f, 0x6b, 0xbb, 0xbf,
- 0xfe, 0xfe, 0xec, 0x70, 0x54, 0xaf, 0xf2, 0x8f, 0x69, 0x93, 0x1a, 0x5d, 0x0e, 0xf0, 0xd6, 0x30,
- 0x71, 0xa6, 0xdd, 0x20, 0x3b, 0x9f, 0xa7, 0xac, 0xe7, 0x83, 0xe9, 0x7b, 0x41, 0x9f, 0x82, 0xd9,
- 0xe2, 0x50, 0x65, 0xe1, 0x2a, 0x1c, 0xee, 0x8d, 0x84, 0xc9, 0xe8, 0x08, 0x0e, 0x0a, 0x33, 0x01,
- 0xd3, 0x76, 0x54, 0x99, 0x16, 0x2d, 0x72, 0xfd, 0x69, 0xf4, 0xe1, 0xd3, 0xd6, 0xf3, 0xa4, 0x8f,
- 0xc7, 0xb7, 0x2b, 0x59, 0x23, 0xcb, 0xf3, 0x1a, 0xe1, 0xad, 0x8b, 0x48, 0xc0, 0x39, 0x38, 0xae,
- 0x84, 0xc6, 0x75, 0xa6, 0x04, 0x2b, 0x29, 0xc1, 0xc3, 0x2a, 0x4f, 0x05, 0x1f, 0xb0, 0xa7, 0x0c,
- 0x6a, 0xe2, 0xec, 0x44, 0x44, 0x35, 0x39, 0xbc, 0x16, 0x82, 0x52, 0xcc, 0x92, 0xe9, 0x4b, 0x16,
- 0x23, 0x6a, 0xcc, 0x1d, 0xfe, 0xd1, 0xc4, 0xd7, 0xe6, 0x26, 0xd1, 0xa8, 0x4d, 0x3c, 0x8f, 0x9d,
- 0x6c, 0xab, 0xb3, 0x79, 0x09, 0xd6, 0xd4, 0x31, 0xc4, 0x1c, 0xd7, 0x4a, 0xda, 0x46, 0x43, 0xa4,
- 0x16, 0x21, 0xff, 0xc9, 0x43, 0xe5, 0x27, 0x4f, 0x32, 0x05, 0x0b, 0x03, 0x76, 0x36, 0x7a, 0xf6,
- 0x8a, 0x90, 0x20, 0xfa, 0xaa, 0x69, 0x2d, 0x0a, 0x49, 0x87, 0xfc, 0xf1, 0xb2, 0x2c, 0xf2, 0xba,
- 0xeb, 0xaa, 0x61, 0xed, 0x35, 0x18, 0xa4, 0x41, 0x4a, 0xf7, 0x89, 0x45, 0xc2, 0xdf, 0x80, 0x44,
- 0x8a, 0xcb, 0x49, 0xef, 0x61, 0x5e, 0xa6, 0x22, 0x2c, 0x55, 0x77, 0x0e, 0xe0, 0xfc, 0x35, 0xc3,
- 0x56, 0xdb, 0xe0, 0x19, 0xe2, 0xe1, 0xb0, 0xe3, 0x39, 0xa1, 0xc4, 0xcc, 0xa4, 0xdf, 0xca, 0xd2,
- 0x75, 0x9d, 0x99, 0x41, 0xc3, 0x98, 0xfd, 0xd8, 0x19, 0x20, 0x51, 0x37, 0xec, 0x8d, 0x74, 0x13,
- 0x0f, 0x42, 0x11, 0x75, 0x68, 0x58, 0x65, 0xcd, 0xbf, 0xfc, 0x16, 0xea, 0x37, 0xd6, 0x56, 0x59,
- 0xc3, 0x69, 0x4d, 0x49, 0x4d, 0x7c, 0x98, 0xaf, 0x85, 0x93, 0x8e, 0x2a, 0xea, 0x86, 0x19, 0x0c,
- 0x64, 0x2d, 0xc5, 0x79, 0xd8, 0xbd, 0xdc, 0x91, 0x53, 0x3c, 0x48, 0x41, 0xad, 0xd8, 0xdd, 0x09,
- 0x2e, 0xfd, 0x32, 0x71, 0xe3, 0xd7, 0x81, 0x26, 0x34, 0xeb, 0xc8, 0x5c, 0x68, 0x67, 0xd4, 0x5e,
- 0x1f, 0x47, 0xbc, 0xd5, 0x96, 0x72, 0x6a, 0xfb, 0x23, 0x3a, 0xbd, 0xdc, 0x32, 0x09, 0x61, 0x0a,
- 0xb1, 0xbf, 0x02, 0x51, 0x1b, 0x24, 0xe7, 0x4d, 0x27, 0xd3, 0x38, 0x1e, 0x7a, 0x76, 0x2c, 0xbe,
- 0xdc, 0x11, 0x8f, 0x6a, 0x82, 0x6e, 0xf5, 0x55, 0xf7, 0xf7, 0x8e, 0x2c, 0x5d, 0xa1, 0x52, 0xe5,
- 0xb0, 0x3e, 0xaa, 0x39, 0xa1, 0x04, 0xf1, 0x09, 0xec, 0xa6, 0x34, 0x1c, 0xaa, 0xaa, 0x3a, 0xdf,
- 0xad, 0x65, 0xce, 0x2f, 0x19, 0x30, 0x34, 0x38, 0x44, 0x7c, 0xd6, 0x4d, 0x46, 0x8a, 0xd6, 0xcd,
- 0xd0, 0xcd, 0x36, 0xb2, 0x28, 0xa2, 0x44, 0xe9, 0xda, 0x1c, 0xa5, 0xd5, 0xa6, 0x90, 0x48, 0xf6,
- 0xf4, 0xad, 0x4b, 0x02, 0x89, 0x81, 0xcc, 0x90, 0x57, 0x0c, 0x0c, 0xf5, 0x28, 0xf5, 0xfc, 0xca,
- 0x66, 0x5b, 0x61, 0x2c, 0x7c, 0x3e, 0x3d, 0x2e, 0x35, 0x9f, 0xc2, 0xb1, 0x72, 0x77, 0x7b, 0x3b,
- 0x00, 0x15, 0x51, 0x59, 0xd5, 0xc8, 0x21, 0x5c, 0x36, 0xf0, 0xa2, 0x9d, 0xdb, 0xd9, 0x8b, 0xef,
- 0x95, 0xbd, 0x9b, 0x0e, 0x4a, 0xb7, 0xfd, 0x27, 0xe1, 0x36, 0xab, 0x02, 0x07, 0x5e, 0xba, 0x55,
- 0x26, 0x02, 0xc3, 0xd6, 0xde, 0xfd, 0x15, 0x5f, 0xef, 0x10, 0x5a, 0x93, 0x3e, 0x68, 0x5f, 0x19,
- 0xbd, 0x8e, 0x6a, 0x4b, 0x7f, 0x82, 0x93, 0x62, 0x42, 0x8d, 0x0e, 0x7c, 0x42, 0x98, 0x2d, 0x48,
- 0x8e, 0x02, 0x40, 0xa7, 0xa1, 0xc0, 0x0b, 0x7a, 0xe0, 0x79, 0x65, 0x8c, 0x02, 0xa7, 0x3e, 0x4e,
- 0x1d, 0xca, 0x14, 0x8d, 0x1b, 0xde, 0x0a, 0x80, 0xc4, 0x0c, 0xef, 0xeb, 0x05, 0xa0, 0x18, 0x05,
- 0x83, 0xa5, 0x3d, 0xd8, 0x19, 0xd3, 0x36, 0xa3, 0x8d, 0x96, 0xbe, 0x2a, 0xa4, 0x6e, 0x7a, 0x78,
- 0xa1, 0xb9, 0x1c, 0x44, 0xaf, 0x62, 0x7d, 0x1b, 0x32, 0xd0, 0x81, 0x06, 0x9c, 0x98, 0x3c, 0x4f,
- 0x87, 0x34, 0x05, 0x11, 0xb4, 0x86, 0x6e, 0x73, 0x63, 0xb1, 0xe0, 0x8c, 0x2a, 0x4d, 0xb0, 0xec,
- 0x7b, 0xba, 0x19, 0x0b, 0x61, 0x1d, 0xa4, 0xa6, 0xd8, 0x53, 0xcf, 0x0b, 0x97, 0xf4, 0x55, 0xca,
- 0x02, 0xbf, 0x8a, 0x3d, 0xb7, 0x4d, 0x32, 0x61, 0xbc, 0xee, 0x2b, 0x86, 0x67, 0xc1, 0x15, 0x10,
- 0xcf, 0xbd, 0x62, 0x69, 0xca, 0x9f, 0xe5, 0xcb, 0x18, 0xd4, 0x2d, 0xd5, 0xd9, 0x03, 0x44, 0x1f,
- 0xa3, 0xdb, 0x71, 0x2c, 0x74, 0x14, 0x06, 0x52, 0x9e, 0xf8, 0x4b, 0x35, 0x78, 0xe4, 0x27, 0xf2,
- 0x60, 0x22, 0x31, 0x80, 0x3b, 0xd7, 0x95, 0xa2, 0xc4, 0x89, 0xfb, 0x0b, 0x23, 0xf0, 0x4c, 0x48,
- 0x5e, 0x19, 0x92, 0x35, 0x3c, 0x58, 0x47, 0x55, 0x35, 0x31, 0x31, 0x2f, 0x96, 0x6f, 0xa8, 0xe9,
- 0x66, 0x78, 0x8b, 0x0f, 0x7e, 0x7e, 0xcd, 0x75, 0x85, 0x34, 0x67, 0xb1, 0xcf, 0x47, 0x3d, 0x39,
- 0x2a, 0x3f, 0x40, 0x6c, 0x40, 0x03, 0xa8, 0xd9, 0x73, 0xc0, 0xc9, 0xa9, 0x06, 0xb0, 0x57, 0x98,
- 0xd7, 0xab, 0xaf, 0x4c, 0xa0, 0x28, 0x4a, 0x09, 0xe3, 0x21, 0xd6, 0xa3, 0x7b, 0x9e, 0xae, 0x69,
- 0x72, 0x42, 0xd8, 0xac, 0xe7, 0x20, 0x57, 0x82, 0x42, 0xd0, 0xb8, 0x05, 0x7d, 0xb3, 0xb1, 0x57,
- 0x0a, 0x60, 0xa2, 0xa0, 0x42, 0x2e, 0x18, 0x84, 0x29, 0xc7, 0xdc, 0xfb, 0x34, 0x7f, 0x41, 0xc8,
- 0x29, 0x31, 0xe5, 0x00, 0x1c, 0x11, 0x23, 0x30, 0x84, 0xd4, 0x8e, 0xf4, 0x24, 0xfb, 0x51, 0xb6,
- 0x33, 0xac, 0x37, 0x4d, 0x42, 0xa5, 0x18, 0x05, 0x79, 0x61, 0x19, 0xeb, 0xc0, 0x1f, 0x62, 0x79,
- 0x7e, 0x1c, 0xf0, 0xa2, 0x72, 0x5a, 0xaf, 0x90, 0xe5, 0x14, 0x90, 0xb3, 0xe7, 0x6a, 0x29, 0xde,
- 0xe3, 0x0a, 0xc3, 0x8e, 0x3d, 0x5d, 0x7a, 0xab, 0x5e, 0x04, 0xa1, 0xda, 0x73, 0xde, 0x24, 0x04,
- 0xe0, 0x92, 0xe5, 0x40, 0x46, 0x6e, 0x0c, 0xec, 0xd0, 0x1d, 0xf9, 0x45, 0x12, 0xb5, 0xf3, 0x23,
- 0x0c, 0xd7, 0x3a, 0x5c, 0xbb, 0x72, 0x57, 0x32, 0x7c, 0x3b, 0x94, 0x67, 0x80, 0x2e, 0x5b, 0xbc,
- 0x61, 0x15, 0x6f, 0xa0, 0x5b, 0xcb, 0xef, 0x91, 0x46, 0xcf, 0xd5, 0x35, 0xf0, 0x2e, 0x9e, 0xc6,
- 0x9b, 0x93, 0x6d, 0x52, 0xf3, 0xa1, 0xf6, 0x70, 0x04, 0xd7, 0x9d, 0x81, 0xad, 0xb6, 0x9c, 0x67,
- 0x26, 0x28, 0x4e, 0x79, 0x12, 0xac, 0x72, 0x2f, 0x38, 0xe8, 0xe2, 0x9e, 0xcb, 0xca, 0x47, 0xc5,
- 0x0f, 0xc5, 0x5e, 0x7e, 0x67, 0xd9, 0x0a, 0xa8, 0xda, 0x3b, 0xaf, 0xed, 0x2d, 0x77, 0xf5, 0x48,
- 0xc6, 0x32, 0x96, 0x2a, 0xf2, 0x71, 0x65, 0x90, 0x82, 0xae, 0xe6, 0xf3, 0x2b, 0x72, 0x96, 0x88,
- 0xe8, 0x14, 0x5b, 0x42, 0x92, 0xcb, 0xf8, 0x86, 0x22, 0xab, 0x38, 0x1c, 0x13, 0x8b, 0xf8, 0xe3,
- 0xd2, 0xe0, 0xe7, 0x5a, 0xea, 0xb0, 0x48, 0xda, 0x2e, 0xe5, 0x2e, 0x3f, 0x71, 0xe8, 0x7d, 0x5a,
- 0x1d, 0x7d, 0xea, 0x98, 0x77, 0xe1, 0x38, 0xa7, 0x3b, 0xa4, 0xb4, 0xb1, 0xa7, 0x19, 0xa0, 0x08,
- 0x5a, 0x9a, 0xb9, 0x6d, 0x60, 0xb0, 0xf2, 0x8c, 0xb8, 0x5e, 0x69, 0x6a, 0x8d, 0xdd, 0xcb, 0x5f,
- 0xe2, 0x6b, 0x28, 0x13, 0xd3, 0xcb, 0xb2, 0x64, 0xa0, 0x98, 0x38, 0x91, 0x4c, 0x87, 0x52, 0xad,
- 0x35, 0x25, 0x12, 0x4f, 0x85, 0xb1, 0x10, 0x4f, 0x2f, 0x26, 0xfc, 0x20, 0xc4, 0x6f, 0xd2, 0xf0,
- 0x19, 0x54, 0xb4, 0xa0, 0xbc, 0xb3, 0x8d, 0xaa, 0xbf, 0xb4, 0xec, 0x1e, 0x53, 0x03, 0x1b, 0xcb,
- 0xd0, 0xa0, 0xb7, 0xbd, 0xf7, 0x79, 0x07, 0xc2, 0x0c, 0xde, 0x77, 0x78, 0xa3, 0x3a, 0x90, 0x72,
- 0x15, 0x74, 0x8f, 0xeb, 0x3e, 0x75, 0xa9, 0x4d, 0x09, 0x1b, 0xb7, 0xd0, 0xcf, 0x3e, 0x2d, 0x41,
- 0x74, 0x66, 0x6f, 0xb2, 0x48, 0x9f, 0xf3, 0xe7, 0x32, 0x2d, 0x60, 0xde, 0x84, 0x35, 0xd3, 0xbf,
- 0xd6, 0xd3, 0x03, 0x7b, 0xbc, 0xa0, 0x6d, 0x0b, 0xf9, 0xd9, 0x20, 0x06, 0xad, 0xac, 0x8a, 0x8d,
- 0xaa, 0x10, 0xdb, 0xe9, 0x12, 0x4a, 0xc4, 0xc0, 0xa4, 0xee, 0x69, 0x83, 0xd6, 0xf8, 0x10, 0x1d,
- 0xf6, 0x2f, 0xc1, 0xd2, 0x50, 0x8a, 0x18, 0xc9, 0xca, 0x76, 0x98, 0x98, 0x92, 0xbe, 0xb2, 0xf2,
- 0x44, 0x6d, 0x6e, 0xf1, 0xf6, 0xe0, 0x1b, 0x44, 0x7f, 0xe9, 0x7e, 0x2b, 0x10, 0x96, 0xb6, 0x2b,
- 0xd5, 0x55, 0xd4, 0x68, 0x3a, 0x7b, 0xb4, 0x94, 0xda, 0xbe, 0xec, 0xb0, 0xbd, 0x5a, 0xab, 0x15,
- 0xcf, 0x7d, 0x3b, 0x8c, 0x15, 0x89, 0xb2, 0x0c, 0x0c, 0xa7, 0x3b, 0xba, 0x32, 0x47, 0x25, 0x69,
- 0x55, 0xbb, 0xf7, 0x59, 0x2a, 0xfb, 0x77, 0x80, 0xf8, 0x16, 0xe4, 0xd6, 0xa7, 0x3e, 0x61, 0xc7,
- 0xce, 0xd2, 0x9c, 0x76, 0x85, 0x4f, 0x41, 0x66, 0x4b, 0x21, 0xf1, 0x69, 0x41, 0x4a, 0x79, 0x3a,
- 0x84, 0x96, 0x3d, 0x92, 0xa2, 0x1b, 0x08, 0x26, 0x29, 0x63, 0x42, 0x98, 0x1a, 0xdc, 0xa7, 0x84,
- 0x74, 0xc9, 0x65, 0xf2, 0x2f, 0x74, 0xab, 0xa6, 0xfc, 0x86, 0xcd, 0x61, 0xba, 0xcd, 0x1a, 0x4e,
- 0xdf, 0xfb, 0x79, 0x2c, 0x5c, 0x9e, 0x40, 0x36, 0x07, 0x5f, 0xc6, 0x08, 0x32, 0x36, 0x7a, 0x82,
- 0xa9, 0x42, 0x8b, 0x8b, 0x9e, 0xe2, 0xfc, 0xaf, 0x59, 0x53, 0xeb, 0x73, 0xbe, 0xc2, 0x9b, 0xc2,
- 0xa8, 0x36, 0x79, 0xcb, 0xd7, 0x2d, 0x95, 0xcd, 0xf3, 0x32, 0xa1, 0xde, 0x37, 0x2d, 0x4b, 0x31,
- 0x6f, 0x6b, 0x72, 0x23, 0x92, 0xe9, 0x8c, 0x7b, 0xc5, 0x0b, 0x66, 0x43, 0xaf, 0xa4, 0x4b, 0xc0,
- 0x58, 0xe4, 0xc4, 0x3d, 0x70, 0x4b, 0x44, 0x39, 0xc3, 0xcd, 0x63, 0xbb, 0x9d, 0xe6, 0xf9, 0xfb,
- 0x31, 0x38, 0x18, 0x94, 0xb0, 0xaa, 0x5a, 0x76, 0xf1, 0xd2, 0xe1, 0xac, 0x71, 0x31, 0xb7, 0x6e,
- 0xf8, 0x4e, 0x78, 0x50, 0xc1, 0x13, 0x6e, 0xac, 0x59, 0x66, 0x62, 0xbc, 0xf4, 0x30, 0x3f, 0xda,
- 0xb2, 0xff, 0x8d, 0x6c, 0x93, 0xb9, 0xd8, 0x54, 0x2c, 0x21, 0xd2, 0x34, 0xd2, 0x65, 0xd3, 0xd2,
- 0x30, 0x3f, 0x36, 0x20, 0x28, 0x65, 0xb9, 0xa4, 0x68, 0x4c, 0x1f, 0x4f, 0xe3, 0xca, 0xa5, 0xbe,
- 0x0f, 0x28, 0x9a, 0xf8, 0xf8, 0xe3, 0xdf, 0xa6, 0xc9, 0x9d, 0x95, 0x09, 0x6f, 0xc6, 0x37, 0xf8,
- 0x20, 0xd2, 0x51, 0xf2, 0xc0, 0x6d, 0x33, 0x75, 0xd3, 0x00, 0xea, 0x3d, 0xf7, 0x1e, 0xc0, 0x5b,
- 0xf0, 0x17, 0xff, 0x14, 0x8c, 0xa8, 0xf0, 0xb5, 0xfe, 0xc9, 0x53, 0x08, 0xca, 0x48, 0xa4, 0x6c,
- 0xc7, 0x7e, 0x4a, 0x5c, 0x31, 0x01, 0xce, 0xa6, 0x68, 0x97, 0x9b, 0xc6, 0x1f, 0xe2, 0x20, 0x54,
- 0x3d, 0xde, 0xc8, 0x80, 0x86, 0xe9, 0xc5, 0x0a, 0x2c, 0xb6, 0x2e, 0xb3, 0xb6, 0x1d, 0xbf, 0x79,
- 0x12, 0x27, 0x69, 0x1f, 0xc2, 0x1f, 0xa3, 0xd5, 0x22, 0xab, 0x4f, 0x1c, 0x9f, 0x35, 0xc1, 0xe3,
- 0x0d, 0xd5, 0x5b, 0xd5, 0xa4, 0x72, 0x8c, 0x7c, 0x5c, 0x8b, 0xd0, 0x1c, 0xfc, 0x8f, 0x2e, 0x95,
- 0x59, 0x0f, 0x2e, 0xc5, 0xd7, 0x7b, 0x58, 0xbe, 0x27, 0x91, 0x2b, 0x09, 0x4a, 0x7c, 0x3b, 0x21,
- 0x19, 0x07, 0x32, 0xc5, 0x37, 0xc2, 0x69, 0x7f, 0x10, 0x53, 0xa7, 0xcf, 0x2e, 0x0b, 0x87, 0xb4,
- 0x39, 0x6e, 0x49, 0xb7, 0xfb, 0x1d, 0x29, 0xf1, 0x9e, 0x70, 0xdd, 0x61, 0x70, 0xe1, 0x63, 0x23,
- 0xcd, 0x7f, 0x7e, 0x33, 0xf0, 0x29, 0x5a, 0x5e, 0x19, 0xe4, 0xc7, 0xed, 0xf1, 0x80, 0x9e, 0xaa,
- 0xe9, 0xa8, 0xd8, 0x07, 0x4a, 0x03, 0xab, 0x13, 0x50, 0x72, 0x59, 0x26, 0x62, 0x0e, 0xff, 0xa4,
- 0xaf, 0x05, 0x73, 0x0e, 0xf6, 0xdc, 0x06, 0xa2, 0xb8, 0xd3, 0x64, 0x22, 0xa8, 0x58, 0x6b, 0x44,
- 0xa7, 0x9e, 0x14, 0xde, 0x79, 0x87, 0xed, 0x13, 0xee, 0xad, 0xbd, 0x87, 0xed, 0xe8, 0x82, 0xa7,
- 0x20, 0x8c, 0x81, 0xd4, 0x7b, 0x45, 0xe1, 0x19, 0xda, 0x17, 0x4a, 0xdb, 0xc6, 0xb3, 0xf7, 0x6b,
- 0xc9, 0x17, 0x53, 0x96, 0x58, 0x00, 0x21, 0x5a, 0x52, 0xdd, 0xf7, 0xb7, 0xf3, 0x64, 0x8b, 0xfd,
- 0x40, 0x70, 0x10, 0xd7, 0xd3, 0x7e, 0xa7, 0x6b, 0xb2, 0xb5, 0xbf, 0x02, 0x0a, 0x63, 0xb8, 0x6c,
- 0xa9, 0xb0, 0x6d, 0x84, 0x1e, 0x81, 0x1d, 0x69, 0xe5, 0x02, 0xd2, 0x81, 0x63, 0x28, 0x9e, 0x58,
- 0xfc, 0x20, 0xcc, 0xaa, 0xbc, 0x3e, 0x0b, 0x61, 0x24, 0xea, 0x41, 0x6c, 0xf5, 0x24, 0x64, 0x4e,
- 0xee, 0x3a, 0xaf, 0xb3, 0xec, 0xf3, 0xe2, 0x73, 0x66, 0x7f, 0x1d, 0x1e, 0xd3, 0x5d, 0xfc, 0x0c,
- 0x20, 0xb9, 0xca, 0xe8, 0x61, 0x8a, 0x82, 0xb7, 0xc3, 0x80, 0x3c, 0x5e, 0x09, 0x08, 0x88, 0x5a,
- 0x92, 0xdd, 0xfc, 0x42, 0xa0, 0xb1, 0x42, 0x6d, 0xbf, 0xd8, 0x06, 0x6b, 0x5a, 0xa3, 0x9a, 0x1b,
- 0xf7, 0x97, 0x35, 0xef, 0x31, 0xb0, 0x05, 0x95, 0x89, 0x5a, 0x37, 0xd2, 0x4c, 0x77, 0xe2, 0x51,
- 0xc9, 0x54, 0x6e, 0xab, 0x0d, 0x69, 0xa6, 0xa0, 0xa0, 0x20, 0xa7, 0xfc, 0xa9, 0x6c, 0x1b, 0x19,
- 0x97, 0x8d, 0xa6, 0xac, 0xed, 0x6f, 0x25, 0xbc, 0xac, 0x5d, 0x2c, 0x95, 0xc3, 0xaa, 0xca, 0x9b,
- 0x7d, 0x4b, 0x88, 0x72, 0x6a, 0x2f, 0xe8, 0x50, 0x70, 0x45, 0xf3, 0x09, 0xfe, 0x5e, 0xb8, 0xe5,
- 0xe8, 0x4b, 0xc8, 0xc1, 0xc8, 0x07, 0x5c, 0x94, 0xe2, 0xc6, 0x8e, 0xdd, 0x50, 0xa2, 0xee, 0x67,
- 0x85, 0xac, 0x0a, 0x91, 0x69, 0x9f, 0xc4, 0x02, 0x66, 0x59, 0xd8, 0x7c, 0x37, 0xb3, 0xab, 0x93,
- 0xc4, 0x83, 0xfc, 0xa0, 0x72, 0x0e, 0x3d, 0x16, 0x5a, 0x9e, 0xf8, 0xb6, 0x9b, 0xeb, 0x68, 0xa2,
- 0xa4, 0xd5, 0x93, 0x16, 0x4e, 0x69, 0xd5, 0xca, 0xa5, 0x5b, 0x33, 0xce, 0x91, 0x0f, 0x8a, 0xc3,
- 0x1c, 0x80, 0xbe, 0x66, 0x1d, 0xc9, 0xec, 0x17, 0x46, 0x51, 0x50, 0x92, 0x1c, 0x31, 0x7d, 0xfc,
- 0x72, 0x25, 0xb3, 0x38, 0xe6, 0x8a, 0x08, 0xc7, 0x1a, 0x8a, 0x7e, 0x51, 0x35, 0xe7, 0x8b, 0xec,
- 0xb7, 0x2f, 0xf7, 0x10, 0x10, 0x37, 0x16, 0x5c, 0xfe, 0xc0, 0xf3, 0x68, 0x50, 0x7a, 0x46, 0x5c,
- 0x5e, 0xbe, 0x97, 0xc3, 0xde, 0x11, 0xfc, 0x9d, 0x0d, 0x3a, 0xd5, 0xfd, 0x76, 0xeb, 0x89, 0xd7,
- 0x2d, 0xb7, 0x65, 0x3f, 0xd5, 0x23, 0xad, 0xba, 0xb7, 0xca, 0x4a, 0x4f, 0x79, 0x8d, 0x3b, 0x64,
- 0xf5, 0xf5, 0xfa, 0x80, 0xb0, 0xf3, 0x24, 0x9e, 0x5a, 0x91, 0xb1, 0xb5, 0x20, 0x06, 0x56, 0x70,
- 0xb4, 0x57, 0x6f, 0x0f, 0xad, 0x06, 0x3b, 0xc0, 0xa5, 0x59, 0xf6, 0x1b, 0x03, 0x4e, 0xe6, 0xb8,
- 0x9f, 0xff, 0xe8, 0x41, 0x78, 0xd1, 0x98, 0xc1, 0xaa, 0x70, 0xd0, 0xc3, 0x10, 0xcd, 0x49, 0x1b,
- 0x68, 0x20, 0x89, 0x00, 0x52, 0xf0, 0xa5, 0x5c, 0xfe, 0x75, 0x69, 0x43, 0x29, 0x9e, 0x54, 0xdc,
- 0xfc, 0x6b, 0xee, 0xe7, 0x9e, 0xba, 0x19, 0xe3, 0x9c, 0x32, 0xbf, 0xde, 0xec, 0xc3, 0x59, 0xdc,
- 0x2a, 0x76, 0x85, 0x4c, 0x5d, 0x78, 0x28, 0xda, 0xca, 0xd8, 0xa2, 0xf2, 0x2a, 0xc2, 0x0e, 0x88,
- 0xb5, 0x66, 0x4b, 0x3f, 0xca, 0x43, 0xd0, 0x46, 0x8c, 0xb0, 0xe1, 0x81, 0x64, 0x07, 0x41, 0xa5,
- 0x21, 0xed, 0x9a, 0x56, 0x5e, 0x36, 0x4a, 0x5c, 0xf5, 0xa7, 0x3f, 0xd9, 0x9a, 0xb8, 0x8a, 0xea,
- 0x5a, 0x7a, 0x7b, 0x2d, 0x3d, 0xc9, 0x70, 0x43, 0x7f, 0x42, 0xf8, 0xa5, 0xf3, 0x00, 0x32, 0x0e,
- 0xf8, 0x20, 0x90, 0xc1, 0x72, 0xbc, 0x12, 0xcb, 0x22, 0xa3, 0xf3, 0x97, 0xb8, 0x58, 0xea, 0xeb,
- 0xea, 0xd0, 0x8c, 0x34, 0xb3, 0x36, 0x37, 0x1c, 0x43, 0xe7, 0x7c, 0x93, 0x65, 0x41, 0x00, 0xf0,
- 0xb2, 0xe4, 0xae, 0x31, 0x58, 0x06, 0x7a, 0x35, 0x89, 0xdf, 0x6e, 0x38, 0x96, 0x3f, 0xb0, 0xa5,
- 0x5c, 0xcb, 0x87, 0x96, 0x9b, 0x64, 0xa0, 0x7a, 0xfd, 0x48, 0x8b, 0xd3, 0xf0, 0xa1, 0x67, 0x32,
- 0x77, 0x0b, 0x24, 0x21, 0x79, 0xb0, 0xef, 0x66, 0x6d, 0x1a, 0x53, 0x11, 0xad, 0x0d, 0xd8, 0x31,
- 0x8c, 0xc0, 0xb3, 0x2c, 0xf0, 0x44, 0x45, 0x0a, 0xc0, 0x7b, 0xa5, 0xf0, 0x37, 0x3f, 0xea, 0xb3,
- 0xf5, 0x58, 0x18, 0x51, 0x04, 0x7f, 0x23, 0xf8, 0xbb, 0xcc, 0x6a, 0xdc, 0xf0, 0x30, 0xfa, 0x87,
- 0x3d, 0xc4, 0x75, 0x04, 0x1e, 0x2d, 0x45, 0xf0, 0xe2, 0x42, 0x67, 0xd2, 0x88, 0xc0, 0x04, 0x44,
- 0xe7, 0xab, 0x02, 0xf0, 0xbe, 0x86, 0x1a, 0x1d, 0xc0, 0x9b, 0x28, 0x04, 0x05, 0x39, 0x28, 0xf2,
- 0xfb, 0x3f, 0x2d, 0x79, 0x3e, 0xcf, 0x0a, 0xef, 0x65, 0x23, 0xf4, 0x3c, 0x41, 0xbc, 0xb0, 0x0f,
- 0xae, 0x26, 0xb8, 0x58, 0xa1, 0x75, 0xdf, 0x27, 0xcd, 0x4a, 0xbd, 0xa3, 0x6a, 0x9e, 0xe7, 0x32,
- 0x13, 0x65, 0x71, 0x75, 0x21, 0xa6, 0xbe, 0xb3, 0xcd, 0x9c, 0x42, 0xa1, 0x62, 0x6b, 0x9c, 0x79,
- 0xbf, 0xef, 0x93, 0xc3, 0x7c, 0xf2, 0x57, 0x70, 0x68, 0x14, 0x5d, 0xf1, 0xb7, 0x2a, 0x71, 0x11,
- 0xfc, 0x7a, 0xdd, 0x0e, 0xdf, 0xa1, 0xef, 0xca, 0x5e, 0xb3, 0x2e, 0x67, 0xf1, 0x82, 0x25, 0x84,
- 0x20, 0x11, 0x07, 0x6a, 0xe5, 0x4d, 0x63, 0xe9, 0xb0, 0x39, 0xf3, 0x42, 0x13, 0x8e, 0xc3, 0x39,
- 0x0a, 0x18, 0x8c, 0x15, 0x37, 0x1b, 0xec, 0x2d, 0x9b, 0x4b, 0x97, 0x20, 0x8b, 0x67, 0x34, 0xcb,
- 0xa2, 0x5b, 0x3d, 0xce, 0xdd, 0xb5, 0xd6, 0xbe, 0xf1, 0x75, 0x3c, 0x15, 0x93, 0xd7, 0x47, 0xd8,
- 0x0a, 0x97, 0xd1, 0xe4, 0x68, 0xb8, 0x16, 0xa8, 0x64, 0xb7, 0x9e, 0x8e, 0x55, 0x2c, 0x45, 0xab,
- 0xc4, 0xb8, 0xaa, 0xc7, 0x26, 0x69, 0x92, 0x7d, 0x47, 0x53, 0x11, 0x07, 0x04, 0x18, 0x70, 0x7b,
- 0xcb, 0xbb, 0x5f, 0x60, 0x55, 0x07, 0xbb, 0x28, 0x2a, 0x74, 0x09, 0x2f, 0x6f, 0x91, 0x19, 0xf3,
- 0x5c, 0xcb, 0x29, 0x1e, 0xef, 0x87, 0xd4, 0xa4, 0x83, 0x1c, 0xe7, 0x8a, 0x61, 0xb4, 0xfe, 0x7a,
- 0xa4, 0x2c, 0xc0, 0x63, 0x47, 0x53, 0x93, 0x24, 0xde, 0x1e, 0x46, 0x62, 0x7e, 0xb2, 0x76, 0x58,
- 0x39, 0x80, 0x3a, 0x54, 0x41, 0xa4, 0xa5, 0xaf, 0xa5, 0x7f, 0x18, 0xcf, 0xca, 0xe6, 0x17, 0x5e,
- 0xc8, 0x0a, 0x54, 0x9e, 0x24, 0x35, 0xa5, 0x85, 0x1e, 0x4e, 0xe4, 0x00, 0xd4, 0xfc, 0xb2, 0x08,
- 0x5d, 0xef, 0x99, 0x28, 0xe9, 0xcf, 0x5c, 0xa2, 0x89, 0x4c, 0x10, 0xba, 0x4c, 0xa3, 0x35, 0x35,
- 0x99, 0xb7, 0x5e, 0xfd, 0x5e, 0x5e, 0x63, 0xd5, 0x3a, 0x6e, 0xf9, 0x2a, 0xf1, 0x0b, 0x34, 0xfc,
- 0x40, 0x8f, 0xe8, 0x85, 0xc5, 0x82, 0x16, 0xa0, 0xfc, 0x39, 0x94, 0xbb, 0xb0, 0x6a, 0x3d, 0x9a,
- 0xe0, 0x04, 0xf4, 0x90, 0x04, 0x57, 0x70, 0x99, 0xc3, 0x98, 0x35, 0x37, 0x3f, 0x2e, 0x36, 0x27,
- 0x81, 0x27, 0xbb, 0x5f, 0x33, 0x32, 0xe3, 0x93, 0xd3, 0x1d, 0x79, 0xa9, 0x0e, 0x43, 0x0b, 0x02,
- 0xa5, 0x31, 0x2f, 0x96, 0x93, 0x8f, 0xea, 0x2a, 0x84, 0x68, 0x52, 0x2f, 0x89, 0x1a, 0xfe, 0xb4,
- 0xc6, 0x11, 0xd5, 0x64, 0xe3, 0x44, 0xc5, 0xe9, 0xfe, 0x17, 0x7f, 0x03, 0xd6, 0x9b, 0x62, 0xff,
- 0xd0, 0xf5, 0xdc, 0x9f, 0x04, 0x0c, 0xe3, 0x0f, 0x41, 0x6f, 0x48, 0x62, 0x79, 0x6d, 0xd2, 0xc1,
- 0x51, 0x76, 0xc3, 0x4e, 0x6b, 0x54, 0x54, 0x42, 0xb9, 0xa5, 0x82, 0x47, 0x48, 0x8b, 0x91, 0x63,
- 0xba, 0xcb, 0x34, 0x8c, 0x2e, 0x36, 0x09, 0x85, 0x44, 0x1e, 0x1d, 0x1f, 0x28, 0x90, 0x60, 0xbc,
- 0x58, 0xb9, 0xd7, 0xfe, 0xe6, 0x12, 0xe8, 0xe2, 0x5f, 0x4b, 0x80, 0x0b, 0x90, 0x10, 0x39, 0xd2,
- 0x2e, 0x84, 0xd1, 0x99, 0x3d, 0xe6, 0x84, 0xdb, 0x41, 0x17, 0x73, 0x28, 0xfc, 0xc5, 0x15, 0x08,
- 0xb0, 0x15, 0x61, 0x69, 0x90, 0x29, 0xea, 0xdb, 0xa9, 0xac, 0xe6, 0x4f, 0x26, 0xbb, 0xde, 0x50,
- 0xa0, 0xcc, 0xd8, 0x3d, 0x4b, 0x5d, 0xe2, 0xb7, 0x87, 0x3f, 0x42, 0x81, 0x67, 0x91, 0xc4, 0x54,
- 0x18, 0xe7, 0x39, 0x6a, 0x3a, 0xc9, 0xc9, 0x87, 0xd5, 0x55, 0x54, 0x06, 0xab, 0xd1, 0x44, 0xf0,
- 0x9d, 0x03, 0x78, 0x9b, 0x7a, 0xd0, 0x40, 0x72, 0xd8, 0x37, 0xc5, 0x77, 0x3d, 0xbf, 0x7f, 0x2c,
- 0xc4, 0xce, 0x96, 0x16, 0x17, 0xe6, 0x12, 0x6b, 0x84, 0x20, 0x82, 0x47, 0xbc, 0xc3, 0x9b, 0x21,
- 0xed, 0x60, 0x75, 0x37, 0xac, 0x94, 0x71, 0x46, 0xb3, 0xdc, 0x6e, 0x6a, 0x71, 0x84, 0x5d, 0xef,
- 0x0e, 0x92, 0x87, 0x21, 0xc4, 0x1a, 0x06, 0xad, 0xff, 0x0f, 0x34, 0xfa, 0x75, 0x10, 0xc8, 0x08,
- 0x3b, 0x7a, 0x8b, 0x0d, 0x16, 0xb6, 0x9c, 0x93, 0xe3, 0x42, 0xc4, 0x65, 0x5d, 0x40, 0x62, 0x7f,
- 0xc6, 0x3e, 0xd1, 0xd5, 0x3e, 0x39, 0x34, 0xfe, 0xb7, 0x96, 0xd7, 0xaf, 0xc3, 0xa4, 0x1c, 0x8c,
- 0x11, 0xa8, 0xd9, 0xce, 0x54, 0x03, 0x8c, 0xc9, 0x93, 0xfc, 0xbf, 0x06, 0xe0, 0x66, 0xbf, 0xb7,
- 0xca, 0x54, 0xf4, 0x9e, 0x98, 0x14, 0x53, 0x78, 0x3b, 0xf8, 0x3a, 0x7f, 0xa2, 0x36, 0xa1, 0x3c,
- 0xf0, 0x3d, 0x61, 0x20, 0x6c, 0x89, 0x63, 0x83, 0x22, 0xd6, 0xae, 0xef, 0x90, 0x70, 0x88, 0x89,
- 0xa6, 0xca, 0x38, 0x7f, 0x12, 0x8c, 0x31, 0x6d, 0x0e, 0xc9, 0x73, 0x61, 0xa9, 0x39, 0x4b, 0x14,
- 0x5b, 0xcc, 0xea, 0xd7, 0xe1, 0xaf, 0x01, 0x9f, 0x89, 0x12, 0xe5, 0x9d, 0xa9, 0x4e, 0xf0, 0xbf,
- 0x6d, 0xff, 0x97, 0x48, 0x3c, 0xd9, 0x20, 0x61, 0x2c, 0x87, 0x6e, 0x2b, 0xcb, 0x0f, 0x87, 0x36,
- 0xc0, 0x12, 0x9f, 0xa1, 0xad, 0x33, 0x59, 0x7c, 0x12, 0x5a, 0x8a, 0xe0, 0x54, 0x58, 0xe6, 0x4c,
- 0x08, 0x01, 0x8d, 0xb9, 0x27, 0x4d, 0x9c, 0xbc, 0xca, 0x14, 0x39, 0x71, 0x43, 0xf1, 0xa7, 0x02,
- 0x58, 0x85, 0x99, 0x54, 0x41, 0x14, 0xb2, 0xab, 0xdf, 0x7e, 0x89, 0xc2, 0x96, 0x24, 0xeb, 0x67,
- 0x8b, 0x43, 0xda, 0x27, 0x91, 0xe1, 0x2a, 0x0f, 0xf5, 0xc9, 0x25, 0x21, 0xc8, 0x5c, 0xe3, 0x81,
- 0x02, 0x3c, 0xa1, 0xbf, 0x99, 0x16, 0x69, 0x63, 0x68, 0xf3, 0xa1, 0xe9, 0x2e, 0xd4, 0xb9, 0xda,
- 0x28, 0x00, 0x06, 0x8a, 0xc1, 0xbe, 0xaf, 0x89, 0xa2, 0x79, 0x06, 0xb8, 0x64, 0x9f, 0x79, 0xbb,
- 0xe7, 0x34, 0x69, 0x73, 0x79, 0xc1, 0xac, 0x2f, 0x69, 0x64, 0x90, 0x7a, 0x02, 0x99, 0x4d, 0xe9,
- 0x7c, 0xab, 0x57, 0x7a, 0x3c, 0x38, 0x0a, 0xd0, 0x57, 0x74, 0x1e, 0x1e, 0x57, 0xdb, 0xe4, 0x8d,
- 0x44, 0x22, 0x08, 0xc3, 0x55, 0xbf, 0xb9, 0xeb, 0xd9, 0xdf, 0xc3, 0x98, 0x8a, 0x83, 0x62, 0x94,
- 0x95, 0x61, 0xa2, 0x3b, 0x71, 0x7e, 0x18, 0x5b, 0x92, 0x79, 0x69, 0xc8, 0x4b, 0xea, 0x25, 0x81,
- 0xb8, 0xfa, 0xcb, 0x42, 0x41, 0xea, 0xb8, 0xe8, 0xb3, 0xf2, 0x34, 0x96, 0x7b, 0xcf, 0x29, 0x15,
- 0xd4, 0x9f, 0xc1, 0x14, 0xb1, 0x57, 0x59, 0xa1, 0xb0, 0xaa, 0xd6, 0xaf, 0x74, 0xd7, 0xde, 0x34,
- 0xa5, 0x09, 0x43, 0x88, 0x72, 0x43, 0x6d, 0x13, 0xb3, 0xcb, 0xb9, 0xaf, 0x45, 0xb4, 0x7f, 0xe3,
- 0xe5, 0x7f, 0xb3, 0x14, 0x06, 0x39, 0xfe, 0x52, 0xdf, 0x6a, 0x0b, 0x40, 0x1a, 0xf4, 0x8e, 0xd2,
- 0x9b, 0xa6, 0x3d, 0x96, 0x4d, 0xce, 0x54, 0x0c, 0x65, 0x41, 0x8e, 0x56, 0x8f, 0xcb, 0x00, 0x8f,
- 0xba, 0xdb, 0x17, 0x1b, 0x94, 0xa1, 0xd8, 0x9e, 0xfb, 0x63, 0x8c, 0x01, 0xd4, 0x89, 0xf5, 0x81,
- 0x16, 0xfa, 0x43, 0xd6, 0xfe, 0x4c, 0x44, 0x3d, 0x16, 0x26, 0x4c, 0x58, 0x07, 0x9f, 0xcd, 0xb5,
- 0x35, 0xb3, 0xf9, 0xd4, 0xb3, 0x90, 0x43, 0x04, 0x74, 0x20, 0x2a, 0xfe, 0x62, 0xfa, 0x17, 0x97,
- 0xbe, 0x0a, 0xa3, 0xb7, 0x48, 0xe7, 0x67, 0x32, 0xaa, 0x9c, 0x64, 0x99, 0x8a, 0x1b, 0x07, 0x3a,
- 0x0e, 0x3c, 0x0f, 0x84, 0x5b, 0x01, 0x10, 0x85, 0x9e, 0x27, 0x09, 0xd4, 0xae, 0x91, 0xdb, 0x65,
- 0xcd, 0xdd, 0xe2, 0xf1, 0x08, 0x00, 0x3b, 0xe4, 0xe4, 0x2c, 0xf7, 0x5e, 0xfe, 0x45, 0x19, 0x9a,
- 0x69, 0x7c, 0x61, 0xdb, 0x29, 0xf8, 0x97, 0xd7, 0x49, 0x52, 0xde, 0x80, 0x2c, 0x5e, 0x55, 0x60,
- 0xc9, 0xbc, 0x9a, 0x56, 0x4d, 0x01, 0x6e, 0x4e, 0x36, 0x85, 0x4a, 0x11, 0x12, 0x5e, 0xb7, 0x7d,
- 0x96, 0x23, 0x89, 0x3c, 0x14, 0x14, 0x0f, 0xad, 0x40, 0x7f, 0x0c, 0x88, 0xb8, 0x07, 0xa2, 0x70,
- 0x2c, 0x69, 0xa9, 0xec, 0x87, 0x45, 0x99, 0x33, 0x06, 0xca, 0xad, 0xb4, 0x5c, 0x44, 0x1c, 0x37,
- 0x7b, 0xfb, 0x6a, 0x3b, 0x23, 0x74, 0x60, 0xc5, 0xa6, 0x69, 0x9c, 0x0c, 0x23, 0x95, 0x69, 0x27,
- 0x39, 0xb8, 0x29, 0x81, 0x55, 0x59, 0x53, 0xc2, 0xe9, 0xf3, 0x25, 0x63, 0xa0, 0x25, 0xc3, 0x79,
- 0x78, 0x62, 0x7f, 0x37, 0x0f, 0xe9, 0x8c, 0xec, 0xf1, 0x43, 0x4d, 0x40, 0x6c, 0x4f, 0xa1, 0xff,
- 0xe7, 0x1c, 0xb2, 0xe4, 0xde, 0x7b, 0x34, 0xb1, 0x4b, 0x16, 0x3d, 0x7f, 0xba, 0xac, 0x99, 0xd8,
- 0xa8, 0xa1, 0x7f, 0xf5, 0xfc, 0x08, 0x14, 0xb6, 0x5c, 0x62, 0x1a, 0x53, 0x7b, 0x76, 0x00, 0x32,
- 0xbe, 0xba, 0xbb, 0x50, 0xb9, 0xa2, 0x4c, 0xf2, 0x4a, 0x00, 0xc5, 0xc6, 0x7c, 0x91, 0xb9, 0xa6,
- 0x86, 0x72, 0x35, 0x2d, 0xe1, 0x7a, 0xb9, 0xd2, 0xd0, 0x62, 0x22, 0xf0, 0x87, 0xe4, 0xbc, 0x89,
- 0x3b, 0xb8, 0xac, 0xb2, 0x91, 0xa1, 0xdc, 0x4c, 0xdd, 0xab, 0x2b, 0xcd, 0x0e, 0x94, 0xb4, 0x17,
- 0x4b, 0x01, 0xcf, 0xec, 0x76, 0xe9, 0x2f, 0x0f, 0x56, 0xc4, 0x75, 0x76, 0x9d, 0xfe, 0x44, 0x5c,
- 0x63, 0x5d, 0x5d, 0xd9, 0x9a, 0x59, 0x6f, 0xba, 0xf4, 0x96, 0xa1, 0x47, 0xee, 0x94, 0xe9, 0xe6,
- 0x0a, 0x55, 0x00, 0x89, 0x8d, 0x2d, 0x69, 0x1b, 0x34, 0x4a, 0xd2, 0x3f, 0xa8, 0x3c, 0x9c, 0x1a,
- 0x66, 0x25, 0x68, 0x4b, 0xdc, 0x84, 0xe2, 0xe1, 0xc1, 0xbf, 0xc2, 0xe3, 0x5d, 0xc5, 0xd7, 0x34,
- 0x03, 0xd1, 0x8f, 0xf0, 0xae, 0x1b, 0x25, 0x13, 0x45, 0xc1, 0x64, 0x18, 0x55, 0x27, 0x2d, 0xac,
- 0xd3, 0x5d, 0x94, 0xab, 0x66, 0xb4, 0xef, 0x1c, 0xca, 0x95, 0x44, 0xb1, 0x95, 0xd2, 0x73, 0x66,
- 0x3e, 0x7c, 0xc7, 0x5f, 0x86, 0x0e, 0xb4, 0x81, 0x15, 0xa8, 0x0f, 0xba, 0x0c, 0x0e, 0xf1, 0x1b,
- 0xec, 0x3f, 0x2f, 0x08, 0x26, 0xef, 0x2b, 0x13, 0x96, 0x98, 0xec, 0x16, 0x88, 0xe8, 0x30, 0x49,
- 0xe8, 0xa7, 0x69, 0x3c, 0x10, 0x7d, 0x3c, 0x5c, 0x73, 0xd2, 0x9d, 0xf3, 0xd6, 0x3e, 0x8a, 0xcb,
- 0x05, 0xb0, 0x24, 0x3b, 0x99, 0xa7, 0x2b, 0x05, 0x96, 0x9a, 0x7d, 0x1e, 0xbd, 0x93, 0x0a, 0x2d,
- 0x79, 0xdf, 0x4f, 0xb3, 0x43, 0xf0, 0x44, 0x4f, 0xe0, 0xac, 0x78, 0x9c, 0x64, 0x85, 0x9b, 0x5e,
- 0x11, 0x0e, 0xea, 0x78, 0x59, 0xf1, 0xaf, 0x80, 0x10, 0xf4, 0xd9, 0x74, 0x0b, 0x18, 0x56, 0x58,
- 0xaa, 0xd7, 0xea, 0xc6, 0xd7, 0x8d, 0x72, 0x0b, 0x82, 0x44, 0x1e, 0x41, 0x9a, 0xbe, 0x41, 0x9b,
- 0xe4, 0x36, 0x27, 0x02, 0x5d, 0xd3, 0x00, 0x60, 0xaa, 0xa1, 0x16, 0x5c, 0xa7, 0x22, 0x2b, 0x2a,
- 0xcb, 0xe0, 0xed, 0xd2, 0xfb, 0xfd, 0x7a, 0x82, 0x21, 0xc0, 0x5d, 0xa6, 0x68, 0x5c, 0x81, 0xe0,
- 0xa4, 0xf8, 0xb5, 0x25, 0x7f, 0xfc, 0x72, 0x8a, 0x91, 0x1f, 0xad, 0x86, 0xcc, 0xa9, 0xe8, 0x67,
- 0x60, 0xfa, 0xdc, 0x07, 0x0e, 0x38, 0x4c, 0x6e, 0x6e, 0x2f, 0xad, 0xcc, 0x43, 0x92, 0x73, 0xe4,
- 0xa7, 0x05, 0x96, 0x43, 0x44, 0x30, 0x75, 0x8c, 0x18, 0xd0, 0x78, 0x04, 0xcb, 0x03, 0xf3, 0x2c,
- 0xce, 0x19, 0xc6, 0x15, 0xd1, 0x9c, 0x14, 0xd5, 0xf5, 0x3e, 0x57, 0x16, 0x15, 0xa8, 0xeb, 0xa7,
- 0xac, 0x18, 0x86, 0x41, 0x16, 0x55, 0x48, 0x3d, 0xa9, 0xb2, 0xdf, 0xc7, 0x6b, 0xef, 0xbf, 0x6c,
- 0xa1, 0x59, 0x59, 0x2c, 0xa7, 0x57, 0xad, 0x35, 0xe8, 0x75, 0x3e, 0xe3, 0x7b, 0xae, 0x48, 0xf4,
- 0x41, 0x1b, 0x84, 0xae, 0x7c, 0xeb, 0x85, 0x07, 0x2f, 0x65, 0xef, 0x55, 0x4d, 0x82, 0x9c, 0xef,
- 0xaa, 0xcc, 0x66, 0x6e, 0xc4, 0xdb, 0x15, 0xf7, 0x7b, 0x62, 0x42, 0x0b, 0x3a, 0x1d, 0xd3, 0x18,
- 0x12, 0xdb, 0x08, 0x50, 0xb2, 0x37, 0xd8, 0x2c, 0x55, 0x47, 0xb6, 0xf6, 0xc1, 0x3a, 0x9b, 0x59,
- 0x00, 0xe4, 0x25, 0x6e, 0x40, 0xdf, 0xb4, 0x38, 0x1f, 0x00, 0x17, 0x6c, 0x20, 0x59, 0x97, 0x46,
- 0xb9, 0xff, 0xea, 0x9e, 0x57, 0x34, 0x19, 0x54, 0xdd, 0x7f, 0xa0, 0x5f, 0x74, 0x72, 0x1b, 0xf2,
- 0xc1, 0x93, 0xed, 0x91, 0xa8, 0x15, 0x5e, 0x10, 0xfc, 0x24, 0xe1, 0xe6, 0x9b, 0xdb, 0x52, 0x2c,
- 0x44, 0x5c, 0xef, 0xdb, 0x6e, 0xc4, 0x50, 0x3f, 0x11, 0xd6, 0x7b, 0x36, 0xfc, 0x05, 0xb2, 0x55,
- 0x53, 0x2e, 0xb5, 0x43, 0x50, 0xd7, 0x56, 0x95, 0xc4, 0x5c, 0xe1, 0x26, 0xe3, 0x82, 0x63, 0x4f,
- 0xb3, 0x9e, 0x4c, 0x87, 0x3e, 0xab, 0x89, 0x33, 0x77, 0xab, 0xb9, 0xcf, 0xba, 0x1e, 0x7c, 0xc3,
- 0x41, 0x2f, 0xe2, 0x2b, 0x14, 0xd6, 0xd3, 0x55, 0x7f, 0x68, 0x37, 0x0c, 0x42, 0x2d, 0xbf, 0x9a,
- 0x51, 0x6c, 0xfe, 0x70, 0x45, 0xc2, 0x4f, 0x5d, 0xf4, 0x0a, 0x08, 0x2a, 0xd8, 0x89, 0xf1, 0x08,
- 0x2e, 0xbd, 0x70, 0x5b, 0xf5, 0x53, 0xf8, 0x5e, 0xc6, 0xec, 0x5c, 0x7b, 0xdc, 0x81, 0x16, 0xba,
- 0xc7, 0x52, 0x64, 0x7b, 0x0f, 0x2d, 0x41, 0x22, 0x60, 0x15, 0x58, 0x3d, 0xa0, 0x45, 0x16, 0x7d,
- 0xdd, 0xcc, 0xe5, 0x00, 0xc5, 0xd8, 0x0e, 0x9b, 0x88, 0x99, 0xde, 0xa4, 0xcd, 0x8b, 0x3c, 0xeb,
- 0x6c, 0x3f, 0x98, 0xec, 0xf9, 0x9a, 0x21, 0xb0, 0xd4, 0xd1, 0x42, 0x0c, 0xe0, 0x09, 0x79, 0x2a,
- 0x28, 0xf9, 0x2e, 0x25, 0x6e, 0xf4, 0x5d, 0xc5, 0xd5, 0xba, 0x0d, 0x94, 0xd5, 0x02, 0xfa, 0xa3,
- 0xab, 0xcf, 0xb6, 0xf5, 0xab, 0x1d, 0x32, 0xc3, 0x98, 0xc8, 0x54, 0x4c, 0xd1, 0xff, 0xfe, 0x4d,
- 0x5e, 0xc8, 0xeb, 0x18, 0x7e, 0xa7, 0x09, 0x54, 0xf5, 0x20, 0x39, 0x36, 0xee, 0x6c, 0x67, 0x9c,
- 0x88, 0x08, 0xf4, 0xdf, 0xae, 0x77, 0x4a, 0x14, 0x29, 0x5e, 0x13, 0xc4, 0x18, 0x55, 0x8e, 0xdf,
- 0x1b, 0x91, 0xb7, 0x6f, 0x43, 0x92, 0x00, 0x0d, 0xd0, 0xcf, 0xdb, 0x32, 0x70, 0xc0, 0xf3, 0x51,
- 0xea, 0xa8, 0xf8, 0xb9, 0x97, 0x16, 0x68, 0xa6, 0xf3, 0xc1, 0xbf, 0xdb, 0x59, 0x71, 0xb2, 0xb0,
- 0x94, 0xbc, 0x2f, 0xdf, 0xf9, 0xa3, 0x4d, 0x29, 0x04, 0xfe, 0xf6, 0xf0, 0x2f, 0x51, 0x58, 0xe9,
- 0xa2, 0x5b, 0x2a, 0xc0, 0xcf, 0x35, 0xba, 0x35, 0x5a, 0x4f, 0x66, 0x7f, 0x4d, 0xa5, 0x25, 0x75,
- 0x5d, 0xff, 0x53, 0x02, 0x8b, 0x0b, 0x4d, 0x50, 0x7a, 0x9e, 0xf2, 0x94, 0xb8, 0x61, 0x35, 0x87,
- 0xc5, 0x7f, 0x89, 0x4f, 0xeb, 0xc6, 0x2a, 0x48, 0x22, 0xe4, 0x2f, 0x78, 0x7e, 0xa0, 0x2d, 0x98,
- 0x21, 0x62, 0xd8, 0xf7, 0xbd, 0x2b, 0xde, 0x77, 0x07, 0xde, 0x55, 0xa2, 0xb2, 0xb9, 0x4a, 0x68,
- 0x5e, 0x4a, 0x0a, 0x0b, 0xc9, 0x49, 0x8e, 0xce, 0x57, 0x83, 0xb5, 0xca, 0xa0, 0x1c, 0x9b, 0xbb,
- 0x5f, 0x6a, 0xf1, 0x92, 0xac, 0x04, 0x8c, 0x1b, 0x46, 0x15, 0x99, 0x14, 0xe6, 0x06, 0xd1, 0x46,
- 0x77, 0x76, 0x3f, 0x2e, 0x37, 0x5b, 0x39, 0xdd, 0x3d, 0x96, 0x95, 0xd9, 0xe5, 0x8c, 0x03, 0x86,
- 0xc6, 0x02, 0x17, 0x95, 0x9a, 0x1c, 0x8c, 0x77, 0xe4, 0x47, 0xfe, 0xe3, 0x87, 0xe5, 0x28, 0xd5,
- 0xcf, 0x48, 0xce, 0x1c, 0x2f, 0xda, 0x23, 0x6c, 0xbc, 0xdf, 0xa7, 0x3f, 0x24, 0x82, 0x65, 0xb7,
- 0xe1, 0x49, 0x07, 0x0f, 0x67, 0x5d, 0x25, 0x05, 0x23, 0xb3, 0x5f, 0xe1, 0xf3, 0xb2, 0x5d, 0xf2,
- 0x22, 0x0b, 0xa3, 0x16, 0xc3, 0xdc, 0xa0, 0xa8, 0x29, 0xb3, 0xf2, 0xc6, 0xdc, 0x98, 0x98, 0xd0,
- 0x78, 0x83, 0xda, 0xea, 0x5e, 0x17, 0x37, 0x30, 0xcf, 0xb0, 0x5c, 0xec, 0xa1, 0xee, 0x70, 0xd5,
- 0x19, 0x0d, 0x86, 0x07, 0x2f, 0x4a, 0x97, 0x5e, 0xa2, 0xf4, 0x53, 0x4b, 0x38, 0x15, 0x53, 0x5b,
- 0xe5, 0xa1, 0x08, 0x43, 0xf8, 0x44, 0x04, 0x5e, 0xe4, 0xf7, 0x68, 0xcf, 0x85, 0xca, 0x25, 0x10,
- 0xed, 0xcc, 0xfa, 0x69, 0x1a, 0x39, 0x51, 0x1f, 0x92, 0xbd, 0xbe, 0xc7, 0x90, 0x1e, 0xb8, 0xde,
- 0x26, 0x2b, 0xc7, 0x5e, 0xb9, 0x2c, 0x36, 0x51, 0xe2, 0x6e, 0x1c, 0xe0, 0xd6, 0x4c, 0x0c, 0x11,
- 0x0d, 0x8f, 0x47, 0x6d, 0xb5, 0xc2, 0xb1, 0xfb, 0x0a, 0xef, 0xec, 0x0e, 0x2b, 0x00, 0xef, 0x1f,
- 0x0d, 0x5b, 0xd8, 0x6a, 0xba, 0xdb, 0x09, 0x3c, 0x6c, 0x50, 0x7a, 0x80, 0xda, 0xd1, 0xbc, 0x11,
- 0x91, 0xd6, 0x6c, 0xf5, 0x04, 0x9b, 0x0c, 0xbc, 0xc9, 0x15, 0x7e, 0x03, 0xbe, 0xe6, 0x6a, 0x31,
- 0x23, 0xef, 0x02, 0xfb, 0xb6, 0xc4, 0xfa, 0xf7, 0xe0, 0xf7, 0x29, 0x7f, 0x75, 0x71, 0x4d, 0x07,
- 0xea, 0x81, 0xea, 0x16, 0x70, 0xd6, 0xea, 0xb1, 0x6b, 0x44, 0x7d, 0xe8, 0xeb, 0x14, 0xfb, 0x7e,
- 0xd8, 0x68, 0xb4, 0x41, 0x60, 0x47, 0xa9, 0x93, 0xc5, 0x78, 0xc2, 0xc7, 0xb5, 0xcd, 0xe7, 0x6f,
- 0x11, 0x9c, 0x72, 0x6b, 0x99, 0x9f, 0xc0, 0x9c, 0x32, 0x01, 0x64, 0x1b, 0x7f, 0x0d, 0x00, 0xbf,
- 0x1d, 0xa1, 0x81, 0x51, 0x0f, 0x96, 0x2e, 0x02, 0x80, 0x26, 0xc1, 0x90, 0x70, 0x81, 0xfd, 0x20,
- 0x79, 0xd1, 0x61, 0x06, 0x0a, 0xab, 0x43, 0x02, 0xc1, 0x80, 0x0e, 0xbb, 0x1a, 0xb1, 0xfa, 0x98,
- 0x64, 0xcc, 0xbb, 0xe3, 0xf3, 0x58, 0x23, 0x7e, 0xfa, 0x91, 0x22, 0x5e, 0x61, 0x11, 0xe5, 0xff,
- 0xfa, 0xe5, 0x64, 0xa4
-};
-
-fastimage_t bfin_logo = {
- DEF_BFIN_LOGO_DATA,
- DEF_BFIN_LOGO_WIDTH,
- DEF_BFIN_LOGO_HEIGHT,
- DEF_BFIN_LOGO_BPP,
- DEF_BFIN_LOGO_PIXEL_SIZE,
- DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
deleted file mode 100644
index c5b0be96f192..000000000000
--- a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
+++ /dev/null
@@ -1,1242 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where: 'screen' is the pointer to the frame buffer
- * 'width' is the screen width
- * 'x' is the horizontal position
- * 'y' is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 19303
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define DEF_BFIN_LOGO_WIDTH 230
-#define DEF_BFIN_LOGO_HEIGHT 230
-#define DEF_BFIN_LOGO_PIXELS 52900
-#define DEF_BFIN_LOGO_BPP 16
-#define DEF_BFIN_LOGO_PIXEL_SIZE 2
-#define DEF_BFIN_LOGO_SIZE 105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77,
- 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6,
- 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb,
- 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38,
- 0x20, 0x85, 0x23, 0x48, 0x45, 0x24, 0x77, 0x65, 0x09, 0x55, 0x59, 0x97, 0x53, 0x2d, 0x99, 0x53,
- 0x39, 0x99, 0x3f, 0xd2, 0x42, 0x6e, 0x49, 0xcc, 0x4a, 0x41, 0x35, 0x52, 0x90, 0x1c, 0xa9, 0xd9,
- 0x9a, 0xdb, 0x90, 0x18, 0xa9, 0xd6, 0xc5, 0x52, 0xb9, 0x3b, 0x77, 0xc5, 0xea, 0x9c, 0x86, 0xe6,
- 0x72, 0xdf, 0x37, 0x5f, 0x0f, 0xe3, 0xdf, 0x36, 0xb6, 0x93, 0xb4, 0x61, 0x3e, 0x5f, 0x85, 0xc4,
- 0x63, 0x67, 0xfc, 0xb5, 0x3f, 0xbc, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0x3d, 0x89, 0x44, 0x84,
- 0x88, 0x1f, 0x32, 0xe8, 0x34, 0x43, 0xc4, 0x8f, 0x05, 0x98, 0x2f, 0x2d, 0xa1, 0x25, 0x3a, 0x88,
- 0x7e, 0xb2, 0x9f, 0x74, 0xc6, 0x0c, 0x78, 0xdc, 0x81, 0xae, 0xc3, 0xb3, 0x22, 0xab, 0x3f, 0x64,
- 0x60, 0x0e, 0x81, 0x41, 0x27, 0xb9, 0x40, 0x05, 0xa9, 0x12, 0x99, 0x5c, 0xd6, 0xa4, 0xea, 0x54,
- 0x0f, 0x6e, 0x8e, 0x4e, 0x55, 0x93, 0x4a, 0x2e, 0x2b, 0x91, 0x05, 0x29, 0x27, 0xc7, 0x2a, 0xe6,
- 0x54, 0xc4, 0x0f, 0x0b, 0x3c, 0x8b, 0x0b, 0x88, 0xc1, 0x26, 0xd5, 0xa0, 0x7a, 0x91, 0x0d, 0xb1,
- 0x4a, 0x5d, 0x97, 0x7e, 0xc8, 0xb0, 0x64, 0x14, 0xc6, 0x94, 0x61, 0xc8, 0xd0, 0xac, 0x27, 0x74,
- 0x8b, 0xec, 0xa0, 0xba, 0x49, 0x85, 0x39, 0xed, 0x10, 0xf9, 0xfc, 0xc1, 0x00, 0x4b, 0x23, 0x66,
- 0xb1, 0x53, 0x35, 0xc9, 0x12, 0x88, 0xc1, 0x25, 0x63, 0xa9, 0xb9, 0xd5, 0xd2, 0x6a, 0x29, 0x35,
- 0x4f, 0x19, 0xba, 0xf4, 0xc0, 0x1e, 0xcf, 0xec, 0x9a, 0xb1, 0xd5, 0xd2, 0x6d, 0x61, 0xcc, 0x4b,
- 0xc6, 0x21, 0x83, 0x12, 0x71, 0xda, 0x89, 0x18, 0x5d, 0xa0, 0xfa, 0x49, 0x51, 0xe7, 0x3e, 0x69,
- 0x60, 0x69, 0x74, 0x92, 0x41, 0xaa, 0x49, 0xb5, 0x88, 0xd8, 0x9a, 0x42, 0x5c, 0x95, 0x9a, 0x4b,
- 0xcd, 0xcd, 0xfa, 0x41, 0xb5, 0x93, 0x4c, 0xf7, 0xbf, 0x3a, 0x08, 0xb9, 0x4c, 0xa9, 0x83, 0x57,
- 0xae, 0x21, 0x59, 0x6d, 0xd6, 0x2f, 0xb2, 0x20, 0xa3, 0x58, 0x42, 0x1f, 0xe7, 0xec, 0x45, 0x08,
- 0xa0, 0x25, 0xc0, 0x23, 0x48, 0x63, 0x88, 0xed, 0xd2, 0xaf, 0x19, 0xd7, 0x90, 0x0e, 0x25, 0x74,
- 0x72, 0x19, 0x9d, 0xe3, 0xff, 0x5e, 0xa0, 0x16, 0x59, 0x90, 0xd4, 0x35, 0x63, 0x97, 0x3e, 0x84,
- 0x24, 0x34, 0x18, 0x95, 0x4f, 0x11, 0x8f, 0x17, 0x58, 0xaf, 0x06, 0x29, 0xe0, 0x71, 0xc8, 0x00,
- 0x12, 0xa6, 0xd4, 0x35, 0xa9, 0x3a, 0xb6, 0x2c, 0x57, 0x5a, 0x24, 0xa3, 0x84, 0x0e, 0x74, 0xf2,
- 0x90, 0x21, 0x84, 0xe4, 0x73, 0x41, 0xe4, 0xf3, 0x31, 0x03, 0x4b, 0xa4, 0x5c, 0xb6, 0x88, 0xe4,
- 0x91, 0x31, 0xaf, 0x1d, 0x0f, 0xb1, 0x25, 0x32, 0xba, 0x80, 0xbb, 0x05, 0xa9, 0x10, 0x8b, 0x75,
- 0xf3, 0xa4, 0x1a, 0x6b, 0xdb, 0xfc, 0xef, 0x26, 0x62, 0x2b, 0x00, 0x26, 0x17, 0xd0, 0x0a, 0x49,
- 0xa0, 0x35, 0xaf, 0xdb, 0xd2, 0xac, 0x5f, 0xa0, 0xe8, 0x22, 0xdc, 0x73, 0x81, 0x52, 0xea, 0xba,
- 0x2d, 0x53, 0x86, 0x90, 0x16, 0xa4, 0x53, 0x64, 0xf3, 0x71, 0x00, 0x98, 0x0c, 0x52, 0x83, 0xea,
- 0x66, 0x24, 0x91, 0xa5, 0xe6, 0x42, 0xe4, 0x31, 0xf9, 0xce, 0x25, 0x32, 0xb0, 0x88, 0xba, 0x38,
- 0xe9, 0x14, 0x75, 0xed, 0xa3, 0x06, 0x66, 0x72, 0x52, 0x3d, 0x64, 0x60, 0xd0, 0x0a, 0x47, 0x17,
- 0x7c, 0xaf, 0x44, 0xf9, 0xd3, 0x12, 0xa0, 0x6d, 0xa7, 0x8c, 0x21, 0x56, 0x8e, 0x74, 0xad, 0xc8,
- 0xe6, 0xa3, 0x03, 0x2f, 0x93, 0x60, 0xed, 0x84, 0xd8, 0xc2, 0x76, 0x10, 0xb4, 0xe4, 0x1a, 0x75,
- 0x42, 0x35, 0xa0, 0xde, 0x27, 0x3b, 0x4b, 0xd2, 0x71, 0xd7, 0x3b, 0x55, 0x60, 0xdb, 0x12, 0xc8,
- 0x96, 0x02, 0x36, 0x0b, 0x9b, 0xb1, 0x88, 0x74, 0xd0, 0x22, 0x8b, 0xa7, 0x53, 0xd5, 0xa5, 0x2f,
- 0x35, 0x2f, 0x16, 0xc8, 0xa4, 0x44, 0x72, 0x80, 0x38, 0xa8, 0x7a, 0x41, 0xf7, 0xbe, 0xe1, 0x90,
- 0xde, 0xcb, 0x26, 0xf2, 0x19, 0xa4, 0xa6, 0xd0, 0x6f, 0x0b, 0xec, 0x6f, 0x44, 0x36, 0x1f, 0x0d,
- 0x68, 0x49, 0x3f, 0x89, 0x77, 0xf9, 0x85, 0xca, 0x24, 0xa0, 0x83, 0x70, 0xa9, 0xaf, 0x1b, 0x5b,
- 0x2c, 0x2d, 0x96, 0x6f, 0x8c, 0x87, 0xf4, 0xe7, 0xd4, 0xd7, 0xe2, 0x2c, 0x28, 0x27, 0x39, 0x65,
- 0x04, 0xd9, 0x97, 0x73, 0xeb, 0x66, 0xa1, 0xef, 0x25, 0x22, 0x1e, 0xfc, 0x4a, 0xb9, 0x66, 0x1c,
- 0x32, 0x14, 0xe3, 0xdb, 0x3d, 0x4b, 0xde, 0x65, 0x77, 0x9a, 0xc3, 0xf6, 0x5f, 0x0e, 0xfb, 0xec,
- 0x8c, 0xf9, 0x7d, 0x83, 0x97, 0x0d, 0xc6, 0xb1, 0xb9, 0x40, 0x81, 0x07, 0x77, 0x11, 0x5d, 0x15,
- 0x6d, 0xda, 0x62, 0x83, 0xd7, 0xaf, 0x8c, 0x39, 0xbd, 0x77, 0x6e, 0x2b, 0xf8, 0x84, 0x7c, 0x01,
- 0xed, 0x41, 0x0e, 0x0f, 0x8f, 0x8c, 0x1e, 0x8e, 0x61, 0xf3, 0x40, 0xcc, 0x6f, 0x49, 0x90, 0x02,
- 0x4f, 0xd2, 0xa4, 0x7a, 0x81, 0x12, 0x6d, 0xa0, 0x62, 0x02, 0xa4, 0xb2, 0x44, 0x46, 0xe8, 0x18,
- 0x73, 0xa7, 0xaa, 0x38, 0x77, 0xbc, 0x46, 0xbd, 0xa9, 0x9f, 0xb6, 0x9e, 0x1c, 0xfe, 0x60, 0xf4,
- 0xa5, 0x81, 0x69, 0x7b, 0x8b, 0xe5, 0xba, 0x51, 0xa9, 0x4b, 0xd4, 0xb4, 0x9d, 0x2a, 0xd8, 0xa1,
- 0x74, 0x8a, 0x36, 0x50, 0x51, 0x01, 0x52, 0x39, 0xa8, 0x06, 0xdf, 0x39, 0x5d, 0xa4, 0x3b, 0xfe,
- 0x85, 0xec, 0x7d, 0xc3, 0xb4, 0x95, 0x1c, 0x08, 0xdb, 0xcf, 0x5b, 0xab, 0xcd, 0xd7, 0x8d, 0x6f,
- 0xea, 0xff, 0x12, 0x71, 0xf9, 0x75, 0x9c, 0x64, 0x6a, 0x09, 0xa5, 0x0e, 0x6c, 0x20, 0xd8, 0x6d,
- 0x16, 0xeb, 0x7d, 0x45, 0x14, 0x5b, 0x2a, 0x69, 0xc9, 0x0e, 0xc4, 0x25, 0x58, 0x3e, 0x3b, 0xcd,
- 0x9f, 0x22, 0x5b, 0xf6, 0x2e, 0x7b, 0x0e, 0xed, 0x4e, 0xae, 0x25, 0xad, 0x8d, 0x4e, 0x12, 0xf4,
- 0xec, 0x20, 0xa7, 0x67, 0x8b, 0xf3, 0xce, 0xdb, 0x1d, 0x60, 0xc1, 0x36, 0xa9, 0x20, 0xae, 0xdc,
- 0x5f, 0x94, 0xb5, 0x12, 0x73, 0x79, 0x48, 0x8f, 0xa4, 0xd1, 0xf0, 0x8c, 0xce, 0x85, 0x58, 0xfc,
- 0x9a, 0x3a, 0x4b, 0x1e, 0x48, 0xb9, 0x2a, 0x0e, 0xaa, 0x5b, 0x2d, 0x4a, 0x9d, 0x5c, 0x94, 0xcc,
- 0x22, 0x41, 0x4b, 0x2c, 0x80, 0x05, 0x7b, 0x3c, 0xc4, 0xd2, 0x45, 0xbb, 0xe7, 0xd7, 0x94, 0x97,
- 0xbd, 0xcb, 0x9e, 0x50, 0x01, 0x8b, 0x99, 0xee, 0x4a, 0x4b, 0x20, 0xca, 0x39, 0x29, 0x4a, 0x66,
- 0x91, 0x80, 0x35, 0xec, 0xda, 0xf1, 0x12, 0x59, 0xf1, 0xee, 0x79, 0x96, 0xdc, 0x21, 0xfb, 0x84,
- 0x3c, 0x90, 0x03, 0x3f, 0x41, 0xaa, 0xdb, 0xa2, 0xd4, 0x8b, 0x92, 0x59, 0x0c, 0x60, 0x0d, 0xdb,
- 0x65, 0xe8, 0x32, 0x14, 0x4b, 0xc3, 0xe2, 0xbb, 0xd2, 0x39, 0xbf, 0x72, 0xca, 0x20, 0x4a, 0x66,
- 0x71, 0x40, 0x4b, 0xc0, 0x86, 0x5d, 0x32, 0x12, 0x3a, 0xfa, 0x09, 0xcd, 0x40, 0x2e, 0x63, 0xcc,
- 0x4a, 0x64, 0xcd, 0x8a, 0x5e, 0x83, 0x42, 0x01, 0xab, 0xe5, 0x22, 0xbb, 0x86, 0x24, 0xe3, 0x49,
- 0xcd, 0xa0, 0x83, 0x80, 0x0c, 0x3e, 0xd8, 0x67, 0xd2, 0x4f, 0x6a, 0x0a, 0x4f, 0x09, 0xb4, 0x44,
- 0x90, 0x82, 0x3c, 0x0e, 0x79, 0x11, 0x57, 0xcb, 0xad, 0x81, 0x96, 0x4c, 0xaa, 0xc1, 0x9f, 0x1f,
- 0x14, 0xb5, 0x6c, 0x41, 0xa0, 0xb9, 0xbc, 0xb9, 0x66, 0xfd, 0x94, 0x61, 0x81, 0x7a, 0x72, 0xb3,
- 0x08, 0x52, 0x4b, 0x46, 0xd8, 0x99, 0x88, 0x5a, 0xb6, 0x10, 0x00, 0x97, 0xb0, 0xb7, 0x1c, 0x32,
- 0x6c, 0x3d, 0x33, 0xab, 0x78, 0xe8, 0x20, 0x94, 0x7a, 0xf0, 0x19, 0x88, 0x5a, 0xb6, 0x10, 0x80,
- 0x15, 0xdb, 0xa9, 0x9a, 0x32, 0x34, 0xeb, 0x9f, 0xec, 0x3c, 0x20, 0x42, 0xb3, 0xc8, 0x8a, 0xb6,
- 0x6c, 0x21, 0xe0, 0xad, 0x58, 0xa5, 0xee, 0xc9, 0xce, 0xa3, 0x44, 0x06, 0x73, 0x00, 0x5b, 0xf6,
- 0xc9, 0xce, 0xe3, 0xc7, 0x0c, 0x2d, 0xe1, 0xe4, 0xa2, 0x96, 0x21, 0x36, 0xf5, 0xf3, 0x07, 0x88,
- 0x7f, 0x20, 0x72, 0xd9, 0xf1, 0x27, 0xc3, 0x49, 0x1e, 0x54, 0x4d, 0xb2, 0x93, 0xea, 0x60, 0x4e,
- 0x79, 0x7c, 0x1d, 0x04, 0xe8, 0x79, 0xc8, 0xc1, 0xcd, 0xe5, 0xd5, 0x22, 0x52, 0x81, 0xdf, 0x91,
- 0x2c, 0xa6, 0xe4, 0xf2, 0x00, 0xf1, 0x35, 0x75, 0x50, 0x75, 0x42, 0x75, 0x50, 0xf5, 0xc9, 0x96,
- 0xfd, 0x08, 0x10, 0x8d, 0x6e, 0xb1, 0x84, 0xed, 0xd3, 0xf6, 0xeb, 0xc6, 0x1d, 0x39, 0xd8, 0xc8,
- 0x4a, 0x64, 0x4b, 0x8b, 0x2b, 0x66, 0x21, 0x00, 0x2e, 0x43, 0x88, 0xcb, 0xc1, 0x34, 0xbb, 0xcb,
- 0x6b, 0x94, 0x4b, 0x7d, 0x48, 0xff, 0xa9, 0xe1, 0x4d, 0xfd, 0x09, 0xd5, 0x56, 0xe5, 0x13, 0xec,
- 0xaa, 0x17, 0x74, 0x61, 0xfb, 0xc9, 0xe1, 0x69, 0x7b, 0xf6, 0x08, 0x8c, 0xb8, 0x62, 0x16, 0x0a,
- 0xd8, 0x5d, 0x86, 0xb4, 0x6b, 0xc6, 0xa6, 0xb4, 0xdf, 0xf5, 0x59, 0xf2, 0x9c, 0xfa, 0x53, 0x43,
- 0xb7, 0xa5, 0xc5, 0x72, 0x97, 0xcd, 0xb6, 0x9a, 0x41, 0x9e, 0x49, 0xa7, 0xea, 0x19, 0x9d, 0x52,
- 0x07, 0x27, 0x0e, 0xe0, 0xcc, 0x1e, 0xac, 0xc7, 0x3b, 0xcd, 0x90, 0x5b, 0x90, 0x4d, 0x36, 0x21,
- 0x7b, 0x56, 0x5c, 0x31, 0x0b, 0x01, 0xf6, 0x14, 0xac, 0xa5, 0xf0, 0x14, 0x00, 0x2f, 0x70, 0xe2,
- 0x0e, 0xbe, 0xdb, 0x6b, 0xd4, 0x21, 0x3d, 0xb0, 0xe9, 0x52, 0xd3, 0x19, 0xee, 0x34, 0xa8, 0xde,
- 0x69, 0x7e, 0x69, 0xe0, 0xe4, 0xe8, 0xc8, 0xe8, 0x25, 0xf4, 0xe7, 0x83, 0xd1, 0xc3, 0xc3, 0x17,
- 0xac, 0x8b, 0x2c, 0x9c, 0x67, 0x58, 0x33, 0x1e, 0x1e, 0xde, 0x69, 0xce, 0x2c, 0xd7, 0x1d, 0xc4,
- 0xda, 0xf1, 0x2e, 0xd1, 0xc7, 0x5e, 0x00, 0x52, 0x73, 0x09, 0x59, 0xac, 0x4b, 0xc6, 0x0b, 0xd6,
- 0x1b, 0xf6, 0x0b, 0x56, 0xc8, 0x65, 0x85, 0x6c, 0xb9, 0x10, 0xdb, 0x6d, 0xf9, 0x26, 0xed, 0xca,
- 0xa7, 0x25, 0xa6, 0x0c, 0x87, 0x87, 0xd7, 0x1d, 0x1a, 0x77, 0x8f, 0x7b, 0x6c, 0x06, 0x46, 0x8f,
- 0xbb, 0xcd, 0x5d, 0xe6, 0x1a, 0x19, 0x9d, 0x32, 0xc0, 0xe9, 0x4d, 0xc6, 0x1c, 0xb6, 0x9f, 0xc8,
- 0xa2, 0x67, 0xa7, 0x8c, 0x53, 0x86, 0x4e, 0x95, 0xc8, 0x65, 0xbe, 0xe0, 0xb9, 0x8c, 0x8f, 0x77,
- 0x0d, 0xaa, 0xc3, 0xf6, 0x75, 0x47, 0x1b, 0xe2, 0x05, 0x18, 0x59, 0x77, 0x74, 0x5b, 0x20, 0x5f,
- 0x4e, 0xa9, 0xfb, 0xc6, 0x98, 0x5a, 0x32, 0xb5, 0xc4, 0x75, 0xe3, 0xba, 0x63, 0x6c, 0x26, 0xe2,
- 0xa1, 0xbc, 0xac, 0xb7, 0xdd, 0x87, 0x47, 0x9d, 0x97, 0xf2, 0xce, 0x7a, 0xd6, 0x1d, 0x90, 0xd9,
- 0xb7, 0x40, 0x41, 0x6e, 0x65, 0x66, 0xc9, 0xe4, 0xad, 0x1f, 0x71, 0xc5, 0xcc, 0x0f, 0xbc, 0x37,
- 0x36, 0x18, 0xe3, 0xc1, 0x93, 0xcb, 0xc2, 0xf6, 0x36, 0xf7, 0xb2, 0xa7, 0xce, 0xcb, 0x73, 0xb2,
- 0xec, 0x09, 0xdb, 0x9d, 0xe4, 0x35, 0xea, 0x0b, 0xf6, 0x84, 0x8a, 0x4e, 0x71, 0x97, 0x21, 0x43,
- 0x99, 0x8b, 0xf2, 0x9e, 0xf6, 0xcd, 0xf9, 0x57, 0x02, 0x1b, 0x81, 0x8d, 0xbb, 0xe5, 0xa1, 0xef,
- 0xd1, 0xdf, 0x2b, 0x68, 0x8c, 0xfb, 0x29, 0xef, 0x6e, 0x17, 0x58, 0xc9, 0x4e, 0xd2, 0xcb, 0x5e,
- 0xcb, 0xe8, 0x27, 0x1c, 0xe4, 0xbc, 0xb2, 0xa2, 0xf5, 0x93, 0x2f, 0x78, 0x2e, 0x05, 0x6f, 0x2c,
- 0xc8, 0xd8, 0xd8, 0x4c, 0xbb, 0x6f, 0x25, 0x50, 0x1e, 0x6a, 0x40, 0xc3, 0x14, 0x6e, 0x08, 0x7d,
- 0x7f, 0x77, 0xdc, 0x4f, 0x0e, 0x68, 0x89, 0xd4, 0x79, 0x1e, 0x8b, 0x6c, 0x99, 0x6b, 0xdc, 0xdf,
- 0x10, 0xea, 0x0d, 0x4f, 0x44, 0x26, 0x22, 0xf3, 0xdc, 0x98, 0xe0, 0x46, 0x6f, 0xd8, 0x14, 0x2e,
- 0x0f, 0xd9, 0x7c, 0x23, 0xa3, 0x20, 0xf7, 0x07, 0xb2, 0xec, 0x54, 0x4b, 0x64, 0x8c, 0x39, 0x24,
- 0x7a, 0xd8, 0xf3, 0x46, 0xb2, 0x5c, 0xca, 0x65, 0x6d, 0xee, 0x39, 0xbf, 0x29, 0x0c, 0xac, 0xac,
- 0x3e, 0xe4, 0xc7, 0x7c, 0xa4, 0x3c, 0x74, 0xc1, 0x9a, 0xea, 0x5b, 0xee, 0x27, 0xc3, 0xf6, 0x8d,
- 0xc0, 0x04, 0x7a, 0x6d, 0x2a, 0xc0, 0xff, 0x34, 0x85, 0xdb, 0x7d, 0x6b, 0xc6, 0xec, 0x0c, 0x39,
- 0xc9, 0x56, 0x0b, 0x21, 0x5a, 0xb2, 0x79, 0x83, 0xe7, 0x92, 0x5f, 0x2f, 0x69, 0xa4, 0x2f, 0x57,
- 0x10, 0x33, 0xa9, 0x78, 0xb1, 0xf9, 0x52, 0x79, 0x14, 0x94, 0x3a, 0x9b, 0x2f, 0x35, 0x8f, 0x02,
- 0x7a, 0xc3, 0xcb, 0x9e, 0xec, 0x31, 0x35, 0x5a, 0xd2, 0x6d, 0x11, 0x77, 0x25, 0xf9, 0x23, 0x91,
- 0xcb, 0x0e, 0xa2, 0xcc, 0x35, 0x1f, 0x65, 0x72, 0x23, 0x30, 0xe7, 0xef, 0x0d, 0xc7, 0x72, 0x32,
- 0x9d, 0x24, 0x99, 0x1d, 0xc4, 0x0d, 0x7b, 0x3c, 0xf3, 0xe5, 0xa1, 0x88, 0x67, 0x76, 0x86, 0xf2,
- 0x36, 0x84, 0x62, 0xaf, 0x9a, 0xc2, 0xd3, 0xd6, 0xec, 0xb3, 0xe9, 0xb6, 0x36, 0xeb, 0xc5, 0xc8,
- 0x57, 0xbe, 0x48, 0xe4, 0xd2, 0x49, 0x8e, 0xfb, 0xb1, 0x24, 0x85, 0xed, 0x21, 0x76, 0x52, 0xdd,
- 0xa5, 0x5f, 0x77, 0x08, 0x5c, 0xd9, 0x7c, 0x89, 0xd2, 0x25, 0x97, 0x2d, 0x7b, 0x62, 0x19, 0x3b,
- 0x39, 0x0c, 0xa7, 0xf1, 0xa0, 0x8a, 0x93, 0x52, 0x27, 0xfc, 0x56, 0x80, 0xae, 0xb5, 0xf9, 0xe8,
- 0xac, 0xb3, 0x11, 0xb9, 0x2c, 0x04, 0x89, 0xfb, 0xcb, 0x05, 0x0a, 0x24, 0x71, 0xf5, 0xe1, 0x05,
- 0x2b, 0xaf, 0xe9, 0xfa, 0xc9, 0x1b, 0x76, 0x9e, 0x93, 0xf9, 0x48, 0x62, 0x26, 0xc9, 0xa4, 0x7a,
- 0x23, 0xc0, 0xf3, 0x35, 0x1f, 0x39, 0x39, 0x8c, 0xf3, 0xbf, 0x76, 0xc8, 0x7c, 0xf6, 0x9d, 0xe6,
- 0x26, 0xd5, 0x4d, 0x87, 0xa0, 0x7d, 0x27, 0x22, 0xe9, 0x7d, 0x4b, 0x3c, 0x44, 0x1d, 0x5b, 0x08,
- 0x12, 0xb9, 0x0c, 0x52, 0xc0, 0xdb, 0xec, 0x0c, 0x3c, 0x3e, 0x4b, 0x4e, 0x5b, 0x47, 0x46, 0xbb,
- 0x0c, 0x1d, 0x44, 0x9b, 0x9b, 0x97, 0x2e, 0x9e, 0x4b, 0x3e, 0xcf, 0x6e, 0x91, 0x15, 0xb4, 0x70,
- 0xc4, 0xc3, 0x4b, 0xf7, 0x41, 0x55, 0x99, 0xab, 0xc7, 0xed, 0xb3, 0x97, 0xc8, 0xda, 0x7d, 0x82,
- 0xd4, 0x8e, 0x8c, 0x66, 0x9e, 0x4b, 0xbf, 0x68, 0xfb, 0x14, 0x04, 0xcc, 0x65, 0xe9, 0xe6, 0xe9,
- 0x03, 0xcc, 0x65, 0xd8, 0x0e, 0xeb, 0xa2, 0x93, 0x1c, 0x19, 0xed, 0x71, 0x6b, 0xdc, 0x83, 0xea,
- 0x49, 0xf5, 0x6a, 0x0c, 0x97, 0x50, 0x19, 0xc4, 0xa5, 0xf6, 0xb2, 0x3b, 0x64, 0xe0, 0x0d, 0x9a,
- 0xd8, 0x94, 0xd9, 0xb0, 0x9d, 0xbf, 0x6b, 0x07, 0xc1, 0x98, 0x8f, 0xb8, 0xdb, 0xdc, 0x21, 0x76,
- 0xc9, 0x28, 0x70, 0xb9, 0xec, 0xc9, 0x3c, 0x97, 0x20, 0xc5, 0x58, 0xc4, 0x3d, 0x49, 0xfe, 0x48,
- 0xc5, 0xe5, 0xea, 0xc3, 0x6e, 0x0b, 0x7e, 0xee, 0xba, 0x11, 0x7c, 0x3f, 0xad, 0x96, 0xfe, 0xe8,
- 0x2a, 0x8a, 0xb9, 0x84, 0xe8, 0x07, 0x63, 0x86, 0xb3, 0x22, 0x50, 0x3b, 0x8d, 0xd7, 0xbf, 0xa6,
- 0x70, 0x6c, 0x6e, 0xc2, 0x02, 0xe5, 0xb3, 0x6b, 0x5c, 0x9f, 0x1a, 0x16, 0x28, 0x41, 0x07, 0xb7,
- 0xfb, 0x32, 0xcf, 0x45, 0x2e, 0x13, 0x33, 0xb8, 0x0a, 0x01, 0x17, 0x27, 0x61, 0x4b, 0xcd, 0x7c,
- 0xcc, 0x2b, 0x48, 0xc1, 0x4e, 0xb1, 0xd5, 0x82, 0x1f, 0x39, 0x49, 0x9f, 0xbd, 0xc7, 0x7d, 0x69,
- 0xd4, 0x49, 0x6a, 0x5c, 0xb1, 0x72, 0xb9, 0x43, 0x76, 0x97, 0xed, 0xd2, 0x5f, 0x37, 0x76, 0xe9,
- 0x0f, 0xe9, 0x79, 0xb9, 0x2c, 0x0f, 0xc5, 0xc7, 0xb5, 0x4a, 0x64, 0xcd, 0x7a, 0xf0, 0xfc, 0x95,
- 0xb9, 0x04, 0xcb, 0x29, 0xf3, 0x5c, 0x3a, 0xd5, 0x6b, 0x62, 0xce, 0x73, 0x01, 0xc0, 0xf1, 0xcb,
- 0x52, 0x33, 0xbf, 0x0e, 0x2e, 0x50, 0x26, 0xb4, 0xfe, 0x75, 0x5b, 0xf8, 0xe7, 0x9b, 0xf5, 0x6d,
- 0xee, 0x9b, 0x0e, 0xd0, 0xb6, 0xf1, 0xb6, 0x0f, 0xae, 0xe7, 0x74, 0x96, 0x5c, 0x64, 0xf9, 0xbd,
- 0xc7, 0x46, 0x20, 0xf1, 0x0c, 0x03, 0xcd, 0xfd, 0x99, 0xb6, 0xe6, 0xca, 0xe5, 0xa0, 0x7a, 0x4d,
- 0x8c, 0x46, 0x17, 0x00, 0x9c, 0x57, 0x00, 0xba, 0x0d, 0x3f, 0xc6, 0x7b, 0x12, 0xf0, 0xd7, 0xe1,
- 0xc7, 0x4d, 0xaa, 0xc3, 0xc3, 0xe4, 0x40, 0x7f, 0x94, 0xcb, 0x58, 0xd9, 0xa3, 0xb9, 0x9f, 0x41,
- 0x8a, 0xb7, 0x8b, 0xca, 0x43, 0xa9, 0xec, 0x54, 0x5a, 0xd2, 0x6a, 0xe1, 0xb9, 0xac, 0xf3, 0x66,
- 0x9e, 0x0b, 0xe4, 0x1d, 0x89, 0x5c, 0xe6, 0x8f, 0xe8, 0x19, 0x2f, 0x63, 0x48, 0x8b, 0x1f, 0x77,
- 0x10, 0x37, 0x1d, 0x0f, 0x1f, 0xf6, 0xb8, 0x05, 0x9f, 0x5e, 0xa7, 0xea, 0xa0, 0x4a, 0x4b, 0xac,
- 0x3b, 0x56, 0x23, 0x7d, 0xab, 0x9f, 0x9f, 0xe9, 0xfe, 0xd9, 0xae, 0x7d, 0x17, 0xf7, 0xed, 0x61,
- 0xea, 0x98, 0x76, 0x34, 0x66, 0xf6, 0x5d, 0xd8, 0xfb, 0xa7, 0xa3, 0xc7, 0x96, 0xff, 0x25, 0x0c,
- 0x5c, 0xa6, 0xca, 0x7c, 0xa7, 0x25, 0x61, 0x3b, 0xcf, 0x65, 0x9b, 0x3b, 0xf3, 0x5c, 0xa0, 0x5a,
- 0x8c, 0xa8, 0x63, 0xf3, 0x87, 0x70, 0x9a, 0x84, 0xbf, 0xd2, 0xa5, 0x5f, 0x45, 0xbc, 0xc4, 0xe7,
- 0xe5, 0xd1, 0x92, 0xd7, 0x3e, 0x6e, 0x18, 0xab, 0x6f, 0x7c, 0xa0, 0x38, 0x26, 0xed, 0x8b, 0x1b,
- 0x26, 0xe9, 0x03, 0xc5, 0xd1, 0x9a, 0xef, 0xbb, 0xff, 0x6f, 0xb6, 0x7c, 0x35, 0x55, 0x5e, 0x66,
- 0x07, 0x31, 0x3b, 0xc3, 0x73, 0x49, 0x0e, 0x64, 0x9e, 0x0b, 0xb6, 0x7d, 0x44, 0x2e, 0xf3, 0x05,
- 0x9f, 0x1f, 0x2b, 0x70, 0x17, 0xe2, 0x76, 0x8c, 0x23, 0xa3, 0xb1, 0xbb, 0xbc, 0xf7, 0x77, 0x7d,
- 0x77, 0xe4, 0x8c, 0xa2, 0x11, 0x31, 0xd7, 0x27, 0x9d, 0x78, 0x16, 0x8f, 0x3e, 0xe9, 0x6d, 0x45,
- 0xbd, 0xe2, 0xa8, 0xe2, 0x41, 0xc5, 0x04, 0xba, 0x7a, 0x47, 0xf1, 0x46, 0xdf, 0xff, 0xa4, 0xc8,
- 0xcb, 0x14, 0xf6, 0x2c, 0xc2, 0xde, 0x34, 0x1d, 0x20, 0x62, 0x1d, 0xe2, 0x2a, 0x8b, 0x14, 0xeb,
- 0xd3, 0x6d, 0x2f, 0xe0, 0x13, 0x7b, 0xb1, 0x5c, 0x36, 0xa9, 0x28, 0x2f, 0xec, 0x30, 0x96, 0x8c,
- 0xf8, 0xb1, 0x56, 0xf2, 0x5f, 0xcf, 0xd5, 0x31, 0x67, 0x14, 0xb7, 0x18, 0x1b, 0x33, 0xc7, 0x54,
- 0x54, 0xf2, 0x5c, 0x1e, 0x93, 0xde, 0x62, 0xde, 0xad, 0x7d, 0xb7, 0x96, 0x65, 0x10, 0x9b, 0xe8,
- 0xb1, 0x49, 0x7a, 0x4f, 0x5e, 0xfd, 0x93, 0x78, 0x3a, 0x4b, 0x62, 0x3c, 0x7c, 0x13, 0x91, 0x6c,
- 0xf2, 0xa6, 0x25, 0x5a, 0x2d, 0xe2, 0x79, 0xaf, 0xfc, 0x81, 0xec, 0x51, 0xee, 0x7c, 0xbb, 0xa0,
- 0x1f, 0x79, 0xcb, 0x73, 0x23, 0x00, 0x76, 0xce, 0x3f, 0x12, 0xbf, 0xde, 0xfb, 0x1e, 0x73, 0x55,
- 0x71, 0x46, 0xf1, 0x5a, 0xed, 0x6b, 0xb5, 0xb7, 0x98, 0x63, 0x9c, 0x5c, 0xce, 0x4b, 0xe7, 0xa5,
- 0x13, 0xd2, 0x0a, 0xc4, 0xe6, 0x87, 0xb5, 0x1f, 0xd6, 0x1e, 0x55, 0x4c, 0x48, 0xb1, 0xa4, 0xae,
- 0x54, 0x8c, 0x95, 0xff, 0xd3, 0xde, 0xe8, 0xd2, 0x2b, 0x59, 0x64, 0xc7, 0x66, 0x04, 0x1f, 0x5e,
- 0x9b, 0x9b, 0xce, 0x3a, 0x9b, 0x56, 0x4b, 0x97, 0xbe, 0x49, 0xcc, 0x12, 0xc9, 0x13, 0xfc, 0x79,
- 0x92, 0x2e, 0xbd, 0x20, 0x35, 0x4b, 0x46, 0xec, 0x97, 0xb3, 0xf9, 0x86, 0x75, 0xb5, 0xd5, 0x73,
- 0x88, 0xc9, 0x3e, 0xc4, 0x9b, 0x8d, 0x39, 0xaa, 0xe8, 0xe3, 0x99, 0xac, 0x9c, 0x7f, 0x11, 0xfd,
- 0x41, 0x7c, 0x36, 0x4a, 0xaf, 0x2a, 0x2a, 0xa4, 0x13, 0x9b, 0x9a, 0x77, 0x02, 0xe9, 0xe1, 0x2b,
- 0x15, 0xff, 0x2e, 0xff, 0xbc, 0xfe, 0xa7, 0x17, 0xbf, 0x0f, 0xfc, 0x7e, 0xd3, 0xb7, 0x6e, 0x0a,
- 0xa7, 0xcb, 0xda, 0x8c, 0xc5, 0x12, 0x97, 0xf1, 0x23, 0x5a, 0xb2, 0xf9, 0x21, 0xd5, 0xd9, 0x20,
- 0x5a, 0x72, 0x72, 0x18, 0xe2, 0xcf, 0x1f, 0xcf, 0xd7, 0x35, 0xdc, 0x62, 0x6e, 0x2b, 0x84, 0x35,
- 0x12, 0x0f, 0xc4, 0xe5, 0x8b, 0x51, 0x2e, 0x9f, 0x4d, 0x3b, 0x10, 0xcb, 0x47, 0x6b, 0xae, 0x74,
- 0xff, 0xfd, 0x8d, 0x63, 0xab, 0xab, 0x11, 0x53, 0xb8, 0xd5, 0x92, 0x8b, 0x45, 0x03, 0x9e, 0x61,
- 0xd1, 0x92, 0xcd, 0x17, 0x3c, 0x97, 0x53, 0x71, 0x27, 0xdc, 0x95, 0x3a, 0xd6, 0xdb, 0x30, 0x4d,
- 0x69, 0xee, 0x23, 0x26, 0x8f, 0xc5, 0x4a, 0x5d, 0x76, 0x2e, 0xa5, 0xa0, 0x7f, 0xe7, 0xa3, 0xff,
- 0x9e, 0x40, 0x56, 0xae, 0xbd, 0xb1, 0x77, 0xec, 0x37, 0x67, 0x82, 0x39, 0x9d, 0x08, 0x6c, 0x52,
- 0x89, 0x59, 0x22, 0xf9, 0x03, 0x9f, 0xbf, 0x84, 0x3e, 0x15, 0xb1, 0xe7, 0x2f, 0xcd, 0x92, 0xcf,
- 0x5e, 0xad, 0x6b, 0x78, 0xbe, 0x86, 0x63, 0x32, 0x99, 0xad, 0x4a, 0x8e, 0xcb, 0x64, 0x8e, 0xb9,
- 0x75, 0x74, 0x73, 0x6c, 0xbe, 0xbe, 0x42, 0xfa, 0x9a, 0x7c, 0x6d, 0x97, 0x36, 0xfd, 0x24, 0x36,
- 0xd1, 0x4f, 0x76, 0x8b, 0xd6, 0x4f, 0x01, 0xe0, 0xb9, 0x14, 0x24, 0xc7, 0x2c, 0x79, 0x71, 0x6f,
- 0xa4, 0xfa, 0x3e, 0x73, 0x07, 0xb4, 0x6b, 0x12, 0x97, 0x88, 0x31, 0x9e, 0xcb, 0x54, 0x4c, 0x56,
- 0x46, 0x87, 0x34, 0xf6, 0xf9, 0x63, 0xd2, 0xbd, 0x8a, 0xbf, 0xdd, 0x9b, 0x7d, 0x2e, 0x5a, 0x82,
- 0x31, 0x8b, 0xd6, 0x4f, 0xfe, 0x80, 0x8a, 0x30, 0xcd, 0x7a, 0x21, 0xb3, 0xe0, 0xb8, 0xe4, 0xd7,
- 0x3f, 0xa3, 0x98, 0x0d, 0xce, 0xe2, 0x49, 0x66, 0x32, 0x9d, 0x86, 0x9d, 0xe7, 0x2d, 0xa2, 0x17,
- 0xf9, 0x67, 0xe3, 0x9f, 0xef, 0x93, 0xfe, 0x8e, 0xc9, 0x2e, 0x99, 0x50, 0x53, 0x64, 0x4a, 0xcc,
- 0x91, 0xcd, 0x1b, 0xf1, 0xf5, 0x0a, 0x64, 0x92, 0xff, 0x7e, 0x8e, 0xd2, 0xdc, 0x62, 0xae, 0xd6,
- 0x98, 0xd2, 0x58, 0x36, 0x9b, 0x36, 0x6c, 0x22, 0xc3, 0x02, 0x93, 0x71, 0x5c, 0x9a, 0xa4, 0xdc,
- 0x9d, 0xa4, 0xb7, 0x15, 0x4b, 0xbb, 0xb2, 0xcf, 0x66, 0x91, 0x65, 0x44, 0xdf, 0x4f, 0xde, 0xc0,
- 0x51, 0xaf, 0xa5, 0xe8, 0xe9, 0xa0, 0x01, 0xe2, 0x72, 0xf5, 0x38, 0x73, 0xb4, 0xa6, 0xa2, 0x32,
- 0x95, 0x4c, 0x46, 0x39, 0xab, 0x8c, 0x5f, 0x2b, 0xe7, 0xf9, 0xab, 0x71, 0x4c, 0xe2, 0xf5, 0xd2,
- 0x58, 0x51, 0x56, 0xdd, 0xb3, 0xaf, 0x0f, 0xfd, 0xeb, 0x81, 0xe2, 0xef, 0x72, 0xd0, 0xb2, 0x41,
- 0xaa, 0x55, 0xcc, 0x13, 0xc9, 0x1b, 0x38, 0x52, 0xb2, 0x64, 0xc4, 0x11, 0x90, 0xae, 0x5d, 0xf7,
- 0xaa, 0x91, 0x54, 0xa6, 0xb2, 0x79, 0xe2, 0xb9, 0x4c, 0xbe, 0x96, 0x24, 0x93, 0xb7, 0x2b, 0xfe,
- 0x28, 0xff, 0x56, 0x65, 0xa8, 0xfa, 0x9d, 0x1c, 0xb4, 0xf5, 0x55, 0xc5, 0xbf, 0x3d, 0x97, 0x7d,
- 0x36, 0x70, 0x8e, 0x48, 0x5c, 0x31, 0xf3, 0x05, 0xf4, 0x0e, 0x99, 0xe4, 0xa2, 0x4d, 0xf0, 0xe8,
- 0xaf, 0xf7, 0xb2, 0xcc, 0xf3, 0x35, 0x0f, 0x92, 0xf6, 0x94, 0xf1, 0x96, 0x6a, 0x02, 0x93, 0x89,
- 0x2b, 0x25, 0x77, 0xdd, 0x8e, 0x24, 0xf2, 0x5b, 0xd5, 0xcb, 0xd5, 0xf7, 0xe5, 0xd8, 0x9a, 0x3d,
- 0x53, 0x73, 0x37, 0x07, 0x59, 0xeb, 0x20, 0xa0, 0xdf, 0x14, 0x54, 0xae, 0xa4, 0x1f, 0xf1, 0xe7,
- 0x7e, 0x1a, 0x41, 0x4b, 0xf0, 0x29, 0x77, 0xec, 0xf9, 0xfe, 0x2b, 0xc4, 0x65, 0x7d, 0x26, 0x0d,
- 0x1b, 0xbb, 0xdb, 0x48, 0xb4, 0x79, 0x84, 0x55, 0x52, 0x5a, 0xaf, 0x18, 0xa9, 0xfa, 0x56, 0xf5,
- 0x9e, 0xfc, 0x4e, 0x05, 0x6f, 0xfb, 0xdc, 0xcf, 0xc1, 0xf6, 0x01, 0x4c, 0xaa, 0xc5, 0x3d, 0x66,
- 0xbe, 0x80, 0xa8, 0x17, 0xae, 0x95, 0x04, 0x8f, 0x9a, 0x77, 0x51, 0x9c, 0x5c, 0xa6, 0xe1, 0xf2,
- 0xd9, 0xf9, 0x64, 0x76, 0x2b, 0x13, 0x25, 0xb2, 0x4f, 0x5a, 0x56, 0xad, 0xae, 0xfa, 0xac, 0x6a,
- 0x6f, 0x8c, 0x74, 0x37, 0x56, 0xb6, 0x33, 0x74, 0x4e, 0xf3, 0x81, 0xc8, 0x57, 0xb3, 0x5e, 0x2e,
- 0x56, 0x2e, 0xc8, 0x03, 0x98, 0xcb, 0xb5, 0x68, 0x3d, 0xbc, 0xe3, 0x92, 0x0f, 0xab, 0xe7, 0x98,
- 0x33, 0x69, 0xac, 0xd8, 0x04, 0x26, 0x05, 0xed, 0xba, 0x29, 0x91, 0x8d, 0x52, 0xa3, 0x42, 0x5d,
- 0xb5, 0xbf, 0x2a, 0xb2, 0x2f, 0xf6, 0x95, 0x7d, 0xd2, 0x33, 0x8a, 0x7f, 0x4e, 0xb0, 0x7c, 0xfa,
- 0xc9, 0x2e, 0xfd, 0x4e, 0x73, 0xf2, 0xc9, 0x79, 0xa8, 0x42, 0x21, 0xe6, 0x17, 0xe4, 0x07, 0xa1,
- 0x2a, 0x0c, 0x68, 0x35, 0x99, 0xe4, 0xc5, 0xbd, 0xf7, 0x6a, 0x29, 0x0d, 0x92, 0xcd, 0x8a, 0xd4,
- 0xb2, 0x99, 0xb4, 0x52, 0x56, 0xf2, 0x12, 0xd9, 0x28, 0xfd, 0x45, 0x85, 0xa6, 0x7a, 0x57, 0x95,
- 0xa6, 0xfa, 0x0d, 0x45, 0x3c, 0x93, 0x77, 0x14, 0x36, 0xcd, 0x7f, 0x26, 0x70, 0x06, 0xb5, 0x46,
- 0x7d, 0xf6, 0x69, 0xab, 0x52, 0x77, 0x2d, 0x61, 0x6d, 0x84, 0x9c, 0x15, 0x42, 0x27, 0x6a, 0xd9,
- 0xad, 0x43, 0xa8, 0xd6, 0x84, 0xf7, 0x01, 0x5f, 0x10, 0xa7, 0x6a, 0xef, 0xd5, 0x5e, 0xae, 0xa5,
- 0x18, 0x7b, 0x1a, 0x4d, 0x1b, 0x6f, 0x07, 0x61, 0x89, 0x3c, 0x26, 0xfd, 0x48, 0x3e, 0xbb, 0x6f,
- 0xd7, 0x7e, 0x4d, 0xf5, 0xeb, 0xf2, 0xbe, 0x04, 0x2f, 0xc1, 0x03, 0xc5, 0x2d, 0xe6, 0xa7, 0x47,
- 0xfe, 0x35, 0x21, 0x1b, 0x28, 0x48, 0xb5, 0x20, 0x2e, 0x81, 0x4d, 0x86, 0xeb, 0x54, 0x22, 0x30,
- 0x57, 0x22, 0x83, 0x1e, 0x8b, 0xe2, 0x69, 0xf7, 0x7c, 0xc0, 0xd5, 0x8f, 0xd5, 0x37, 0xeb, 0xb1,
- 0x77, 0x7d, 0x81, 0xfc, 0x9b, 0x57, 0xfd, 0xf5, 0x94, 0xe6, 0x72, 0xed, 0x87, 0xb5, 0xb7, 0xe4,
- 0xb7, 0x2b, 0xb2, 0x49, 0xe6, 0xc4, 0xb3, 0x15, 0xd2, 0xf7, 0xe4, 0x63, 0xfb, 0xfe, 0xa4, 0x5a,
- 0x47, 0xbb, 0x8f, 0xef, 0x63, 0x5f, 0x1f, 0x8d, 0x89, 0xcd, 0x31, 0xef, 0x1e, 0xf9, 0x7c, 0x38,
- 0xf1, 0x6c, 0xd0, 0x59, 0xf2, 0x53, 0xc3, 0xb4, 0x15, 0xd8, 0x04, 0x3e, 0x5b, 0x2c, 0xcf, 0xe8,
- 0x78, 0x36, 0xb5, 0x04, 0xf4, 0x40, 0x15, 0xe3, 0x25, 0xf9, 0x00, 0x57, 0x37, 0xec, 0xd2, 0xe3,
- 0xce, 0x24, 0x41, 0xea, 0x86, 0x7d, 0xf7, 0x5b, 0x91, 0xfa, 0xe7, 0x34, 0x2c, 0xf3, 0x4e, 0xed,
- 0x72, 0xf5, 0x51, 0x45, 0x5f, 0x06, 0x36, 0x1d, 0x15, 0x6d, 0xd5, 0x37, 0xab, 0x76, 0x55, 0xfd,
- 0x66, 0xbf, 0xb1, 0x22, 0x8e, 0x77, 0x69, 0x9f, 0xb4, 0xa2, 0xf2, 0xaa, 0xe2, 0xf9, 0x9a, 0x76,
- 0xcd, 0xe5, 0xb7, 0xde, 0x75, 0x41, 0x96, 0x6d, 0x62, 0xf5, 0x44, 0x2f, 0xcb, 0x73, 0x09, 0xa3,
- 0xdb, 0x72, 0x6e, 0x33, 0xc2, 0x09, 0xb6, 0x2c, 0x21, 0xfa, 0xd8, 0xf3, 0x00, 0xe6, 0x72, 0xc8,
- 0xe0, 0x8c, 0x9e, 0xeb, 0x79, 0x69, 0xe0, 0xb3, 0xd1, 0x23, 0xa7, 0x96, 0xeb, 0xdb, 0x35, 0xed,
- 0xcc, 0xbb, 0xd5, 0x6d, 0xb5, 0xef, 0x54, 0x2f, 0x57, 0xe3, 0x9c, 0xad, 0x89, 0xe8, 0x80, 0x7f,
- 0x97, 0x57, 0x8e, 0x55, 0xbf, 0x5d, 0x75, 0xb8, 0x4a, 0x5d, 0xd5, 0x53, 0xfd, 0xdb, 0x8a, 0xc6,
- 0x58, 0xbd, 0x2a, 0x3d, 0xc6, 0x65, 0x74, 0xcd, 0x31, 0x75, 0x9a, 0xf7, 0x4e, 0x7c, 0x37, 0xc3,
- 0x7a, 0xeb, 0xbc, 0x11, 0x4f, 0x9b, 0x7b, 0xcd, 0x18, 0xff, 0xbe, 0x41, 0x6a, 0xa7, 0x59, 0xe0,
- 0xd2, 0x67, 0x6f, 0xb1, 0x74, 0x6c, 0x4a, 0x26, 0xf4, 0xf9, 0x13, 0x3b, 0x97, 0x6c, 0x1d, 0xf1,
- 0x5c, 0x96, 0xc8, 0x0e, 0x0f, 0x6b, 0x5c, 0x1a, 0x97, 0x75, 0x60, 0x16, 0xc9, 0xe6, 0x2d, 0xe6,
- 0x68, 0x0d, 0xc5, 0xbc, 0x53, 0xdd, 0x53, 0xfd, 0x72, 0xed, 0x9f, 0xf7, 0xff, 0x79, 0xff, 0xcb,
- 0xb5, 0x3d, 0xb5, 0x9f, 0xed, 0x37, 0xec, 0x7f, 0xbb, 0x6a, 0xa4, 0xea, 0x12, 0x62, 0xb1, 0x3e,
- 0x7e, 0x4d, 0x95, 0x42, 0x5e, 0xc1, 0x6d, 0x24, 0x8d, 0x1f, 0x69, 0x5e, 0x6f, 0xa9, 0x3b, 0x0f,
- 0x15, 0x0c, 0xae, 0xa0, 0x31, 0xe7, 0xb7, 0xf9, 0xf6, 0x78, 0x0f, 0x0f, 0xd3, 0x09, 0xef, 0xec,
- 0x65, 0xcf, 0xc7, 0x48, 0xe6, 0xb4, 0xd5, 0xbb, 0x79, 0x56, 0x37, 0xba, 0xcb, 0xa4, 0x45, 0xc9,
- 0xdc, 0x0a, 0xf8, 0x8e, 0x16, 0x02, 0x97, 0x27, 0x87, 0x7b, 0x66, 0xc6, 0x66, 0x34, 0x6e, 0xeb,
- 0x80, 0xff, 0x15, 0x4a, 0x33, 0x87, 0xd8, 0x7c, 0xa0, 0x30, 0x49, 0x1d, 0x8a, 0x8f, 0x98, 0x3d,
- 0x8c, 0xbf, 0x1a, 0x46, 0x1d, 0xf3, 0x0b, 0x45, 0x63, 0x62, 0x14, 0x05, 0xc9, 0x6a, 0x23, 0xb2,
- 0x58, 0x8f, 0xd6, 0x8c, 0x33, 0xef, 0x1d, 0x61, 0xcf, 0x9d, 0xf6, 0x41, 0x1d, 0x8a, 0xf2, 0x10,
- 0x1e, 0x2b, 0x01, 0x9b, 0x4f, 0xe3, 0x4a, 0xcc, 0x13, 0x01, 0x2f, 0x8f, 0xa0, 0x67, 0xa7, 0xad,
- 0x2f, 0x6c, 0xa6, 0x7e, 0x89, 0x92, 0x99, 0x0f, 0xf8, 0x3d, 0x09, 0x6f, 0xc7, 0x22, 0x2e, 0x47,
- 0x67, 0x67, 0x22, 0x5f, 0xcc, 0xce, 0x80, 0x6c, 0x7e, 0xf5, 0xca, 0xbd, 0x5a, 0xcc, 0x66, 0xea,
- 0x08, 0x58, 0x2c, 0x8f, 0x0f, 0x14, 0x6f, 0xd4, 0xdc, 0x62, 0x58, 0xcd, 0x77, 0xa7, 0xbe, 0x9b,
- 0xc1, 0x95, 0x2b, 0x4c, 0xe1, 0xde, 0xe8, 0x30, 0x85, 0x37, 0x02, 0x94, 0xb7, 0xd5, 0x92, 0xf8,
- 0xee, 0x4e, 0x52, 0x60, 0xf3, 0xbc, 0xf5, 0x60, 0x8c, 0xad, 0x0b, 0x3b, 0x93, 0x90, 0xd8, 0xbb,
- 0x6d, 0x4b, 0xe0, 0x4f, 0x21, 0xf0, 0xdd, 0x49, 0x4a, 0x64, 0x23, 0xa3, 0x11, 0x0f, 0x54, 0x82,
- 0x99, 0x9d, 0x29, 0x73, 0x59, 0x87, 0xbf, 0x7a, 0xf5, 0x5e, 0xed, 0x38, 0xc7, 0x66, 0x72, 0xb6,
- 0x08, 0xd6, 0xaa, 0x98, 0xc7, 0x33, 0x35, 0xf7, 0x99, 0x76, 0x24, 0x91, 0xed, 0x17, 0xc7, 0x7d,
- 0x1b, 0x01, 0xcc, 0x23, 0x5f, 0xbf, 0x62, 0x9e, 0xab, 0x40, 0x31, 0xe7, 0xbf, 0x34, 0x9a, 0xdc,
- 0x37, 0xe3, 0x2c, 0xf9, 0x8c, 0xae, 0xdb, 0x32, 0x6d, 0x3d, 0x6f, 0x7d, 0x33, 0xae, 0xfe, 0x4f,
- 0x3f, 0xc9, 0x77, 0xfb, 0xa2, 0x1f, 0xd3, 0x37, 0xf1, 0x63, 0x07, 0xce, 0x11, 0x51, 0xea, 0x98,
- 0xcd, 0x93, 0x5e, 0x25, 0xb2, 0x4b, 0xa3, 0x94, 0x77, 0xdc, 0x0f, 0x95, 0x79, 0xc6, 0x10, 0x9b,
- 0x6f, 0x0f, 0x7f, 0xfe, 0x2a, 0x96, 0xcd, 0xdb, 0x8a, 0xc6, 0x4a, 0xc1, 0xfe, 0x01, 0x0e, 0x8f,
- 0x21, 0x16, 0x2b, 0x2a, 0xef, 0x20, 0x1e, 0x9f, 0xaf, 0xb1, 0x31, 0x54, 0xc3, 0x7f, 0x9c, 0x7a,
- 0x6e, 0xfe, 0x8a, 0xbf, 0x3c, 0xca, 0xa3, 0x90, 0x4f, 0x89, 0x73, 0x9d, 0x4d, 0xe1, 0x7b, 0x5f,
- 0x4c, 0x19, 0x92, 0xe7, 0x70, 0x80, 0x08, 0x52, 0xe7, 0xd4, 0x07, 0x55, 0xf1, 0x71, 0x2e, 0x3a,
- 0x2a, 0x99, 0xa2, 0x35, 0x9b, 0x2b, 0x70, 0x57, 0xb6, 0x25, 0xe3, 0x9a, 0x91, 0xef, 0x95, 0x88,
- 0xb8, 0x74, 0xd4, 0x79, 0x61, 0xad, 0x3b, 0xed, 0xc3, 0x6c, 0x8e, 0x8c, 0xfe, 0xe1, 0xe8, 0xbd,
- 0x5a, 0x1b, 0xb3, 0xc1, 0x9c, 0xa9, 0xb9, 0xaa, 0xb8, 0x83, 0xc6, 0x03, 0x34, 0xee, 0x28, 0x6e,
- 0x2b, 0x1c, 0x88, 0xc5, 0xfa, 0x1a, 0xc8, 0x82, 0xa6, 0x34, 0x7b, 0x8e, 0xfc, 0xd1, 0x7d, 0x9a,
- 0xab, 0x0a, 0xc4, 0xd5, 0x93, 0x79, 0x98, 0x0c, 0x38, 0xdb, 0x70, 0x69, 0x34, 0xf7, 0x1a, 0xfd,
- 0xd0, 0xf1, 0x74, 0x48, 0xec, 0xf6, 0x95, 0x23, 0x84, 0x5e, 0x89, 0x42, 0xde, 0x7a, 0x89, 0x6c,
- 0xdd, 0x61, 0xf3, 0x95, 0x87, 0x1a, 0xd1, 0x0a, 0x67, 0xdb, 0x64, 0x73, 0xdd, 0xbc, 0x5c, 0x4f,
- 0x69, 0x20, 0x73, 0xfd, 0x16, 0x1a, 0xf7, 0xb9, 0x9f, 0xb7, 0xd0, 0x23, 0x1b, 0x5a, 0x1f, 0xa9,
- 0x86, 0x3d, 0x2d, 0x3f, 0x3f, 0x6f, 0x43, 0x36, 0x2b, 0xe8, 0xd6, 0xde, 0xf0, 0x7c, 0x9a, 0x5a,
- 0x3f, 0x70, 0xe6, 0xef, 0xb4, 0x7f, 0xc9, 0x98, 0x7b, 0xed, 0xd2, 0x4e, 0x75, 0xa9, 0x59, 0xec,
- 0xf6, 0x95, 0x1b, 0xa0, 0xaa, 0x33, 0xf4, 0x4a, 0x64, 0xcc, 0x42, 0xe6, 0x56, 0x89, 0x6c, 0xb7,
- 0x0b, 0xd7, 0x6a, 0x32, 0x85, 0x57, 0x02, 0xed, 0xbe, 0x88, 0xa7, 0x87, 0xab, 0x51, 0xb8, 0xfb,
- 0xd4, 0x1f, 0x5e, 0xfd, 0xea, 0x95, 0xff, 0xad, 0x8f, 0xd4, 0x47, 0x6a, 0x23, 0xb5, 0xf7, 0xd0,
- 0x40, 0xff, 0xaa, 0xff, 0xf9, 0x91, 0x5f, 0x9d, 0x88, 0x0c, 0xdf, 0xf3, 0xe4, 0xc2, 0x24, 0xa0,
- 0x37, 0xdc, 0xe3, 0xce, 0x5e, 0x83, 0x82, 0x47, 0x3f, 0x09, 0x7e, 0x76, 0xc8, 0x19, 0x11, 0xf5,
- 0x6c, 0x66, 0xe0, 0x0e, 0xd1, 0x84, 0x0e, 0xb2, 0x32, 0x84, 0xab, 0x50, 0x77, 0xab, 0x3c, 0x04,
- 0x8c, 0x4c, 0x44, 0x1a, 0x42, 0x73, 0x7e, 0x8e, 0x4d, 0x24, 0x9b, 0x5f, 0x3a, 0x46, 0x86, 0x0d,
- 0x03, 0x3f, 0x39, 0xb5, 0xfb, 0xad, 0xdd, 0x6f, 0x95, 0xbd, 0xa5, 0x39, 0xd5, 0x76, 0xaa, 0xe7,
- 0x8c, 0x7f, 0xe0, 0x57, 0xae, 0x88, 0xe7, 0x75, 0xdf, 0x69, 0x3f, 0xbf, 0x4a, 0xce, 0xa7, 0xac,
- 0xf2, 0x14, 0xab, 0x67, 0x37, 0x02, 0xa9, 0xeb, 0x77, 0xa5, 0x46, 0x13, 0xd7, 0xef, 0x54, 0xec,
- 0xf9, 0x9e, 0x0d, 0xb8, 0x43, 0xf4, 0x92, 0x91, 0x31, 0xc7, 0xe6, 0x39, 0x37, 0xa9, 0x96, 0x3d,
- 0x7c, 0x6d, 0x90, 0x8f, 0x23, 0xe5, 0xa1, 0x71, 0x3f, 0xd4, 0x36, 0xec, 0x71, 0x6b, 0x5c, 0xeb,
- 0x8e, 0x9b, 0x8e, 0x4b, 0xa3, 0x97, 0xd0, 0xcf, 0x75, 0x47, 0x99, 0xab, 0xcd, 0x3d, 0x36, 0xb3,
- 0xec, 0xa1, 0xbc, 0xed, 0xbe, 0x71, 0x7f, 0xa6, 0x55, 0x32, 0x59, 0xcf, 0x52, 0xde, 0x5c, 0xce,
- 0x23, 0x60, 0x68, 0x89, 0x66, 0xbd, 0x68, 0x01, 0x65, 0x03, 0xee, 0x10, 0xdd, 0xac, 0xef, 0xb6,
- 0xc4, 0xeb, 0x3c, 0xa8, 0xd8, 0xc3, 0x6b, 0x49, 0xb0, 0x3d, 0x37, 0x02, 0x98, 0xcd, 0xb1, 0x99,
- 0x36, 0xc4, 0x67, 0x19, 0x1a, 0x1a, 0x17, 0xd4, 0x88, 0x45, 0x7b, 0x50, 0x4f, 0x9d, 0xd7, 0x16,
- 0xc3, 0x64, 0x20, 0x03, 0x83, 0xb1, 0x30, 0x85, 0x2f, 0x65, 0xa9, 0x0e, 0x13, 0x8b, 0x7e, 0x92,
- 0x31, 0xf3, 0xfd, 0x4e, 0xe9, 0x22, 0x7f, 0x07, 0x4f, 0x07, 0x78, 0xfd, 0x0a, 0x56, 0x0f, 0x1d,
- 0x73, 0xbd, 0x9f, 0x8c, 0xad, 0x96, 0xf5, 0x90, 0xdb, 0x17, 0x62, 0x36, 0x23, 0x9e, 0x59, 0x0f,
- 0xae, 0xf2, 0x3b, 0x8b, 0xe4, 0x31, 0xc2, 0x49, 0x24, 0xae, 0x32, 0x8a, 0x99, 0x5c, 0x4d, 0xcb,
- 0x5d, 0x32, 0xe6, 0xfc, 0xb9, 0xaf, 0x99, 0x48, 0xeb, 0xab, 0xba, 0x2d, 0xcd, 0xa2, 0x9e, 0x4d,
- 0x03, 0x6c, 0xbf, 0x42, 0xff, 0x83, 0xc4, 0x5e, 0xb4, 0x4a, 0x9d, 0x29, 0x1c, 0xff, 0xbd, 0xc3,
- 0xaa, 0x09, 0x75, 0x60, 0xdb, 0x91, 0x4d, 0x1b, 0xf1, 0x44, 0x38, 0x16, 0xa1, 0xe2, 0x2f, 0x96,
- 0xc8, 0x8d, 0xbb, 0xd9, 0xed, 0x9d, 0x64, 0xcc, 0x47, 0xde, 0xde, 0x82, 0x64, 0xc2, 0x59, 0x6d,
- 0x88, 0x9b, 0x88, 0xf6, 0x6c, 0x32, 0xe8, 0x68, 0x95, 0x82, 0x29, 0x43, 0xa9, 0x39, 0x7e, 0xb7,
- 0x77, 0x50, 0x15, 0x5b, 0x27, 0x0b, 0x63, 0x15, 0xd9, 0x9e, 0xe5, 0x1c, 0x9b, 0x36, 0x5f, 0x9d,
- 0xaf, 0xce, 0x0b, 0x15, 0x82, 0x81, 0x47, 0x5e, 0x22, 0xb7, 0xce, 0x24, 0x80, 0xf2, 0x6e, 0x45,
- 0x32, 0x21, 0xd3, 0x12, 0xec, 0x59, 0xd1, 0xa3, 0x97, 0x08, 0x58, 0x29, 0x21, 0xfa, 0x0c, 0x95,
- 0x60, 0xe8, 0x98, 0xeb, 0x4e, 0xf2, 0x83, 0xd1, 0x54, 0x76, 0xe8, 0x7c, 0x04, 0xb3, 0x39, 0xe7,
- 0x1f, 0xf7, 0x9f, 0x46, 0x03, 0xf3, 0xb8, 0xc1, 0xdb, 0x3b, 0x59, 0x2c, 0xd7, 0xd4, 0x30, 0x85,
- 0x2f, 0xe4, 0x50, 0xb7, 0x52, 0x40, 0xa7, 0x8a, 0x89, 0x7a, 0xf4, 0x44, 0x3d, 0x2b, 0x80, 0x5f,
- 0x29, 0x21, 0xdb, 0x2d, 0xfe, 0x7b, 0x59, 0x33, 0xae, 0xa4, 0x31, 0x5f, 0x60, 0xd5, 0x2c, 0x0f,
- 0xe1, 0xaa, 0xdb, 0x30, 0x80, 0xc7, 0xc6, 0x2d, 0xaf, 0x92, 0xb1, 0x58, 0x7d, 0x58, 0xe6, 0xda,
- 0x4a, 0x1f, 0x5c, 0x2d, 0xa1, 0xd4, 0x95, 0x8a, 0x7a, 0x36, 0x0e, 0xfc, 0x4a, 0x09, 0x5e, 0xbb,
- 0x78, 0xff, 0x67, 0x88, 0x5d, 0xf6, 0xa4, 0x97, 0x31, 0xf0, 0x1c, 0x34, 0x44, 0xe3, 0x57, 0x0d,
- 0xa1, 0xc6, 0x70, 0xbe, 0xba, 0x55, 0xc0, 0x9c, 0x7f, 0x6b, 0xfd, 0xe0, 0x9c, 0x24, 0xcc, 0x19,
- 0x32, 0x47, 0x44, 0x3d, 0x0b, 0xa0, 0xa3, 0x7b, 0x4a, 0xf0, 0xf4, 0xc4, 0x4b, 0x85, 0x5c, 0xf6,
- 0xa5, 0x23, 0xd1, 0xea, 0x89, 0x97, 0x23, 0xd0, 0xb4, 0xbd, 0x61, 0x1c, 0xc5, 0x02, 0xcd, 0x9a,
- 0xeb, 0x0e, 0x24, 0x1d, 0x26, 0x22, 0xb9, 0x54, 0x07, 0x8e, 0x9f, 0x63, 0x29, 0x17, 0xd3, 0x14,
- 0xfd, 0xb3, 0x00, 0xb0, 0x79, 0x06, 0xd5, 0x5d, 0x88, 0xc9, 0x78, 0xcb, 0x43, 0x4b, 0xec, 0x34,
- 0xcf, 0xf9, 0x57, 0x33, 0x7e, 0xf7, 0xc0, 0x26, 0xae, 0x88, 0x5f, 0x38, 0x8f, 0xf8, 0x7e, 0x6d,
- 0xee, 0xad, 0x76, 0x8e, 0x87, 0x53, 0x60, 0x4a, 0x9d, 0xb8, 0x3b, 0xc1, 0x51, 0x67, 0xa8, 0xb7,
- 0x2c, 0xc4, 0x2a, 0x79, 0x74, 0xaa, 0xc6, 0x66, 0x52, 0xd7, 0x58, 0x4f, 0xfc, 0xfe, 0x61, 0x14,
- 0x0b, 0x2b, 0x81, 0xad, 0x76, 0xdd, 0x84, 0x6a, 0xf0, 0xd8, 0x0b, 0xb4, 0xbd, 0x57, 0x4d, 0x3e,
- 0x26, 0x02, 0x36, 0x4f, 0x62, 0xa4, 0x70, 0xda, 0x9a, 0xce, 0xea, 0x79, 0x94, 0x98, 0x88, 0x74,
- 0x5b, 0xe8, 0x2d, 0x7e, 0x0a, 0x27, 0x59, 0x6a, 0x9e, 0x32, 0x42, 0x27, 0xc6, 0xed, 0xbb, 0x6a,
- 0xd2, 0x9b, 0xde, 0xd7, 0xf8, 0xca, 0x04, 0x80, 0x12, 0xd9, 0x6c, 0x4e, 0x52, 0x59, 0x6c, 0xac,
- 0x3e, 0x1c, 0x9b, 0xd9, 0xaa, 0x96, 0x05, 0x7f, 0x31, 0x54, 0x01, 0xda, 0xbe, 0xab, 0x26, 0x1d,
- 0xf5, 0xbe, 0x82, 0x86, 0x4a, 0xee, 0x5e, 0x38, 0x6d, 0x1d, 0xcf, 0xb2, 0x56, 0x3e, 0x2a, 0xa4,
- 0xae, 0x87, 0x98, 0x19, 0x5a, 0x02, 0x7b, 0x1e, 0xb7, 0xeb, 0xee, 0x44, 0x4b, 0xf4, 0x73, 0x2b,
- 0x25, 0xe4, 0x29, 0x26, 0x3e, 0xb7, 0x40, 0xad, 0x3b, 0xe2, 0xfb, 0x4f, 0x3c, 0x3e, 0x40, 0x8d,
- 0x7e, 0x7a, 0xcb, 0x9f, 0x06, 0xa2, 0x9a, 0xd0, 0x49, 0x77, 0x3b, 0xc6, 0x4e, 0xf0, 0x4a, 0x09,
- 0x1d, 0x4b, 0x87, 0x0c, 0x74, 0xd2, 0xb3, 0x4b, 0xc6, 0xd9, 0x99, 0xde, 0x0c, 0xbb, 0x91, 0x47,
- 0x8b, 0x76, 0xdf, 0x56, 0x3c, 0x06, 0x3c, 0xa0, 0x57, 0x26, 0x8e, 0x9d, 0x6c, 0x37, 0x36, 0xf1,
- 0x4e, 0x04, 0xf6, 0x94, 0xce, 0xa4, 0xef, 0x0d, 0x3a, 0x56, 0x50, 0xde, 0x27, 0xc7, 0x65, 0x6f,
- 0x38, 0x5d, 0xa7, 0xea, 0xcc, 0x80, 0x5c, 0xe8, 0xed, 0x17, 0x3b, 0xc1, 0x3b, 0x91, 0x66, 0x7d,
- 0xab, 0x25, 0x55, 0x04, 0x78, 0x91, 0x1d, 0x19, 0xad, 0xf3, 0x66, 0xf2, 0x12, 0x14, 0x0f, 0xab,
- 0x31, 0x43, 0xb8, 0xb6, 0xee, 0xc8, 0xe7, 0x53, 0x69, 0x89, 0x2e, 0xfd, 0x76, 0xdb, 0x9d, 0xf0,
- 0xfa, 0x35, 0xd9, 0xfb, 0x8a, 0x31, 0x65, 0xb8, 0xe9, 0xa0, 0xbc, 0xe5, 0xa1, 0xd5, 0xb4, 0x0c,
- 0x14, 0x83, 0x43, 0xdc, 0x79, 0xaf, 0x8f, 0xf3, 0x1b, 0xe1, 0xd1, 0x1b, 0xe6, 0xdf, 0x71, 0x25,
- 0x90, 0x5f, 0xcd, 0x10, 0x1c, 0xa3, 0xde, 0x4e, 0x3e, 0x3d, 0x5e, 0xbf, 0xae, 0x25, 0xed, 0x44,
- 0x00, 0x0b, 0x54, 0x8b, 0xe5, 0xa6, 0xe3, 0xb2, 0x27, 0xb1, 0x6f, 0x57, 0xb1, 0x38, 0x04, 0x2f,
- 0x91, 0x29, 0xdc, 0xc8, 0x79, 0x72, 0x37, 0xa2, 0x1d, 0x31, 0xe7, 0xfc, 0x73, 0x5c, 0x9c, 0xa5,
- 0x21, 0x84, 0xab, 0x58, 0xce, 0x47, 0x6e, 0xd8, 0x93, 0x67, 0x96, 0x0b, 0xe4, 0xb2, 0x6e, 0xcb,
- 0xf6, 0x89, 0x9d, 0xe0, 0x98, 0x48, 0xb3, 0x5e, 0xc8, 0x64, 0x8e, 0xc7, 0xa4, 0x3a, 0x6c, 0xbf,
- 0xe9, 0xe8, 0x71, 0x43, 0x3e, 0x6c, 0x5f, 0xda, 0x1d, 0x26, 0x44, 0x30, 0x21, 0xc7, 0x6e, 0x3e,
- 0xda, 0xdb, 0xb2, 0x37, 0x0c, 0x7d, 0x31, 0x33, 0xed, 0x48, 0x7f, 0x1f, 0xed, 0x7d, 0xd9, 0xc0,
- 0xc5, 0x56, 0x20, 0x56, 0x66, 0xf3, 0xb5, 0xfb, 0xe0, 0xbc, 0x17, 0xf4, 0xaa, 0x85, 0x51, 0xe7,
- 0x85, 0x8e, 0x99, 0xab, 0xdc, 0xab, 0x23, 0x9e, 0x7c, 0xec, 0x1f, 0xf8, 0x74, 0xcd, 0xdb, 0x28,
- 0x46, 0x8d, 0xcf, 0x17, 0x80, 0xfd, 0x9a, 0xea, 0xdb, 0x3a, 0x40, 0x1c, 0xd2, 0xbf, 0x34, 0x70,
- 0xc9, 0xd1, 0xe6, 0x8e, 0x78, 0x6c, 0xbe, 0x8d, 0x80, 0xa0, 0xf7, 0x12, 0x01, 0xdd, 0x2f, 0xaf,
- 0x70, 0x71, 0xcb, 0x71, 0xee, 0x67, 0xa6, 0xd7, 0x82, 0x34, 0xf6, 0x72, 0x92, 0x08, 0x2c, 0xda,
- 0x7c, 0x75, 0xde, 0x3d, 0xde, 0x65, 0x8f, 0xdf, 0x33, 0x3b, 0x33, 0x16, 0x37, 0x96, 0xd1, 0x7b,
- 0x9a, 0xb8, 0xbb, 0x34, 0x84, 0x4a, 0xcd, 0xf9, 0x7d, 0x3e, 0x1c, 0xa3, 0x06, 0x2f, 0xd0, 0xd3,
- 0x2e, 0x99, 0x58, 0x2a, 0xc1, 0x46, 0x48, 0x1d, 0xc3, 0x77, 0x92, 0x3b, 0xcd, 0xbf, 0x1c, 0xfe,
- 0xcc, 0xa1, 0x71, 0x5d, 0x9e, 0x01, 0x39, 0x01, 0x86, 0xd2, 0x45, 0xbd, 0x20, 0x8b, 0xeb, 0x4a,
- 0x00, 0x98, 0x5c, 0x09, 0x98, 0xd2, 0xf2, 0x18, 0xcb, 0xe5, 0x46, 0x94, 0xc9, 0x65, 0xc4, 0xe2,
- 0x45, 0x34, 0x7a, 0x12, 0xc6, 0x45, 0x60, 0xd3, 0x6f, 0x0a, 0xe3, 0x58, 0x66, 0xb2, 0x85, 0x9d,
- 0xdb, 0x27, 0x84, 0xbe, 0xc4, 0xdb, 0xe1, 0xd4, 0x09, 0xdf, 0xaf, 0xa2, 0x2b, 0xa5, 0xd5, 0x03,
- 0xeb, 0xcd, 0xb4, 0xf5, 0xe4, 0xf0, 0x4d, 0x07, 0xf4, 0x86, 0xa6, 0xbc, 0x36, 0xee, 0xfc, 0x00,
- 0x62, 0x33, 0x2d, 0x47, 0x90, 0x2d, 0xbb, 0x91, 0xa6, 0xcf, 0x69, 0x32, 0x9f, 0xa6, 0x18, 0x3e,
- 0x23, 0x9e, 0x65, 0x4e, 0x2e, 0xe3, 0x39, 0x05, 0x36, 0xc7, 0xfd, 0x70, 0xbf, 0x8d, 0xc0, 0xd0,
- 0xe6, 0x39, 0x13, 0x5a, 0x72, 0x96, 0x3c, 0x9b, 0x33, 0x33, 0x1d, 0xd1, 0x9c, 0xcb, 0xa7, 0xdb,
- 0x3f, 0x2b, 0xac, 0x95, 0xa9, 0x7f, 0xe7, 0xe1, 0xec, 0x0d, 0xd2, 0xb0, 0xa3, 0x1a, 0x17, 0x74,
- 0x1e, 0xb5, 0xf9, 0x70, 0xb6, 0x72, 0xa6, 0x4c, 0x01, 0xb0, 0x45, 0x33, 0x49, 0x64, 0x7a, 0x46,
- 0xa3, 0xd9, 0x42, 0x5e, 0xc8, 0xfe, 0x02, 0x4e, 0x63, 0xd9, 0x5c, 0x09, 0x80, 0x9d, 0xfb, 0xa5,
- 0x83, 0xb7, 0xcd, 0x68, 0xc9, 0x41, 0xd5, 0x21, 0xfd, 0x33, 0xba, 0x7d, 0x32, 0x3a, 0xa7, 0xcf,
- 0x09, 0x95, 0x2a, 0xa6, 0x9e, 0xf2, 0x93, 0x9a, 0x50, 0xb3, 0x10, 0xd6, 0x4a, 0x65, 0x8a, 0x4e,
- 0x13, 0x00, 0xe8, 0x85, 0x07, 0x76, 0x0f, 0xac, 0x95, 0x2b, 0x39, 0x9c, 0x1e, 0xc8, 0x17, 0x38,
- 0x8a, 0xcd, 0x75, 0x10, 0x0f, 0xf0, 0xf9, 0x7c, 0x90, 0x6d, 0x7b, 0x31, 0xca, 0x66, 0xc4, 0x03,
- 0x36, 0x50, 0x79, 0xa8, 0x2b, 0x26, 0xfe, 0xd5, 0xa9, 0x7a, 0xff, 0xff, 0xb9, 0xbb, 0xfe, 0x98,
- 0x36, 0xae, 0x3c, 0x8f, 0x1a, 0xa4, 0xce, 0x69, 0xf9, 0x63, 0xb6, 0xa1, 0xed, 0x54, 0x25, 0x96,
- 0xe7, 0x70, 0x13, 0x5c, 0xd1, 0x0a, 0xdf, 0xd1, 0x1c, 0xee, 0x11, 0x14, 0xbb, 0x21, 0x0a, 0x56,
- 0xa9, 0x0e, 0xb7, 0x44, 0xc1, 0x0d, 0x24, 0x8e, 0x61, 0x53, 0xe4, 0xa2, 0x0a, 0x59, 0x5c, 0xc4,
- 0x51, 0x60, 0x43, 0x0d, 0x55, 0x23, 0x97, 0xbd, 0x72, 0x0e, 0x51, 0x59, 0xc7, 0x28, 0x9c, 0x4c,
- 0x14, 0x24, 0x13, 0x5d, 0x2a, 0xc3, 0x2d, 0x2b, 0x1b, 0x6d, 0xd8, 0x1a, 0x5d, 0x90, 0xcc, 0x5d,
- 0x73, 0x67, 0x6b, 0x4b, 0xce, 0x96, 0x82, 0x2e, 0x96, 0xca, 0x49, 0xde, 0x3b, 0xaa, 0xf3, 0x4a,
- 0x59, 0xc5, 0x37, 0xdf, 0x79, 0x33, 0x9e, 0x19, 0xff, 0x9a, 0x31, 0x06, 0xee, 0xcc, 0x7b, 0xaa,
- 0x54, 0x83, 0x89, 0x3d, 0xef, 0xf3, 0xbe, 0xef, 0xfb, 0xe3, 0x7d, 0xbf, 0x9f, 0xaf, 0xfe, 0x81,
- 0xe1, 0x98, 0xf6, 0xb1, 0x24, 0x26, 0x35, 0x88, 0xcf, 0x02, 0xbb, 0xc1, 0x41, 0xb5, 0x80, 0xb8,
- 0x08, 0x41, 0x36, 0xef, 0xed, 0x10, 0x39, 0x61, 0x47, 0xfd, 0xda, 0x0b, 0xc9, 0xdb, 0x91, 0x8e,
- 0xe8, 0x72, 0x9c, 0x93, 0xd2, 0xfe, 0x20, 0xc2, 0x13, 0xa1, 0x59, 0xe7, 0x07, 0x4b, 0x6a, 0xdb,
- 0xc1, 0x3f, 0x3f, 0x66, 0xf0, 0x63, 0xda, 0x07, 0x86, 0x3b, 0xfa, 0x51, 0x95, 0xb8, 0xb4, 0x19,
- 0xb1, 0x32, 0xd3, 0xda, 0x01, 0xe6, 0x1d, 0x31, 0x32, 0x52, 0x89, 0x65, 0x91, 0xca, 0x92, 0x92,
- 0x2f, 0xf4, 0x7d, 0xee, 0xb6, 0x40, 0x45, 0x74, 0xef, 0x71, 0xe4, 0x23, 0x4a, 0x9d, 0xd3, 0x31,
- 0xc8, 0x03, 0x03, 0x3d, 0x1a, 0x67, 0xa4, 0x73, 0xc1, 0x03, 0x5a, 0xb3, 0x22, 0x2a, 0xbc, 0x99,
- 0x3e, 0x89, 0xcd, 0xaa, 0xee, 0x50, 0xd2, 0xe9, 0x57, 0x5f, 0x15, 0xb5, 0x8b, 0xba, 0x94, 0xcd,
- 0x66, 0xe8, 0x4e, 0x7c, 0x10, 0x25, 0x13, 0x71, 0x10, 0x80, 0x55, 0xc0, 0x45, 0x08, 0xe4, 0xd4,
- 0xea, 0xc8, 0x79, 0xef, 0x80, 0xd8, 0x1d, 0xd4, 0x00, 0xed, 0x1b, 0x90, 0x3c, 0x44, 0x9d, 0xf1,
- 0x13, 0x51, 0xc8, 0x86, 0x27, 0xfc, 0x0b, 0xb4, 0x6c, 0x86, 0xbc, 0x4f, 0xc3, 0xbe, 0x78, 0xab,
- 0x5b, 0x93, 0x72, 0x47, 0xde, 0x49, 0x9f, 0xb5, 0x7e, 0xb5, 0x58, 0x64, 0x48, 0x5e, 0x42, 0xe7,
- 0x75, 0xd1, 0x8c, 0x88, 0xf2, 0xdc, 0x6f, 0x2d, 0xba, 0xc1, 0x5a, 0xb0, 0x55, 0x5a, 0x6e, 0x75,
- 0x6e, 0xe1, 0x8f, 0x09, 0xae, 0xf2, 0x71, 0x56, 0xb5, 0xe0, 0x81, 0xf5, 0xdb, 0x7f, 0x24, 0x19,
- 0x3c, 0xe9, 0x9c, 0xdb, 0x25, 0xba, 0xf6, 0x1a, 0x98, 0x2e, 0x20, 0x26, 0xdc, 0x1e, 0xeb, 0x4e,
- 0xc9, 0x19, 0x91, 0x97, 0x54, 0x92, 0x67, 0x74, 0x1f, 0xe9, 0xd2, 0x59, 0xf3, 0x52, 0x47, 0x29,
- 0xd9, 0x4c, 0xd7, 0x29, 0x1c, 0x34, 0xc9, 0xe4, 0x2c, 0x58, 0x2e, 0x2b, 0xfd, 0x16, 0xde, 0xa9,
- 0x7c, 0x87, 0xe4, 0x56, 0x04, 0xb7, 0x2e, 0x05, 0xff, 0x2f, 0x72, 0x09, 0x78, 0x68, 0xd2, 0x59,
- 0xb7, 0x1b, 0xe1, 0x3a, 0x1a, 0xcd, 0x05, 0xcf, 0x52, 0xd0, 0x17, 0x9f, 0xf4, 0xa4, 0x3f, 0xcd,
- 0x26, 0xf1, 0x44, 0x03, 0xfd, 0x8c, 0xe5, 0x39, 0x9f, 0x19, 0xc5, 0xda, 0x0f, 0x5e, 0x57, 0x5b,
- 0xc4, 0x08, 0xbb, 0x46, 0xf9, 0x95, 0xec, 0xd9, 0x64, 0xc4, 0x3a, 0x95, 0x7e, 0x75, 0x65, 0x12,
- 0xd9, 0x55, 0x75, 0xc8, 0x5b, 0x28, 0x92, 0x28, 0x9b, 0x1d, 0xe6, 0x79, 0xc8, 0x95, 0xdd, 0x51,
- 0x56, 0x17, 0x8a, 0x0e, 0xb6, 0x05, 0xc0, 0x4f, 0x21, 0xfc, 0xc0, 0x57, 0x91, 0x2a, 0x99, 0x30,
- 0xee, 0xd3, 0x6c, 0x06, 0xb7, 0x44, 0xb4, 0x26, 0x74, 0x9b, 0x3e, 0x68, 0x51, 0x03, 0x74, 0x33,
- 0x02, 0xd9, 0x76, 0x5c, 0x0f, 0xd9, 0x43, 0xa4, 0x5f, 0xed, 0x52, 0xb3, 0xab, 0x61, 0xc4, 0x5a,
- 0x6c, 0x15, 0x05, 0x66, 0x12, 0xd4, 0x47, 0xcb, 0x5d, 0x20, 0x07, 0x63, 0xaa, 0x55, 0xf5, 0x35,
- 0xfd, 0xbc, 0xe5, 0xb0, 0xab, 0xce, 0x2f, 0x2d, 0x8e, 0x90, 0x8a, 0xa6, 0x33, 0x0e, 0xb5, 0xf4,
- 0x7f, 0xf0, 0x12, 0x7e, 0x38, 0x29, 0x6a, 0x5d, 0x99, 0x74, 0xe3, 0x2d, 0xfc, 0x39, 0xf2, 0x96,
- 0x08, 0x46, 0xa8, 0x52, 0xf3, 0x60, 0x49, 0x26, 0xe2, 0x9d, 0x84, 0xda, 0x70, 0xd6, 0xee, 0xb9,
- 0x8a, 0x8f, 0xaa, 0x9e, 0xa8, 0x4f, 0x29, 0xe5, 0xcc, 0x3b, 0x9a, 0x74, 0x84, 0x3f, 0x52, 0x10,
- 0x92, 0x83, 0xb1, 0x1a, 0x2b, 0xb0, 0x68, 0xf3, 0xa7, 0x82, 0x9c, 0xd3, 0xb7, 0xd8, 0xe2, 0xde,
- 0xdc, 0x11, 0xbe, 0x4c, 0xc3, 0x49, 0x57, 0xec, 0x42, 0x4d, 0xee, 0x89, 0xa8, 0x30, 0xcf, 0xf2,
- 0x24, 0x76, 0x15, 0x43, 0xf1, 0x9c, 0x8b, 0xd8, 0x45, 0x51, 0xab, 0x46, 0xc1, 0xd4, 0x50, 0x1f,
- 0x1c, 0x9d, 0xc9, 0xc6, 0xd3, 0xab, 0x74, 0x72, 0xfa, 0x35, 0x92, 0x4a, 0xbf, 0x9a, 0xf5, 0xde,
- 0x56, 0x88, 0x5e, 0x7b, 0xa1, 0x77, 0xcf, 0xfd, 0x01, 0x60, 0x0e, 0x4e, 0x9f, 0x46, 0x6c, 0x54,
- 0x55, 0x66, 0xaa, 0x75, 0x0d, 0xc6, 0x12, 0x79, 0x9d, 0xb9, 0xa8, 0x2e, 0x70, 0x29, 0x08, 0x31,
- 0xc4, 0xde, 0x24, 0xd3, 0xda, 0x49, 0xec, 0x31, 0x51, 0x49, 0x56, 0x92, 0xcf, 0xbd, 0x02, 0x7a,
- 0x5e, 0x4e, 0xe1, 0x99, 0x5b, 0x36, 0x59, 0x9d, 0x79, 0x50, 0xfc, 0x4c, 0xee, 0x84, 0x65, 0xe3,
- 0xe9, 0x57, 0x71, 0x17, 0x2d, 0x95, 0xac, 0xdd, 0xd3, 0xa4, 0x2b, 0x34, 0xeb, 0x2e, 0x92, 0xa8,
- 0xf3, 0x43, 0x85, 0x58, 0xe6, 0xa9, 0xa1, 0x3e, 0xff, 0x1a, 0xe5, 0xbb, 0x3a, 0xe3, 0xf9, 0xa0,
- 0x89, 0xaa, 0x8f, 0x00, 0x4b, 0x75, 0x80, 0xed, 0x5d, 0xfd, 0x73, 0xfc, 0x1d, 0x72, 0x54, 0x35,
- 0xaa, 0xb2, 0x2a, 0x2b, 0x49, 0x90, 0xca, 0xfb, 0x14, 0xb2, 0xf7, 0x73, 0xf6, 0x05, 0x43, 0xec,
- 0x06, 0x07, 0xc5, 0xcf, 0x84, 0x78, 0x0f, 0x30, 0xfb, 0x6e, 0x19, 0xd0, 0xde, 0x04, 0xa9, 0x7c,
- 0xc2, 0x93, 0xca, 0x52, 0x52, 0x58, 0xf7, 0xbc, 0x33, 0x2c, 0xa7, 0x82, 0x55, 0x19, 0xe5, 0x92,
- 0xc3, 0x73, 0x85, 0x58, 0x33, 0xb4, 0x05, 0x7c, 0x79, 0xa0, 0x09, 0x76, 0x50, 0x7b, 0x6c, 0x88,
- 0xc2, 0xb4, 0x9a, 0xb9, 0x01, 0x03, 0xdb, 0x1b, 0xb0, 0x1c, 0x55, 0x75, 0x2a, 0x81, 0xfb, 0xf9,
- 0x31, 0xe1, 0xa2, 0xfe, 0x3f, 0x97, 0x77, 0x02, 0x7d, 0x87, 0x0e, 0x0e, 0xf3, 0x2c, 0x8a, 0xc2,
- 0x96, 0x25, 0x73, 0x27, 0x59, 0xa9, 0x94, 0xd3, 0xaf, 0x20, 0x87, 0xbf, 0x50, 0xab, 0x07, 0x06,
- 0xd4, 0xf5, 0x80, 0x57, 0x9e, 0x7b, 0xae, 0x10, 0xb8, 0x95, 0xe3, 0x3e, 0x90, 0x32, 0xd0, 0x5d,
- 0xf7, 0x43, 0x26, 0xce, 0xfe, 0x9b, 0x24, 0x96, 0x56, 0xd5, 0x73, 0x24, 0xdc, 0x9f, 0xf8, 0xd5,
- 0x67, 0x74, 0xa7, 0x72, 0xd6, 0xe0, 0x42, 0xa7, 0xbe, 0x83, 0xd1, 0xdd, 0x2d, 0xe9, 0x59, 0x9a,
- 0x91, 0x1c, 0xa6, 0x4a, 0xe5, 0x0a, 0xb1, 0xc0, 0xeb, 0x14, 0xbb, 0xf3, 0x01, 0x19, 0xe7, 0x8d,
- 0x4a, 0x31, 0x2c, 0xe5, 0xb4, 0x6d, 0x19, 0xf7, 0xe6, 0x1b, 0x25, 0xdc, 0x08, 0xa3, 0x9d, 0x98,
- 0x2a, 0x97, 0x25, 0x25, 0xa3, 0xaa, 0x3b, 0xfa, 0x63, 0xda, 0x5c, 0x51, 0x20, 0x79, 0x09, 0xca,
- 0xb6, 0x2c, 0xfe, 0x5b, 0x13, 0xc4, 0x88, 0x36, 0xa7, 0x67, 0x59, 0xe7, 0xae, 0x52, 0xab, 0xf1,
- 0x44, 0xdd, 0x99, 0xb4, 0x60, 0xd7, 0x0c, 0xbb, 0x93, 0xd5, 0x0c, 0xe7, 0x21, 0x44, 0xed, 0xa5,
- 0xa0, 0x39, 0xa6, 0x7a, 0x98, 0xb3, 0x1a, 0x30, 0x7d, 0x38, 0xe3, 0xe8, 0x36, 0xf3, 0x24, 0x56,
- 0x49, 0x22, 0x24, 0x0f, 0x31, 0x51, 0x8e, 0x19, 0xfc, 0x0e, 0xf5, 0x6c, 0xb9, 0x25, 0x73, 0x4c,
- 0x75, 0x30, 0x3a, 0x88, 0x1b, 0xe9, 0xde, 0x5c, 0xd5, 0x0c, 0xcb, 0x0b, 0x68, 0x18, 0xbf, 0xfa,
- 0x89, 0x7a, 0x33, 0x79, 0x33, 0xb8, 0xe0, 0x8d, 0xec, 0x06, 0x94, 0xf4, 0x68, 0x0b, 0x74, 0x49,
- 0x90, 0x4c, 0x64, 0x0b, 0xe1, 0x56, 0xd8, 0x43, 0x52, 0x3f, 0x3b, 0x92, 0x68, 0xb1, 0x21, 0x24,
- 0xae, 0xe2, 0x60, 0xc7, 0xde, 0xe7, 0xc5, 0x1e, 0xcf, 0xe8, 0x20, 0x63, 0x3d, 0x97, 0xce, 0x84,
- 0x0e, 0xe2, 0xc5, 0xef, 0x99, 0xc8, 0x19, 0x16, 0xfc, 0x6a, 0x13, 0x5a, 0x09, 0x23, 0x76, 0x8a,
- 0x92, 0xca, 0xd9, 0xa4, 0xb5, 0xb0, 0x65, 0xd8, 0xbd, 0x3c, 0xd8, 0x48, 0x22, 0x9c, 0x28, 0x77,
- 0x89, 0xeb, 0x4c, 0x34, 0x67, 0xf0, 0x66, 0x73, 0x3e, 0x68, 0xb6, 0x05, 0xb8, 0xfd, 0x27, 0x17,
- 0x3c, 0x63, 0xa7, 0x72, 0xcb, 0xf0, 0x91, 0x2e, 0xb7, 0x35, 0xdb, 0xa4, 0x2b, 0x7e, 0xfb, 0x87,
- 0x8b, 0xa8, 0xcb, 0x4b, 0x60, 0x15, 0x20, 0xf6, 0xf5, 0x44, 0xc3, 0x9e, 0x48, 0x1a, 0xac, 0xd6,
- 0x25, 0x75, 0x2d, 0xa5, 0x60, 0x09, 0xf1, 0xd4, 0x6a, 0x93, 0x54, 0x34, 0x8d, 0xd8, 0x9c, 0x1e,
- 0xa2, 0x08, 0xd2, 0xbe, 0xc1, 0x60, 0x2c, 0x1b, 0xcb, 0x88, 0xbc, 0xe4, 0x07, 0xc3, 0x1d, 0xfd,
- 0x21, 0x32, 0xd7, 0x3a, 0xac, 0xd0, 0xbd, 0xfa, 0x14, 0x45, 0x6c, 0xff, 0xb0, 0x9e, 0x25, 0xcb,
- 0x53, 0x78, 0x12, 0x3b, 0x44, 0x7e, 0x4b, 0x9d, 0xb0, 0xec, 0xed, 0xdf, 0x9c, 0x7e, 0x77, 0x6b,
- 0x2c, 0x01, 0x95, 0x8a, 0xe8, 0xaa, 0x5a, 0x2a, 0x9a, 0x60, 0x43, 0x43, 0x3e, 0x88, 0xb4, 0x7f,
- 0x3b, 0x5b, 0x65, 0x82, 0xbc, 0xe4, 0x8e, 0xfe, 0x07, 0xc3, 0xa8, 0x80, 0xff, 0x24, 0x75, 0x40,
- 0xe7, 0x21, 0x64, 0xff, 0xe4, 0x7a, 0xd7, 0xff, 0xe7, 0xc1, 0x7a, 0x96, 0x6c, 0xfe, 0xe4, 0x55,
- 0xfc, 0x1d, 0xe5, 0xb7, 0x6a, 0x17, 0x13, 0x93, 0xd5, 0x60, 0x2d, 0xb6, 0xdd, 0xbe, 0x17, 0x81,
- 0x73, 0xb6, 0xd5, 0x9d, 0x1a, 0xcb, 0xcb, 0x25, 0x9b, 0xd7, 0xf4, 0xfd, 0x01, 0x69, 0x68, 0xd6,
- 0x58, 0xb3, 0x3d, 0xe7, 0xf3, 0xda, 0x1f, 0x0c, 0xfe, 0x9c, 0x1a, 0x53, 0x5e, 0x02, 0xfd, 0xc9,
- 0x8a, 0xb9, 0xbf, 0x1b, 0xeb, 0x59, 0x22, 0xce, 0x1e, 0x39, 0x65, 0xd1, 0x9f, 0x52, 0xba, 0x54,
- 0x8f, 0x19, 0xcd, 0xf2, 0x33, 0xd5, 0xee, 0x78, 0x23, 0xa9, 0x68, 0x56, 0x44, 0xb7, 0x0c, 0x52,
- 0xb1, 0x94, 0xd3, 0x5c, 0xf9, 0x75, 0x7e, 0x29, 0x27, 0x6d, 0x5b, 0x40, 0x9e, 0xe5, 0x39, 0x4f,
- 0x29, 0x7f, 0x30, 0x3c, 0x11, 0xb9, 0x9d, 0xde, 0x24, 0xe8, 0xfe, 0x6e, 0x45, 0x7a, 0xca, 0xb2,
- 0x99, 0x04, 0x5b, 0x86, 0x4d, 0x39, 0x7a, 0x7d, 0x9f, 0x38, 0xa5, 0xec, 0x54, 0xb2, 0x3b, 0x73,
- 0x2d, 0x2b, 0x77, 0x4f, 0x61, 0x58, 0x82, 0x05, 0xb4, 0x29, 0x59, 0x32, 0x01, 0xcd, 0x2a, 0xad,
- 0x14, 0x34, 0xdb, 0x63, 0xf2, 0x2c, 0x4f, 0x3a, 0x83, 0x3f, 0x10, 0xc5, 0x12, 0xf6, 0x4c, 0xf1,
- 0xf6, 0x77, 0x03, 0xcf, 0x72, 0x36, 0xd9, 0x61, 0x0d, 0xb4, 0x25, 0x44, 0x2f, 0xb9, 0x3c, 0xb6,
- 0x2f, 0x2d, 0x7b, 0x53, 0xcb, 0x45, 0xc7, 0xf3, 0x74, 0xd2, 0xb1, 0x04, 0x1f, 0x65, 0x56, 0x05,
- 0x4c, 0x6d, 0xb9, 0xd1, 0xf4, 0xc5, 0xe5, 0x59, 0x9e, 0xf4, 0x2a, 0xfe, 0x85, 0x9e, 0xb2, 0x02,
- 0x44, 0x4e, 0x4f, 0xb6, 0x8b, 0x42, 0xf1, 0x9d, 0xb2, 0xac, 0xdd, 0xb3, 0x65, 0x60, 0xed, 0xbf,
- 0x93, 0xd8, 0x2d, 0x9c, 0xf3, 0xcb, 0x0a, 0x8b, 0xc2, 0x42, 0x06, 0x5d, 0xf6, 0xdf, 0x86, 0x13,
- 0xb1, 0x01, 0x29, 0x51, 0x03, 0x3e, 0x9a, 0xa5, 0x24, 0xe8, 0xcd, 0x5c, 0x68, 0x46, 0x12, 0xd9,
- 0x24, 0xcf, 0x88, 0x1d, 0xd3, 0x8a, 0x67, 0x00, 0x29, 0xc8, 0x2d, 0x43, 0x93, 0xae, 0x18, 0x63,
- 0x79, 0x2c, 0x03, 0xfe, 0x35, 0x3d, 0xbb, 0x0f, 0xe5, 0x82, 0x1b, 0xbf, 0xa8, 0x5a, 0xaa, 0xcd,
- 0x91, 0x69, 0x40, 0x26, 0x64, 0xae, 0x55, 0xef, 0x73, 0x2b, 0xc8, 0x7c, 0xb0, 0x84, 0x39, 0xa6,
- 0x8a, 0xe7, 0x60, 0xf9, 0x82, 0x91, 0x8d, 0x2f, 0x46, 0x83, 0x3d, 0x51, 0x8f, 0xaa, 0xc4, 0xb0,
- 0x84, 0x3a, 0x78, 0xc8, 0x80, 0x2e, 0xb6, 0x88, 0x01, 0xe8, 0x4a, 0xc4, 0xf6, 0xc2, 0xaf, 0xe6,
- 0x82, 0x15, 0x63, 0x47, 0x21, 0x11, 0x75, 0x60, 0xd5, 0xce, 0xa5, 0x6b, 0x23, 0x74, 0xfc, 0x34,
- 0x5f, 0x2c, 0x35, 0xd8, 0x6a, 0x4e, 0xce, 0xb6, 0x44, 0xa2, 0xc5, 0x96, 0xf9, 0x69, 0x35, 0x18,
- 0x44, 0xf5, 0xc4, 0x23, 0x74, 0x70, 0x4a, 0xcd, 0x16, 0x5d, 0x5c, 0x96, 0xad, 0xb1, 0x9c, 0x4b,
- 0x4a, 0xe5, 0x45, 0xec, 0x2a, 0xce, 0x59, 0xed, 0x46, 0x6c, 0xde, 0xb2, 0xf3, 0xfa, 0x4a, 0x67,
- 0x1c, 0x38, 0x46, 0x73, 0xbd, 0xc3, 0x97, 0x80, 0x1b, 0xb6, 0xfc, 0xd1, 0xa4, 0x19, 0xf8, 0xb2,
- 0x9e, 0xb4, 0x7d, 0xee, 0xcc, 0x4f, 0x0b, 0xb9, 0x79, 0x95, 0xa4, 0x78, 0x2f, 0x85, 0x31, 0xba,
- 0xd7, 0x6e, 0x71, 0x69, 0x4c, 0x74, 0x37, 0x52, 0xa5, 0x6d, 0x36, 0x73, 0x59, 0x77, 0xf7, 0x89,
- 0x77, 0x94, 0x8f, 0x79, 0xda, 0xb2, 0xd5, 0x9d, 0x6d, 0xc5, 0xc4, 0x47, 0x7b, 0x0c, 0xb8, 0xb8,
- 0x73, 0xbd, 0x23, 0x42, 0x79, 0x83, 0x70, 0x96, 0xed, 0x44, 0x36, 0xe3, 0xde, 0x6c, 0x7a, 0xb3,
- 0xce, 0x9f, 0xed, 0x79, 0xef, 0x13, 0xa9, 0x9d, 0x6c, 0x33, 0x8d, 0x4d, 0xa2, 0xd8, 0x34, 0x26,
- 0x9f, 0x83, 0x89, 0xfb, 0x69, 0x25, 0xe9, 0xe2, 0x9d, 0x43, 0x5d, 0xca, 0xdc, 0x72, 0x95, 0x7b,
- 0x54, 0x44, 0x43, 0x22, 0x58, 0x26, 0x12, 0x93, 0x1e, 0xe9, 0x11, 0x03, 0x21, 0x9a, 0xe8, 0xbb,
- 0x65, 0x42, 0xb3, 0x3f, 0x98, 0xed, 0x99, 0x2f, 0x62, 0x3f, 0x97, 0xa0, 0x05, 0xe1, 0xf6, 0xeb,
- 0x9a, 0xbe, 0x98, 0x62, 0xec, 0xa8, 0x6e, 0xa4, 0x5b, 0xd7, 0x63, 0xe6, 0x32, 0xd4, 0x4f, 0x62,
- 0x9d, 0xca, 0x2a, 0x9d, 0x2b, 0x19, 0x53, 0x8f, 0xaa, 0x77, 0x7e, 0xd3, 0x05, 0xda, 0x70, 0xc1,
- 0x93, 0xce, 0xf6, 0x2c, 0x7c, 0xcf, 0xd3, 0x70, 0xfe, 0xd6, 0x0f, 0x3b, 0x4b, 0xc9, 0xcc, 0xfe,
- 0xe6, 0x54, 0x56, 0x2c, 0x4f, 0x4a, 0x94, 0xb4, 0x62, 0xf3, 0x31, 0xd1, 0x2d, 0x57, 0x99, 0x80,
- 0x01, 0xff, 0x22, 0xe6, 0x52, 0xdd, 0xd1, 0xb3, 0xbd, 0x24, 0x35, 0xd8, 0xfa, 0xc0, 0xce, 0xfd,
- 0x11, 0xf0, 0x1f, 0x27, 0x45, 0xb1, 0xf4, 0xc5, 0xb3, 0xe7, 0xff, 0x88, 0xcb, 0x66, 0x66, 0x9b,
- 0x76, 0x29, 0x0b, 0x96, 0xe0, 0x39, 0x4b, 0xeb, 0x3c, 0x04, 0x8c, 0x46, 0xc5, 0x73, 0x5f, 0x82,
- 0x62, 0xb0, 0xdd, 0x3a, 0x21, 0xb3, 0xc4, 0x2d, 0xdc, 0xaf, 0x86, 0x2a, 0x0c, 0xf4, 0x6a, 0x04,
- 0xef, 0x2b, 0x40, 0x5b, 0xfa, 0x28, 0xcb, 0x67, 0xd2, 0x33, 0x15, 0xcc, 0x8d, 0x65, 0x22, 0x31,
- 0xa7, 0xdf, 0x29, 0x96, 0xd9, 0x6c, 0xda, 0x6c, 0x58, 0x3e, 0x26, 0x3a, 0x95, 0xe2, 0xd5, 0x42,
- 0x30, 0x20, 0x93, 0xab, 0x78, 0xe2, 0x05, 0x48, 0x2a, 0xb7, 0x0c, 0xab, 0x02, 0x0e, 0xd1, 0xfb,
- 0xc4, 0x13, 0x35, 0xc4, 0x2c, 0xd1, 0xcf, 0x66, 0xf0, 0x73, 0x05, 0x68, 0x4b, 0x67, 0x1c, 0x6a,
- 0x04, 0x96, 0x72, 0x62, 0x09, 0x63, 0xde, 0xb2, 0x73, 0x2c, 0xe5, 0x34, 0xc7, 0x5d, 0xdc, 0x1b,
- 0x16, 0x9c, 0xb4, 0x1b, 0xe1, 0xcc, 0xcf, 0x0c, 0xb9, 0xbe, 0xb9, 0xef, 0x2f, 0xd9, 0x31, 0x83,
- 0xb3, 0x5d, 0xa7, 0x0b, 0x5b, 0xe5, 0xfd, 0x18, 0xec, 0xdd, 0xf3, 0x9c, 0x5e, 0xc8, 0xf7, 0xf2,
- 0x98, 0x80, 0xbb, 0x04, 0x0e, 0x4b, 0x71, 0x24, 0x72, 0x61, 0x09, 0xd5, 0x3b, 0xe2, 0xb1, 0xdc,
- 0x09, 0x7b, 0x21, 0x58, 0x22, 0x0f, 0xa5, 0x4d, 0x10, 0x0b, 0xda, 0x08, 0x67, 0x96, 0xa7, 0x33,
- 0xba, 0x2a, 0x91, 0xbb, 0x68, 0x6e, 0x7d, 0xe0, 0x1e, 0xb3, 0x38, 0x2c, 0x59, 0x94, 0xd5, 0x0c,
- 0xbd, 0x1e, 0xf8, 0x3f, 0x95, 0x33, 0x58, 0xb2, 0x7c, 0xbf, 0x9b, 0x44, 0x21, 0x99, 0x77, 0x83,
- 0xb1, 0xf8, 0xb7, 0x93, 0x9e, 0xa7, 0xa2, 0x58, 0xf6, 0xb9, 0x0b, 0xc3, 0x12, 0xc5, 0x69, 0xe1,
- 0x7e, 0x93, 0x45, 0x73, 0x23, 0x7c, 0x3f, 0x43, 0x05, 0x1e, 0xdc, 0x45, 0x7f, 0xa4, 0x93, 0x76,
- 0xc6, 0x96, 0x94, 0x40, 0xef, 0x04, 0x45, 0x11, 0x58, 0xb2, 0x2c, 0x4b, 0xc8, 0x5c, 0x0a, 0xdf,
- 0x0b, 0xc2, 0xf2, 0x81, 0xe1, 0x79, 0x2d, 0xb2, 0x10, 0x56, 0xd5, 0x85, 0x44, 0xd5, 0xc1, 0xbb,
- 0x9c, 0xf4, 0x88, 0xdb, 0xc1, 0xfd, 0x81, 0x42, 0xb1, 0x84, 0x39, 0xab, 0xe2, 0xf2, 0xb0, 0x9f,
- 0x86, 0x33, 0x71, 0x10, 0x18, 0xb1, 0x8f, 0xcd, 0x67, 0x98, 0x8c, 0x7c, 0xf1, 0x01, 0xfc, 0xec,
- 0xc5, 0xe0, 0x95, 0xa0, 0x3e, 0xcf, 0x73, 0x86, 0xa8, 0x26, 0xf5, 0x37, 0xa0, 0x2f, 0x1f, 0x18,
- 0xce, 0x30, 0xbb, 0xf7, 0x9a, 0xbe, 0x10, 0x4e, 0xad, 0xfa, 0x68, 0x48, 0x12, 0x96, 0xf5, 0xd1,
- 0xdd, 0xc0, 0x12, 0x3a, 0x57, 0xb4, 0x31, 0x91, 0x63, 0xa8, 0x93, 0x4e, 0xe7, 0x20, 0x18, 0x55,
- 0xf5, 0x98, 0xa5, 0x73, 0xce, 0x42, 0x7e, 0x65, 0x31, 0xc4, 0x64, 0xd9, 0x13, 0x16, 0xdd, 0x57,
- 0xf2, 0xc7, 0x2d, 0x1c, 0x7c, 0x92, 0x2f, 0xf4, 0x48, 0xab, 0x54, 0x9b, 0x0a, 0xc9, 0x27, 0xa8,
- 0x88, 0x42, 0x3d, 0xdd, 0x09, 0x11, 0x2c, 0xc1, 0x2b, 0xd9, 0x49, 0xe4, 0x27, 0x7d, 0xc2, 0xcd,
- 0x23, 0x42, 0xb3, 0x3e, 0x5a, 0x6d, 0x9a, 0x4d, 0xeb, 0xc8, 0xf6, 0xc0, 0xc0, 0xef, 0xd5, 0x29,
- 0x36, 0xd6, 0x8a, 0x04, 0x4b, 0x64, 0xc3, 0xae, 0x19, 0xd2, 0x2d, 0x04, 0x88, 0x15, 0x50, 0x67,
- 0xaf, 0x01, 0xc5, 0xf4, 0xc6, 0x0b, 0x88, 0xc5, 0xc2, 0x49, 0x07, 0x58, 0x8a, 0x9d, 0xd2, 0xa0,
- 0xe5, 0x76, 0x1e, 0x2d, 0x48, 0x45, 0xf3, 0x9a, 0x1e, 0x4e, 0xda, 0xf3, 0xb1, 0xd8, 0x40, 0x2a,
- 0x7b, 0xf3, 0x55, 0xfc, 0x5d, 0xf3, 0x5c, 0x06, 0x0e, 0xdc, 0x6c, 0xa3, 0x58, 0x22, 0x3f, 0x88,
- 0x09, 0x3f, 0x53, 0x2f, 0x6d, 0x88, 0x3e, 0x03, 0x0b, 0x07, 0xca, 0x70, 0xfa, 0xb2, 0x60, 0x2c,
- 0xa5, 0x70, 0x05, 0x47, 0x12, 0x63, 0x3b, 0x8e, 0x16, 0x64, 0x92, 0xcd, 0xa7, 0xe1, 0xf6, 0x58,
- 0xaf, 0x0d, 0xf1, 0xf6, 0xc8, 0x93, 0x4f, 0x16, 0x55, 0x7f, 0x69, 0xf1, 0xe7, 0xc1, 0x37, 0x5b,
- 0x2c, 0xfa, 0x32, 0x3b, 0x96, 0x28, 0x5a, 0x30, 0xa7, 0x3f, 0xa3, 0x03, 0xab, 0xa8, 0xc7, 0x5c,
- 0x88, 0xed, 0xb3, 0x11, 0x9e, 0x94, 0x88, 0x65, 0xfe, 0xf7, 0x5e, 0xec, 0xd4, 0x60, 0x46, 0x6c,
- 0x04, 0x9f, 0xc1, 0x21, 0x23, 0xb4, 0x4a, 0xdb, 0xad, 0xeb, 0xd6, 0x5f, 0xd3, 0xd7, 0x58, 0xa1,
- 0x4b, 0x26, 0xc4, 0xe0, 0xee, 0x13, 0xdc, 0x9d, 0x2c, 0x75, 0xc2, 0x66, 0xe5, 0xb8, 0xc9, 0x34,
- 0x50, 0xd6, 0x4f, 0xb1, 0x60, 0x09, 0x99, 0x53, 0xe9, 0x03, 0xb8, 0xab, 0x3e, 0xd2, 0x3d, 0xa0,
- 0x4f, 0x59, 0x94, 0x65, 0xbc, 0xb3, 0x11, 0x61, 0xb0, 0x14, 0xd3, 0xb8, 0x70, 0xc6, 0x76, 0xe7,
- 0x95, 0x29, 0xc2, 0xa2, 0xb8, 0x42, 0x40, 0xdd, 0x6f, 0x8d, 0x15, 0x7c, 0x58, 0x21, 0x57, 0x54,
- 0x7b, 0xac, 0xc5, 0xc6, 0xf2, 0x70, 0xa3, 0x1b, 0xb5, 0x53, 0xca, 0x4c, 0x7c, 0xf1, 0xb9, 0x56,
- 0x88, 0xad, 0x13, 0xda, 0xad, 0x35, 0xdf, 0xab, 0xa1, 0x61, 0x62, 0x3e, 0x99, 0x78, 0x61, 0x59,
- 0xc9, 0xfc, 0x48, 0x67, 0xc4, 0xb6, 0x0a, 0xa8, 0x21, 0x89, 0x24, 0x96, 0x68, 0x2c, 0x87, 0x24,
- 0xe8, 0xcb, 0xb5, 0x3c, 0xf2, 0xf1, 0xd0, 0x49, 0xda, 0xa5, 0xdc, 0x32, 0xdc, 0xb3, 0xb3, 0x5e,
- 0x48, 0x44, 0x30, 0xc1, 0xea, 0x9a, 0x1f, 0x68, 0xd2, 0x8d, 0xa9, 0x4a, 0xc9, 0x15, 0x62, 0x06,
- 0xbf, 0x4f, 0x1c, 0x22, 0xc1, 0xd3, 0x42, 0x79, 0x85, 0x46, 0x0c, 0x38, 0xf3, 0xc4, 0xb9, 0x45,
- 0x8a, 0x25, 0x86, 0xc7, 0x66, 0xa9, 0x67, 0xb6, 0xd0, 0xa1, 0xc2, 0x0b, 0xe9, 0xcc, 0xc2, 0x72,
- 0x0a, 0x96, 0x24, 0x9d, 0xb1, 0xb0, 0xfa, 0xd5, 0xa6, 0x7c, 0x90, 0x1c, 0x53, 0xad, 0x0f, 0x84,
- 0xbc, 0xb9, 0x32, 0xd9, 0x37, 0xc2, 0x6b, 0x06, 0x4c, 0x3b, 0xab, 0x1a, 0x53, 0x45, 0xa9, 0x5d,
- 0xf9, 0x13, 0xd3, 0xbb, 0xe6, 0x1e, 0x73, 0xb5, 0x69, 0x54, 0x85, 0xea, 0x10, 0x8f, 0xe9, 0x8e,
- 0x69, 0x21, 0x57, 0x44, 0x41, 0x66, 0x8f, 0x1b, 0x80, 0x95, 0x5f, 0x1c, 0x99, 0x05, 0x28, 0xc7,
- 0x07, 0x58, 0x28, 0xd1, 0xeb, 0xdf, 0x62, 0x7f, 0x5e, 0xfe, 0x01, 0x3d, 0x0f, 0x97, 0x6b, 0x4a,
- 0xc0, 0x9a, 0x05, 0x8e, 0xc0, 0x3b, 0xfa, 0xa8, 0xba, 0x10, 0x2c, 0x7f, 0x4d, 0x63, 0x29, 0xae,
- 0x71, 0x51, 0x77, 0x0a, 0x69, 0x13, 0xaa, 0x4b, 0x10, 0x6f, 0x5a, 0x36, 0x1c, 0x61, 0x40, 0x1d,
- 0x3d, 0xa6, 0xad, 0xd2, 0xfe, 0xc4, 0x54, 0x63, 0x7d, 0xe8, 0xf8, 0xca, 0x1e, 0x1b, 0xa8, 0x36,
- 0xdd, 0xd1, 0x43, 0x25, 0x29, 0x54, 0xd2, 0x03, 0x87, 0xd3, 0x0f, 0xd4, 0x04, 0x3f, 0x1a, 0x18,
- 0x63, 0x32, 0xad, 0x50, 0xf1, 0x64, 0xfc, 0xa0, 0x3b, 0x92, 0x2d, 0xa6, 0xf7, 0xe1, 0x77, 0x87,
- 0xbf, 0x7e, 0xd1, 0x29, 0xa3, 0xe6, 0x4b, 0xd4, 0x94, 0xd5, 0xbd, 0x38, 0xff, 0x02, 0xdc, 0x7d,
- 0x9d, 0x52, 0xc2, 0xee, 0x2d, 0x04, 0x4b, 0xd0, 0x97, 0xe2, 0x3e, 0x09, 0xbc, 0x33, 0x36, 0x20,
- 0x0d, 0xc9, 0x59, 0x55, 0xab, 0xbb, 0x5e, 0x42, 0x65, 0x49, 0xc8, 0x1b, 0x55, 0xc3, 0xbd, 0xec,
- 0x77, 0x8e, 0xeb, 0x9e, 0x6d, 0x47, 0xec, 0x33, 0x88, 0xc7, 0x8d, 0xa9, 0x10, 0xb3, 0xd6, 0x49,
- 0xca, 0x5a, 0x9a, 0xc1, 0x2b, 0xc9, 0x59, 0x15, 0x58, 0x05, 0x5b, 0x86, 0x77, 0xcd, 0x67, 0x74,
- 0x8f, 0x53, 0x74, 0x0d, 0xf4, 0x58, 0xdc, 0xff, 0x7c, 0x67, 0x69, 0x6b, 0x90, 0x3a, 0x50, 0x96,
- 0xcf, 0xd6, 0xa5, 0x71, 0xb3, 0xed, 0xf5, 0x78, 0x39, 0x8d, 0x21, 0x6f, 0xb6, 0xcb, 0xfe, 0xfb,
- 0xb0, 0x86, 0x66, 0x6f, 0x38, 0xa5, 0x2c, 0x24, 0x07, 0x6f, 0x43, 0x92, 0x7f, 0x09, 0x58, 0xe2,
- 0x56, 0x29, 0x12, 0x59, 0x46, 0xf7, 0xf3, 0x13, 0x47, 0xd2, 0x19, 0xef, 0xb5, 0x01, 0x92, 0xdb,
- 0x8e, 0xa0, 0x17, 0x22, 0x4f, 0xb5, 0xae, 0x16, 0x1b, 0x30, 0x6b, 0x41, 0xef, 0x27, 0x21, 0x3a,
- 0x46, 0x6c, 0x56, 0x35, 0x6f, 0x79, 0xe8, 0xa8, 0xb1, 0xba, 0x04, 0x55, 0x26, 0xa0, 0x7f, 0xf6,
- 0x57, 0x5b, 0x22, 0x8b, 0x7c, 0x06, 0xa7, 0x27, 0xb1, 0x92, 0x32, 0x67, 0x08, 0xf4, 0x9b, 0x11,
- 0x1c, 0xd9, 0x72, 0xfc, 0xbf, 0x33, 0x62, 0x9b, 0xf2, 0xa8, 0xba, 0xd9, 0xf4, 0x6f, 0x9d, 0x4f,
- 0xdf, 0x48, 0x45, 0x12, 0xe6, 0x90, 0xec, 0xbb, 0xc3, 0x23, 0x25, 0xa8, 0x33, 0x7b, 0xfd, 0x8e,
- 0xbd, 0x92, 0x8a, 0x68, 0x50, 0x52, 0x0c, 0x4f, 0x0a, 0x96, 0x2b, 0x44, 0x6c, 0x00, 0x9d, 0xac,
- 0x62, 0x48, 0xc2, 0x0d, 0xf8, 0x96, 0xa1, 0xc7, 0xfc, 0x95, 0x1d, 0x72, 0x1a, 0x6a, 0xdd, 0xbd,
- 0xb6, 0x73, 0x81, 0x49, 0xcf, 0x84, 0xbd, 0x27, 0x23, 0x9a, 0xc0, 0xb9, 0x59, 0x4d, 0xa1, 0x3e,
- 0x3f, 0xc0, 0xb1, 0x51, 0xc9, 0xf7, 0x3d, 0xab, 0x00, 0x7a, 0x33, 0xad, 0x10, 0x0a, 0xb2, 0x4b,
- 0x39, 0x46, 0xe9, 0xf8, 0xd9, 0x8c, 0x73, 0x4c, 0xd5, 0xa5, 0x6c, 0x54, 0x6e, 0x12, 0xa0, 0xc3,
- 0xe5, 0xbc, 0xbf, 0xa4, 0x6f, 0xa1, 0xf5, 0x2f, 0x74, 0x56, 0x1c, 0x65, 0xd1, 0xf3, 0xbd, 0xe4,
- 0x93, 0xa1, 0xc9, 0xa2, 0xf9, 0x2f, 0x87, 0x2f, 0x51, 0x4f, 0x85, 0x69, 0xf3, 0xad, 0x4c, 0xe6,
- 0x46, 0x7d, 0x14, 0x62, 0xeb, 0xe2, 0xa7, 0xb4, 0x38, 0x96, 0x2b, 0x04, 0x54, 0x27, 0x65, 0x47,
- 0x32, 0x12, 0x5f, 0x8e, 0x2e, 0x47, 0xd0, 0x1c, 0x0a, 0xb5, 0xcd, 0xff, 0x68, 0x9d, 0xb0, 0x5f,
- 0xf7, 0x00, 0xeb, 0x4f, 0x93, 0xee, 0x10, 0x79, 0xcf, 0xde, 0x1f, 0x58, 0xa0, 0xd0, 0x84, 0x5b,
- 0xac, 0x46, 0x65, 0x6a, 0x64, 0xaf, 0xa4, 0xe4, 0x89, 0xfa, 0x4b, 0xcb, 0xc7, 0x66, 0x2e, 0x2f,
- 0xa6, 0x94, 0xdc, 0xdf, 0x38, 0x01, 0x20, 0x79, 0x88, 0x1c, 0x53, 0x61, 0x5a, 0x60, 0x56, 0x02,
- 0xcd, 0xb7, 0x75, 0x29, 0x65, 0xd2, 0x3f, 0x9d, 0xd3, 0x37, 0xe9, 0x56, 0xd5, 0xfc, 0x27, 0x60,
- 0x7b, 0x3e, 0x57, 0x9b, 0xa7, 0xde, 0x4a, 0xc5, 0x91, 0x99, 0x49, 0xd9, 0x84, 0xbf, 0x68, 0x54,
- 0xf6, 0xda, 0x76, 0x86, 0xe6, 0x60, 0x4c, 0xda, 0xfd, 0xa5, 0x18, 0x96, 0x33, 0x78, 0x8d, 0xd5,
- 0x97, 0x91, 0x25, 0x86, 0xf1, 0x42, 0x62, 0xd3, 0x91, 0xe9, 0x75, 0x7a, 0xae, 0x0e, 0x2f, 0x0f,
- 0x2f, 0x0e, 0x2d, 0x36, 0x2c, 0xb6, 0xf9, 0xda, 0x02, 0x4f, 0xc3, 0x35, 0x56, 0xd8, 0xc5, 0x8d,
- 0xca, 0x87, 0x0e, 0x40, 0xb3, 0xd7, 0x9e, 0xb9, 0x9b, 0x69, 0x25, 0xf9, 0x05, 0xe5, 0x81, 0xb1,
- 0x6c, 0xb3, 0xf2, 0x92, 0x2a, 0xed, 0xb8, 0x65, 0x3f, 0xd9, 0x61, 0x50, 0x06, 0x5d, 0xb7, 0xae,
- 0xd9, 0x8c, 0x5b, 0x7b, 0x6d, 0x13, 0xf6, 0xcc, 0xb3, 0xd7, 0x56, 0x63, 0x9d, 0xb7, 0x40, 0xae,
- 0x27, 0xfb, 0x04, 0x5c, 0xee, 0xdd, 0xc2, 0x29, 0x64, 0xed, 0x24, 0x11, 0x3c, 0xca, 0x4c, 0x9e,
- 0x6c, 0xfe, 0xd5, 0x61, 0xf8, 0x2c, 0x38, 0xdf, 0x4e, 0xec, 0x00, 0x4d, 0x67, 0xbc, 0x2e, 0x20,
- 0x25, 0xaf, 0x20, 0x37, 0x96, 0xd0, 0x69, 0xea, 0x7c, 0x9a, 0xbd, 0xc3, 0xbe, 0x6e, 0x8f, 0x11,
- 0xbe, 0x6d, 0x7b, 0x8b, 0x35, 0x66, 0x89, 0x59, 0x5a, 0x3e, 0xfd, 0xd1, 0x1e, 0x77, 0x57, 0xac,
- 0x83, 0x74, 0x3a, 0x23, 0xed, 0xd1, 0x3e, 0xcf, 0x98, 0x0a, 0x76, 0x30, 0x64, 0x05, 0xd5, 0xba,
- 0x20, 0xf7, 0xa8, 0xc5, 0xc6, 0xf6, 0x00, 0xe7, 0xa3, 0x09, 0x77, 0x43, 0x1c, 0x03, 0xe2, 0x0a,
- 0x31, 0x6e, 0x89, 0x0d, 0xec, 0x9f, 0x5c, 0xb2, 0xcc, 0xcb, 0x3d, 0x16, 0xe0, 0x57, 0x86, 0x8e,
- 0x1d, 0x6d, 0x81, 0xf4, 0x79, 0x8e, 0xee, 0x24, 0x50, 0xeb, 0xaa, 0xb1, 0x72, 0x9d, 0xe5, 0x98,
- 0xf3, 0x55, 0xf7, 0xb7, 0xa6, 0x3f, 0xbe, 0xc6, 0x93, 0x49, 0xc0, 0xf0, 0x4d, 0x66, 0xf2, 0xd0,
- 0xdc, 0x38, 0x72, 0xfa, 0x4f, 0xd0, 0xce, 0xd9, 0xc9, 0xed, 0x97, 0x2f, 0x3e, 0x15, 0x0c, 0x7a,
- 0x73, 0xe7, 0xfb, 0x88, 0x61, 0xa9, 0xc1, 0xb6, 0x0c, 0xc0, 0x0d, 0x93, 0x8e, 0x64, 0x24, 0xd1,
- 0x16, 0x18, 0xb7, 0x74, 0x29, 0x4b, 0x5f, 0x81, 0x78, 0xc0, 0x08, 0x8e, 0x22, 0x79, 0x9b, 0x04,
- 0xe4, 0xfb, 0xb6, 0x58, 0xa7, 0x02, 0x6d, 0x7e, 0xa8, 0x75, 0x62, 0xff, 0x95, 0x31, 0x15, 0xb0,
- 0x06, 0xb7, 0xba, 0xd9, 0xb5, 0xe0, 0xa3, 0x09, 0x9c, 0x23, 0x95, 0x94, 0xaf, 0xf9, 0x0f, 0x94,
- 0x3d, 0xff, 0xf5, 0x8b, 0xdf, 0x1f, 0xa9, 0x78, 0xf3, 0x5f, 0xcf, 0xef, 0x5f, 0xe6, 0x16, 0xc3,
- 0x13, 0x61, 0x9a, 0xb0, 0x87, 0xbc, 0xbd, 0xb6, 0x52, 0x32, 0xfb, 0xec, 0x31, 0x13, 0xfe, 0x3e,
- 0x37, 0x6e, 0x45, 0x9d, 0x38, 0xe0, 0x79, 0xa1, 0xff, 0x61, 0xb3, 0x89, 0x38, 0x31, 0xc4, 0x49,
- 0x25, 0x87, 0x63, 0x12, 0x4d, 0xc6, 0x43, 0x79, 0xe9, 0xe5, 0x17, 0x47, 0x98, 0xcf, 0x1c, 0x53,
- 0xe5, 0x6b, 0xd3, 0x42, 0x85, 0xa5, 0xda, 0x2f, 0x45, 0x2e, 0x6b, 0xb2, 0x60, 0x09, 0x77, 0x92,
- 0xa9, 0x9f, 0x8a, 0x2a, 0xe4, 0xeb, 0xfc, 0x6b, 0x86, 0x5c, 0x37, 0x65, 0x1a, 0x2c, 0xb5, 0xe6,
- 0xa8, 0x51, 0x09, 0x9d, 0x13, 0xfa, 0x18, 0x34, 0x15, 0x24, 0x67, 0x43, 0x40, 0x2d, 0xd4, 0x45,
- 0xec, 0x9f, 0x7e, 0x3a, 0x75, 0x84, 0xd9, 0xd5, 0xd4, 0xd3, 0xeb, 0xdf, 0x6d, 0x82, 0x4a, 0xf7,
- 0x3d, 0x97, 0x4c, 0x36, 0x57, 0x67, 0x7d, 0x00, 0x4e, 0x8e, 0xdc, 0xf1, 0xaf, 0x4d, 0xa2, 0xd5,
- 0x5d, 0xe7, 0xdf, 0x76, 0x8c, 0x5b, 0xc0, 0x8a, 0x2b, 0x25, 0x15, 0xd0, 0x9f, 0xeb, 0xc3, 0xf2,
- 0x0f, 0x1e, 0xbd, 0x06, 0x1e, 0x65, 0x46, 0x24, 0x39, 0xd9, 0xa4, 0xe7, 0xf5, 0xf2, 0xdf, 0x32,
- 0x9f, 0xdb, 0xa5, 0x5c, 0xf0, 0xe4, 0x97, 0x61, 0x39, 0x18, 0x83, 0x4e, 0x16, 0xe2, 0xef, 0xcb,
- 0x26, 0x97, 0xa5, 0xe4, 0x07, 0xee, 0x74, 0x99, 0x1c, 0x8c, 0x6f, 0x3b, 0x76, 0x72, 0xb3, 0x32,
- 0xab, 0x02, 0xae, 0xff, 0x5a, 0x6a, 0x67, 0x6f, 0x19, 0x9e, 0xd7, 0x02, 0x9a, 0x9c, 0x4d, 0xfb,
- 0x59, 0xc9, 0x07, 0xe5, 0x4e, 0x6e, 0x2d, 0x8e, 0x9e, 0x90, 0xfd, 0xa7, 0x6e, 0x3f, 0x98, 0x7e,
- 0x50, 0x56, 0xc0, 0x9a, 0xa1, 0xc5, 0x06, 0xfc, 0xd4, 0x62, 0xbc, 0x47, 0x70, 0xa3, 0x47, 0xe9,
- 0x7d, 0x1b, 0xf4, 0x09, 0x8c, 0xaa, 0xab, 0xb4, 0x65, 0x1f, 0xfe, 0x97, 0xf9, 0xed, 0xc6, 0xa1,
- 0xa3, 0x49, 0xfd, 0x28, 0x40, 0x31, 0x7c, 0x9c, 0x99, 0x6f, 0xb2, 0xbf, 0x77, 0x1e, 0xfd, 0xee,
- 0xd5, 0xbf, 0x67, 0x22, 0xd4, 0x5d, 0xca, 0x72, 0x57, 0x3e, 0x67, 0xad, 0x2f, 0x0e, 0xbc, 0xae,
- 0x62, 0xef, 0x8a, 0x24, 0xd6, 0x33, 0xc6, 0x0a, 0x8c, 0x58, 0xb3, 0x59, 0xc8, 0xd5, 0x14, 0xa1,
- 0x2b, 0x70, 0x27, 0xec, 0xf9, 0x54, 0xe0, 0x0a, 0xa5, 0x3c, 0xe4, 0xa5, 0xfc, 0x14, 0x4a, 0xeb,
- 0x80, 0xde, 0x6c, 0xe4, 0x79, 0x28, 0x5f, 0xbe, 0x70, 0x02, 0xf6, 0x75, 0x72, 0x2f, 0x3b, 0x65,
- 0xe3, 0x1f, 0xee, 0x07, 0x07, 0x29, 0x8a, 0x8c, 0x37, 0x9b, 0x1f, 0x3a, 0xa0, 0xc7, 0x95, 0x58,
- 0xfd, 0xe2, 0x08, 0x5e, 0xeb, 0xea, 0xa7, 0x35, 0x45, 0xb3, 0xb9, 0xcc, 0xd4, 0x6c, 0xfe, 0xe9,
- 0xa7, 0xff, 0x78, 0xfe, 0x48, 0x83, 0xef, 0xb8, 0x8f, 0xc2, 0x8b, 0x9e, 0x80, 0x1b, 0xa0, 0x88,
- 0x70, 0x6c, 0xa0, 0xe6, 0x69, 0x6a, 0x36, 0x24, 0x51, 0x3d, 0x5e, 0x71, 0xfc, 0xf5, 0x3f, 0x5d,
- 0x21, 0x90, 0x9f, 0xda, 0xa8, 0xac, 0xb1, 0xe6, 0x83, 0xa6, 0x33, 0x67, 0xfd, 0x25, 0x8b, 0x50,
- 0xe6, 0x18, 0x5e, 0xa3, 0x32, 0xf5, 0x7c, 0x06, 0x5c, 0x5b, 0xdd, 0x3b, 0x43, 0x12, 0xed, 0x8e,
- 0x6b, 0x7a, 0x40, 0x93, 0x5a, 0x0d, 0x6a, 0x6f, 0x57, 0x25, 0xfd, 0xcd, 0xff, 0xc0, 0x16, 0x2b,
- 0x9c, 0xc2, 0x13, 0x4a, 0xb6, 0x70, 0x6a, 0xef, 0xf3, 0xf0, 0x50, 0xed, 0x6b, 0x93, 0x6e, 0xde,
- 0x02, 0x27, 0xec, 0x3d, 0xbb, 0x78, 0x2d, 0x6a, 0x54, 0x0d, 0x6c, 0xd6, 0xad, 0xee, 0x7b, 0x94,
- 0x5d, 0xfb, 0x8d, 0xfd, 0x0f, 0x9f, 0x3e, 0xea, 0xf2, 0x9d, 0x7d, 0x76, 0xf6, 0xd9, 0x7b, 0xcf,
- 0x4e, 0x3f, 0x3b, 0x4d, 0x63, 0x77, 0x9c, 0xc1, 0x94, 0x42, 0x91, 0xfa, 0xe9, 0x59, 0xd9, 0x05,
- 0x98, 0xcf, 0x3a, 0x9e, 0x9d, 0x65, 0xe6, 0x7b, 0xbf, 0x6a, 0xc6, 0xfe, 0x4c, 0x41, 0x02, 0x9e,
- 0xe0, 0xcf, 0x8c, 0x5b, 0xa4, 0x67, 0x8e, 0x48, 0xf1, 0xed, 0x23, 0x89, 0x66, 0x73, 0xa6, 0xef,
- 0xdd, 0x6b, 0x4f, 0xff, 0xeb, 0xa9, 0xe0, 0xce, 0xb3, 0xdc, 0xd1, 0xce, 0x5e, 0x33, 0xd4, 0xf9,
- 0xfb, 0x03, 0x7d, 0x6e, 0x88, 0x05, 0x9d, 0xa1, 0xd1, 0x1c, 0xc1, 0xf4, 0x95, 0x1d, 0x7c, 0xa9,
- 0xa4, 0xb1, 0x7c, 0xf4, 0xda, 0xde, 0xfb, 0x25, 0x48, 0x5b, 0x5e, 0xd3, 0xe3, 0xf4, 0xbd, 0x9d,
- 0x94, 0x8a, 0x37, 0x88, 0xde, 0x00, 0x9b, 0x35, 0x74, 0x53, 0xfa, 0x9d, 0xbb, 0x62, 0xdc, 0x37,
- 0x26, 0x1b, 0x6e, 0x18, 0x96, 0x5d, 0x91, 0x7d, 0x22, 0xbb, 0x4c, 0x21, 0xc5, 0xca, 0x60, 0xc3,
- 0xb3, 0xf7, 0x28, 0x0c, 0x3f, 0x69, 0x18, 0x6e, 0xf8, 0x3c, 0x39, 0x87, 0xd1, 0x94, 0x5d, 0xf9,
- 0x5d, 0x4f, 0x95, 0x76, 0x4c, 0xa5, 0xa0, 0xac, 0xa9, 0x46, 0x25, 0xa6, 0x8d, 0x7d, 0x96, 0x3f,
- 0x6b, 0x6f, 0x76, 0x24, 0x23, 0x89, 0xb2, 0x0c, 0xf7, 0x24, 0x5d, 0xca, 0xfa, 0xb4, 0xce, 0x9a,
- 0xce, 0x78, 0x99, 0x29, 0xbf, 0x3a, 0xea, 0x4c, 0xb2, 0x59, 0x66, 0xfa, 0x3a, 0xd8, 0x1f, 0xbc,
- 0x4e, 0xe9, 0x1d, 0x14, 0x3d, 0xe8, 0x79, 0xdd, 0xf1, 0x46, 0xd2, 0x6e, 0x60, 0x65, 0x53, 0x56,
- 0x71, 0x74, 0xef, 0xfd, 0x12, 0xd0, 0x96, 0xb3, 0xaa, 0xad, 0x4b, 0xbd, 0xf6, 0xb8, 0x77, 0x29,
- 0x2c, 0xc5, 0x06, 0x98, 0xc1, 0x43, 0x5e, 0xe8, 0x78, 0xf6, 0x6a, 0xf4, 0x51, 0xf0, 0xdf, 0x7d,
- 0xb2, 0xe5, 0x8e, 0xc5, 0xe1, 0xc5, 0xe1, 0xbb, 0xc3, 0x77, 0x3b, 0xa6, 0x1b, 0x3e, 0x97, 0x7d,
- 0xf2, 0xec, 0x2c, 0x75, 0xa2, 0x32, 0x48, 0x36, 0x5c, 0xb9, 0xf0, 0x8b, 0x8e, 0xdb, 0x43, 0x94,
- 0xb7, 0x3d, 0xcc, 0x9f, 0x77, 0x3b, 0x6e, 0x37, 0xdc, 0xb8, 0x6b, 0xee, 0xd6, 0x61, 0xda, 0xe7,
- 0xb5, 0xc0, 0x99, 0x1b, 0x1b, 0xa8, 0xa5, 0x63, 0xdc, 0xbb, 0x85, 0x65, 0xba, 0xfd, 0x66, 0xc4,
- 0xee, 0x39, 0xc2, 0x69, 0x56, 0x4f, 0x2b, 0x53, 0x45, 0x0d, 0x91, 0xcb, 0x4d, 0x02, 0x59, 0xea,
- 0x9b, 0x04, 0x77, 0xe3, 0x2c, 0x6d, 0x6a, 0x30, 0x88, 0xec, 0x82, 0xbf, 0x09, 0x68, 0xf6, 0xbe,
- 0xff, 0x97, 0xcd, 0x4e, 0x84, 0xe1, 0x51, 0x9e, 0x7f, 0x26, 0xfb, 0xe3, 0x6b, 0x7b, 0x7f, 0x53,
- 0x02, 0x71, 0x71, 0xa4, 0x2d, 0x81, 0x37, 0xbe, 0x94, 0x14, 0x4a, 0xe0, 0x26, 0x01, 0xcf, 0x26,
- 0x7c, 0xb2, 0x52, 0xb2, 0x3d, 0x06, 0xfd, 0xb4, 0x36, 0x82, 0x21, 0xcf, 0xa2, 0x3b, 0xe4, 0x62,
- 0xe6, 0xcd, 0x8e, 0x45, 0x0a, 0xcd, 0x61, 0xea, 0x34, 0x3d, 0x4d, 0x9f, 0xae, 0x67, 0x65, 0x57,
- 0x3a, 0x6e, 0x0c, 0x2f, 0x56, 0x2c, 0xc3, 0x6f, 0xe3, 0xcc, 0x0c, 0xd1, 0xff, 0xfd, 0xcd, 0x7c,
- 0xc7, 0xe2, 0xa3, 0xc9, 0xdf, 0x9b, 0x21, 0x92, 0x34, 0x6e, 0xe9, 0xb5, 0x41, 0xa7, 0xc4, 0x90,
- 0x17, 0xba, 0xb2, 0x71, 0x53, 0xc8, 0x12, 0xec, 0x8b, 0x7f, 0x1d, 0xe4, 0x7e, 0xd7, 0x16, 0x68,
- 0x67, 0x62, 0xa9, 0xce, 0xf8, 0xb9, 0x00, 0xf7, 0xf3, 0xfe, 0xc0, 0x4d, 0x3a, 0x9e, 0x73, 0x2d,
- 0xad, 0xa2, 0x64, 0x55, 0x9d, 0xce, 0xcd, 0x74, 0x33, 0x1e, 0x1b, 0x98, 0x55, 0x41, 0x6e, 0x4b,
- 0x8f, 0xb9, 0xc5, 0x56, 0xeb, 0x0a, 0x79, 0xe1, 0x5b, 0xf4, 0xb9, 0xef, 0x39, 0xa0, 0x97, 0x4a,
- 0x3e, 0xb2, 0xa9, 0xc1, 0xc6, 0x2d, 0xd0, 0xb1, 0x66, 0xd2, 0xfd, 0x17, 0xd7, 0x7f, 0x39, 0xd8,
- 0x7e, 0x96, 0xb1, 0xf5, 0x64, 0xbc, 0xb8, 0x09, 0x75, 0xc6, 0xee, 0x3d, 0x96, 0x34, 0x53, 0x84,
- 0x6e, 0x9e, 0xf6, 0x47, 0x5a, 0x6c, 0x33, 0x02, 0x1f, 0x6b, 0xcb, 0xb0, 0xed, 0xd8, 0x76, 0xcc,
- 0x5b, 0x84, 0xd6, 0x41, 0xb7, 0x0e, 0x3c, 0xb2, 0xe5, 0xf8, 0x43, 0xfb, 0xac, 0xaa, 0x51, 0xd9,
- 0x48, 0xa2, 0xd9, 0xa5, 0x3c, 0xb1, 0x3e, 0x7c, 0x97, 0x92, 0xcc, 0xcb, 0xcf, 0xde, 0x03, 0x3d,
- 0x29, 0xbb, 0xdc, 0xf0, 0xf9, 0xd0, 0xdd, 0xe9, 0xf5, 0x6f, 0x6c, 0xec, 0x3b, 0xb8, 0x19, 0xb3,
- 0x9c, 0x58, 0xed, 0xb8, 0xfd, 0xca, 0x78, 0x6c, 0x00, 0xb7, 0xde, 0xb3, 0x4f, 0x7a, 0xa8, 0x55,
- 0xf0, 0xcc, 0x51, 0x27, 0x10, 0x7f, 0x62, 0x5a, 0xe8, 0x36, 0x1c, 0x61, 0x64, 0xad, 0x3e, 0x0a,
- 0x1c, 0x81, 0xec, 0x64, 0x99, 0x79, 0xc2, 0x89, 0x05, 0x0f, 0xfd, 0x1d, 0xe8, 0xd9, 0xa5, 0x9c,
- 0xb7, 0xa0, 0x88, 0x4e, 0x93, 0x2e, 0x75, 0xad, 0x71, 0x6b, 0x3a, 0xdb, 0x28, 0xc4, 0x04, 0x09,
- 0xff, 0x46, 0x98, 0x8d, 0xcc, 0xa2, 0x39, 0x18, 0x0f, 0x79, 0xc7, 0x2d, 0xf9, 0xda, 0x43, 0x23,
- 0x78, 0x6c, 0x60, 0x29, 0xf8, 0x28, 0x78, 0x73, 0xe1, 0xe6, 0x64, 0xf8, 0x67, 0xd4, 0x0a, 0x1c,
- 0xa7, 0xfd, 0x4a, 0x5e, 0x44, 0xf3, 0xd7, 0x6f, 0xa4, 0x66, 0x7f, 0xed, 0xf6, 0x10, 0x6a, 0xcb,
- 0x54, 0xed, 0x81, 0x2a, 0x85, 0xb7, 0x1d, 0xc2, 0x27, 0x6b, 0xb1, 0x65, 0x62, 0xa0, 0xeb, 0x52,
- 0x2e, 0x47, 0x86, 0x17, 0x1b, 0x7e, 0xc1, 0x60, 0x49, 0x49, 0xe5, 0x85, 0x1b, 0xc3, 0xcb, 0xce,
- 0x08, 0xf6, 0x76, 0xfa, 0x93, 0xe3, 0x9f, 0xb6, 0xaf, 0x0f, 0x2f, 0x1e, 0xb9, 0x3d, 0x79, 0xb3,
- 0x9c, 0x92, 0x86, 0x25, 0xea, 0x74, 0xc2, 0xb4, 0xa9, 0x7a, 0x4b, 0x83, 0xc5, 0x06, 0xb8, 0x15,
- 0xee, 0x0f, 0xf0, 0x3d, 0xf9, 0x2a, 0x2d, 0x8a, 0xdd, 0x0c, 0xc6, 0xf8, 0x99, 0x3d, 0x0a, 0xf2,
- 0xba, 0x07, 0xbd, 0x7b, 0x35, 0x25, 0x77, 0x4b, 0x41, 0x06, 0x33, 0xb2, 0x62, 0x46, 0xd2, 0xe6,
- 0x52, 0x70, 0xdc, 0x32, 0xa6, 0x12, 0x7e, 0x17, 0x88, 0x02, 0x89, 0xa3, 0xb9, 0x49, 0xd4, 0x58,
- 0x2b, 0x22, 0x0d, 0xeb, 0xb2, 0xbb, 0x70, 0x36, 0x85, 0x4f, 0xf3, 0x63, 0x24, 0x80, 0xe5, 0x2f,
- 0xdf, 0xd8, 0xeb, 0xbb, 0x12, 0x74, 0x8b, 0xbc, 0x66, 0xe8, 0xb5, 0xc5, 0x29, 0xdb, 0x5a, 0xc8,
- 0x76, 0x3d, 0x82, 0xa3, 0x1d, 0x3b, 0x6f, 0x11, 0x3e, 0x1b, 0x92, 0x89, 0xa7, 0x61, 0xe1, 0xbb,
- 0xab, 0x4d, 0xcb, 0x21, 0x56, 0x2e, 0x19, 0xa9, 0xbc, 0x3d, 0xbd, 0xde, 0xef, 0x5b, 0xc9, 0xb0,
- 0x0e, 0xdb, 0x76, 0x67, 0x04, 0xe2, 0xd6, 0x47, 0x96, 0xfb, 0xfd, 0xdf, 0x87, 0x27, 0x3d, 0x5d,
- 0xca, 0x4c, 0xfa, 0x49, 0x41, 0x9e, 0x0b, 0xb0, 0x6b, 0xbc, 0xed, 0xe0, 0xa3, 0x5c, 0x66, 0x42,
- 0xb1, 0xf1, 0x72, 0x17, 0xf7, 0xcd, 0x8c, 0x58, 0x8f, 0x99, 0x95, 0xb0, 0x54, 0x1f, 0x79, 0xcd,
- 0x90, 0xeb, 0x76, 0x85, 0x43, 0xf2, 0x5c, 0x20, 0xaa, 0xe6, 0xe3, 0x66, 0xc4, 0xa2, 0xea, 0x7b,
- 0x76, 0x88, 0x5c, 0x8a, 0x5b, 0xbb, 0xe0, 0xd9, 0x4d, 0xd8, 0xda, 0x23, 0x43, 0xab, 0xa0, 0x69,
- 0x9e, 0x75, 0x84, 0x1b, 0x04, 0x68, 0xbe, 0xf4, 0xe8, 0xb5, 0x32, 0xd3, 0xde, 0xc6, 0xf1, 0x50,
- 0xa6, 0x4e, 0x99, 0x09, 0xbe, 0x71, 0x9f, 0x5b, 0xc8, 0xc2, 0x5a, 0xa5, 0x8d, 0xd0, 0x71, 0x33,
- 0x61, 0x3d, 0x23, 0x68, 0x4b, 0xf8, 0x79, 0xc8, 0xcb, 0x7f, 0xb7, 0x06, 0xab, 0xbd, 0x39, 0xbd,
- 0x3e, 0x74, 0x9b, 0xd6, 0x97, 0xe0, 0x87, 0x7c, 0xd2, 0x71, 0x63, 0x68, 0x71, 0x39, 0xf2, 0xfb,
- 0x0c, 0x7c, 0x3b, 0x46, 0x6c, 0xc1, 0xbd, 0x1c, 0x5d, 0x0e, 0x4d, 0xaf, 0x4f, 0x87, 0xea, 0x23,
- 0xe5, 0xae, 0x52, 0x32, 0xb3, 0xa5, 0xa1, 0xc1, 0xd6, 0x0c, 0xec, 0x1d, 0x23, 0xdf, 0x32, 0x9d,
- 0xc1, 0x27, 0x68, 0xef, 0xa2, 0x3e, 0xc6, 0xff, 0x06, 0x5d, 0x4a, 0x24, 0xab, 0x30, 0x39, 0x4d,
- 0x61, 0xa4, 0x9e, 0xaf, 0x4a, 0x9b, 0x9b, 0xab, 0x16, 0x9d, 0xd6, 0xd0, 0x29, 0x48, 0xc1, 0xfb,
- 0x26, 0x70, 0xaf, 0xdc, 0xea, 0x6a, 0xa7, 0xbb, 0x37, 0x0e, 0xc6, 0xa4, 0x64, 0x9d, 0x00, 0x9a,
- 0x0f, 0xed, 0x43, 0xa1, 0xe1, 0xe5, 0x8e, 0x69, 0xd9, 0x15, 0xca, 0x06, 0x14, 0xa0, 0xd9, 0x2e,
- 0xeb, 0x31, 0xef, 0x6d, 0x37, 0x45, 0xd0, 0x96, 0xcf, 0x6b, 0x7b, 0xcc, 0xe5, 0x94, 0xff, 0xdf,
- 0x6b, 0x13, 0x6a, 0xfc, 0x1a, 0x2b, 0x3c, 0xe5, 0xcb, 0x29, 0x7d, 0x06, 0xd6, 0x0c, 0x68, 0xf7,
- 0x4f, 0xd8, 0xf9, 0xba, 0x75, 0x06, 0x9f, 0xf2, 0x4f, 0xaf, 0x5e, 0x98, 0x6e, 0xb8, 0x42, 0xf9,
- 0x91, 0xef, 0x3d, 0xeb, 0x90, 0x0d, 0x77, 0x4c, 0x4f, 0xaf, 0x9e, 0x08, 0x45, 0x33, 0x70, 0x47,
- 0x96, 0x92, 0x84, 0x6f, 0x39, 0x46, 0xa1, 0x19, 0x75, 0x46, 0x1f, 0xe6, 0x8c, 0xb9, 0x94, 0x92,
- 0xc0, 0x4d, 0x4a, 0x9d, 0xe7, 0x82, 0x4c, 0x74, 0x05, 0x09, 0x3d, 0x4d, 0x7c, 0x71, 0x3e, 0x2f,
- 0x93, 0x11, 0x2b, 0x77, 0xb1, 0x48, 0xfa, 0x12, 0xe8, 0x36, 0x03, 0x76, 0x69, 0x6c, 0x60, 0x2a,
- 0x28, 0xe6, 0x93, 0xb2, 0x48, 0xf2, 0xa5, 0x19, 0xf2, 0x80, 0xa8, 0x3d, 0xcb, 0xc8, 0x79, 0x7b,
- 0xec, 0x0b, 0x89, 0xf5, 0xb9, 0x2b, 0x44, 0xf9, 0x4d, 0x27, 0xa0, 0x79, 0x03, 0xed, 0x6a, 0xe4,
- 0x6d, 0x03, 0xa2, 0x43, 0x32, 0xfd, 0xc7, 0x73, 0xfa, 0x59, 0x55, 0xfa, 0xed, 0xf5, 0xee, 0x0c,
- 0x96, 0x13, 0x7d, 0x7d, 0xa0, 0xcf, 0xfd, 0x75, 0xb0, 0xc7, 0xcc, 0x5f, 0x77, 0x0d, 0x86, 0xb4,
- 0x65, 0xb9, 0x4b, 0x88, 0xf0, 0x84, 0x1d, 0x76, 0xea, 0xcd, 0xf8, 0xb8, 0x80, 0xb1, 0x1e, 0x7b,
- 0xbb, 0x62, 0x7d, 0x9a, 0x7a, 0x02, 0xf0, 0x49, 0x28, 0xa9, 0xa4, 0xed, 0x9e, 0xe5, 0xd0, 0x5f,
- 0xbb, 0x84, 0x76, 0x31, 0x9a, 0xb3, 0x10, 0x55, 0x8f, 0x53, 0x68, 0xc6, 0x96, 0x02, 0x4d, 0x39,
- 0x7b, 0x18, 0xac, 0x10, 0xf7, 0xec, 0xe8, 0x3c, 0xe7, 0x7f, 0xd6, 0xac, 0x0a, 0x4e, 0x06, 0xc2,
- 0xcf, 0x5f, 0xfb, 0x6e, 0x1d, 0x67, 0xc1, 0x00, 0x7f, 0xdd, 0x0c, 0xde, 0xa4, 0x9b, 0xb0, 0x23,
- 0xb6, 0x7c, 0x71, 0x2c, 0x41, 0x4f, 0x36, 0xe9, 0xb8, 0xcf, 0xd8, 0x24, 0xd6, 0x2d, 0x83, 0x80,
- 0x24, 0x9a, 0x94, 0xb6, 0x96, 0x6e, 0x0b, 0x6d, 0x12, 0x93, 0x2e, 0x1a, 0x4d, 0xb0, 0xe9, 0x2f,
- 0x23, 0x34, 0x59, 0x0f, 0xf3, 0x9f, 0xdf, 0x6f, 0xd2, 0xed, 0x55, 0xd7, 0x5a, 0x96, 0x23, 0x0b,
- 0x22, 0xb1, 0x84, 0x5f, 0xb8, 0xf7, 0x14, 0x24, 0xac, 0x84, 0x93, 0xda, 0xfd, 0xfc, 0x75, 0x1c,
- 0xc1, 0x11, 0xc2, 0xdf, 0x87, 0x85, 0xf9, 0xc4, 0xe3, 0xe6, 0xf6, 0x10, 0x6d, 0xf9, 0x20, 0x2c,
- 0xa9, 0x13, 0x96, 0xb2, 0x7b, 0x42, 0xf3, 0x0c, 0x0f, 0xfa, 0x0a, 0x01, 0x59, 0x6c, 0xac, 0x26,
- 0x6a, 0xd2, 0x2d, 0x05, 0xd1, 0x2a, 0x85, 0x3c, 0xdc, 0x29, 0x09, 0xf1, 0xb0, 0x79, 0x0b, 0xdc,
- 0x8e, 0x72, 0x9f, 0xd7, 0xa5, 0x64, 0xf7, 0x13, 0x7f, 0x8f, 0x6d, 0x19, 0xe0, 0x9e, 0x91, 0xcf,
- 0xb1, 0x5e, 0x4a, 0x86, 0xbc, 0x9c, 0xd6, 0xdb, 0x08, 0x6f, 0x12, 0xd0, 0xef, 0x2d, 0x9c, 0x90,
- 0x92, 0x03, 0x92, 0xa0, 0xed, 0x38, 0xfe, 0x29, 0xa3, 0x20, 0x5b, 0x6c, 0xed, 0x1c, 0x92, 0x71,
- 0xb0, 0xf2, 0xa4, 0x22, 0x09, 0x73, 0x4c, 0x45, 0xe9, 0x90, 0x74, 0x34, 0x8f, 0x3a, 0x65, 0x53,
- 0x6f, 0x7d, 0xf2, 0x3e, 0x7b, 0x7b, 0x8d, 0x9e, 0x85, 0x9b, 0xf2, 0x82, 0xb1, 0x44, 0x77, 0x5d,
- 0xdf, 0x39, 0xe0, 0x96, 0x57, 0x18, 0x27, 0x98, 0xd3, 0x83, 0x7d, 0xff, 0x34, 0x2c, 0xf4, 0xbb,
- 0x67, 0x55, 0x28, 0xdf, 0x29, 0x9e, 0xa2, 0x2d, 0x7f, 0x74, 0x38, 0x59, 0xcb, 0xa7, 0x43, 0x76,
- 0xa1, 0x81, 0x3e, 0x61, 0x97, 0xfc, 0xac, 0x75, 0xd4, 0xa4, 0xab, 0xa3, 0x7c, 0x57, 0xf6, 0x9c,
- 0xdc, 0x32, 0x20, 0x6f, 0x23, 0x92, 0x78, 0xe8, 0xe0, 0x2c, 0x8d, 0x46, 0x25, 0xe4, 0xa4, 0x0f,
- 0xc6, 0xf8, 0x6c, 0xdb, 0xc0, 0x3a, 0x92, 0x1a, 0x93, 0xa3, 0xbc, 0x7e, 0xbb, 0x90, 0x2b, 0x0d,
- 0x18, 0x2d, 0x58, 0xbd, 0x0a, 0x73, 0x2a, 0xb8, 0xed, 0xe0, 0x5e, 0x67, 0x1a, 0xe1, 0x04, 0x44,
- 0x21, 0x21, 0x0f, 0x6b, 0x81, 0xf6, 0x6b, 0x5b, 0xdd, 0xdc, 0xce, 0x5c, 0x21, 0xa0, 0xe6, 0x80,
- 0xfa, 0xcb, 0xa4, 0x54, 0xb6, 0xba, 0x67, 0x24, 0xd8, 0xb1, 0xfc, 0xd5, 0xc0, 0xde, 0x26, 0x16,
- 0x92, 0x68, 0x5e, 0xe0, 0xd0, 0x1c, 0x94, 0xfd, 0xcf, 0xbb, 0xe8, 0xf6, 0x7a, 0x06, 0x2f, 0x25,
- 0xc1, 0xb7, 0xad, 0x62, 0x26, 0xa6, 0x05, 0xdf, 0x73, 0xe7, 0x48, 0xc2, 0xba, 0xc0, 0x4d, 0x2b,
- 0x8a, 0xc4, 0x6e, 0x3b, 0x84, 0x96, 0x37, 0xca, 0x88, 0x69, 0x0b, 0x08, 0x11, 0xae, 0x36, 0xa1,
- 0xd5, 0xe5, 0x5b, 0x90, 0x20, 0x17, 0x71, 0xcf, 0xf4, 0x7a, 0x07, 0x58, 0x3e, 0x97, 0xe9, 0xb8,
- 0x1d, 0x78, 0x96, 0xa1, 0xb7, 0x6e, 0xa2, 0x13, 0x16, 0x7c, 0xaf, 0x48, 0x82, 0x8b, 0x43, 0x40,
- 0xb5, 0x17, 0xf2, 0xe4, 0xd6, 0x79, 0x32, 0xdf, 0x0d, 0xd2, 0x4a, 0x9d, 0x03, 0xdc, 0x1d, 0x07,
- 0x48, 0x20, 0xf2, 0x7e, 0xf8, 0x1a, 0xdb, 0x88, 0xf5, 0x07, 0x5e, 0x8d, 0xf2, 0xa5, 0x97, 0xad,
- 0x48, 0x67, 0xcf, 0x53, 0xe8, 0x2b, 0xc2, 0x21, 0x9b, 0x49, 0x0e, 0x9b, 0xcd, 0x8d, 0x4a, 0x85,
- 0xe0, 0x5e, 0x96, 0x7d, 0x76, 0xc8, 0xad, 0x67, 0xe2, 0x10, 0x0c, 0x96, 0x71, 0x2f, 0xca, 0x26,
- 0xc8, 0x67, 0xd2, 0xd5, 0x7e, 0xbe, 0xe5, 0xd0, 0xd0, 0xf2, 0x85, 0x1b, 0x32, 0xca, 0xa6, 0x45,
- 0x71, 0x4d, 0x40, 0xb3, 0xfd, 0xe8, 0xdf, 0x9d, 0xdf, 0xba, 0x84, 0x69, 0x21, 0x3a, 0xb3, 0xed,
- 0x58, 0xf0, 0x84, 0xbc, 0x68, 0x42, 0xcc, 0xa8, 0x49, 0xb7, 0x73, 0x34, 0x59, 0xf6, 0x65, 0xdc,
- 0x0a, 0x77, 0xe4, 0xa9, 0xf7, 0x44, 0xd0, 0xbb, 0x09, 0xea, 0x59, 0xf8, 0xf6, 0x45, 0xb7, 0x0e,
- 0x71, 0x3a, 0x0e, 0xc6, 0x84, 0xfc, 0x0e, 0x4d, 0x3a, 0xb0, 0x7c, 0xa8, 0x5d, 0x78, 0x85, 0xc2,
- 0xf2, 0xb2, 0xec, 0x4a, 0xc7, 0xf4, 0xf0, 0x6a, 0x7b, 0x68, 0x9c, 0xd1, 0xbf, 0x0a, 0x12, 0xb8,
- 0x7f, 0x7b, 0x99, 0x38, 0x04, 0xb0, 0x3a, 0xa3, 0xb5, 0xde, 0xe0, 0x9d, 0xd3, 0x10, 0x39, 0xb9,
- 0x49, 0x5b, 0x8c, 0x5c, 0x5d, 0xcf, 0x08, 0xfe, 0x15, 0xad, 0x2d, 0xdb, 0x02, 0x7c, 0xad, 0xab,
- 0x20, 0x9d, 0x71, 0xfe, 0xbe, 0x5b, 0x21, 0x1e, 0x3a, 0x22, 0x02, 0xa4, 0x84, 0x33, 0x7d, 0xa4,
- 0x46, 0xb7, 0xf8, 0x53, 0x41, 0xc6, 0x79, 0xa7, 0xb5, 0x33, 0xde, 0xea, 0xce, 0xec, 0x2f, 0x89,
- 0xcb, 0xe6, 0x9c, 0x9e, 0x5a, 0x13, 0x4a, 0xef, 0x50, 0x36, 0x04, 0x65, 0x0f, 0x86, 0x4f, 0x73,
- 0x27, 0xed, 0x37, 0x9d, 0xf3, 0x96, 0x16, 0x1b, 0xe1, 0x87, 0xde, 0xd8, 0xf5, 0xd1, 0x8a, 0x68,
- 0x7d, 0xd4, 0x49, 0xed, 0xbe, 0x8a, 0x68, 0xad, 0xab, 0x2a, 0x67, 0xbf, 0x93, 0x5c, 0x83, 0xa9,
- 0x1c, 0xb8, 0xd4, 0x6b, 0x7f, 0xd9, 0xdf, 0x1f, 0x10, 0xab, 0xa7, 0x31, 0xfe, 0x2f, 0x75, 0xd7,
- 0x1b, 0xd3, 0xd6, 0xb9, 0xde, 0xf7, 0x21, 0xd2, 0xfc, 0x21, 0x52, 0x7d, 0x75, 0xd9, 0x7a, 0xba,
- 0x10, 0x6e, 0x33, 0xa5, 0x51, 0xb8, 0x82, 0x28, 0x08, 0x37, 0x17, 0x6e, 0x80, 0x0a, 0x22, 0x2a,
- 0x85, 0x96, 0xae, 0xd0, 0x90, 0xc5, 0x21, 0x36, 0x62, 0x5e, 0x5a, 0xa5, 0x16, 0xb7, 0xca, 0xb8,
- 0xb4, 0x23, 0x80, 0x2d, 0x51, 0x2f, 0xd1, 0x45, 0x2e, 0x59, 0x99, 0x21, 0x0a, 0x35, 0xb6, 0x84,
- 0xe6, 0x20, 0xa5, 0x72, 0xd8, 0x98, 0x6c, 0x26, 0xdf, 0xfa, 0xf8, 0x03, 0xba, 0xf6, 0x87, 0x48,
- 0xc7, 0x9b, 0x90, 0xec, 0xde, 0x90, 0x1c, 0x7f, 0x40, 0xca, 0x99, 0x94, 0x49, 0xe7, 0x4e, 0x54,
- 0x73, 0x54, 0x27, 0x61, 0xef, 0xef, 0x7d, 0x7d, 0x7c, 0xce, 0xf1, 0x1f, 0x02, 0xac, 0xba, 0x52,
- 0x79, 0xd4, 0x2a, 0xc1, 0xc4, 0x1c, 0xbf, 0xcf, 0xfb, 0xfc, 0xff, 0x3d, 0xcf, 0x43, 0x22, 0x84,
- 0xf9, 0x3c, 0x9e, 0x34, 0x27, 0x9e, 0x2d, 0xb2, 0x96, 0xad, 0x49, 0x67, 0x8c, 0x58, 0x4b, 0xf0,
- 0x92, 0x48, 0xa5, 0x73, 0xd9, 0x9f, 0x34, 0xf3, 0x8c, 0x2b, 0x98, 0xe4, 0x80, 0x5c, 0xab, 0x62,
- 0xdf, 0x26, 0x8d, 0x38, 0x7b, 0x50, 0x93, 0xc6, 0x7b, 0x59, 0x34, 0x2a, 0x5e, 0x8e, 0x96, 0x4b,
- 0x5c, 0x9c, 0x69, 0x62, 0xad, 0x8e, 0x7b, 0x72, 0x31, 0x92, 0x52, 0xf9, 0xcd, 0x7a, 0x54, 0xb4,
- 0x3c, 0xd3, 0xf2, 0xd1, 0x22, 0x4f, 0x94, 0x54, 0x60, 0x26, 0x76, 0xcc, 0xa7, 0x5f, 0x6f, 0xb0,
- 0x14, 0xb4, 0x73, 0xb5, 0x74, 0xd2, 0xb5, 0xff, 0x7a, 0x18, 0xb4, 0xca, 0x86, 0xc0, 0xb8, 0xd9,
- 0xc6, 0xb8, 0x79, 0x8a, 0x71, 0x53, 0x3c, 0x95, 0x5e, 0xc0, 0x56, 0xea, 0x16, 0xa9, 0x2f, 0x98,
- 0x1c, 0xeb, 0xb6, 0xdf, 0x1b, 0x46, 0xad, 0x02, 0xbf, 0xaf, 0xc7, 0xdd, 0x59, 0xd8, 0xdf, 0xb2,
- 0x57, 0x5e, 0x6e, 0x16, 0x32, 0xb1, 0x5c, 0x7c, 0xe7, 0xfe, 0x53, 0x96, 0x3f, 0xa6, 0x9a, 0xa7,
- 0x44, 0x52, 0x26, 0x8d, 0x2b, 0x6e, 0x5f, 0xda, 0xb1, 0x8a, 0xcc, 0x3a, 0x95, 0xca, 0x9b, 0x8e,
- 0x55, 0x5f, 0xc6, 0xb4, 0xc0, 0x38, 0x80, 0x18, 0x1e, 0xbe, 0x8a, 0x72, 0x57, 0xd8, 0x44, 0x3c,
- 0x44, 0x0e, 0x7d, 0xc1, 0x41, 0x8d, 0x97, 0x13, 0xa6, 0xf2, 0xa0, 0x9d, 0x1b, 0xd1, 0x59, 0xcb,
- 0x74, 0xb1, 0x7e, 0x93, 0xcc, 0x8a, 0xe7, 0xa4, 0x4b, 0x95, 0x14, 0x20, 0x35, 0xf4, 0xb2, 0xc7,
- 0xf8, 0x30, 0x91, 0x1d, 0x15, 0xaa, 0x02, 0xd3, 0xc3, 0xc5, 0xbb, 0xdf, 0x8a, 0xe3, 0xe2, 0x62,
- 0x52, 0xa2, 0x54, 0x9e, 0xe8, 0xd6, 0x83, 0xb6, 0xdd, 0xf5, 0x57, 0x6f, 0x12, 0xcf, 0x0e, 0x19,
- 0xc6, 0x62, 0xf9, 0x6d, 0x37, 0x74, 0xdb, 0x5a, 0x49, 0x14, 0xed, 0x58, 0x66, 0x3e, 0x21, 0xe3,
- 0xa6, 0x78, 0xaa, 0x66, 0xc0, 0xb9, 0x8a, 0xaa, 0xfa, 0x55, 0xb7, 0xd1, 0x35, 0x12, 0x44, 0x1e,
- 0x71, 0xc5, 0x83, 0x0d, 0x55, 0x7c, 0x36, 0x1c, 0x82, 0x37, 0xbd, 0x77, 0x4e, 0xea, 0xad, 0xa5,
- 0xf6, 0x5c, 0x4b, 0x09, 0x1d, 0x67, 0xf4, 0x33, 0xe6, 0xfd, 0x3a, 0x6c, 0xc6, 0xd6, 0x9e, 0xf9,
- 0x5c, 0x20, 0x86, 0x27, 0x06, 0x2f, 0x3f, 0x81, 0xdf, 0xe3, 0x23, 0x91, 0xe5, 0x90, 0x5d, 0xe1,
- 0x34, 0xe6, 0x33, 0x8d, 0x0a, 0x4a, 0x5e, 0x0d, 0x93, 0xad, 0x70, 0x5a, 0xc8, 0x6c, 0xab, 0xef,
- 0x71, 0xbc, 0x63, 0x43, 0x24, 0x51, 0x9e, 0xae, 0x8a, 0x3c, 0xd5, 0x4b, 0x33, 0x02, 0x92, 0x8a,
- 0x99, 0xc2, 0x93, 0xf4, 0x05, 0xd5, 0x7b, 0x34, 0x58, 0x76, 0x8e, 0xd7, 0x05, 0x61, 0xcb, 0x8b,
- 0xb8, 0x7c, 0x8d, 0xeb, 0xac, 0xad, 0xd6, 0xd5, 0xb9, 0x98, 0x75, 0xd8, 0xe9, 0x93, 0x2e, 0x1a,
- 0xa7, 0x87, 0xfb, 0x82, 0x55, 0x81, 0xe4, 0xd8, 0xee, 0x50, 0x23, 0x93, 0x24, 0xf6, 0xd9, 0xf2,
- 0x8e, 0x0a, 0x39, 0x71, 0x24, 0xa8, 0x7d, 0xce, 0xc2, 0xf3, 0x0d, 0x5b, 0xd2, 0xfe, 0x84, 0x53,
- 0xcb, 0xcd, 0xb6, 0xb7, 0x9c, 0xb1, 0x74, 0x26, 0x3b, 0x17, 0x44, 0xec, 0x3b, 0x64, 0x07, 0x2a,
- 0x81, 0x8b, 0x23, 0xb7, 0xcf, 0x93, 0xfb, 0x87, 0xfb, 0xb3, 0x1f, 0x5e, 0x22, 0x13, 0xfb, 0x9b,
- 0x5e, 0x99, 0xc4, 0x96, 0x91, 0xd4, 0xce, 0x1d, 0x18, 0x83, 0x06, 0x58, 0x3c, 0xc5, 0x1b, 0xc0,
- 0x36, 0x34, 0xed, 0xab, 0xc7, 0x3b, 0xae, 0xc5, 0x89, 0xe7, 0x03, 0x9f, 0xed, 0x13, 0xea, 0xf7,
- 0x2c, 0xf9, 0x93, 0x91, 0xc2, 0x26, 0x1f, 0x96, 0x27, 0x52, 0x23, 0x71, 0x36, 0x0b, 0x98, 0x65,
- 0xcb, 0xd5, 0x1b, 0x4c, 0xb3, 0x72, 0xe4, 0x9d, 0x57, 0xbc, 0x88, 0x4b, 0x18, 0x8d, 0x84, 0x60,
- 0x57, 0xb9, 0xb8, 0xf6, 0x54, 0xb1, 0x03, 0x51, 0xfd, 0xdb, 0xf5, 0x86, 0xdc, 0xe3, 0x62, 0xbf,
- 0x06, 0x73, 0xb7, 0x36, 0xf3, 0x95, 0x1d, 0x64, 0xf5, 0xf4, 0xaf, 0xee, 0xb4, 0x61, 0x91, 0x3d,
- 0x09, 0x22, 0xee, 0x4d, 0x6e, 0x77, 0x55, 0x4d, 0xc2, 0x79, 0xfb, 0xbc, 0xc0, 0xcb, 0x19, 0x19,
- 0x37, 0xdc, 0x54, 0x26, 0x9a, 0x5e, 0xe3, 0x1a, 0x5c, 0x0e, 0xc2, 0x4d, 0xc7, 0x12, 0xf5, 0xf1,
- 0xcf, 0x23, 0x53, 0xed, 0xf4, 0x67, 0x24, 0x9f, 0x3c, 0xe3, 0x81, 0x66, 0x3d, 0x48, 0x64, 0x24,
- 0x39, 0x36, 0x17, 0xca, 0x46, 0x81, 0xaf, 0xc8, 0x89, 0xf2, 0xd8, 0x81, 0x23, 0xfb, 0xe1, 0x25,
- 0x8b, 0x2d, 0xdf, 0x27, 0xb1, 0xe5, 0x03, 0xb1, 0xb8, 0xb2, 0x50, 0xfc, 0x09, 0xa5, 0x66, 0x35,
- 0x76, 0x9e, 0x90, 0xb5, 0xdb, 0x43, 0x09, 0x1f, 0xfa, 0x2d, 0xcc, 0xff, 0x46, 0x35, 0x9a, 0x68,
- 0x58, 0xa2, 0x41, 0xd2, 0xa6, 0x05, 0xe5, 0x8e, 0xde, 0xa5, 0xd2, 0xb5, 0x52, 0x88, 0xdf, 0xae,
- 0x74, 0xb1, 0xc9, 0x39, 0x88, 0x02, 0xd5, 0x33, 0xe9, 0x71, 0x23, 0x7b, 0xd0, 0x22, 0xa1, 0x0e,
- 0x38, 0x4a, 0xfe, 0x8b, 0xa4, 0x36, 0xc4, 0x16, 0x69, 0x81, 0x6e, 0xba, 0xd3, 0xda, 0xac, 0x41,
- 0x0d, 0x1e, 0x8e, 0x6d, 0xac, 0x29, 0xd6, 0xa1, 0x7c, 0x56, 0xb9, 0x35, 0x83, 0x86, 0xb9, 0x90,
- 0xde, 0x92, 0xfa, 0xb2, 0x27, 0xdd, 0xfb, 0xf1, 0x64, 0xca, 0xd3, 0xa4, 0x11, 0xf9, 0x57, 0xe4,
- 0xaf, 0x08, 0x91, 0xd3, 0x49, 0x47, 0x4b, 0xb1, 0x52, 0xed, 0x86, 0x03, 0xaf, 0x11, 0x0b, 0x94,
- 0x21, 0x9e, 0x61, 0x9e, 0x9b, 0x44, 0xc3, 0x2e, 0x65, 0x64, 0x74, 0xcd, 0x63, 0x56, 0x11, 0x2a,
- 0x6e, 0xf0, 0x9c, 0x47, 0x85, 0xe4, 0x18, 0xb6, 0xc7, 0xaf, 0x53, 0x14, 0xd9, 0x5e, 0xbf, 0xd8,
- 0xec, 0x8f, 0x83, 0xb6, 0x19, 0x0f, 0x6a, 0x85, 0x2f, 0xb3, 0x0c, 0xf0, 0xcb, 0x2c, 0x12, 0x8b,
- 0xb7, 0x72, 0xa2, 0xf6, 0xd6, 0x12, 0x3e, 0xb8, 0x50, 0x21, 0xb1, 0xc2, 0xf3, 0x21, 0x1a, 0x76,
- 0x80, 0x44, 0x96, 0xbe, 0xcc, 0x54, 0xe1, 0x6e, 0xc0, 0x3a, 0xf2, 0x9a, 0x2c, 0xd1, 0x93, 0x7c,
- 0x8e, 0x75, 0x2e, 0xa4, 0xbe, 0x07, 0xf5, 0x1e, 0xe5, 0x58, 0xc6, 0x97, 0x36, 0xc7, 0x51, 0x43,
- 0xc4, 0x94, 0xd8, 0xdb, 0x29, 0xcc, 0x09, 0x28, 0xce, 0x2f, 0x69, 0x9f, 0x48, 0xc9, 0x26, 0xea,
- 0x79, 0xb9, 0x21, 0x2a, 0xd2, 0x61, 0xe8, 0x88, 0x88, 0x7a, 0x5e, 0x8e, 0x0a, 0x3f, 0xd4, 0x24,
- 0x03, 0x74, 0xdf, 0x66, 0x43, 0xb1, 0x8c, 0x1f, 0x59, 0x65, 0xa0, 0xa1, 0x25, 0x3e, 0x5b, 0xb5,
- 0xa0, 0x9e, 0x22, 0x30, 0x98, 0x4a, 0x45, 0xfb, 0xc0, 0x6b, 0x5b, 0x1e, 0x07, 0xe1, 0xe6, 0xc0,
- 0x12, 0xad, 0xd5, 0x5b, 0x07, 0x6e, 0xc4, 0x32, 0x7c, 0x76, 0xc5, 0xb3, 0xee, 0x85, 0x5c, 0x5a,
- 0x64, 0xa3, 0x0b, 0x55, 0xd3, 0xab, 0x6e, 0xec, 0x2f, 0xdf, 0x9f, 0xf7, 0x03, 0xcf, 0xc7, 0xd0,
- 0x81, 0xee, 0x25, 0xb3, 0xb0, 0x9b, 0x49, 0x55, 0xc0, 0x7b, 0x33, 0x1f, 0xaf, 0x4f, 0xf7, 0xd3,
- 0x47, 0x8f, 0xcc, 0x05, 0x88, 0xb7, 0xb6, 0x4c, 0x79, 0xf9, 0x59, 0xdb, 0x4d, 0xf8, 0xb0, 0xb9,
- 0xc2, 0xdd, 0x58, 0x34, 0xc2, 0x62, 0x1d, 0x92, 0x94, 0x8c, 0x03, 0x62, 0x0f, 0xe6, 0x9d, 0x68,
- 0x63, 0xa0, 0x3b, 0x0d, 0x2d, 0x19, 0x9a, 0x6d, 0x4f, 0x3c, 0xe3, 0xcf, 0x05, 0x4d, 0x81, 0xbe,
- 0x60, 0x38, 0x84, 0xfd, 0xdb, 0x44, 0x4e, 0xc5, 0xd2, 0xba, 0xb2, 0x72, 0x9a, 0xe5, 0x66, 0xf7,
- 0x42, 0x27, 0x33, 0x39, 0x56, 0x32, 0x08, 0x5a, 0x89, 0xed, 0xd9, 0x51, 0x2a, 0x95, 0xfc, 0xcb,
- 0x6e, 0xce, 0x62, 0x8a, 0xc4, 0x8f, 0xac, 0xd6, 0xe3, 0x8c, 0xf9, 0x13, 0xb1, 0x74, 0x4c, 0xaa,
- 0xce, 0x28, 0xf9, 0xff, 0x45, 0x63, 0xa2, 0x61, 0xaa, 0xb7, 0xdb, 0x56, 0x4f, 0xf7, 0xd2, 0xb2,
- 0x33, 0xea, 0x0b, 0x50, 0xd9, 0xa4, 0xc8, 0x8b, 0xb7, 0x3e, 0xf3, 0xc7, 0xb6, 0xb3, 0x5c, 0x1c,
- 0x1d, 0xbc, 0x88, 0xcf, 0xc2, 0xa1, 0x15, 0x0f, 0xfe, 0x0c, 0x7b, 0xd9, 0x6d, 0x5f, 0xdc, 0x87,
- 0xbd, 0x84, 0xe7, 0x03, 0xc4, 0xd6, 0x39, 0x62, 0x2d, 0xf5, 0xf6, 0x0f, 0xf6, 0x7c, 0xc8, 0x3e,
- 0x64, 0x2f, 0x8e, 0x52, 0x88, 0x8f, 0x43, 0x75, 0xd6, 0x90, 0x0e, 0x19, 0x95, 0x68, 0x20, 0x9e,
- 0x77, 0x92, 0x6a, 0x90, 0xcf, 0x88, 0xdf, 0x43, 0xab, 0x23, 0x2b, 0x85, 0x89, 0x74, 0x2c, 0x4f,
- 0x6a, 0x16, 0x94, 0x28, 0x62, 0xd2, 0xc8, 0x32, 0xf6, 0x99, 0x6d, 0x55, 0x4f, 0x43, 0xc2, 0xd0,
- 0x8d, 0x43, 0xee, 0x78, 0xc2, 0xba, 0x9a, 0x26, 0x9e, 0xc7, 0xb9, 0xe0, 0x1c, 0xe3, 0xa5, 0x9c,
- 0xad, 0x58, 0x6d, 0x6a, 0x37, 0x94, 0xdf, 0x1a, 0x7e, 0x2e, 0xbf, 0x3d, 0x68, 0x93, 0x1b, 0x09,
- 0xea, 0xa5, 0xb2, 0x5a, 0xaa, 0x2c, 0x95, 0xa8, 0x8a, 0xd4, 0xd9, 0x92, 0x63, 0x43, 0x76, 0xa9,
- 0xf9, 0x65, 0xb6, 0x72, 0xd1, 0xd8, 0x6d, 0x8b, 0x08, 0x31, 0x70, 0x72, 0xd9, 0xb9, 0xec, 0x58,
- 0xf6, 0xc7, 0xfc, 0x69, 0x5e, 0x62, 0x51, 0x2b, 0xe6, 0x5c, 0x5e, 0x75, 0x5d, 0x8b, 0xfb, 0xa0,
- 0x75, 0x65, 0x9f, 0xbc, 0xe5, 0x65, 0x5a, 0x82, 0xe6, 0xf5, 0x32, 0x2c, 0x13, 0xf4, 0xb3, 0x4f,
- 0x06, 0x6e, 0x11, 0x1d, 0x24, 0x9b, 0x02, 0x46, 0xd7, 0x96, 0x97, 0x61, 0xc7, 0xb7, 0xbc, 0x24,
- 0x7e, 0x92, 0xfb, 0x82, 0xfb, 0x89, 0x30, 0x95, 0x0d, 0xeb, 0xaf, 0xb8, 0xa0, 0xb5, 0xf5, 0x73,
- 0x37, 0xe0, 0xe7, 0x23, 0x77, 0x82, 0xcd, 0xd7, 0x7a, 0x09, 0x64, 0xd1, 0x84, 0xf6, 0x74, 0xa1,
- 0x7b, 0x95, 0x1b, 0x07, 0x94, 0x96, 0x75, 0x89, 0x68, 0x58, 0x49, 0xad, 0x6c, 0xb2, 0x4c, 0x7c,
- 0x38, 0xaa, 0x44, 0x3c, 0x9b, 0x1c, 0x8b, 0x2e, 0x27, 0x64, 0x6d, 0x5d, 0x6a, 0xc6, 0xc3, 0x3a,
- 0xab, 0xfc, 0x49, 0x67, 0xe2, 0x70, 0x2c, 0x1d, 0x0a, 0x87, 0x50, 0x4d, 0xcd, 0x89, 0xc8, 0xe8,
- 0x55, 0x46, 0x6b, 0xf4, 0x95, 0xe0, 0x96, 0xf1, 0xa5, 0xe4, 0x24, 0xf4, 0xbb, 0xa8, 0xf1, 0xa7,
- 0xca, 0xbb, 0xf8, 0x80, 0xa6, 0x0b, 0x47, 0x61, 0x9f, 0x1d, 0x32, 0x17, 0xdf, 0x39, 0xd2, 0x5e,
- 0x34, 0xca, 0x63, 0xb9, 0x14, 0xb9, 0x79, 0x49, 0xc7, 0xea, 0xc0, 0x92, 0xd5, 0x4f, 0xf4, 0x50,
- 0x2c, 0x96, 0xb1, 0x64, 0x3e, 0xee, 0x7a, 0x9d, 0x4e, 0xa3, 0xe4, 0xc2, 0x3c, 0x3e, 0x49, 0x9a,
- 0xc8, 0x2a, 0xd1, 0x35, 0x16, 0x49, 0xb9, 0xf9, 0x89, 0x06, 0x33, 0x9f, 0x8f, 0x36, 0x9d, 0x6f,
- 0x39, 0xfd, 0xab, 0xf0, 0x7f, 0xb8, 0x78, 0x55, 0xa0, 0x2a, 0x60, 0x0a, 0x64, 0xa3, 0x13, 0x72,
- 0x4c, 0x6e, 0x8a, 0x0f, 0xd9, 0x3b, 0x6b, 0xf7, 0x1e, 0x93, 0xa8, 0xf8, 0xe6, 0x6c, 0x74, 0x3e,
- 0xa5, 0x3f, 0x2f, 0x96, 0x05, 0xdd, 0x2e, 0x41, 0x40, 0x31, 0x0f, 0x34, 0x27, 0x6a, 0x7f, 0x7a,
- 0xd2, 0x68, 0x1c, 0x8f, 0x65, 0x1c, 0x31, 0xc6, 0x4b, 0x48, 0xa5, 0x9f, 0xd8, 0x3c, 0xc5, 0x5b,
- 0x59, 0xe3, 0x58, 0xdd, 0x5a, 0xcd, 0xf8, 0x11, 0x8d, 0x4c, 0x65, 0x9b, 0x8b, 0x6b, 0x65, 0xc2,
- 0x2c, 0x10, 0x3b, 0x4c, 0xab, 0x60, 0xb0, 0x99, 0xd5, 0xe9, 0x88, 0x58, 0x2d, 0x5d, 0x22, 0x71,
- 0xfe, 0x04, 0xb1, 0x25, 0x95, 0xb5, 0x1e, 0xf4, 0x53, 0xa9, 0x5c, 0x4e, 0xd3, 0x98, 0x03, 0x33,
- 0xfa, 0xb5, 0xaf, 0x42, 0xc3, 0x56, 0x9a, 0x14, 0x33, 0x49, 0xe2, 0x10, 0x44, 0x15, 0x39, 0xf2,
- 0x5b, 0x7d, 0x32, 0xf1, 0x8f, 0x76, 0xf8, 0x9d, 0x24, 0x96, 0xf6, 0x58, 0x88, 0xcc, 0x11, 0x1d,
- 0x12, 0x73, 0x12, 0x4e, 0x5a, 0xfd, 0xe4, 0x13, 0x27, 0x63, 0x12, 0xb0, 0xa8, 0x9b, 0x9c, 0x71,
- 0x3c, 0x97, 0xe2, 0x71, 0x23, 0x63, 0xce, 0x55, 0x67, 0xcc, 0x97, 0x20, 0x76, 0x51, 0xee, 0xcb,
- 0x7f, 0x76, 0xec, 0xc5, 0x85, 0xbf, 0x4f, 0xe2, 0x70, 0xc2, 0xcd, 0x81, 0x9b, 0xfe, 0x58, 0x46,
- 0xda, 0xce, 0xf2, 0xb2, 0x85, 0xfc, 0x4e, 0xf2, 0xe9, 0x25, 0xe7, 0xea, 0xba, 0xe7, 0xf8, 0xbe,
- 0xe6, 0xeb, 0x33, 0xcf, 0xa7, 0xce, 0xb6, 0xe2, 0x6d, 0x12, 0x4c, 0x01, 0xad, 0xe7, 0x83, 0xf8,
- 0x80, 0x49, 0x8e, 0x3e, 0xa6, 0xa6, 0x12, 0x48, 0x64, 0x4c, 0xff, 0xd3, 0x6b, 0x1c, 0xad, 0x09,
- 0xe0, 0xb6, 0xdd, 0x20, 0x52, 0xe9, 0xc7, 0x1d, 0x35, 0x8e, 0xab, 0x15, 0x11, 0x44, 0xa5, 0x0b,
- 0x59, 0xb5, 0x27, 0xe0, 0x72, 0x03, 0xe3, 0xae, 0xb6, 0xe3, 0x63, 0x93, 0xe3, 0xa9, 0x7f, 0x7c,
- 0xd2, 0x75, 0xa7, 0xe1, 0x7a, 0xed, 0xf5, 0xda, 0x0f, 0x6b, 0x2f, 0xd7, 0x32, 0xdb, 0xac, 0xdf,
- 0xd0, 0x85, 0xee, 0x15, 0xed, 0x29, 0x0f, 0xd9, 0xf9, 0x12, 0x0c, 0x4f, 0x66, 0x1b, 0x1b, 0x18,
- 0x14, 0x1d, 0xa2, 0xfd, 0x1a, 0x09, 0x95, 0xf7, 0xef, 0x88, 0x37, 0xea, 0xd9, 0x10, 0x81, 0x0c,
- 0x43, 0xf6, 0xab, 0x8d, 0xe8, 0xbe, 0x86, 0x0a, 0xbc, 0x84, 0x87, 0x81, 0x28, 0x90, 0xd9, 0x03,
- 0x27, 0x95, 0x4a, 0xeb, 0x92, 0x23, 0x16, 0x4b, 0x6f, 0x08, 0x47, 0x8f, 0x1c, 0x3d, 0xb2, 0xe5,
- 0x75, 0x48, 0x4c, 0x5e, 0xad, 0xf4, 0x15, 0x27, 0xe5, 0x72, 0x36, 0xaa, 0xdc, 0x6c, 0x9c, 0x20,
- 0xec, 0x91, 0x63, 0x79, 0x80, 0xf8, 0x16, 0x6f, 0xdd, 0x70, 0x2e, 0xf9, 0x57, 0x15, 0x72, 0xfa,
- 0x7f, 0xf6, 0xd1, 0x1f, 0xec, 0xfb, 0xe9, 0x9d, 0xd6, 0xe3, 0x9b, 0xa7, 0x87, 0xf5, 0x7e, 0x29,
- 0xd3, 0x82, 0xea, 0x33, 0x14, 0x24, 0xd0, 0xc5, 0xac, 0xa5, 0xf6, 0x93, 0x1e, 0x3d, 0x62, 0xc9,
- 0xe0, 0xe9, 0xac, 0x37, 0x09, 0x2f, 0x6f, 0x5a, 0x89, 0xdf, 0xd3, 0x92, 0x36, 0xfc, 0x52, 0xf9,
- 0x89, 0x7b, 0xc3, 0x39, 0x12, 0x59, 0xcc, 0xa7, 0x54, 0x64, 0x42, 0xa2, 0x99, 0xe5, 0x55, 0xb4,
- 0x31, 0xd0, 0xfd, 0x8b, 0x2c, 0xde, 0x54, 0xbd, 0x9c, 0x76, 0xc3, 0x55, 0x9a, 0xd9, 0xd7, 0xfa,
- 0x9d, 0xb8, 0x63, 0xc9, 0x31, 0x6d, 0x36, 0x6f, 0xaa, 0xb7, 0x14, 0x8f, 0x55, 0x2d, 0xc1, 0x0e,
- 0xa3, 0x3b, 0x40, 0x8f, 0x0a, 0xf1, 0x65, 0xaf, 0x74, 0x95, 0x72, 0x08, 0xb8, 0xf9, 0x91, 0x60,
- 0xee, 0x31, 0x30, 0x15, 0x40, 0xa9, 0xad, 0x86, 0x9e, 0xa7, 0xac, 0x52, 0xa5, 0x0e, 0x06, 0x4c,
- 0x7c, 0xa6, 0x75, 0xb4, 0x2c, 0xe4, 0x92, 0xd8, 0x3e, 0xa6, 0x61, 0x13, 0x8e, 0x4c, 0x37, 0xe1,
- 0x02, 0xb9, 0xa3, 0xa8, 0xc9, 0x66, 0xfc, 0xf8, 0x3e, 0x39, 0x0d, 0xeb, 0x4d, 0xc7, 0x12, 0x91,
- 0x4c, 0xc2, 0x4b, 0x35, 0xea, 0x44, 0x5e, 0xef, 0xb7, 0x71, 0x1f, 0xc3, 0xb8, 0x21, 0xdf, 0x39,
- 0xc0, 0xb0, 0xdf, 0xc0, 0x89, 0x8b, 0x27, 0x92, 0xfb, 0x9a, 0x1a, 0xc3, 0xf2, 0x04, 0x77, 0x29,
- 0x62, 0x2b, 0x22, 0xea, 0xf3, 0x15, 0x9b, 0xdc, 0x28, 0xcd, 0xba, 0xea, 0x71, 0x03, 0xf8, 0x3e,
- 0x90, 0x51, 0x0b, 0x59, 0x83, 0xee, 0xa7, 0xaf, 0x74, 0x91, 0x9b, 0x98, 0xc8, 0x3f, 0xfd, 0x2d,
- 0xe7, 0x2a, 0xea, 0xcf, 0x6a, 0x36, 0x10, 0x33, 0x7f, 0x30, 0x07, 0x4e, 0xbd, 0x15, 0xc7, 0x3b,
- 0x70, 0xfe, 0xd5, 0x92, 0x36, 0x63, 0xc8, 0x10, 0x1f, 0x4d, 0x71, 0x15, 0x71, 0xb5, 0x68, 0x64,
- 0x9a, 0x38, 0x1c, 0x52, 0x6f, 0x19, 0xbc, 0x26, 0x3d, 0x8a, 0xec, 0x4e, 0xc3, 0x44, 0x09, 0xa6,
- 0xd6, 0x2c, 0xc0, 0x9a, 0x43, 0xc3, 0xea, 0xfd, 0x9e, 0xb9, 0x32, 0xf9, 0x74, 0xa0, 0x79, 0xc2,
- 0xa1, 0x6a, 0x09, 0x3d, 0x04, 0x57, 0xdd, 0xf2, 0x98, 0xfc, 0xf9, 0x5f, 0x07, 0x1e, 0x09, 0x87,
- 0xd3, 0xbf, 0x2a, 0x83, 0x7a, 0x47, 0x5d, 0x81, 0x8b, 0xb3, 0x8a, 0x68, 0x8b, 0xb4, 0x91, 0xa2,
- 0xf1, 0xff, 0xf2, 0xc0, 0x12, 0x78, 0x79, 0x8d, 0xbf, 0x37, 0xcc, 0xf2, 0x9b, 0x0a, 0x2f, 0xdb,
- 0xe8, 0xcd, 0x1e, 0x20, 0xbe, 0x03, 0x2f, 0x8d, 0x04, 0xf4, 0x08, 0xa2, 0x21, 0x7b, 0x75, 0xb2,
- 0x10, 0x9f, 0x28, 0x79, 0x3d, 0x5a, 0xab, 0x5e, 0xde, 0x57, 0xc7, 0x89, 0x82, 0xf2, 0x99, 0xf1,
- 0xbc, 0x1a, 0xe7, 0xe2, 0x7a, 0x5d, 0x7a, 0xbd, 0x01, 0x9a, 0x4b, 0xdc, 0x3e, 0x58, 0xb4, 0xe7,
- 0x95, 0x65, 0x2a, 0x8b, 0x37, 0x33, 0x23, 0xb6, 0x64, 0x37, 0x91, 0x10, 0xb9, 0x87, 0xbe, 0xcc,
- 0xf2, 0x0e, 0x39, 0x32, 0x78, 0xac, 0xdb, 0x94, 0x47, 0x2a, 0x4f, 0xda, 0x0d, 0xac, 0x62, 0x65,
- 0xd2, 0xec, 0xc8, 0xc3, 0xc6, 0x34, 0x44, 0xf6, 0x3d, 0x1a, 0xef, 0x0b, 0x5a, 0x73, 0x36, 0xa4,
- 0xbd, 0x03, 0x6b, 0x5c, 0x29, 0x2f, 0x59, 0x7e, 0x69, 0x93, 0x4b, 0x47, 0xb7, 0x0b, 0xbc, 0x2c,
- 0xbf, 0x1d, 0x7c, 0x90, 0xee, 0x75, 0xb7, 0xc8, 0x1b, 0x62, 0x3a, 0xba, 0xe2, 0x11, 0xc6, 0xea,
- 0xec, 0xdd, 0xf6, 0x5f, 0xcc, 0x46, 0xe3, 0x0f, 0x85, 0x52, 0xd4, 0x3b, 0x32, 0xf8, 0x4a, 0x5d,
- 0x6d, 0x2e, 0xd4, 0x6d, 0xbf, 0xdb, 0x3b, 0xb2, 0x60, 0x25, 0xbc, 0x74, 0x2c, 0x11, 0x2f, 0x36,
- 0xb1, 0x11, 0xb7, 0x64, 0x68, 0x9e, 0x1a, 0xbc, 0x24, 0x3a, 0x96, 0xc4, 0x67, 0xb7, 0x88, 0x8e,
- 0xba, 0xe5, 0x5c, 0xf6, 0x25, 0x2d, 0x19, 0x3d, 0x52, 0x08, 0x13, 0xc0, 0xe1, 0x03, 0x53, 0x8f,
- 0x96, 0x65, 0x82, 0x0a, 0x28, 0x92, 0xf7, 0x3e, 0xd8, 0x0f, 0xb6, 0x6b, 0x90, 0xc6, 0x96, 0xd3,
- 0xc3, 0x55, 0x81, 0x51, 0x41, 0xf1, 0x9a, 0x15, 0xaa, 0xb3, 0xb1, 0x1a, 0x81, 0xa1, 0x43, 0xff,
- 0x0c, 0x57, 0xba, 0xb0, 0x57, 0xa7, 0x18, 0x5f, 0xd9, 0xc4, 0xe3, 0xb9, 0x06, 0x0a, 0x5e, 0x40,
- 0x24, 0xbe, 0x13, 0xea, 0x63, 0x30, 0x1f, 0x5d, 0x6a, 0xf7, 0xc1, 0x74, 0xd2, 0xde, 0x00, 0x9e,
- 0xd8, 0x54, 0xf5, 0xb4, 0xef, 0x5f, 0xcc, 0x3d, 0x46, 0x95, 0x43, 0x8b, 0x1a, 0x4b, 0x34, 0xcf,
- 0xa7, 0xf4, 0xf7, 0xae, 0xdd, 0xc0, 0x30, 0x20, 0x5a, 0x6b, 0xb9, 0xee, 0x85, 0x67, 0x46, 0xb3,
- 0x54, 0xf9, 0xef, 0x30, 0x7b, 0x51, 0x1c, 0x8d, 0x60, 0xcf, 0xb0, 0x59, 0xf0, 0x65, 0x2d, 0x72,
- 0x44, 0x0c, 0x87, 0xbe, 0xf4, 0x0c, 0xd9, 0x9f, 0x5c, 0x3c, 0x68, 0xbb, 0x30, 0xbb, 0xc0, 0x7f,
- 0x15, 0xff, 0xba, 0x28, 0xa2, 0x45, 0x4c, 0xcc, 0x72, 0x55, 0x7c, 0x76, 0xcb, 0xcb, 0x6a, 0x60,
- 0xc9, 0xe1, 0xd6, 0x04, 0xfc, 0x58, 0x12, 0x93, 0x10, 0x7b, 0x19, 0x63, 0xc8, 0xa0, 0x6c, 0x4e,
- 0x34, 0x2d, 0x5c, 0x0b, 0x3b, 0x62, 0xcc, 0x5e, 0xc2, 0x0f, 0xdc, 0x48, 0xe9, 0x9f, 0xf8, 0x78,
- 0x47, 0x3a, 0xe4, 0x93, 0xa9, 0xbd, 0x55, 0xb8, 0xc9, 0x2a, 0xd5, 0xc7, 0xfe, 0xbe, 0xf5, 0xeb,
- 0x7d, 0x6c, 0x09, 0x57, 0xa6, 0x30, 0xd3, 0x4c, 0xac, 0x78, 0x6f, 0x58, 0xef, 0x13, 0x30, 0x0c,
- 0x54, 0x36, 0x5a, 0xec, 0xf9, 0x30, 0x6b, 0xa9, 0xcf, 0x4c, 0xaf, 0x71, 0x16, 0xf8, 0xdf, 0xe4,
- 0x53, 0x39, 0x96, 0xa1, 0x6d, 0x62, 0x99, 0xbe, 0xb2, 0x08, 0x1f, 0x85, 0x26, 0x8d, 0xe8, 0xcf,
- 0xe1, 0xb7, 0xef, 0x6b, 0x2a, 0xc9, 0x2c, 0x0f, 0xa4, 0xf5, 0x72, 0x80, 0x8c, 0x85, 0x26, 0x6e,
- 0x91, 0xb4, 0xd8, 0x01, 0x58, 0xc7, 0x48, 0x51, 0x27, 0x4f, 0xf1, 0x36, 0x91, 0x0c, 0xdd, 0xb3,
- 0x87, 0x67, 0x55, 0xa4, 0x92, 0x55, 0x21, 0xb5, 0xf7, 0x44, 0xf9, 0xad, 0x39, 0xe4, 0xf2, 0xb3,
- 0xc8, 0x81, 0x66, 0x89, 0x5c, 0xde, 0x1b, 0x3e, 0x48, 0x62, 0xfb, 0xd1, 0xd9, 0x28, 0x7f, 0x2d,
- 0xfe, 0xb1, 0x2e, 0x26, 0x19, 0x24, 0x4f, 0xc3, 0x66, 0x00, 0x41, 0x4f, 0xb0, 0x4f, 0xb7, 0xc6,
- 0x55, 0xcd, 0xc2, 0xea, 0x0d, 0xf8, 0x07, 0x28, 0xc7, 0x62, 0x12, 0xf2, 0xb1, 0x73, 0x24, 0x3a,
- 0x3c, 0xf0, 0xda, 0x8c, 0x9b, 0xbc, 0x82, 0xf3, 0x58, 0x65, 0xe7, 0xa1, 0xad, 0x0b, 0x60, 0x17,
- 0x2e, 0xf3, 0xf3, 0x78, 0x44, 0xd3, 0x1a, 0x6e, 0x4e, 0x9c, 0xf8, 0x9f, 0x77, 0x60, 0x2d, 0xf7,
- 0x8a, 0xeb, 0x52, 0x6a, 0xd0, 0x40, 0xf9, 0xc0, 0x2f, 0xd1, 0x23, 0xb6, 0xe6, 0x53, 0x13, 0x24,
- 0x6a, 0x9d, 0xf1, 0xe8, 0xe3, 0x14, 0x96, 0x65, 0xd1, 0xfa, 0x27, 0x20, 0x22, 0xab, 0x32, 0x8b,
- 0xf1, 0x7d, 0x09, 0x3c, 0xb9, 0x25, 0x73, 0xaf, 0x42, 0xc6, 0x8d, 0xd1, 0xa2, 0x11, 0xde, 0xa5,
- 0x76, 0x7f, 0x5a, 0xbb, 0x81, 0x45, 0xa0, 0x66, 0x41, 0xb5, 0x96, 0x9b, 0x1c, 0xbb, 0x4f, 0x5c,
- 0xbc, 0x5d, 0x63, 0x2d, 0x81, 0x4d, 0xb8, 0x24, 0xeb, 0xe3, 0x8a, 0xaa, 0xc0, 0xb6, 0x8e, 0x97,
- 0x13, 0x32, 0xf4, 0x63, 0xbb, 0x01, 0xbd, 0x79, 0x99, 0x82, 0x54, 0x62, 0x6a, 0x96, 0xf6, 0x13,
- 0xc2, 0x66, 0xb1, 0x3c, 0x22, 0x4f, 0x24, 0x89, 0x8b, 0xdf, 0xa6, 0x1d, 0x88, 0x5f, 0x0c, 0xff,
- 0xc7, 0xf0, 0xfc, 0x42, 0x94, 0x37, 0xf3, 0x67, 0x35, 0x59, 0x8c, 0x4d, 0x6e, 0xc5, 0xc3, 0x7e,
- 0xb6, 0x45, 0xba, 0x37, 0xcc, 0xfc, 0x68, 0x62, 0x29, 0xe0, 0x8f, 0x12, 0x1d, 0x6b, 0x2d, 0xf0,
- 0xb2, 0x35, 0xff, 0x6a, 0xbb, 0x61, 0x95, 0xf8, 0xf5, 0xbe, 0x44, 0x3e, 0x1b, 0x24, 0xab, 0xe7,
- 0x35, 0x69, 0xec, 0xb6, 0x33, 0x54, 0xbd, 0x98, 0xc5, 0xa9, 0x7f, 0xe7, 0xf1, 0x11, 0x6e, 0x22,
- 0xe7, 0xfe, 0xe2, 0xc3, 0x85, 0xb7, 0x3d, 0xe7, 0xa6, 0xba, 0xf6, 0xd3, 0xa1, 0xa0, 0xc5, 0xc4,
- 0xa6, 0xa3, 0x7a, 0x8c, 0x37, 0x36, 0x21, 0x81, 0x8a, 0x7b, 0x48, 0xd6, 0xb8, 0x05, 0x5a, 0xb3,
- 0xd0, 0xcb, 0x05, 0x45, 0x08, 0xc8, 0x85, 0xf9, 0x29, 0xd2, 0xa8, 0xb0, 0xf3, 0xb4, 0xcf, 0x35,
- 0x0e, 0x56, 0x67, 0x4e, 0x63, 0xf5, 0x16, 0xf3, 0x58, 0xb0, 0xb9, 0x90, 0xea, 0x69, 0xdd, 0x29,
- 0x1b, 0xb7, 0x30, 0x4c, 0xfa, 0x59, 0x9d, 0x37, 0x0a, 0x5d, 0xa1, 0xfd, 0x02, 0x9a, 0x0e, 0x1a,
- 0x76, 0x3b, 0x8f, 0x28, 0x60, 0xbc, 0xd4, 0x46, 0x51, 0xed, 0x86, 0xa3, 0x47, 0x66, 0x3c, 0x13,
- 0x59, 0x16, 0x75, 0x8d, 0x04, 0x31, 0xa3, 0x6e, 0x54, 0xe0, 0xe2, 0x5b, 0xde, 0x93, 0x2e, 0x8f,
- 0x6b, 0x23, 0x10, 0xe5, 0x2f, 0xf2, 0x8a, 0x8f, 0x0d, 0xdf, 0x68, 0x24, 0xc8, 0xbc, 0x07, 0x54,
- 0xa3, 0x94, 0x38, 0x91, 0xd6, 0xf8, 0x88, 0x97, 0xc0, 0x7c, 0x1f, 0x1f, 0x89, 0xc2, 0x9e, 0x15,
- 0x3c, 0xf5, 0xa5, 0x86, 0x8d, 0x54, 0x8c, 0x4d, 0x21, 0x21, 0x1c, 0xce, 0xa5, 0x94, 0x7f, 0x73,
- 0xe0, 0xc8, 0xfb, 0x6e, 0x05, 0xab, 0xc0, 0x72, 0xf0, 0x97, 0x6b, 0xfb, 0x02, 0xf0, 0xa0, 0xac,
- 0xfe, 0x6f, 0xae, 0xff, 0xd9, 0x48, 0x9d, 0x6d, 0x3f, 0x52, 0xa9, 0xd6, 0xa0, 0xb7, 0xfe, 0xb9,
- 0xd4, 0x5a, 0x56, 0xa2, 0xb3, 0x5d, 0x38, 0x99, 0x9f, 0x16, 0x65, 0x61, 0x88, 0xc5, 0x5d, 0x60,
- 0x94, 0x4b, 0xc5, 0x64, 0xc4, 0xc5, 0xca, 0xa9, 0xb5, 0xd3, 0x29, 0xa4, 0x20, 0xed, 0x5d, 0xc1,
- 0x1e, 0x84, 0xcc, 0xb6, 0xb6, 0x6b, 0x05, 0xc8, 0xfd, 0xaa, 0xc0, 0x4f, 0x03, 0xda, 0x7e, 0x06,
- 0x4c, 0x40, 0x2c, 0x8e, 0x5b, 0x3a, 0xf3, 0x35, 0x62, 0x7d, 0x4f, 0x61, 0x9d, 0x4d, 0x2b, 0x97,
- 0x8a, 0x5d, 0xec, 0xc9, 0x9f, 0xda, 0x76, 0x1e, 0x5b, 0xa0, 0xe6, 0x1c, 0xb1, 0xdf, 0xc0, 0x14,
- 0x60, 0x19, 0xf9, 0x48, 0x4a, 0xfe, 0x9c, 0x65, 0xdd, 0x30, 0x9f, 0x72, 0x2e, 0xb4, 0xe2, 0xf9,
- 0xc5, 0xec, 0xa1, 0x3b, 0x8f, 0xf8, 0x87, 0x42, 0xb7, 0xad, 0x9d, 0x76, 0xf9, 0x0e, 0xd9, 0x59,
- 0x75, 0x0e, 0xd8, 0x59, 0xd5, 0xd7, 0x87, 0x86, 0xf0, 0x51, 0x7b, 0x47, 0x7c, 0x1f, 0x62, 0x2d,
- 0xfd, 0xc9, 0xf9, 0xb8, 0xf2, 0x54, 0x34, 0x07, 0x9c, 0x61, 0xbc, 0x24, 0x77, 0x5b, 0xee, 0x71,
- 0xb1, 0x3b, 0x91, 0x68, 0x3e, 0x17, 0x64, 0xb8, 0x18, 0x54, 0x42, 0x94, 0xaa, 0xf5, 0x52, 0x43,
- 0x38, 0xe8, 0x48, 0x1f, 0x4e, 0x84, 0xe9, 0x3c, 0x12, 0xe6, 0xc3, 0xee, 0x8d, 0x97, 0xaf, 0xe7,
- 0xa7, 0xbd, 0x4e, 0x0f, 0x9b, 0x82, 0xa3, 0xa9, 0x52, 0x4b, 0x52, 0x8e, 0x18, 0xe6, 0xb8, 0x18,
- 0x5f, 0xa9, 0x95, 0xb7, 0x74, 0x28, 0x93, 0xd5, 0x9e, 0xda, 0x22, 0xed, 0x95, 0x99, 0x4f, 0xa1,
- 0xca, 0xad, 0xe5, 0x08, 0xbf, 0x3d, 0x91, 0xed, 0xb6, 0xef, 0xa4, 0x87, 0xa1, 0x01, 0x79, 0x5a,
- 0xab, 0xd6, 0x7a, 0x59, 0x67, 0xbb, 0x18, 0x7f, 0xf4, 0xf6, 0xfa, 0x78, 0x87, 0xd6, 0x5b, 0x85,
- 0x04, 0x62, 0x06, 0x88, 0xb9, 0xd0, 0xb9, 0xc0, 0x78, 0xa6, 0x58, 0x7e, 0x78, 0x1e, 0x61, 0x5a,
- 0x13, 0x45, 0x35, 0xfd, 0x4a, 0x97, 0x72, 0xef, 0xd0, 0xa1, 0xc0, 0xc5, 0x4d, 0x81, 0xdb, 0x81,
- 0xea, 0x3b, 0x51, 0xbe, 0x2d, 0xfd, 0x34, 0xf4, 0x87, 0x31, 0x44, 0x6b, 0x4c, 0xb7, 0x5a, 0x88,
- 0xbd, 0xd1, 0xd6, 0xb2, 0xce, 0x76, 0xd1, 0x0c, 0x1e, 0xd3, 0xa3, 0x31, 0x74, 0x59, 0x3c, 0xe9,
- 0x55, 0xde, 0x69, 0x93, 0x9b, 0x0b, 0x52, 0x9b, 0x03, 0xa9, 0xcc, 0x4c, 0x48, 0xd0, 0x52, 0x93,
- 0xc6, 0xbb, 0xbd, 0x5c, 0x9c, 0x71, 0xb2, 0x5a, 0x32, 0xba, 0xb4, 0xd1, 0xa6, 0xa1, 0xa3, 0x89,
- 0x67, 0xf6, 0x1a, 0x9d, 0x9b, 0x7b, 0xef, 0xb4, 0x55, 0xf1, 0xcd, 0x73, 0xa1, 0xa6, 0x32, 0xfe,
- 0x77, 0x29, 0x75, 0xd6, 0x6e, 0x79, 0x7d, 0x65, 0xf0, 0x95, 0x2a, 0x49, 0xcd, 0xb7, 0x05, 0xd8,
- 0x41, 0xf5, 0x33, 0x1f, 0xcd, 0x6f, 0x39, 0xc3, 0xf9, 0x6a, 0xcf, 0x1e, 0x67, 0x53, 0x67, 0xab,
- 0xcc, 0x4b, 0xc8, 0x03, 0xad, 0x7b, 0x6f, 0xeb, 0xbb, 0xed, 0xe5, 0xcf, 0xd9, 0xbb, 0xf5, 0xb8,
- 0xb5, 0x9e, 0x5a, 0x67, 0x6d, 0x46, 0xc3, 0x4b, 0x64, 0x90, 0xc1, 0xaf, 0x16, 0x49, 0xe1, 0x23,
- 0xbc, 0x1b, 0x53, 0xc1, 0xfb, 0x50, 0x90, 0x67, 0xc8, 0x8e, 0x68, 0xbb, 0x0d, 0x2e, 0xd7, 0xd2,
- 0x7e, 0xbb, 0xd0, 0x83, 0x60, 0xcb, 0xbd, 0x68, 0xb8, 0x2d, 0xe9, 0xc8, 0xf8, 0x64, 0x05, 0xc9,
- 0x37, 0x9f, 0xea, 0xb6, 0x6b, 0x75, 0xd1, 0xa2, 0x91, 0x8b, 0x53, 0xab, 0x92, 0x66, 0x7a, 0xf4,
- 0x1a, 0xff, 0x75, 0xaf, 0xfa, 0x44, 0x53, 0xc4, 0x8e, 0x52, 0xa9, 0x4c, 0x20, 0xe3, 0x93, 0x0e,
- 0x61, 0x42, 0xd9, 0xbd, 0xe1, 0x07, 0x22, 0x8b, 0x4b, 0x73, 0x62, 0x5d, 0x51, 0x2f, 0x20, 0x9e,
- 0x96, 0xfc, 0x6e, 0x72, 0xdf, 0x31, 0x99, 0x25, 0xb1, 0x67, 0x2d, 0xab, 0xa2, 0xef, 0xd2, 0xd1,
- 0x54, 0xf4, 0xe5, 0xd3, 0xac, 0xaf, 0x37, 0x8c, 0x04, 0x69, 0xc6, 0x30, 0x6b, 0xae, 0x58, 0x93,
- 0x3f, 0x68, 0x83, 0x56, 0x54, 0x4f, 0x0d, 0x37, 0x4e, 0xc1, 0x91, 0x6b, 0x11, 0x0b, 0x88, 0x77,
- 0xc4, 0x6c, 0x38, 0x54, 0x19, 0x71, 0x73, 0xf4, 0x48, 0x3a, 0x4a, 0x7f, 0xdb, 0xf6, 0x55, 0x4d,
- 0x7d, 0xaa, 0xdd, 0x90, 0xca, 0xa3, 0xe3, 0xaa, 0x02, 0x8b, 0xba, 0x0c, 0xa2, 0x3a, 0x2d, 0x14,
- 0xfd, 0x25, 0x75, 0x76, 0xd8, 0xd0, 0x85, 0x2c, 0x4f, 0xa4, 0x9a, 0x44, 0xf4, 0x22, 0xea, 0xd9,
- 0xca, 0xfd, 0x63, 0x35, 0xf0, 0x09, 0xa2, 0xe3, 0x12, 0x45, 0x95, 0x90, 0x35, 0xce, 0x14, 0xd8,
- 0x10, 0x39, 0xfe, 0x74, 0xf8, 0x12, 0xe1, 0x65, 0x4d, 0xc2, 0x91, 0x61, 0x31, 0x06, 0x4f, 0x2c,
- 0xdb, 0xf1, 0xa2, 0xfe, 0xb3, 0x57, 0xc6, 0xb5, 0x1e, 0xc2, 0x33, 0xe1, 0x7e, 0xaf, 0x36, 0x9b,
- 0xd1, 0xe3, 0xf2, 0xb1, 0x6c, 0x6c, 0x0c, 0x3a, 0x56, 0x1e, 0x86, 0x17, 0xa7, 0x60, 0xc1, 0xb0,
- 0x17, 0xa3, 0x34, 0x8b, 0x88, 0x88, 0xfb, 0x81, 0x08, 0x7b, 0x2d, 0x8c, 0x4d, 0xf5, 0x62, 0xf6,
- 0xe5, 0x5e, 0xb8, 0xa9, 0x60, 0xd5, 0xaf, 0xba, 0xa1, 0x57, 0x76, 0xc6, 0x99, 0x31, 0x2d, 0x80,
- 0x6e, 0x01, 0x54, 0x70, 0x46, 0x82, 0xe5, 0x33, 0x9a, 0x0a, 0x4a, 0x52, 0x8b, 0xf9, 0xe8, 0x41,
- 0x04, 0x53, 0xd2, 0xd7, 0x7a, 0xd2, 0xc5, 0x90, 0x09, 0x2b, 0x9e, 0x72, 0xd5, 0x0f, 0xd4, 0x8b,
- 0x14, 0xc4, 0x45, 0x26, 0x3b, 0xd5, 0xab, 0xf5, 0x62, 0x27, 0x64, 0x4c, 0x9d, 0xc0, 0xe9, 0xea,
- 0xa5, 0x04, 0x92, 0x86, 0x9a, 0x0e, 0x08, 0x98, 0x22, 0x64, 0x8c, 0x5a, 0xa4, 0x0b, 0x02, 0x26,
- 0x5a, 0x66, 0x7f, 0x17, 0x49, 0x3d, 0xc8, 0xe3, 0xfa, 0xc0, 0x49, 0xec, 0x03, 0xbb, 0xd2, 0x55,
- 0xda, 0xf3, 0x8c, 0xf9, 0x22, 0xd5, 0xd2, 0xbc, 0xe0, 0x8d, 0x2f, 0x84, 0x1f, 0xf1, 0x90, 0x4b,
- 0x62, 0xfb, 0xb3, 0xd5, 0x19, 0xc5, 0x6f, 0x55, 0x9f, 0x6f, 0xaa, 0xb7, 0x85, 0xd6, 0xe3, 0x69,
- 0x37, 0x8c, 0x6c, 0xc9, 0xe8, 0xad, 0xf7, 0xf5, 0x86, 0x6c, 0x28, 0x96, 0xb7, 0xa3, 0x7e, 0x12,
- 0x75, 0x46, 0x84, 0xea, 0x0c, 0x93, 0x6f, 0x6c, 0x95, 0xbb, 0x53, 0x01, 0x65, 0x8b, 0x1e, 0x79,
- 0x44, 0xce, 0xe8, 0x73, 0xfd, 0xcd, 0x1e, 0xb9, 0xa9, 0xcc, 0x60, 0x06, 0x92, 0x72, 0xa7, 0x8a,
- 0x80, 0x82, 0xf1, 0xa4, 0xb5, 0x73, 0xa2, 0xfd, 0x1d, 0x99, 0xca, 0x53, 0x73, 0x10, 0x69, 0x54,
- 0x4b, 0xda, 0x1b, 0x3a, 0x4f, 0x3b, 0x46, 0xf0, 0xb9, 0xb5, 0x32, 0xd8, 0x17, 0x60, 0x7d, 0x24,
- 0x3e, 0xb9, 0xd4, 0x66, 0xc2, 0xae, 0x44, 0x04, 0x7a, 0xe3, 0xc9, 0x39, 0x55, 0x67, 0xb4, 0xff,
- 0xce, 0xd0, 0xb1, 0x40, 0xac, 0x71, 0x8b, 0x0c, 0x2c, 0x85, 0xbe, 0x4a, 0x33, 0x12, 0x6c, 0x91,
- 0x72, 0x62, 0x24, 0x15, 0x49, 0x55, 0x4b, 0xf0, 0x85, 0xc9, 0xdd, 0x8b, 0x47, 0x52, 0x14, 0x91,
- 0x1e, 0x6a, 0x8a, 0xe7, 0x44, 0x65, 0xb7, 0xd7, 0xbd, 0x61, 0x2e, 0x6e, 0xac, 0x88, 0x90, 0x4c,
- 0x34, 0x9b, 0xc9, 0xb9, 0x3f, 0x4f, 0x3d, 0x17, 0x6a, 0x92, 0xd6, 0xb4, 0x4f, 0x6a, 0x21, 0xef,
- 0x55, 0xdc, 0xc3, 0x09, 0x5d, 0xcc, 0x30, 0x9e, 0xec, 0x3e, 0x5a, 0xa4, 0x64, 0x51, 0xef, 0xd7,
- 0x95, 0xae, 0x67, 0x02, 0xab, 0x84, 0x39, 0x96, 0x58, 0xf5, 0x84, 0xdd, 0x66, 0x5f, 0x56, 0x99,
- 0xbe, 0x56, 0x9e, 0xa0, 0x87, 0x47, 0x85, 0x57, 0xe3, 0xeb, 0x5e, 0xcc, 0xcd, 0xfb, 0x87, 0x92,
- 0x3d, 0x28, 0x2f, 0x97, 0xcb, 0x1e, 0xf7, 0x6c, 0xa8, 0xce, 0x36, 0x69, 0x5c, 0xac, 0x40, 0x6b,
- 0xdc, 0x93, 0xde, 0x67, 0x02, 0x6a, 0xfd, 0x98, 0x31, 0xe0, 0x4f, 0x3c, 0x8b, 0x1f, 0xec, 0x57,
- 0x5e, 0x1b, 0x34, 0xa8, 0x04, 0x69, 0x6a, 0xe2, 0x33, 0xf2, 0x8a, 0x66, 0x23, 0xda, 0x9d, 0x06,
- 0x9e, 0x55, 0xb0, 0xa4, 0xea, 0x8c, 0x56, 0x27, 0x12, 0x19, 0xcf, 0x6b, 0xa7, 0xea, 0xb4, 0x5e,
- 0xbb, 0xaf, 0x71, 0x43, 0xb6, 0xdf, 0xc6, 0x0b, 0xb6, 0x26, 0x1d, 0x0e, 0x1c, 0x78, 0x4d, 0x7d,
- 0x35, 0x39, 0x0c, 0x24, 0x10, 0x30, 0x40, 0x5a, 0x94, 0x10, 0xcd, 0x3d, 0xb8, 0x23, 0x29, 0xcc,
- 0x77, 0x03, 0x2f, 0xc1, 0xb7, 0x6e, 0x3b, 0x6c, 0x1f, 0xa4, 0x32, 0x1d, 0x1d, 0x15, 0xa0, 0xd7,
- 0x94, 0xf7, 0xdf, 0xe4, 0x2a, 0x9f, 0xe6, 0x1a, 0x77, 0xd5, 0x6d, 0x91, 0xac, 0x92, 0x95, 0xdc,
- 0x58, 0x87, 0xd4, 0x1c, 0x2f, 0xee, 0x04, 0x67, 0x3f, 0x33, 0xe3, 0xd1, 0xf6, 0x1f, 0x5d, 0x75,
- 0x17, 0x6b, 0xa9, 0x27, 0x17, 0xa1, 0x61, 0x09, 0x2f, 0x59, 0xce, 0x07, 0xbc, 0x94, 0x81, 0x8e,
- 0x5a, 0xf7, 0xbe, 0x0c, 0x2f, 0xbd, 0xc9, 0xf5, 0xb8, 0xe7, 0x53, 0xd9, 0x28, 0x9d, 0x7d, 0xd9,
- 0x55, 0x3a, 0x2d, 0xb1, 0xd2, 0x97, 0x32, 0x65, 0x4b, 0x18, 0xdb, 0xf2, 0x5e, 0x75, 0xcb, 0x9f,
- 0x1b, 0x5d, 0x27, 0x8b, 0xc9, 0xdd, 0xe3, 0x9e, 0x71, 0x7f, 0xe7, 0x7e, 0xc8, 0x83, 0x8f, 0xe4,
- 0xc9, 0x6e, 0x59, 0x6f, 0x0d, 0x2c, 0xb5, 0xae, 0x7e, 0x3a, 0xbb, 0xee, 0x62, 0x34, 0xa3, 0xa1,
- 0xbf, 0x1b, 0x7f, 0x73, 0xb6, 0x95, 0x58, 0x87, 0xd5, 0x40, 0xcf, 0xb8, 0x42, 0x9f, 0xce, 0xe6,
- 0x7d, 0x83, 0x64, 0x75, 0x62, 0xa6, 0xf0, 0xdd, 0x9e, 0x5f, 0x1f, 0x4e, 0xf8, 0x13, 0xbe, 0x98,
- 0x2f, 0x06, 0x7e, 0x3d, 0x0d, 0xaa, 0x3f, 0xdf, 0x33, 0xfe, 0x9d, 0x7b, 0x83, 0xd6, 0xf6, 0x1c,
- 0x4b, 0x56, 0x12, 0xb3, 0x39, 0x63, 0xe6, 0x3b, 0xec, 0xdf, 0x35, 0x10, 0xfa, 0xc9, 0xf8, 0xd3,
- 0xd0, 0x57, 0x42, 0x3a, 0xca, 0x2a, 0xd4, 0xf2, 0x98, 0x8a, 0xd4, 0x43, 0x67, 0xbe, 0x59, 0xc0,
- 0x4c, 0x96, 0x0d, 0x31, 0x27, 0x3e, 0xf9, 0x1b, 0xf0, 0x16, 0x9d, 0x22, 0xe0, 0xe5, 0xab, 0x44,
- 0x3e, 0x9b, 0xe2, 0xbb, 0xc3, 0x2a, 0x23, 0x56, 0xe9, 0x71, 0x7f, 0x1a, 0x0c, 0x87, 0xaa, 0x16,
- 0x96, 0x87, 0xff, 0xab, 0xb9, 0xd4, 0x96, 0x0c, 0x16, 0xe6, 0xe8, 0x31, 0x49, 0x5b, 0xf1, 0x94,
- 0xc6, 0x72, 0xf7, 0x7b, 0x27, 0x32, 0xa8, 0x85, 0x11, 0xa9, 0xcc, 0xd7, 0xbb, 0x80, 0xd1, 0x3a,
- 0xe9, 0xda, 0xcd, 0xe6, 0x9b, 0xa3, 0x47, 0xd6, 0xbd, 0x11, 0x3a, 0x2d, 0xb1, 0x2e, 0x3f, 0x2d,
- 0x71, 0x37, 0x92, 0xc9, 0x62, 0x12, 0x54, 0x30, 0x8c, 0xae, 0x75, 0xef, 0xb9, 0xe0, 0x88, 0x8e,
- 0x66, 0xc9, 0x29, 0xa4, 0xa2, 0x5c, 0xfc, 0x5a, 0xbc, 0x2d, 0x86, 0x1c, 0xd5, 0x5b, 0x37, 0x6b,
- 0x9c, 0x14, 0xc7, 0xe3, 0x24, 0x1c, 0x5d, 0x72, 0xae, 0xee, 0x8e, 0x90, 0x75, 0x76, 0x32, 0xae,
- 0x40, 0xa6, 0xe1, 0xbb, 0x13, 0x7f, 0xc0, 0x41, 0x27, 0x88, 0x20, 0x73, 0x6b, 0xf5, 0x23, 0xc7,
- 0x45, 0x7d, 0xfa, 0x3c, 0x61, 0xba, 0x08, 0xb9, 0x35, 0x37, 0xf3, 0xe8, 0x84, 0x5b, 0x88, 0xc2,
- 0xad, 0xab, 0x6d, 0xb1, 0x9a, 0xd8, 0x73, 0x3e, 0xca, 0x8f, 0x87, 0x7f, 0x1f, 0xc4, 0x94, 0xcc,
- 0x15, 0xcf, 0x96, 0xfe, 0x89, 0x43, 0x23, 0x41, 0x48, 0x20, 0x30, 0x08, 0x11, 0x11, 0xb3, 0x6f,
- 0x81, 0x0f, 0xcd, 0x32, 0x0d, 0x2b, 0xe4, 0x1e, 0xef, 0x7e, 0x0f, 0x38, 0xb4, 0x15, 0x26, 0x1e,
- 0xb0, 0x69, 0x4a, 0xa5, 0xa4, 0xe0, 0x63, 0x32, 0x34, 0x5a, 0x5a, 0xf7, 0x6a, 0xfd, 0x60, 0x85,
- 0x0c, 0xbf, 0x1c, 0x8d, 0x53, 0xe4, 0x08, 0xd5, 0x63, 0xc8, 0x15, 0x4c, 0xc8, 0x43, 0xf6, 0xca,
- 0xb8, 0x88, 0xe2, 0xdf, 0xd0, 0x17, 0x9c, 0xa7, 0x1e, 0x2d, 0x76, 0x88, 0xee, 0xb6, 0xe7, 0x96,
- 0x3d, 0xb7, 0xa1, 0xe3, 0xfe, 0xc5, 0x6e, 0xfb, 0x34, 0xb9, 0xdd, 0xc2, 0x58, 0x52, 0x43, 0xf2,
- 0xd8, 0x49, 0x17, 0xb0, 0x9b, 0xfd, 0x73, 0x94, 0x8b, 0x1f, 0xd1, 0xfa, 0xda, 0xf9, 0x17, 0xd6,
- 0x9a, 0x4f, 0x30, 0xc5, 0x47, 0x33, 0xab, 0x67, 0x27, 0x72, 0x16, 0xe8, 0x86, 0xf5, 0x06, 0xad,
- 0xa1, 0x10, 0xa2, 0x95, 0xa0, 0xfc, 0xcd, 0x20, 0x44, 0xfe, 0x6e, 0xa5, 0xff, 0x69, 0x5e, 0xf9,
- 0xe8, 0x85, 0x15, 0x04, 0x6c, 0x66, 0xcd, 0x8d, 0x17, 0xd3, 0xd1, 0xe9, 0x85, 0xe9, 0x4b, 0xd3,
- 0xcf, 0xbe, 0xf8, 0xea, 0x8b, 0x6f, 0x5d, 0xe8, 0x6e, 0xa9, 0xb3, 0x0d, 0x69, 0x9e, 0x58, 0x1e,
- 0x7b, 0xc5, 0xd5, 0xe3, 0x5e, 0xf7, 0x8e, 0x04, 0x9b, 0x88, 0x36, 0x1d, 0x09, 0xa2, 0x72, 0x7f,
- 0x41, 0xb8, 0x4d, 0xad, 0x25, 0x34, 0xec, 0x86, 0x58, 0x8a, 0x3e, 0xde, 0x1f, 0xa1, 0xb2, 0xb0,
- 0x90, 0x55, 0x65, 0xb2, 0xbc, 0xbe, 0x5e, 0x34, 0xce, 0xb8, 0x29, 0x3e, 0x04, 0x99, 0x02, 0x8a,
- 0xe6, 0xc2, 0xfc, 0xf9, 0xdd, 0xff, 0x16, 0xf4, 0x08, 0x9b, 0x85, 0xaa, 0x80, 0x3c, 0x76, 0x97,
- 0x4e, 0x8e, 0xdc, 0x8d, 0x0f, 0xc4, 0xe6, 0xd9, 0x1c, 0x38, 0x72, 0xbd, 0x21, 0xd1, 0xfc, 0xa7,
- 0x1d, 0x06, 0x1d, 0x1d, 0xef, 0x38, 0xde, 0x85, 0x89, 0xd2, 0x43, 0xf6, 0x06, 0xf7, 0xed, 0xa1,
- 0x89, 0xf7, 0x7c, 0x6f, 0xfb, 0xda, 0x7c, 0xa7, 0x08, 0xb5, 0xf1, 0xef, 0xf1, 0xe7, 0x09, 0x59,
- 0x15, 0x12, 0x55, 0x3a, 0x2f, 0x9e, 0x7f, 0x51, 0x4c, 0xef, 0xe5, 0xe9, 0x3c, 0xbd, 0x07, 0x03,
- 0xf8, 0x4f, 0x37, 0x7b, 0x0b, 0x1c, 0xfb, 0xe8, 0xc5, 0x87, 0xb4, 0x97, 0x68, 0x80, 0xd6, 0x64,
- 0x51, 0x8f, 0x65, 0x73, 0x9e, 0x30, 0x75, 0xed, 0x3d, 0xf1, 0xfc, 0x82, 0xd5, 0xf2, 0xe1, 0xb3,
- 0xcb, 0x5f, 0x5d, 0xee, 0xbf, 0xfc, 0xfb, 0xbf, 0xfd, 0xdf, 0xfe, 0x44, 0xf3, 0x9d, 0x86, 0x78,
- 0xb3, 0x54, 0x78, 0xe2, 0xe3, 0x1d, 0x67, 0xbb, 0xee, 0xf6, 0x76, 0xdb, 0x4f, 0xba, 0x4c, 0x81,
- 0xa6, 0x78, 0x8b, 0x84, 0x1c, 0xdb, 0x90, 0x3d, 0xf7, 0xd8, 0x4c, 0xb5, 0x31, 0x17, 0x8f, 0x88,
- 0x7d, 0xc1, 0xdd, 0x68, 0xb7, 0xdd, 0x90, 0x52, 0x0f, 0x85, 0x9d, 0xac, 0x84, 0xf1, 0x64, 0xb2,
- 0x45, 0xe2, 0x37, 0xe2, 0xb9, 0xf1, 0x92, 0x25, 0x33, 0x17, 0x4c, 0x94, 0xe9, 0x09, 0xdf, 0x99,
- 0x80, 0xe9, 0x6f, 0x8a, 0x53, 0x6e, 0xee, 0xda, 0xa3, 0x7d, 0x3d, 0x3f, 0x91, 0x7b, 0x93, 0xdb,
- 0x7c, 0xbd, 0x74, 0xae, 0x68, 0x67, 0x2d, 0xe6, 0x3b, 0xdf, 0xbf, 0xb8, 0x3c, 0xfc, 0xd9, 0xb9,
- 0xbf, 0xe8, 0xec, 0x7f, 0xd3, 0x4b, 0xe8, 0x9b, 0xd6, 0x87, 0x84, 0x9e, 0x75, 0x3e, 0xeb, 0x7c,
- 0xde, 0x79, 0xf8, 0x6d, 0x50, 0x2b, 0x25, 0x0b, 0xa1, 0x89, 0x36, 0x07, 0x21, 0xc2, 0xf3, 0x36,
- 0x1e, 0x74, 0x8a, 0xce, 0xc6, 0x63, 0xbd, 0xc0, 0xf4, 0x4f, 0xf9, 0xa9, 0x78, 0x6d, 0xf9, 0xf9,
- 0x6a, 0xea, 0xdf, 0x19, 0xef, 0x0a, 0xdf, 0xcf, 0xcf, 0xa9, 0x3a, 0xc6, 0x9f, 0xf0, 0x9d, 0xf0,
- 0x9d, 0x9a, 0x68, 0x6b, 0x6d, 0x7b, 0xd6, 0xe9, 0xed, 0x3c, 0xdd, 0xfd, 0xe0, 0x5d, 0xf3, 0xbb,
- 0x23, 0x67, 0x30, 0xd7, 0x55, 0xfb, 0xc4, 0xd0, 0xa8, 0xd8, 0x55, 0xf4, 0x0a, 0xe1, 0x25, 0xd0,
- 0x3a, 0x98, 0xb2, 0xb4, 0xe2, 0xc9, 0x89, 0x4d, 0x02, 0xf0, 0xb5, 0xd0, 0xba, 0xc2, 0xd8, 0x0f,
- 0xb3, 0x6f, 0x8f, 0xc9, 0xe5, 0xab, 0x71, 0x6c, 0xab, 0x7e, 0xf2, 0x92, 0x2d, 0x36, 0x9d, 0xb5,
- 0x3d, 0xee, 0x34, 0xd1, 0xfc, 0xdd, 0xf6, 0xfd, 0x74, 0x15, 0xb5, 0xd3, 0x9a, 0x6a, 0x13, 0x8d,
- 0x4f, 0xae, 0x74, 0x5d, 0xde, 0x75, 0x3f, 0x3c, 0xc3, 0x83, 0x0e, 0x96, 0x21, 0xf8, 0xb6, 0xe8,
- 0xf4, 0x3c, 0xdb, 0x55, 0x6f, 0x5b, 0xf9, 0xe0, 0xcf, 0xdf, 0x6d, 0x6a, 0x31, 0x9b, 0xe6, 0x4d,
- 0x0f, 0x4c, 0xdf, 0x9b, 0x0e, 0xb5, 0x1e, 0x7a, 0xf3, 0x34, 0xa1, 0x7e, 0x42, 0xe3, 0x84, 0x08,
- 0x8f, 0x09, 0x3d, 0x7c, 0xf3, 0x39, 0xa1, 0xc3, 0x27, 0x0e, 0x9f, 0x68, 0x3d, 0x61, 0x39, 0x61,
- 0x3d, 0xe1, 0x38, 0xe6, 0xa3, 0xc4, 0x57, 0x24, 0x91, 0xd1, 0x09, 0xb1, 0xf8, 0x15, 0x36, 0x99,
- 0xf4, 0x98, 0xe3, 0x58, 0x2b, 0x79, 0xb7, 0x47, 0xe4, 0xfd, 0xfb, 0xdf, 0xfc, 0xbe, 0x65, 0xb4,
- 0x85, 0x6b, 0xa9, 0x6a, 0x9c, 0xcc, 0xf7, 0x0f, 0x6b, 0x9f, 0x11, 0x5b, 0xe3, 0xdf, 0x77, 0x63,
- 0xd6, 0x33, 0x30, 0x76, 0xb8, 0xd5, 0x1b, 0xe2, 0x05, 0x21, 0xfb, 0x3b, 0xc4, 0x25, 0x2f, 0xef,
- 0x5c, 0xdb, 0x0b, 0x01, 0x81, 0x7a, 0xb9, 0x56, 0x1f, 0x6f, 0x56, 0xe2, 0xc7, 0xee, 0x66, 0xc8,
- 0x94, 0xa7, 0x49, 0xe3, 0x93, 0x8b, 0xac, 0x5b, 0xa8, 0xd2, 0x6c, 0xfe, 0x9d, 0x79, 0x5a, 0xee,
- 0x79, 0x30, 0x7f, 0xa3, 0xb3, 0x16, 0x5b, 0x72, 0xea, 0xfb, 0xbf, 0xec, 0x5f, 0xff, 0x20, 0x75,
- 0xe6, 0xdb, 0xc6, 0xa7, 0x8d, 0x9c, 0xc9, 0x6c, 0x1a, 0x25, 0x7c, 0x9d, 0x37, 0x45, 0x08, 0x6f,
- 0x1f, 0x98, 0x72, 0x26, 0xc2, 0xdb, 0xfa, 0xd3, 0xf5, 0xfd, 0xf5, 0xe3, 0xf5, 0x5e, 0x42, 0xdf,
- 0xd4, 0x3f, 0xac, 0x7f, 0x5e, 0xff, 0xfc, 0x8d, 0xc3, 0xc7, 0x5a, 0x8f, 0x59, 0x8e, 0x39, 0x6a,
- 0x1c, 0xf9, 0x99, 0xb1, 0x0a, 0xf1, 0x15, 0x48, 0xfb, 0x33, 0x8e, 0x1a, 0x4b, 0x4d, 0xeb, 0xb1,
- 0xe7, 0x6f, 0x3c, 0x24, 0xef, 0xd7, 0x5f, 0x7f, 0xa8, 0x3e, 0x42, 0x7e, 0xe7, 0xb7, 0x8d, 0xeb,
- 0x3f, 0x6f, 0xd7, 0x3d, 0x2f, 0x7b, 0xbe, 0xb3, 0x5d, 0xd3, 0xc3, 0xeb, 0x5e, 0xcc, 0x5b, 0x42,
- 0x66, 0xe1, 0x6c, 0x57, 0xee, 0xf1, 0x86, 0xc8, 0xfc, 0xda, 0xdc, 0xe3, 0x1f, 0x4e, 0xc3, 0xfe,
- 0x71, 0x69, 0xd1, 0x38, 0x64, 0x87, 0x9d, 0xb8, 0xea, 0xc1, 0xac, 0xc4, 0xdd, 0xc7, 0x27, 0x3b,
- 0x4b, 0xed, 0x24, 0xb9, 0xf9, 0x97, 0xe9, 0x34, 0xfd, 0x83, 0xfd, 0x7f, 0x65, 0xfb, 0x57, 0xdb,
- 0xba, 0x2d, 0xf4, 0xce, 0xdc, 0xe9, 0x5b, 0x8d, 0x69, 0xca, 0xd5, 0x66, 0x72, 0xc6, 0xe6, 0xba,
- 0x6b, 0x75, 0xf3, 0x75, 0x91, 0xba, 0x07, 0x84, 0x72, 0x75, 0x87, 0xf2, 0x5c, 0x1d, 0x07, 0x4f,
- 0xdf, 0xc8, 0x73, 0x54, 0xe5, 0x67, 0x99, 0x5d, 0x17, 0x3a, 0x4e, 0xd3, 0xbf, 0x83, 0x93, 0x87,
- 0x09, 0x27, 0xbf, 0x21, 0xef, 0x02, 0x4e, 0x3e, 0x20, 0xef, 0xdf, 0x6c, 0x5a, 0x6d, 0x5c, 0xf9,
- 0x79, 0xf1, 0xb3, 0xd1, 0x29, 0xc4, 0xb6, 0x1e, 0x2a, 0x95, 0x40, 0xf3, 0x00, 0xb3, 0x70, 0x49,
- 0xde, 0x10, 0x47, 0x89, 0x44, 0x3e, 0x10, 0x73, 0x8f, 0xe5, 0x32, 0xd3, 0x68, 0x7e, 0x1c, 0x84,
- 0xba, 0x04, 0xf2, 0xc3, 0x88, 0x4f, 0xca, 0xcd, 0xe6, 0xdf, 0x1f, 0x3f, 0x99, 0x8f, 0xd4, 0x59,
- 0x8b, 0xfd, 0x81, 0x53, 0xbd, 0xff, 0x7d, 0xb1, 0xdb, 0x76, 0xd3, 0xfe, 0x9f, 0xf6, 0xf5, 0xfe,
- 0xd9, 0x33, 0x9f, 0x36, 0xce, 0x35, 0xae, 0x12, 0x82, 0xb4, 0xbe, 0x66, 0x6a, 0xae, 0x33, 0xd7,
- 0x8d, 0x52, 0xae, 0x46, 0xea, 0xbe, 0xa7, 0x5c, 0x65, 0x92, 0xfa, 0xcd, 0x1b, 0x8f, 0xf4, 0x1c,
- 0x2d, 0xc7, 0x4f, 0x0d, 0x67, 0x19, 0x27, 0x1f, 0x51, 0x4e, 0x9e, 0xce, 0x73, 0xd2, 0x6c, 0x7a,
- 0xda, 0x78, 0xab, 0xf1, 0xfd, 0xbf, 0x54, 0x9f, 0x8b, 0xdd, 0x32, 0xec, 0x4e, 0x35, 0xba, 0xfa,
- 0x82, 0x66, 0xe1, 0x90, 0x54, 0x67, 0xc3, 0x93, 0x62, 0xf7, 0xc9, 0x46, 0x3e, 0x07, 0xf4, 0xc3,
- 0x6a, 0xd8, 0x3f, 0x36, 0xa1, 0xdf, 0x58, 0x9d, 0xcd, 0xff, 0xc3, 0xcc, 0x04, 0x62, 0xda, 0x16,
- 0x5e, 0x12, 0xe3, 0x28, 0xe6, 0x38, 0xc3, 0xcb, 0x45, 0x6c, 0xf0, 0x2f, 0xf6, 0x15, 0x9b, 0xe7,
- 0x83, 0x91, 0x33, 0x23, 0xa7, 0xe7, 0x4e, 0x2b, 0x5c, 0xe5, 0xea, 0x54, 0xae, 0x2a, 0x72, 0x0a,
- 0xcd, 0xab, 0x72, 0xb4, 0x58, 0xeb, 0xaa, 0x9a, 0xd5, 0x51, 0x63, 0x25, 0xba, 0x55, 0xe5, 0x64,
- 0x8e, 0xbc, 0xc7, 0x35, 0xc2, 0x49, 0xce, 0x94, 0x6e, 0x3c, 0xdf, 0xf8, 0xf1, 0x4f, 0x14, 0x3e,
- 0x2e, 0x12, 0x89, 0xc4, 0xc6, 0x86, 0x21, 0xfb, 0x8c, 0x27, 0x1c, 0x42, 0xcf, 0x49, 0x15, 0x45,
- 0xfe, 0x1d, 0x38, 0x12, 0x11, 0x27, 0xe4, 0x16, 0x19, 0x93, 0x9f, 0x27, 0xb2, 0xda, 0xda, 0xf6,
- 0x8f, 0x91, 0x80, 0xc0, 0x18, 0xcd, 0x4f, 0x73, 0x67, 0xd1, 0xe6, 0xcb, 0x36, 0xf9, 0xed, 0x95,
- 0xa3, 0x9b, 0x1c, 0xf3, 0x72, 0x13, 0xcd, 0xe8, 0x04, 0x46, 0xb7, 0x59, 0xb7, 0xfd, 0xa6, 0xfd,
- 0x4b, 0xdb, 0x3f, 0x7d, 0xf0, 0xeb, 0x77, 0x66, 0xcf, 0x84, 0xcf, 0xdc, 0x22, 0x5c, 0xfd, 0x77,
- 0x45, 0x03, 0xe7, 0xb5, 0x2f, 0x38, 0xaa, 0xca, 0x28, 0xe3, 0xa9, 0xb5, 0x40, 0x0e, 0xfa, 0x7f,
- 0x7c, 0xa7, 0xb5, 0x06, 0xaf, 0x3e, 0x7c, 0xc3, 0x5b, 0x7f, 0x89, 0x48, 0x24, 0x38, 0x39, 0x4a,
- 0x6e, 0xc6, 0x53, 0x72, 0x4b, 0x3e, 0x6b, 0xfc, 0xb7, 0x9f, 0x77, 0xfc, 0x09, 0xab, 0xef, 0x5c,
- 0xe9, 0x42, 0xd7, 0x47, 0x8f, 0x7b, 0xcb, 0x3b, 0x17, 0xba, 0x40, 0x7c, 0xd5, 0x4b, 0x72, 0x36,
- 0xca, 0xa2, 0x48, 0xa9, 0x19, 0x48, 0xac, 0x16, 0x09, 0xbc, 0x6c, 0xa9, 0x80, 0x71, 0xfd, 0xf1,
- 0x10, 0xf0, 0x1d, 0x23, 0xc1, 0x51, 0xa1, 0x2f, 0x28, 0x7f, 0x8e, 0x3d, 0x05, 0xfa, 0x4d, 0x0b,
- 0xff, 0x5f, 0x7e, 0x2a, 0x7e, 0x2f, 0xdb, 0xf5, 0x00, 0x9e, 0x5e, 0x86, 0xa4, 0xb6, 0x9f, 0xed,
- 0x9a, 0x22, 0x3c, 0xad, 0xb3, 0xfd, 0xca, 0xfe, 0x8f, 0xff, 0x57, 0xde, 0xd5, 0x84, 0x44, 0x15,
- 0x45, 0x61, 0x77, 0x05, 0x09, 0x19, 0xb5, 0x50, 0x6a, 0x61, 0xe1, 0xa6, 0x18, 0x41, 0xd3, 0x8d,
- 0x4c, 0x9b, 0xc9, 0x55, 0xfe, 0x91, 0x4e, 0x06, 0x3a, 0xab, 0xb8, 0xb8, 0x90, 0x47, 0x98, 0x3c,
- 0x66, 0x44, 0x6a, 0x16, 0x89, 0xb8, 0x88, 0xc9, 0x1c, 0x1d, 0x47, 0x90, 0x71, 0x13, 0xe5, 0x62,
- 0x60, 0xac, 0x46, 0xa7, 0x62, 0xc0, 0x36, 0x81, 0x2e, 0x02, 0x23, 0x05, 0x93, 0x04, 0x37, 0x2d,
- 0x5c, 0xb8, 0x70, 0xe1, 0x62, 0x20, 0x11, 0x3a, 0xdf, 0xb9, 0xef, 0xfa, 0xde, 0x1b, 0xb5, 0x9c,
- 0x71, 0xfc, 0xab, 0xfb, 0x21, 0x38, 0xef, 0xcd, 0x8f, 0xe3, 0xf7, 0xce, 0x3d, 0x3f, 0xf7, 0xbc,
- 0xfb, 0x89, 0x41, 0xcf, 0x90, 0x7b, 0xca, 0x1d, 0xae, 0x1e, 0x31, 0xec, 0x14, 0x56, 0x6a, 0xda,
- 0xa8, 0x62, 0x74, 0x8b, 0x39, 0x4d, 0xc7, 0x16, 0x1d, 0x07, 0x93, 0xf0, 0x92, 0xbf, 0xd8, 0x26,
- 0xab, 0x2a, 0x25, 0x93, 0xf1, 0x6b, 0x67, 0x2e, 0x60, 0x4e, 0x8d, 0xd2, 0x95, 0x53, 0xaf, 0xd1,
- 0x9c, 0xa0, 0xe3, 0x5e, 0x1a, 0xa8, 0x5b, 0x24, 0x17, 0xe3, 0x21, 0x55, 0x0f, 0xc0, 0xde, 0x15,
- 0xb7, 0xd6, 0xaf, 0x30, 0x97, 0xcb, 0x2b, 0x07, 0xdb, 0xad, 0xf9, 0x24, 0x00, 0x6b, 0x54, 0x58,
- 0x1f, 0xc0, 0x3d, 0xda, 0xd8, 0xaf, 0x0b, 0xaa, 0x13, 0xc5, 0xb9, 0x21, 0xd3, 0xc2, 0xa9, 0xb2,
- 0x53, 0xa5, 0xdf, 0x21, 0x2d, 0x55, 0xce, 0xbe, 0xf9, 0xa2, 0x41, 0x3c, 0x12, 0x41, 0x31, 0x49,
- 0x3e, 0xb5, 0x8b, 0xfc, 0xdc, 0x12, 0xdb, 0xa8, 0x39, 0xeb, 0x9a, 0x11, 0x2f, 0x81, 0xb8, 0x53,
- 0xc0, 0xe3, 0x88, 0x25, 0xde, 0xe9, 0xa6, 0x57, 0x2d, 0xd1, 0xeb, 0xef, 0x57, 0x04, 0x6f, 0x9c,
- 0xbb, 0x79, 0x87, 0xdf, 0x19, 0x9a, 0x45, 0xb8, 0x72, 0xea, 0xb4, 0x32, 0xf6, 0x93, 0xd0, 0xa1,
- 0x30, 0xb3, 0xb8, 0xe6, 0x18, 0xf6, 0x27, 0x06, 0x97, 0xfe, 0xf5, 0x70, 0xe2, 0xb4, 0xc6, 0x3d,
- 0x56, 0xa0, 0xef, 0x33, 0x35, 0x5d, 0x38, 0xb3, 0x40, 0xd9, 0xe6, 0xb3, 0xa6, 0xfd, 0x56, 0x82,
- 0xb2, 0x65, 0xd5, 0xb4, 0xd4, 0x9f, 0x86, 0xa5, 0xca, 0xd9, 0xf7, 0x4b, 0x6b, 0xa9, 0xe8, 0x10,
- 0xef, 0x28, 0x4a, 0x0a, 0x13, 0xa3, 0x1f, 0x38, 0x3e, 0xa2, 0x6c, 0x86, 0xe7, 0x5c, 0xe5, 0x47,
- 0x3d, 0x34, 0x97, 0x3e, 0xb1, 0x00, 0x47, 0xb6, 0xe3, 0x1d, 0xb6, 0xc9, 0x91, 0x0a, 0x5f, 0xc5,
- 0x94, 0x7b, 0x40, 0xcb, 0x17, 0x6b, 0xad, 0xd0, 0x5c, 0x80, 0x9a, 0x18, 0x7b, 0x4a, 0x3d, 0x1e,
- 0x41, 0xe6, 0x1e, 0xb5, 0xac, 0x03, 0xa3, 0x57, 0xd6, 0x6f, 0xcc, 0xb0, 0xe8, 0x42, 0x39, 0x6e,
- 0x1e, 0x72, 0x83, 0x9e, 0x02, 0x87, 0xe8, 0xa6, 0x7c, 0x59, 0xb2, 0xa9, 0x54, 0x1a, 0x0f, 0x73,
- 0xc8, 0xff, 0xa5, 0x39, 0xfb, 0x22, 0xab, 0x86, 0x9d, 0x52, 0x2e, 0x43, 0x33, 0xef, 0x37, 0x2d,
- 0xe4, 0xf6, 0x39, 0x47, 0x98, 0xd1, 0x2a, 0x4b, 0x16, 0xb3, 0xc9, 0xb8, 0x5c, 0x6a, 0x62, 0x93,
- 0x8e, 0x26, 0x39, 0x72, 0x2d, 0x32, 0x6c, 0x72, 0xd2, 0xf3, 0x46, 0x07, 0x8f, 0xe3, 0xe5, 0x25,
- 0xbc, 0x77, 0x36, 0x2a, 0x18, 0xe8, 0x88, 0xf0, 0xc6, 0x46, 0x17, 0xed, 0x7d, 0xbd, 0x7d, 0xe5,
- 0xfe, 0x94, 0x3f, 0x85, 0xbb, 0xc4, 0xfd, 0xf4, 0x93, 0xd9, 0xae, 0xcc, 0x27, 0x19, 0xd8, 0x5d,
- 0x23, 0xb9, 0x92, 0x9a, 0x96, 0x6b, 0x9b, 0x6d, 0x47, 0xa6, 0x6c, 0x2b, 0x39, 0x95, 0xba, 0x8b,
- 0x2a, 0xf2, 0xe5, 0xec, 0x54, 0xf4, 0x6b, 0x83, 0x1e, 0x8a, 0x8e, 0x0c, 0x46, 0x8b, 0xb6, 0xa3,
- 0x5d, 0x99, 0xc5, 0x28, 0x8c, 0x22, 0x6e, 0x25, 0x8b, 0x2c, 0x64, 0x26, 0x7d, 0xce, 0xb8, 0xa7,
- 0x5e, 0x6b, 0x67, 0x1e, 0x51, 0xfd, 0x78, 0x60, 0x64, 0x22, 0x0e, 0x01, 0xed, 0x8d, 0x70, 0xc2,
- 0xee, 0x11, 0xf3, 0x05, 0xfa, 0x0e, 0xc6, 0x08, 0xd8, 0x5f, 0xe9, 0xb8, 0x19, 0xc8, 0x25, 0xd0,
- 0x41, 0x9c, 0xe4, 0xfe, 0x2e, 0x54, 0x82, 0x72, 0x93, 0x6d, 0x66, 0xca, 0xa9, 0xca, 0x65, 0xd8,
- 0x46, 0x6b, 0xa2, 0x34, 0xeb, 0x0e, 0x68, 0x43, 0xee, 0x10, 0x57, 0x1b, 0x3e, 0x1a, 0x7e, 0x14,
- 0x76, 0x6a, 0x01, 0x3d, 0x2e, 0x32, 0xe2, 0x1d, 0x2f, 0x31, 0x89, 0x4c, 0xb9, 0xed, 0x3a, 0x7c,
- 0xbe, 0xcb, 0xd8, 0xe5, 0xa9, 0x04, 0xbb, 0x89, 0xeb, 0x14, 0xad, 0xcf, 0x7d, 0x4d, 0xab, 0xb5,
- 0x76, 0x06, 0x54, 0xa7, 0xc8, 0xa7, 0x54, 0xa6, 0xca, 0xdf, 0x27, 0x1d, 0x9f, 0x0b, 0x37, 0x22,
- 0x49, 0x43, 0xdf, 0x47, 0xe9, 0xa8, 0x1d, 0xed, 0x50, 0x8c, 0xc2, 0x97, 0x96, 0x5c, 0x85, 0x6a,
- 0x76, 0x7b, 0xcd, 0x5a, 0x6b, 0x03, 0xc7, 0x45, 0x89, 0x5a, 0x39, 0xeb, 0x2e, 0x71, 0xb4, 0x6b,
- 0x62, 0x89, 0x8e, 0xc1, 0x4b, 0x7a, 0xab, 0x83, 0x22, 0x5d, 0x89, 0xc7, 0xdc, 0x4d, 0x1c, 0xea,
- 0xb0, 0x67, 0xd3, 0xee, 0x5a, 0x41, 0xaf, 0xa4, 0xec, 0x08, 0x4a, 0x2e, 0xfe, 0x4d, 0xf9, 0xe8,
- 0xb4, 0x01, 0xf9, 0x09, 0xd6, 0x0f, 0x9a, 0x63, 0xe7, 0x7b, 0xe1, 0x35, 0x8f, 0x46, 0xe3, 0x6d,
- 0x2f, 0x46, 0x65, 0x74, 0x24, 0xeb, 0x47, 0x51, 0x9a, 0x73, 0x3b, 0x88, 0xd1, 0x05, 0xcf, 0x70,
- 0xad, 0x8f, 0x78, 0x43, 0xb4, 0xab, 0xd0, 0x45, 0x3e, 0xd2, 0xe7, 0x1c, 0x72, 0x77, 0x08, 0xe8,
- 0xa6, 0x5b, 0xf5, 0xce, 0xf0, 0x4e, 0xb2, 0x7f, 0xb0, 0xac, 0x17, 0xde, 0xc3, 0x5e, 0x09, 0xe8,
- 0x29, 0x68, 0x99, 0x83, 0xb7, 0xf4, 0xaf, 0x8f, 0xa5, 0xe2, 0xa1, 0xd3, 0x5d, 0x25, 0xd8, 0x9d,
- 0x4d, 0x74, 0xd0, 0x17, 0xce, 0xcc, 0x47, 0x8e, 0xcb, 0x32, 0xad, 0x8c, 0xda, 0xe7, 0x5c, 0xac,
- 0x3c, 0x96, 0x52, 0x5c, 0xf4, 0x56, 0x9b, 0x17, 0x53, 0x64, 0xa5, 0xde, 0x6a, 0x9f, 0xd3, 0xe7,
- 0x1c, 0xae, 0x9e, 0x72, 0xc7, 0xc5, 0x0b, 0xb2, 0xc8, 0xf6, 0x9a, 0xd9, 0x2a, 0x3b, 0x93, 0x79,
- 0x79, 0x6a, 0x87, 0x05, 0x44, 0x3e, 0x0f, 0x35, 0x7b, 0x6f, 0x52, 0x5f, 0x39, 0xd6, 0xb8, 0xd0,
- 0x0d, 0x84, 0x1e, 0xde, 0xbd, 0x3a, 0x98, 0x76, 0xa2, 0x67, 0x1f, 0xeb, 0x1e, 0x27, 0x03, 0xb8,
- 0xc3, 0x10, 0xfb, 0x81, 0x61, 0x3f, 0xb1, 0xa3, 0x53, 0x45, 0xdd, 0x7b, 0xa4, 0x33, 0xaa, 0x6a,
- 0x47, 0x0e, 0x51, 0x2f, 0x50, 0x05, 0xa8, 0x27, 0x16, 0xa1, 0x77, 0x0e, 0xdd, 0x5b, 0xe9, 0x25,
- 0xed, 0xaf, 0x66, 0x7f, 0x79, 0xbb, 0x5f, 0xdf, 0x88, 0x7c, 0x9f, 0xc6, 0x5a, 0x88, 0x09, 0xca,
- 0x35, 0x79, 0x05, 0xfa, 0xfd, 0x34, 0xd6, 0xbb, 0x5a, 0xe6, 0xba, 0xb3, 0x07, 0xf7, 0xda, 0xa3,
- 0xa6, 0x9b, 0xe4, 0x6b, 0x03, 0x57, 0x87, 0xc2, 0xb2, 0x81, 0x1f, 0x5c, 0xf3, 0xc5, 0xf3, 0xa0,
- 0x17, 0x94, 0xf9, 0x67, 0x58, 0x15, 0x55, 0xf6, 0x8b, 0x14, 0xef, 0x4b, 0x8a, 0xfe, 0xf6, 0xb3,
- 0x87, 0xae, 0x0a, 0xb6, 0xdf, 0x51, 0x6c, 0x63, 0x14, 0xd9, 0xcb, 0x78, 0xf9, 0x6c, 0xd5, 0xaa,
- 0x01, 0x28, 0x52, 0x23, 0xfb, 0xe8, 0x29, 0xd8, 0xf9, 0xd7, 0x2a, 0x05, 0xdc, 0x68, 0xd3, 0x84,
- 0xde, 0x19, 0x58, 0x88, 0x6c, 0xbc, 0xc2, 0x1e, 0x1c, 0x00, 0xee, 0x4e, 0x87, 0xb6, 0xd8, 0xdd,
- 0x40, 0x63, 0x20, 0x18, 0x42, 0x4f, 0xd0, 0xc5, 0xd7, 0x97, 0xb2, 0x46, 0x25, 0xe1, 0x5e, 0xac,
- 0x99, 0xfb, 0x89, 0xc2, 0x09, 0x74, 0x0e, 0x99, 0xc0, 0xe3, 0xe1, 0x84, 0x97, 0xce, 0x36, 0xc7,
- 0x2a, 0xf9, 0x99, 0xd9, 0x7f, 0x4e, 0x66, 0xd8, 0x88, 0xcc, 0x47, 0x1a, 0x03, 0x66, 0xcd, 0xe0,
- 0x38, 0xb8, 0xdb, 0x7d, 0x98, 0x8c, 0xbe, 0x34, 0xaa, 0x47, 0x12, 0x52, 0x11, 0x56, 0x56, 0x00,
- 0x76, 0x0e, 0xb9, 0xd2, 0x35, 0xcb, 0x31, 0x94, 0x83, 0x2d, 0x19, 0xbb, 0x10, 0xc9, 0xba, 0x1e,
- 0xea, 0x09, 0x52, 0xe7, 0xda, 0x21, 0xea, 0x34, 0x75, 0x2e, 0x5b, 0x3c, 0xd7, 0xfb, 0x75, 0x6b,
- 0x27, 0xd4, 0x3a, 0x03, 0xbf, 0xcd, 0x3d, 0x9e, 0xe0, 0x73, 0xfd, 0xfa, 0x41, 0xde, 0x3f, 0x53,
- 0xc8, 0xef, 0xb8, 0xd6, 0x2a, 0x7d, 0x4f, 0xee, 0x2a, 0xb3, 0xb9, 0x1c, 0x92, 0x53, 0x3b, 0x8a,
- 0xff, 0xf0, 0x6c, 0x17, 0xaf, 0xc1, 0xd9, 0x6d, 0x59, 0x62, 0x96, 0x6d, 0x1a, 0xfa, 0xf3, 0xe9,
- 0x67, 0xb2, 0x82, 0xcb, 0xd2, 0xff, 0x94, 0x06, 0x79, 0x7c, 0xd5, 0x95, 0x83, 0x4f, 0xc9, 0x08,
- 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2,
- 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8,
- 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c,
- 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00
-};
-
-fastimage_t bfin_logo = {
- DEF_BFIN_LOGO_DATA,
- DEF_BFIN_LOGO_WIDTH,
- DEF_BFIN_LOGO_HEIGHT,
- DEF_BFIN_LOGO_BPP,
- DEF_BFIN_LOGO_PIXEL_SIZE,
- DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
deleted file mode 100644
index 1955f668ff93..000000000000
--- a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where: 'screen' is the pointer to the frame buffer
- * 'width' is the screen width
- * 'x' is the horizontal position
- * 'y' is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 16703
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define DEF_BFIN_LOGO_WIDTH 230
-#define DEF_BFIN_LOGO_HEIGHT 230
-#define DEF_BFIN_LOGO_PIXELS 52900
-#define DEF_BFIN_LOGO_BPP 16
-#define DEF_BFIN_LOGO_PIXEL_SIZE 2
-#define DEF_BFIN_LOGO_SIZE 105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xff, 0xff, 0x86, 0x51, 0xd0, 0x3c, 0xfc, 0x65, 0xea, 0x02, 0x56, 0x77, 0x71, 0xde, 0xb1,
- 0x96, 0x62, 0x13, 0xa4, 0x11, 0xbb, 0x19, 0xd3, 0x9a, 0xab, 0x0c, 0x4c, 0x38, 0xa6, 0xe4, 0x24,
- 0x50, 0x2c, 0xfd, 0x3f, 0xd2, 0xc8, 0x41, 0x4b, 0xb3, 0x73, 0x7a, 0xdd, 0x22, 0x8d, 0x88, 0xd2,
- 0x32, 0x18, 0x2e, 0x8a, 0x93, 0x47, 0xf5, 0x99, 0xc7, 0x3f, 0x9c, 0xf5, 0xe7, 0x24, 0xbe, 0xe2,
- 0xbd, 0x73, 0xa7, 0x5a, 0xa6, 0x8d, 0x39, 0xa0, 0x0b, 0xfc, 0x62, 0x94, 0x5d, 0x17, 0xa1, 0x97,
- 0x72, 0xa9, 0xd4, 0xc5, 0xe3, 0x2e, 0x63, 0x86, 0x09, 0x55, 0x3c, 0xd5, 0xc2, 0xe4, 0x56, 0x1d,
- 0x05, 0xc5, 0x76, 0xe7, 0x35, 0x0c, 0x83, 0xbd, 0x33, 0x9b, 0x9f, 0xed, 0x10, 0xb2, 0x96, 0x1a,
- 0xe3, 0x9f, 0x16, 0x88, 0x0b, 0x5b, 0x7e, 0x9c, 0x8e, 0xd4, 0xd1, 0xc0, 0x1b, 0x36, 0xee, 0x23,
- 0xf3, 0xf9, 0xd7, 0x6e, 0xe0, 0x42, 0xe2, 0x99, 0xbe, 0x90, 0xb0, 0x6c, 0xc7, 0x2c, 0xa3, 0x75,
- 0xf6, 0xb6, 0x9d, 0x30, 0x18, 0x87, 0x9c, 0x49, 0x07, 0xf7, 0x78, 0x49, 0x72, 0xa3, 0x62, 0x28,
- 0x7d, 0xa1, 0xc9, 0x15, 0x76, 0x75, 0x63, 0xf7, 0xdf, 0xf4, 0x99, 0x81, 0xa7, 0x1f, 0xfd, 0x93,
- 0xfa, 0x71, 0x91, 0x1b, 0xbe, 0x3e, 0x38, 0xcf, 0x84, 0x51, 0x34, 0x43, 0x23, 0xa7, 0x31, 0x61,
- 0x44, 0x1b, 0x4d, 0x5c, 0x17, 0xcb, 0x39, 0xc6, 0x81, 0x8f, 0x10, 0xb1, 0x73, 0xa0, 0x51, 0x3e,
- 0xba, 0x38, 0xd1, 0x0f, 0x9a, 0x84, 0xc3, 0xa6, 0x30, 0x30, 0x27, 0x4a, 0x01, 0xf8, 0xca, 0xbf,
- 0xea, 0x0e, 0x6f, 0xe3, 0xeb, 0x7d, 0x8a, 0x59, 0x22, 0x07, 0x15, 0xe0, 0xcf, 0x04, 0xb6, 0x03,
- 0xdd, 0x71, 0xef, 0x6a, 0x25, 0xc2, 0x9d, 0x8f, 0xc1, 0x63, 0x2a, 0xec, 0xb8, 0x3e, 0x32, 0xee,
- 0xda, 0x98, 0x28, 0xc0, 0x60, 0x42, 0xe7, 0x0d, 0x38, 0x1b, 0xd0, 0xaa, 0x4c, 0xc4, 0x93, 0x19,
- 0x7a, 0x42, 0x41, 0xe5, 0xf8, 0xa8, 0x42, 0xbc, 0x9c, 0xb4, 0xd8, 0xd2, 0x85, 0xe6, 0x2d, 0xd6,
- 0xad, 0x5c, 0x6d, 0xaa, 0xf8, 0xa5, 0x81, 0xf8, 0x38, 0x05, 0xd9, 0x7c, 0xe2, 0x37, 0x5a, 0x47,
- 0x9d, 0xe7, 0x60, 0x1c, 0xbc, 0x02, 0x2b, 0x66, 0x3a, 0x49, 0xdb, 0xa0, 0xd3, 0x5d, 0x4c, 0xaf,
- 0x8c, 0x01, 0x4d, 0xe3, 0xce, 0xe7, 0x5a, 0xf1, 0x5e, 0x82, 0xd6, 0xcf, 0x69, 0x0c, 0x74, 0x42,
- 0x0a, 0xb3, 0xa3, 0x5a, 0x30, 0x40, 0xee, 0xf6, 0xea, 0xa6, 0xcc, 0x30, 0x44, 0x8c, 0x0f, 0xbc,
- 0x68, 0x0c, 0x49, 0x76, 0x06, 0x1c, 0x76, 0x91, 0xe2, 0xd4, 0x53, 0xc4, 0x29, 0x74, 0x2d, 0x81,
- 0x2e, 0x1f, 0x55, 0x27, 0x36, 0x73, 0x50, 0x24, 0x75, 0xcb, 0x5b, 0x3a, 0xc8, 0x82, 0x0a, 0xf7,
- 0x93, 0x25, 0x94, 0x3d, 0x4a, 0x85, 0x6c, 0xcc, 0x84, 0x1c, 0x5b, 0x58, 0xa9, 0x61, 0xe0, 0xde,
- 0xc2, 0x9e, 0xc6, 0x35, 0xaa, 0x9f, 0x2c, 0x98, 0x5b, 0xd7, 0x74, 0x10, 0x9f, 0x61, 0x8c, 0x67,
- 0x04, 0x3a, 0x1c, 0x37, 0x69, 0x3d, 0xb0, 0x07, 0x8c, 0xfc, 0x22, 0x65, 0x2d, 0x7c, 0x83, 0x91,
- 0x02, 0xc7, 0x4c, 0x59, 0xd3, 0x9e, 0x63, 0x44, 0x64, 0x3f, 0xb8, 0xc4, 0x24, 0x8e, 0xe4, 0xb9,
- 0x64, 0x11, 0x8a, 0x4e, 0x4f, 0xd7, 0x88, 0xb3, 0x5d, 0xb8, 0xe0, 0x19, 0x04, 0xf7, 0x47, 0xec,
- 0xf9, 0xa8, 0x4f, 0x6a, 0xa6, 0x66, 0x49, 0x1b, 0x34, 0xe9, 0xf9, 0x3c, 0x44, 0x51, 0x05, 0x1d,
- 0xb6, 0x81, 0x82, 0xc8, 0xc1, 0x26, 0x3c, 0x1d, 0x8a, 0xa8, 0x2d, 0x80, 0xc7, 0xc9, 0x47, 0x32,
- 0x67, 0x32, 0x05, 0xc1, 0xb1, 0x0a, 0x7e, 0x9b, 0x1e, 0x62, 0xb6, 0x6c, 0x1a, 0x82, 0xf2, 0x49,
- 0xbf, 0x14, 0x0d, 0x7f, 0x0f, 0x61, 0xf9, 0x6e, 0x9f, 0xfa, 0x6b, 0x63, 0x18, 0xfd, 0x36, 0x46,
- 0x1b, 0xc4, 0x76, 0x0e, 0x30, 0x60, 0x29, 0x31, 0x23, 0x42, 0x95, 0x99, 0xbd, 0x9f, 0x5b, 0xe3,
- 0xc8, 0xbd, 0xa4, 0xf9, 0xae, 0xce, 0xcf, 0x9e, 0x43, 0x8f, 0xe3, 0x9d, 0x5b, 0x3b, 0x4e, 0x87,
- 0xe9, 0x58, 0xda, 0x8d, 0xd7, 0x78, 0x43, 0x78, 0x52, 0x01, 0xf2, 0x31, 0xa4, 0x43, 0xeb, 0x84,
- 0x00, 0xf7, 0x5f, 0x2b, 0x63, 0x9d, 0xb9, 0x34, 0x86, 0x9c, 0x94, 0x33, 0xa4, 0x60, 0x36, 0xe0,
- 0x17, 0xf3, 0x6a, 0x7c, 0x0d, 0x3b, 0xe7, 0x7d, 0x2c, 0xc2, 0x92, 0x83, 0x5f, 0xc7, 0x39, 0x2d,
- 0xc6, 0x48, 0x61, 0xc4, 0xde, 0x32, 0x49, 0x8e, 0xbc, 0x7c, 0xf0, 0x18, 0xda, 0xe7, 0x7c, 0xef,
- 0x49, 0xd1, 0xa7, 0xf9, 0xa9, 0x11, 0x67, 0x33, 0x28, 0xee, 0x65, 0x47, 0x99, 0xa7, 0x83, 0xdf,
- 0x3f, 0x8c, 0x23, 0x2f, 0xb5, 0x55, 0xff, 0x79, 0x0b, 0xc0, 0xc7, 0x3d, 0x1e, 0x2b, 0xf9, 0x20,
- 0x93, 0x6b, 0x05, 0x50, 0x94, 0x0c, 0x5c, 0x3f, 0x94, 0x4b, 0x99, 0x10, 0x25, 0x4b, 0xb7, 0x1a,
- 0x8c, 0xe1, 0xaf, 0xe9, 0x8b, 0xde, 0x89, 0x50, 0xa8, 0x08, 0xbb, 0x1a, 0xec, 0xdf, 0xe8, 0x95,
- 0x06, 0x51, 0xe6, 0xb7, 0x26, 0x07, 0xeb, 0x5b, 0x8e, 0x4b, 0x50, 0x64, 0x5c, 0x8d, 0xb5, 0x52,
- 0x30, 0xf5, 0xc9, 0x07, 0xf2, 0x54, 0x4f, 0x7c, 0xb0, 0xfb, 0xa4, 0x48, 0xfd, 0x3c, 0x50, 0xbb,
- 0xcb, 0x39, 0xbe, 0x9a, 0x74, 0x44, 0x85, 0x01, 0x0f, 0x77, 0x1d, 0x86, 0x1f, 0x9a, 0x35, 0x06,
- 0x14, 0x48, 0x08, 0x6d, 0xc1, 0x89, 0xc6, 0x38, 0x5c, 0x8f, 0x1a, 0xc4, 0x89, 0xe7, 0x29, 0xa2,
- 0x87, 0x8a, 0xf2, 0xf7, 0x13, 0x5c, 0x2b, 0x0c, 0x17, 0x22, 0xc6, 0x02, 0x97, 0x5c, 0xe9, 0x10,
- 0xc4, 0xbd, 0x6b, 0x91, 0x9a, 0x0b, 0x70, 0x85, 0xd3, 0x91, 0xce, 0x12, 0x34, 0xef, 0xe3, 0xf7,
- 0xf6, 0xbf, 0x55, 0x0a, 0x67, 0xdd, 0x42, 0x7c, 0xa0, 0x46, 0xad, 0x30, 0xa1, 0xdf, 0x73, 0x6d,
- 0x93, 0x26, 0x57, 0xae, 0x2a, 0xe6, 0xea, 0x2c, 0xe5, 0xf3, 0x09, 0xaa, 0xdd, 0x09, 0xc7, 0xa0,
- 0x0c, 0xef, 0x86, 0xa8, 0x42, 0x93, 0x5e, 0x61, 0xe4, 0xa4, 0x08, 0xaa, 0x37, 0x4b, 0xd4, 0x94,
- 0x83, 0xe1, 0x42, 0x06, 0x65, 0x11, 0x4e, 0xbf, 0xc3, 0xfb, 0xbf, 0x86, 0x4f, 0x01, 0x69, 0x93,
- 0xd5, 0xc8, 0xb4, 0x5d, 0x23, 0x79, 0x38, 0x8a, 0x6b, 0x9f, 0xfb, 0x56, 0xb0, 0x16, 0x6e, 0x9f,
- 0xdf, 0x40, 0x96, 0x9c, 0x92, 0x17, 0xae, 0xdb, 0xba, 0x4e, 0xd6, 0x88, 0x44, 0x2f, 0xaf, 0x84,
- 0xa3, 0xb6, 0x04, 0xa1, 0x59, 0x42, 0x3f, 0xd4, 0x45, 0x0d, 0x76, 0xb2, 0x67, 0x6f, 0xab, 0xad,
- 0xe8, 0xda, 0x1d, 0x8e, 0x07, 0x96, 0xc5, 0x1c, 0xf9, 0x97, 0xe2, 0x21, 0x97, 0xd9, 0x4c, 0x79,
- 0x02, 0xe5, 0x0c, 0x57, 0x59, 0x1b, 0xcb, 0x09, 0x9a, 0xb3, 0x34, 0xc7, 0x0b, 0x66, 0x8a, 0xc9,
- 0x38, 0xa6, 0x2c, 0x27, 0xac, 0x20, 0xbd, 0x69, 0x54, 0xa1, 0x33, 0x9a, 0x70, 0x4f, 0x9d, 0xe2,
- 0x6e, 0x79, 0x72, 0x17, 0xfc, 0x12, 0xe9, 0x96, 0x0c, 0x12, 0x5d, 0x44, 0xb7, 0x71, 0x87, 0x03,
- 0xeb, 0x2d, 0x30, 0x1f, 0xe8, 0xa0, 0x70, 0x60, 0xb4, 0x4d, 0x98, 0xcb, 0xa3, 0x58, 0x94, 0x04,
- 0xa2, 0xae, 0x14, 0xca, 0xf4, 0x6b, 0x22, 0x12, 0x04, 0xcc, 0x28, 0x7e, 0xea, 0x66, 0xb6, 0x18,
- 0x86, 0xdc, 0xcc, 0xef, 0xeb, 0x3a, 0x3e, 0x4e, 0xcc, 0xd5, 0x94, 0xc7, 0x5e, 0xdd, 0x1f, 0x96,
- 0xd0, 0x8f, 0x18, 0xe9, 0xbf, 0xe0, 0xda, 0x0c, 0x80, 0xaa, 0x29, 0xef, 0x31, 0xd7, 0x69, 0xfc,
- 0x35, 0xa5, 0xb6, 0x91, 0x0f, 0x44, 0x8f, 0x32, 0x34, 0x69, 0x6d, 0xc7, 0x44, 0xa7, 0xa6, 0x58,
- 0x01, 0xef, 0x51, 0x41, 0xef, 0x5c, 0xa6, 0xff, 0x92, 0xcd, 0xc7, 0x4c, 0xc8, 0x2a, 0x0d, 0x9c,
- 0xdb, 0x05, 0x55, 0x31, 0xfb, 0x74, 0x2b, 0x87, 0x3b, 0x2e, 0x38, 0x71, 0x15, 0xff, 0xa2, 0x51,
- 0xcc, 0x3d, 0xa7, 0xfc, 0xc3, 0xfd, 0x8e, 0x24, 0x1d, 0x5f, 0x61, 0x4a, 0x4b, 0x5d, 0xd8, 0x9b,
- 0x46, 0x72, 0x48, 0xf3, 0xcf, 0xbc, 0x41, 0xde, 0xc7, 0x44, 0xf1, 0x29, 0xfc, 0x14, 0xa6, 0x76,
- 0x5a, 0xec, 0x23, 0x38, 0xa1, 0xee, 0xd8, 0x46, 0x2a, 0x6e, 0xf2, 0x0e, 0x45, 0xa6, 0x11, 0x21,
- 0xfd, 0x3a, 0xc2, 0x1b, 0xdb, 0xb3, 0x0b, 0x1f, 0xe0, 0xc4, 0xf6, 0x75, 0xf7, 0x0f, 0xee, 0x15,
- 0xc3, 0x83, 0x65, 0xc4, 0x0c, 0x59, 0x6e, 0xdc, 0x43, 0x25, 0x2a, 0x66, 0x6d, 0x32, 0x3b, 0x0c,
- 0xb6, 0x78, 0xe3, 0xde, 0x21, 0xc3, 0xcf, 0xb8, 0x70, 0x8d, 0xcf, 0xd8, 0x5e, 0x18, 0xb1, 0x89,
- 0x6e, 0x99, 0xb6, 0x02, 0x36, 0xde, 0x1b, 0x85, 0xb4, 0xd7, 0x71, 0x89, 0x0e, 0x70, 0x4d, 0x7f,
- 0x44, 0xa0, 0xcc, 0x2d, 0xb3, 0xfb, 0x3a, 0x99, 0x7e, 0xea, 0x16, 0xda, 0x1d, 0x88, 0x8b, 0x03,
- 0xf6, 0x74, 0x1c, 0xd9, 0x2b, 0x84, 0xb4, 0xa9, 0x65, 0xab, 0x5d, 0xa6, 0x7f, 0x1f, 0x29, 0x3b,
- 0x9c, 0x85, 0x08, 0x75, 0x85, 0x6e, 0xb8, 0xc9, 0x0c, 0x50, 0xb9, 0x04, 0x3d, 0x38, 0x90, 0x78,
- 0x55, 0x27, 0x71, 0xc4, 0xec, 0x18, 0x6e, 0x60, 0xd5, 0xa0, 0x63, 0xd0, 0x93, 0xa0, 0x5f, 0x51,
- 0xf0, 0x1f, 0x6a, 0x9b, 0x5a, 0xb4, 0x65, 0x6a, 0x67, 0x4e, 0x1d, 0x40, 0xaa, 0x9a, 0x31, 0x84,
- 0xf4, 0xd2, 0xd7, 0x4f, 0x09, 0x0f, 0x02, 0xe9, 0xc6, 0x1b, 0x20, 0x9a, 0xe5, 0x11, 0x21, 0x0d,
- 0x13, 0x5c, 0xc6, 0x93, 0x26, 0xb5, 0xb3, 0x95, 0x3b, 0xf0, 0x93, 0x7e, 0x8c, 0xdc, 0xe1, 0xfe,
- 0x58, 0x18, 0xb1, 0xb0, 0xd9, 0x0f, 0x9e, 0xad, 0x51, 0x05, 0x41, 0x24, 0xb6, 0xb8, 0xbe, 0xc2,
- 0x84, 0x30, 0x82, 0xf6, 0x3b, 0x4e, 0x84, 0xf7, 0xe6, 0xc5, 0x20, 0x1e, 0x53, 0x42, 0xad, 0x0b,
- 0x39, 0x97, 0x70, 0xbf, 0x59, 0xf9, 0x24, 0xbb, 0x03, 0x07, 0xed, 0xc2, 0xf0, 0xf0, 0x91, 0x8f,
- 0x6b, 0x1f, 0x70, 0x49, 0x0a, 0x52, 0x99, 0x4e, 0xcf, 0x9b, 0x22, 0x0b, 0x26, 0xae, 0x0d, 0xe6,
- 0x23, 0x36, 0x7c, 0xd5, 0xbe, 0x65, 0x1c, 0xdb, 0x68, 0x2d, 0x12, 0xe2, 0x1a, 0xc8, 0xd9, 0x74,
- 0x25, 0x3a, 0x44, 0x8e, 0x84, 0x35, 0xf6, 0x6c, 0x96, 0x71, 0x19, 0xdf, 0x58, 0x6a, 0xf2, 0xbc,
- 0x6f, 0x5a, 0xfe, 0xd2, 0x77, 0x68, 0x8e, 0xae, 0xab, 0x9e, 0x3c, 0xd7, 0xc5, 0x15, 0xe4, 0xc2,
- 0xe1, 0xa2, 0xb1, 0xa8, 0xfe, 0x7b, 0xb1, 0x0e, 0x21, 0x39, 0xa9, 0xe4, 0xa8, 0xcc, 0xa7, 0x12,
- 0xc6, 0x64, 0x6b, 0xf8, 0x85, 0xed, 0xfc, 0x8e, 0x17, 0x7c, 0x8e, 0xd0, 0x7a, 0xfb, 0x53, 0x99,
- 0x1c, 0x36, 0xe3, 0x39, 0x32, 0xd2, 0x56, 0x16, 0xcb, 0xba, 0x03, 0x05, 0xfc, 0x65, 0x25, 0x83,
- 0xec, 0xe6, 0x92, 0x84, 0xbf, 0x8b, 0x4f, 0x89, 0x75, 0x4f, 0x5b, 0x9e, 0xd4, 0x79, 0x1e, 0xc7,
- 0xee, 0xb2, 0x44, 0xcd, 0x59, 0x45, 0x34, 0xc9, 0xe8, 0x03, 0xca, 0x99, 0x19, 0x56, 0x62, 0x51,
- 0xc5, 0x40, 0xd2, 0xfb, 0x85, 0xb2, 0xf0, 0x02, 0xab, 0x58, 0x98, 0x60, 0x42, 0xda, 0x81, 0xbb,
- 0x63, 0x45, 0x85, 0x62, 0x21, 0x6b, 0xa9, 0x95, 0x12, 0x0a, 0x25, 0xb3, 0x99, 0xfa, 0x5f, 0x3a,
- 0xb2, 0xc5, 0xdb, 0x92, 0x21, 0x19, 0x8d, 0x38, 0x45, 0xbb, 0xa4, 0xa3, 0xf2, 0xb5, 0xdf, 0xe2,
- 0x94, 0xd8, 0xed, 0xf7, 0xf8, 0x85, 0x80, 0xb5, 0x87, 0xf1, 0x1a, 0xd0, 0xfb, 0x71, 0x4e, 0x2b,
- 0xd8, 0xdf, 0x96, 0x73, 0x31, 0xf2, 0x3f, 0x4b, 0x76, 0xac, 0xd1, 0xdd, 0x0c, 0x47, 0x78, 0x4e,
- 0xc6, 0x13, 0x14, 0x13, 0xf5, 0xa5, 0xde, 0x87, 0x55, 0xd1, 0xdc, 0x13, 0x56, 0x54, 0x8a, 0x17,
- 0xd8, 0x0d, 0x72, 0x6a, 0x60, 0x84, 0xd1, 0x07, 0xfd, 0x0b, 0x99, 0x77, 0x66, 0x96, 0x9b, 0x22,
- 0x23, 0x04, 0xc1, 0x21, 0x1c, 0x90, 0x65, 0x24, 0x63, 0xc8, 0xaf, 0x1a, 0xdb, 0xe0, 0xe0, 0x66,
- 0xf4, 0x34, 0xeb, 0x35, 0x28, 0x61, 0xbc, 0x20, 0x7a, 0xdc, 0x77, 0x1b, 0xf0, 0xd4, 0xbd, 0xb8,
- 0xb3, 0xaa, 0x61, 0x59, 0x45, 0x9e, 0x89, 0x77, 0xc4, 0xfd, 0xbc, 0x5c, 0xb0, 0xcf, 0x76, 0x0f,
- 0x49, 0xa8, 0xa4, 0x23, 0x34, 0x81, 0x41, 0xc7, 0xc8, 0x81, 0x5a, 0xb8, 0xf7, 0x20, 0x8c, 0xed,
- 0xc2, 0x59, 0x97, 0xa0, 0x9e, 0x1c, 0x27, 0xaf, 0x43, 0xcd, 0x8a, 0xb0, 0x6c, 0x6d, 0xbc, 0x75,
- 0x4c, 0x8f, 0x66, 0x6a, 0x7c, 0xb7, 0x8a, 0x40, 0xcb, 0xed, 0xce, 0xe7, 0x82, 0xfe, 0x33, 0x6e,
- 0xc2, 0xf6, 0xa0, 0x9a, 0xcb, 0x01, 0xa2, 0xd6, 0xb0, 0xf8, 0x2a, 0x97, 0xfb, 0x8e, 0xbd, 0x39,
- 0xd5, 0xfb, 0x95, 0xdf, 0xe3, 0x3b, 0x72, 0x46, 0x06, 0x5f, 0xd5, 0xb2, 0x70, 0xb8, 0x9d, 0x9b,
- 0xee, 0x7e, 0xeb, 0x9b, 0x84, 0xb2, 0x47, 0x56, 0xc7, 0xc6, 0x3e, 0xcd, 0x0d, 0x83, 0x83, 0x5c,
- 0x0f, 0x2b, 0x37, 0x7b, 0x09, 0x35, 0xc7, 0x9c, 0x96, 0x00, 0xbe, 0x91, 0xaf, 0x3e, 0xa4, 0xff,
- 0xd9, 0x73, 0x3f, 0x19, 0x57, 0xd1, 0xf6, 0xcc, 0x72, 0xbc, 0x5a, 0xfd, 0x15, 0x57, 0xd0, 0x0b,
- 0x79, 0xfb, 0x14, 0x3e, 0x67, 0x19, 0x9f, 0xec, 0x07, 0xe2, 0x48, 0x51, 0x1d, 0x4d, 0x70, 0xfa,
- 0x0d, 0xe5, 0xa7, 0x9c, 0x05, 0x8a, 0x81, 0x7d, 0x94, 0x0d, 0x96, 0x69, 0xf7, 0xc7, 0x7c, 0xe1,
- 0x26, 0xf8, 0x58, 0xf5, 0xad, 0x41, 0x36, 0xdd, 0xc2, 0xe6, 0x34, 0xa3, 0x2e, 0x35, 0x2a, 0x80,
- 0x12, 0x3b, 0x71, 0x86, 0xb5, 0x14, 0xc9, 0x38, 0x50, 0x6a, 0xd4, 0xa1, 0x24, 0x8c, 0xe8, 0xa6,
- 0x20, 0x6a, 0xfa, 0x3e, 0xc3, 0x64, 0xc4, 0x02, 0xa3, 0xe8, 0xa3, 0xb8, 0x6a, 0x29, 0xfe, 0x76,
- 0xbb, 0x3e, 0xaa, 0x11, 0xc5, 0x64, 0x76, 0xcc, 0x75, 0xc1, 0xfe, 0xe6, 0x8b, 0xf3, 0x47, 0x80,
- 0x11, 0xf3, 0x69, 0x2b, 0x90, 0x31, 0xb5, 0xc6, 0x85, 0x08, 0xe6, 0xb6, 0x2e, 0xe2, 0x05, 0xf5,
- 0x64, 0xbe, 0x2d, 0xb9, 0xba, 0xcb, 0x84, 0xba, 0x30, 0x5e, 0xb1, 0xbe, 0x59, 0xa7, 0x7e, 0x0d,
- 0x9f, 0xc0, 0xb0, 0x5e, 0x21, 0x3b, 0x18, 0xf2, 0x98, 0x23, 0x78, 0xfd, 0xbd, 0xb8, 0xbf, 0x54,
- 0xaf, 0xe8, 0xe4, 0x40, 0x60, 0xfa, 0x41, 0x65, 0xc2, 0x41, 0x5f, 0x59, 0xd4, 0xef, 0xb1, 0x20,
- 0x0c, 0x5a, 0xf2, 0xa0, 0x90, 0xfc, 0x21, 0xec, 0xa1, 0x78, 0xd4, 0x89, 0xc2, 0x55, 0x55, 0x0c,
- 0x50, 0x65, 0x80, 0x5f, 0x0a, 0x9b, 0xd1, 0xa7, 0xdd, 0xc4, 0x8b, 0x62, 0xe5, 0xfd, 0x80, 0x19,
- 0x33, 0x92, 0x0a, 0xad, 0xac, 0x7d, 0x16, 0xe3, 0xe2, 0xcb, 0xc3, 0x53, 0x66, 0x94, 0xe1, 0xbe,
- 0x84, 0xd1, 0xcd, 0xbf, 0x21, 0x8b, 0x83, 0x44, 0xde, 0xa6, 0x73, 0x45, 0x40, 0xf6, 0x63, 0xc7,
- 0x07, 0x20, 0x35, 0x98, 0xc2, 0x03, 0x2d, 0xd7, 0xdd, 0xb8, 0xe6, 0x77, 0x37, 0xfb, 0x00, 0x18,
- 0x47, 0x0b, 0x22, 0xaa, 0x1e, 0x97, 0x5c, 0x57, 0x44, 0xa5, 0x86, 0xb5, 0x0f, 0xdc, 0x2c, 0x17,
- 0x37, 0xbe, 0x8c, 0x55, 0x5c, 0x09, 0x4b, 0xa5, 0x82, 0xce, 0x2f, 0xd4, 0xa9, 0x1b, 0x87, 0x85,
- 0x36, 0xde, 0x43, 0x4d, 0xab, 0xc8, 0xa7, 0xc6, 0x13, 0xe0, 0xbe, 0x56, 0x6e, 0xeb, 0xa9, 0xeb,
- 0xad, 0x39, 0x8b, 0x46, 0x4a, 0xc3, 0xa7, 0xe3, 0x6f, 0xca, 0x48, 0x2c, 0x9d, 0x33, 0x49, 0xc3,
- 0xf6, 0xc9, 0x50, 0xc4, 0x85, 0x6a, 0x0f, 0x07, 0x3d, 0x65, 0x1c, 0x36, 0xe9, 0x3a, 0x68, 0x79,
- 0x53, 0x41, 0xc0, 0x28, 0x04, 0x34, 0x03, 0xbc, 0x56, 0xe6, 0x7e, 0x8b, 0x98, 0x15, 0xb8, 0x21,
- 0x55, 0x39, 0x79, 0x44, 0xb9, 0x39, 0x9e, 0x7a, 0xd6, 0xde, 0x70, 0x59, 0xe4, 0x5f, 0x54, 0x14,
- 0xae, 0x3c, 0xd5, 0x59, 0x28, 0x21, 0x71, 0xa4, 0xa0, 0xc7, 0xf5, 0x09, 0xa0, 0xa2, 0x5f, 0x88,
- 0x56, 0xe7, 0xb5, 0x10, 0x4d, 0xf5, 0x9d, 0x27, 0xb0, 0x45, 0x91, 0x6c, 0x85, 0x41, 0xc6, 0x05,
- 0x5e, 0x90, 0x58, 0x65, 0x6b, 0x3b, 0x8a, 0x44, 0xff, 0xdd, 0xeb, 0x1b, 0xb7, 0xfd, 0x0c, 0xef,
- 0x7d, 0x19, 0xc8, 0x13, 0x0b, 0x5c, 0x93, 0x73, 0x8a, 0x7e, 0x5a, 0x1f, 0x87, 0x37, 0x36, 0xd2,
- 0xc5, 0x1f, 0xfb, 0xc9, 0x7c, 0x15, 0xf5, 0xc9, 0x5e, 0xec, 0x14, 0x07, 0xcf, 0x9b, 0xd4, 0x99,
- 0xa8, 0x48, 0xa1, 0xf1, 0xbe, 0xc6, 0xdd, 0xde, 0x94, 0x38, 0x2a, 0xfe, 0x1a, 0xf0, 0x43, 0x9d,
- 0x14, 0x98, 0x8c, 0xec, 0xc1, 0xd2, 0x09, 0xab, 0xc2, 0xd1, 0x16, 0x7c, 0xe7, 0xf5, 0x63, 0x09,
- 0xb5, 0xdc, 0x4e, 0xea, 0x22, 0xff, 0xd2, 0x16, 0x02, 0x66, 0x12, 0x54, 0x74, 0xe5, 0x51, 0xa0,
- 0xc8, 0x66, 0x80, 0x0b, 0x6f, 0x0a, 0x03, 0x5a, 0x01, 0xd8, 0xf1, 0x4e, 0xf1, 0x5e, 0xff, 0x42,
- 0x2e, 0x6d, 0x30, 0x59, 0x5a, 0x66, 0xe0, 0x8f, 0xb2, 0x98, 0x97, 0x48, 0x55, 0x0a, 0x65, 0x7d,
- 0xdd, 0x2b, 0x1d, 0xcb, 0x7b, 0x5b, 0x06, 0x0c, 0xfe, 0xf3, 0x41, 0x2f, 0x2d, 0xa5, 0xc6, 0xc0,
- 0xf4, 0xdb, 0xb0, 0xe1, 0xe1, 0xed, 0xbe, 0x20, 0x48, 0xdb, 0x97, 0x69, 0x2b, 0x10, 0x24, 0x77,
- 0x66, 0x65, 0xeb, 0x91, 0x85, 0xc6, 0x23, 0xcf, 0xbc, 0xb7, 0x2c, 0x6a, 0x9d, 0x68, 0xce, 0xa7,
- 0x47, 0x09, 0x48, 0xa4, 0xc3, 0xec, 0x33, 0x91, 0xf6, 0x8e, 0x65, 0x25, 0xe8, 0x2f, 0xa9, 0xeb,
- 0xf8, 0x3b, 0x12, 0xdd, 0xaa, 0x27, 0x5e, 0x40, 0xa8, 0x6f, 0xc4, 0xf4, 0x97, 0x50, 0xbf, 0xd2,
- 0xc0, 0x37, 0x73, 0xdb, 0x01, 0x87, 0x03, 0xc3, 0x50, 0x85, 0x60, 0xae, 0x52, 0x8c, 0xf2, 0x7b,
- 0xe8, 0x3b, 0x63, 0xc0, 0x62, 0x62, 0x23, 0x24, 0xb9, 0xe8, 0x9a, 0xd7, 0xb5, 0xd9, 0x0c, 0x1e,
- 0x0d, 0xf1, 0xdd, 0xb6, 0xf1, 0xde, 0x1e, 0x79, 0xa7, 0xf1, 0xfb, 0x94, 0xb3, 0x6e, 0x96, 0x8c,
- 0x6d, 0xdd, 0x05, 0x0c, 0xa3, 0xc6, 0xce, 0x52, 0xe8, 0x55, 0x4a, 0xef, 0x6b, 0x00, 0x96, 0x13,
- 0x8a, 0x2c, 0xfe, 0xab, 0x4f, 0xed, 0xb3, 0x64, 0xd6, 0x72, 0x54, 0x36, 0x2f, 0x85, 0xb6, 0x8b,
- 0xfd, 0x91, 0x37, 0xec, 0x72, 0xb1, 0xf0, 0xe6, 0xc1, 0x21, 0x3d, 0x1c, 0x45, 0x05, 0x37, 0x9f,
- 0xbe, 0x2d, 0x32, 0xfa, 0x30, 0xa9, 0x1d, 0x02, 0x14, 0xe4, 0x94, 0xaa, 0x61, 0x32, 0x23, 0x2a,
- 0x47, 0x01, 0xba, 0x7c, 0x80, 0x80, 0xaa, 0xfa, 0xa8, 0xaf, 0xba, 0xfe, 0xdc, 0x3d, 0x75, 0x85,
- 0x49, 0x34, 0x04, 0x13, 0xbf, 0xfa, 0x87, 0x2e, 0x17, 0x48, 0xef, 0xcb, 0xc9, 0x63, 0xad, 0xae,
- 0x97, 0xb9, 0x2e, 0x9d, 0x4a, 0xcc, 0x3f, 0x10, 0x8a, 0x9e, 0x62, 0x5a, 0x9f, 0x3c, 0x52, 0x5d,
- 0xf0, 0xa9, 0xb9, 0x64, 0x4c, 0xad, 0x4d, 0x12, 0x99, 0xb7, 0x30, 0x8a, 0x59, 0xb8, 0xff, 0xcd,
- 0x96, 0xc1, 0x0d, 0x22, 0xef, 0xd1, 0x45, 0xa5, 0x95, 0x5d, 0x24, 0x15, 0x59, 0x28, 0x09, 0xfe,
- 0x9b, 0xa7, 0x5c, 0x10, 0x23, 0x75, 0x57, 0xcc, 0x12, 0x69, 0xc2, 0x89, 0x9b, 0xac, 0x01, 0x8b,
- 0x20, 0x24, 0x77, 0x7c, 0x74, 0x6d, 0x7e, 0x34, 0x9c, 0x6b, 0xf8, 0x39, 0x2f, 0x8f, 0x16, 0x85,
- 0x84, 0xa5, 0x43, 0x90, 0xe2, 0xd2, 0x89, 0x1e, 0xa4, 0x3a, 0x27, 0x8f, 0xfc, 0xe2, 0x00, 0xbd,
- 0x12, 0x66, 0x63, 0x65, 0x85, 0xc2, 0x79, 0x4a, 0xf6, 0xb2, 0xbb, 0x45, 0x1e, 0x6e, 0xe8, 0x09,
- 0x91, 0xe4, 0x68, 0x5d, 0x2a, 0x0e, 0xc4, 0xab, 0x31, 0x99, 0xf2, 0x68, 0x01, 0x0a, 0x18, 0xab,
- 0xb4, 0x3a, 0xb5, 0x3e, 0x4c, 0xb8, 0x87, 0x9c, 0xff, 0xa5, 0x35, 0xfd, 0x5b, 0xf0, 0x17, 0xc1,
- 0x58, 0xff, 0xfe, 0xcb, 0x54, 0x72, 0x4f, 0xdc, 0xbf, 0xd8, 0x14, 0x6d, 0xfb, 0x7f, 0xbc, 0xd9,
- 0xc3, 0x7b, 0x87, 0x55, 0x7a, 0x1f, 0x71, 0xae, 0xe7, 0xd9, 0x17, 0xc3, 0x34, 0x49, 0x82, 0x92,
- 0x25, 0xd2, 0xce, 0xba, 0x17, 0x98, 0x48, 0x9e, 0x04, 0x4c, 0x67, 0xb1, 0xfa, 0x3d, 0xe5, 0x8d,
- 0xa1, 0x08, 0x79, 0x7c, 0xd0, 0x22, 0x57, 0xc4, 0x16, 0x11, 0xd3, 0xb1, 0xe4, 0xac, 0x7d, 0x38,
- 0xee, 0x3a, 0xf2, 0x47, 0x6b, 0xf9, 0x7f, 0x88, 0xbe, 0x86, 0x10, 0x6f, 0x19, 0x52, 0x86, 0x7c,
- 0x25, 0xbc, 0x13, 0x4f, 0x02, 0x30, 0x85, 0xca, 0x2b, 0x62, 0x41, 0x7e, 0xd3, 0x69, 0x76, 0x9f,
- 0xb6, 0x17, 0x68, 0x36, 0xd3, 0x87, 0x59, 0x9d, 0x8c, 0x62, 0xa9, 0x4b, 0x0c, 0x68, 0x76, 0xaf,
- 0xc1, 0x0e, 0xb9, 0x36, 0xea, 0x4f, 0xd1, 0x29, 0x68, 0xfc, 0x55, 0x7b, 0xac, 0x35, 0xb3, 0xff,
- 0xa3, 0xcd, 0x5e, 0xf4, 0x63, 0x9c, 0x51, 0x92, 0x66, 0x9b, 0x45, 0xf0, 0x5f, 0xce, 0x9f, 0x63,
- 0x04, 0x42, 0x1c, 0x07, 0x6f, 0xa7, 0x6e, 0xbf, 0xd6, 0xd1, 0x96, 0x74, 0x76, 0x8d, 0x82, 0xb1,
- 0x2b, 0x50, 0xcd, 0xfa, 0x3b, 0x16, 0x9a, 0xf6, 0x92, 0xb5, 0xa2, 0x6f, 0x95, 0x87, 0xf0, 0xc7,
- 0x07, 0x0d, 0x75, 0x0c, 0x21, 0x94, 0xf5, 0x6a, 0x3a, 0x7f, 0xc1, 0xcd, 0x1a, 0x10, 0x1c, 0x94,
- 0x18, 0x02, 0x4c, 0xa5, 0x17, 0x1e, 0x26, 0x1c, 0x38, 0x02, 0x5d, 0x5a, 0xd7, 0x9b, 0xf2, 0xfd,
- 0x49, 0x09, 0x64, 0xf5, 0x27, 0x66, 0x06, 0x75, 0x59, 0x66, 0xf2, 0xc5, 0xf3, 0xdb, 0x25, 0x16,
- 0x05, 0x6d, 0xc2, 0xf7, 0xbb, 0x27, 0xa2, 0x20, 0x40, 0x9e, 0x0d, 0xe8, 0x30, 0x9c, 0xfb, 0xff,
- 0xc2, 0xee, 0xc1, 0x13, 0x18, 0x8a, 0x57, 0x3b, 0x8f, 0x36, 0xc8, 0x56, 0xfe, 0xfb, 0x79, 0x3b,
- 0x3d, 0xbf, 0x21, 0x89, 0x7f, 0x8e, 0xcd, 0xdd, 0x25, 0x1f, 0x82, 0xca, 0x36, 0x9a, 0x17, 0x60,
- 0xb1, 0x12, 0xd3, 0x12, 0x0b, 0x9d, 0x29, 0xcf, 0x2c, 0xe5, 0xa6, 0xe5, 0xbe, 0xe2, 0xba, 0x0b,
- 0xc2, 0x05, 0x30, 0xa6, 0x25, 0x25, 0xa1, 0xfa, 0xff, 0x50, 0xae, 0x1a, 0xed, 0x57, 0xc6, 0x48,
- 0x1f, 0x60, 0x76, 0xe9, 0xfc, 0x95, 0xbb, 0x4e, 0xea, 0x6d, 0xeb, 0xf7, 0xb9, 0x9e, 0x55, 0x3d,
- 0xad, 0x27, 0x11, 0x55, 0x71, 0xc7, 0x5f, 0x29, 0xc8, 0xbf, 0x9d, 0xcb, 0x66, 0x4f, 0xc3, 0x8a,
- 0x9b, 0x9d, 0x4e, 0x45, 0x00, 0x7d, 0x6c, 0xf8, 0xb9, 0x53, 0x23, 0x7a, 0x28, 0xaf, 0x7c, 0x7a,
- 0xcf, 0x40, 0xf7, 0x90, 0xeb, 0x8c, 0x5b, 0x62, 0x0a, 0x63, 0x31, 0xa0, 0x1e, 0x42, 0xf2, 0x9c,
- 0xa6, 0x87, 0x68, 0x8d, 0xad, 0x77, 0x6f, 0xed, 0x11, 0x5e, 0x94, 0x09, 0x30, 0x78, 0x4c, 0xae,
- 0x8c, 0xdf, 0xda, 0x48, 0xd3, 0x2e, 0x61, 0x90, 0x77, 0x33, 0xe8, 0x78, 0xa4, 0xdd, 0x3b, 0x73,
- 0xd7, 0xc6, 0xb3, 0xbc, 0x9d, 0x72, 0x8d, 0x2d, 0xec, 0x46, 0x1f, 0x4e, 0xe3, 0xc3, 0x69, 0x0e,
- 0x67, 0xe3, 0x04, 0x55, 0x3b, 0xb0, 0x7e, 0xb3, 0x68, 0x67, 0x3f, 0x2e, 0xd8, 0xee, 0x40, 0xfd,
- 0xbc, 0x77, 0xd8, 0x83, 0xa5, 0x9d, 0xde, 0xd8, 0x93, 0x89, 0x22, 0xdb, 0x05, 0x01, 0x1d, 0x14,
- 0x71, 0x84, 0xed, 0x8f, 0x36, 0x14, 0x12, 0x6f, 0xfa, 0x89, 0x60, 0x79, 0x73, 0x0c, 0xaa, 0x49,
- 0x29, 0xce, 0xb9, 0x76, 0x53, 0x6d, 0xe0, 0x0a, 0xe2, 0x36, 0xc2, 0xb7, 0x4b, 0x82, 0x9f, 0xce,
- 0x81, 0xb5, 0xc4, 0xf1, 0xd4, 0x58, 0x42, 0x5f, 0xb4, 0xcc, 0x24, 0xcd, 0x18, 0x3c, 0x66, 0xf1,
- 0xab, 0x68, 0x6d, 0x36, 0xed, 0x32, 0x40, 0xa2, 0x07, 0x7a, 0x7e, 0x45, 0x53, 0x6c, 0xcb, 0x27,
- 0xd4, 0x81, 0x36, 0x1b, 0x4b, 0x00, 0x7d, 0x1f, 0xf3, 0xb0, 0x79, 0xc6, 0x48, 0xdd, 0x6c, 0x6a,
- 0xd3, 0x9f, 0xf4, 0xad, 0xc4, 0xcd, 0x45, 0xa7, 0xaf, 0xdc, 0x13, 0x66, 0xe2, 0xaf, 0xca, 0xa3,
- 0x42, 0x5c, 0xbf, 0x08, 0x79, 0x20, 0x07, 0xc5, 0xd6, 0x82, 0x34, 0x39, 0x2c, 0xe3, 0xd3, 0x8d,
- 0x12, 0x1d, 0x9f, 0x98, 0xe8, 0x1a, 0xcc, 0x0d, 0xbf, 0xc5, 0x2f, 0x62, 0xbb, 0x0e, 0x23, 0x50,
- 0x92, 0x92, 0xf0, 0xce, 0x70, 0x5d, 0x51, 0x38, 0x2c, 0x9c, 0xc8, 0xc0, 0xbb, 0xa4, 0x9b, 0x81,
- 0x83, 0xa9, 0x32, 0xe7, 0x3a, 0x47, 0x2a, 0xd3, 0xbc, 0x09, 0xd4, 0x5a, 0x1f, 0xf1, 0x72, 0xb8,
- 0xaf, 0xba, 0x24, 0x2f, 0x25, 0xd9, 0xc0, 0x76, 0xe1, 0xee, 0x7d, 0x7f, 0x60, 0x42, 0xfc, 0xec,
- 0xe3, 0x32, 0x13, 0x46, 0x7e, 0x5c, 0x8e, 0xa1, 0x46, 0xe8, 0x93, 0x14, 0xd7, 0x90, 0xf9, 0x80,
- 0xfa, 0x4f, 0xd7, 0x03, 0x0d, 0x97, 0x22, 0xc0, 0x6b, 0xbd, 0x97, 0xb3, 0x0e, 0xf4, 0xc5, 0x92,
- 0x42, 0x6b, 0x1b, 0xeb, 0xdc, 0x13, 0x13, 0x01, 0x42, 0x1c, 0xf0, 0x88, 0x31, 0x2c, 0x42, 0x59,
- 0x67, 0x7e, 0xff, 0x77, 0xab, 0xc1, 0x47, 0x50, 0x51, 0x64, 0x7d, 0x8f, 0xec, 0x68, 0xcc, 0x34,
- 0x76, 0xbf, 0x65, 0x89, 0x9c, 0x18, 0x7b, 0x21, 0x86, 0xbf, 0x3d, 0x79, 0xae, 0x6f, 0xc2, 0x12,
- 0x21, 0x3a, 0x95, 0x62, 0x65, 0xc9, 0xcc, 0xee, 0x08, 0x3a, 0xaf, 0xe9, 0x31, 0xe5, 0x6a, 0xa2,
- 0x27, 0x30, 0x34, 0x7b, 0x04, 0xf0, 0xe7, 0xd5, 0x14, 0x95, 0xd5, 0xbc, 0x05, 0x94, 0x4e, 0xb9,
- 0xa9, 0x1d, 0x10, 0x20, 0xe9, 0xbd, 0xf8, 0x44, 0xbe, 0x95, 0xb0, 0x2b, 0x9e, 0x3c, 0xd2, 0x5c,
- 0x47, 0x89, 0x0a, 0xee, 0xa9, 0xb8, 0xc9, 0xb5, 0x3f, 0x19, 0xf5, 0xf8, 0x33, 0x18, 0x9d, 0xa9,
- 0x01, 0xcf, 0xdc, 0xa2, 0x6c, 0x85, 0xde, 0x19, 0x24, 0xdd, 0x36, 0x19, 0x1a, 0x54, 0x9f, 0x52,
- 0xd3, 0xf8, 0xf5, 0x88, 0x73, 0x9f, 0xf7, 0x98, 0xa6, 0x41, 0x0d, 0xe0, 0xfe, 0xf8, 0x18, 0xb2,
- 0xe9, 0x2a, 0x60, 0x0e, 0xf3, 0xbe, 0x56, 0x8b, 0xee, 0x17, 0x8e, 0x56, 0x5e, 0x62, 0x7d, 0xb6,
- 0x18, 0x95, 0xba, 0xb5, 0xb3, 0x0e, 0x1c, 0x1b, 0x28, 0xb8, 0x8d, 0x0c, 0x63, 0x14, 0x37, 0x41,
- 0xa2, 0xe7, 0xf6, 0x63, 0x2e, 0xf8, 0x6c, 0x63, 0x45, 0xfc, 0x95, 0xb0, 0x90, 0xd3, 0x1e, 0x4f,
- 0x58, 0xfd, 0x40, 0xad, 0x6a, 0x1a, 0x82, 0x4c, 0x57, 0xae, 0x10, 0x69, 0x1f, 0xe0, 0xca, 0x67,
- 0x53, 0x6b, 0xb4, 0x8c, 0x5c, 0x67, 0x4b, 0x1d, 0x2f, 0x24, 0x50, 0xbd, 0xa8, 0xf3, 0x50, 0x23,
- 0xd2, 0xab, 0x48, 0x8f, 0x87, 0x01, 0xc0, 0x2d, 0x4d, 0x67, 0xee, 0x31, 0x87, 0x29, 0xd1, 0xd5,
- 0x49, 0x29, 0x86, 0x2b, 0x07, 0x05, 0xaa, 0x88, 0x15, 0xbc, 0xb0, 0x70, 0x0f, 0x75, 0x90, 0x35,
- 0xde, 0x09, 0x43, 0xe5, 0xa1, 0x11, 0x53, 0x60, 0x4f, 0x46, 0x1a, 0x58, 0xf1, 0x9f, 0x56, 0xef,
- 0x2e, 0xb8, 0x4a, 0xce, 0x4a, 0x86, 0x22, 0x59, 0x99, 0x4c, 0x81, 0xfd, 0x67, 0xf1, 0x19, 0xc4,
- 0xb3, 0x82, 0xd7, 0xd5, 0x6b, 0xc2, 0xe3, 0xbc, 0x1b, 0x84, 0x91, 0x09, 0x9f, 0x17, 0x85, 0x5c,
- 0xb4, 0x4d, 0x4f, 0x43, 0x0c, 0xae, 0x49, 0x98, 0xa4, 0x94, 0xf9, 0x63, 0x77, 0x16, 0x71, 0xc6,
- 0xc5, 0x74, 0xdc, 0xb9, 0xd2, 0x63, 0x64, 0x4c, 0xb4, 0x96, 0x44, 0x0b, 0x9a, 0x43, 0xb7, 0x74,
- 0xf6, 0xe3, 0x37, 0x2d, 0xc9, 0x93, 0xcd, 0x5a, 0x6e, 0x47, 0xd2, 0xed, 0x9b, 0x39, 0x06, 0xc7,
- 0xde, 0x49, 0xa8, 0x66, 0x0f, 0x54, 0xac, 0x57, 0xb6, 0xe5, 0x92, 0x81, 0xb1, 0xb0, 0x8c, 0xd5,
- 0xe5, 0x7b, 0x61, 0x1b, 0x2b, 0x63, 0xdd, 0x55, 0xe5, 0x6e, 0xa2, 0x60, 0xf5, 0x80, 0x15, 0x87,
- 0xd6, 0x78, 0x6c, 0x70, 0x69, 0x23, 0x6b, 0x34, 0x3f, 0x6c, 0x4a, 0x52, 0xe1, 0x59, 0xeb, 0x95,
- 0x2a, 0x75, 0x4f, 0x06, 0x15, 0x7f, 0xb6, 0x20, 0x81, 0xdf, 0x93, 0x7d, 0x37, 0x59, 0xd7, 0x9d,
- 0x6d, 0x1b, 0x00, 0x0b, 0x69, 0x92, 0x47, 0xe0, 0xde, 0xab, 0xaa, 0xa1, 0x54, 0x03, 0x50, 0xfa,
- 0x5c, 0xb3, 0xfb, 0xcf, 0xfb, 0xad, 0x5c, 0xfd, 0xd6, 0xfd, 0x73, 0x9b, 0x25, 0x77, 0xae, 0x5e,
- 0x75, 0x5a, 0xbd, 0xb4, 0x7c, 0xa9, 0xc4, 0xea, 0x22, 0xd9, 0xc3, 0x53, 0xd9, 0x3c, 0xb3, 0xc3,
- 0x45, 0x58, 0x02, 0x62, 0x3a, 0x79, 0x83, 0xbd, 0x91, 0x78, 0xa5, 0xd9, 0x0c, 0x08, 0x31, 0x55,
- 0x9c, 0x14, 0x89, 0x2f, 0xf4, 0x0d, 0x2c, 0x5c, 0x55, 0xe2, 0x82, 0xb9, 0x66, 0x22, 0xb3, 0xff,
- 0xfd, 0xf2, 0x5f, 0x71, 0xab, 0x47, 0x45, 0xc1, 0xf4, 0x84, 0x2d, 0x6d, 0xcd, 0xc2, 0xa9, 0x38,
- 0x29, 0xf5, 0x3c, 0xb2, 0xef, 0xa7, 0x44, 0x98, 0xb7, 0x84, 0xa0, 0xde, 0xda, 0xa9, 0x99, 0x25,
- 0x83, 0x11, 0x93, 0xcd, 0x2c, 0x5a, 0xa2, 0x9a, 0xff, 0xb0, 0x4a, 0x80, 0x3e, 0x2c, 0x52, 0xf3,
- 0x8f, 0xbd, 0xdd, 0xc5, 0x17, 0xea, 0x6b, 0xb4, 0x75, 0xa7, 0x22, 0xe9, 0xc1, 0xbd, 0x74, 0x80,
- 0x62, 0x6a, 0x55, 0x46, 0x4d, 0xf4, 0x47, 0x5a, 0x25, 0xc2, 0x67, 0x9b, 0xdc, 0xf8, 0x1b, 0xe7,
- 0xff, 0xd1, 0x44, 0xe6, 0xbe, 0x6c, 0xa4, 0x9d, 0xc3, 0x6e, 0x44, 0xfb, 0x54, 0xd5, 0x53, 0xec,
- 0xe4, 0x03, 0x9c, 0x22, 0xa0, 0xa1, 0xd1, 0x1a, 0x6e, 0xa3, 0x10, 0xf9, 0xd0, 0x14, 0xa6, 0x20,
- 0x8c, 0xe0, 0x35, 0x72, 0x92, 0x41, 0x43, 0x83, 0x93, 0x11, 0xec, 0x3d, 0x74, 0x43, 0x4a, 0x92,
- 0xe4, 0x91, 0xb7, 0xf2, 0xed, 0x9a, 0x6f, 0xd4, 0x23, 0x67, 0x07, 0xfb, 0x90, 0xb1, 0xb0, 0x23,
- 0x14, 0x7a, 0x50, 0x48, 0xdf, 0x89, 0x19, 0xa0, 0xdb, 0xf5, 0xff, 0x38, 0xfa, 0x97, 0x6b, 0x7b,
- 0xd3, 0x50, 0x77, 0xcf, 0xce, 0x4e, 0x6d, 0x79, 0x93, 0xc5, 0x49, 0xad, 0x17, 0x55, 0xa6, 0xd4,
- 0x82, 0x7d, 0x17, 0x2d, 0x0b, 0x76, 0x55, 0x90, 0x83, 0x56, 0x72, 0x76, 0xac, 0xe4, 0x24, 0x91,
- 0x4f, 0x85, 0xf7, 0xc7, 0x9d, 0x38, 0xd0, 0x92, 0x30, 0x91, 0x99, 0x25, 0x8a, 0x6c, 0xaa, 0x2d,
- 0xbb, 0x88, 0x30, 0x8c, 0xf2, 0xa6, 0x23, 0x60, 0x89, 0x44, 0x02, 0x1e, 0x18, 0xb4, 0xd9, 0xab,
- 0x4b, 0xa4, 0x57, 0xef, 0x49, 0x3c, 0x02, 0xe5, 0x7d, 0x38, 0x36, 0x49, 0x5b, 0xcd, 0x2d, 0x6f,
- 0x9d, 0x90, 0x63, 0xe0, 0x56, 0xa6, 0x9a, 0xf9, 0xf8, 0x65, 0xc1, 0x88, 0x8d, 0x43, 0x5b, 0xe0,
- 0xc2, 0x90, 0xaa, 0x22, 0xd2, 0x40, 0xe2, 0x94, 0x2d, 0x48, 0x75, 0xcb, 0x67, 0x84, 0xa5, 0xe1,
- 0xc3, 0x08, 0x30, 0xfa, 0xd7, 0xfd, 0x27, 0x9c, 0xb1, 0x03, 0x0f, 0x58, 0x15, 0x5a, 0x15, 0x4a,
- 0xa8, 0x48, 0x23, 0x74, 0xec, 0xc4, 0xe9, 0x83, 0xa6, 0xc3, 0x82, 0x7a, 0x0f, 0x2c, 0x17, 0x93,
- 0x14, 0x21, 0x03, 0xc2, 0xba, 0x4f, 0x47, 0xae, 0x53, 0xa7, 0x54, 0x53, 0xed, 0x79, 0xe0, 0x05,
- 0xa3, 0x27, 0xf8, 0xae, 0x99, 0xd5, 0x03, 0x01, 0x86, 0x92, 0xab, 0x03, 0xc2, 0x6a, 0xc3, 0xe8,
- 0x15, 0xc8, 0x40, 0x7b, 0x11, 0xc7, 0x89, 0xb5, 0x6d, 0x4d, 0x22, 0x61, 0x2d, 0x5a, 0x12, 0x5a,
- 0x48, 0x28, 0x0e, 0xeb, 0x5e, 0xde, 0x8b, 0x3f, 0x52, 0xb0, 0xeb, 0x8c, 0x0b, 0x83, 0x9e, 0x56,
- 0x6e, 0x66, 0xa4, 0xc7, 0xc1, 0x7c, 0x02, 0x85, 0x16, 0xe0, 0x64, 0x88, 0x04, 0x5a, 0xaa, 0xfb,
- 0xb3, 0xc1, 0xf7, 0x7d, 0x41, 0xc3, 0xf6, 0x00, 0x56, 0x61, 0xb8, 0xe7, 0xb5, 0x01, 0x05, 0x1d,
- 0x51, 0x99, 0x1d, 0xd9, 0x63, 0x24, 0x05, 0x4e, 0xfe, 0xe0, 0x26, 0xbb, 0xd6, 0xbb, 0x88, 0x33,
- 0x31, 0x20, 0x6d, 0x97, 0x69, 0x31, 0x5e, 0x03, 0xac, 0x13, 0x39, 0xa8, 0x5b, 0x18, 0x9b, 0x18,
- 0xbe, 0xf1, 0x54, 0x7d, 0xff, 0xa3, 0x61, 0xb3, 0x0c, 0x12, 0xf8, 0xde, 0xad, 0x3f, 0x50, 0xd1,
- 0xfc, 0x24, 0x94, 0x8a, 0x7e, 0xbd, 0xe5, 0xbe, 0x03, 0x74, 0xfb, 0xe5, 0xbb, 0x40, 0xcd, 0x09,
- 0xe2, 0x25, 0x30, 0xac, 0x2f, 0xc0, 0x73, 0x3a, 0x26, 0x5a, 0xbc, 0x3f, 0xc0, 0x90, 0xff, 0xc0,
- 0xe0, 0x14, 0xc5, 0x30, 0x1f, 0x21, 0x33, 0x77, 0xa6, 0xe5, 0xd3, 0x24, 0xca, 0xe4, 0x95, 0x01,
- 0x42, 0xa7, 0x7c, 0xe1, 0x8e, 0xd6, 0x6c, 0x00, 0xea, 0x5c, 0x83, 0x62, 0xb6, 0x19, 0xb6, 0xbf,
- 0x0a, 0xeb, 0x79, 0x15, 0x5a, 0x32, 0xa1, 0xa3, 0x76, 0xc2, 0x03, 0x28, 0xb7, 0x48, 0xc8, 0x25,
- 0xaa, 0xc5, 0x78, 0x93, 0x1f, 0x94, 0x6c, 0xdd, 0xca, 0x34, 0xf4, 0xee, 0xa4, 0xb1, 0x90, 0x66,
- 0xc9, 0x5f, 0xf0, 0x1c, 0x0e, 0x25, 0x72, 0x94, 0xa0, 0xa6, 0x66, 0x43, 0x01, 0xd4, 0x10, 0xe1,
- 0x07, 0x17, 0x9d, 0x51, 0xf0, 0xbd, 0xd8, 0x89, 0x33, 0xd5, 0xb3, 0x8c, 0xfd, 0x77, 0x8c, 0xc9,
- 0xa0, 0x8f, 0x7a, 0x07, 0x34, 0x3a, 0xfc, 0x86, 0x0f, 0x37, 0x03, 0x39, 0x2a, 0x5c, 0x0b, 0x69,
- 0x3c, 0xd6, 0xce, 0x88, 0x50, 0xe2, 0x20, 0x2e, 0x1e, 0xea, 0x66, 0x9d, 0xdf, 0x5a, 0xd2, 0x6a,
- 0xcb, 0x3d, 0xf9, 0xda, 0x58, 0x8e, 0xaf, 0x73, 0x3a, 0xd5, 0x6f, 0x7b, 0x9a, 0x44, 0x8b, 0xde,
- 0x92, 0xa4, 0x08, 0xf1, 0xae, 0xb1, 0x7c, 0xa9, 0x42, 0x2f, 0xc1, 0x83, 0x07, 0x9b, 0x0f, 0x65,
- 0xaf, 0x3e, 0x33, 0xbe, 0xf4, 0x21, 0x5d, 0xf8, 0x3c, 0x50, 0x1d, 0xe8, 0x9f, 0x43, 0xa1, 0x79,
- 0x11, 0x19, 0x8c, 0x48, 0xf7, 0xe2, 0x9d, 0x72, 0x73, 0xfc, 0x95, 0x12, 0x0f, 0x37, 0x5e, 0x7a,
- 0x71, 0xa0, 0xa0, 0x0e, 0x6a, 0x16, 0xfd, 0xbf, 0xa3, 0x63, 0x4a, 0x46, 0xa9, 0xe9, 0xb7, 0x8a,
- 0x00, 0xbd, 0x14, 0xe7, 0x39, 0x08, 0xe0, 0x24, 0xe5, 0x66, 0xd7, 0xa3, 0x95, 0xbf, 0x34, 0x08,
- 0x06, 0x57, 0x55, 0x9e, 0xd3, 0x21, 0x39, 0xe5, 0xe1, 0x0e, 0x6e, 0xa0, 0x83, 0x5e, 0xa7, 0x83,
- 0xf7, 0x38, 0x19, 0x15, 0xd3, 0xfe, 0x69, 0xb7, 0x8e, 0x52, 0x0b, 0x06, 0xf3, 0xf4, 0xa7, 0x21,
- 0x8a, 0x6c, 0x79, 0x4d, 0x56, 0x50, 0xed, 0xc0, 0xce, 0xda, 0xf0, 0xdf, 0xb7, 0x88, 0x53, 0x47,
- 0xda, 0x4b, 0x20, 0x2e, 0xf8, 0xc9, 0xb7, 0xf2, 0x38, 0x44, 0x7a, 0x52, 0x23, 0x80, 0x4f, 0x50,
- 0x83, 0x05, 0x63, 0xcd, 0xad, 0x0d, 0x1e, 0xa2, 0x22, 0xe4, 0xf3, 0x16, 0xfc, 0x6e, 0x85, 0x52,
- 0x46, 0x37, 0xd2, 0x52, 0xb3, 0x50, 0x4b, 0x27, 0x74, 0xe4, 0xb0, 0xac, 0x18, 0xdd, 0x4b, 0x30,
- 0x20, 0x0b, 0x20, 0x12, 0x2b, 0x45, 0xd7, 0xf8, 0xa8, 0xba, 0x65, 0x21, 0x81, 0x4e, 0x82, 0xc1,
- 0xa1, 0x6c, 0xad, 0x92, 0x2c, 0x5d, 0x10, 0xd6, 0x9d, 0xa3, 0x7d, 0x08, 0x7e, 0xd9, 0x14, 0xaa,
- 0x90, 0x5e, 0x8f, 0xd4, 0xcd, 0x51, 0xd9, 0xa6, 0x61, 0x58, 0x0c, 0x21, 0xd2, 0x5e, 0x17, 0x10,
- 0xe7, 0x2a, 0x1f, 0xa4, 0x63, 0x1d, 0x0f, 0xec, 0xc5, 0x76, 0x93, 0x36, 0x47, 0x31, 0x45, 0x3b,
- 0x87, 0x65, 0x9d, 0xee, 0x26, 0x4e, 0x42, 0x97, 0x74, 0x00, 0x9e, 0x26, 0x95, 0x64, 0x19, 0x2b,
- 0x3b, 0x14, 0x18, 0xeb, 0xd7, 0xfc, 0x20, 0x21, 0xcf, 0x1b, 0x25, 0xa7, 0x89, 0xfb, 0x7c, 0xeb,
- 0x91, 0xfd, 0xe7, 0x77, 0x6e, 0x4a, 0xa4, 0xb6, 0x4c, 0xe5, 0x9f, 0x3e, 0x46, 0x28, 0x41, 0x58,
- 0xab, 0x82, 0x12, 0x61, 0x75, 0x74, 0xb1, 0x6a, 0xbd, 0xeb, 0x3f, 0x56, 0x24, 0x83, 0xc9, 0x6c,
- 0x30, 0x1f, 0xd2, 0x78, 0x22, 0xb6, 0x16, 0xb6, 0x59, 0xaf, 0xee, 0xc3, 0x3a, 0x77, 0xfb, 0xe0,
- 0x40, 0x3d, 0x33, 0xcf, 0x39, 0x43, 0xa0, 0x6e, 0xb7, 0xa5, 0x85, 0xf7, 0xaa, 0xfa, 0x25, 0xea,
- 0x7c, 0x6c, 0xf7, 0xfd, 0x87, 0x11, 0xb1, 0x69, 0x1e, 0xa9, 0x92, 0x28, 0x73, 0x82, 0xf8, 0xa9,
- 0x26, 0x6f, 0x45, 0x31, 0x11, 0x49, 0x36, 0xb5, 0x35, 0x16, 0x40, 0x37, 0xb4, 0xe3, 0xf9, 0x8e,
- 0x8c, 0x32, 0x92, 0x2b, 0xef, 0x9c, 0xb0, 0xd1, 0x57, 0xea, 0xbe, 0xf0, 0xb1, 0x73, 0xb1, 0xad,
- 0xe6, 0x42, 0xb6, 0xed, 0xf2, 0x04, 0x07, 0xa2, 0x49, 0xf8, 0x73, 0x88, 0x2d, 0x99, 0x8c, 0x24,
- 0xb7, 0xd1, 0x10, 0xf8, 0xe4, 0xbf, 0xb6, 0x12, 0x07, 0xf9, 0xad, 0x2c, 0xb1, 0x82, 0xc5, 0xe6,
- 0x83, 0x22, 0xa6, 0xce, 0xbd, 0xb0, 0xb0, 0xf1, 0x79, 0x83, 0xc9, 0xaa, 0xa0, 0xc2, 0x69, 0x7f,
- 0x51, 0xfd, 0xc6, 0x17, 0xfe, 0x96, 0x9f, 0x1f, 0xce, 0x83, 0xfe, 0xd6, 0x68, 0x9e, 0x0c, 0xbb,
- 0x1c, 0x9f, 0x40, 0x97, 0x03, 0x88, 0x8c, 0x2c, 0xa7, 0x4a, 0xb6, 0xef, 0xb9, 0xe0, 0x59, 0xc6,
- 0x1e, 0x98, 0x31, 0x52, 0x22, 0x41, 0xf6, 0xb7, 0x5e, 0x5b, 0x2e, 0xa0, 0xbf, 0x3e, 0x99, 0xaa,
- 0x63, 0x97, 0xa7, 0x0a, 0xc5, 0x14, 0x33, 0x95, 0x01, 0xc1, 0x80, 0x75, 0xd3, 0xe8, 0x27, 0x3c,
- 0xf5, 0x7c, 0x00, 0x46, 0x14, 0x0c, 0xd8, 0x6d, 0x25, 0x20, 0x77, 0x0b, 0xaa, 0xb3, 0xa7, 0xe0,
- 0xe6, 0x88, 0x31, 0x7e, 0xcc, 0x1e, 0xee, 0xe4, 0xbe, 0x66, 0x2a, 0x8a, 0xa7, 0x68, 0x94, 0x4f,
- 0xa2, 0xb8, 0x3c, 0x3d, 0x75, 0x72, 0xf0, 0x8f, 0x94, 0xcf, 0x2c, 0x13, 0xbd, 0x6a, 0x53, 0x57,
- 0xac, 0x4f, 0x0b, 0x3d, 0x9c, 0x15, 0x32, 0x05, 0x7e, 0xfa, 0xf5, 0xb8, 0x53, 0xdb, 0x01, 0x8d,
- 0x35, 0x5a, 0x01, 0x98, 0xca, 0x47, 0x90, 0x51, 0xa8, 0x1a, 0x84, 0xcd, 0x86, 0x81, 0x8e, 0x53,
- 0x40, 0x4d, 0x76, 0xa8, 0xbd, 0x8b, 0x96, 0xd6, 0xb9, 0xc8, 0xd9, 0x71, 0x6f, 0x58, 0x2a, 0x70,
- 0xab, 0x11, 0x84, 0x70, 0x36, 0xc0, 0xc1, 0x5f, 0x2b, 0x2c, 0xa3, 0x5a, 0x32, 0x56, 0x1a, 0xb4,
- 0xdd, 0xaf, 0x4b, 0x6e, 0x4c, 0x4e, 0xa4, 0xdf, 0x2f, 0xdb, 0x0d, 0x01, 0xe0, 0xc7, 0x1c, 0x09,
- 0x78, 0x09, 0xaa, 0x51, 0xf0, 0x0f, 0x08, 0x6b, 0x61, 0x2a, 0x7b, 0x30, 0xa2, 0xf1, 0x26, 0xcc,
- 0xf0, 0x04, 0x38, 0xd1, 0xf5, 0x6c, 0x21, 0xf7, 0x8e, 0x6b, 0xc0, 0xb6, 0x9c, 0x8d, 0xb7, 0x7c,
- 0xff, 0x33, 0x28, 0x48, 0x06, 0x7b, 0x47, 0x05, 0xbb, 0xe2, 0x23, 0xb3, 0x00, 0x72, 0x43, 0xbe,
- 0xbe, 0xee, 0x8d, 0xb7, 0xa5, 0x26, 0x93, 0x61, 0x7a, 0x1f, 0x46, 0x1e, 0x13, 0x76, 0x35, 0x87,
- 0x75, 0x87, 0x7d, 0xe0, 0x71, 0xc1, 0x9b, 0xdc, 0x54, 0x56, 0x3f, 0xa1, 0x47, 0x63, 0xed, 0x08,
- 0x77, 0xe0, 0x6e, 0xbe, 0xe6, 0x83, 0xc0, 0xae, 0x96, 0x0e, 0xcf, 0x61, 0xb2, 0x6f, 0x8b, 0x04,
- 0x24, 0x9f, 0xa8, 0x0a, 0xf2, 0xb2, 0x77, 0x7b, 0x1c, 0xac, 0x97, 0x16, 0x4a, 0x28, 0xdf, 0x3e,
- 0xe9, 0xcb, 0x0d, 0x8a, 0x28, 0x86, 0xf0, 0x33, 0x17, 0x8e, 0x0b, 0xfa, 0x49, 0x4c, 0x84, 0x38,
- 0x3a, 0x05, 0xc2, 0xef, 0xba, 0xe0, 0xec, 0x83, 0xfd, 0x6f, 0x68, 0x60, 0xc8, 0xe6, 0x45, 0xca,
- 0x71, 0x82, 0x7b, 0xc2, 0xa6, 0x08, 0x2d, 0xa0, 0xc4, 0x20, 0x6c, 0x85, 0x74, 0x6f, 0x52, 0xa5,
- 0xcb, 0xaf, 0x01, 0x15, 0xab, 0x5d, 0x4f, 0x1f, 0x1b, 0xe5, 0xe9, 0x07, 0x9a, 0xb6, 0x41, 0xde,
- 0x68, 0xdc, 0x65, 0xaa, 0x7b, 0x93, 0xea, 0xba, 0x60, 0xc4, 0xb6, 0xef, 0x23, 0x6e, 0xb2, 0xa1,
- 0xce, 0xdc, 0xf5, 0xe8, 0xd4, 0x8c, 0x24, 0xdd, 0xda, 0xaa, 0x8c, 0x8c, 0x7b, 0xa9, 0x70, 0xeb,
- 0x8b, 0xb2, 0xe5, 0xc4, 0x66, 0x5f, 0xcf, 0x66, 0x39, 0x6d, 0xfd, 0x64, 0x59, 0x34, 0x5b, 0x6b,
- 0x56, 0xbe, 0x64, 0x89, 0x1e, 0x3c, 0x29, 0x55, 0xcf, 0x28, 0xce, 0x7f, 0xb6, 0xb8, 0xb7, 0x84,
- 0x82, 0x7e, 0xd4, 0xee, 0x67, 0x8f, 0x74, 0xf4, 0x0f, 0x30, 0x11, 0xc1, 0x21, 0xb5, 0x97, 0xcb,
- 0xb0, 0xa6, 0x4e, 0xb1, 0x39, 0x6b, 0xed, 0xb8, 0xb4, 0x1d, 0x9b, 0x88, 0xb4, 0x65, 0x9a, 0x5c,
- 0x55, 0x4e, 0x8d, 0xbd, 0x3e, 0x6a, 0xad, 0x79, 0xae, 0x56, 0x17, 0xfd, 0x6c, 0xdb, 0x95, 0x20,
- 0x90, 0xbc, 0xa0, 0x51, 0x8d, 0x82, 0x83, 0x70, 0x36, 0x94, 0x8f, 0x43, 0x5a, 0x9d, 0xc2, 0xa0,
- 0x08, 0x9a, 0xad, 0xb6, 0x0c, 0x8e, 0xa1, 0x7d, 0x69, 0xfb, 0x36, 0x36, 0xa6, 0x9c, 0x6f, 0xa1,
- 0x14, 0x37, 0xfe, 0xaa, 0xd7, 0xab, 0xd9, 0xeb, 0x8c, 0x2b, 0x86, 0xa8, 0x2f, 0x72, 0x32, 0x3c,
- 0x9a, 0x9b, 0x75, 0x19, 0x64, 0xe4, 0x21, 0xd9, 0xdc, 0xd8, 0x99, 0xf6, 0xdb, 0x1a, 0xe7, 0x7e,
- 0xdf, 0x5b, 0x38, 0x82, 0xe8, 0x6b, 0x3f, 0x3e, 0x56, 0x14, 0x5e, 0x85, 0xce, 0x20, 0xee, 0x05,
- 0x41, 0xa9, 0xb1, 0x09, 0xc0, 0xa9, 0xc2, 0x30, 0xa2, 0x54, 0xd5, 0x76, 0x14, 0xfb, 0x20, 0x8d,
- 0x66, 0xd6, 0x76, 0xa4, 0xa0, 0xe7, 0x92, 0x15, 0xd9, 0x25, 0x73, 0x00, 0x7b, 0x2f, 0xd6, 0x59,
- 0x5d, 0x3a, 0x94, 0xe0, 0x39, 0xe7, 0xe8, 0xbe, 0x2d, 0x3e, 0x30, 0x26, 0x18, 0xb5, 0x95, 0x7a,
- 0x92, 0x55, 0x31, 0x0b, 0x21, 0xc0, 0x92, 0xb3, 0x3e, 0x96, 0x3c, 0xe0, 0x53, 0xe3, 0x9d, 0xcc,
- 0x7b, 0xdc, 0x8e, 0xd1, 0x46, 0xf9, 0x7b, 0x1e, 0x3c, 0x00, 0x48, 0x97, 0x37, 0xef, 0x4d, 0x4a,
- 0x85, 0xdd, 0xab, 0x32, 0xec, 0xe2, 0x60, 0xd0, 0xee, 0x75, 0x02, 0xca, 0xf6, 0xb1, 0x0e, 0x1e,
- 0x9d, 0x6e, 0x20, 0x9f, 0xcd, 0x5e, 0x7f, 0xb1, 0x13, 0x3c, 0x07, 0xd4, 0x0a, 0x43, 0xff, 0x40,
- 0xd2, 0xc5, 0x9b, 0x5b, 0x5e, 0x89, 0x5e, 0x48, 0x28, 0x5b, 0xe0, 0x3a, 0x18, 0x6c, 0x83, 0xa7,
- 0x82, 0x7f, 0xb5, 0xd7, 0xbf, 0xcd, 0x09, 0x70, 0x36, 0xe5, 0xaf, 0x60, 0x0a, 0x98, 0x7c, 0x70,
- 0x7d, 0xac, 0x46, 0xb4, 0x30, 0x19, 0xf1, 0x3c, 0xc7, 0x55, 0xfd, 0x6f, 0x7a, 0x4b, 0xe5, 0x53,
- 0xcf, 0x06, 0x83, 0xca, 0x76, 0x30, 0x86, 0x27, 0x66, 0xf8, 0x3f, 0xea, 0x0e, 0x1d, 0xce, 0x01,
- 0xb3, 0x04, 0x62, 0xb3, 0xb3, 0x3f, 0xfe, 0x5f, 0x8a, 0x03, 0xc9, 0xfd, 0xb9, 0x8f, 0xc4, 0xa6,
- 0x60, 0x6e, 0xd9, 0x64, 0xe1, 0x51, 0x46, 0xb5, 0x09, 0xa3, 0x6a, 0x5c, 0x9e, 0xc2, 0xa4, 0xcc,
- 0xe6, 0xe1, 0x5f, 0xb4, 0x25, 0x1c, 0x19, 0x10, 0x25, 0xb7, 0x57, 0x6a, 0xbd, 0xd1, 0x6e, 0x32,
- 0xc7, 0xe4, 0xb1, 0x38, 0x93, 0x8c, 0x25, 0xfc, 0x13, 0x69, 0x44, 0xaf, 0x21, 0x0e, 0x66, 0xcc,
- 0x84, 0x62, 0xe3, 0x40, 0xd1, 0x6e, 0x7e, 0xc5, 0xd7, 0xcf, 0xdb, 0x37, 0x28, 0x74, 0xdb, 0x95,
- 0x3f, 0x72, 0xbd, 0x69, 0xe4, 0x48, 0xe4, 0xb7, 0xc5, 0xcc, 0xf5, 0x0a, 0x7a, 0xb5, 0x3f, 0x9f,
- 0x56, 0x4b, 0x6a, 0x13, 0xc6, 0x49, 0x54, 0x4a, 0x29, 0x85, 0xd4, 0x6f, 0x87, 0xa0, 0x8b, 0x48,
- 0x36, 0x28, 0xad, 0x9e, 0xa6, 0x54, 0x25, 0x54, 0x52, 0x22, 0xeb, 0x56, 0x26, 0x66, 0x2d, 0x70,
- 0x99, 0xa6, 0xfa, 0x14, 0x6f, 0x38, 0xc5, 0xe3, 0x87, 0xaf, 0x7d, 0x8d, 0x41, 0x63, 0x4b, 0x37,
- 0xe1, 0x18, 0xe9, 0xfa, 0x5f, 0x35, 0xdc, 0x14, 0x1f, 0x47, 0x4d, 0x23, 0x7c, 0x72, 0x29, 0xa3,
- 0x05, 0xbd, 0xbf, 0xd4, 0x5e, 0x12, 0x5e, 0x65, 0x63, 0x5f, 0xf9, 0xd9, 0xe3, 0x96, 0x0c, 0x7d,
- 0x56, 0xd1, 0x4b, 0xfc, 0xd2, 0x14, 0xec, 0x46, 0xd0, 0x1a, 0xbb, 0x76, 0xa9, 0x6f, 0xfe, 0xe7,
- 0x9d, 0xe9, 0x3f, 0x51, 0x5c, 0xaf, 0x51, 0x49, 0x2e, 0x1d, 0x2b, 0xbb, 0x63, 0xe7, 0x2d, 0xf4,
- 0x40, 0x92, 0x7b, 0xdf, 0x92, 0x78, 0xbd, 0xb3, 0x67, 0x73, 0x8e, 0xa1, 0xb8, 0x77, 0x95, 0x43,
- 0xb2, 0x2b, 0xa9, 0x64, 0xa3, 0xf0, 0xf6, 0xe9, 0xd9, 0x52, 0xef, 0x7a, 0xc5, 0x58, 0x07, 0xf5,
- 0x80, 0xfb, 0xd4, 0xc1, 0xe3, 0xad, 0xf7, 0x9c, 0xbd, 0x3b, 0xb9, 0xa0, 0xbd, 0xa9, 0xad, 0x6d,
- 0xac, 0x58, 0xe8, 0xec, 0x42, 0xee, 0xc0, 0x81, 0x03, 0x62, 0x2c, 0x20, 0xd2, 0x84, 0xff, 0x80,
- 0xbc, 0x02, 0x5f, 0x84, 0x7e, 0x76, 0x2f, 0xe6, 0x23, 0x4c, 0x26, 0x24, 0x11, 0xd8, 0x3b, 0xfb,
- 0x4d, 0xc4, 0x9a, 0x1d, 0x7f, 0x08, 0x80, 0xa4, 0xc2, 0x0e, 0x98, 0xd9, 0x09, 0x86, 0x74, 0xa2,
- 0xc5, 0x9a, 0xac, 0xe8, 0x5a, 0xe0, 0x82, 0xeb, 0x72, 0xec, 0xe6, 0x20, 0xc3, 0x79, 0xd6, 0xef,
- 0x70, 0x64, 0x47, 0x4f, 0xae, 0xbc, 0x1e, 0x88, 0x28, 0x0a, 0xdb, 0xcc, 0x99, 0xf6, 0x03, 0xe3,
- 0x61, 0x92, 0xbb, 0x8a, 0xff, 0x23, 0x3d, 0xef, 0x19, 0x4a, 0xa8, 0xe6, 0x8c, 0x27, 0x2e, 0x60,
- 0xe6, 0xdd, 0xc7, 0x08, 0x71, 0x61, 0xf7, 0x7e, 0x5e, 0x2c, 0xea, 0x00, 0x96, 0x61, 0x8e, 0xac,
- 0x14, 0xad, 0xec, 0x73, 0xe2, 0xba, 0xbf, 0xf0, 0xc5, 0x68, 0x14, 0x5b, 0x75, 0x4a, 0xba, 0x8a,
- 0xd6, 0x8b, 0xe2, 0xe4, 0x45, 0x9e, 0xcf, 0xef, 0x34, 0xa3, 0x55, 0xe3, 0x3d, 0x4b, 0x19, 0xd7,
- 0x8d, 0x7a, 0x9f, 0x51, 0xe4, 0xf6, 0x16, 0xf4, 0xaa, 0x7f, 0x65, 0x17, 0x32, 0x05, 0x05, 0x82,
- 0x73, 0x06, 0xc7, 0x87, 0x3d, 0xc4, 0x07, 0x54, 0xa5, 0x34, 0x0e, 0xd0, 0x3c, 0xbc, 0x92, 0x79,
- 0x4f, 0x50, 0xa4, 0xe0, 0xa5, 0xaf, 0xda, 0xfc, 0xb9, 0x1b, 0x12, 0x38, 0x0e, 0x9a, 0x6c, 0x4e,
- 0x6a, 0x3a, 0x67, 0x60, 0x3f, 0x54, 0x9a, 0x9a, 0xfe, 0x7e, 0xd0, 0x51, 0x71, 0x99, 0xa6, 0xd9,
- 0xe6, 0x0b, 0x4a, 0x1a, 0x03, 0xce, 0xcb, 0xf6, 0x48, 0x93, 0xd1, 0x22, 0x06, 0x53, 0x82, 0x47,
- 0x16, 0x6c, 0x67, 0xb1, 0xf4, 0x59, 0x15, 0x7e, 0xcc, 0x2f, 0x50, 0xbe, 0x0a, 0x46, 0x6b, 0x98,
- 0xd0, 0x2c, 0xa6, 0x96, 0x8c, 0x90, 0x69, 0xab, 0x03, 0x4a, 0x2a, 0xab, 0xea, 0x2c, 0x32, 0xfa,
- 0x53, 0x39, 0x82, 0x67, 0x72, 0xf4, 0x9a, 0xfc, 0x83, 0x07, 0xdd, 0xb6, 0xe3, 0xcb, 0x69, 0x27,
- 0x16, 0x54, 0xf4, 0x4f, 0x9f, 0x0f, 0x00, 0x9b, 0xd4, 0x50, 0xa3, 0xf6, 0x4d, 0x4f, 0x0f, 0x46,
- 0x29, 0x7c, 0x3e, 0x46, 0x8a, 0x86, 0x12, 0xab, 0xdc, 0x65, 0x4b, 0xa4, 0x2c, 0x79, 0x14, 0x63,
- 0x87, 0x94, 0x61, 0x15, 0x4e, 0x5d, 0xab, 0xc3, 0x74, 0x83, 0xf6, 0x1f, 0xaa, 0x95, 0x43, 0x55,
- 0xc2, 0x01, 0x86, 0x2f, 0x2a, 0xfd, 0x4a, 0x97, 0x15, 0x7b, 0x26, 0xb3, 0x78, 0xf3, 0x89, 0xd2,
- 0x12, 0xe5, 0x78, 0xa4, 0x56, 0x36, 0x1d, 0x3f, 0xce, 0x77, 0x66, 0xdf, 0xeb, 0x82, 0xb5, 0xf9,
- 0x1c, 0x1c, 0xec, 0x29, 0x85, 0xc3, 0xc0, 0xc8, 0xe3, 0xbf, 0x30, 0x84, 0x0a, 0x70, 0x74, 0x1b,
- 0xb6, 0x77, 0xdb, 0x8a, 0x2c, 0xbe, 0x42, 0x13, 0xb1, 0x02, 0x4f, 0xff, 0xe9, 0x92, 0xa3, 0xb3,
- 0x6c, 0xd3, 0x3f, 0xc0, 0xd0, 0x32, 0x57, 0x94, 0xb8, 0x7a, 0x8f, 0xa2, 0xef, 0xfc, 0x31, 0xe7,
- 0x50, 0x09, 0x49, 0xe1, 0x4d, 0xd0, 0x09, 0x1e, 0x52, 0xb4, 0x8b, 0x01, 0xf2, 0xf8, 0x38, 0xb7,
- 0xa9, 0xf3, 0xd9, 0xbe, 0x4a, 0x8e, 0x66, 0x2d, 0x2e, 0x3a, 0x7f, 0x36, 0x45, 0xef, 0xfa, 0x90,
- 0x02, 0xb0, 0xfa, 0x19, 0x04, 0xf2, 0x41, 0x74, 0xcf, 0x6c, 0x5b, 0x6a, 0x40, 0x33, 0x30, 0xb9,
- 0x0f, 0x3d, 0x62, 0xe9, 0x26, 0x69, 0xf1, 0x3e, 0x3c, 0x29, 0x84, 0xd7, 0xb1, 0xb1, 0x53, 0x0f,
- 0x99, 0x80, 0xfe, 0x77, 0x6d, 0xd1, 0xdd, 0xe9, 0x37, 0xb9, 0x54, 0x45, 0xe6, 0x44, 0x9c, 0x9f,
- 0x68, 0x5b, 0x45, 0x47, 0xdf, 0x5d, 0xa2, 0xe9, 0x67, 0x1c, 0x37, 0x10, 0xcb, 0xb7, 0x1a, 0xcc,
- 0x58, 0x0f, 0xe8, 0x92, 0x01, 0x43, 0x23, 0xc6, 0xce, 0x7c, 0xeb, 0x57, 0xb1, 0x12, 0xaa, 0xef,
- 0x82, 0x21, 0x9a, 0x28, 0x44, 0x1c, 0xf0, 0x75, 0xf6, 0xc0, 0x68, 0x69, 0x71, 0x2f, 0xb1, 0x17,
- 0x57, 0xee, 0x50, 0x32, 0x64, 0x73, 0x4a, 0xae, 0x91, 0xae, 0xb6, 0xa7, 0xc2, 0xcb, 0x33, 0xb3,
- 0x8b, 0x82, 0xea, 0x42, 0xdb, 0x9b, 0xbd, 0xd0, 0xc8, 0x27, 0xfc, 0xb9, 0x32, 0xc9, 0xe0, 0x06,
- 0x5d, 0xd3, 0xd1, 0x02, 0x5b, 0x7b, 0x29, 0x96, 0x19, 0x52, 0x0f, 0xd9, 0x4f, 0x6f, 0x0a, 0x61,
- 0xc6, 0x95, 0xe4, 0x85, 0x33, 0x42, 0xea, 0xa4, 0xba, 0x0e, 0x96, 0xc9, 0x1f, 0x49, 0xaf, 0x53,
- 0x6e, 0xe4, 0x2b, 0x95, 0x37, 0x11, 0xa3, 0x88, 0xb2, 0x98, 0xa5, 0x1f, 0xc0, 0xe5, 0xa4, 0x95,
- 0xa3, 0x0b, 0x80, 0x4c, 0x9d, 0x8a, 0x1e, 0x9f, 0x6e, 0x23, 0x61, 0x5d, 0x3a, 0x2d, 0x64, 0xe3,
- 0x76, 0x50, 0xf1, 0xe0, 0x4f, 0x54, 0x22, 0xb9, 0x1f, 0x9a, 0x80, 0xfc, 0xdf, 0xf4, 0x69, 0xb3,
- 0xa2, 0x11, 0xb1, 0x9e, 0x55, 0xd1, 0x3d, 0x0a, 0x4b, 0x98, 0x3e, 0x8e, 0x7e, 0x50, 0x48, 0x62,
- 0xf6, 0xcd, 0x14, 0x24, 0xf0, 0xe0, 0x36, 0x69, 0x95, 0xae, 0x34, 0x58, 0xeb, 0xd7, 0xaa, 0x93,
- 0xdd, 0xfd, 0x92, 0x03, 0xdb, 0xaf, 0xc4, 0x7f, 0xdd, 0x35, 0xe6, 0x13, 0xaa, 0x51, 0xb0, 0x05,
- 0xb1, 0xf8, 0x46, 0xf7, 0x66, 0x5c, 0xeb, 0x97, 0x7c, 0xb3, 0x33, 0xc0, 0x26, 0x58, 0x36, 0x4f,
- 0x93, 0x2c, 0xe1, 0x49, 0x02, 0xca, 0xa3, 0x97, 0x2e, 0x03, 0x8f, 0x61, 0xaa, 0x7d, 0xf3, 0xa1,
- 0xbc, 0xa3, 0xa0, 0x06, 0x18, 0x38, 0x75, 0x75, 0x6a, 0x96, 0xab, 0x39, 0x23, 0xad, 0x2b, 0x9e,
- 0xcd, 0x42, 0x74, 0xf8, 0xe6, 0x01, 0xfc, 0xf1, 0x51, 0x06, 0x23, 0xef, 0x8c, 0xab, 0xba, 0x67,
- 0x8c, 0xf2, 0x88, 0x29, 0x86, 0x3a, 0x5c, 0xc3, 0x0e, 0xcf, 0xf6, 0x56, 0xb9, 0xc3, 0xb2, 0xc5,
- 0xfb, 0x1b, 0x58, 0xfe, 0xaf, 0x8b, 0x67, 0x98, 0x77, 0x89, 0xaf, 0xda, 0xff, 0x64, 0x46, 0xaf,
- 0x6a, 0xbe, 0x52, 0x62, 0xc4, 0x98, 0x8e, 0x52, 0x2e, 0x38, 0xcc, 0x2e, 0x63, 0x82, 0x20, 0x93,
- 0x54, 0xb0, 0x03, 0x70, 0x46, 0xe5, 0x66, 0x7f, 0xf0, 0xf7, 0x0e, 0xe3, 0xf0, 0x37, 0x72, 0xfe,
- 0xfe, 0x18, 0x51, 0x93, 0xc4, 0x39, 0xbf, 0xa1, 0xaf, 0x13, 0xcf, 0xff, 0x84, 0xb4, 0x2c, 0x52,
- 0xaf, 0xc6, 0x53, 0x29, 0xe3, 0xd8, 0xe9, 0x64, 0x4e, 0xf5, 0x58, 0x90, 0xcd, 0xa9, 0x4f, 0x75,
- 0x30, 0x6d, 0xf2, 0x2a, 0xe4, 0xbc, 0x53, 0x13, 0xfd, 0xf4, 0xdb, 0xaa, 0x09, 0xe5, 0xcb, 0x7a,
- 0x97, 0xd0, 0x19, 0xcc, 0xe4, 0x8e, 0xc0, 0x28, 0xea, 0xef, 0xbd, 0xef, 0xc1, 0x4b, 0xd0, 0xd0,
- 0x95, 0xb7, 0x2a, 0x0f, 0x2c, 0x30, 0xe7, 0xac, 0x96, 0x22, 0x89, 0x7c, 0xfe, 0xa6, 0xf6, 0xd4,
- 0x46, 0xd2, 0xc3, 0x84, 0x68, 0x4e, 0x66, 0xfc, 0xba, 0x0a, 0x68, 0x43, 0xbc, 0xd7, 0xef, 0xcc,
- 0x3e, 0xc6, 0xb8, 0xa7, 0x77, 0x33, 0x0f, 0x91, 0x0d, 0xd0, 0xe3, 0xe9, 0xcb, 0xd2, 0x17, 0x61,
- 0xd7, 0x03, 0xee, 0xce, 0xce, 0xa4, 0xd8, 0x21, 0x14, 0xab, 0x0b, 0x8f, 0x8e, 0x89, 0x68, 0x23,
- 0x0d, 0x39, 0x5c, 0x95, 0x6b, 0xaf, 0xa8, 0x3c, 0x11, 0xfe, 0x66, 0xeb, 0xa4, 0xfd, 0xeb, 0x2b,
- 0x9c, 0xac, 0xa9, 0xc5, 0x29, 0x5b, 0x21, 0xd8, 0x50, 0x0c, 0x84, 0xc3, 0x3b, 0x0c, 0xbb, 0xbc,
- 0xca, 0x08, 0x79, 0xf6, 0x2b, 0xc0, 0x2d, 0xa0, 0x71, 0x8a, 0xed, 0x55, 0x4c, 0xd7, 0xb1, 0x3f,
- 0x29, 0xb1, 0xa7, 0x5b, 0xeb, 0xf4, 0x7b, 0xf7, 0xb9, 0x64, 0x8c, 0x8c, 0x04, 0x77, 0x78, 0x2c,
- 0xee, 0x99, 0x81, 0x95, 0xee, 0x55, 0x34, 0x0e, 0xc0, 0x7a, 0x67, 0xb1, 0x83, 0x46, 0x31, 0x58,
- 0xf6, 0x12, 0x8e, 0x6c, 0x24, 0x2a, 0xc1, 0xfc, 0xe7, 0x23, 0x0b, 0x21, 0x4a, 0x2a, 0xde, 0xf5,
- 0xa4, 0xe9, 0x78, 0xde, 0x10, 0xef, 0x74, 0x7a, 0xa9, 0x1f, 0x49, 0xe5, 0x3f, 0x6d, 0xb5, 0xa5,
- 0x5d, 0xaa, 0x11, 0x4f, 0x7d, 0x1e, 0x0e, 0xe1, 0xc3, 0x70, 0xb5, 0xb5, 0x9a, 0x62, 0x99, 0x91,
- 0xb0, 0x9e, 0x22, 0x4a, 0x17, 0x67, 0xdf, 0xad, 0x1f, 0xa7, 0x18, 0xeb, 0x3c, 0x99, 0xef, 0x1c,
- 0xbe, 0xed, 0xb2, 0x93, 0xd5, 0x93, 0xdf, 0xae, 0x61, 0x16, 0x6f, 0x42, 0x5b, 0x87, 0xb2, 0x33,
- 0x08, 0x30, 0xcf, 0x5a, 0xc1, 0xc5, 0x86, 0x4f, 0xe8, 0x81, 0x31, 0xf4, 0x50, 0xa8, 0xe7, 0x30,
- 0x24, 0x42, 0xf2, 0x4e, 0xa5, 0xa1, 0x03, 0x46, 0xb9, 0xd9, 0x50, 0xb9, 0xfa, 0xfb, 0xd4, 0x87,
- 0xd0, 0xcb, 0x22, 0xdc, 0xcc, 0x5b, 0xad, 0xa7, 0x50, 0xaa, 0xb1, 0xed, 0x8b, 0xbf, 0x8a, 0xda,
- 0x4b, 0x6a, 0xac, 0x34, 0xc4, 0xb5, 0xd1, 0x92, 0x17, 0xad, 0x4f, 0x2c, 0x43, 0x57, 0x2e, 0xf3,
- 0x44, 0x52, 0x10, 0x78, 0x50, 0x31, 0x4b, 0x4e, 0x0f, 0x21, 0x95, 0x84, 0x65, 0x63, 0x8d, 0x05,
- 0x68, 0x43, 0xe6, 0xf9, 0x01, 0xa6, 0xdb, 0xf1, 0xbe, 0xc4, 0x45, 0x66, 0x24, 0x15, 0xd3, 0x96,
- 0xf6, 0xa7, 0x40, 0xe9, 0x36, 0xa7, 0x2a, 0x18, 0x44, 0x1c, 0x27, 0x06, 0x6f, 0xf0, 0x6f, 0xbb,
- 0x2f, 0xf5, 0x47, 0x9f, 0xf9, 0xa4, 0x11, 0x22, 0xee, 0x14, 0x8d, 0xde, 0xe7, 0x4c, 0x9d, 0xad,
- 0x05, 0x5d, 0xf7, 0xf1, 0x58, 0xf8, 0x49, 0xac, 0x7a, 0xa1, 0x7b, 0x79, 0xfd, 0x0a, 0xbd, 0xf8,
- 0x86, 0x61, 0x14, 0x09, 0x4c, 0x14, 0x25, 0x57, 0x87, 0x4c, 0x85, 0x4b, 0x4e, 0x89, 0x52, 0xf9,
- 0x82, 0xfe, 0x70, 0x3f, 0x21, 0x73, 0x44, 0xf5, 0x5a, 0x77, 0xf6, 0xda, 0x57, 0xe0, 0xe3, 0xed,
- 0xb0, 0x3f, 0xb0, 0x34, 0x12, 0xdf, 0x24, 0x91, 0x2e, 0xe3, 0x2f, 0x75, 0xe7, 0x88, 0xfa, 0xb5,
- 0xd1, 0x67, 0xc4, 0x75, 0xf8, 0xa8, 0x67, 0x70, 0x91, 0x3b, 0x4c, 0xcb, 0x1b, 0x99, 0x90, 0x99,
- 0x0b, 0x45, 0x1c, 0xef, 0xeb, 0x90, 0x40, 0xb5, 0xc2, 0x63, 0xc6, 0x35, 0x8c, 0xdf, 0xd6, 0xfb,
- 0x3d, 0x12, 0x23, 0x39, 0x6a, 0x47, 0x6a, 0x1d, 0xf7, 0x5b, 0x84, 0x0b, 0x1d, 0x45, 0x53, 0xa3,
- 0x46, 0x33, 0x93, 0x73, 0x02, 0xb3, 0xef, 0xc3, 0x78, 0xfe, 0x28, 0xcc, 0x12, 0x60, 0x64, 0xb6,
- 0xf8, 0x57, 0xf3, 0x8a, 0xc3, 0x3b, 0xdc, 0xf6, 0xb8, 0x4b, 0x72, 0x78, 0x68, 0xcc, 0x72, 0xf6,
- 0xd9, 0x12, 0x9f, 0xe5, 0xdc, 0xb0, 0x9a, 0x5d, 0xb3, 0x2e, 0x47, 0x34, 0xdb, 0x86, 0x14, 0x64,
- 0x7a, 0x05, 0x78, 0xde, 0xb2, 0xd9, 0x15, 0xa7, 0xa2, 0x80, 0x83, 0x06, 0x40, 0x0f, 0x80, 0xef,
- 0xe9, 0xb8, 0xc0, 0x3e, 0x28, 0x1f, 0x87, 0x9a, 0x9a, 0xb1, 0x50, 0xc6, 0x08, 0x83, 0x59, 0xca,
- 0xe7, 0x1f, 0x90, 0xeb, 0x11, 0x4d, 0x10, 0x5e, 0x20, 0x80, 0xa1, 0xdf, 0xdd, 0x30, 0x80, 0xb1,
- 0xa2, 0x16, 0xcc, 0x2b, 0x7c, 0x13, 0x44, 0xbc, 0x36, 0xf6, 0x28, 0x31, 0xb8, 0xa1, 0xaf, 0x4c,
- 0xb7, 0x4d, 0x2a, 0xdc, 0xb5, 0x6e, 0x4c, 0x81, 0xe9, 0xe4, 0x83, 0xdb, 0xbb, 0x1c, 0x65, 0x8f,
- 0x8d, 0x4e, 0xfb, 0x02, 0xab, 0x81, 0x08, 0x56, 0x9f, 0x86, 0x0c, 0x16, 0xb9, 0xd1, 0xf6, 0x2c,
- 0xbe, 0xbb, 0xa0, 0x3e, 0x9a, 0x73, 0x19, 0xf7, 0xfc, 0xfc, 0xfd, 0x7e, 0xd3, 0x13, 0xad, 0x78,
- 0xdb, 0x3c, 0xac, 0xb2, 0xfb, 0xe9, 0xc8, 0xa5, 0xfc, 0x67, 0xd1, 0xa4, 0x3d, 0x67, 0x00, 0x52,
- 0x40, 0x58, 0xa5, 0x82, 0xe6, 0x7b, 0x57, 0x10, 0x57, 0x71, 0x06, 0x71, 0x88, 0xdd, 0xd0, 0xf5,
- 0x9f, 0x20, 0x2a, 0x7c, 0x73, 0xdf, 0x68, 0xda, 0xe5, 0x97, 0xe3, 0x35, 0x3b, 0xb8, 0x35, 0xed,
- 0x0b, 0xa4, 0x3a, 0x44, 0x0c, 0x18, 0x7d, 0x94, 0x98, 0x80, 0xdf, 0x41, 0xac, 0xd2, 0xc3, 0xd6,
- 0xa1, 0xfa, 0xce, 0x82, 0x95, 0x42, 0x59, 0x33, 0x3d, 0x81, 0x9f, 0xe9, 0x3c, 0xfa, 0xfe, 0x05,
- 0x61, 0x6f, 0xde, 0xa1, 0x0f, 0x86, 0x1a, 0xcb, 0x13, 0x3d, 0x94, 0x92, 0x27, 0x44, 0xa6, 0x55,
- 0xb3, 0x0e, 0x01, 0x26, 0x7e, 0x62, 0x82, 0xc2, 0x88, 0x05, 0x09, 0xac, 0xda, 0xa1, 0x09, 0x60,
- 0x25, 0xda, 0x86, 0x96, 0x54, 0xfa, 0xf8, 0x38, 0x05, 0x67, 0x1c, 0x52, 0x6a, 0x03, 0x1a, 0x54,
- 0x21, 0x50, 0x3f, 0x84, 0xbb, 0x2c, 0x3a, 0x40, 0x2b, 0x9b, 0xeb, 0x82, 0x25, 0x79, 0x4e, 0x37,
- 0x19, 0x07, 0x6b, 0x71, 0x8b, 0xaa, 0x6f, 0x32, 0x29, 0x31, 0x52, 0xc6, 0x7b, 0xec, 0xfe, 0xbe,
- 0xf8, 0x6e, 0x9b, 0x73, 0x13, 0xd7, 0xa9, 0xb8, 0x9f, 0x40, 0x38, 0x3e, 0x68, 0x7a, 0xd8, 0x82,
- 0xe2, 0xe0, 0x8a, 0xac, 0x69, 0x85, 0x90, 0x2c, 0xbd, 0x7a, 0x8e, 0xa1, 0xef, 0x47, 0x09, 0x8d,
- 0xb9, 0x1a, 0x90, 0xa5, 0x22, 0xc1, 0xa8, 0xe5, 0x92, 0x28, 0xd7, 0xf5, 0x8a, 0x95, 0x83, 0x0c,
- 0x97, 0x16, 0x1d, 0xc8, 0x1b, 0x40, 0x80, 0x2b, 0x7f, 0x4b, 0x76, 0xe7, 0x6c, 0x69, 0x99, 0xd3,
- 0x75, 0xee, 0xb0, 0x00, 0xb6, 0xa8, 0x87, 0x85, 0xf5, 0x63, 0x4e, 0xc4, 0xfc, 0x4c, 0x2e, 0x3c,
- 0x23, 0x8f, 0xa6, 0x79, 0x97, 0x07, 0xe4, 0x80, 0xf8, 0xde, 0xf5, 0x46, 0x60, 0x62, 0xd7, 0x5d,
- 0x23, 0x7b, 0xe4, 0xbd, 0x06, 0x66, 0x2a, 0x16, 0x31, 0x55, 0x04, 0xde, 0x5c, 0x14, 0x8b, 0x25,
- 0x0a, 0x0e, 0x14, 0xe6, 0xf3, 0xb8, 0x88, 0xf9, 0xc0, 0x5e, 0xeb, 0xef, 0x41, 0x69, 0x2a, 0x1c,
- 0x2e, 0x05, 0x1c, 0x88, 0x2d, 0xd5, 0x38, 0x48, 0xe6, 0x0c, 0x17, 0x58, 0xbb, 0xc9, 0xd8, 0xd7,
- 0xa3, 0xbc, 0x63, 0x5b, 0x9c, 0xa9, 0xf1, 0x99, 0x1e, 0xcb, 0x56, 0x9c, 0xfb, 0x17, 0xe0, 0x64,
- 0x78, 0x3d, 0xd5, 0x0b, 0x92, 0x29, 0x8a, 0xd7, 0x73, 0xbd, 0x16, 0xc6, 0x7d, 0x41, 0x52, 0xb2,
- 0x46, 0x04, 0xc7, 0xbc, 0x59, 0xe2, 0x33, 0xb8, 0x15, 0x06, 0x81, 0x85, 0x66, 0x38, 0x56, 0x33,
- 0xf6, 0x50, 0xc5, 0x11, 0xd6, 0xec, 0x4a, 0x45, 0x4f, 0x05, 0x21, 0x9a, 0x8b, 0xc2, 0xb9, 0x5f,
- 0x54, 0x7e, 0x2a, 0x44, 0xa6, 0xd4, 0x5a, 0xd9, 0x93, 0x20, 0x87, 0xbc, 0xc9, 0x80, 0x3a, 0x46,
- 0x99, 0x54, 0x57, 0x7a, 0x8a, 0xb5, 0x11, 0xbf, 0x9c, 0xa7, 0xc3, 0xac, 0xea, 0xb1, 0x54, 0xd3,
- 0xe7, 0x2e, 0x31, 0xc0, 0x0e, 0x48, 0x8e, 0xb9, 0x31, 0xd3, 0x2a, 0xf9, 0xdf, 0xa7, 0xcd, 0x99,
- 0x48, 0xc1, 0x29, 0x8d, 0xe1, 0x49, 0x58, 0xd7, 0xd4, 0x1d, 0x61, 0xf6, 0xc0, 0xca, 0x47, 0x6f,
- 0x6a, 0x55, 0x49, 0xf3, 0xe0, 0xe0, 0x4c, 0xf1, 0xe5, 0x32, 0xc0, 0x4c, 0xe2, 0xac, 0x1f, 0xea,
- 0x4f, 0xf3, 0x8d, 0xe1, 0x4d, 0xf6, 0xf0, 0xf4, 0x6c, 0x34, 0x17, 0x17, 0xdd, 0x0d, 0xa2, 0x02,
- 0xad, 0xcf, 0xc7, 0x15, 0x54, 0xdc, 0xeb, 0x04, 0x26, 0xf4, 0x01, 0xa9, 0x33, 0x8f, 0x8a, 0xe1,
- 0x66, 0xfe, 0xb6, 0x2b, 0x95, 0xcd, 0x1f, 0x62, 0x81, 0x54, 0x70, 0x68, 0x88, 0x53, 0x89, 0x69,
- 0x4a, 0x31, 0xcc, 0x48, 0x8d, 0xaf, 0x83, 0x7f, 0xf9, 0xa8, 0x7f, 0x63, 0x9f, 0x0c, 0x24, 0xc7,
- 0x9f, 0x21, 0x8a, 0x0d, 0xb4, 0xcd, 0xfe, 0xd4, 0x8a, 0xc5, 0x3d, 0xf5, 0x17, 0x73, 0x44, 0x40,
- 0xee, 0x08, 0x94, 0x0d, 0x56, 0x78, 0xae, 0x00, 0x61, 0xa4, 0x94, 0xc8, 0xd1, 0x4c, 0xbd, 0xdb,
- 0x27, 0xf8, 0x05, 0x84, 0x27, 0xaf, 0x88, 0xbd, 0x41, 0x97, 0x82, 0x4e, 0x07, 0x11, 0xc0, 0xf2,
- 0xff, 0xa4, 0x51, 0x7f, 0x86, 0x8e, 0xe8, 0x72, 0x93, 0xb2, 0x24, 0xbc, 0x60, 0xd0, 0xbf, 0xad,
- 0x6c, 0xaf, 0xa7, 0x8c, 0x04, 0x50, 0x1d, 0x83, 0xac, 0x7c, 0x25, 0xf6, 0x07, 0x70, 0xd8, 0xe2,
- 0x8e, 0x13, 0x5d, 0x22, 0x4e, 0x3e, 0xec, 0xf7, 0xf8, 0x93, 0x40, 0x1e, 0x8a, 0xed, 0x48, 0x05,
- 0x1c, 0xe4, 0x8f, 0xa5, 0x56, 0x82, 0x53, 0xf7, 0x18, 0x76, 0x4e, 0xa4, 0x2b, 0xde, 0x64, 0xcf,
- 0xc8, 0x39, 0x33, 0x52, 0x8a, 0x35, 0x78, 0xd9, 0x8e, 0x72, 0x1a, 0x86, 0x58, 0x8c, 0xba, 0x8d,
- 0xe2, 0x8e, 0xab, 0x8e, 0xbd, 0x9e, 0x33, 0x41, 0x40, 0x42, 0x76, 0x45, 0x91, 0x2c, 0x79, 0xfc,
- 0x32, 0xa9, 0x76, 0x2e, 0x42, 0x99, 0xa2, 0x7a, 0xbc, 0xe8, 0xcd, 0x64, 0xb9, 0x00, 0x87, 0xb1,
- 0xe3, 0x48, 0xa4, 0x25, 0x8d, 0x6a, 0x5b, 0xf0, 0x89, 0xf8, 0x24, 0x11, 0x1a, 0x2f, 0x2d, 0x99,
- 0xf8, 0x72, 0x38, 0xd8, 0xec, 0xef, 0xfe, 0x13, 0x9f, 0x5e, 0x3b, 0x0b, 0xd6, 0x83, 0xb7, 0x03,
- 0xb8, 0x7b, 0xe6, 0x34, 0xa7, 0x0b, 0xc3, 0x9d, 0x48, 0xdf, 0x8f, 0xe1, 0xc3, 0x62, 0x6b, 0xd4,
- 0xb1, 0x6c, 0xff, 0xf5, 0x45, 0xe4, 0xf5, 0x0d, 0xda, 0xc8, 0x96, 0x02, 0x30, 0x93, 0xcb, 0x76,
- 0x40, 0xfe, 0xea, 0x25, 0x66, 0xe8, 0xde, 0x30, 0x90, 0xed, 0x46, 0x56, 0x5c, 0xcf, 0x0d, 0x2a,
- 0xd3, 0x00, 0xa4, 0xfd, 0x84, 0x48, 0x5d, 0x5d, 0xe5, 0x8e, 0x45, 0x6f, 0x1d, 0xb4, 0x3d, 0x88,
- 0x92, 0x47, 0x3e, 0xfc, 0x97, 0x21, 0x3f, 0x03, 0x14, 0xef, 0x1e, 0xc4, 0xe5, 0x76, 0x87, 0x33,
- 0x35, 0x1b, 0x2d, 0xfe, 0x4f, 0xf0, 0x0f, 0xdf, 0x50, 0xcb, 0x4a, 0xb1, 0x1d, 0xed, 0x87, 0x14,
- 0x18, 0xa3, 0x6b, 0xc2, 0xd9, 0x2c, 0x3d, 0x69, 0xdf, 0xd5, 0x07, 0x10, 0x55, 0x8a, 0xab, 0xe5,
- 0xa7, 0x26, 0x27, 0xa2, 0xe6, 0xb3, 0xac, 0x75, 0x77, 0x37, 0xb8, 0xf3, 0xcb, 0x39, 0xa7, 0x98,
- 0xe3, 0x3a, 0x1d, 0x3b, 0xce, 0xcb, 0x51, 0x71, 0x5e, 0xfd, 0x98, 0x72, 0xa5, 0x6b, 0xec, 0x16,
- 0x7a, 0x8c, 0xec, 0xa4, 0xfa, 0x6e, 0xf3, 0x75, 0xac, 0x32, 0xb7, 0x37, 0x16, 0xba, 0xf3, 0x78,
- 0xf3, 0x4b, 0xb2, 0x0f, 0xec, 0x3a, 0xab, 0x52, 0x25, 0xc6, 0xcc, 0x6f, 0xc1, 0xb1, 0xc9, 0x82,
- 0xc2, 0x34, 0xd4, 0xd9, 0x11, 0x0b, 0x67, 0x7e, 0x72, 0x30, 0xd6, 0x40, 0xf4, 0xa4, 0xdc, 0xe7,
- 0x21, 0x5c, 0x3e, 0x25, 0xd4, 0xd4, 0x74, 0xea, 0x5a, 0xb8, 0x0a, 0x6a, 0x15, 0x1c, 0xa9, 0x96,
- 0xd8, 0x77, 0x23, 0x00, 0x73, 0xad, 0x26, 0x8a, 0x34, 0x2f, 0x5c, 0x08, 0x8b, 0x66, 0xa1, 0x47,
- 0x53, 0x1d, 0xd6, 0x31, 0x49, 0xca, 0x72, 0xd8, 0x9f, 0x41, 0x0a, 0x91, 0xe7, 0xad, 0x97, 0xc9,
- 0x58, 0xe2, 0x31, 0x15, 0x01, 0xbd, 0x53, 0xf4, 0x3a, 0xb1, 0x1f, 0xef, 0xce, 0x7d, 0xb0, 0x47,
- 0xb9, 0x66, 0xf3, 0x12, 0x80, 0xfb, 0x81, 0x7d, 0xba, 0x87, 0xca, 0x55, 0xcf, 0x60, 0x40, 0xdf,
- 0xad, 0xf9, 0x20, 0xbe, 0x04, 0x44, 0x32, 0x34, 0x71, 0xdc, 0x9b, 0x8f, 0xa0, 0x8b, 0xf8, 0x48,
- 0xbe, 0x35, 0xc9, 0xa9, 0x7b, 0x79, 0x81, 0x3e, 0xee, 0x14, 0x5b, 0x91, 0xa4, 0xa8, 0xbe, 0x27,
- 0x2b, 0x85, 0xdc, 0xf4, 0x7d, 0xf5, 0x09, 0xbe, 0x9e, 0x70, 0x18, 0xb1, 0x03, 0xde, 0x95, 0x92,
- 0x49, 0xd1, 0xc8, 0xd5, 0xbf, 0x88, 0xd3, 0xd8, 0x9c, 0x09, 0xfe, 0x2d, 0x91, 0x61, 0x37, 0xaa,
- 0x8c, 0x9c, 0x6a, 0x73, 0x48, 0xbc, 0x36, 0xd2, 0x58, 0x38, 0x9b, 0xdc, 0x51, 0x04, 0xdd, 0xe5,
- 0xce, 0x64, 0x77, 0x3c, 0x08, 0x40, 0x35, 0x92, 0xfa, 0x74, 0xb9, 0xd6, 0xeb, 0xcf, 0x85, 0xf9,
- 0x9a, 0xf5, 0x29, 0xa9, 0x22, 0xb7, 0xd7, 0x8b, 0xd8, 0xc6, 0x9f, 0xdb, 0xd1, 0x34, 0x38, 0x3f,
- 0xa8, 0xfd, 0xe5, 0x26, 0xb5, 0x3a, 0x5c, 0x30, 0xcc, 0xca, 0x33, 0x5d, 0xc5, 0x0f, 0x36, 0x0c,
- 0xe6, 0xa9, 0x2b, 0xe7, 0x7c, 0x9a, 0xcc, 0x3d, 0x87, 0xbd, 0x62, 0x81, 0x0d, 0xf7, 0x9c, 0xc2,
- 0x0e, 0xb9, 0xec, 0x39, 0xc0, 0xa4, 0xf2, 0x61, 0x67, 0x4f, 0x16, 0x2d, 0x2b, 0x8f, 0xdb, 0xb3,
- 0xea, 0x2d, 0x62, 0x84, 0x2c, 0xb3, 0x1f, 0xb7, 0x4b, 0x5b, 0xff, 0x83, 0x30, 0x50, 0x1f, 0xd8,
- 0xc5, 0x73, 0x65, 0x14, 0x84, 0x9a, 0xc3, 0xee, 0xda, 0xba, 0xc9, 0xc5, 0xe7, 0x6e, 0x7d, 0xb6,
- 0xaf, 0xb9, 0xba, 0x8b, 0x87, 0x71, 0x00, 0x84, 0x1a, 0xd8, 0x85, 0xa1, 0xb5, 0x78, 0xe5, 0xd7,
- 0x08, 0x70, 0xa3, 0xef, 0x2d, 0x81, 0xe1, 0x5e, 0xb1, 0xe4, 0x84, 0x70, 0x05, 0x6d, 0x2e, 0x3a,
- 0x7e, 0x8d, 0x08, 0x04, 0x81, 0x37, 0xd0, 0xf8, 0x24, 0x13, 0x66, 0xd7, 0xef, 0xe9, 0x7b, 0xc7,
- 0x01, 0xb1, 0x89, 0xcc, 0xf6, 0x09, 0x07, 0xdd, 0x7b, 0xf1, 0x29, 0x34, 0xd3, 0x3e, 0xbf, 0x44,
- 0x66, 0x52, 0xc8, 0x62, 0x65, 0xf9, 0x7f, 0x7d, 0x1b, 0x58, 0xdb, 0xcc, 0xea, 0x78, 0x85, 0x45,
- 0x30, 0x1b, 0xb7, 0x57, 0x46, 0xf6, 0x22, 0x4f, 0x59, 0x02, 0x2a, 0xbf, 0xa8, 0x8d, 0xa7, 0xa8,
- 0x9d, 0x20, 0x9d, 0x63, 0x3a, 0xdb, 0xe3, 0x74, 0xcd, 0x73, 0x43, 0x6f, 0xda, 0x1c, 0x94, 0xac,
- 0x24, 0x2f, 0xc8, 0xef, 0x0e, 0xff, 0xe4, 0xf2, 0xc6, 0x76, 0xd0, 0xe1, 0xbe, 0x09, 0xc2, 0xcb,
- 0xfb, 0x43, 0x9c, 0xa1, 0xf6, 0x66, 0x1d, 0x0a, 0xdc, 0xf7, 0x1d, 0xc3, 0x18, 0x36, 0xd5, 0x9f,
- 0x7b, 0xd0, 0xfa, 0xd2, 0xad, 0x55, 0x98, 0xe9, 0x8a, 0x7b, 0x80, 0xf4, 0xea, 0xba, 0xde, 0xf1,
- 0x08, 0xb2, 0xf2, 0xaf, 0x27, 0x1a, 0xf3, 0xe0, 0xef, 0x00, 0x10, 0x7f, 0xd1, 0xd5, 0x32, 0x10,
- 0x25, 0x95, 0x93, 0xf3, 0xd0, 0x9e, 0x31, 0xad, 0x26, 0x32, 0x53, 0xe2, 0x4e, 0x64, 0x69, 0xad,
- 0xa3, 0xf3, 0xd3, 0x92, 0x94, 0x72, 0xd4, 0xb3, 0xaf, 0x89, 0xf6, 0x02, 0x69, 0x8a, 0x4d, 0xf2,
- 0x91, 0x06, 0xbf, 0xf1, 0x66, 0x7f, 0xc3, 0x87, 0x9c, 0xec, 0x45, 0x42, 0x0c, 0x40, 0x79, 0x0e,
- 0xbe, 0x43, 0xe6, 0x11, 0xe9, 0x0b, 0x69, 0x0d, 0x89, 0x07, 0xef, 0xf7, 0x59, 0x43, 0x81, 0xe3,
- 0xfb, 0xee, 0x59, 0xb0, 0x48, 0x67, 0x64, 0x8e, 0x06, 0x24, 0xc1, 0x08, 0xe0, 0xb2, 0xb5, 0x1f,
- 0x48, 0xb9, 0x6e, 0x9d, 0x6b, 0x5c, 0xf8, 0x9c, 0xd6, 0x18, 0xbd, 0xc3, 0x21, 0x78, 0xda, 0x88,
- 0x0a, 0x59, 0xb1, 0xcb, 0x7d, 0xba, 0x7a, 0xe5, 0x1f, 0x8e, 0xb1, 0x2f, 0x20, 0x4b, 0xde, 0x5c,
- 0xfe, 0x0d, 0xfe, 0x4c, 0x5f, 0x12, 0x41, 0xd4, 0xc8, 0xb2, 0xdb, 0xa5, 0xa1, 0x3b, 0xc2, 0x05,
- 0xbc, 0x27, 0x55, 0x47, 0xef, 0x67, 0xd7, 0x2b, 0x94, 0x5b, 0x2d, 0x0c, 0xda, 0x92, 0xe1, 0x37,
- 0x80, 0xea, 0x3a, 0x5e, 0xb6, 0x45, 0xef, 0x5f, 0xb0, 0xec, 0xe5, 0x45, 0x06, 0x05, 0xc4, 0x83,
- 0x75, 0x3c, 0x58, 0xea, 0xfc, 0xe2, 0x53, 0xa6, 0x6b, 0xc9, 0x9e, 0x05, 0xbd, 0x85, 0x5d, 0x19,
- 0xb0, 0xd4, 0xa1, 0x00, 0xd3, 0xde, 0x5d, 0xfe, 0x0e, 0x57, 0x48, 0xd4, 0x87, 0xde, 0xd9, 0xf4,
- 0x40, 0x24, 0xeb, 0xe4, 0xec, 0x6d, 0xcb, 0xcc, 0xf1, 0xd8, 0xa3, 0xc8, 0x12, 0x9b, 0x0a, 0xc6,
- 0x85, 0xec, 0x63, 0x48, 0xcb, 0x0e, 0x91, 0x30, 0x1e, 0x45, 0xb3, 0x2a, 0xc7, 0xe0, 0xb5, 0x8f,
- 0x93, 0xf0, 0xbf, 0xd5, 0x9e, 0x83, 0xbd, 0x51, 0x9a, 0xda, 0x11, 0xe0, 0xb0, 0xfe, 0x19, 0xd9,
- 0xec, 0xed, 0xa7, 0x1d, 0xf2, 0x41, 0xc9, 0x27, 0xaa, 0xef, 0x41, 0x1c, 0x79, 0xb9, 0x65, 0x20,
- 0x64, 0x54, 0x9b, 0xd6, 0xdb, 0xee, 0x5e, 0x3e, 0xa1, 0x0f, 0x4a, 0x89, 0xac, 0x2c, 0xdf, 0x20,
- 0x35, 0x83, 0xf2, 0x15, 0x39, 0xf0, 0xb5, 0xc5, 0xc6, 0x27, 0x9c, 0x23, 0x57, 0xbe, 0x31, 0x5e,
- 0x7c, 0xfd, 0x25, 0x3a, 0xac, 0xca, 0x80, 0xed, 0x73, 0x27, 0x73, 0x3d, 0xe4, 0xec, 0xc1, 0xf4,
- 0x7c, 0x41, 0xcd, 0x92, 0xc4, 0x05, 0x09, 0xaf, 0x7c, 0x3c, 0x51, 0xd1, 0x01, 0x46, 0x26, 0x08,
- 0xfb, 0x44, 0xca, 0x8b, 0x19, 0xd8, 0x53, 0x46, 0x45, 0x3d, 0xca, 0x7a, 0x3d, 0x7a, 0xb6, 0x50,
- 0xfa, 0x3f, 0x1a, 0xd0, 0x3d, 0x53, 0xb5, 0x0f, 0xfc, 0xa5, 0x0f, 0x8a, 0xdd, 0x64, 0x80, 0x17,
- 0x73, 0xcf, 0xd4, 0x16, 0x41, 0x29, 0xee, 0xbb, 0x6d, 0x10, 0xd4, 0xd7, 0x90, 0xde, 0x78, 0x3b,
- 0xe2, 0x46, 0xdc, 0xe9, 0x37, 0xf9, 0x32, 0xc5, 0xf1, 0xe0, 0x9c, 0x9d, 0x45, 0x46, 0x47, 0xd7,
- 0xc7, 0x00, 0x04, 0xeb, 0xf5, 0xd7, 0x8a, 0x05, 0xc5, 0x6c, 0x8c, 0x9b, 0x03, 0x4d, 0x49, 0xca,
- 0xc7, 0x61, 0x9f, 0xdb, 0x56, 0xee, 0x6b, 0xf2, 0x9f, 0x98, 0xd4, 0xce, 0xb6, 0x59, 0x51, 0x1f,
- 0x3e, 0x41, 0xe1, 0xc0, 0x3e, 0x38, 0xd6, 0x86, 0x62, 0xe6, 0x58, 0xc6, 0x7a, 0xda, 0x7c, 0xe8,
- 0x7a, 0x8a, 0xdc, 0xdb, 0x58, 0x67, 0x49, 0x81, 0x0b, 0x9a, 0x97, 0x22, 0xba, 0xcd, 0xb6, 0xe3,
- 0x41, 0x80, 0x68, 0x5c, 0x0d, 0x8f, 0x0f, 0xb0, 0x0e, 0xab, 0xc6, 0xb7, 0x29, 0x0f, 0x07, 0x3c,
- 0x88, 0x1b, 0x41, 0x5d, 0x33, 0x2e, 0xa7, 0x2d, 0x1d, 0xae, 0x6b, 0x5d, 0x37, 0x48, 0x2e, 0xa3,
- 0x82, 0xd5, 0xc9, 0x28, 0xbc, 0x72, 0x7c, 0xad, 0x9a, 0x7d, 0xe0, 0x24, 0x31, 0x36, 0x8b, 0x49,
- 0x33, 0x44, 0x5a, 0xc8, 0x26, 0x82, 0x5f, 0x21, 0xf0, 0xdf, 0x2e, 0x97, 0x8d, 0x0a, 0x01, 0xa9,
- 0xec, 0x00, 0x8d, 0xbb, 0x9c, 0xff, 0x0b, 0x77, 0x99, 0xab, 0x1d, 0x29, 0xbe, 0x62, 0x6f, 0x1d,
- 0x68, 0xb4, 0x00, 0x61, 0xa9, 0x90, 0x55, 0x89, 0xd9, 0x31, 0x5d, 0x80, 0xd9, 0xb7, 0x53, 0xbe,
- 0xd3, 0x29, 0x1c, 0x75, 0x7f, 0x4c, 0x56, 0x73, 0x7f, 0xb5, 0x42, 0xfb, 0xb6, 0xc1, 0x2d, 0x86,
- 0xd6, 0x73, 0xa1, 0xa3, 0xe1, 0xe6, 0x8e, 0x47, 0x10, 0xbc, 0xce, 0xb2, 0x85, 0xef, 0xfd, 0x33,
- 0x1f, 0x18, 0xe9, 0x87, 0x36, 0xc2, 0x5e, 0x22, 0xb8, 0x62, 0x67, 0x33, 0xbc, 0xc8, 0x46, 0x53,
- 0x55, 0xd7, 0xef, 0x82, 0x98, 0xb7, 0x21, 0x12, 0x04, 0xd3, 0x0f, 0x80, 0x52, 0xe0, 0x35, 0xa7,
- 0x04, 0xc2, 0x47, 0x6a, 0xc8, 0xdc, 0xda, 0x9f, 0xe3, 0x18, 0x3c, 0x5d, 0x97, 0x31, 0x3b, 0x45,
- 0x56, 0xdc, 0xe3, 0x82, 0xb6, 0x7d, 0xcf, 0x60, 0x2b, 0xbe, 0x6a, 0x8b, 0xcc, 0x68, 0x55, 0xfb,
- 0x57, 0x7b, 0x80, 0x78, 0x07, 0xdd, 0xae, 0xf6, 0xb7, 0xac, 0x77, 0x9c, 0x71, 0x12, 0xbe, 0xf5,
- 0xf8, 0xda, 0xd2, 0xfd, 0x4f, 0x2d, 0xe3, 0xa0, 0xb2, 0xde, 0x67, 0x61, 0x4e, 0x79, 0xd0, 0xa1,
- 0x42, 0xc3, 0x0b, 0x27, 0x70, 0xd8, 0x2f, 0xaa, 0x28, 0x96, 0x65, 0x6e, 0x61, 0xe2, 0x2f, 0x52,
- 0xc7, 0x96, 0x4d, 0x96, 0x96, 0xeb, 0x37, 0xcb, 0xdd, 0x90, 0xab, 0xc7, 0x74, 0xd0, 0x09, 0xcc,
- 0x25, 0x52, 0x88, 0xee, 0x91, 0xd5, 0xdc, 0xcc, 0x20, 0x51, 0x24, 0x22, 0x1c, 0x8c, 0xad, 0xc2,
- 0x85, 0x36, 0x6b, 0xcc, 0x07, 0x7e, 0x17, 0x2b, 0xaf, 0x98, 0x30, 0x3c, 0xb2, 0xf4, 0x4b, 0x0b,
- 0x57, 0x10, 0x2e, 0x35, 0x64, 0x16, 0xf0, 0x3a, 0xf6, 0xab, 0x6f, 0x5f, 0x0a, 0x2b, 0xa7, 0x4b,
- 0xec, 0xf2, 0x02, 0x2b, 0x0a, 0xcf, 0x35, 0xd1, 0xf0, 0xc3, 0x4b, 0x0c, 0x8e, 0x1b, 0x08, 0xcf,
- 0x45, 0xf1, 0x98, 0x8c, 0xf7, 0x60, 0x60, 0xf6, 0x69, 0x22, 0x49, 0x70, 0x48, 0xbe, 0x2c, 0xb2,
- 0xba, 0xfd, 0x92, 0x1f, 0xfd, 0xfd, 0xdb, 0x93, 0x73, 0x6d, 0xb2, 0x7f, 0xe8, 0xe3, 0x4c, 0xa8,
- 0x7f, 0x12, 0x9a, 0xde, 0xe3, 0xee, 0x30, 0xc8, 0xcc, 0xcb, 0xa2, 0x99, 0xcf, 0x7e, 0xa2, 0x9f,
- 0xba, 0x1f, 0xd6, 0x38, 0x08, 0xc3, 0x45, 0xbd, 0x55, 0x47, 0x69, 0xbd, 0xd2, 0x42, 0x69, 0xf3,
- 0xb3, 0x68, 0xb7, 0xe5, 0x58, 0x4d, 0xb7, 0xd4, 0x47, 0x32, 0x45, 0xa1, 0x8c, 0x46, 0x76, 0xa2,
- 0x1d, 0x7a, 0x80, 0x1f, 0xde, 0xbd, 0x15, 0x96, 0x8a, 0xf9, 0xa6, 0xdb, 0x62, 0x98, 0x49, 0xef,
- 0xa7, 0x35, 0x4a, 0x19, 0x91, 0x23, 0x66, 0xa9, 0x3c, 0x64, 0x4c, 0x1f, 0xde, 0x93, 0x6e, 0x2b,
- 0x0e, 0xb1, 0xca, 0xa6, 0x2e, 0x3c, 0x24, 0x46, 0x88, 0x31, 0xe3, 0x11, 0x5b, 0x50, 0x63, 0xb2,
- 0x87, 0xca, 0x8c, 0x89, 0x09, 0x81, 0x52, 0x32, 0xc1, 0x5c, 0xa9, 0xbe, 0x1b, 0x77, 0xad, 0x67,
- 0x4d, 0xd2, 0x64, 0x24, 0x32, 0x9a, 0x00, 0xcf, 0xad, 0xd2, 0x04, 0x79, 0xde, 0x34, 0xb8, 0xdd,
- 0xef, 0x12, 0xaa, 0x35, 0x35, 0xa8, 0xca, 0x5e, 0xf3, 0x0b, 0xe3, 0x0f, 0xb4, 0x79, 0x67, 0xf2,
- 0x0f, 0x52, 0xa2, 0xe1, 0x12, 0x57, 0xa0, 0x33, 0xf3, 0xb8, 0x75, 0xcc, 0xd2, 0x29, 0xed, 0x21,
- 0x19, 0x41, 0xda, 0x67, 0x39, 0x60, 0x54, 0x2d, 0x51, 0x78, 0xc5, 0x34, 0x3b, 0x4b, 0xd5, 0x0a,
- 0x26, 0xa8, 0xde, 0x30, 0x3b, 0x60, 0xf1, 0x5b, 0x99, 0xff, 0xa3, 0x06, 0x71, 0x98, 0xca, 0xfa,
- 0x6f, 0x23, 0x74, 0x4d, 0x19, 0x49, 0xb2, 0x9b, 0x04, 0x68, 0x98, 0x03, 0xa8, 0x75, 0x5f, 0x44,
- 0x14, 0xe9, 0xa0, 0xa7, 0x23, 0x01, 0x3b, 0x77, 0x3e, 0xa1, 0x83, 0xc8, 0x44, 0xe6, 0x20, 0xab,
- 0x28, 0x48, 0xa1, 0xa0, 0xf0, 0x41, 0xc1, 0x83, 0x03, 0x62, 0x4e, 0x9f, 0x41, 0xfc, 0xb0, 0x93,
- 0x86, 0xc2, 0x12, 0x72, 0x42, 0xaf, 0xd3, 0x72, 0x6d, 0x89, 0xad, 0x54, 0xc9, 0xba, 0x29, 0xd7,
- 0x0e, 0x9d, 0x58, 0x3a, 0xb0, 0x85, 0x5d, 0x09, 0x1d, 0x1f, 0x03, 0xed, 0x9c, 0xce, 0xf3, 0x00,
- 0x42, 0xcb, 0xca, 0x06, 0x97, 0xff, 0xb6, 0xbc, 0x9b, 0xdc, 0xd5, 0x36, 0xf8, 0xd8, 0xd2, 0xc7,
- 0xfd, 0xf6, 0x07, 0x3c, 0x60, 0x12, 0x6c, 0x6d, 0xa3, 0x7d, 0xdd, 0x55, 0x7b, 0xf2, 0x31, 0xc3,
- 0x53, 0x8e, 0x30, 0xcc, 0x43, 0x08, 0xe6, 0x7a, 0x33, 0xca, 0xae, 0x24, 0x70, 0x80, 0x86, 0x59,
- 0xa2, 0x7c, 0x37, 0xc1, 0x2d, 0x54, 0x2b, 0x49, 0xc4, 0x5c, 0x7e, 0x47, 0xb7, 0xac, 0xac, 0x69,
- 0xa0, 0x22, 0x9b, 0xa0, 0xdc, 0xfa, 0x3f, 0xfe, 0xa4, 0x95, 0xca, 0x72, 0xa6, 0xdc, 0x84, 0x52,
- 0x51, 0xcb, 0x12, 0x72, 0xb8, 0xd5, 0x60, 0x95, 0x41, 0x91, 0x70, 0x6c, 0x68, 0x7c, 0xac, 0xa2,
- 0x0f, 0xe1, 0x3e, 0xc7, 0x22, 0x31, 0xba, 0x1b, 0x6d, 0x24, 0xa6, 0x2f, 0xf1, 0x75, 0xf3, 0x66,
- 0x13, 0x28, 0xb4, 0x1e, 0x86, 0x98, 0x47, 0x95, 0xc9, 0x0a, 0x40, 0x0b, 0xc4, 0x08, 0x80, 0x90,
- 0x7a, 0x9f, 0x66, 0x1b, 0x42, 0x8a, 0xa6, 0xb8, 0x7a, 0xc3, 0xab, 0x50, 0xc0, 0x83, 0x8b, 0xc8,
- 0x31, 0xc3, 0xee, 0x75, 0x91, 0x45, 0x80, 0xb8, 0x5d, 0x07, 0x08, 0xbc, 0x03, 0x22, 0x99, 0xac,
- 0x92, 0xab, 0x01, 0x87, 0x3e, 0xe5, 0xcc, 0x7d, 0xe4, 0x14, 0x28, 0x3b, 0xf5, 0x8e, 0x9f, 0x45,
- 0x24, 0xb0, 0x62, 0xd3, 0x02, 0x99, 0xb0, 0xe0, 0xeb, 0x03, 0xb8, 0x46, 0x8f, 0x47, 0x85, 0x6c,
- 0x65, 0x9d, 0x31, 0x80, 0xb8, 0x2f, 0x31, 0xff, 0xa8, 0x3a, 0x89, 0x47, 0xf9, 0x40, 0x06, 0xd3,
- 0xc3, 0x6b, 0x84, 0x01, 0x41, 0x1f, 0x4b, 0xee, 0x80, 0xed, 0xb2, 0xaa, 0xe9, 0x3d, 0x39, 0xa6,
- 0xe6, 0xf0, 0x70, 0x1f, 0xe6, 0x4e, 0xcf, 0xa1, 0x3d, 0xf3, 0x60, 0xd4, 0x39, 0xb8, 0x4b, 0x47,
- 0xb0, 0xc7, 0x7c, 0xae, 0x7b, 0x8d, 0x03, 0x23, 0xbb, 0xd8, 0x02, 0x85, 0x4e, 0x03, 0x5e, 0xf2,
- 0x0b, 0x0b, 0xc9, 0xec, 0x9a, 0x17, 0x23, 0x5f, 0x75, 0x1e, 0x64, 0x1d, 0x8a, 0x2e, 0xb4, 0x74,
- 0x6e, 0x4e, 0xff, 0x3a, 0xf2, 0x85, 0x5b, 0xe0, 0x43, 0xe9, 0x00, 0x99, 0xa3, 0x83, 0xe6, 0x2e,
- 0x3e, 0xa2, 0xd6, 0x00, 0x58, 0x6b, 0x9e, 0x4c, 0xe0, 0x03, 0xe3, 0x16, 0x15, 0x66, 0x64, 0x4a,
- 0x0d, 0xa8, 0xb9, 0x2c, 0x79, 0xdc, 0x55, 0xce, 0x4b, 0x5c, 0xc5, 0xf6, 0x5d, 0xf5, 0x5f, 0x36,
- 0x72, 0xe6, 0x26, 0x5e, 0xda, 0xe3, 0xef, 0xa8, 0xc5, 0x87, 0xce, 0x9f, 0x95, 0x5e, 0xc2, 0x9a,
- 0xf8, 0xd4, 0xf6, 0x56, 0x11, 0x98, 0x5a, 0xfb, 0x8f, 0x99, 0x4d, 0x54, 0x30, 0x94, 0xb4, 0x01,
- 0x0d, 0x58, 0x7a, 0xdb, 0x7d, 0x3b, 0x06, 0x2b, 0x76, 0x3a, 0xba, 0xf2, 0x87, 0x7d, 0x96, 0xf9,
- 0x9f, 0x4c, 0x10, 0x31, 0xec, 0xb0, 0x8f, 0x60, 0x9d, 0x06, 0x3a, 0x72, 0x2b, 0xa1, 0x95, 0x2d,
- 0x96, 0xf5, 0xe7, 0x1d, 0x82, 0x61, 0xc4, 0x5f, 0x60, 0xf2, 0x65, 0x2c, 0x4c, 0x79, 0xa5, 0x99,
- 0xdf, 0x24, 0x5f, 0x70, 0xed, 0x20, 0xca, 0x2b, 0x6d, 0xe0, 0x23, 0xc1, 0xfb, 0x4f, 0x65, 0xeb,
- 0xd3, 0xc2, 0xe3, 0x10, 0x5d, 0x85, 0xbe, 0xc1, 0xdc, 0x41, 0x92, 0xb6, 0xb6, 0x7e, 0xf1, 0x40,
- 0x0c, 0xfd, 0x8c, 0x3c, 0xad, 0x03, 0x57, 0x04, 0x35, 0xa2, 0x2f, 0x6c, 0x01, 0x81, 0x41, 0x99,
- 0xcc, 0xd7, 0xb6, 0x3b, 0x5d, 0xb7, 0xf9, 0x24, 0x47, 0x13, 0xe4, 0xc7, 0x30, 0xc0, 0xdb, 0x17,
- 0xfb, 0xa4, 0x5f, 0xae, 0x03, 0xf6, 0xe0, 0xed, 0x21, 0xec, 0x40, 0x39, 0xcd, 0xfa, 0x69, 0xde,
- 0x75, 0xa9, 0xe1, 0x42, 0x9c, 0xb0, 0xef, 0x8d, 0xa5, 0x17, 0x38, 0xe9, 0xca, 0x20, 0x62, 0xfb,
- 0x57, 0x15, 0x63, 0xbe, 0x3f, 0x72, 0x91, 0xc1, 0xd8, 0xe9, 0xab, 0x65, 0x1b, 0x64, 0x47, 0xb0,
- 0xad, 0x4c, 0xcc, 0xc5, 0x0c, 0x19, 0x9d, 0x96, 0xe6, 0x70, 0x9a, 0x00, 0x59, 0x1b, 0x3c, 0x5e,
- 0xc2, 0xcb, 0xb2, 0x18, 0xc7, 0xee, 0xe2, 0xe3, 0xd5, 0xa4, 0xb0, 0x96, 0x0f, 0x92, 0xea, 0x27,
- 0x29, 0xd2, 0x17, 0x7e, 0x2d, 0x58, 0x6e, 0x25, 0x62, 0x17, 0x84, 0x8c, 0x04, 0xc7, 0xc9, 0x04,
- 0x75, 0x96, 0x8f, 0xe0, 0xb6, 0x4f, 0xeb, 0x2f, 0xec, 0x8f, 0x09, 0x5a, 0xab, 0x7e, 0x61, 0xcd,
- 0xcf, 0xfc, 0xac, 0x92, 0x59, 0xb4, 0xfe, 0x31, 0xbb, 0x25, 0xd2, 0x0a, 0x68, 0xce, 0xb2, 0x4c,
- 0x61, 0x7e, 0xc5, 0x64, 0xa0, 0x9c, 0xa7, 0x3d, 0xbf, 0xfb, 0x63, 0x8a, 0xbc, 0x7f, 0x8c, 0x8d,
- 0x82, 0xfd, 0xd7, 0x7f, 0x6e, 0x20, 0x8a, 0x25, 0x36, 0x43, 0x25, 0x4c, 0x9f, 0x05, 0x57, 0xe0,
- 0x19, 0x25, 0xf4, 0x14, 0x5d, 0xe4, 0x3f, 0x3b, 0x76, 0x3e, 0xc8, 0xba, 0xc8, 0x8b, 0xca, 0x06,
- 0x3a, 0xa0, 0x06, 0x6e, 0x22, 0x47, 0xba, 0x97, 0x45, 0x06, 0x63, 0x23, 0x1b, 0x0f, 0xb3, 0x6f,
- 0x09, 0x77, 0x8f, 0x49, 0x01, 0x4d, 0x3f, 0x52, 0xa6, 0x3c, 0x4b, 0xdb, 0x95, 0x3d, 0x1b, 0xbe,
- 0xef, 0x50, 0x63, 0xaa, 0x3e, 0xca, 0xd6, 0x51, 0x43, 0xa9, 0x61, 0xe6, 0xec, 0xc2, 0x88, 0xca,
- 0x39, 0x68, 0x0d, 0xfc, 0xbe, 0xe4, 0xab, 0xaa, 0x78, 0x85, 0x77, 0xb1, 0x89, 0xbd, 0xf0, 0x4c,
- 0x1a, 0xaf, 0x41, 0x5f, 0xb3, 0xfe, 0x95, 0x96, 0x47, 0x76, 0x8c, 0xbe, 0x27, 0xd5, 0x5c, 0x1f,
- 0x48, 0x09, 0xc7, 0x23, 0x0c, 0x52, 0x82, 0x94, 0xd1, 0x60, 0x76, 0x67, 0x22, 0x84, 0x6c, 0x5b,
- 0x8a, 0xa3, 0x19, 0x92, 0xe4, 0xa4, 0x4f, 0xc8, 0x56, 0x47, 0xda, 0xfe, 0x95, 0xc9, 0x57, 0x08,
- 0xa6, 0x1f, 0x0a, 0x98, 0x0f, 0xcc, 0xc2, 0xff, 0x58, 0x1f, 0xb8, 0x5c, 0x0c, 0xd5, 0x68, 0xa4,
- 0x30, 0xc5, 0x66, 0x5c, 0x4d, 0x17, 0x78, 0xec, 0x8a, 0x6c, 0xe0, 0x9f, 0x4f, 0x74, 0xbf, 0xe3,
- 0x6c, 0xdb, 0x98, 0x27, 0x2c, 0xb8, 0x71, 0xe4, 0x72, 0x71, 0xf4, 0xa1, 0x33, 0x3a, 0xc9, 0x4d,
- 0xa5, 0x10, 0x03, 0xa7, 0xa6, 0x5e, 0xa3, 0x85, 0xed, 0xfa, 0x5b, 0x7d, 0x63, 0x43, 0x39, 0xe8,
- 0x29, 0x97, 0xc1, 0x83, 0xe2, 0x8d, 0x1d, 0xa2, 0x27, 0xbd, 0xa1, 0xe6, 0x68, 0xb9, 0x9b, 0xab,
- 0x9f, 0x46, 0x50, 0x1a, 0x0b, 0x25, 0x6f, 0x05, 0xc5, 0xc4, 0x1e, 0x29, 0x02, 0x6b, 0x2c, 0xb6,
- 0x74, 0x7c, 0xcb, 0x4c, 0x77, 0xab, 0xc3, 0xc6, 0xc8, 0xa2, 0x81, 0xaa, 0x6f, 0xe0, 0xba, 0x36,
- 0xa7, 0x05, 0xc7, 0xd0, 0x76, 0x6a, 0x55, 0x67, 0x59, 0x9d, 0xff, 0x75, 0xdb, 0x35, 0x2c, 0xe2,
- 0x51, 0x82, 0xce, 0x1f, 0x2c, 0x49, 0xdd, 0x04, 0x9e, 0xcf, 0xa2, 0xa1, 0x03, 0xf3, 0x3a, 0x79,
- 0xda, 0x59, 0xbc, 0x75, 0x76, 0xdd, 0xb0, 0xe3, 0x3e, 0xe3, 0xbc, 0x0b, 0xfe, 0x62, 0xed, 0xd5,
- 0x9a, 0x5f, 0x08, 0xb1, 0xab, 0xf3, 0xa9, 0x95, 0xa7, 0x5c, 0xe3, 0x7b, 0x58, 0xfb, 0xc1, 0x34,
- 0x09, 0x56, 0xb2, 0xab, 0x31, 0x46, 0xac, 0x3c, 0x56, 0x08, 0xcb, 0x0c, 0x08, 0xa0, 0x82, 0xf3,
- 0xc0, 0x91, 0xcd, 0xd0, 0x5d, 0x43, 0xa8, 0xbe, 0x46, 0x36, 0x8a, 0xfb, 0x25, 0x92, 0x18, 0x8d,
- 0xdd, 0x9d, 0xd6, 0xce, 0x99, 0xcc, 0x6d, 0x36, 0xa0, 0x8c, 0xab, 0x8f, 0xe0, 0x2f, 0x29, 0xbc,
- 0x02, 0xef, 0x25, 0xb6, 0xb2, 0xfc, 0x9f, 0x8f, 0xe8, 0xc1, 0x49, 0x0c, 0x5b, 0x77, 0x46, 0xf6,
- 0x60, 0xac, 0x9d, 0xd8, 0xd8, 0x6f, 0xee, 0xf0, 0x93, 0x9f, 0xe8, 0x38, 0x1f, 0x25, 0x3e, 0x9e,
- 0x5d, 0xef, 0x93, 0xef, 0xd4, 0x4d, 0x8a, 0xff, 0xa0, 0x78, 0xac, 0x91, 0x52, 0x02, 0x86, 0x60,
- 0x5a, 0xcb, 0x31, 0x6a, 0x29, 0xf8, 0xe9, 0xee, 0xec, 0x05, 0xf8, 0x4d, 0xdd, 0x70, 0xdc, 0x65,
- 0x84, 0x44, 0xac, 0x71, 0xdc, 0x74, 0x3a, 0xac, 0xa2, 0x09, 0xfd, 0x47, 0xb3, 0x0c, 0xef, 0x99,
- 0x43, 0x46, 0xc9, 0x2b, 0x95, 0x43, 0xc0, 0x59, 0xda, 0x3a, 0x43, 0x26, 0x99, 0x8a, 0x57, 0xf3,
- 0x5e, 0x41, 0x1f, 0x3e, 0x22, 0xf4, 0x57, 0x54, 0x98, 0x5a, 0xf5, 0x8c, 0x37, 0x0c, 0xca, 0xd4,
- 0x29, 0xb4, 0x9d, 0x1a, 0xf4, 0x45, 0x28, 0x2e, 0xe7, 0xfd, 0x52, 0xef, 0x3a, 0xee, 0xbe, 0x6e,
- 0xfc, 0xe1, 0x15, 0x3e, 0xfb, 0x89, 0x93, 0x81, 0xfe, 0x67, 0xa0, 0xaa, 0xe2, 0x11, 0x9e, 0xaa,
- 0xdf, 0x5a, 0x11, 0x6e, 0xae, 0x7c, 0xb5, 0xa6, 0x0f, 0xe8, 0x34, 0x00, 0x0d, 0x85, 0x8a, 0xfc,
- 0x2b, 0xa5, 0x7a, 0x3f, 0xf4, 0x17, 0x00, 0xde, 0x1c, 0x8b, 0x18, 0x2c, 0xc9, 0x8c, 0x02, 0x52,
- 0x77, 0x29, 0xd5, 0x92, 0x84, 0x70, 0xe7, 0xca, 0xfa, 0xe5, 0xc5, 0xe2, 0xaf, 0xdd, 0x73, 0x3c,
- 0xe8, 0x59, 0x2b, 0xf4, 0x2f, 0x3a, 0xe9, 0x40, 0x3d, 0xb4, 0x13, 0x12, 0x65, 0x36, 0xa5, 0x82,
- 0x2c, 0xd4, 0xa5, 0x0e, 0xcf, 0x8e, 0x63, 0x57, 0xff, 0xfc, 0x75, 0x87, 0x86, 0xda, 0xa8, 0x5e,
- 0x54, 0xde, 0xc2, 0x40, 0x9a, 0x4e, 0xfd, 0xd6, 0x41, 0xdf, 0x39, 0x03, 0x8a, 0x0a, 0xf1, 0x8a,
- 0x21, 0x74, 0x71, 0x83, 0x0e, 0x49, 0x64, 0x92, 0xce, 0x27, 0x3d, 0xed, 0x53, 0x48, 0x96, 0x13,
- 0x1d, 0xfb, 0x8b, 0x07, 0x56, 0x05, 0x13, 0x96, 0x47, 0x96, 0x5a, 0x92, 0x6b, 0x19, 0xef, 0x36,
- 0xaf, 0x6d, 0x98, 0x47, 0x85, 0x20, 0x0f, 0xed, 0xfe, 0xb6, 0xba, 0x45, 0xca, 0x42, 0x1f, 0xf5,
- 0x0d, 0x55, 0xe8, 0x24, 0x26, 0x6c, 0x30, 0xff, 0xe6, 0x55, 0xd7, 0xeb, 0xed, 0x12, 0x99, 0x14,
- 0x8e, 0xfb, 0x5b, 0x38, 0xb9, 0xfc, 0xdb, 0x9c, 0x70, 0x8d, 0x63, 0x1d, 0xc6, 0xef, 0x5b, 0x9b,
- 0xa4, 0x30, 0x4d, 0x23, 0x17, 0xb6, 0x0e, 0xf0, 0x8a, 0xd2, 0x50, 0x7e, 0x44, 0x34, 0x59, 0xe9,
- 0xc9, 0x34, 0x3e, 0xf6, 0x75, 0x6d, 0xfc, 0xc0, 0x8a, 0xfd, 0xf9, 0x73, 0xb4, 0x0c, 0xe1, 0x23,
- 0xcd, 0x45, 0x62, 0xec, 0x3e, 0xaa, 0x8e, 0xd3, 0x86, 0xcf, 0x53, 0xd7, 0x93, 0x62, 0x47, 0x23,
- 0xd9, 0x18, 0x06, 0xa2, 0x35, 0xef, 0x73, 0x57, 0x50, 0xc9, 0xdc, 0xbb, 0xb7, 0x05, 0xc6, 0x52,
- 0x44, 0xe8, 0x15, 0x6b, 0x5b, 0xd2, 0xf3, 0xf3, 0xd4, 0x1c, 0xa4, 0xaf, 0x73, 0x6a, 0x91, 0x81,
- 0x0b, 0xe8, 0x15, 0xed, 0x54, 0x60, 0xc2, 0x0e, 0xc8, 0xf9, 0x69, 0xbb, 0xac, 0x55, 0xcc, 0x36,
- 0xaf, 0x04, 0x3c, 0x2f, 0xc9, 0xbf, 0x1c, 0xc6, 0x99, 0x48, 0x0c, 0x5d, 0xd7, 0x16, 0xf0, 0x46,
- 0x8d, 0x59, 0x7b, 0x78, 0x49, 0xa4, 0xb5, 0x4c, 0x60, 0xa1, 0x24, 0x58, 0x61, 0x38, 0xa1, 0x46,
- 0x37, 0x02, 0xd0, 0x73, 0x52, 0xa5, 0x4b, 0xb3, 0xc9, 0xd9, 0x32, 0x43, 0xa6, 0x6a, 0xce, 0x14,
- 0xba, 0xe5, 0x71, 0xfc, 0x5e, 0xd6, 0xc3, 0x46, 0x4a, 0x4e, 0xfd, 0x6b, 0xa1, 0x75, 0xd0, 0x22,
- 0x6b, 0xe6, 0x1f, 0xc4, 0x1d, 0x1f, 0x22, 0x69, 0x09, 0x24, 0x1b, 0x92, 0x38, 0x42, 0xaa, 0x67,
- 0x52, 0x76, 0xba, 0xae, 0x9e, 0x3e, 0x68, 0x66, 0x96, 0xd4, 0x79, 0xb0, 0xeb, 0xe6, 0x86, 0x29,
- 0x2b, 0x74, 0x16, 0x22, 0x9f, 0xb6, 0xe6, 0xbd, 0xe3, 0xf9, 0xaa, 0x5f, 0xcf, 0xe1, 0xcb, 0xdb,
- 0xd4, 0x91, 0x13, 0xb2, 0x30, 0x52, 0xe1, 0xde, 0xbc, 0xef, 0x94, 0xe9, 0x2c, 0xfe, 0xd0, 0xdb,
- 0x44, 0x46, 0x24, 0xeb, 0x2f, 0xf7, 0x54, 0x7c, 0x49, 0x50, 0x1f, 0x64, 0xdb, 0xc1, 0xa6, 0x98,
- 0x5e, 0xd6, 0xce, 0xc2, 0xec, 0x76, 0x39, 0xa7, 0x27, 0xc3, 0x9c, 0x2f, 0xc9, 0xf8, 0xd0, 0xa3,
- 0xb4, 0x77, 0xea, 0xd6, 0xab, 0xbd, 0x64, 0xaf, 0x07, 0x77, 0x8f, 0x20, 0x59, 0x9e, 0x48, 0x02,
- 0x74, 0xb5, 0x45, 0x93, 0x74, 0x52, 0xba, 0x9c, 0x3b, 0xcd, 0x75, 0x7f, 0x4b, 0x4d, 0x15, 0x4a,
- 0x65, 0x90, 0x67, 0x3f, 0xdc, 0x55, 0x29, 0x69, 0xbb, 0x4d, 0x5a, 0xe9, 0x1d, 0xf4, 0x5d, 0xf5,
- 0x8a, 0x9f, 0x62, 0x2d, 0x12, 0xb3, 0x31, 0xdf, 0x52, 0x77, 0xfe, 0x34, 0xf5, 0xdf, 0xa3, 0xb7,
- 0x04, 0x94, 0x8e, 0xc2, 0xa7, 0xd4, 0xfa, 0x8f, 0xd9, 0x86, 0x56, 0x8b, 0x1b, 0xf0, 0x64, 0xea,
- 0x3b, 0x08, 0x59, 0x58, 0x23, 0xeb, 0x9a, 0x3d, 0xb7, 0xea, 0xb4, 0x28, 0xbe, 0x15, 0x6d, 0x0e,
- 0x0b, 0x25, 0x4d, 0x5e, 0x2d, 0xf7, 0x65, 0xdf, 0x21, 0x26, 0x89, 0x75, 0x1b, 0xbe, 0x94, 0x10,
- 0xb4, 0x77, 0xee, 0x03, 0xc6, 0x34, 0x98, 0xdb, 0x82, 0x02, 0xac, 0x50, 0x2e, 0xec, 0x94, 0x2e,
- 0xb3, 0x7b, 0x78, 0x82, 0xa9, 0x48, 0x82, 0xff, 0xa8, 0x7b, 0x82, 0x9f, 0xf1, 0xa8, 0x7e, 0x57,
- 0x82, 0xad, 0xab, 0x88, 0x8b, 0x8f, 0xc0, 0x9c, 0xa1, 0x26, 0xb5, 0xa4, 0xc0, 0x0c, 0xf0, 0x46,
- 0x4c, 0x9f, 0x04, 0x79, 0x80, 0x33, 0x3b, 0x9b, 0x91, 0x34, 0x67, 0x06, 0x2f, 0x89, 0x46, 0xf3,
- 0x90, 0x7a, 0xba, 0x7f, 0x03, 0x0d, 0xcb, 0xad, 0xa9, 0x4c, 0xd3, 0x50, 0x1d, 0x8a, 0x26, 0x16,
- 0x05, 0x30, 0x76, 0x8a, 0x77, 0x06, 0x86, 0x01, 0x43, 0x9d, 0xbf, 0xf8, 0xfe, 0xe8, 0xfc, 0xe3,
- 0xd2, 0x52, 0xf7, 0x71, 0xfa, 0x14, 0xb0, 0x62, 0xe4, 0x76, 0x4c, 0xba, 0x6f, 0x35, 0x55, 0xf1,
- 0x3b, 0x0a, 0xcb, 0x6c, 0x4e, 0x2d, 0x1d, 0x50, 0xb1, 0x99, 0xa4, 0x57, 0xd1, 0x26, 0x2f, 0x90,
- 0x66, 0x9c, 0xb2, 0x40, 0xb4, 0xb6, 0xa4, 0xb9, 0xa4, 0xff, 0x4b, 0x88, 0x1e, 0xbc, 0xe2, 0xd8,
- 0xba, 0xc9, 0x14, 0xbb, 0x79, 0x85, 0x27, 0xdc, 0xb1, 0xde, 0xd7, 0x0a, 0x0f, 0x92, 0xf7, 0x7c,
- 0xe9, 0xe9, 0x9a, 0x67, 0xeb, 0x6a, 0xf5, 0x67, 0xbc, 0x3b, 0xf3, 0x12, 0xd9, 0x4e, 0x26, 0x8c,
- 0x82, 0x17, 0x3f, 0x4d, 0x75, 0xdb, 0x6a, 0xb7, 0x4e, 0x4b, 0x78, 0x32, 0xbe, 0x22, 0x11, 0x99,
- 0x23, 0x5e, 0xfa, 0xda, 0xd8, 0x20, 0x25, 0x2f, 0x49, 0x0e, 0x04, 0xbe, 0xe2, 0x95, 0x7f, 0x5d,
- 0xc0, 0x05, 0x41, 0x55, 0xc2, 0x15, 0x43, 0x38, 0xb1, 0xf6, 0x38, 0xb2, 0x3a, 0x6f, 0x91, 0x05,
- 0x5a, 0xf9, 0xfa, 0xce, 0x79, 0x56, 0x16, 0xfd, 0x41, 0xe1, 0x42, 0x89, 0x77, 0x3e, 0x63, 0x69,
- 0xd4, 0x06, 0x43, 0x81, 0x25, 0x10, 0x4b, 0x5c, 0x3b, 0xbb, 0x5c, 0x19, 0x77, 0x01, 0x01, 0xad,
- 0x58, 0xa7, 0x88, 0x7e, 0x1c, 0x04, 0x00, 0x13, 0xa5, 0x65, 0x91, 0x3b, 0xb8, 0x4a, 0x4d, 0xe1,
- 0x9c, 0x7d, 0x91, 0x74, 0x64, 0x36, 0x15, 0xff, 0xe8, 0xf7, 0x0d, 0x86, 0x7d, 0xcb, 0x55, 0xbc,
- 0x09, 0x01, 0x71, 0xd5, 0x91, 0xd2, 0xd9, 0x83, 0xa1, 0x82, 0x69, 0xeb, 0x93, 0x99, 0x51, 0x40,
- 0xfe, 0xc4, 0xbe, 0x95, 0x16, 0x95, 0x42, 0x9c, 0xfa, 0x30, 0x87, 0x72, 0x92, 0x46, 0x42, 0x20,
- 0xa2, 0x9c, 0xae, 0xdb, 0x5a, 0x26, 0xc9, 0x1a, 0x9c, 0x0a, 0xed, 0xa9, 0x48, 0x61, 0x3c, 0xa3,
- 0x6a, 0xa9, 0xef, 0x2b, 0x67, 0x8f, 0xe4, 0x8f, 0xef, 0xd2, 0xd5, 0xf6, 0x9f, 0x63, 0x5d, 0x8c,
- 0x4f, 0x28, 0xc1, 0xc8, 0x3c, 0x20, 0x22, 0x58, 0x53, 0x3d, 0xab, 0xbd, 0x76, 0x54, 0x40, 0xe2,
- 0xdb, 0xc6, 0x79, 0xdf, 0x47, 0x61, 0xfe, 0x3c, 0xf6, 0x0e, 0xe2, 0x1f, 0xd4, 0x4a, 0x3d, 0x4a,
- 0x1a, 0xbe, 0x45, 0x27, 0x74, 0xd7, 0xe9, 0x74, 0x7d, 0xd1, 0x54, 0x56, 0xd6, 0xd7, 0xcf, 0xa0,
- 0x5c, 0x70, 0xbd, 0xa3, 0xbb, 0x91, 0x98, 0x23, 0x4c, 0x57, 0xc7, 0xcf, 0xc8, 0x0e, 0x91, 0x1f,
- 0x3c, 0x2f, 0x1e, 0x98, 0x2c, 0xf6, 0xe2, 0x13, 0x67, 0x95, 0xb4, 0xb4, 0xdc, 0x4e, 0x69, 0x9f,
- 0x99, 0x3d, 0x1c, 0xb6, 0x80, 0xe8, 0xc9, 0x38, 0xd2, 0x29, 0xca, 0x0a, 0x18, 0x53, 0xdc, 0x5b,
- 0x4b, 0x91, 0x8b, 0xde, 0x3f, 0xd1, 0x3b, 0x01, 0x83, 0xb5, 0xf5, 0xd3, 0x13, 0x7a, 0x0e, 0xcf,
- 0xa5, 0x3d, 0xba, 0x9f, 0x5d, 0xb4, 0x40, 0x21, 0x79, 0x22, 0x7d, 0xbd, 0xca, 0x0c, 0x1f, 0xb9,
- 0xcd, 0x7d, 0x44, 0x86, 0x23, 0xc3, 0xa8, 0x36, 0xda, 0xc4, 0xb1, 0xf5, 0x77, 0x96, 0xa4, 0x5e,
- 0x85, 0x55, 0x95, 0x05, 0x3b, 0x9c, 0x12, 0x95, 0x4a, 0x30, 0xed, 0x5e, 0xc0, 0xb4, 0x2d, 0xed,
- 0xda, 0x63, 0x49, 0xc7, 0xed, 0x96, 0xa3, 0xc0, 0xf4, 0x02, 0x5f, 0x41, 0x99, 0x79, 0xf2, 0x16,
- 0x42, 0x20, 0x14, 0x3a, 0x89, 0xa0, 0x4b, 0x52, 0x88, 0xdf, 0x1d, 0xf2, 0x5f, 0x5c, 0x8d, 0xb3,
- 0xf0, 0x58, 0x37, 0x3d, 0xfd, 0xb9, 0x23, 0xb5, 0xe0, 0xbb, 0xa9, 0x59, 0x60, 0x2a, 0xa9, 0xcc,
- 0xfd, 0xef, 0xc0, 0x08, 0xcf, 0x54, 0xc0, 0xed, 0xa9, 0xd3, 0x3c, 0xbe, 0x24, 0xe7, 0xb9, 0xd1,
- 0x7d, 0xd1, 0x08, 0xa1, 0xd0, 0xe2, 0x6f, 0x20, 0x8d, 0xa3, 0x87, 0x20, 0x83, 0x82, 0x24, 0x3f,
- 0x3b, 0x15, 0x48, 0x10, 0x89, 0x04, 0xc6, 0x1e, 0x46, 0xba, 0x49, 0x88, 0x05, 0x15, 0xcf, 0xd8,
- 0xc8, 0xa7, 0xdb, 0xca, 0x46, 0x07, 0x6a, 0x94, 0x60, 0xbc, 0x9b, 0x2b, 0xa6, 0xb0, 0x24, 0x31,
- 0xe9, 0x5a, 0x11, 0x96, 0x22, 0x48, 0x63, 0xb6, 0xb1, 0x43, 0x97, 0xf4, 0x98, 0x09, 0xd4, 0xf3,
- 0x99, 0xd1, 0xfd, 0xb6, 0xe1, 0x3e, 0x27, 0x4a, 0xc4, 0x96, 0x7f, 0x0d, 0x18, 0xd4, 0xd9, 0x31,
- 0x3a, 0x80, 0xfc, 0x64, 0x62, 0x86, 0x8c, 0xdd, 0xd8, 0x45, 0x2c, 0x43, 0x53, 0x03, 0x93, 0x46,
- 0xf9, 0x38, 0x08, 0x7d, 0xc0, 0xb1, 0x5d, 0xc9, 0xe3, 0xff, 0x06, 0x5e, 0x13, 0x3e, 0x9d, 0x7a,
- 0x7e, 0x58, 0x61, 0xb9, 0xc8, 0x9f, 0xf0, 0xaf, 0x9f, 0xe9, 0x6b, 0x3d, 0x66, 0xd2, 0xb0, 0x90,
- 0x8f, 0xd4, 0x79, 0xa9, 0xbd, 0x49, 0x2e, 0x9b, 0xd9, 0xe6, 0x87, 0x34, 0x13, 0x84, 0x70, 0xf8,
- 0xe1, 0x6a, 0x64, 0x18, 0x3f, 0xf2, 0xed, 0x77, 0xc1, 0xf7, 0xbc, 0xaf, 0xf3, 0xb3, 0x21, 0x26,
- 0x22, 0x72, 0x49, 0x26, 0x07, 0xd1, 0x99, 0x47, 0x54, 0x4d, 0x52, 0xa7, 0xe2, 0x60, 0xa3, 0x7a,
- 0xb2, 0x24, 0x94, 0xe0, 0xe4, 0xc2, 0xcc, 0x3e, 0x7c, 0x8f, 0x7f, 0x81, 0x61, 0xb4, 0xa4, 0x81,
- 0x54, 0xa0, 0xfa, 0xdf, 0xb5, 0x5f, 0xee, 0xe2, 0xc2, 0x3b, 0x29, 0x2a, 0x70, 0xc5, 0x77, 0x81,
- 0x40, 0x01, 0x67, 0x9f, 0x75, 0x2b, 0x05, 0xa2, 0x5a, 0x8d, 0x71, 0x60, 0x17, 0x53, 0xf8, 0x8c,
- 0xe8, 0x8b, 0x54, 0x85, 0xdd, 0x18, 0x23, 0x94, 0x75, 0x84, 0x89, 0x74, 0x67, 0xd1, 0xfd, 0xe3,
- 0xca, 0x07, 0xf9, 0x08, 0x95, 0xbc, 0xe3, 0xce, 0xf5, 0x58, 0xed, 0x0e, 0xc4, 0x46, 0xc2, 0x20,
- 0xcd, 0x10, 0xb9, 0x3b, 0x46, 0x87, 0xda, 0xa7, 0x7d, 0x64, 0x65, 0x06, 0x0a, 0xda, 0xf2, 0xa3,
- 0x3e, 0xc4, 0x84, 0xe0, 0x4d, 0x27, 0xc1, 0xde, 0x6d, 0x06, 0x51, 0x20, 0x9c, 0xc0, 0x17, 0x89,
- 0xbf, 0x24, 0x22, 0xdd, 0x71, 0x20, 0xfa, 0xc6, 0xc1, 0x09, 0x55, 0xce, 0xc7, 0x91, 0x64, 0xcc,
- 0x00, 0xa1, 0xd6, 0x62, 0xbf, 0x1b, 0x76, 0x16, 0x00, 0x4e, 0xa2, 0x20, 0xf7, 0x22, 0x6b, 0xa0,
- 0x63, 0xa8, 0x5d, 0x35, 0xd6, 0xbb, 0xfb, 0xb8, 0x08, 0xed, 0x89, 0x04, 0xc9, 0xb1, 0x91, 0xe5,
- 0x7e, 0xe1, 0xf1, 0x21, 0x30, 0xed, 0x01, 0x3a, 0x04, 0x01, 0x11, 0xc9, 0x6d, 0x67, 0xb2, 0x68,
- 0x09, 0x14, 0xa6, 0x10, 0x39, 0x9d, 0xcc, 0x87, 0x98, 0x0a, 0x6b, 0xd7, 0x7d, 0xd3, 0xce, 0x77,
- 0x56, 0x0b, 0x5f, 0xdf, 0x6a, 0x04, 0xf1, 0x13, 0x8b, 0x54, 0x11, 0x2b, 0x31, 0xc8, 0xff, 0xcf,
- 0x52, 0xab, 0xdb, 0x13, 0xfc, 0x06, 0xed, 0xcc, 0x31, 0x00, 0xbf, 0xd8, 0x7b, 0x9b, 0xea, 0xcf,
- 0x80, 0xc9, 0x3c, 0x95, 0xe2, 0x07, 0x39, 0x8c, 0x70, 0x54, 0x70, 0x3e, 0x4a, 0x8d, 0xa1, 0xfc,
- 0x82, 0x4b, 0xc2, 0x14, 0xb0, 0xc9, 0x86, 0x66, 0x0b, 0x9d, 0xce, 0xf0, 0x3b, 0x04, 0xd0, 0xc1,
- 0x83, 0x40, 0x4e, 0x7b, 0x6f, 0x1b, 0x55, 0x11, 0x76, 0x91, 0x16, 0x66, 0xaa, 0x24, 0x99, 0x95,
- 0xb4, 0x26, 0x1f, 0x29, 0xc3, 0x05, 0x7f, 0x0a, 0x72, 0x83, 0x6a, 0x4c, 0xa7, 0x1a, 0xd0, 0x6e,
- 0xab, 0xeb, 0xbf, 0x17, 0x1f, 0x15, 0x3e, 0xac, 0xdd, 0x1d, 0x30, 0xc2, 0x1c, 0x2c, 0xd3, 0xf3,
- 0x68, 0xd7, 0x8e, 0x11, 0x52, 0x45, 0x8f, 0xd9, 0xd6, 0x0f, 0x4c, 0x4f, 0x8d, 0x0a, 0x4c, 0x80,
- 0x0d, 0x4d, 0x1b, 0x14, 0x9f, 0x26, 0xa0, 0x5f, 0x7d, 0xd4, 0xbb, 0x83, 0x36, 0x5a, 0xd7, 0x4a,
- 0x61, 0xd5, 0x34, 0x8a, 0x89, 0xd5, 0x4c, 0x76, 0xda, 0x68, 0x79, 0xf4, 0x33, 0x05, 0x9a, 0x6e,
- 0xbb, 0x87, 0x65, 0xed, 0x62, 0x6c, 0xfa, 0x9d, 0xc9, 0xcc, 0x98, 0xe4, 0x38, 0xd4, 0xec, 0xbb,
- 0x8a, 0x28, 0x87, 0x23, 0x7a, 0x00, 0x8c, 0x15, 0x5d, 0x78, 0x61, 0xf3, 0xf7, 0x44, 0x64, 0xbb,
- 0x38, 0x65, 0xd9, 0x84, 0x0c, 0x56, 0xf7, 0x43, 0xc5, 0x96, 0x64, 0xcb, 0xef, 0x85, 0xa8, 0x2a,
- 0x9d, 0x1e, 0x47, 0x23, 0xf5, 0x14, 0x0f, 0xbf, 0x6f, 0x23, 0x12, 0x64, 0x38, 0xa8, 0x87, 0x96,
- 0xa2, 0x3d, 0xfd, 0x52, 0xb0, 0x49, 0x4c, 0xae, 0x09, 0xf0, 0x4e, 0x28, 0x5b, 0xb5, 0xe1, 0x7f,
- 0x10, 0xd1, 0x84, 0x43, 0xde, 0xb7, 0xd3, 0xdb, 0x9b, 0x1f, 0x78, 0x8e, 0xd9, 0x19, 0x11, 0x08,
- 0x7b, 0x3a, 0xd1, 0x97, 0xb4, 0xc7, 0x75, 0x4d, 0x79, 0xf5, 0xf0, 0x6b, 0xfe, 0xc7, 0x54, 0x17,
- 0x37, 0x70, 0x38, 0x92, 0xc3, 0x9c, 0xee, 0xca, 0xfe, 0xf5, 0xb3, 0x26, 0x45, 0xfa, 0x37, 0x80,
- 0x28, 0x5c, 0xda, 0x6e, 0x06, 0x98, 0x75, 0xd6, 0x2c, 0x79, 0xe0, 0xe3, 0x9a, 0x07, 0x3c, 0x57,
- 0xf6, 0xbd, 0x7b, 0xca, 0x91, 0x70, 0xfb, 0x00, 0xc9, 0x5b, 0x6d, 0x09, 0xf8, 0x4f, 0xd5, 0x4a,
- 0x9d, 0x3f, 0x00, 0xfe, 0x4f, 0x59, 0x9f, 0xa1, 0x5b, 0xe2, 0x40, 0x65, 0x8f, 0xba, 0x1a, 0xd6,
- 0x87, 0x68, 0x6d, 0xda, 0x87, 0x78, 0x08, 0xa8, 0x23, 0xdf, 0xdb, 0xa9, 0x85, 0x9d, 0x91, 0xe1,
- 0x77, 0x72, 0xc3, 0x74, 0x55, 0x6a, 0x56, 0xdf, 0x33, 0xf1, 0x15, 0x05, 0x7d, 0xd7, 0x69, 0x96,
- 0xf9, 0x08, 0xa4, 0x4b, 0xd0, 0x11, 0xa2, 0xe2, 0xf6, 0x0a, 0x94, 0x8c, 0x1a, 0x14, 0x52, 0xe8,
- 0xf2, 0xa9, 0x89, 0x23, 0x01, 0x0a, 0xa8, 0xf3, 0xaa, 0x7e, 0x9a, 0x1e, 0x70, 0xb3, 0xaf, 0xf6,
- 0x77, 0xf8, 0xc5, 0x81, 0x6e, 0x2c, 0xbd, 0x2a, 0x6c, 0x13, 0x9e, 0xd1, 0x30, 0xde, 0xe1, 0xd8,
- 0xc7, 0x43, 0xa6, 0x39, 0x6d, 0x80, 0xc1, 0x51, 0x30, 0x30, 0x7e, 0xe5, 0x2b, 0x04, 0x76, 0x5d,
- 0x41, 0x5c, 0x15, 0x11, 0xb9, 0x0d, 0xe9, 0x8b, 0xd3, 0x6e, 0x35, 0x79, 0xd1, 0x69, 0x75, 0xe6,
- 0x08, 0x0c, 0x8e, 0x90, 0x00, 0xa0, 0x4d, 0x78, 0x19, 0xa5, 0x5f, 0x41, 0x38, 0x16, 0xea, 0x1b,
- 0x19, 0xce, 0xba, 0xb8, 0x6e, 0x46, 0x31, 0x9a, 0x38, 0x91, 0xd2, 0xbe, 0x9b, 0x9d, 0xbc, 0x3b,
- 0x75, 0x37, 0x04, 0x95, 0x27, 0x50, 0x95, 0x9a, 0x79, 0x63, 0x36, 0x91, 0xc4, 0x6e, 0x0d, 0x77,
- 0xb7, 0x53, 0xe9, 0x16, 0x01, 0xc6, 0x03, 0x6b, 0x8f, 0xb7, 0xb6, 0x36, 0x01, 0x11, 0x20, 0x87,
- 0x5c, 0x5d, 0x62, 0xbf, 0x2f, 0x7b, 0x05, 0xdd, 0x3a, 0x09, 0x4b, 0xdc, 0x30, 0x8f, 0x38, 0x1e,
- 0xc1, 0xee, 0xd1, 0x0f, 0xe6, 0xe4, 0x95, 0x0a, 0x13, 0x0e, 0x45, 0xf9, 0xf3, 0xcd, 0xee, 0x52,
- 0x38, 0x0e, 0x86, 0x9b, 0xc4, 0x23, 0x2d, 0x49, 0xac, 0x77, 0x9b, 0x48, 0xf0, 0xde, 0x9b, 0x14,
- 0xd0, 0x3f, 0xba, 0x6a, 0x74, 0xb0, 0x9f, 0x52, 0xc9, 0xb0, 0x7e, 0xbe, 0xa5, 0xaf, 0xa9, 0x9b,
- 0x03, 0xc9, 0x30, 0x08, 0x66, 0x41, 0xf8, 0x22, 0x37, 0x69, 0x06, 0x34, 0xd5, 0xc2, 0xc6, 0x0a,
- 0x25, 0x6c, 0xaf, 0xed, 0x72, 0xb1, 0x71, 0xb3, 0xcb, 0xd9, 0x2d, 0xba, 0xb2, 0x13, 0x34, 0xf5,
- 0x09, 0xa3, 0xe5, 0x1a, 0x24, 0xcb, 0x47, 0x28, 0x1e, 0xcf, 0xf9, 0x29, 0x89, 0x22, 0xa9, 0xbf,
- 0x1d, 0x94, 0x03, 0x69, 0x7f, 0xeb, 0xa5, 0x4b, 0x39, 0x59, 0xfa, 0xbd, 0xec, 0x3e, 0xb7, 0x33,
- 0x62, 0x51, 0x65, 0xa9, 0x78, 0x6c, 0xdc, 0xb7, 0xca, 0x7f, 0xfa, 0x54, 0x25, 0x00, 0xe9, 0x9f,
- 0xa6, 0x4b, 0x0e, 0x24, 0x34, 0xee, 0x0f, 0x17, 0x9b, 0x6a, 0xe3, 0xe4, 0xee, 0x4d, 0x83, 0xa4,
- 0x79, 0x75, 0x8c, 0x46, 0x12, 0x6f, 0x28, 0x50, 0xef, 0x1f, 0x70, 0x9c, 0x49, 0x70, 0x7c, 0xd9,
- 0x19, 0x30, 0x43, 0x07, 0x49, 0x1f, 0xba, 0x7f, 0x1b, 0x17, 0xec, 0x01, 0x92, 0xcf, 0xd9, 0x32,
- 0xfa, 0xf2, 0xd9, 0x40, 0xf2, 0xb8, 0xaf, 0xa2, 0x42, 0xeb, 0x11, 0x36, 0xf9, 0x6b, 0x7c, 0x27,
- 0x68, 0x4c, 0xd6, 0x18, 0x76, 0x40, 0x31, 0xaf, 0x76, 0x38, 0x82, 0x97, 0x8b, 0xc5, 0x15, 0x41,
- 0x80, 0xdd, 0xab, 0xf1, 0x67, 0x00, 0x42, 0xfc, 0x37, 0x37, 0xe8, 0x29, 0x39, 0xea, 0x8c, 0x1c,
- 0x48, 0xe6, 0xb0, 0x5d, 0xa3, 0xae, 0x17, 0x6a, 0xe6, 0x5b, 0x5c, 0x71, 0x40, 0xc4, 0x5a, 0x8c,
- 0xee, 0x95, 0x0a, 0x0e, 0xcd, 0x4b, 0xbb, 0x4d, 0x66, 0x81, 0x9a, 0xc7, 0xf6, 0xe8, 0xf7, 0x99,
- 0x2e, 0x77, 0x3f, 0x3a, 0x4d, 0xa9, 0x12, 0xcc, 0x2a, 0x7d, 0xe3, 0xe8, 0x37, 0x6b, 0x9e, 0xd4,
- 0x38, 0x53, 0x30, 0x18, 0xbd, 0xf5, 0xb7, 0x61, 0x59, 0x64, 0xea, 0x9e, 0x55, 0x86, 0xe6, 0x1a,
- 0xce, 0x94, 0xe1, 0x34, 0x82, 0x6b, 0xcf, 0x3b, 0x5f, 0x86, 0x76, 0x74, 0xdf, 0x72, 0xf5, 0xa8,
- 0x08, 0x87, 0x50, 0x27, 0xc2, 0x9a, 0x98, 0x78, 0xe4, 0x09, 0x14, 0xc2, 0x65, 0x4b, 0x7a, 0xc9,
- 0xd9, 0x62, 0x1d, 0xb2, 0xa1, 0xc1, 0xab, 0x7e, 0xa0, 0x08, 0x9b, 0xd7, 0xb6, 0xcd, 0xe0, 0x40,
- 0xf7, 0xc6, 0xea, 0x41, 0xf1, 0xf4, 0x27, 0x93, 0x7e, 0xf6, 0x5f, 0x23, 0x76, 0x79, 0x48, 0x91,
- 0x45, 0x09, 0x08, 0xd8, 0xa2, 0x37, 0x49, 0x49, 0x85, 0x47, 0xa6, 0xdc, 0x21, 0x3d, 0xd0, 0x58,
- 0xac, 0x9e, 0xd2, 0x06, 0x02, 0x28, 0xbb, 0xb8, 0xd7, 0xb4, 0x35, 0x5d, 0x10, 0x95, 0xd6, 0xc8,
- 0x1c, 0xc5, 0x02, 0x8e, 0x57, 0x83, 0x51, 0x28, 0x25, 0xfd, 0x21, 0xd5, 0x3b, 0xe8, 0x22, 0x77,
- 0xe2, 0x99, 0x18, 0x61, 0x85, 0xce, 0x11, 0x70, 0x71, 0x2f, 0x99, 0x6e, 0x35, 0x43, 0xfa, 0x77,
- 0x24, 0xf8, 0x60, 0xb7, 0x06, 0x9c, 0x9a, 0xad, 0x55, 0xe6, 0x13, 0xa2, 0x28, 0x47, 0xb5, 0x17,
- 0x6c, 0xca, 0x9a, 0x97, 0x24, 0x52, 0x8a, 0xcb, 0x93, 0x85, 0x59, 0x52, 0x8a, 0x7a, 0xd6, 0xde,
- 0xc3, 0x10, 0x7e, 0x5d, 0x90, 0xe3, 0xb0, 0x8f, 0x51, 0x29, 0x36, 0xec, 0x9d, 0x7b, 0xd5, 0xed,
- 0x09, 0xd6, 0x23, 0x5b, 0xdc, 0x23, 0x4e, 0xeb, 0x28, 0x69, 0x66, 0xb5, 0x95, 0x05, 0x55, 0x2e,
- 0x5e, 0x2e, 0x90, 0x62, 0x1f, 0xdf, 0x7b, 0x71, 0xe7, 0x49, 0xb9, 0xda, 0x40, 0x59, 0x77, 0xc3,
- 0xde, 0x82, 0x16, 0xb2, 0x37, 0x1d, 0x37, 0x73, 0xae, 0xdd, 0xe0, 0x89, 0x44, 0x3e, 0x0f, 0x30,
- 0x73, 0xb4, 0x70, 0x18, 0xb2, 0x4f, 0xe1, 0x75, 0x97, 0x56, 0x16, 0x21, 0x77, 0x89, 0xb8, 0x13,
- 0x17, 0xf9, 0xdb, 0xee, 0xbe, 0x43, 0x1c, 0xd6, 0x62, 0x74, 0x4f, 0x0d, 0xb7, 0xb1, 0x35, 0x94,
- 0x44, 0x6b, 0x88, 0xf8, 0xd3, 0x00, 0x07, 0x5d, 0x17, 0x97, 0x68, 0x20, 0x22, 0x2d, 0xee, 0xd5,
- 0xf5, 0x55, 0x0d, 0xad, 0xfc, 0x7a, 0xbd, 0xd9, 0xa9, 0xa3, 0xb9, 0xda, 0x78, 0xa5, 0x06, 0x8a,
- 0x1e, 0x9a, 0x4b, 0xf1, 0x6c, 0x14, 0xca, 0x5b, 0x9d, 0x54, 0x46, 0x71, 0xa4, 0xf9, 0x29, 0xa9,
- 0xf6, 0x29, 0x7c, 0xec, 0x3d, 0xc9, 0x2d, 0x8d, 0xa0, 0xb6, 0x5e, 0xc5, 0x5a, 0x74, 0xde, 0xda,
- 0x0f, 0x7e, 0xe6, 0x73, 0x58, 0x2f, 0x5b, 0x51, 0x40, 0xbd, 0xfd, 0x91, 0x9e, 0xa3, 0x71, 0x09,
- 0xef, 0x77, 0xce, 0xc5, 0xd5, 0x6c, 0x87, 0xf2, 0xcd, 0xf0, 0x0b, 0xdc, 0x29, 0xe8, 0x95, 0x55,
- 0x4a, 0x23, 0x03, 0x86, 0x9d, 0x16, 0xfe, 0x97, 0x86, 0xc1, 0xc9, 0x28, 0xf1, 0x0b, 0x98, 0x31,
- 0xe4, 0xea, 0xee, 0xe3, 0xf0, 0xa2, 0x9e, 0x43, 0xbe, 0x2c, 0x46, 0xa1, 0x09, 0x08, 0x26, 0x08,
- 0x6f, 0x50, 0x94, 0x0e, 0x37, 0xb3, 0xce, 0xa3, 0xde, 0x5b, 0xee, 0x33, 0x86, 0x5a, 0x22, 0xa9,
- 0xe6, 0x64, 0x9a, 0xba, 0x8d, 0xf2, 0xb0, 0x9e, 0xc2, 0xc8, 0x04, 0x6d, 0xe8, 0x65, 0xa0, 0x16,
- 0xb0, 0x01, 0x93, 0x60, 0x6d, 0x1c, 0xcf, 0xff, 0x85, 0xde, 0xe4, 0xc1, 0x66, 0x43, 0x0e, 0x77,
- 0xaf, 0xe2, 0xd2, 0xae, 0x31, 0xa2, 0x9e, 0x9c, 0x01, 0x0a, 0x0e, 0xe6, 0x39, 0xa4, 0xe1, 0x8c,
- 0x88, 0xd5, 0x5e, 0x64, 0x7d, 0x0f, 0xed, 0x5e, 0x98, 0xc1, 0x49, 0xdc, 0x62, 0xe4, 0x61, 0xcf,
- 0x1b, 0x1e, 0xea, 0x83, 0x11, 0x42, 0x5d, 0x80, 0x06, 0xcc, 0x0b, 0xa1, 0x53, 0x45, 0xab, 0x6d,
- 0xe9, 0x00, 0x47, 0xf8, 0xda, 0xea, 0x27, 0xc1, 0x6c, 0x03, 0x2b, 0xaf, 0xcd, 0x54, 0xbc, 0x27,
- 0x5b, 0x07, 0xef, 0x6c, 0xfb, 0xce, 0x3a, 0xe0, 0x98, 0x5f, 0x99, 0xb8, 0xb2, 0x08, 0xdd, 0xc6,
- 0xbc, 0x94, 0xb5, 0x56, 0x25, 0x8d, 0x8d, 0x99, 0x24, 0x09, 0x37, 0x3f, 0x21, 0xae, 0x03, 0x69,
- 0x84, 0x73, 0xd9, 0xd9, 0xda, 0x8f, 0xc6, 0x23, 0x95, 0xfa, 0xff, 0xec, 0x91, 0x4b, 0x81, 0x3e,
- 0xbb, 0x2f, 0xc2, 0x7a, 0x3d, 0x65, 0xfc, 0x21, 0xc7, 0xcb, 0xec, 0x47, 0x63, 0x18, 0x33, 0xd1,
- 0x45, 0x5d, 0x72, 0xbe, 0x89, 0xbb, 0x08, 0x41, 0xf3, 0xcc, 0xd6, 0xc7, 0xfa, 0xa6, 0xe1, 0x91,
- 0x42, 0xf1, 0x96, 0xe6, 0x0e, 0x2b, 0x48, 0xfe, 0x5b, 0x09, 0x11, 0x44, 0xab, 0x24, 0x55, 0xef,
- 0x68, 0x8a, 0x3f, 0xc9, 0x9e, 0x13, 0x7a, 0x8b, 0x4b, 0x96, 0x20, 0x3b, 0xbf, 0xcc, 0x8c, 0x55,
- 0xe9, 0xe6, 0x6b, 0x28, 0xa0, 0x88, 0x68, 0x80, 0x66, 0x6e, 0x61, 0xb0, 0xdb, 0x2e, 0xf7, 0x93,
- 0x53, 0x33, 0xdc, 0xb2, 0xfb, 0x00, 0xbe, 0x65, 0x5b, 0x1a, 0x28, 0x9d, 0xcd, 0xb2, 0xb4, 0x25,
- 0xdf, 0x4f, 0x7c, 0xfc, 0x61, 0xd4, 0x2e, 0xcc, 0x50, 0x6a, 0x0c, 0xee, 0xd5, 0x0c, 0x9d, 0x7e,
- 0xbd, 0x4c, 0x03, 0x6b, 0xf4, 0x8d, 0xbf, 0xeb, 0xa3, 0x0e, 0x24, 0x13, 0x6c, 0xc6, 0x3b, 0x1c,
- 0xc2, 0x97, 0x04, 0x3d, 0xb2, 0x11, 0xbf, 0x29, 0x9a, 0x58, 0xd4, 0x56, 0xb4, 0x09, 0xa9, 0x81,
- 0x03, 0x05, 0x62, 0x87, 0x8e, 0x34, 0x5b, 0xd5, 0x06, 0x06, 0x39, 0x1a, 0x9f, 0x04, 0xe8, 0x4a,
- 0xf7, 0x0c, 0x91, 0xeb, 0x81, 0xb8, 0x95, 0x55, 0x2e, 0xa1, 0x69, 0xbb, 0x29, 0x5a, 0xd1, 0xb6,
- 0x39, 0x5c, 0x2a, 0xe9, 0x76, 0x2e, 0x08, 0x48, 0x55, 0x73, 0x60, 0x69, 0xf8, 0x43, 0x39, 0xee,
- 0xe8, 0xc6, 0xf6, 0xd7, 0xdb, 0xf9, 0x65, 0x84, 0x30, 0x1d, 0x75, 0x48, 0x29, 0xd1, 0xf4, 0xbb,
- 0x76, 0x5c, 0x5c, 0x40, 0xbb, 0x46, 0xcb, 0x45, 0xe6, 0x4b, 0x10, 0x37, 0xb9, 0xe9, 0xc7, 0x91,
- 0x3f, 0x0f, 0x9c, 0x02, 0x91, 0x9a, 0x27, 0x18, 0xbd, 0x26, 0xbf, 0x38, 0xc0, 0xf9, 0x14, 0xf5,
- 0xf3, 0xe9, 0xb1, 0x14, 0x56, 0xc0, 0x7b, 0xdd, 0xa1, 0x43, 0x4d, 0xca, 0x68, 0x24, 0xb2, 0x23,
- 0x47, 0xd5, 0x10, 0x7c, 0xb0, 0x51, 0x95, 0x7c, 0x54, 0xc2, 0x4d, 0xce, 0xc0, 0xa0, 0x62, 0xc2,
- 0xa0, 0x8d, 0x52, 0x26, 0xea, 0x8f, 0x36, 0xf5, 0x9f, 0x26, 0x2b, 0x68, 0x20, 0x93, 0xa3, 0x3c,
- 0xdf, 0xf9, 0xa5, 0xff, 0x35, 0x0f, 0x7e, 0xda, 0xc4, 0x5f, 0x5e, 0xca, 0xc6, 0xef, 0x49, 0x78,
- 0x1a, 0xec, 0x6b, 0x18, 0x83, 0x50, 0xa1, 0x88, 0x12, 0xff, 0x92, 0x6d, 0x60, 0xff, 0x21, 0x0e,
- 0x0c, 0xae, 0xbf, 0x3f, 0x82, 0x60, 0x64, 0x07, 0x1b, 0xd9, 0xbb, 0xb9, 0xea, 0x51, 0x87, 0xf4,
- 0x1e, 0xc3, 0x60, 0xba, 0xe1, 0x01, 0x20, 0x30, 0x2b, 0x13, 0xf2, 0x58, 0x9f, 0x3b, 0xde, 0x25,
- 0xb8, 0x7a, 0x9d, 0x47, 0xb6, 0x4c, 0x94, 0xb2, 0xb0, 0x7b, 0x28, 0x0b, 0xa5, 0x80, 0x22, 0x67,
- 0x14, 0x49, 0x9e, 0x86, 0x0b, 0x69, 0xad, 0x1e, 0x27, 0xac, 0x1e, 0x0e, 0x44, 0x85, 0x2a, 0xa9,
- 0x81, 0x9c, 0x35, 0xdf, 0x95, 0xec, 0x12, 0x7d, 0x32, 0x05, 0xfb, 0x72, 0x3f, 0x55, 0x24, 0xc8,
- 0xb4, 0x59, 0xaa, 0x39, 0x36, 0xe4, 0x2b, 0x38, 0x14, 0xdb, 0x37, 0x8c, 0xba, 0x69, 0xce, 0xf0,
- 0x76, 0x8e, 0x8f, 0x99, 0x4b, 0x3d, 0x07, 0x56, 0xaf, 0x96, 0xf2, 0xe1, 0xad, 0x41, 0x97, 0x09,
- 0x52, 0x7c, 0x84, 0xcc, 0xb9, 0x84, 0x61, 0x0c, 0xf6, 0xb8, 0x3f, 0x90, 0x0c, 0xef, 0x2e, 0x6c,
- 0xd9, 0x44, 0x9e, 0x17, 0x64, 0x7d, 0x7f, 0x78, 0xe1, 0x45, 0x63, 0xd3, 0x97, 0xfa, 0xd2, 0x3e,
- 0x70, 0x6b, 0x36, 0x1f, 0x74, 0x6f, 0x27, 0x97, 0x38, 0xb1, 0x20, 0xdc, 0xb3, 0x8a, 0x33, 0x1b,
- 0x62, 0xb1, 0x1a, 0x92, 0x42, 0x55, 0x0e, 0x18, 0xa1, 0xd2, 0xf1, 0xe9, 0xed, 0x03, 0xe9, 0xc9,
- 0xdc, 0xa0, 0x18, 0xd7, 0x7f, 0xcf, 0x8b, 0xef, 0x00, 0x1f, 0x50, 0xac, 0x04, 0x2a, 0x93, 0x4e,
- 0x00, 0xd2, 0x32, 0xe5, 0xb1, 0xc3, 0x6d, 0xe0, 0x57, 0xf5, 0x0e, 0x6d, 0x1c, 0x5f, 0xb7, 0xf6,
- 0xaa, 0xb6, 0xc3, 0x63, 0x7c, 0x34, 0xed, 0x22, 0x9e, 0x61, 0xd7, 0xe0, 0x1c, 0x6c, 0xa7, 0x77,
- 0xd2, 0x5e, 0x99, 0xee, 0xa3, 0x24, 0x00, 0xe3, 0x93, 0x2a, 0x62, 0x4b, 0x99, 0x56, 0xf9, 0xfe,
- 0x9c, 0x70, 0x91, 0x27, 0x6f, 0x62, 0x39, 0xf9, 0xe0, 0x6e, 0xc0, 0x17, 0xe2, 0x6e, 0xed, 0x67,
- 0x18, 0xb3, 0x7b, 0x5f, 0x8f, 0x18, 0x68, 0x8c, 0x29, 0x7b, 0x79, 0x97, 0x73, 0x0d, 0xcd, 0x1b,
- 0xfa, 0x08, 0xab, 0x1f, 0x24, 0x71, 0x37, 0x7f, 0x82, 0x6f, 0x29, 0x89, 0xe1, 0x5b, 0x2c, 0xeb,
- 0x73, 0xfe, 0x55, 0x91, 0x2c, 0x14, 0xac, 0x9a, 0x43, 0x6d, 0xd5, 0x06, 0x1b, 0xdc, 0x9f, 0x90,
- 0x02, 0x6b, 0xf5, 0x6d, 0x8c, 0x3c, 0x04, 0xf0, 0xa7, 0x2d, 0x6a, 0x3a, 0x6b, 0xc7, 0x8d, 0x16,
- 0x78, 0xa4, 0x06, 0x1b, 0x9f, 0x0d, 0x62, 0x6b, 0x81, 0x63, 0xb9, 0x22, 0xd4, 0x2c, 0xfb, 0x70,
- 0xdd, 0x78, 0x46, 0xf0, 0x7b, 0x37, 0x64, 0x5f, 0xf8, 0xfd, 0x9d, 0x3a, 0x4e, 0xb9, 0x56, 0x02,
- 0x0b, 0x3e, 0x19, 0x02, 0x5a, 0x12, 0x14, 0x95, 0x4e, 0x88, 0x58, 0xa1, 0x55, 0xd4, 0xde, 0xae,
- 0x1d, 0x4b, 0xd3, 0x5b, 0x8f, 0xb9, 0x63, 0xfa, 0x3a, 0xe3, 0x5e, 0x76, 0xd6, 0x4b, 0x7e, 0x30,
- 0xce, 0xf7, 0x37, 0xa9, 0x53, 0x3b, 0x61, 0x0c, 0x62, 0x73, 0x85, 0xfa, 0x7b, 0x93, 0x85, 0x75,
- 0x90, 0x9e, 0x15, 0x1d, 0x88, 0x9d, 0x3c, 0x76, 0xa8, 0x9c, 0xe0, 0x3e, 0xda, 0xf3, 0x2c, 0x99,
- 0x98, 0x6a, 0x41, 0x01, 0xd8, 0xb2, 0xdd, 0x43, 0x23, 0x64, 0xd8, 0xa7, 0x27, 0xdf, 0xbc, 0x3d,
- 0xb7, 0xa3, 0x5a, 0xda, 0x6f, 0xdc, 0x0f, 0x30, 0xd1, 0xaa, 0x72, 0x61, 0xde, 0xc6, 0xa2, 0xba,
- 0x9e, 0x01, 0x1b, 0x3f, 0x42, 0x82, 0xb3, 0x0b, 0xe1, 0xf1, 0x63, 0x96, 0xf5, 0x3b, 0x0b, 0xd9,
- 0x14, 0x1d, 0x79, 0x2f, 0x76, 0xf4, 0xaf, 0x0f, 0x4c, 0x3b, 0xe0, 0xe7, 0xb8, 0xe1, 0x9f, 0x9f,
- 0x80, 0x8a, 0xb3, 0x03, 0xe4, 0x90, 0x84, 0x9b, 0x7d, 0xa4, 0x2b, 0x61, 0x76, 0x85, 0x03, 0xd4,
- 0x31, 0xbb, 0xba, 0x94, 0x0e, 0xf5, 0x05, 0xda, 0x83, 0x99, 0x55, 0xfc, 0x1e, 0x86, 0x5e, 0xf9,
- 0x52, 0x66, 0x60, 0x78, 0x04, 0x70, 0xc5, 0x2d, 0x24, 0xd6, 0x1d, 0xcb, 0x05, 0xd6, 0xc1, 0x9d,
- 0xc4, 0xd0, 0x2e, 0xb9, 0x06, 0x9d, 0xb9, 0x11, 0x80, 0x09, 0x5f, 0x57, 0x0b, 0x58, 0xf7, 0x98,
- 0xfe, 0xcb, 0xaf, 0x5c, 0x59, 0xcb, 0xbc, 0x5c, 0x8e, 0xf7, 0x66, 0x2b, 0x69, 0xdf, 0xa3, 0x3d,
- 0xb7, 0xad, 0xd0, 0x1b, 0x2d, 0x77, 0x75, 0xd5, 0x30, 0xaf, 0xd3, 0x05, 0xc6, 0x97, 0xdf, 0x75,
- 0xcd, 0x2c, 0xfa, 0x4b, 0x6a, 0xe5, 0x3e, 0x11, 0xb3, 0xfc, 0x7d, 0xda, 0xd0, 0x2b, 0xa8, 0xd5,
- 0xf9, 0xf4, 0x1a, 0x6b, 0x32, 0xce, 0x94, 0x9d, 0xa2, 0xc0, 0xca, 0x7c, 0x47, 0x30, 0x38, 0x0d,
- 0xca, 0x46, 0xea, 0x8d, 0x3d, 0xe1, 0xf7, 0x29, 0xd5, 0x39, 0x02, 0x92, 0x83, 0x6f, 0xdb, 0x42,
- 0xdd, 0xab, 0xe7, 0x03, 0x5d, 0x34, 0x0f, 0x91, 0x38, 0x7d, 0x46, 0x1c, 0x28, 0xe5, 0x77, 0xc6,
- 0xb5, 0xd8, 0x1b, 0x5a, 0xca, 0xd8, 0x4c, 0xbd, 0xb8, 0x14, 0x5b, 0x1a, 0xdf, 0x17, 0x73, 0x90,
- 0x4b, 0x01, 0xf6, 0x7e, 0xd0, 0x7a, 0x0e, 0xcc, 0x4c, 0x58, 0xfa, 0x41, 0x51, 0xbe, 0x96, 0x2d,
- 0x38, 0xfd, 0x68, 0x3f, 0x4b, 0xad, 0x6f, 0xb4, 0x0e, 0x4f, 0x29, 0xc8, 0xf9, 0x2c, 0x7d, 0xca,
- 0x07, 0xb6, 0x29, 0xc5, 0x04, 0x72, 0xc1, 0x69, 0xc4, 0xee, 0xd4, 0x22, 0x96, 0xb5, 0x1b, 0x0b,
- 0xbe, 0x9e, 0x39, 0x2a, 0xf7, 0x5f, 0x36, 0x7f, 0xeb, 0x75, 0xd4, 0x4b, 0x8b, 0x58, 0xab, 0x61,
- 0x25, 0x4e, 0xc4, 0x56, 0x5e, 0x76, 0x16, 0x9f, 0xcb, 0xee, 0xc7, 0xd9, 0x36, 0xfa, 0x71, 0x14,
- 0x65, 0x2b, 0xe0, 0x34, 0xbb, 0x42, 0xcf, 0x9e, 0xac, 0xa4, 0x17, 0x52, 0x77, 0x5b, 0x92, 0x9b,
- 0xfa, 0xb6, 0x09, 0x53, 0x71, 0x28, 0x70, 0xa2, 0x6d, 0xb8, 0x79, 0x1a, 0x98, 0x82, 0xde, 0x94,
- 0xdb, 0xe6, 0x4d, 0x1c, 0x46, 0x26, 0x7e, 0x33, 0x61, 0x92, 0x24, 0xae, 0x66, 0xcf, 0xa8, 0x62,
- 0xac, 0xd9, 0x96, 0xce, 0xd6, 0xc7, 0xc2, 0x10, 0x16, 0x95, 0x82, 0xab, 0x12, 0x4c, 0x03, 0x14,
- 0x3b, 0x74, 0x0d, 0x01, 0x7a, 0x4a, 0x53, 0x24, 0xec, 0xf1, 0xdb, 0xd6, 0x5a, 0xf0, 0x2c, 0xb5,
- 0x80, 0x8c, 0x37, 0x39, 0x5f, 0x87, 0x65, 0x97, 0x60, 0x47, 0x73, 0x89, 0x4f, 0xb2, 0x35, 0x9c,
- 0xe5, 0x89, 0x47, 0x06, 0x09, 0xd5, 0x81, 0x7b, 0x3e, 0x64, 0xd2, 0xcd, 0xa3, 0xb9, 0x8e, 0x31,
- 0xde, 0x7e, 0xf8, 0xbf, 0x8a, 0x58, 0x5c, 0xf1, 0xd6, 0x3c, 0xd4, 0x0f, 0x6a, 0xbd, 0x95, 0xc2,
- 0x51, 0x7a, 0x8f, 0x57, 0x3a, 0x72, 0x2a, 0x00, 0xcd, 0x5e, 0xf3, 0x94, 0x99, 0x82, 0x82, 0x4b,
- 0x87, 0x8f, 0xee, 0xbe, 0xb7, 0xf2, 0xca, 0xff, 0x0a, 0xd6, 0x98, 0x12, 0xd6, 0xb4, 0x5f, 0x57,
- 0xb4, 0xd3, 0xc0, 0xa4, 0xc3, 0xd2, 0xfe, 0x74, 0x65, 0x82, 0xcc, 0x2e, 0xad, 0x66, 0x4c, 0x53,
- 0x3d, 0x17, 0xcd, 0xf7, 0xb1, 0x98, 0x9f, 0x9a, 0xd1, 0xa9, 0x01, 0x09, 0x9f, 0x3f, 0x9c, 0x97,
- 0x1e, 0xf6, 0xd8, 0x6b, 0xf8, 0x50, 0x82, 0x5d, 0xfe, 0x77, 0x05, 0x49, 0xaa, 0xa8, 0xcd, 0x93,
- 0xb1, 0x2b, 0xb5, 0xeb, 0xd0, 0x08, 0x11, 0x0c, 0x77, 0xcb, 0x8d, 0xc6, 0xfa, 0x16, 0x42, 0xbd,
- 0x00, 0xae, 0x16, 0x9b, 0xd8, 0x40, 0xc8, 0xca, 0xcb, 0x20, 0x7a, 0x37, 0xb4, 0x01, 0x09, 0x79,
- 0xc5, 0xb9, 0x73, 0xd8, 0xe1, 0x3b, 0x65, 0x7c, 0x8e, 0x30, 0xc3, 0xef, 0x25, 0x4e, 0xc4, 0x83,
- 0x95, 0x95, 0x73, 0x97, 0xd9, 0x4f, 0x63, 0xed, 0x2a, 0x9d, 0x2f, 0xbf, 0x42, 0x4f, 0xd5, 0xfe,
- 0x93, 0x18, 0xff, 0x42, 0xcd, 0x4f, 0x0d, 0x99, 0x33, 0x31, 0x0f, 0x19, 0x36, 0xfb, 0x50, 0x17,
- 0x1e, 0x1f, 0xb6, 0xe9, 0x6e, 0x51, 0x76, 0x41, 0x18, 0x5e, 0xea, 0x6c, 0x9a, 0x42, 0xfa, 0xbf,
- 0x68, 0x50, 0x07, 0xc7, 0xf9, 0xef, 0x3e, 0x4e, 0x34, 0xb4, 0x3e, 0xe5, 0x69, 0xc8, 0xbb, 0x98,
- 0xd8, 0xcc, 0x9a, 0x10, 0xc0, 0x4e, 0x62, 0x40, 0x8b, 0x03, 0xf4, 0xc1, 0x7b, 0x62, 0xdc, 0x53,
- 0xa6, 0xad, 0xe4, 0x91, 0xf5, 0xb3, 0xa3, 0xf8, 0x84, 0xa7, 0x25, 0x19, 0x44, 0x68, 0xbc, 0x7b,
- 0x4e, 0x05, 0x6b, 0x7e, 0x3e, 0xb4, 0x8b, 0xea, 0x4d, 0x3b, 0x71, 0xe2, 0x06, 0xf3, 0xcb, 0xda,
- 0x52, 0xae, 0xa5, 0x44, 0x8e, 0x7e, 0x78, 0xbe, 0x3c, 0xa9, 0x57, 0xaf, 0x47, 0x06, 0xf5, 0xf2,
- 0x8f, 0xe3, 0x5f, 0xbe, 0x9e, 0x1b, 0x6f, 0xfc, 0xbf, 0xc1, 0x82, 0x45, 0x85, 0xca, 0x08, 0xa6,
- 0xd1, 0xfe, 0x9f, 0xc2, 0x37, 0x31, 0x6a, 0x67, 0x2c, 0x4d, 0x45, 0x95, 0xba, 0xca, 0x0b, 0xdf,
- 0x81, 0xf0, 0x68, 0x32, 0xa0, 0x6c, 0xc0, 0x92, 0x87, 0x3d, 0x85, 0xe4, 0x81, 0xe2, 0xd3, 0x80,
- 0x0c, 0x3b, 0xb0, 0xb9, 0x45, 0x6e, 0x0e, 0xdb, 0xc0, 0xcf, 0x48, 0xf7, 0x04, 0xb3, 0x54, 0xb7,
- 0x71, 0xf9, 0x2d, 0xe2, 0xf2, 0xea, 0x5e, 0xa1, 0xe7, 0x05, 0x92, 0xe2, 0xfa, 0xe7, 0x9b, 0xea,
- 0x37, 0xb3, 0x55, 0xbf, 0xec, 0xd8, 0x61, 0xa8, 0x2a, 0x76, 0x54, 0x45, 0x0c, 0xf3, 0xc1, 0xb5,
- 0xf5, 0xc5, 0xf9, 0x00, 0x4b, 0xd3, 0x47, 0xf4, 0xa8, 0xe8, 0x0c, 0x77, 0x85, 0xe5, 0xc3, 0x69,
- 0xed, 0xc3, 0x30, 0xaf, 0xfd, 0x0b, 0x54, 0x46, 0x88, 0x1c, 0x83, 0x76, 0xc4, 0x57, 0xa8, 0x8e,
- 0x51, 0xc2, 0xb2, 0x76, 0x08, 0x23, 0x2d, 0x4e, 0x29, 0xae, 0x0f, 0xb4, 0x1f, 0x3a, 0x78, 0x3c,
- 0x8b, 0x73, 0x7d, 0x30, 0xb0, 0x75, 0x3e, 0xe0, 0x1a, 0x85, 0x65, 0xa3, 0x21, 0xb9, 0x53, 0x04,
- 0xbd, 0xfb, 0x20, 0x31, 0xfe, 0xbd, 0xf5, 0x55, 0x2c, 0xee, 0x1f, 0xab, 0xe6, 0x50, 0xdc, 0x3d,
- 0x6e, 0x31, 0x4f, 0xcb, 0xca, 0x3a, 0x4d, 0x19, 0x7b, 0x3b, 0xae, 0xd8, 0xf7, 0xfb, 0xa5, 0x6d,
- 0x92, 0x30, 0x26, 0x00, 0x02, 0xda, 0xd0, 0xd8, 0x61, 0x06, 0x81, 0x4e, 0xf9, 0x66, 0x60, 0x0d,
- 0x48, 0x6e, 0x58, 0x08, 0xdb, 0xfb, 0xc3, 0x39, 0x5f, 0x90, 0xbf, 0x51, 0xb5, 0x37, 0x9f, 0xc2,
- 0x87, 0x63, 0xb8, 0x39, 0x46, 0x6a, 0xdf, 0x3d, 0x48, 0x02, 0xff, 0x01, 0x24, 0x49, 0xf8, 0x5a,
- 0x52, 0xbb, 0xfd, 0x56, 0xfa, 0x00, 0x11, 0x97, 0xbb, 0x88, 0xba, 0x2b, 0x54, 0x00, 0xd9, 0xc6,
- 0x78, 0x93, 0x3f, 0xab, 0xfa, 0x56, 0x68, 0x5d, 0x73, 0x2b, 0xc7, 0x90, 0xad, 0x51, 0x19, 0x82,
- 0x02, 0x42, 0x66, 0x10, 0x40, 0x07, 0x99, 0x87, 0x2f, 0x9c, 0x1c, 0xe6, 0x39, 0x9d, 0x84, 0xab,
- 0x08, 0xbc, 0xbf, 0x44, 0x17, 0xbe, 0x41, 0x83, 0x9b, 0xb0, 0x36, 0x15, 0xe1, 0x9d, 0xfb, 0x8a,
- 0x87, 0x7a, 0x6f, 0xcc, 0x46, 0x0a, 0xb7, 0xbb, 0x1d, 0x8f, 0xdd, 0xa4, 0x8b, 0xb3, 0x0e, 0x78,
- 0x7f, 0x89, 0xd5, 0x49, 0x81, 0xe7, 0x5a, 0x09, 0x5b, 0x5b, 0x98, 0xf2, 0x65, 0xfc, 0x78, 0x09,
- 0xa0, 0xe3, 0xd7, 0x66, 0xa5, 0xaf, 0xd5, 0x8e, 0x1c, 0x80, 0x43, 0x56, 0x12, 0x9a, 0x03, 0x72,
- 0x5c, 0xcc, 0x82, 0x50, 0xf7, 0x53, 0x97, 0xda, 0xfc, 0xf0, 0x96, 0xda, 0xec, 0x10, 0x57, 0xc2,
- 0xc4, 0x02, 0x06, 0xdb, 0x2d, 0xe6, 0x96, 0x29, 0x0b, 0x04, 0x56, 0xf9, 0x39, 0x02, 0x37, 0x3c,
- 0x65, 0x9a, 0x76, 0xa1, 0x0b, 0x1c, 0xa3, 0xae, 0x7c, 0xae, 0xb3, 0x68, 0x5c, 0x1b, 0x2f, 0xaf,
- 0xfe, 0x9c, 0xb9, 0x64, 0x3d, 0x35, 0x84, 0x2d, 0x26, 0x48, 0xa8, 0x4d, 0x0a, 0x57, 0xec, 0x15,
- 0x2f, 0x7b, 0x8d, 0x1a, 0x6d, 0xb4, 0x72, 0xb1, 0xf3, 0xfa, 0x97, 0x9f, 0x3a, 0x8a, 0xe6, 0x5e,
- 0xf1, 0xc4, 0xcc, 0x6e, 0x75, 0x25, 0x5b, 0x4d, 0x6b, 0xac, 0x47, 0x30, 0xa5, 0x64, 0x51, 0xf1,
- 0x87, 0xf0, 0x85, 0x54, 0x82, 0x23, 0x3e, 0xf8, 0x32, 0xbd, 0x11, 0x17, 0x8a, 0xb3, 0x49, 0xac,
- 0xec, 0x6f, 0x59, 0x7e, 0x5f, 0xd0, 0xcd, 0x3f, 0xa8, 0x1e, 0xa8, 0xd6, 0xb8, 0xda, 0x92, 0x03,
- 0x4f, 0xc8, 0x12, 0x59, 0x93, 0x8c, 0xb3, 0x48, 0x8a, 0x80, 0xef, 0xbe, 0xb9, 0xd4, 0xfa, 0x90,
- 0xd9, 0xf2, 0x1c, 0x7a, 0x3e, 0x73, 0x99, 0x33, 0xaf, 0x6a, 0x79, 0x03, 0xf2, 0x02, 0x5b, 0x1a,
- 0x4f, 0xf7, 0x09, 0x9a, 0x7a, 0x07, 0xd4, 0xe8, 0x88, 0xc1, 0x5b, 0xf0, 0x05, 0xd0, 0x30, 0xab,
- 0x6c, 0x18, 0x6a, 0x3e, 0x8d, 0x1e, 0xdd, 0x2d, 0xdb, 0x23, 0xa8, 0xdb, 0x7c, 0xaa, 0xd1, 0xd6,
- 0xe3, 0xc6, 0xaa, 0xf7, 0x34, 0xad, 0x09, 0xba, 0xf2, 0xa7, 0x16, 0xed, 0x88, 0x7c, 0xe4, 0xe4,
- 0xcc, 0x99, 0x7e, 0xa1, 0xb4, 0x8f, 0xaf, 0x35, 0x11, 0x01, 0x42, 0xf2, 0x19, 0x37, 0x51, 0x18,
- 0x25, 0xc2, 0x35, 0x43, 0xde, 0x85, 0xd8, 0x43, 0x41, 0x16, 0x59, 0x28, 0x1e, 0xc8, 0x6f, 0xd2,
- 0xba, 0xbf, 0x18, 0x52, 0x9c, 0x13, 0x9c, 0x15, 0xe9, 0xbc, 0xd7, 0x21, 0xfa, 0x59, 0x9a, 0x60,
- 0x1e, 0xec, 0x64, 0xd9, 0x60, 0x8d, 0x31, 0x8c, 0xd6, 0x1e, 0x7d, 0xc4, 0xa8, 0x81, 0x76, 0x41,
- 0xa2, 0x41, 0x37, 0x04, 0xe4, 0x87, 0xc5, 0xe4, 0x58, 0x01, 0x37, 0x93, 0x9a, 0x76, 0xbd, 0x20,
- 0x86, 0xc9, 0xb7, 0x52, 0xb6, 0xd3, 0x59, 0x3f, 0x9f, 0xc8, 0xea, 0xbb, 0x9a, 0x71, 0x34, 0x36,
- 0x26, 0x83, 0xd2, 0xab, 0xb6, 0x6b, 0x45, 0x58, 0x0b, 0x73, 0xfd, 0x8d, 0x50, 0x0d, 0x81, 0x12,
- 0x10, 0x5a, 0xdf, 0x2c, 0x53, 0x6b, 0x48, 0x18, 0x60, 0x10, 0x69, 0xcd, 0x73, 0x52, 0x40, 0xd6,
- 0x14, 0x69, 0x68, 0x68, 0x8e, 0xe3, 0x01, 0x54, 0x3c, 0x8e, 0x8b, 0xe0, 0x77, 0x77, 0xdc, 0x5f,
- 0xca, 0x01, 0xc6, 0x08, 0x0b, 0xbf, 0x16, 0x5d, 0x71, 0x8f, 0x3e, 0xf7, 0x8e, 0x8f, 0x1f, 0x66,
- 0xcf, 0x49, 0xb3, 0xe8, 0x55, 0x00, 0x8d, 0x86, 0xcb, 0x3f, 0x2b, 0x03, 0x61, 0xde, 0x10, 0x4e,
- 0x7b, 0x24, 0xb2, 0x08, 0xec, 0x0f, 0xe6, 0xcd, 0x9c, 0xa1, 0xa4, 0x98, 0xe0, 0x0d, 0xcd, 0x20,
- 0xfa, 0x3a, 0x83, 0xb5, 0xec, 0x4c, 0x69, 0xa6, 0xfa, 0x2d, 0xe6, 0x76, 0xda, 0x8c, 0xc2, 0xe2,
- 0x04, 0x75, 0xfd, 0xb3, 0xdc, 0x8d, 0x93, 0x64, 0xd1, 0xa3, 0xcc, 0xb0, 0xf5, 0xbd, 0x0a, 0xaa,
- 0xbe, 0x0e, 0xe8, 0x19, 0x01, 0xb8, 0xc2, 0x4f, 0x5e, 0x78, 0x2f, 0x1a, 0x30, 0xf0, 0xb3, 0x8a,
- 0x5d, 0x9d, 0xc5, 0xac, 0xf4, 0x7b, 0x0d, 0xe4, 0xd4, 0x96, 0xea, 0xca, 0x4b, 0x85, 0x81, 0x3a,
- 0x0d, 0xe9, 0x0b, 0x37, 0x56, 0x9d, 0x0e, 0xd7, 0x02, 0x67, 0x87, 0x03, 0x09, 0xfd, 0x1b, 0x67,
- 0xd5, 0xe4, 0x69, 0xcc, 0xfc, 0xc3, 0xbf, 0x9a, 0x6d, 0x93, 0xc4, 0x45, 0x9c, 0xf8, 0xd9, 0x03,
- 0xad, 0x65, 0x70, 0x82, 0x49, 0xd3, 0xac, 0xa7, 0x8a, 0xf3, 0xda, 0x01, 0xbd, 0x26, 0xb3, 0xa4,
- 0xd7, 0x8a, 0x91, 0xbf, 0xea, 0x8b, 0x2b, 0xb0, 0x6c, 0xd8, 0x84, 0x7b, 0x4b, 0xf4, 0x2c, 0xbc,
- 0x45, 0x30, 0xe1, 0xf0, 0xbf, 0xfc, 0x4c, 0x81, 0xfc, 0x07, 0xa7, 0xea, 0x34, 0xcb, 0x15, 0x55,
- 0xa9, 0x9e, 0x70, 0x4f, 0xbb, 0xd8, 0x1b, 0xd6, 0x1b, 0x2d, 0x4e, 0x20, 0x72, 0x44, 0x00, 0x36,
- 0x1f, 0x23, 0x06, 0x40, 0x7e, 0xde, 0x3e, 0xd4, 0x61, 0x6f, 0x12, 0x56, 0x04, 0xd7, 0x58, 0x2f,
- 0x8d, 0x66, 0x0b, 0xff, 0xd2, 0x23, 0x5c, 0xf4, 0xd4, 0xa3, 0x58, 0xd0, 0x6d, 0xf6, 0x98, 0xab,
- 0xc5, 0x53, 0xea, 0xc4, 0x37, 0x47, 0xc3, 0x4a, 0x8d, 0xc6, 0x4c, 0x19, 0x5d, 0x17, 0xb4, 0x39,
- 0x71, 0xe9, 0x99, 0x82, 0xe6, 0x5b, 0xc5, 0x90, 0x33, 0xf7, 0x5b, 0x8d, 0x98, 0x4c, 0xcd, 0x7a,
- 0x6b, 0xd8, 0xb9, 0x8c, 0x11, 0x34, 0x8d, 0xc0, 0x9a, 0x57, 0x2a, 0x12, 0xd5, 0x7f, 0x3f, 0x94,
- 0x70, 0x93, 0x1a, 0x11, 0xe9, 0xf3, 0x99, 0x4f, 0x10, 0x38, 0xc7, 0xc2, 0xec, 0x62, 0xac, 0x59,
- 0x90, 0x3a, 0x85, 0x1d, 0xeb, 0xee, 0xa3, 0x90, 0x59, 0xfd, 0x0a, 0x07, 0x0a, 0xc7, 0x32, 0x2d,
- 0x11, 0x18, 0x53, 0x70, 0x80, 0x59, 0x59, 0x51, 0x33, 0xd8, 0x29, 0x85, 0xf4, 0x09, 0xf6, 0x76,
- 0x1e, 0x49, 0xa6, 0x79, 0xc1, 0x2c, 0xae, 0xa6, 0x54, 0xbe, 0xf6, 0x54, 0xb1, 0x95, 0x39, 0x97,
- 0xeb, 0xdc, 0xb2, 0xff, 0x99, 0x19, 0x9a, 0x9b, 0x0e, 0xad, 0x0e, 0x3f, 0xbf, 0xe0, 0x39, 0x8e,
- 0x27, 0x37, 0x1c, 0xdc, 0x86, 0x20, 0x1f, 0x21, 0xd5, 0x0e, 0xd6, 0xbc, 0x45, 0x3e, 0x1d, 0x33,
- 0x3b, 0x15, 0x35, 0xf9, 0x52, 0x98, 0x6f, 0x9a, 0x44, 0x25, 0x01, 0x6b, 0x3d, 0x47, 0x3b, 0x11,
- 0x35, 0x0e, 0x2a, 0xb5, 0x4e, 0xb3, 0xc9, 0x24, 0xe5, 0xae, 0x5b, 0x0e, 0x5f, 0x6a, 0x85, 0x89,
- 0xe5, 0x94, 0xd1, 0x74, 0x08, 0x70, 0x8b, 0xbe, 0x4d, 0xb8, 0x77, 0x4c, 0xa3, 0x14, 0x04, 0x09,
- 0xfe, 0x17, 0x0a, 0xca, 0xb0, 0x9a, 0x5d, 0x63, 0x01, 0xd0, 0xf3, 0xe9, 0x3d, 0xde, 0xaf, 0x0b,
- 0x31, 0x13, 0x61, 0x7a, 0x99, 0xf7, 0x00, 0x17, 0xb0, 0x3a, 0xfc, 0x27, 0x62, 0xfe, 0xd1, 0x36,
- 0x87, 0xb5, 0xfe, 0xd2, 0xad, 0xff, 0xfd, 0xfb, 0xb5, 0x38, 0x8b, 0xca, 0x64, 0xdc, 0x55, 0xb5,
- 0x4e, 0xed, 0x07, 0x07, 0x97, 0x13, 0x6b, 0xa1, 0x33, 0x42, 0x95, 0xb2, 0xaa, 0x0b, 0xf9, 0x1d,
- 0x94, 0x86, 0x37, 0x17, 0xe4, 0x7a, 0x63, 0xe8, 0x99, 0x5b, 0xe9, 0xfc, 0x30, 0x6e, 0x26, 0xed,
- 0x21, 0xd2, 0x0a, 0x28, 0xe5, 0xa0, 0xd7, 0x64, 0x02, 0x5e, 0xb1, 0x3a, 0x40, 0x4d, 0x2c, 0x2b,
- 0x4e, 0xc9, 0xbe, 0xf3, 0xe6, 0x91, 0x34, 0xe6, 0x71, 0xd5, 0xce, 0xdb, 0x47, 0x40, 0xbd, 0x80,
- 0x80, 0x48, 0x9b, 0xaf, 0x81, 0xf4, 0x83, 0x3f, 0x8e, 0x3c, 0x49, 0xf6, 0x29, 0x0c, 0x17, 0x91,
- 0xf2, 0x8f, 0x83, 0xfb, 0xb6, 0x04, 0x57, 0x13, 0x2f, 0x59, 0xa1, 0x7b, 0x72, 0xd4, 0x6c, 0x84,
- 0x41, 0x36, 0x86, 0x9e, 0x56, 0x7a, 0x73, 0x59, 0x54, 0x47, 0x8c, 0x85, 0x3f, 0x8d, 0x3a, 0xcc,
- 0x1b, 0x0b, 0x97, 0x26, 0x7a, 0x53, 0x09, 0x05, 0x37, 0xa1, 0x6d, 0x36, 0x62, 0xe9, 0x43, 0xb1,
- 0xf3, 0xe3, 0xb1, 0xc0, 0x80, 0xf7, 0x2e, 0xae, 0x49, 0x7a, 0xe6, 0xba, 0x1b, 0x42, 0x87, 0x5c,
- 0xc3, 0xae, 0x2c, 0xd0, 0xd2, 0x98, 0x77, 0x43, 0xd1, 0x81, 0x26, 0x9a, 0xe2, 0xbf, 0xf4, 0x6f,
- 0xee, 0x24, 0x52, 0xfb, 0x1f, 0x6a, 0x1f, 0x21, 0xef, 0xf0, 0xc6, 0x02, 0x85, 0xde, 0x1a, 0x4d,
- 0x13, 0xff, 0xa1, 0x58, 0x43, 0x79, 0xb7, 0xc9, 0x45, 0x51, 0x3f, 0x90, 0xb6, 0x76, 0xbb, 0xfb,
- 0x51, 0x8e, 0x37, 0xab, 0x13, 0x36, 0x84, 0x7b, 0xea, 0xea, 0x68, 0x49, 0xd7, 0x5b, 0x42, 0x64,
- 0x09, 0x76, 0x7b, 0x6e, 0xe6, 0x93, 0xd3, 0x27, 0x37, 0xce, 0x2f, 0xd7, 0x3b, 0x1e, 0xf0, 0xd2,
- 0x15, 0xb0, 0xc9, 0xb3, 0x09, 0xef, 0xfe, 0x60, 0xa5, 0x79, 0xb5, 0xb6, 0x30, 0x85, 0x0e, 0xcc,
- 0xbb, 0x23, 0x53, 0x58, 0x28, 0xf5, 0x66, 0xe7, 0xed, 0x2a, 0x0e, 0x8e, 0xdd, 0x23, 0x0d, 0x36,
- 0x84, 0xf3, 0xbe, 0x75, 0xe9, 0xf7, 0x47, 0x07, 0xf4, 0x39, 0x7b, 0x57, 0xe7, 0x1d, 0x94, 0xff,
- 0xe7, 0xe4, 0x9b, 0x91, 0x3d, 0x6e, 0xba, 0x28, 0xca, 0x07, 0xbb, 0xc9, 0xb1, 0x84, 0x7c, 0x6a,
- 0x50, 0x97, 0xf1, 0xf7, 0x22, 0xa7, 0xa3, 0x36, 0x28, 0xe9, 0x3a, 0x60, 0x30, 0x84, 0x73, 0xe8,
- 0x60, 0xbf, 0x26, 0xac, 0x57, 0xa9, 0xab, 0xd2, 0xb1, 0x3f, 0xff, 0xfc, 0x33, 0xe0, 0x8d
-};
-
-fastimage_t bfin_logo = {
- DEF_BFIN_LOGO_DATA,
- DEF_BFIN_LOGO_WIDTH,
- DEF_BFIN_LOGO_HEIGHT,
- DEF_BFIN_LOGO_BPP,
- DEF_BFIN_LOGO_PIXEL_SIZE,
- DEF_BFIN_LOGO_SIZE
-};
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index a1462bdeccd9..000000000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * U-Boot - bitops.h Routines for bit operations
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#ifdef __KERNEL__
-/*
- * Function prototypes to keep gcc -Wall happy
- */
-
-/*
- * The __ functions are not atomic
- */
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static __inline__ unsigned long ffz(unsigned long word)
-{
- unsigned long result = 0;
-
- while (word & 1) {
- result++;
- word >>= 1;
- }
- return result;
-}
-
-static __inline__ void set_bit(int nr, volatile void *addr)
-{
- int *a = (int *)addr;
- int mask;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- *a |= mask;
- local_irq_restore(flags);
-}
-
-static __inline__ void __set_bit(int nr, volatile void *addr)
-{
- int *a = (int *)addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- *a |= mask;
-}
-#define PLATFORM__SET_BIT
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit() barrier()
-#define smp_mb__after_clear_bit() barrier()
-
-static __inline__ void clear_bit(int nr, volatile void *addr)
-{
- int *a = (int *)addr;
- int mask;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- *a &= ~mask;
- local_irq_restore(flags);
-}
-
-static __inline__ void change_bit(int nr, volatile void *addr)
-{
- int mask, flags;
- unsigned long *ADDR = (unsigned long *)addr;
-
- ADDR += nr >> 5;
- mask = 1 << (nr & 31);
- local_irq_save(flags);
- *ADDR ^= mask;
- local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile void *addr)
-{
- int mask;
- unsigned long *ADDR = (unsigned long *)addr;
-
- ADDR += nr >> 5;
- mask = 1 << (nr & 31);
- *ADDR ^= mask;
-}
-
-static __inline__ int test_and_set_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
- *a |= mask;
- local_irq_restore(flags);
-
- return retval;
-}
-
-static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a |= mask;
- return retval;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
- *a &= ~mask;
- local_irq_restore(flags);
-
- return retval;
-}
-
-static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a &= ~mask;
- return retval;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
- *a ^= mask;
- local_irq_restore(flags);
-
- return retval;
-}
-
-static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- volatile unsigned int *a = (volatile unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a ^= mask;
- return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
-{
- return ((1UL << (nr & 31)) &
- (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, volatile void *addr)
-{
- int *a = (int *)addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#define find_first_zero_bit(addr, size) \
- find_next_zero_bit((addr), (size), 0)
-
-static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
-{
- unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
- unsigned long result = offset & ~31UL;
- unsigned long tmp;
-
- if (offset >= size)
- return size;
- size -= result;
- offset &= 31UL;
- if (offset) {
- tmp = *(p++);
- tmp |= ~0UL >> (32 - offset);
- if (size < 32)
- goto found_first;
- if (~tmp)
- goto found_middle;
- size -= 32;
- result += 32;
- }
- while (size & ~31UL) {
- if (~(tmp = *(p++)))
- goto found_middle;
- result += 32;
- size -= 32;
- }
- if (!size)
- return result;
- tmp = *p;
-
- found_first:
- tmp |= ~0UL >> size;
- found_middle:
- return result + ffz(tmp);
-}
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-static __inline__ int ext2_set_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- unsigned long flags;
- volatile unsigned char *ADDR = (unsigned char *)addr;
-
- ADDR += nr >> 3;
- mask = 1 << (nr & 0x07);
- local_irq_save(flags);
- retval = (mask & *ADDR) != 0;
- *ADDR |= mask;
- local_irq_restore(flags);
- return retval;
-}
-
-static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
-{
- int mask, retval;
- unsigned long flags;
- volatile unsigned char *ADDR = (unsigned char *)addr;
-
- ADDR += nr >> 3;
- mask = 1 << (nr & 0x07);
- local_irq_save(flags);
- retval = (mask & *ADDR) != 0;
- *ADDR &= ~mask;
- local_irq_restore(flags);
- return retval;
-}
-
-static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
-{
- int mask;
- const volatile unsigned char *ADDR = (const unsigned char *)addr;
-
- ADDR += nr >> 3;
- mask = 1 << (nr & 0x07);
- return ((mask & *ADDR) != 0);
-}
-
-#define ext2_find_first_zero_bit(addr, size) \
- ext2_find_next_zero_bit((addr), (size), 0)
-
-static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
- unsigned long size,
- unsigned long offset)
-{
- unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
- unsigned long result = offset & ~31UL;
- unsigned long tmp;
-
- if (offset >= size)
- return size;
- size -= result;
- offset &= 31UL;
- if (offset) {
- tmp = *(p++);
- tmp |= ~0UL >> (32 - offset);
- if (size < 32)
- goto found_first;
- if (~tmp)
- goto found_middle;
- size -= 32;
- result += 32;
- }
- while (size & ~31UL) {
- if (~(tmp = *(p++)))
- goto found_middle;
- result += 32;
- size -= 32;
- }
- if (!size)
- return result;
- tmp = *p;
-
- found_first:
- tmp |= ~0UL >> size;
- found_middle:
- return result + ffz(tmp);
-}
-
-/* Bitmap functions for the minix filesystem. */
-#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr) set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr) test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index 204d02b5f37c..000000000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_GLOB_BLACKFIN__
-#define __MACH_GLOB_BLACKFIN__
-
-#include "blackfin_def.h"
-#ifndef __ASSEMBLY__
-#include "blackfin_cdef.h"
-#endif
-#include "blackfin_local.h"
-
-#endif /* __MACH_GLOB_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
deleted file mode 100644
index 86087117ef41..000000000000
--- a/arch/blackfin/include/asm/blackfin_cdef.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_CDEF_BLACKFIN__
-#define __MACH_CDEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_cdef.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_cdef.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_cdef.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_cdef.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_cdef.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_cdef.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_cdef.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_cdef.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_cdef.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_cdef.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_cdef.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_cdef.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_cdef.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_cdef.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_cdef.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_cdef.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_cdef.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_cdef.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_cdef.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_cdef.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_cdef.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_cdef.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_cdef.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_cdef.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_cdef.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_cdef.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_cdef.h"
-#endif
-
-#endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
deleted file mode 100644
index c96a3ecbbad8..000000000000
--- a/arch/blackfin/include/asm/blackfin_def.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_DEF_BLACKFIN__
-#define __MACH_DEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_def.h"
-# include "mach-bf561/anomaly.h"
-# include "mach-bf561/def_local.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_def.h"
-# include "mach-bf609/anomaly.h"
-# include "mach-bf609/def_local.h"
-#endif
-
-#endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
deleted file mode 100644
index 00556de2849e..000000000000
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * U-Boot - blackfin_local.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __BLACKFIN_LOCAL_H__
-#define __BLACKFIN_LOCAL_H__
-
-#include <asm/mem_map.h>
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-#define OFFSET_(x) (x & 0x0000FFFF)
-#define MK_BMSK_(x) (1 << x)
-
-/* Ideally this should be USEC not MSEC, but the USEC multiplication
- * likes to overflow 32bit quantities which is all our assembler
- * currently supports ;(
- */
-#define USEC_PER_MSEC 1000
-#define MSEC_PER_SEC 1000
-#define BFIN_SCLK (100000000)
-#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
-#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
-
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#include <linux/linkage.h>
-#include <asm/cache.h>
-
-#ifndef __ASSEMBLY__
-# ifdef SHARED_RESOURCES
-# include <asm/shared_resources.h>
-# endif
-
-# include <linux/types.h>
-
-# define bfin_revid() (bfin_read_CHIPID() >> 28)
-
-extern int bfin_os_log_check(void);
-extern void bfin_os_log_dump(void);
-
-extern void blackfin_icache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_icache_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
-
-/* Use DMA to move data from on chip to external memory. The L1 instruction
- * regions can only be accessed via DMA, so if the address in question is in
- * that region, make sure we attempt to DMA indirectly.
- */
-# ifdef __ADSPBF561__
- /* Core B regions all need dma from Core A */
-# define addr_bfin_on_chip_mem(addr) \
- ((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
- (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
-# else
-# define addr_bfin_on_chip_mem(addr) \
- (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
-# endif
-
-# include <asm/system.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
- u32 __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = " #asm_size "[%1]" #asm_ext ";" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- #asm_size "[%0] = %1;" \
- : \
- : "a" (addr), "d" ((u##size)(val)) \
- : "memory" \
- )
-
-#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32, , )
-#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
-
-#define bfin_read(addr) \
-({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BFIN_BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
- switch (sizeof(*(addr))) { \
- case 1: bfin_write8(addr, val); break; \
- case 2: bfin_write16(addr, val); break; \
- case 4: bfin_write32(addr, val); break; \
- default: \
- BFIN_BUG(); \
- } \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#define bfin_readPTR(addr) bfin_read32(addr)
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "ssync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else if (ANOMALY_05000244)
- __asm__ __volatile__(
- "nop;"
- "nop;"
- "nop;"
- "ssync;"
- );
- else
- __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "csync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else if (ANOMALY_05000244)
- __asm__ __volatile__(
- "nop;"
- "nop;"
- "nop;"
- "csync;"
- );
- else
- __asm__ __volatile__("csync;");
-}
-
-#else /* __ASSEMBLY__ */
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
deleted file mode 100644
index 593ba5a4cf00..000000000000
--- a/arch/blackfin/include/asm/byteorder.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * U-Boot - byteorder.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __BYTEORDER_HAS_U64__
-# define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
deleted file mode 100644
index 568885a2c286..000000000000
--- a/arch/blackfin/include/asm/cache.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h> /* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX 5
-
-#if defined(CONFIG_SMP) && \
- !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
- __raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
- __raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h
deleted file mode 100644
index 05ae03c09a30..000000000000
--- a/arch/blackfin/include/asm/clock.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2012 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __CLOCK_H__
-#define __CLOCK_H__
-
-#include <asm/blackfin.h>
-#ifdef PLL_CTL
-#include <asm/mach-common/bits/pll.h>
-# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
-#else
-#include <asm/mach-common/bits/cgu.h>
-# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
-# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
-# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
-# define SSEL SYSSEL
-# define SSEL_P SYSSEL_P
-#endif
-
-__attribute__((always_inline))
-static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
-{
- uint32_t quotient;
- uint32_t i, j;
-
- for (quotient = 1, i = 1; dividend > divisor; ++i) {
- j = divisor << i;
- if (j > dividend || (j & 0x80000000)) {
- --i;
- quotient += (1 << i);
- dividend -= (divisor << i);
- i = 0;
- }
- }
-
- return quotient;
-}
-
-__attribute__((always_inline))
-static inline uint32_t early_get_uart_clk(void)
-{
- uint32_t msel, pll_ctl, vco;
- uint32_t div, ssel, sclk, uclk;
-
- pll_ctl = bfin_read_PLL_CTL();
- msel = (pll_ctl & MSEL) >> MSEL_P;
- if (msel == 0)
- msel = (MSEL >> MSEL_P) + 1;
-
- vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
- sclk = vco;
- if (!pll_is_bypassed()) {
- div = bfin_read_PLL_DIV();
- ssel = (div & SSEL) >> SSEL_P;
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
- sclk = vco/ssel;
-#else
- sclk = early_division(vco, ssel);
-#endif
- }
- uclk = sclk;
-#ifdef CGU_DIV
- ssel = (div & S0SEL) >> S0SEL_P;
- uclk = early_division(sclk, ssel);
-#endif
- return uclk;
-}
-
-extern u_long get_vco(void);
-extern u_long get_cclk(void);
-extern u_long get_sclk(void);
-
-#ifdef CGU_DIV
-extern u_long get_sclk0(void);
-extern u_long get_sclk1(void);
-extern u_long get_dclk(void);
-# define get_uart_clk get_sclk0
-# define get_i2c_clk get_sclk0
-# define get_spi_clk get_sclk1
-#else
-# define get_uart_clk get_sclk
-# define get_i2c_clk get_sclk
-# define get_spi_clk get_sclk
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h
deleted file mode 100644
index 2d8b293c3ea5..000000000000
--- a/arch/blackfin/include/asm/config-pre.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * config-pre.h - common defines for Blackfin boards in config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
-#define __ASM_BLACKFIN_CONFIG_PRE_H__
-
-/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
- * Depending on your cpu, some of these may not be valid, check your HRM.
- * The actual values here are meaningless as long as they're unique.
- */
-#define BFIN_BOOT_BYPASS 1 /* bypass bootrom */
-#define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */
-#define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */
-#define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */
-#define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */
-#define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */
-#define BFIN_BOOT_UART 7 /* boot ldr over uart */
-#define BFIN_BOOT_IDLE 8 /* do nothing, just idle */
-#define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */
-#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
-#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
-#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
-#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
-#define BFIN_BOOT_RSI_MASTER 14 /* boot ldr from rsi */
-#define BFIN_BOOT_LP_SLAVE 15 /* boot ldr from link port */
-
-#ifndef __ASSEMBLY__
-static inline const char *get_bfin_boot_mode(int bfin_boot)
-{
- switch (bfin_boot) {
- case BFIN_BOOT_BYPASS: return "bypass";
- case BFIN_BOOT_PARA: return "parallel flash";
- case BFIN_BOOT_SPI_MASTER: return "spi flash";
- case BFIN_BOOT_SPI_SLAVE: return "spi slave";
- case BFIN_BOOT_TWI_MASTER: return "i2c flash";
- case BFIN_BOOT_TWI_SLAVE: return "i2c slave";
- case BFIN_BOOT_UART: return "uart";
- case BFIN_BOOT_IDLE: return "idle";
- case BFIN_BOOT_FIFO: return "fifo";
- case BFIN_BOOT_MEM: return "memory";
- case BFIN_BOOT_16HOST_DMA: return "16bit dma";
- case BFIN_BOOT_8HOST_DMA: return "8bit dma";
- case BFIN_BOOT_NAND: return "nand flash";
- case BFIN_BOOT_RSI_MASTER: return "rsi master";
- case BFIN_BOOT_LP_SLAVE: return "link port slave";
- default: return "INVALID";
- }
-}
-#endif
-
-/* Most bootroms allow for EVT1 redirection */
-#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
- && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
-# undef CONFIG_BFIN_BOOTROM_USES_EVT1
-#else
-# define CONFIG_BFIN_BOOTROM_USES_EVT1
-#endif
-
-/* Define the default SPI CS used when booting out of SPI */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
- defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
- defined(__ADSPBF51x__)
-# define BFIN_BOOT_SPI_SSEL 2
-#else
-# define BFIN_BOOT_SPI_SSEL 1
-#endif
-
-/* Define to get a GPIO CS with the Blackfin SPI controller */
-#define MAX_CTRL_CS 8
-
-/* There is no Blackfin/NetBSD port */
-#undef CONFIG_BOOTM_NETBSD
-
-/* We rarely use interrupts, so favor throughput over latency */
-#define CONFIG_BFIN_INS_LOWOVERHEAD
-
-#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
deleted file mode 100644
index 4e8313d811e2..000000000000
--- a/arch/blackfin/include/asm/config.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * config.h - setup common defines for Blackfin boards based on config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
-#define __ASM_BLACKFIN_CONFIG_POST_H__
-
-/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
-#include <asm-offsets.h>
-
-/* Sanity check CONFIG_BFIN_CPU */
-#ifndef CONFIG_BFIN_CPU
-# error CONFIG_BFIN_CPU: your board config needs to define this
-#endif
-
-#ifndef CONFIG_BFIN_SCRATCH_REG
-# define CONFIG_BFIN_SCRATCH_REG retn
-#endif
-
-/* U-Boot wants this config name */
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-
-/* Make sure the structure is properly aligned */
-#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
-# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
-#endif
-
-/* Set default CONFIG_VCO_HZ if need be */
-#if !defined(CONFIG_VCO_HZ)
-# if (CONFIG_CLKIN_HALF == 0)
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
-# endif
-#endif
-
-/* Set default CONFIG_CCLK_HZ if need be */
-#if !defined(CONFIG_CCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
-# else
-# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Set default CONFIG_SCLK_HZ if need be */
-#if !defined(CONFIG_SCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
-# else
-# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Since we use these to program PLL registers directly,
- * make sure the values are sane and won't screw us up.
- */
-#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
-# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
-#endif
-#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
-# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
-#endif
-#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
-# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
-#endif
-
-/* If we are using KGDB, make sure we defer exceptions */
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_EXCEPTION_DEFER 1
-#endif
-
-/* Using L1 scratch pad makes sense for everyone by default. */
-#ifndef CONFIG_LINUX_CMDLINE_ADDR
-# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
-#endif
-#ifndef CONFIG_LINUX_CMDLINE_SIZE
-# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
-#endif
-
-/* Set default SPI flash CS to the one we boot from */
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
-# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
-#endif
-
-/* We need envcrc to embed the env into LDRs */
-#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
-# define CONFIG_BUILD_ENVCRC
-#endif
-
-/* Default/common Blackfin memory layout */
-#ifndef CONFIG_SYS_SDRAM_BASE
-# define CONFIG_SYS_SDRAM_BASE 0
-#endif
-#ifndef CONFIG_SYS_MAX_RAM_SIZE
-# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
-#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-# if CONFIG_SYS_MAX_RAM_SIZE
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-# else
-# define CONFIG_SYS_MONITOR_BASE 0
-# endif
-#endif
-#ifndef CONFIG_SYS_MALLOC_BASE
-# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#endif
-#ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
-#endif
-#ifndef CONFIG_SYS_MEMTEST_START
-# define CONFIG_SYS_MEMTEST_START 0
-#endif
-#ifndef CONFIG_SYS_MEMTEST_END
-# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
-#endif
-#ifndef CONFIG_SYS_POST_WORD_ADDR
-# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4)
-#endif
-
-/* Check to make sure everything fits in external RAM */
-#if CONFIG_SYS_MAX_RAM_SIZE && \
- ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
-# error Memory Map does not fit into configuration
-#endif
-
-/* Default/common Blackfin environment settings */
-#ifndef CONFIG_LOADADDR
-# define CONFIG_LOADADDR 0x1000000
-#endif
-#ifndef CONFIG_SYS_LOAD_ADDR
-# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#endif
-#ifndef CONFIG_SYS_BOOTM_LEN
-# define CONFIG_SYS_BOOTM_LEN 0x4000000
-#endif
-#ifndef CONFIG_SYS_CBSIZE
-# define CONFIG_SYS_CBSIZE 1024
-#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
-# error "kgdb needs cbsize to be >= 1024"
-#endif
-#ifndef CONFIG_SYS_BARGSIZE
-# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#endif
-#ifndef CONFIG_SYS_PBSIZE
-# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#endif
-#ifndef CONFIG_SYS_MAXARGS
-# define CONFIG_SYS_MAXARGS 16
-#endif
-
-/* Blackfin POST tests */
-#ifdef CONFIG_POST_BSPEC1_GPIO_LEDS
-# define CONFIG_POST_BSPEC1 \
- { \
- "LED test", "led", "This test verifies LEDs on the board.", \
- POST_MEM | POST_ALWAYS, &led_post_test, NULL, NULL, \
- CONFIG_SYS_POST_BSPEC1, \
- }
-#endif
-#ifdef CONFIG_POST_BSPEC2_GPIO_BUTTONS
-# define CONFIG_POST_BSPEC2 \
- { \
- "Button test", "button", "This test verifies buttons on the board.", \
- POST_MEM | POST_ALWAYS, &button_post_test, NULL, NULL, \
- CONFIG_SYS_POST_BSPEC2, \
- }
-#endif
-
-#define CONFIG_CPU CONFIG_BFIN_CPU
-
-#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 420380dab1cb..000000000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * cplb.h - defines for managing CPLB tables
- *
- * Copyright (c) 2002-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPLB_H__
-#define __ASM_BLACKFIN_CPLB_H__
-
-#include <asm/mach-common/bits/mpu.h>
-
-#define CPLB_ENABLE_ICACHE_P 0
-#define CPLB_ENABLE_DCACHE_P 1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P 4
-#define CPLB_ENABLE_DCPLBS_P 5
-
-#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
- CPLB_ENABLE_ICPLBS | \
- CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED 0x0000
-#define CPLB_NO_UNLOCKED 0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL 0x0003
-
-#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-
-/* Data Attibutes*/
-#if defined(__ADSPBF60x__)
-#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
- CPLB_USER_RD | CPLB_VALID)
-#else
-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
- CPLB_USER_RD | CPLB_VALID)
-#endif
-#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-# define ANOMALY_05000158_WORKAROUND 0x200
-#else
-# define ANOMALY_05000158_WORKAROUND 0
-#endif
-
-#ifdef CONFIG_DCACHE_WB /*Write Back Policy */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
- CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
- CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
- CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
- CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#else /*Write Through */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
- CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
- CPLB_USER_WR | CPLB_VALID | \
- ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
- CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
- CPLB_USER_WR | CPLB_VALID | \
- ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-
-#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/deferred.h b/arch/blackfin/include/asm/deferred.h
deleted file mode 100644
index e75d7e80ada3..000000000000
--- a/arch/blackfin/include/asm/deferred.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * U-Boot - deferred register layout
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DEFER_H
-#define _BLACKFIN_DEFER_H
-
-#define deferred_regs_DCPLB_FAULT_ADDR 0
-#define deferred_regs_ICPLB_FAULT_ADDR 1
-#define deferred_regs_retx 2
-#define deferred_regs_SEQSTAT 3
-#define deferred_regs_SYSCFG 4
-#define deferred_regs_IMASK 5
-#define deferred_regs_last 6
-
-#endif /* _BLACKFIN_DEFER_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
deleted file mode 100644
index 06c3edd03ebb..000000000000
--- a/arch/blackfin/include/asm/delay.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * U-Boot - delay.h Routines for introducing delays
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-/*
- * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
- * Copyright (C) 1994 Hamish Macdonald
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-static __inline__ void __delay(unsigned long loops)
-{
- __asm__ __volatile__("1:\t%0 += -1;\n\t"
- "cc = %0 == 0;\n\t"
- "if ! cc jump 1b;\n":"=d"(loops)
- :"0"(loops));
-}
-
-/*
- * Use only for very small delays ( < 1 msec). Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays. This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-static __inline__ void __udelay(unsigned long usecs)
-{
- __delay(usecs);
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 8a7c07933ebf..000000000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/types.h>
-#ifdef __ADSPBF60x__
-#include <asm/mach-common/bits/dde.h>
-#else
-#include <asm/mach-common/bits/dma.h>
-#endif
-
-struct dmasg_large {
- void *next_desc_addr;
- u32 start_addr;
- u16 cfg;
- u16 x_count;
- s16 x_modify;
- u16 y_count;
- s16 y_modify;
-} __attribute__((packed));
-
-struct dmasg {
- u32 start_addr;
- u16 cfg;
- u16 x_count;
- s16 x_modify;
- u16 y_count;
- s16 y_modify;
-} __attribute__((packed));
-
-struct dma_register {
-#ifdef __ADSPBF60x__
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- u32 start_addr; /* DMA Start address register */
- u32 config; /* DMA Configuration register */
-
- u32 x_count; /* DMA x_count register */
- s32 x_modify; /* DMA x_modify register */
- u32 y_count; /* DMA y_count register */
- s32 y_modify; /* DMA y_modify register */
- u32 __pad0[2];
-
- void *curr_desc_ptr; /* DMA Curr Descriptor Pointer register */
- void *prev_desc_ptr; /* DMA Prev Descriptor Pointer register */
- void *curr_addr; /* DMA Current Address Pointer register */
- u32 status; /* DMA irq status register */
- u32 curr_x_count; /* DMA Current x-count register */
- u32 curr_y_count; /* DMA Current y-count register */
- u32 __pad1[2];
-
- u32 bw_limit; /* DMA Bandwidth Limit Count */
- u32 curr_bw_limit; /* DMA curr Bandwidth Limit Count */
- u32 bw_monitor; /* DMA Bandwidth Monitor Count */
- u32 curr_bw_monitor; /* DMA curr Bandwidth Monitor Count */
-#else
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- u32 start_addr; /* DMA Start address register */
-
- u16 config; /* DMA Configuration register */
- u16 dummy1; /* DMA Configuration register */
-
- u32 reserved;
-
- u16 x_count; /* DMA x_count register */
- u16 dummy2;
-
- s16 x_modify; /* DMA x_modify register */
- u16 dummy3;
-
- u16 y_count; /* DMA y_count register */
- u16 dummy4;
-
- s16 y_modify; /* DMA y_modify register */
- u16 dummy5;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer register */
-
- u32 curr_addr_ptr; /* DMA Current Address Pointer register */
-
- u16 status; /* DMA irq status register */
- u16 dummy6;
-
- u16 peripheral_map; /* DMA peripheral map register */
- u16 dummy7;
-
- u16 curr_x_count; /* DMA Current x-count register */
- u16 dummy8;
-
- u32 reserved2;
-
- u16 curr_y_count; /* DMA Current y-count register */
- u16 dummy9;
-
- u32 reserved3;
-#endif
-};
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index 98fe79c93caf..000000000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * entry.h - routines for context saving and restoring (for interrupts/exceptions)
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __BLACKFIN_ENTRY_H
-#define __BLACKFIN_ENTRY_H
-#ifdef __ASSEMBLY__
-
-#define SAVE_ALL_INT save_context_no_interrupts
-#define SAVE_ALL_SYS save_context_no_interrupts
-#define SAVE_CONTEXT save_context_with_interrupts
-
-#define RESTORE_ALL restore_context_no_interrupts
-#define RESTORE_ALL_SYS restore_context_no_interrupts
-#define RESTORE_CONTEXT restore_context_with_interrupts
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
- [--sp] = R0;
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- [--sp] = RETI;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
- p0.l = lo(IPEND)
- p0.h = hi(IPEND)
- r0 = [p0];
-#endif
- [--sp] = r0; /* Skip IPEND as well. */
-.endm
-
-.macro save_context_no_interrupts
- [--sp] = R0;
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
- p0.l = lo(IPEND)
- p0.h = hi(IPEND)
- r0 = [p0];
-#endif
- [--sp] = r0; /* Skip IPEND as well. */
-.endm
-
-.macro restore_context_no_interrupts
- sp += 4;
- SYSCFG = [sp++];
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- r0 = [sp++];
- RETI = r0;
- RETS = [sp++];
-
- sp += 4;
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 4;
-.endm
-
-.macro restore_context_with_interrupts
- sp += 4;
- SYSCFG = [sp++];
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- RETI = [sp++];
- RETS = [sp++];
-
- sp += 4;
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 4;
-.endm
-
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
deleted file mode 100644
index 69a6971dd02b..000000000000
--- a/arch/blackfin/include/asm/global_data.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - global_data.h Declarations for global data of U-Boot
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <asm/u-boot.h>
-
-/* Architecture-specific global data */
-struct arch_global_data {
- unsigned long board_type;
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P3")
-
-#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
deleted file mode 100644
index 1fa1a8e6ecf7..000000000000
--- a/arch/blackfin/include/asm/gpio.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#include <asm-generic/gpio.h>
-#include <asm/portmux.h>
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#define GPIO_0 0
-#define GPIO_1 1
-#define GPIO_2 2
-#define GPIO_3 3
-#define GPIO_4 4
-#define GPIO_5 5
-#define GPIO_6 6
-#define GPIO_7 7
-#define GPIO_8 8
-#define GPIO_9 9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-#define MAX_GPIOS MAX_BLACKFIN_GPIOS
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_ADI_GPIO2
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
- unsigned short data;
- unsigned short dummy1;
- unsigned short data_clear;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short toggle;
- unsigned short dummy4;
- unsigned short maska;
- unsigned short dummy5;
- unsigned short maska_clear;
- unsigned short dummy6;
- unsigned short maska_set;
- unsigned short dummy7;
- unsigned short maska_toggle;
- unsigned short dummy8;
- unsigned short maskb;
- unsigned short dummy9;
- unsigned short maskb_clear;
- unsigned short dummy10;
- unsigned short maskb_set;
- unsigned short dummy11;
- unsigned short maskb_toggle;
- unsigned short dummy12;
- unsigned short dir;
- unsigned short dummy13;
- unsigned short polar;
- unsigned short dummy14;
- unsigned short edge;
- unsigned short dummy15;
- unsigned short both;
- unsigned short dummy16;
- unsigned short inen;
-};
-#else
-extern struct gpio_port_t * const gpio_array[];
-#endif
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-void special_gpio_free(unsigned gpio);
-int special_gpio_request(unsigned gpio, const char *label);
-#endif
-
-void gpio_labels(void);
-
-static inline int gpio_is_valid(int number)
-{
- return number >= 0 && number < MAX_GPIOS;
-}
-
-#include <linux/ctype.h>
-
-#define gpio_status() gpio_labels()
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index d3337e4facfc..000000000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * U-Boot - io.h IO routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_IO_H
-#define _BLACKFIN_IO_H
-
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-
-static inline void sync(void)
-{
- SSYNC();
-}
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE (0)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
- return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
- return (phys_addr_t)(vaddr);
-}
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
- unsigned int val;
- int tmp;
-
- __asm__ __volatile__ (
- "cli %1;"
- "NOP; NOP; SSYNC;"
- "%0 = b [%2] (z);"
- "sti %1;"
- : "=d"(val), "=d"(tmp)
- : "a"(addr)
- );
-
- return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
- unsigned int val;
- int tmp;
-
- __asm__ __volatile__ (
- "cli %1;"
- "NOP; NOP; SSYNC;"
- "%0 = w [%2] (z);"
- "sti %1;"
- : "=d"(val), "=d"(tmp)
- : "a"(addr)
- );
-
- return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
- unsigned int val;
- int tmp;
-
- __asm__ __volatile__ (
- "cli %1;"
- "NOP; NOP; SSYNC;"
- "%0 = [%2];"
- "sti %1;"
- : "=d"(val), "=d"(tmp)
- : "a"(addr)
- );
-
- return val;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c) memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port) readb(__io(port))
-#define inw(port) readw(__io(port))
-#define inl(port) readl(__io(port))
-#define in_le32(port) inl(port)
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-#define out_le32(x, port) outl(x, port)
-
-#define inb_p(port) inb(__io(port))
-#define inw_p(port) inw(__io(port))
-#define inl_p(port) inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c) readsb(a, d, c)
-#define ioread16_rep(a, d, c) readsw(a, d, c)
-#define ioread32_rep(a, d, c) readsl(a, d, c)
-#define iowrite8_rep(a, s, c) writesb(a, s, c)
-#define iowrite16_rep(a, s, c) writesw(a, s, c)
-#define iowrite32_rep(a, s, c) writesl(a, s, c)
-
-#define ioread8(x) readb(x)
-#define ioread16(x) readw(x)
-#define ioread32(x) readl(x)
-#define iowrite8(val, x) writeb(val, x)
-#define iowrite16(val, x) writew(val, x)
-#define iowrite32(val, x) writel(val, x)
-
-#define mmiowb() wmb()
-
-#ifndef __ASSEMBLY__
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
- insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
- insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
- insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
- outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
- outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
- outsb((unsigned long)addr, buf, len);
-}
-
-#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
-/* This hack for CF/IDE needs to be addressed at some point */
-extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
-extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
-extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char *addr);
-#undef inb
-#undef outb
-#undef insw
-#undef outsw
-#define inb(addr) cf_inb((void *)(addr))
-#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
-#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
-#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
-#endif
-
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index 60d5317797a0..000000000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * U-Boot - linkage.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
deleted file mode 100644
index 27864e5b3ea3..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
+++ /dev/null
@@ -1,1782 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF504_proc__
-#define __BFIN_CDEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MODE() bfin_read16(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write16(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PWM1_CTRL() bfin_read16(PWM1_CTRL)
-#define bfin_write_PWM1_CTRL(val) bfin_write16(PWM1_CTRL, val)
-#define bfin_read_PWM1_STAT() bfin_read16(PWM1_STAT)
-#define bfin_write_PWM1_STAT(val) bfin_write16(PWM1_STAT, val)
-#define bfin_read_PWM1_TM() bfin_read16(PWM1_TM)
-#define bfin_write_PWM1_TM(val) bfin_write16(PWM1_TM, val)
-#define bfin_read_PWM1_DT() bfin_read16(PWM1_DT)
-#define bfin_write_PWM1_DT(val) bfin_write16(PWM1_DT, val)
-#define bfin_read_PWM1_GATE() bfin_read16(PWM1_GATE)
-#define bfin_write_PWM1_GATE(val) bfin_write16(PWM1_GATE, val)
-#define bfin_read_PWM1_CHA() bfin_read16(PWM1_CHA)
-#define bfin_write_PWM1_CHA(val) bfin_write16(PWM1_CHA, val)
-#define bfin_read_PWM1_CHB() bfin_read16(PWM1_CHB)
-#define bfin_write_PWM1_CHB(val) bfin_write16(PWM1_CHB, val)
-#define bfin_read_PWM1_CHC() bfin_read16(PWM1_CHC)
-#define bfin_write_PWM1_CHC(val) bfin_write16(PWM1_CHC, val)
-#define bfin_read_PWM1_SEG() bfin_read16(PWM1_SEG)
-#define bfin_write_PWM1_SEG(val) bfin_write16(PWM1_SEG, val)
-#define bfin_read_PWM1_SYNCWT() bfin_read16(PWM1_SYNCWT)
-#define bfin_write_PWM1_SYNCWT(val) bfin_write16(PWM1_SYNCWT, val)
-#define bfin_read_PWM1_CHAL() bfin_read16(PWM1_CHAL)
-#define bfin_write_PWM1_CHAL(val) bfin_write16(PWM1_CHAL, val)
-#define bfin_read_PWM1_CHBL() bfin_read16(PWM1_CHBL)
-#define bfin_write_PWM1_CHBL(val) bfin_write16(PWM1_CHBL, val)
-#define bfin_read_PWM1_CHCL() bfin_read16(PWM1_CHCL)
-#define bfin_write_PWM1_CHCL(val) bfin_write16(PWM1_CHCL, val)
-#define bfin_read_PWM1_LSI() bfin_read16(PWM1_LSI)
-#define bfin_write_PWM1_LSI(val) bfin_write16(PWM1_LSI, val)
-#define bfin_read_PWM1_STAT2() bfin_read16(PWM1_STAT2)
-#define bfin_write_PWM1_STAT2(val) bfin_write16(PWM1_STAT2, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_FLASH_CONTROL() bfin_read16(FLASH_CONTROL)
-#define bfin_write_FLASH_CONTROL(val) bfin_write16(FLASH_CONTROL, val)
-#define bfin_read_FLASH_CONTROL_SET() bfin_read16(FLASH_CONTROL_SET)
-#define bfin_write_FLASH_CONTROL_SET(val) bfin_write16(FLASH_CONTROL_SET, val)
-#define bfin_read_FLASH_CONTROL_CLEAR() bfin_read16(FLASH_CONTROL_CLEAR)
-#define bfin_write_FLASH_CONTROL_CLEAR(val) bfin_write16(FLASH_CONTROL_CLEAR, val)
-#define bfin_read_CNT1_CONFIG() bfin_read16(CNT1_CONFIG)
-#define bfin_write_CNT1_CONFIG(val) bfin_write16(CNT1_CONFIG, val)
-#define bfin_read_CNT1_IMASK() bfin_read16(CNT1_IMASK)
-#define bfin_write_CNT1_IMASK(val) bfin_write16(CNT1_IMASK, val)
-#define bfin_read_CNT1_STATUS() bfin_read16(CNT1_STATUS)
-#define bfin_write_CNT1_STATUS(val) bfin_write16(CNT1_STATUS, val)
-#define bfin_read_CNT1_COMMAND() bfin_read16(CNT1_COMMAND)
-#define bfin_write_CNT1_COMMAND(val) bfin_write16(CNT1_COMMAND, val)
-#define bfin_read_CNT1_DEBOUNCE() bfin_read16(CNT1_DEBOUNCE)
-#define bfin_write_CNT1_DEBOUNCE(val) bfin_write16(CNT1_DEBOUNCE, val)
-#define bfin_read_CNT1_COUNTER() bfin_read32(CNT1_COUNTER)
-#define bfin_write_CNT1_COUNTER(val) bfin_write32(CNT1_COUNTER, val)
-#define bfin_read_CNT1_MAX() bfin_read32(CNT1_MAX)
-#define bfin_write_CNT1_MAX(val) bfin_write32(CNT1_MAX, val)
-#define bfin_read_CNT1_MIN() bfin_read32(CNT1_MIN)
-#define bfin_write_CNT1_MIN(val) bfin_write32(CNT1_MIN, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_CNT0_CONFIG() bfin_read16(CNT0_CONFIG)
-#define bfin_write_CNT0_CONFIG(val) bfin_write16(CNT0_CONFIG, val)
-#define bfin_read_CNT0_IMASK() bfin_read16(CNT0_IMASK)
-#define bfin_write_CNT0_IMASK(val) bfin_write16(CNT0_IMASK, val)
-#define bfin_read_CNT0_STATUS() bfin_read16(CNT0_STATUS)
-#define bfin_write_CNT0_STATUS(val) bfin_write16(CNT0_STATUS, val)
-#define bfin_read_CNT0_COMMAND() bfin_read16(CNT0_COMMAND)
-#define bfin_write_CNT0_COMMAND(val) bfin_write16(CNT0_COMMAND, val)
-#define bfin_read_CNT0_DEBOUNCE() bfin_read16(CNT0_DEBOUNCE)
-#define bfin_write_CNT0_DEBOUNCE(val) bfin_write16(CNT0_DEBOUNCE, val)
-#define bfin_read_CNT0_COUNTER() bfin_read32(CNT0_COUNTER)
-#define bfin_write_CNT0_COUNTER(val) bfin_write32(CNT0_COUNTER, val)
-#define bfin_read_CNT0_MAX() bfin_read32(CNT0_MAX)
-#define bfin_write_CNT0_MAX(val) bfin_write32(CNT0_MAX, val)
-#define bfin_read_CNT0_MIN() bfin_read32(CNT0_MIN)
-#define bfin_write_CNT0_MIN(val) bfin_write32(CNT0_MIN, val)
-#define bfin_read_PWM0_CTRL() bfin_read16(PWM0_CTRL)
-#define bfin_write_PWM0_CTRL(val) bfin_write16(PWM0_CTRL, val)
-#define bfin_read_PWM0_STAT() bfin_read16(PWM0_STAT)
-#define bfin_write_PWM0_STAT(val) bfin_write16(PWM0_STAT, val)
-#define bfin_read_PWM0_TM() bfin_read16(PWM0_TM)
-#define bfin_write_PWM0_TM(val) bfin_write16(PWM0_TM, val)
-#define bfin_read_PWM0_DT() bfin_read16(PWM0_DT)
-#define bfin_write_PWM0_DT(val) bfin_write16(PWM0_DT, val)
-#define bfin_read_PWM0_GATE() bfin_read16(PWM0_GATE)
-#define bfin_write_PWM0_GATE(val) bfin_write16(PWM0_GATE, val)
-#define bfin_read_PWM0_CHA() bfin_read16(PWM0_CHA)
-#define bfin_write_PWM0_CHA(val) bfin_write16(PWM0_CHA, val)
-#define bfin_read_PWM0_CHB() bfin_read16(PWM0_CHB)
-#define bfin_write_PWM0_CHB(val) bfin_write16(PWM0_CHB, val)
-#define bfin_read_PWM0_CHC() bfin_read16(PWM0_CHC)
-#define bfin_write_PWM0_CHC(val) bfin_write16(PWM0_CHC, val)
-#define bfin_read_PWM0_SEG() bfin_read16(PWM0_SEG)
-#define bfin_write_PWM0_SEG(val) bfin_write16(PWM0_SEG, val)
-#define bfin_read_PWM0_SYNCWT() bfin_read16(PWM0_SYNCWT)
-#define bfin_write_PWM0_SYNCWT(val) bfin_write16(PWM0_SYNCWT, val)
-#define bfin_read_PWM0_CHAL() bfin_read16(PWM0_CHAL)
-#define bfin_write_PWM0_CHAL(val) bfin_write16(PWM0_CHAL, val)
-#define bfin_read_PWM0_CHBL() bfin_read16(PWM0_CHBL)
-#define bfin_write_PWM0_CHBL(val) bfin_write16(PWM0_CHBL, val)
-#define bfin_read_PWM0_CHCL() bfin_read16(PWM0_CHCL)
-#define bfin_write_PWM0_CHCL(val) bfin_write16(PWM0_CHCL, val)
-#define bfin_read_PWM0_LSI() bfin_read16(PWM0_LSI)
-#define bfin_write_PWM0_LSI(val) bfin_write16(PWM0_LSI, val)
-#define bfin_read_PWM0_STAT2() bfin_read16(PWM0_STAT2)
-#define bfin_write_PWM0_STAT2(val) bfin_write16(PWM0_STAT2, val)
-#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF504_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_def.h b/arch/blackfin/include/asm/mach-bf506/BF504_def.h
deleted file mode 100644
index 8b0345f313ab..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/BF504_def.h
+++ /dev/null
@@ -1,944 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF504_proc__
-#define __BFIN_DEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_MODE 0xFFC00A20 /* Asynchronous Memory Mode Control Register */
-#define EBIU_FCTL 0xFFC00A24 /* Asynchronous Memory Parameter Control Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define CAN_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define PWM1_CTRL 0xFFC03000 /* PWM1 Control Register */
-#define PWM1_STAT 0xFFC03004 /* PWM1 Status Register */
-#define PWM1_TM 0xFFC03008 /* PWM1 Period Register */
-#define PWM1_DT 0xFFC0300C /* PWM1 Dead Time Register */
-#define PWM1_GATE 0xFFC03010 /* PWM1 Chopping Control */
-#define PWM1_CHA 0xFFC03014 /* PWM1 Channel A Duty Control */
-#define PWM1_CHB 0xFFC03018 /* PWM1 Channel B Duty Control */
-#define PWM1_CHC 0xFFC0301C /* PWM1 Channel C Duty Control */
-#define PWM1_SEG 0xFFC03020 /* PWM1 Crossover and Output Enable */
-#define PWM1_SYNCWT 0xFFC03024 /* PWM1 Sync pulse width control */
-#define PWM1_CHAL 0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */
-#define PWM1_CHBL 0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */
-#define PWM1_CHCL 0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */
-#define PWM1_LSI 0xFFC03034 /* Low Side Invert (SR mode only) */
-#define PWM1_STAT2 0xFFC03038 /* PWM1 Status Register */
-#define ACM_CTL 0xFFC03100 /* ACM Control Register */
-#define ACM_TC0 0xFFC03104 /* ACM Timing Configuration 0 Register */
-#define ACM_TC1 0xFFC03108 /* ACM Timing Configuration 1 Register */
-#define ACM_STAT 0xFFC0310C /* ACM Status Register */
-#define ACM_ES 0xFFC03110 /* ACM Event Status Register */
-#define ACM_IMSK 0xFFC03114 /* ACM Interrupt Mask Register */
-#define ACM_MS 0xFFC03118 /* ACM Missed Event Status Register */
-#define ACM_EMSK 0xFFC0311C /* ACM Missed Event Interrupt Mask Register */
-#define ACM_ER0 0xFFC03120 /* ACM Event 0 Control Register */
-#define ACM_ER1 0xFFC03124 /* ACM Event 1 Control Register */
-#define ACM_ER2 0xFFC03128 /* ACM Event 2 Control Register */
-#define ACM_ER3 0xFFC0312C /* ACM Event 3 Control Register */
-#define ACM_ER4 0xFFC03130 /* ACM Event 4 Control Register */
-#define ACM_ER5 0xFFC03134 /* ACM Event 5 Control Register */
-#define ACM_ER6 0xFFC03138 /* ACM Event 6 Control Register */
-#define ACM_ER7 0xFFC0313C /* ACM Event 7 Control Register */
-#define ACM_ER8 0xFFC03140 /* ACM Event 8 Control Register */
-#define ACM_ER9 0xFFC03144 /* ACM Event 9 Control Register */
-#define ACM_ER10 0xFFC03148 /* ACM Event 10 Control Register */
-#define ACM_ER11 0xFFC0314C /* ACM Event 11 Control Register */
-#define ACM_ER12 0xFFC03150 /* ACM Event 12 Control Register */
-#define ACM_ER13 0xFFC03154 /* ACM Event 13 Control Register */
-#define ACM_ER14 0xFFC03158 /* ACM Event 14 Control Register */
-#define ACM_ER15 0xFFC0315C /* ACM Event 15 Control Register */
-#define ACM_ET0 0xFFC03180 /* ACM Event 0 Time Register */
-#define ACM_ET1 0xFFC03184 /* ACM Event 1 Time Register */
-#define ACM_ET2 0xFFC03188 /* ACM Event 2 Time Register */
-#define ACM_ET3 0xFFC0318C /* ACM Event 3 Time Register */
-#define ACM_ET4 0xFFC03190 /* ACM Event 4 Time Register */
-#define ACM_ET5 0xFFC03194 /* ACM Event 5 Time Register */
-#define ACM_ET6 0xFFC03198 /* ACM Event 6 Time Register */
-#define ACM_ET7 0xFFC0319C /* ACM Event 7 Time Register */
-#define ACM_ET8 0xFFC031A0 /* ACM Event 8 Time Register */
-#define ACM_ET9 0xFFC031A4 /* ACM Event 9 Time Register */
-#define ACM_ET10 0xFFC031A8 /* ACM Event 10 Time Register */
-#define ACM_ET11 0xFFC031AC /* ACM Event 11 Time Register */
-#define ACM_ET12 0xFFC031B0 /* ACM Event 12 Time Register */
-#define ACM_ET13 0xFFC031B4 /* ACM Event 13 Time Register */
-#define ACM_ET14 0xFFC031B8 /* ACM Event 14 Time Register */
-#define ACM_ET15 0xFFC031BC /* ACM Event 15 Time Register */
-#define ACM_TMR0 0xFFC031C0 /* ACM Timer 0 Registers */
-#define ACM_TMR1 0xFFC031C4 /* ACM Timer 1 Registers */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define FLASH_CONTROL 0xFFC0328C /* Stacked flash control register */
-#define FLASH_CONTROL_SET 0xFFC03290 /* Stacked flash control set register */
-#define FLASH_CONTROL_CLEAR 0xFFC03294 /* Stacked flash control clear register */
-#define CNT1_CONFIG 0xFFC03300 /* Counter 1 Configuration Register */
-#define CNT1_IMASK 0xFFC03304 /* Counter 1 Interrupt Mask Register */
-#define CNT1_STATUS 0xFFC03308 /* Counter 1 Status Register */
-#define CNT1_COMMAND 0xFFC0330C /* Counter 1 Command Register */
-#define CNT1_DEBOUNCE 0xFFC03310 /* Counter 1 Debounce Register */
-#define CNT1_COUNTER 0xFFC03314 /* Counter 1 Counter Register */
-#define CNT1_MAX 0xFFC03318 /* Counter 1 Boundry Value Register - max count */
-#define CNT1_MIN 0xFFC0331C /* Counter 1 Boundry Value Register - min count */
-#define SPI1_CTL 0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define CNT0_CONFIG 0xFFC03500 /* Configuration/Control Register */
-#define CNT0_IMASK 0xFFC03504 /* Interrupt Mask Register */
-#define CNT0_STATUS 0xFFC03508 /* Status Register */
-#define CNT0_COMMAND 0xFFC0350C /* Command Register */
-#define CNT0_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */
-#define CNT0_COUNTER 0xFFC03514 /* Counter Register */
-#define CNT0_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT0_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */
-#define PWM0_CTRL 0xFFC03700 /* PWM Control Register */
-#define PWM0_STAT 0xFFC03704 /* PWM Status Register */
-#define PWM0_TM 0xFFC03708 /* PWM Period Register */
-#define PWM0_DT 0xFFC0370C /* PWM Dead Time Register */
-#define PWM0_GATE 0xFFC03710 /* PWM Chopping Control */
-#define PWM0_CHA 0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM0_CHB 0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM0_CHC 0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM0_SEG 0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM0_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */
-#define PWM0_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM0_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM0_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM0_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM0_STAT2 0xFFC03738 /* PWM Status Register */
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE 0x8000
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE 0x8000
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF504_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
deleted file mode 100644
index 4c5baac39572..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF506_proc__
-#define __BFIN_CDEF_ADSP_BF506_proc__
-
-#include "BF504_cdef.h"
-
-#endif /* __BFIN_CDEF_ADSP_BF506_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_def.h b/arch/blackfin/include/asm/mach-bf506/BF506_def.h
deleted file mode 100644
index 1f91397ea432..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/BF506_def.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF506_proc__
-#define __BFIN_DEF_ADSP_BF506_proc__
-
-#include "BF504_def.h"
-
-#endif /* __BFIN_DEF_ADSP_BF506_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h
deleted file mode 100644
index 5b3227a8ea38..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/anomaly.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
-#define ANOMALY_05000476 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
-#define ANOMALY_05000478 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
-#define ANOMALY_05000486 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
-#define ANOMALY_05000495 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf506/def_local.h b/arch/blackfin/include/asm/mach-bf506/def_local.h
deleted file mode 100644
index e7a416db8ede..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF50x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf506/gpio.h b/arch/blackfin/include/asm/mach-bf506/gpio.h
deleted file mode 100644
index 08a82f4001b7..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/gpio.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 35
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf506/portmux.h b/arch/blackfin/include/asm/mach-bf506/portmux.h
deleted file mode 100644
index 086186d0754e..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/portmux.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF13
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-
-/* UART Port Mux */
-#ifdef CONFIG_BF506_UART0_PORTF
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#else
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#endif
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF506_UART1_PORTG
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#else
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#endif
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-
-/* CAN */
-#define P_CAN_TX (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_CAN_RX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-
-/* PWM */
-#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PWM0_TRIP (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-
-#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_PWM1_TRIP (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-
-/* ACM */
-#define P_ACM_SE_DIFF (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_ACM_RANGE (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_ACM_A0 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_ACM_A1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ACM_A2 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf506/ports.h b/arch/blackfin/include/asm/mach-bf506/ports.h
deleted file mode 100644
index f1e9cc00d4df..000000000000
--- a/arch/blackfin/include/asm/mach-bf506/ports.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK 0x0003
-#define PORT_x_MUX_1_MASK 0x000C
-#define PORT_x_MUX_2_MASK 0x0030
-#define PORT_x_MUX_3_MASK 0x00C0
-#define PORT_x_MUX_4_MASK 0x0300
-#define PORT_x_MUX_5_MASK 0x0C00
-#define PORT_x_MUX_6_MASK 0x3000
-#define PORT_x_MUX_7_MASK 0xC000
-
-#define PORT_x_MUX_FUNC_1 (0x0)
-#define PORT_x_MUX_FUNC_2 (0x1)
-#define PORT_x_MUX_FUNC_3 (0x2)
-#define PORT_x_MUX_FUNC_4 (0x3)
-#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
deleted file mode 100644
index db70e7740940..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
+++ /dev/null
@@ -1,1000 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF512_proc__
-#define __BFIN_CDEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PWM_CTRL() bfin_read16(PWM_CTRL)
-#define bfin_write_PWM_CTRL(val) bfin_write16(PWM_CTRL, val)
-#define bfin_read_PWM_STAT() bfin_read16(PWM_STAT)
-#define bfin_write_PWM_STAT(val) bfin_write16(PWM_STAT, val)
-#define bfin_read_PWM_TM() bfin_read16(PWM_TM)
-#define bfin_write_PWM_TM(val) bfin_write16(PWM_TM, val)
-#define bfin_read_PWM_DT() bfin_read16(PWM_DT)
-#define bfin_write_PWM_DT(val) bfin_write16(PWM_DT, val)
-#define bfin_read_PWM_GATE() bfin_read16(PWM_GATE)
-#define bfin_write_PWM_GATE(val) bfin_write16(PWM_GATE, val)
-#define bfin_read_PWM_CHA() bfin_read16(PWM_CHA)
-#define bfin_write_PWM_CHA(val) bfin_write16(PWM_CHA, val)
-#define bfin_read_PWM_CHB() bfin_read16(PWM_CHB)
-#define bfin_write_PWM_CHB(val) bfin_write16(PWM_CHB, val)
-#define bfin_read_PWM_CHC() bfin_read16(PWM_CHC)
-#define bfin_write_PWM_CHC(val) bfin_write16(PWM_CHC, val)
-#define bfin_read_PWM_SEG() bfin_read16(PWM_SEG)
-#define bfin_write_PWM_SEG(val) bfin_write16(PWM_SEG, val)
-#define bfin_read_PWM_SYNCWT() bfin_read16(PWM_SYNCWT)
-#define bfin_write_PWM_SYNCWT(val) bfin_write16(PWM_SYNCWT, val)
-#define bfin_read_PWM_CHAL() bfin_read16(PWM_CHAL)
-#define bfin_write_PWM_CHAL(val) bfin_write16(PWM_CHAL, val)
-#define bfin_read_PWM_CHBL() bfin_read16(PWM_CHBL)
-#define bfin_write_PWM_CHBL(val) bfin_write16(PWM_CHBL, val)
-#define bfin_read_PWM_CHCL() bfin_read16(PWM_CHCL)
-#define bfin_write_PWM_CHCL(val) bfin_write16(PWM_CHCL, val)
-#define bfin_read_PWM_LSI() bfin_read16(PWM_LSI)
-#define bfin_write_PWM_LSI(val) bfin_write16(PWM_LSI, val)
-#define bfin_read_PWM_STAT2() bfin_read16(PWM_STAT2)
-#define bfin_write_PWM_STAT2(val) bfin_write16(PWM_STAT2, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF512_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_def.h b/arch/blackfin/include/asm/mach-bf518/BF512_def.h
deleted file mode 100644
index bbaf22fa95fe..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF512_def.h
+++ /dev/null
@@ -1,517 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF512_proc__
-#define __BFIN_DEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI1_CTL 0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC03508 /* Status Register */
-#define CNT_COMMAND 0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER 0xFFC03514 /* Counter Register */
-#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */
-#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS 0xFFC03628 /* Secure Status */
-#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PWM_CTRL 0xFFC03700 /* PWM Control Register */
-#define PWM_STAT 0xFFC03704 /* PWM Status Register */
-#define PWM_TM 0xFFC03708 /* PWM Period Register */
-#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */
-#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */
-#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */
-#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM_STAT2 0xFFC03738 /* PWM Status Register */
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF512_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
deleted file mode 100644
index b13246f6ddc8..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF514_proc__
-#define __BFIN_CDEF_ADSP_BF514_proc__
-
-#include "BF512_cdef.h"
-
-#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_def.h b/arch/blackfin/include/asm/mach-bf518/BF514_def.h
deleted file mode 100644
index 708a4f722775..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF514_def.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF514_proc__
-#define __BFIN_DEF_ADSP_BF514_proc__
-
-#include "BF512_def.h"
-
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-
-#endif /* __BFIN_DEF_ADSP_BF514_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
deleted file mode 100644
index 872294472160..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF516_proc__
-#define __BFIN_CDEF_ADSP_BF516_proc__
-
-#include "BF514_cdef.h"
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_def.h b/arch/blackfin/include/asm/mach-bf518/BF516_def.h
deleted file mode 100644
index 8139c9b273bf..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF516_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF516_proc__
-#define __BFIN_DEF_ADSP_BF516_proc__
-
-#include "BF514_def.h"
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF516_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
deleted file mode 100644
index 0e582e10d139..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF518_proc__
-#define __BFIN_CDEF_ADSP_BF518_proc__
-
-#include "BF516_cdef.h"
-
-#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val)
-#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val)
-#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val)
-#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val)
-#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO)
-#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_def.h b/arch/blackfin/include/asm/mach-bf518/BF518_def.h
deleted file mode 100644
index eec70d466623..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/BF518_def.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF518_proc__
-#define __BFIN_DEF_ADSP_BF518_proc__
-
-#include "BF516_def.h"
-
-#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
-
-#endif /* __BFIN_DEF_ADSP_BF518_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h
deleted file mode 100644
index 56383f7cbc07..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/anomaly.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf518/def_local.h b/arch/blackfin/include/asm/mach-bf518/def_local.h
deleted file mode 100644
index 73f67d83880d..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF51x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf518/gpio.h b/arch/blackfin/include/asm/mach-bf518/gpio.h
deleted file mode 100644
index 9af6ce0f6321..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/gpio.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf518/portmux.h b/arch/blackfin/include/asm/mach-bf518/portmux.h
deleted file mode 100644
index cd84a569b04e..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/portmux.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-
-/* PWM */
-#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf518/ports.h b/arch/blackfin/include/asm/mach-bf518/ports.h
deleted file mode 100644
index f1e9cc00d4df..000000000000
--- a/arch/blackfin/include/asm/mach-bf518/ports.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK 0x0003
-#define PORT_x_MUX_1_MASK 0x000C
-#define PORT_x_MUX_2_MASK 0x0030
-#define PORT_x_MUX_3_MASK 0x00C0
-#define PORT_x_MUX_4_MASK 0x0300
-#define PORT_x_MUX_5_MASK 0x0C00
-#define PORT_x_MUX_6_MASK 0x3000
-#define PORT_x_MUX_7_MASK 0xC000
-
-#define PORT_x_MUX_FUNC_1 (0x0)
-#define PORT_x_MUX_FUNC_2 (0x1)
-#define PORT_x_MUX_FUNC_3 (0x2)
-#define PORT_x_MUX_FUNC_4 (0x3)
-#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
deleted file mode 100644
index 49a60afac6d3..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
+++ /dev/null
@@ -1,1012 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF522_proc__
-#define __BFIN_CDEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW)
-#define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
deleted file mode 100644
index 075c6970b51e..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h
+++ /dev/null
@@ -1,513 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF522_proc__
-#define __BFIN_DEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_SLEW 0xFFC03284 /* Non-GPIO Port slew control */
-#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define HOST_CONTROL 0xFFC03400 /* HOST Control Register */
-#define HOST_STATUS 0xFFC03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
-#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC03508 /* Status Register */
-#define CNT_COMMAND 0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER 0xFFC03514 /* Counter Register */
-#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */
-#define OTP_CONTROL 0xFFC03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0360C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS 0xFFC03628 /* Secure Status */
-#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define NFC_CTL 0xFFC03700 /* NAND Control Register */
-#define NFC_STAT 0xFFC03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC0370C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC0371C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03720 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03728 /* NAND Page Control Register */
-#define NFC_READ 0xFFC0372C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03740 /* NAND Address Register */
-#define NFC_CMD 0xFFC03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
deleted file mode 100644
index 593330ebdc56..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF522_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
deleted file mode 100644
index e88a450a9167..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF523_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF522_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
deleted file mode 100644
index 060dce31a2b2..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF524_proc__
-#define __BFIN_CDEF_ADSP_BF524_proc__
-
-#include "BF522_cdef.h"
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
deleted file mode 100644
index f0e77166a7c4..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF524_proc__
-#define __BFIN_DEF_ADSP_BF524_proc__
-
-#include "BF522_def.h"
-
-#define USB_FADDR 0xFFC03800 /* Function address register */
-#define USB_POWER 0xFFC03804 /* Power management register */
-#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03820 /* USB frame number */
-#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
deleted file mode 100644
index 415eb07af080..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF524_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_def.h b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
deleted file mode 100644
index 930cb595c6a3..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF525_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF524_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
deleted file mode 100644
index 515acd3285e7..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF526_proc__
-#define __BFIN_CDEF_ADSP_BF526_proc__
-
-#include "BF524_cdef.h"
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
deleted file mode 100644
index 40b5b01f11cf..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF526_proc__
-#define __BFIN_DEF_ADSP_BF526_proc__
-
-#include "BF524_def.h"
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
deleted file mode 100644
index c5abe62dba16..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF526_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_def.h b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
deleted file mode 100644
index 95416745f6bd..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/BF527_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF526_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h
deleted file mode 100644
index 688470611e15..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h
deleted file mode 100644
index 1ffa2398172e..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/def_local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "gpio.h"
-#include "mem_map.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF52x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf527/gpio.h b/arch/blackfin/include/asm/mach-bf527/gpio.h
deleted file mode 100644
index f80c2995efdb..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf527/mem_map.h b/arch/blackfin/include/asm/mach-bf527/mem_map.h
deleted file mode 100644
index 8386b4b26685..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/mem_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BF52X_MEM_MAP_H__
-#define __BF52X_MEM_MAP_H__
-
-#define L1_DATA_A_SRAM (0xFF800000)
-#define L1_DATA_A_SRAM_SIZE (0x4000)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM (0xFF900000)
-#define L1_DATA_B_SRAM_SIZE (0x4000)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM (0xFFA00000)
-#define L1_INST_SRAM_SIZE (0xC000)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/portmux.h b/arch/blackfin/include/asm/mach-bf527/portmux.h
deleted file mode 100644
index aa165581d8c0..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if !defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#else
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#else
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if !defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#else
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf527/ports.h b/arch/blackfin/include/asm/mach-bf527/ports.h
deleted file mode 100644
index e6b1df87087c..000000000000
--- a/arch/blackfin/include/asm/mach-bf527/ports.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK 0x0003
-#define PORT_x_MUX_1_MASK 0x000C
-#define PORT_x_MUX_2_MASK 0x0030
-#define PORT_x_MUX_3_MASK 0x00C0
-#define PORT_x_MUX_4_MASK 0x0300
-#define PORT_x_MUX_5_MASK 0x0C00
-#define PORT_x_MUX_6_MASK 0x3000
-#define PORT_x_MUX_7_MASK 0xC000
-
-#define PORT_x_MUX_FUNC_1 (0x0)
-#define PORT_x_MUX_FUNC_2 (0x1)
-#define PORT_x_MUX_FUNC_3 (0x2)
-#define PORT_x_MUX_FUNC_4 (0x3)
-#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-#include "../mach-common/bits/ports-j.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
deleted file mode 100644
index 2572bfa90847..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF531_proc__
-#define __BFIN_CDEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
-#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D)
-#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
-#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D)
-#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
-#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
-#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D)
-#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
-#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
-#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
-#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S)
-#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
-#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S)
-#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
-#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
-#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S)
-#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
-#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
-#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
-#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D)
-#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
-#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D)
-#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
-#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
-#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D)
-#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
-#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
-#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
-#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S)
-#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
-#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S)
-#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
-#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
-#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S)
-#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
-#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
-#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG)
-#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT)
-#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY)
-#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT)
-#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY)
-#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT)
-#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP)
-#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val)
-#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT)
-#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT)
-#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG)
-#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT)
-#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY)
-#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT)
-#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY)
-#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT)
-#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP)
-#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val)
-#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT)
-#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT)
-#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG)
-#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT)
-#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY)
-#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT)
-#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY)
-#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT)
-#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP)
-#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val)
-#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT)
-#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT)
-#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG)
-#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT)
-#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY)
-#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT)
-#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY)
-#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT)
-#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP)
-#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val)
-#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT)
-#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT)
-#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG)
-#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT)
-#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY)
-#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT)
-#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY)
-#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT)
-#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP)
-#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val)
-#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT)
-#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT)
-#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG)
-#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT)
-#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY)
-#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT)
-#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY)
-#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT)
-#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP)
-#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val)
-#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT)
-#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT)
-#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG)
-#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT)
-#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY)
-#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT)
-#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY)
-#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT)
-#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP)
-#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val)
-#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT)
-#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT)
-#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG)
-#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT)
-#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY)
-#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT)
-#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY)
-#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT)
-#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP)
-#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val)
-#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT)
-#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT)
-#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
-#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0)
-#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1)
-#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0)
-#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1)
-#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX)
-#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val)
-#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX)
-#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val)
-#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV)
-#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val)
-#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV)
-#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val)
-#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV)
-#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val)
-#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV)
-#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val)
-#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT)
-#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val)
-#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0)
-#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val)
-#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1)
-#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val)
-#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2)
-#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val)
-#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3)
-#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val)
-#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0)
-#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val)
-#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1)
-#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val)
-#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2)
-#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val)
-#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3)
-#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val)
-#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1)
-#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val)
-#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2)
-#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val)
-#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL)
-#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val)
-#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0)
-#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1)
-#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0)
-#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1)
-#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX)
-#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val)
-#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX)
-#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val)
-#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV)
-#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val)
-#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV)
-#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val)
-#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV)
-#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val)
-#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV)
-#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val)
-#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT)
-#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val)
-#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0)
-#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val)
-#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1)
-#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val)
-#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2)
-#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val)
-#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3)
-#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val)
-#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0)
-#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val)
-#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1)
-#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val)
-#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2)
-#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val)
-#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3)
-#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val)
-#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1)
-#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val)
-#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2)
-#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val)
-#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL)
-#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val)
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h
deleted file mode 100644
index 2bcd2d88dc3d..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF531_proc__
-#define __BFIN_DEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define MDMAFLX0_DMACNFG_D 0xFFC00E08
-#define MDMAFLX0_XCOUNT_D 0xFFC00E10
-#define MDMAFLX0_XMODIFY_D 0xFFC00E14
-#define MDMAFLX0_YCOUNT_D 0xFFC00E18
-#define MDMAFLX0_YMODIFY_D 0xFFC00E1C
-#define MDMAFLX0_IRQSTAT_D 0xFFC00E28
-#define MDMAFLX0_PMAP_D 0xFFC00E2C
-#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30
-#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38
-#define MDMAFLX0_DMACNFG_S 0xFFC00E48
-#define MDMAFLX0_XCOUNT_S 0xFFC00E50
-#define MDMAFLX0_XMODIFY_S 0xFFC00E54
-#define MDMAFLX0_YCOUNT_S 0xFFC00E58
-#define MDMAFLX0_YMODIFY_S 0xFFC00E5C
-#define MDMAFLX0_IRQSTAT_S 0xFFC00E68
-#define MDMAFLX0_PMAP_S 0xFFC00E6C
-#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70
-#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78
-#define MDMAFLX1_DMACNFG_D 0xFFC00E88
-#define MDMAFLX1_XCOUNT_D 0xFFC00E90
-#define MDMAFLX1_XMODIFY_D 0xFFC00E94
-#define MDMAFLX1_YCOUNT_D 0xFFC00E98
-#define MDMAFLX1_YMODIFY_D 0xFFC00E9C
-#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8
-#define MDMAFLX1_PMAP_D 0xFFC00EAC
-#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0
-#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8
-#define MDMAFLX1_DMACNFG_S 0xFFC00EC8
-#define MDMAFLX1_XCOUNT_S 0xFFC00ED0
-#define MDMAFLX1_XMODIFY_S 0xFFC00ED4
-#define MDMAFLX1_YCOUNT_S 0xFFC00ED8
-#define MDMAFLX1_YMODIFY_S 0xFFC00EDC
-#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8
-#define MDMAFLX1_PMAP_S 0xFFC00EEC
-#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0
-#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8
-#define DMAFLX0_DMACNFG 0xFFC00C08
-#define DMAFLX0_XCOUNT 0xFFC00C10
-#define DMAFLX0_XMODIFY 0xFFC00C14
-#define DMAFLX0_YCOUNT 0xFFC00C18
-#define DMAFLX0_YMODIFY 0xFFC00C1C
-#define DMAFLX0_IRQSTAT 0xFFC00C28
-#define DMAFLX0_PMAP 0xFFC00C2C
-#define DMAFLX0_CURXCOUNT 0xFFC00C30
-#define DMAFLX0_CURYCOUNT 0xFFC00C38
-#define DMAFLX1_DMACNFG 0xFFC00C48
-#define DMAFLX1_XCOUNT 0xFFC00C50
-#define DMAFLX1_XMODIFY 0xFFC00C54
-#define DMAFLX1_YCOUNT 0xFFC00C58
-#define DMAFLX1_YMODIFY 0xFFC00C5C
-#define DMAFLX1_IRQSTAT 0xFFC00C68
-#define DMAFLX1_PMAP 0xFFC00C6C
-#define DMAFLX1_CURXCOUNT 0xFFC00C70
-#define DMAFLX1_CURYCOUNT 0xFFC00C78
-#define DMAFLX2_DMACNFG 0xFFC00C88
-#define DMAFLX2_XCOUNT 0xFFC00C90
-#define DMAFLX2_XMODIFY 0xFFC00C94
-#define DMAFLX2_YCOUNT 0xFFC00C98
-#define DMAFLX2_YMODIFY 0xFFC00C9C
-#define DMAFLX2_IRQSTAT 0xFFC00CA8
-#define DMAFLX2_PMAP 0xFFC00CAC
-#define DMAFLX2_CURXCOUNT 0xFFC00CB0
-#define DMAFLX2_CURYCOUNT 0xFFC00CB8
-#define DMAFLX3_DMACNFG 0xFFC00CC8
-#define DMAFLX3_XCOUNT 0xFFC00CD0
-#define DMAFLX3_XMODIFY 0xFFC00CD4
-#define DMAFLX3_YCOUNT 0xFFC00CD8
-#define DMAFLX3_YMODIFY 0xFFC00CDC
-#define DMAFLX3_IRQSTAT 0xFFC00CE8
-#define DMAFLX3_PMAP 0xFFC00CEC
-#define DMAFLX3_CURXCOUNT 0xFFC00CF0
-#define DMAFLX3_CURYCOUNT 0xFFC00CF8
-#define DMAFLX4_DMACNFG 0xFFC00D08
-#define DMAFLX4_XCOUNT 0xFFC00D10
-#define DMAFLX4_XMODIFY 0xFFC00D14
-#define DMAFLX4_YCOUNT 0xFFC00D18
-#define DMAFLX4_YMODIFY 0xFFC00D1C
-#define DMAFLX4_IRQSTAT 0xFFC00D28
-#define DMAFLX4_PMAP 0xFFC00D2C
-#define DMAFLX4_CURXCOUNT 0xFFC00D30
-#define DMAFLX4_CURYCOUNT 0xFFC00D38
-#define DMAFLX5_DMACNFG 0xFFC00D48
-#define DMAFLX5_XCOUNT 0xFFC00D50
-#define DMAFLX5_XMODIFY 0xFFC00D54
-#define DMAFLX5_YCOUNT 0xFFC00D58
-#define DMAFLX5_YMODIFY 0xFFC00D5C
-#define DMAFLX5_IRQSTAT 0xFFC00D68
-#define DMAFLX5_PMAP 0xFFC00D6C
-#define DMAFLX5_CURXCOUNT 0xFFC00D70
-#define DMAFLX5_CURYCOUNT 0xFFC00D78
-#define DMAFLX6_DMACNFG 0xFFC00D88
-#define DMAFLX6_XCOUNT 0xFFC00D90
-#define DMAFLX6_XMODIFY 0xFFC00D94
-#define DMAFLX6_YCOUNT 0xFFC00D98
-#define DMAFLX6_YMODIFY 0xFFC00D9C
-#define DMAFLX6_IRQSTAT 0xFFC00DA8
-#define DMAFLX6_PMAP 0xFFC00DAC
-#define DMAFLX6_CURXCOUNT 0xFFC00DB0
-#define DMAFLX6_CURYCOUNT 0xFFC00DB8
-#define DMAFLX7_DMACNFG 0xFFC00DC8
-#define DMAFLX7_XCOUNT 0xFFC00DD0
-#define DMAFLX7_XMODIFY 0xFFC00DD4
-#define DMAFLX7_YCOUNT 0xFFC00DD8
-#define DMAFLX7_YMODIFY 0xFFC00DDC
-#define DMAFLX7_IRQSTAT 0xFFC00DE8
-#define DMAFLX7_PMAP 0xFFC00DEC
-#define DMAFLX7_CURXCOUNT 0xFFC00DF0
-#define DMAFLX7_CURYCOUNT 0xFFC00DF8
-#define TIMER0_CONFIG 0xFFC00600
-#define TIMER0_COUNTER 0xFFC00604
-#define TIMER0_PERIOD 0xFFC00608
-#define TIMER0_WIDTH 0xFFC0060C
-#define TIMER1_CONFIG 0xFFC00610
-#define TIMER1_COUNTER 0xFFC00614
-#define TIMER1_PERIOD 0xFFC00618
-#define TIMER1_WIDTH 0xFFC0061C
-#define TIMER2_CONFIG 0xFFC00620
-#define TIMER2_COUNTER 0xFFC00624
-#define TIMER2_PERIOD 0xFFC00628
-#define TIMER2_WIDTH 0xFFC0062C
-#define TIMER_ENABLE 0xFFC00640
-#define TIMER_DISABLE 0xFFC00644
-#define TIMER_STATUS 0xFFC00648
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-#define UART_THR 0xFFC00400 /* Transmit Holding */
-#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART_IER 0xFFC00404
-#define UART_IIR 0xFFC00408
-#define UART_LCR 0xFFC0040C
-#define UART_MCR 0xFFC00410
-#define UART_LSR 0xFFC00414
-#define UART_SCR 0xFFC0041C
-#define UART_RBR 0xFFC00400 /* Receive Buffer */
-#define UART0_RBR UART_RBR
-#define UART_GCTL 0xFFC00424
-#define SPT0_TX_CONFIG0 0xFFC00800
-#define SPT0_TX_CONFIG1 0xFFC00804
-#define SPT0_RX_CONFIG0 0xFFC00820
-#define SPT0_RX_CONFIG1 0xFFC00824
-#define SPT0_TX 0xFFC00810
-#define SPT0_RX 0xFFC00818
-#define SPT0_TSCLKDIV 0xFFC00808
-#define SPT0_RSCLKDIV 0xFFC00828
-#define SPT0_TFSDIV 0xFFC0080C
-#define SPT0_RFSDIV 0xFFC0082C
-#define SPT0_STAT 0xFFC00830
-#define SPT0_MTCS0 0xFFC00840
-#define SPT0_MTCS1 0xFFC00844
-#define SPT0_MTCS2 0xFFC00848
-#define SPT0_MTCS3 0xFFC0084C
-#define SPT0_MRCS0 0xFFC00850
-#define SPT0_MRCS1 0xFFC00854
-#define SPT0_MRCS2 0xFFC00858
-#define SPT0_MRCS3 0xFFC0085C
-#define SPT0_MCMC1 0xFFC00838
-#define SPT0_MCMC2 0xFFC0083C
-#define SPT0_CHNL 0xFFC00834
-#define SPT1_TX_CONFIG0 0xFFC00900
-#define SPT1_TX_CONFIG1 0xFFC00904
-#define SPT1_RX_CONFIG0 0xFFC00920
-#define SPT1_RX_CONFIG1 0xFFC00924
-#define SPT1_TX 0xFFC00910
-#define SPT1_RX 0xFFC00918
-#define SPT1_TSCLKDIV 0xFFC00908
-#define SPT1_RSCLKDIV 0xFFC00928
-#define SPT1_TFSDIV 0xFFC0090C
-#define SPT1_RFSDIV 0xFFC0092C
-#define SPT1_STAT 0xFFC00930
-#define SPT1_MTCS0 0xFFC00940
-#define SPT1_MTCS1 0xFFC00944
-#define SPT1_MTCS2 0xFFC00948
-#define SPT1_MTCS3 0xFFC0094C
-#define SPT1_MRCS0 0xFFC00950
-#define SPT1_MRCS1 0xFFC00954
-#define SPT1_MRCS2 0xFFC00958
-#define SPT1_MRCS3 0xFFC0095C
-#define SPT1_MCMC1 0xFFC00938
-#define SPT1_MCMC2 0xFFC0093C
-#define SPT1_CHNL 0xFFC00934
-#define PPI_CONTROL 0xFFC01000
-#define PPI_STATUS 0xFFC01004
-#define PPI_DELAY 0xFFC0100C
-#define PPI_COUNT 0xFFC01008
-#define PPI_FRAME 0xFFC01010
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define CHIPID 0xFFC00014
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300
-#define RTC_ICTL 0xFFC00304
-#define RTC_ISTAT 0xFFC00308
-#define RTC_SWCNT 0xFFC0030C
-#define RTC_ALARM 0xFFC00310
-#define RTC_PREN 0xFFC00314
-#define SPI_CTL 0xFFC00500
-#define SPI_FLG 0xFFC00504
-#define SPI_STAT 0xFFC00508
-#define SPI_TDBR 0xFFC0050C
-#define SPI_RDBR 0xFFC00510
-#define SPI_BAUD 0xFFC00514
-#define SPI_SHADOW 0xFFC00518
-#define FIO_FLAG_D 0xFFC00700
-#define FIO_FLAG_C 0xFFC00704
-#define FIO_FLAG_S 0xFFC00708
-#define FIO_FLAG_T 0xFFC0070C
-#define FIO_MASKA_D 0xFFC00710
-#define FIO_MASKA_C 0xFFC00714
-#define FIO_MASKA_S 0xFFC00718
-#define FIO_MASKA_T 0xFFC0071C
-#define FIO_MASKB_D 0xFFC00720
-#define FIO_MASKB_C 0xFFC00724
-#define FIO_MASKB_S 0xFFC00728
-#define FIO_MASKB_T 0xFFC0072C
-#define FIO_DIR 0xFFC00730
-#define FIO_POLAR 0xFFC00734
-#define FIO_EDGE 0xFFC00738
-#define FIO_BOTH 0xFFC0073C
-#define FIO_INEN 0xFFC00740
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00
-#define DMA0_START_ADDR 0xFFC00C04
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10
-#define DMA0_X_MODIFY 0xFFC00C14
-#define DMA0_Y_COUNT 0xFFC00C18
-#define DMA0_Y_MODIFY 0xFFC00C1C
-#define DMA0_CURR_DESC_PTR 0xFFC00C20
-#define DMA0_CURR_ADDR 0xFFC00C24
-#define DMA0_IRQ_STATUS 0xFFC00C28
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
-#define DMA0_CURR_X_COUNT 0xFFC00C30
-#define DMA0_CURR_Y_COUNT 0xFFC00C38
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40
-#define DMA1_START_ADDR 0xFFC00C44
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50
-#define DMA1_X_MODIFY 0xFFC00C54
-#define DMA1_Y_COUNT 0xFFC00C58
-#define DMA1_Y_MODIFY 0xFFC00C5C
-#define DMA1_CURR_DESC_PTR 0xFFC00C60
-#define DMA1_CURR_ADDR 0xFFC00C64
-#define DMA1_IRQ_STATUS 0xFFC00C68
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
-#define DMA1_CURR_X_COUNT 0xFFC00C70
-#define DMA1_CURR_Y_COUNT 0xFFC00C78
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80
-#define DMA2_START_ADDR 0xFFC00C84
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90
-#define DMA2_X_MODIFY 0xFFC00C94
-#define DMA2_Y_COUNT 0xFFC00C98
-#define DMA2_Y_MODIFY 0xFFC00C9C
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0
-#define DMA2_CURR_ADDR 0xFFC00CA4
-#define DMA2_IRQ_STATUS 0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
-#define DMA2_CURR_X_COUNT 0xFFC00CB0
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
-#define DMA3_START_ADDR 0xFFC00CC4
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0
-#define DMA3_X_MODIFY 0xFFC00CD4
-#define DMA3_Y_COUNT 0xFFC00CD8
-#define DMA3_Y_MODIFY 0xFFC00CDC
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0
-#define DMA3_CURR_ADDR 0xFFC00CE4
-#define DMA3_IRQ_STATUS 0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
-#define DMA3_CURR_X_COUNT 0xFFC00CF0
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00
-#define DMA4_START_ADDR 0xFFC00D04
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10
-#define DMA4_X_MODIFY 0xFFC00D14
-#define DMA4_Y_COUNT 0xFFC00D18
-#define DMA4_Y_MODIFY 0xFFC00D1C
-#define DMA4_CURR_DESC_PTR 0xFFC00D20
-#define DMA4_CURR_ADDR 0xFFC00D24
-#define DMA4_IRQ_STATUS 0xFFC00D28
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
-#define DMA4_CURR_X_COUNT 0xFFC00D30
-#define DMA4_CURR_Y_COUNT 0xFFC00D38
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40
-#define DMA5_START_ADDR 0xFFC00D44
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50
-#define DMA5_X_MODIFY 0xFFC00D54
-#define DMA5_Y_COUNT 0xFFC00D58
-#define DMA5_Y_MODIFY 0xFFC00D5C
-#define DMA5_CURR_DESC_PTR 0xFFC00D60
-#define DMA5_CURR_ADDR 0xFFC00D64
-#define DMA5_IRQ_STATUS 0xFFC00D68
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
-#define DMA5_CURR_X_COUNT 0xFFC00D70
-#define DMA5_CURR_Y_COUNT 0xFFC00D78
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80
-#define DMA6_START_ADDR 0xFFC00D84
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90
-#define DMA6_X_MODIFY 0xFFC00D94
-#define DMA6_Y_COUNT 0xFFC00D98
-#define DMA6_Y_MODIFY 0xFFC00D9C
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0
-#define DMA6_CURR_ADDR 0xFFC00DA4
-#define DMA6_IRQ_STATUS 0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
-#define DMA6_CURR_X_COUNT 0xFFC00DB0
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
-#define DMA7_START_ADDR 0xFFC00DC4
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0
-#define DMA7_X_MODIFY 0xFFC00DD4
-#define DMA7_Y_COUNT 0xFFC00DD8
-#define DMA7_Y_MODIFY 0xFFC00DDC
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0
-#define DMA7_CURR_ADDR 0xFFC00DE4
-#define DMA7_IRQ_STATUS 0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
-#define DMA7_CURR_X_COUNT 0xFFC00DF0
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00
-#define MDMA_D0_START_ADDR 0xFFC00E04
-#define MDMA_D0_CONFIG 0xFFC00E08
-#define MDMA_D0_X_COUNT 0xFFC00E10
-#define MDMA_D0_X_MODIFY 0xFFC00E14
-#define MDMA_D0_Y_COUNT 0xFFC00E18
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20
-#define MDMA_D0_CURR_ADDR 0xFFC00E24
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40
-#define MDMA_S0_START_ADDR 0xFFC00E44
-#define MDMA_S0_CONFIG 0xFFC00E48
-#define MDMA_S0_X_COUNT 0xFFC00E50
-#define MDMA_S0_X_MODIFY 0xFFC00E54
-#define MDMA_S0_Y_COUNT 0xFFC00E58
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60
-#define MDMA_S0_CURR_ADDR 0xFFC00E64
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80
-#define MDMA_D1_START_ADDR 0xFFC00E84
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90
-#define MDMA_D1_X_MODIFY 0xFFC00E94
-#define MDMA_D1_Y_COUNT 0xFFC00E98
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0
-#define MDMA_S1_START_ADDR 0xFFC00EC4
-#define MDMA_S1_CONFIG 0xFFC00EC8
-#define MDMA_S1_X_COUNT 0xFFC00ED0
-#define MDMA_S1_X_MODIFY 0xFFC00ED4
-#define MDMA_S1_Y_COUNT 0xFFC00ED8
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8
-#define EBIU_AMGCTL 0xFFC00A00
-#define EBIU_AMBCTL0 0xFFC00A04
-#define EBIU_AMBCTL1 0xFFC00A08
-#define EBIU_SDGCTL 0xFFC00A10
-#define EBIU_SDBCTL 0xFFC00A14
-#define EBIU_SDRRC 0xFFC00A18
-#define EBIU_SDSTAT 0xFFC00A1C
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
deleted file mode 100644
index 09f25211d86c..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF531_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h
deleted file mode 100644
index 64f55f50c78d..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF532_proc__
-#define __BFIN_DEF_ADSP_BF532_proc__
-
-#include "BF531_def.h"
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF532_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
deleted file mode 100644
index 304432706995..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF532_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h
deleted file mode 100644
index 3c0595f50b10..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define __BFIN_DEF_ADSP_BF533_proc__
-
-#include "BF532_def.h"
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF533_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h
deleted file mode 100644
index 03f2b40912a3..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/anomaly.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated@the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event@Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set@Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h
deleted file mode 100644
index c545b545136b..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF533_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf533/gpio.h b/arch/blackfin/include/asm/mach-bf533/gpio.h
deleted file mode 100644
index e02416db4b00..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/gpio.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-
-#define PORT_F GPIO_PF0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/portmux.h b/arch/blackfin/include/asm/mach-bf533/portmux.h
deleted file mode 100644
index 96f5d9129f20..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/portmux.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf533/ports.h b/arch/blackfin/include/asm/mach-bf533/ports.h
deleted file mode 100644
index 512d6df0256f..000000000000
--- a/arch/blackfin/include/asm/mach-bf533/ports.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-f.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
deleted file mode 100644
index 3d9412d181e6..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
+++ /dev/null
@@ -1,1624 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF534_proc__
-#define __BFIN_CDEF_ADSP_BF534_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h
deleted file mode 100644
index cb6a543d56fd..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF534_def.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF534_proc__
-#define __BFIN_DEF_ADSP_BF534_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Config register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define CHIPID 0xFFC00014
-#define DMA_TC_CNT 0xFFC00B0C
-#define DMA_TC_PER 0xFFC00B10
-
-#if !defined(__ADSPBF536__)
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#endif
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
deleted file mode 100644
index ccf57c8236c2..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF536_proc__
-#define __BFIN_CDEF_ADSP_BF536_proc__
-
-#include "BF534_cdef.h"
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_def.h b/arch/blackfin/include/asm/mach-bf537/BF536_def.h
deleted file mode 100644
index 9d8d00a41275..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF536_def.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF536_proc__
-#define __BFIN_DEF_ADSP_BF536_proc__
-
-#include "BF534_def.h"
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
deleted file mode 100644
index 958363bfcb71..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF536_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_def.h b/arch/blackfin/include/asm/mach-bf537/BF537_def.h
deleted file mode 100644
index 383d7a770b67..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/BF537_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF536_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h
deleted file mode 100644
index 543cd3fb305e..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/anomaly.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode@10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h
deleted file mode 100644
index e210db980d01..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF537_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf537/gpio.h b/arch/blackfin/include/asm/mach-bf537/gpio.h
deleted file mode 100644
index f80c2995efdb..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/portmux.h b/arch/blackfin/include/asm/mach-bf537/portmux.h
deleted file mode 100644
index 71d9eaeb579e..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/portmux.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
-
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0 (GPIO_PH15 + 1)
-#define PORT_PJ1 (GPIO_PH15 + 2)
-#define PORT_PJ2 (GPIO_PH15 + 3)
-#define PORT_PJ3 (GPIO_PH15 + 4)
-#define PORT_PJ4 (GPIO_PH15 + 5)
-#define PORT_PJ5 (GPIO_PH15 + 6)
-#define PORT_PJ6 (GPIO_PH15 + 7)
-#define PORT_PJ7 (GPIO_PH15 + 8)
-#define PORT_PJ8 (GPIO_PH15 + 9)
-#define PORT_PJ9 (GPIO_PH15 + 10)
-#define PORT_PJ10 (GPIO_PH15 + 11)
-#define PORT_PJ11 (GPIO_PH15 + 12)
-
-#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf537/ports.h b/arch/blackfin/include/asm/mach-bf537/ports.h
deleted file mode 100644
index 2f6293409f5a..000000000000
--- a/arch/blackfin/include/asm/mach-bf537/ports.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORT_MUX Masks */
-#define PJSE 0x0001
-#define PJCE_MASK 0x0006
-#define PJCE_SPORT 0x0000
-#define PJCE_CAN 0x0001
-#define PJCE_SPI 0x0002
-#define PFDE 0x0008
-#define PFTE 0x0010
-#define PFS6E 0x0020
-#define PFS5E 0x0040
-#define PFS4E 0x0080
-#define PFFE 0x0100
-#define PGSE 0x0200
-#define PGRE 0x0400
-#define PGTE 0x0800
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h
deleted file mode 100644
index 42acdcc4f04e..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h
+++ /dev/null
@@ -1,2014 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF538_proc__
-#define __BFIN_CDEF_ADSP_BF538_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER)
-#define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val)
-#define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT)
-#define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
-#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
-#define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG)
-#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
-#define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT)
-#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
-#define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY)
-#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
-#define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT)
-#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY)
-#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
-#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
-#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
-#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
-#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
-#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
-#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
-#define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG)
-#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
-#define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT)
-#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
-#define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY)
-#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
-#define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT)
-#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY)
-#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
-#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
-#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
-#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
-#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
-#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
-#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
-#define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG)
-#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
-#define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT)
-#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
-#define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY)
-#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
-#define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT)
-#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY)
-#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
-#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
-#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
-#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
-#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
-#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
-#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
-#define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG)
-#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
-#define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT)
-#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
-#define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY)
-#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
-#define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT)
-#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY)
-#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
-#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
-#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
-#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
-#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
-#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF538_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_def.h b/arch/blackfin/include/asm/mach-bf538/BF538_def.h
deleted file mode 100644
index 1736dabf09cb..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/BF538_def.h
+++ /dev/null
@@ -1,1025 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF538_proc__
-#define __BFIN_DEF_ADSP_BF538_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT 0xFFC00300
-#define RTC_ICTL 0xFFC00304
-#define RTC_ISTAT 0xFFC00308
-#define RTC_SWCNT 0xFFC0030C
-#define RTC_ALARM 0xFFC00310
-#define RTC_PREN 0xFFC00314
-#define UART0_THR 0xFFC00400
-#define UART0_RBR 0xFFC00400
-#define UART0_DLL 0xFFC00400
-#define UART0_DLH 0xFFC00404
-#define UART0_IER 0xFFC00404
-#define UART0_IIR 0xFFC00408
-#define UART0_LCR 0xFFC0040C
-#define UART0_MCR 0xFFC00410
-#define UART0_LSR 0xFFC00414
-#define UART0_SCR 0xFFC0041C
-#define UART0_GCTL 0xFFC00424
-#define UART1_THR 0xFFC02000
-#define UART1_RBR 0xFFC02000
-#define UART1_DLL 0xFFC02000
-#define UART1_DLH 0xFFC02004
-#define UART1_IER 0xFFC02004
-#define UART1_IIR 0xFFC02008
-#define UART1_LCR 0xFFC0200C
-#define UART1_MCR 0xFFC02010
-#define UART1_LSR 0xFFC02014
-#define UART1_SCR 0xFFC0201C
-#define UART1_GCTL 0xFFC02024
-#define UART2_THR 0xFFC02100
-#define UART2_RBR 0xFFC02100
-#define UART2_DLL 0xFFC02100
-#define UART2_DLH 0xFFC02104
-#define UART2_IER 0xFFC02104
-#define UART2_IIR 0xFFC02108
-#define UART2_LCR 0xFFC0210C
-#define UART2_MCR 0xFFC02110
-#define UART2_LSR 0xFFC02114
-#define UART2_SCR 0xFFC0211C
-#define UART2_GCTL 0xFFC02124
-#define SPI0_CTL 0xFFC00500
-#define SPI0_FLG 0xFFC00504
-#define SPI0_STAT 0xFFC00508
-#define SPI0_TDBR 0xFFC0050C
-#define SPI0_RDBR 0xFFC00510
-#define SPI0_BAUD 0xFFC00514
-#define SPI0_SHADOW 0xFFC00518
-#define SPI1_CTL 0xFFC02300
-#define SPI1_FLG 0xFFC02304
-#define SPI1_STAT 0xFFC02308
-#define SPI1_TDBR 0xFFC0230C
-#define SPI1_RDBR 0xFFC02310
-#define SPI1_BAUD 0xFFC02314
-#define SPI1_SHADOW 0xFFC02318
-#define SPI2_CTL 0xFFC02400
-#define SPI2_FLG 0xFFC02404
-#define SPI2_STAT 0xFFC02408
-#define SPI2_TDBR 0xFFC0240C
-#define SPI2_RDBR 0xFFC02410
-#define SPI2_BAUD 0xFFC02414
-#define SPI2_SHADOW 0xFFC02418
-#define TIMER0_CONFIG 0xFFC00600
-#define TIMER0_COUNTER 0xFFC00604
-#define TIMER0_PERIOD 0xFFC00608
-#define TIMER0_WIDTH 0xFFC0060C
-#define TIMER1_CONFIG 0xFFC00610
-#define TIMER1_COUNTER 0xFFC00614
-#define TIMER1_PERIOD 0xFFC00618
-#define TIMER1_WIDTH 0xFFC0061C
-#define TIMER2_CONFIG 0xFFC00620
-#define TIMER2_COUNTER 0xFFC00624
-#define TIMER2_PERIOD 0xFFC00628
-#define TIMER2_WIDTH 0xFFC0062C
-#define TIMER_ENABLE 0xFFC00640
-#define TIMER_DISABLE 0xFFC00644
-#define TIMER_STATUS 0xFFC00648
-#define SPORT0_TCR1 0xFFC00800
-#define SPORT0_TCR2 0xFFC00804
-#define SPORT0_TCLKDIV 0xFFC00808
-#define SPORT0_TFSDIV 0xFFC0080C
-#define SPORT0_TX 0xFFC00810
-#define SPORT0_RX 0xFFC00818
-#define SPORT0_RCR1 0xFFC00820
-#define SPORT0_RCR2 0xFFC00824
-#define SPORT0_RCLKDIV 0xFFC00828
-#define SPORT0_RFSDIV 0xFFC0082C
-#define SPORT0_STAT 0xFFC00830
-#define SPORT0_CHNL 0xFFC00834
-#define SPORT0_MCMC1 0xFFC00838
-#define SPORT0_MCMC2 0xFFC0083C
-#define SPORT0_MTCS0 0xFFC00840
-#define SPORT0_MTCS1 0xFFC00844
-#define SPORT0_MTCS2 0xFFC00848
-#define SPORT0_MTCS3 0xFFC0084C
-#define SPORT0_MRCS0 0xFFC00850
-#define SPORT0_MRCS1 0xFFC00854
-#define SPORT0_MRCS2 0xFFC00858
-#define SPORT0_MRCS3 0xFFC0085C
-#define SPORT1_TCR1 0xFFC00900
-#define SPORT1_TCR2 0xFFC00904
-#define SPORT1_TCLKDIV 0xFFC00908
-#define SPORT1_TFSDIV 0xFFC0090C
-#define SPORT1_TX 0xFFC00910
-#define SPORT1_RX 0xFFC00918
-#define SPORT1_RCR1 0xFFC00920
-#define SPORT1_RCR2 0xFFC00924
-#define SPORT1_RCLKDIV 0xFFC00928
-#define SPORT1_RFSDIV 0xFFC0092C
-#define SPORT1_STAT 0xFFC00930
-#define SPORT1_CHNL 0xFFC00934
-#define SPORT1_MCMC1 0xFFC00938
-#define SPORT1_MCMC2 0xFFC0093C
-#define SPORT1_MTCS0 0xFFC00940
-#define SPORT1_MTCS1 0xFFC00944
-#define SPORT1_MTCS2 0xFFC00948
-#define SPORT1_MTCS3 0xFFC0094C
-#define SPORT1_MRCS0 0xFFC00950
-#define SPORT1_MRCS1 0xFFC00954
-#define SPORT1_MRCS2 0xFFC00958
-#define SPORT1_MRCS3 0xFFC0095C
-#define SPORT2_TCR1 0xFFC02500
-#define SPORT2_TCR2 0xFFC02504
-#define SPORT2_TCLKDIV 0xFFC02508
-#define SPORT2_TFSDIV 0xFFC0250C
-#define SPORT2_TX 0xFFC02510
-#define SPORT2_RX 0xFFC02518
-#define SPORT2_RCR1 0xFFC02520
-#define SPORT2_RCR2 0xFFC02524
-#define SPORT2_RCLKDIV 0xFFC02528
-#define SPORT2_RFSDIV 0xFFC0252C
-#define SPORT2_STAT 0xFFC02530
-#define SPORT2_CHNL 0xFFC02534
-#define SPORT2_MCMC1 0xFFC02538
-#define SPORT2_MCMC2 0xFFC0253C
-#define SPORT2_MTCS0 0xFFC02540
-#define SPORT2_MTCS1 0xFFC02544
-#define SPORT2_MTCS2 0xFFC02548
-#define SPORT2_MTCS3 0xFFC0254C
-#define SPORT2_MRCS0 0xFFC02550
-#define SPORT2_MRCS1 0xFFC02554
-#define SPORT2_MRCS2 0xFFC02558
-#define SPORT2_MRCS3 0xFFC0255C
-#define SPORT3_TCR1 0xFFC02600
-#define SPORT3_TCR2 0xFFC02604
-#define SPORT3_TCLKDIV 0xFFC02608
-#define SPORT3_TFSDIV 0xFFC0260C
-#define SPORT3_TX 0xFFC02610
-#define SPORT3_RX 0xFFC02618
-#define SPORT3_RCR1 0xFFC02620
-#define SPORT3_RCR2 0xFFC02624
-#define SPORT3_RCLKDIV 0xFFC02628
-#define SPORT3_RFSDIV 0xFFC0262C
-#define SPORT3_STAT 0xFFC02630
-#define SPORT3_CHNL 0xFFC02634
-#define SPORT3_MCMC1 0xFFC02638
-#define SPORT3_MCMC2 0xFFC0263C
-#define SPORT3_MTCS0 0xFFC02640
-#define SPORT3_MTCS1 0xFFC02644
-#define SPORT3_MTCS2 0xFFC02648
-#define SPORT3_MTCS3 0xFFC0264C
-#define SPORT3_MRCS0 0xFFC02650
-#define SPORT3_MRCS1 0xFFC02654
-#define SPORT3_MRCS2 0xFFC02658
-#define SPORT3_MRCS3 0xFFC0265C
-#define PORTFIO 0xFFC00700
-#define PORTFIO_CLEAR 0xFFC00704
-#define PORTFIO_SET 0xFFC00708
-#define PORTFIO_TOGGLE 0xFFC0070C
-#define PORTFIO_MASKA 0xFFC00710
-#define PORTFIO_MASKA_CLEAR 0xFFC00714
-#define PORTFIO_MASKA_SET 0xFFC00718
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C
-#define PORTFIO_MASKB 0xFFC00720
-#define PORTFIO_MASKB_CLEAR 0xFFC00724
-#define PORTFIO_MASKB_SET 0xFFC00728
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C
-#define PORTFIO_DIR 0xFFC00730
-#define PORTFIO_POLAR 0xFFC00734
-#define PORTFIO_EDGE 0xFFC00738
-#define PORTFIO_BOTH 0xFFC0073C
-#define PORTFIO_INEN 0xFFC00740
-#define PORTCIO_FER 0xFFC01500
-#define PORTCIO 0xFFC01510
-#define PORTCIO_CLEAR 0xFFC01520
-#define PORTCIO_SET 0xFFC01530
-#define PORTCIO_TOGGLE 0xFFC01540
-#define PORTCIO_DIR 0xFFC01550
-#define PORTCIO_INEN 0xFFC01560
-#define PORTDIO_FER 0xFFC01504
-#define PORTDIO 0xFFC01514
-#define PORTDIO_CLEAR 0xFFC01524
-#define PORTDIO_SET 0xFFC01534
-#define PORTDIO_TOGGLE 0xFFC01544
-#define PORTDIO_DIR 0xFFC01554
-#define PORTDIO_INEN 0xFFC01564
-#define PORTEIO_FER 0xFFC01508
-#define PORTEIO 0xFFC01518
-#define PORTEIO_CLEAR 0xFFC01528
-#define PORTEIO_SET 0xFFC01538
-#define PORTEIO_TOGGLE 0xFFC01548
-#define PORTEIO_DIR 0xFFC01558
-#define PORTEIO_INEN 0xFFC01568
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_TC_PER 0xFFC00B0C /* Traffic Control Periods */
-#define DMA0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00
-#define DMA0_START_ADDR 0xFFC00C04
-#define DMA0_CONFIG 0xFFC00C08
-#define DMA0_X_COUNT 0xFFC00C10
-#define DMA0_X_MODIFY 0xFFC00C14
-#define DMA0_Y_COUNT 0xFFC00C18
-#define DMA0_Y_MODIFY 0xFFC00C1C
-#define DMA0_CURR_DESC_PTR 0xFFC00C20
-#define DMA0_CURR_ADDR 0xFFC00C24
-#define DMA0_IRQ_STATUS 0xFFC00C28
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C
-#define DMA0_CURR_X_COUNT 0xFFC00C30
-#define DMA0_CURR_Y_COUNT 0xFFC00C38
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40
-#define DMA1_START_ADDR 0xFFC00C44
-#define DMA1_CONFIG 0xFFC00C48
-#define DMA1_X_COUNT 0xFFC00C50
-#define DMA1_X_MODIFY 0xFFC00C54
-#define DMA1_Y_COUNT 0xFFC00C58
-#define DMA1_Y_MODIFY 0xFFC00C5C
-#define DMA1_CURR_DESC_PTR 0xFFC00C60
-#define DMA1_CURR_ADDR 0xFFC00C64
-#define DMA1_IRQ_STATUS 0xFFC00C68
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C
-#define DMA1_CURR_X_COUNT 0xFFC00C70
-#define DMA1_CURR_Y_COUNT 0xFFC00C78
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80
-#define DMA2_START_ADDR 0xFFC00C84
-#define DMA2_CONFIG 0xFFC00C88
-#define DMA2_X_COUNT 0xFFC00C90
-#define DMA2_X_MODIFY 0xFFC00C94
-#define DMA2_Y_COUNT 0xFFC00C98
-#define DMA2_Y_MODIFY 0xFFC00C9C
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0
-#define DMA2_CURR_ADDR 0xFFC00CA4
-#define DMA2_IRQ_STATUS 0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC
-#define DMA2_CURR_X_COUNT 0xFFC00CB0
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0
-#define DMA3_START_ADDR 0xFFC00CC4
-#define DMA3_CONFIG 0xFFC00CC8
-#define DMA3_X_COUNT 0xFFC00CD0
-#define DMA3_X_MODIFY 0xFFC00CD4
-#define DMA3_Y_COUNT 0xFFC00CD8
-#define DMA3_Y_MODIFY 0xFFC00CDC
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0
-#define DMA3_CURR_ADDR 0xFFC00CE4
-#define DMA3_IRQ_STATUS 0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC
-#define DMA3_CURR_X_COUNT 0xFFC00CF0
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00
-#define DMA4_START_ADDR 0xFFC00D04
-#define DMA4_CONFIG 0xFFC00D08
-#define DMA4_X_COUNT 0xFFC00D10
-#define DMA4_X_MODIFY 0xFFC00D14
-#define DMA4_Y_COUNT 0xFFC00D18
-#define DMA4_Y_MODIFY 0xFFC00D1C
-#define DMA4_CURR_DESC_PTR 0xFFC00D20
-#define DMA4_CURR_ADDR 0xFFC00D24
-#define DMA4_IRQ_STATUS 0xFFC00D28
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C
-#define DMA4_CURR_X_COUNT 0xFFC00D30
-#define DMA4_CURR_Y_COUNT 0xFFC00D38
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40
-#define DMA5_START_ADDR 0xFFC00D44
-#define DMA5_CONFIG 0xFFC00D48
-#define DMA5_X_COUNT 0xFFC00D50
-#define DMA5_X_MODIFY 0xFFC00D54
-#define DMA5_Y_COUNT 0xFFC00D58
-#define DMA5_Y_MODIFY 0xFFC00D5C
-#define DMA5_CURR_DESC_PTR 0xFFC00D60
-#define DMA5_CURR_ADDR 0xFFC00D64
-#define DMA5_IRQ_STATUS 0xFFC00D68
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C
-#define DMA5_CURR_X_COUNT 0xFFC00D70
-#define DMA5_CURR_Y_COUNT 0xFFC00D78
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80
-#define DMA6_START_ADDR 0xFFC00D84
-#define DMA6_CONFIG 0xFFC00D88
-#define DMA6_X_COUNT 0xFFC00D90
-#define DMA6_X_MODIFY 0xFFC00D94
-#define DMA6_Y_COUNT 0xFFC00D98
-#define DMA6_Y_MODIFY 0xFFC00D9C
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0
-#define DMA6_CURR_ADDR 0xFFC00DA4
-#define DMA6_IRQ_STATUS 0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC
-#define DMA6_CURR_X_COUNT 0xFFC00DB0
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0
-#define DMA7_START_ADDR 0xFFC00DC4
-#define DMA7_CONFIG 0xFFC00DC8
-#define DMA7_X_COUNT 0xFFC00DD0
-#define DMA7_X_MODIFY 0xFFC00DD4
-#define DMA7_Y_COUNT 0xFFC00DD8
-#define DMA7_Y_MODIFY 0xFFC00DDC
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0
-#define DMA7_CURR_ADDR 0xFFC00DE4
-#define DMA7_IRQ_STATUS 0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC
-#define DMA7_CURR_X_COUNT 0xFFC00DF0
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8
-#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
-#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA8_NEXT_DESC_PTR 0xFFC01C00
-#define DMA8_START_ADDR 0xFFC01C04
-#define DMA8_CONFIG 0xFFC01C08
-#define DMA8_X_COUNT 0xFFC01C10
-#define DMA8_X_MODIFY 0xFFC01C14
-#define DMA8_Y_COUNT 0xFFC01C18
-#define DMA8_Y_MODIFY 0xFFC01C1C
-#define DMA8_CURR_DESC_PTR 0xFFC01C20
-#define DMA8_CURR_ADDR 0xFFC01C24
-#define DMA8_IRQ_STATUS 0xFFC01C28
-#define DMA8_PERIPHERAL_MAP 0xFFC01C2C
-#define DMA8_CURR_X_COUNT 0xFFC01C30
-#define DMA8_CURR_Y_COUNT 0xFFC01C38
-#define DMA9_NEXT_DESC_PTR 0xFFC01C40
-#define DMA9_START_ADDR 0xFFC01C44
-#define DMA9_CONFIG 0xFFC01C48
-#define DMA9_X_COUNT 0xFFC01C50
-#define DMA9_X_MODIFY 0xFFC01C54
-#define DMA9_Y_COUNT 0xFFC01C58
-#define DMA9_Y_MODIFY 0xFFC01C5C
-#define DMA9_CURR_DESC_PTR 0xFFC01C60
-#define DMA9_CURR_ADDR 0xFFC01C64
-#define DMA9_IRQ_STATUS 0xFFC01C68
-#define DMA9_PERIPHERAL_MAP 0xFFC01C6C
-#define DMA9_CURR_X_COUNT 0xFFC01C70
-#define DMA9_CURR_Y_COUNT 0xFFC01C78
-#define DMA10_NEXT_DESC_PTR 0xFFC01C80
-#define DMA10_START_ADDR 0xFFC01C84
-#define DMA10_CONFIG 0xFFC01C88
-#define DMA10_X_COUNT 0xFFC01C90
-#define DMA10_X_MODIFY 0xFFC01C94
-#define DMA10_Y_COUNT 0xFFC01C98
-#define DMA10_Y_MODIFY 0xFFC01C9C
-#define DMA10_CURR_DESC_PTR 0xFFC01CA0
-#define DMA10_CURR_ADDR 0xFFC01CA4
-#define DMA10_IRQ_STATUS 0xFFC01CA8
-#define DMA10_PERIPHERAL_MAP 0xFFC01CAC
-#define DMA10_CURR_X_COUNT 0xFFC01CB0
-#define DMA10_CURR_Y_COUNT 0xFFC01CB8
-#define DMA11_NEXT_DESC_PTR 0xFFC01CC0
-#define DMA11_START_ADDR 0xFFC01CC4
-#define DMA11_CONFIG 0xFFC01CC8
-#define DMA11_X_COUNT 0xFFC01CD0
-#define DMA11_X_MODIFY 0xFFC01CD4
-#define DMA11_Y_COUNT 0xFFC01CD8
-#define DMA11_Y_MODIFY 0xFFC01CDC
-#define DMA11_CURR_DESC_PTR 0xFFC01CE0
-#define DMA11_CURR_ADDR 0xFFC01CE4
-#define DMA11_IRQ_STATUS 0xFFC01CE8
-#define DMA11_PERIPHERAL_MAP 0xFFC01CEC
-#define DMA11_CURR_X_COUNT 0xFFC01CF0
-#define DMA11_CURR_Y_COUNT 0xFFC01CF8
-#define DMA12_NEXT_DESC_PTR 0xFFC01D00
-#define DMA12_START_ADDR 0xFFC01D04
-#define DMA12_CONFIG 0xFFC01D08
-#define DMA12_X_COUNT 0xFFC01D10
-#define DMA12_X_MODIFY 0xFFC01D14
-#define DMA12_Y_COUNT 0xFFC01D18
-#define DMA12_Y_MODIFY 0xFFC01D1C
-#define DMA12_CURR_DESC_PTR 0xFFC01D20
-#define DMA12_CURR_ADDR 0xFFC01D24
-#define DMA12_IRQ_STATUS 0xFFC01D28
-#define DMA12_PERIPHERAL_MAP 0xFFC01D2C
-#define DMA12_CURR_X_COUNT 0xFFC01D30
-#define DMA12_CURR_Y_COUNT 0xFFC01D38
-#define DMA13_NEXT_DESC_PTR 0xFFC01D40
-#define DMA13_START_ADDR 0xFFC01D44
-#define DMA13_CONFIG 0xFFC01D48
-#define DMA13_X_COUNT 0xFFC01D50
-#define DMA13_X_MODIFY 0xFFC01D54
-#define DMA13_Y_COUNT 0xFFC01D58
-#define DMA13_Y_MODIFY 0xFFC01D5C
-#define DMA13_CURR_DESC_PTR 0xFFC01D60
-#define DMA13_CURR_ADDR 0xFFC01D64
-#define DMA13_IRQ_STATUS 0xFFC01D68
-#define DMA13_PERIPHERAL_MAP 0xFFC01D6C
-#define DMA13_CURR_X_COUNT 0xFFC01D70
-#define DMA13_CURR_Y_COUNT 0xFFC01D78
-#define DMA14_NEXT_DESC_PTR 0xFFC01D80
-#define DMA14_START_ADDR 0xFFC01D84
-#define DMA14_CONFIG 0xFFC01D88
-#define DMA14_X_COUNT 0xFFC01D90
-#define DMA14_X_MODIFY 0xFFC01D94
-#define DMA14_Y_COUNT 0xFFC01D98
-#define DMA14_Y_MODIFY 0xFFC01D9C
-#define DMA14_CURR_DESC_PTR 0xFFC01DA0
-#define DMA14_CURR_ADDR 0xFFC01DA4
-#define DMA14_IRQ_STATUS 0xFFC01DA8
-#define DMA14_PERIPHERAL_MAP 0xFFC01DAC
-#define DMA14_CURR_X_COUNT 0xFFC01DB0
-#define DMA14_CURR_Y_COUNT 0xFFC01DB8
-#define DMA15_NEXT_DESC_PTR 0xFFC01DC0
-#define DMA15_START_ADDR 0xFFC01DC4
-#define DMA15_CONFIG 0xFFC01DC8
-#define DMA15_X_COUNT 0xFFC01DD0
-#define DMA15_X_MODIFY 0xFFC01DD4
-#define DMA15_Y_COUNT 0xFFC01DD8
-#define DMA15_Y_MODIFY 0xFFC01DDC
-#define DMA15_CURR_DESC_PTR 0xFFC01DE0
-#define DMA15_CURR_ADDR 0xFFC01DE4
-#define DMA15_IRQ_STATUS 0xFFC01DE8
-#define DMA15_PERIPHERAL_MAP 0xFFC01DEC
-#define DMA15_CURR_X_COUNT 0xFFC01DF0
-#define DMA15_CURR_Y_COUNT 0xFFC01DF8
-#define DMA16_NEXT_DESC_PTR 0xFFC01E00
-#define DMA16_START_ADDR 0xFFC01E04
-#define DMA16_CONFIG 0xFFC01E08
-#define DMA16_X_COUNT 0xFFC01E10
-#define DMA16_X_MODIFY 0xFFC01E14
-#define DMA16_Y_COUNT 0xFFC01E18
-#define DMA16_Y_MODIFY 0xFFC01E1C
-#define DMA16_CURR_DESC_PTR 0xFFC01E20
-#define DMA16_CURR_ADDR 0xFFC01E24
-#define DMA16_IRQ_STATUS 0xFFC01E28
-#define DMA16_PERIPHERAL_MAP 0xFFC01E2C
-#define DMA16_CURR_X_COUNT 0xFFC01E30
-#define DMA16_CURR_Y_COUNT 0xFFC01E38
-#define DMA17_NEXT_DESC_PTR 0xFFC01E40
-#define DMA17_START_ADDR 0xFFC01E44
-#define DMA17_CONFIG 0xFFC01E48
-#define DMA17_X_COUNT 0xFFC01E50
-#define DMA17_X_MODIFY 0xFFC01E54
-#define DMA17_Y_COUNT 0xFFC01E58
-#define DMA17_Y_MODIFY 0xFFC01E5C
-#define DMA17_CURR_DESC_PTR 0xFFC01E60
-#define DMA17_CURR_ADDR 0xFFC01E64
-#define DMA17_IRQ_STATUS 0xFFC01E68
-#define DMA17_PERIPHERAL_MAP 0xFFC01E6C
-#define DMA17_CURR_X_COUNT 0xFFC01E70
-#define DMA17_CURR_Y_COUNT 0xFFC01E78
-#define DMA18_NEXT_DESC_PTR 0xFFC01E80
-#define DMA18_START_ADDR 0xFFC01E84
-#define DMA18_CONFIG 0xFFC01E88
-#define DMA18_X_COUNT 0xFFC01E90
-#define DMA18_X_MODIFY 0xFFC01E94
-#define DMA18_Y_COUNT 0xFFC01E98
-#define DMA18_Y_MODIFY 0xFFC01E9C
-#define DMA18_CURR_DESC_PTR 0xFFC01EA0
-#define DMA18_CURR_ADDR 0xFFC01EA4
-#define DMA18_IRQ_STATUS 0xFFC01EA8
-#define DMA18_PERIPHERAL_MAP 0xFFC01EAC
-#define DMA18_CURR_X_COUNT 0xFFC01EB0
-#define DMA18_CURR_Y_COUNT 0xFFC01EB8
-#define DMA19_NEXT_DESC_PTR 0xFFC01EC0
-#define DMA19_START_ADDR 0xFFC01EC4
-#define DMA19_CONFIG 0xFFC01EC8
-#define DMA19_X_COUNT 0xFFC01ED0
-#define DMA19_X_MODIFY 0xFFC01ED4
-#define DMA19_Y_COUNT 0xFFC01ED8
-#define DMA19_Y_MODIFY 0xFFC01EDC
-#define DMA19_CURR_DESC_PTR 0xFFC01EE0
-#define DMA19_CURR_ADDR 0xFFC01EE4
-#define DMA19_IRQ_STATUS 0xFFC01EE8
-#define DMA19_PERIPHERAL_MAP 0xFFC01EEC
-#define DMA19_CURR_X_COUNT 0xFFC01EF0
-#define DMA19_CURR_Y_COUNT 0xFFC01EF8
-#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00
-#define MDMA0_D0_START_ADDR 0xFFC00E04
-#define MDMA0_D0_CONFIG 0xFFC00E08
-#define MDMA0_D0_X_COUNT 0xFFC00E10
-#define MDMA0_D0_X_MODIFY 0xFFC00E14
-#define MDMA0_D0_Y_COUNT 0xFFC00E18
-#define MDMA0_D0_Y_MODIFY 0xFFC00E1C
-#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20
-#define MDMA0_D0_CURR_ADDR 0xFFC00E24
-#define MDMA0_D0_IRQ_STATUS 0xFFC00E28
-#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C
-#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30
-#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38
-#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40
-#define MDMA0_S0_START_ADDR 0xFFC00E44
-#define MDMA0_S0_CONFIG 0xFFC00E48
-#define MDMA0_S0_X_COUNT 0xFFC00E50
-#define MDMA0_S0_X_MODIFY 0xFFC00E54
-#define MDMA0_S0_Y_COUNT 0xFFC00E58
-#define MDMA0_S0_Y_MODIFY 0xFFC00E5C
-#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60
-#define MDMA0_S0_CURR_ADDR 0xFFC00E64
-#define MDMA0_S0_IRQ_STATUS 0xFFC00E68
-#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C
-#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70
-#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78
-#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80
-#define MDMA0_D1_START_ADDR 0xFFC00E84
-#define MDMA0_D1_CONFIG 0xFFC00E88
-#define MDMA0_D1_X_COUNT 0xFFC00E90
-#define MDMA0_D1_X_MODIFY 0xFFC00E94
-#define MDMA0_D1_Y_COUNT 0xFFC00E98
-#define MDMA0_D1_Y_MODIFY 0xFFC00E9C
-#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0
-#define MDMA0_D1_CURR_ADDR 0xFFC00EA4
-#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8
-#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC
-#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0
-#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8
-#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0
-#define MDMA0_S1_START_ADDR 0xFFC00EC4
-#define MDMA0_S1_CONFIG 0xFFC00EC8
-#define MDMA0_S1_X_COUNT 0xFFC00ED0
-#define MDMA0_S1_X_MODIFY 0xFFC00ED4
-#define MDMA0_S1_Y_COUNT 0xFFC00ED8
-#define MDMA0_S1_Y_MODIFY 0xFFC00EDC
-#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0
-#define MDMA0_S1_CURR_ADDR 0xFFC00EE4
-#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8
-#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC
-#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0
-#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
-#define MDMA1_D0_START_ADDR 0xFFC01F04
-#define MDMA1_D0_CONFIG 0xFFC01F08
-#define MDMA1_D0_X_COUNT 0xFFC01F10
-#define MDMA1_D0_X_MODIFY 0xFFC01F14
-#define MDMA1_D0_Y_COUNT 0xFFC01F18
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
-#define MDMA1_S0_START_ADDR 0xFFC01F44
-#define MDMA1_S0_CONFIG 0xFFC01F48
-#define MDMA1_S0_X_COUNT 0xFFC01F50
-#define MDMA1_S0_X_MODIFY 0xFFC01F54
-#define MDMA1_S0_Y_COUNT 0xFFC01F58
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
-#define MDMA1_D1_START_ADDR 0xFFC01F84
-#define MDMA1_D1_CONFIG 0xFFC01F88
-#define MDMA1_D1_X_COUNT 0xFFC01F90
-#define MDMA1_D1_X_MODIFY 0xFFC01F94
-#define MDMA1_D1_Y_COUNT 0xFFC01F98
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
-#define MDMA1_S1_START_ADDR 0xFFC01FC4
-#define MDMA1_S1_CONFIG 0xFFC01FC8
-#define MDMA1_S1_X_COUNT 0xFFC01FD0
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
-#define PPI_CONTROL 0xFFC01000
-#define PPI_STATUS 0xFFC01004
-#define PPI_DELAY 0xFFC0100C
-#define PPI_COUNT 0xFFC01008
-#define PPI_FRAME 0xFFC01010
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWIO Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWIO Master Interrupt Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWIO Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Config register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF538_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h
deleted file mode 100644
index 7e785b45c937..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF538_cdef.h"
diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_def.h b/arch/blackfin/include/asm/mach-bf538/BF539_def.h
deleted file mode 100644
index 5a2ed8d16c5b..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/BF539_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "BF538_def.h"
diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h
deleted file mode 100644
index b6ca99788710..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/anomaly.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf538/def_local.h b/arch/blackfin/include/asm/mach-bf538/def_local.h
deleted file mode 100644
index 54d8e7615125..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF538_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf538/gpio.h b/arch/blackfin/include/asm/mach-bf538/gpio.h
deleted file mode 100644
index bd9adb7183da..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/gpio.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#define BFIN_SPECIAL_GPIO_BANKS 3
-
-#define GPIO_PF0 0 /* PF */
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PC0 16 /* PC */
-#define GPIO_PC1 17
-#define GPIO_PC4 20
-#define GPIO_PC5 21
-#define GPIO_PC6 22
-#define GPIO_PC7 23
-#define GPIO_PC8 24
-#define GPIO_PC9 25
-#define GPIO_PD0 32 /* PD */
-#define GPIO_PD1 33
-#define GPIO_PD2 34
-#define GPIO_PD3 35
-#define GPIO_PD4 36
-#define GPIO_PD5 37
-#define GPIO_PD6 38
-#define GPIO_PD7 39
-#define GPIO_PD8 40
-#define GPIO_PD9 41
-#define GPIO_PD10 42
-#define GPIO_PD11 43
-#define GPIO_PD12 44
-#define GPIO_PD13 45
-#define GPIO_PE0 48 /* PE */
-#define GPIO_PE1 49
-#define GPIO_PE2 50
-#define GPIO_PE3 51
-#define GPIO_PE4 52
-#define GPIO_PE5 53
-#define GPIO_PE6 54
-#define GPIO_PE7 55
-#define GPIO_PE8 56
-#define GPIO_PE9 57
-#define GPIO_PE10 58
-#define GPIO_PE11 59
-#define GPIO_PE12 60
-#define GPIO_PE13 61
-#define GPIO_PE14 62
-#define GPIO_PE15 63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf538/portmux.h b/arch/blackfin/include/asm/mach-bf538/portmux.h
deleted file mode 100644
index b773c5fdbc72..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/portmux.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES 64
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf538/ports.h b/arch/blackfin/include/asm/mach-bf538/ports.h
deleted file mode 100644
index 4ae09f0582ec..000000000000
--- a/arch/blackfin/include/asm/mach-bf538/ports.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
deleted file mode 100644
index 84fa5d2dfbeb..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
+++ /dev/null
@@ -1,2913 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF542_extended__
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
deleted file mode 100644
index d94744d1e41d..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
+++ /dev/null
@@ -1,1463 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__
-#define __BFIN_DEF_ADSP_EDN_BF542_extended__
-
-#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PORTA_FER 0xFFC014C0 /* Function Enable Register */
-#define PORTA 0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER 0xFFC014E0 /* Function Enable Register */
-#define PORTB 0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER 0xFFC01500 /* Function Enable Register */
-#define PORTC 0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER 0xFFC01520 /* Function Enable Register */
-#define PORTD 0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER 0xFFC01540 /* Function Enable Register */
-#define PORTE 0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER 0xFFC01560 /* Function Enable Register */
-#define PORTF 0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER 0xFFC01580 /* Function Enable Register */
-#define PORTG 0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER 0xFFC015A0 /* Function Enable Register */
-#define PORTH 0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER 0xFFC015C0 /* Function Enable Register */
-#define PORTI 0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */
-#define PORTJ 0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */
-#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG 0xFFC04200 /* Configuration Register */
-#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC04208 /* Status Register */
-#define CNT_COMMAND 0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER 0xFFC04214 /* Counter Register */
-#define CNT_MAX 0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN 0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS 0xFFC04328 /* Secure Status */
-#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND 0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS 0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL 0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT 0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD 0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */
-#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xFFC03108 /* Global Control Register */
-#define UART3_LCR 0xFFC0310C /* Line Control Register */
-#define UART3_MCR 0xFFC03110 /* Modem Control Register */
-#define UART3_LSR 0xFFC03114 /* Line Status Register */
-#define UART3_MSR 0xFFC03118 /* Modem Status Register */
-#define UART3_SCR 0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR 0xFFC03C00 /* Function address register */
-#define USB_POWER 0xFFC03C04 /* Power management register */
-#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03C20 /* USB frame number */
-#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
deleted file mode 100644
index 517e14309eea..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
+++ /dev/null
@@ -1,3309 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
deleted file mode 100644
index 4b4f67d9552a..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
+++ /dev/null
@@ -1,1661 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF544_extended__
-#define __BFIN_DEF_ADSP_EDN_BF544_extended__
-
-#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER 0xFFC014C0 /* Function Enable Register */
-#define PORTA 0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER 0xFFC014E0 /* Function Enable Register */
-#define PORTB 0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER 0xFFC01500 /* Function Enable Register */
-#define PORTC 0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER 0xFFC01520 /* Function Enable Register */
-#define PORTD 0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER 0xFFC01540 /* Function Enable Register */
-#define PORTE 0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER 0xFFC01560 /* Function Enable Register */
-#define PORTF 0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER 0xFFC01580 /* Function Enable Register */
-#define PORTG 0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER 0xFFC015A0 /* Function Enable Register */
-#define PORTH 0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER 0xFFC015C0 /* Function Enable Register */
-#define PORTI 0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */
-#define PORTJ 0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG 0xFFC04200 /* Configuration Register */
-#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC04208 /* Status Register */
-#define CNT_COMMAND 0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER 0xFFC04214 /* Counter Register */
-#define CNT_MAX 0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN 0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS 0xFFC04328 /* Secure Status */
-#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define NFC_CTL 0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT 0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD 0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xFFC03108 /* Global Control Register */
-#define UART3_LCR 0xFFC0310C /* Line Control Register */
-#define UART3_MCR 0xFFC03110 /* Modem Control Register */
-#define UART3_LSR 0xFFC03114 /* Line Status Register */
-#define UART3_MSR 0xFFC03118 /* Modem Status Register */
-#define UART3_SCR 0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
deleted file mode 100644
index 7e0c043b1c4b..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
+++ /dev/null
@@ -1,2404 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF547_extended__
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
deleted file mode 100644
index ef9111fed4e4..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
+++ /dev/null
@@ -1,1209 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF547_extended__
-#define __BFIN_DEF_ADSP_EDN_BF547_extended__
-
-#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER 0xFFC014C0 /* Function Enable Register */
-#define PORTA 0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER 0xFFC014E0 /* Function Enable Register */
-#define PORTB 0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER 0xFFC01500 /* Function Enable Register */
-#define PORTC 0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER 0xFFC01520 /* Function Enable Register */
-#define PORTD 0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER 0xFFC01540 /* Function Enable Register */
-#define PORTE 0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER 0xFFC01560 /* Function Enable Register */
-#define PORTF 0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER 0xFFC01580 /* Function Enable Register */
-#define PORTG 0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER 0xFFC015A0 /* Function Enable Register */
-#define PORTH 0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER 0xFFC015C0 /* Function Enable Register */
-#define PORTI 0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */
-#define PORTJ 0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG 0xFFC04200 /* Configuration Register */
-#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC04208 /* Status Register */
-#define CNT_COMMAND 0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER 0xFFC04214 /* Counter Register */
-#define CNT_MAX 0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN 0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS 0xFFC04328 /* Secure Status */
-#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND 0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS 0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL 0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT 0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD 0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xFFC02108 /* Global Control Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_MSR 0xFFC02118 /* Modem Status Register */
-#define UART2_SCR 0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR 0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xFFC03108 /* Global Control Register */
-#define UART3_LCR 0xFFC0310C /* Line Control Register */
-#define UART3_MCR 0xFFC03110 /* Modem Control Register */
-#define UART3_LSR 0xFFC03114 /* Line Status Register */
-#define UART3_MSR 0xFFC03118 /* Modem Status Register */
-#define UART3_SCR 0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR 0xFFC03C00 /* Function address register */
-#define USB_POWER 0xFFC03C04 /* Power management register */
-#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03C20 /* USB frame number */
-#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
deleted file mode 100644
index dfb32760be63..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
+++ /dev/null
@@ -1,3852 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF548_extended__
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
deleted file mode 100644
index 1be6688619cd..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
+++ /dev/null
@@ -1,1933 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__
-#define __BFIN_DEF_ADSP_EDN_BF548_extended__
-
-#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER 0xFFC014C0 /* Function Enable Register */
-#define PORTA 0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER 0xFFC014E0 /* Function Enable Register */
-#define PORTB 0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER 0xFFC01500 /* Function Enable Register */
-#define PORTC 0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER 0xFFC01520 /* Function Enable Register */
-#define PORTD 0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER 0xFFC01540 /* Function Enable Register */
-#define PORTE 0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER 0xFFC01560 /* Function Enable Register */
-#define PORTF 0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER 0xFFC01580 /* Function Enable Register */
-#define PORTG 0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER 0xFFC015A0 /* Function Enable Register */
-#define PORTH 0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER 0xFFC015C0 /* Function Enable Register */
-#define PORTI 0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */
-#define PORTJ 0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG 0xFFC04200 /* Configuration Register */
-#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC04208 /* Status Register */
-#define CNT_COMMAND 0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER 0xFFC04214 /* Counter Register */
-#define CNT_MAX 0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN 0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS 0xFFC04328 /* Secure Status */
-#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND 0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS 0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL 0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT 0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD 0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xFFC02108 /* Global Control Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_MSR 0xFFC02118 /* Modem Status Register */
-#define UART2_SCR 0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR 0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xFFC03108 /* Global Control Register */
-#define UART3_LCR 0xFFC0310C /* Line Control Register */
-#define UART3_MCR 0xFFC03110 /* Modem Control Register */
-#define UART3_LSR 0xFFC03114 /* Line Status Register */
-#define UART3_MSR 0xFFC03118 /* Modem Status Register */
-#define UART3_SCR 0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR 0xFFC03C00 /* Function address register */
-#define USB_POWER 0xFFC03C04 /* Power management register */
-#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03C20 /* USB frame number */
-#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
deleted file mode 100644
index 970f13f5d03d..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
+++ /dev/null
@@ -1,4084 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
-#define __BFIN_CDEF_ADSP_EDN_BF549_extended__
-
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
-#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val)
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ)
-#define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ)
-#define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ)
-#define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ)
-#define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL)
-#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
-#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
-#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL)
-#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
-#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
-#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
deleted file mode 100644
index 33c82b427d98..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
+++ /dev/null
@@ -1,2049 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_BF549_extended__
-#define __BFIN_DEF_ADSP_EDN_BF549_extended__
-
-#define SIC_IMASK0 0xFFC0010C /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xFFC00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xFFC00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xFFC00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xFFC0011C /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xFFC00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xFFC00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xFFC00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xFFC0012C /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xFFC00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0013C /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC0014C /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xFFC00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xFFC00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xFFC00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xFFC0015C /* System Interrupt Assignment Register 11 */
-#define DMAC0_TCPER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TCCNT 0xFFC00B10 /* DMA Controller 0 Current Counts Register */
-#define DMAC1_TCPER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TCCNT 0xFFC01B10 /* DMA Controller 1 Current Counts Register */
-#define DMAC1_PERIMUX 0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
-#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
-#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
-#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
-#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
-#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
-#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
-#define DMA19_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01DC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01DC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01DD0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01DD8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01DE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
-#define DMA20_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xFFC01E04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xFFC01E08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC01E10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xFFC01E14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xFFC01E18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xFFC01E24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
-#define DMA21_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xFFC01E44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xFFC01E48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC01E50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xFFC01E54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xFFC01E58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xFFC01E64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
-#define DMA22_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xFFC01E84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xFFC01E88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC01E90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xFFC01E94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xFFC01E98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xFFC01EA4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
-#define DMA23_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xFFC01EC4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xFFC01EC8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC01ED0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xFFC01ED8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xFFC01EE4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
-#define HMDMA0_CONTROL 0xFFC04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECOUNT 0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA1_CONTROL 0xFFC04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xFFC00A14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xFFC00A18 /* Asynchronous Memory Flash Control Register */
-#define EBIU_DDRCTL0 0xFFC00A20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xFFC00A24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xFFC00A28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xFFC00A2C /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xFFC00A30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xFFC00A34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xFFC00A38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */
-#define EBIU_DDRBRC0 0xFFC00A60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xFFC00A64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xFFC00A68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xFFC00A6C /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xFFC00A70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xFFC00A74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xFFC00A78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xFFC00A7C /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xFFC00A80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xFFC00A84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xFFC00A88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xFFC00A8C /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xFFC00A90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xFFC00A94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xFFC00A98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xFFC00A9C /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xFFC00AA0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xFFC00AA8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xFFC00AAC /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xFFC00AB0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xFFC00AB4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xFFC00AB8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xFFC00ABC /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xFFC00AC0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xFFC00AC4 /* DDR Metrics Counter Clear Register */
-#define PIXC_CTL 0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xFFC04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xFFC04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xFFC0441C /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xFFC04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xFFC0443C /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xFFC0444C /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xFFC04450 /* Holds the transparent color value */
-#define HOST_CONTROL 0xFFC03A00 /* HOSTDP Control Register */
-#define HOST_STATUS 0xFFC03A04 /* HOSTDP Status Register */
-#define HOST_TIMEOUT 0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
-#define PORTA_FER 0xFFC014C0 /* Function Enable Register */
-#define PORTA 0xFFC014C4 /* GPIO Data Register */
-#define PORTA_SET 0xFFC014C8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xFFC014CC /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xFFC014D0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC014D4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC014D8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xFFC014DC /* Multiplexer Control Register */
-#define PORTB_FER 0xFFC014E0 /* Function Enable Register */
-#define PORTB 0xFFC014E4 /* GPIO Data Register */
-#define PORTB_SET 0xFFC014E8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xFFC014EC /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xFFC014F0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC014F4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC014F8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xFFC014FC /* Multiplexer Control Register */
-#define PORTC_FER 0xFFC01500 /* Function Enable Register */
-#define PORTC 0xFFC01504 /* GPIO Data Register */
-#define PORTC_SET 0xFFC01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xFFC0150C /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xFFC01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xFFC0151C /* Multiplexer Control Register */
-#define PORTD_FER 0xFFC01520 /* Function Enable Register */
-#define PORTD 0xFFC01524 /* GPIO Data Register */
-#define PORTD_SET 0xFFC01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xFFC0152C /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xFFC01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xFFC0153C /* Multiplexer Control Register */
-#define PORTE_FER 0xFFC01540 /* Function Enable Register */
-#define PORTE 0xFFC01544 /* GPIO Data Register */
-#define PORTE_SET 0xFFC01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xFFC0154C /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xFFC01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xFFC0155C /* Multiplexer Control Register */
-#define PORTF_FER 0xFFC01560 /* Function Enable Register */
-#define PORTF 0xFFC01564 /* GPIO Data Register */
-#define PORTF_SET 0xFFC01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xFFC0156C /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xFFC01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xFFC0157C /* Multiplexer Control Register */
-#define PORTG_FER 0xFFC01580 /* Function Enable Register */
-#define PORTG 0xFFC01584 /* GPIO Data Register */
-#define PORTG_SET 0xFFC01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xFFC0158C /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xFFC01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xFFC0159C /* Multiplexer Control Register */
-#define PORTH_FER 0xFFC015A0 /* Function Enable Register */
-#define PORTH 0xFFC015A4 /* GPIO Data Register */
-#define PORTH_SET 0xFFC015A8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xFFC015AC /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xFFC015B0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xFFC015B4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xFFC015B8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xFFC015BC /* Multiplexer Control Register */
-#define PORTI_FER 0xFFC015C0 /* Function Enable Register */
-#define PORTI 0xFFC015C4 /* GPIO Data Register */
-#define PORTI_SET 0xFFC015C8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xFFC015CC /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xFFC015D0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xFFC015D4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xFFC015D8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xFFC015DC /* Multiplexer Control Register */
-#define PORTJ_FER 0xFFC015E0 /* Function Enable Register */
-#define PORTJ 0xFFC015E4 /* GPIO Data Register */
-#define PORTJ_SET 0xFFC015E8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xFFC015EC /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xFFC015F0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xFFC015F4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xFFC015F8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xFFC015FC /* Multiplexer Control Register */
-#define PINT0_MASK_SET 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_IRQ 0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xFFC01424 /* Pin Interrupt 0 Latch Register */
-#define PINT1_MASK_SET 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_IRQ 0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xFFC01454 /* Pin Interrupt 1 Latch Register */
-#define PINT2_MASK_SET 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_IRQ 0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xFFC01484 /* Pin Interrupt 2 Latch Register */
-#define PINT3_MASK_SET 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_IRQ 0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xFFC014B4 /* Pin Interrupt 3 Latch Register */
-#define TIMER0_CONFIG 0xFFC01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0160C /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xFFC01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0161C /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xFFC01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0162C /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xFFC01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0163C /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xFFC01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0164C /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xFFC01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0165C /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xFFC01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0166C /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xFFC01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0167C /* Timer 7 Width Register */
-#define TIMER8_CONFIG 0xFFC00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xFFC00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xFFC00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xFFC0060C /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xFFC00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xFFC00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xFFC00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xFFC0061C /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xFFC00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xFFC00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xFFC00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xFFC0062C /* Timer 10 Width Register */
-#define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */
-#define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-#define CNT_CONFIG 0xFFC04200 /* Configuration Register */
-#define CNT_IMASK 0xFFC04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xFFC04208 /* Status Register */
-#define CNT_COMMAND 0xFFC0420C /* Command Register */
-#define CNT_DEBOUNCE 0xFFC04210 /* Debounce Register */
-#define CNT_COUNTER 0xFFC04214 /* Counter Register */
-#define CNT_MAX 0xFFC04218 /* Maximal Count Register */
-#define CNT_MIN 0xFFC0421C /* Minimal Count Register */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */
-#define OTP_CONTROL 0xFFC04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xFFC04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xFFC04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xFFC0430C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT 0xFFC04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xFFC04324 /* Secure Control */
-#define SECURE_STATUS 0xFFC04328 /* Secure Status */
-#define OTP_DATA0 0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divisor Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
-#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
-#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count */
-#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count */
-#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count */
-#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count */
-#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count */
-#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count */
-#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count */
-#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count */
-#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
-#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
-#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
-#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL 0xFFC028D0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL 0xFFC028D4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL 0xFFC028D8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL 0xFFC028DC /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT 0xFFC028E0 /* MXVR System Clock Counter Register */
-#define KPAD_CTL 0xFFC04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xFFC0410C /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
-#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
-#define SDH_COMMAND 0xFFC0390C /* SDH Command */
-#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
-#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
-#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
-#define SDH_STATUS 0xFFC03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
-#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
-#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
-#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
-#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
-#define ATAPI_CONTROL 0xFFC03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xFFC03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xFFC03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xFFC0380C /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xFFC03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xFFC03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xFFC03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xFFC0381C /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xFFC03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xFFC03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xFFC03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xFFC0382C /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xFFC03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xFFC03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xFFC03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xFFC03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xFFC03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xFFC03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
-#define NFC_CTL 0xFFC03B00 /* NAND Control Register */
-#define NFC_STAT 0xFFC03B04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xFFC03B08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xFFC03B0C /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xFFC03B10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xFFC03B14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xFFC03B18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xFFC03B1C /* NAND ECC Register 3 */
-#define NFC_COUNT 0xFFC03B20 /* NAND ECC Count Register */
-#define NFC_RST 0xFFC03B24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xFFC03B28 /* NAND Page Control Register */
-#define NFC_READ 0xFFC03B2C /* NAND Read Data Register */
-#define NFC_ADDR 0xFFC03B40 /* NAND Address Register */
-#define NFC_CMD 0xFFC03B44 /* NAND Command Register */
-#define NFC_DATA_WR 0xFFC03B48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xFFC03B4C /* NAND Data Read Register */
-#define EPPI0_STATUS 0xFFC01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xFFC01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xFFC01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xFFC0101C /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xFFC01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xFFC01034 /* EPPI0 Clipping Register */
-#define EPPI1_STATUS 0xFFC01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xFFC01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xFFC01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xFFC0131C /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xFFC01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xFFC01334 /* EPPI1 Clipping Register */
-#define EPPI2_STATUS 0xFFC02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xFFC02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xFFC02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xFFC0291C /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xFFC02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xFFC02934 /* EPPI2 Clipping Register */
-#define CAN0_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN0_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN0_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN0_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN0_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN0_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN0_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define CAN1_MC1 0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN1_MC2 0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN1_CLOCK 0xFFC03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xFFC03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xFFC03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xFFC0328C /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xFFC03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xFFC032A0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xFFC032B4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
-#define CAN1_AM00L 0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-#define CAN1_AM16L 0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-#define CAN1_MB00_DATA0 0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
-#define CAN1_MB16_DATA0 0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
-#define TWI0_CLKDIV 0xFFC00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xFFC00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0070C /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0071C /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0072C /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
-#define TWI1_CLKDIV 0xFFC02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 Receive Data Register */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 Receive Data Register */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 Receive Data Register */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 Receive Data Register */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xFFC00408 /* Global Control Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xFFC02008 /* Global Control Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xFFC02108 /* Global Control Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_MSR 0xFFC02118 /* Modem Status Register */
-#define UART2_SCR 0xFFC0211C /* Scratch Register */
-#define UART2_IER_SET 0xFFC02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xFFC02124 /* Interrupt Enable Register Clear */
-#define UART2_THR 0xFFC02128 /* Transmit Hold Register */
-#define UART2_RBR 0xFFC0212C /* Receive Buffer Register */
-#define UART3_DLL 0xFFC03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xFFC03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xFFC03108 /* Global Control Register */
-#define UART3_LCR 0xFFC0310C /* Line Control Register */
-#define UART3_MCR 0xFFC03110 /* Modem Control Register */
-#define UART3_LSR 0xFFC03114 /* Line Status Register */
-#define UART3_MSR 0xFFC03118 /* Modem Status Register */
-#define UART3_SCR 0xFFC0311C /* Scratch Register */
-#define UART3_IER_SET 0xFFC03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xFFC03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xFFC03128 /* Transmit Hold Register */
-#define UART3_RBR 0xFFC0312C /* Receive Buffer Register */
-#define USB_FADDR 0xFFC03C00 /* Function address register */
-#define USB_POWER 0xFFC03C04 /* Power management register */
-#define USB_INTRTX 0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xFFC03C10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xFFC03C14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xFFC03C18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xFFC03C1C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xFFC03C20 /* USB frame number */
-#define USB_INDEX 0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xFFC03C28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xFFC03C30 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET 0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xFFC03C4C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO 0xFFC03C80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xFFC03C88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xFFC03C90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xFFC03C98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xFFC03CA0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xFFC03CA8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xFFC03CB0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xFFC03CB8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL 0xFFC03D00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xFFC03D04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xFFC03D08 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO 0xFFC03D48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xFFC03D50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xFFC03D54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xFFC03D58 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB 0xFFC03DE4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST 0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL 0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP 0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xFFC03E04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xFFC03E44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xFFC03E84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xFFC03EC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xFFC03F04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xFFC03F44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xFFC03F84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xFFC03FC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xFFC04000 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL 0xFFC04004 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW 0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH 0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW 0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH 0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL 0xFFC04024 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW 0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH 0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW 0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH 0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL 0xFFC04044 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW 0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH 0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW 0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH 0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL 0xFFC04064 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW 0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH 0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW 0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH 0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL 0xFFC04084 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW 0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH 0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW 0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH 0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL 0xFFC040A4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW 0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH 0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW 0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH 0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL 0xFFC040C4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW 0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH 0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW 0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH 0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL 0xFFC040E4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW 0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH 0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW 0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH 0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
deleted file mode 100644
index fbd309210f69..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF542_proc__
-#define __BFIN_CDEF_ADSP_BF542_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF542-extended_cdef.h"
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_def.h b/arch/blackfin/include/asm/mach-bf548/BF542_def.h
deleted file mode 100644
index 38452ffee089..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF542_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF542_proc__
-#define __BFIN_DEF_ADSP_BF542_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF542-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
deleted file mode 100644
index ef26af33d0b3..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF544_proc__
-#define __BFIN_CDEF_ADSP_BF544_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF544-extended_cdef.h"
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_def.h b/arch/blackfin/include/asm/mach-bf548/BF544_def.h
deleted file mode 100644
index c12e9befb56f..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF544_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF544_proc__
-#define __BFIN_DEF_ADSP_BF544_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF544-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
deleted file mode 100644
index 3f1ff8b4f23a..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF547_proc__
-#define __BFIN_CDEF_ADSP_BF547_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF547-extended_cdef.h"
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_def.h b/arch/blackfin/include/asm/mach-bf548/BF547_def.h
deleted file mode 100644
index e1f666b1c954..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF547_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF547_proc__
-#define __BFIN_DEF_ADSP_BF547_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF547-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
deleted file mode 100644
index c8be3afa0968..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF548_proc__
-#define __BFIN_CDEF_ADSP_BF548_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF548-extended_cdef.h"
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_def.h b/arch/blackfin/include/asm/mach-bf548/BF548_def.h
deleted file mode 100644
index 48b257c7f53d..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF548_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF548_proc__
-#define __BFIN_DEF_ADSP_BF548_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF548-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
deleted file mode 100644
index 212d54e27a0e..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF549_proc__
-#define __BFIN_CDEF_ADSP_BF549_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#include "ADSP-EDN-BF549-extended_cdef.h"
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_def.h b/arch/blackfin/include/asm/mach-bf548/BF549_def.h
deleted file mode 100644
index 22f4a88b6125..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/BF549_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF549_proc__
-#define __BFIN_DEF_ADSP_BF549_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#include "ADSP-EDN-BF549-extended_def.h"
-
-#define CHIPID 0xFFC00014
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration register */
-
-#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h
deleted file mode 100644
index 021fb1977385..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/anomaly.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-/* XXX: let u-boot slide
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-*/
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- * shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem@Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h
deleted file mode 100644
index f1e69a7b0de2..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/def_local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "gpio.h"
-#include "mem_map.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF54x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf548/gpio.h b/arch/blackfin/include/asm/mach-bf548/gpio.h
deleted file mode 100644
index 28037e331964..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/gpio.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31 /* N/A */
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46 /* N/A */
-#define GPIO_PC15 47 /* N/A */
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-#define GPIO_PH0 112
-#define GPIO_PH1 113
-#define GPIO_PH2 114
-#define GPIO_PH3 115
-#define GPIO_PH4 116
-#define GPIO_PH5 117
-#define GPIO_PH6 118
-#define GPIO_PH7 119
-#define GPIO_PH8 120
-#define GPIO_PH9 121
-#define GPIO_PH10 122
-#define GPIO_PH11 123
-#define GPIO_PH12 124
-#define GPIO_PH13 125
-#define GPIO_PH14 126 /* N/A */
-#define GPIO_PH15 127 /* N/A */
-#define GPIO_PI0 128
-#define GPIO_PI1 129
-#define GPIO_PI2 130
-#define GPIO_PI3 131
-#define GPIO_PI4 132
-#define GPIO_PI5 133
-#define GPIO_PI6 134
-#define GPIO_PI7 135
-#define GPIO_PI8 136
-#define GPIO_PI9 137
-#define GPIO_PI10 138
-#define GPIO_PI11 139
-#define GPIO_PI12 140
-#define GPIO_PI13 141
-#define GPIO_PI14 142
-#define GPIO_PI15 143
-#define GPIO_PJ0 144
-#define GPIO_PJ1 145
-#define GPIO_PJ2 146
-#define GPIO_PJ3 147
-#define GPIO_PJ4 148
-#define GPIO_PJ5 149
-#define GPIO_PJ6 150
-#define GPIO_PJ7 151
-#define GPIO_PJ8 152
-#define GPIO_PJ9 153
-#define GPIO_PJ10 154
-#define GPIO_PJ11 155
-#define GPIO_PJ12 156
-#define GPIO_PJ13 157
-#define GPIO_PJ14 158 /* N/A */
-#define GPIO_PJ15 159 /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned short port_fer;
- unsigned short dummy1;
- unsigned short data;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short data_clear;
- unsigned short dummy4;
- unsigned short dir_set;
- unsigned short dummy5;
- unsigned short dir_clear;
- unsigned short dummy6;
- unsigned short inen;
- unsigned short dummy7;
- unsigned int port_mux;
-};
-
-struct gpio_port_s {
- unsigned short fer;
- unsigned short data;
- unsigned short dir;
- unsigned short inen;
- unsigned int mux;
-};
-
-#endif
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/mem_map.h b/arch/blackfin/include/asm/mach-bf548/mem_map.h
deleted file mode 100644
index 4f943977f5f6..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/mem_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BF54X_MEM_MAP_H__
-#define __BF54X_MEM_MAP_H__
-
-#define L1_DATA_A_SRAM (0xFF800000)
-#define L1_DATA_A_SRAM_SIZE (0x4000)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM (0xFF900000)
-#define L1_DATA_B_SRAM_SIZE (0x4000)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM (0xFFA00000)
-#define L1_INST_SRAM_SIZE (0xC000)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/portmux.h b/arch/blackfin/include/asm/mach-bf548/portmux.h
deleted file mode 100644
index e22246202730..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/portmux.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A (P_DONTCARE)
-# define P_ATAPI_D1A (P_DONTCARE)
-# define P_ATAPI_D2A (P_DONTCARE)
-# define P_ATAPI_D3A (P_DONTCARE)
-# define P_ATAPI_D4A (P_DONTCARE)
-# define P_ATAPI_D5A (P_DONTCARE)
-# define P_ATAPI_D6A (P_DONTCARE)
-# define P_ATAPI_D7A (P_DONTCARE)
-# define P_ATAPI_D8A (P_DONTCARE)
-# define P_ATAPI_D9A (P_DONTCARE)
-# define P_ATAPI_D10A (P_DONTCARE)
-# define P_ATAPI_D11A (P_DONTCARE)
-# define P_ATAPI_D12A (P_DONTCARE)
-# define P_ATAPI_D13A (P_DONTCARE)
-# define P_ATAPI_D14A (P_DONTCARE)
-# define P_ATAPI_D15A (P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A (P_DONTCARE)
-# define P_ATAPI_A1A (P_DONTCARE)
-# define P_ATAPI_A2A (P_DONTCARE)
-#endif
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0 (P_DONTCARE)
-#define P_NAND_D1 (P_DONTCARE)
-#define P_NAND_D2 (P_DONTCARE)
-#define P_NAND_D3 (P_DONTCARE)
-#define P_NAND_D4 (P_DONTCARE)
-#define P_NAND_D5 (P_DONTCARE)
-#define P_NAND_D6 (P_DONTCARE)
-#define P_NAND_D7 (P_DONTCARE)
-#define P_NAND_WE (P_DONTCARE)
-#define P_NAND_RE (P_DONTCARE)
-#define P_NAND_CLE (P_DONTCARE)
-#define P_NAND_ALE (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ports.h b/arch/blackfin/include/asm/mach-bf548/ports.h
deleted file mode 100644
index 50054f3f1994..000000000000
--- a/arch/blackfin/include/asm/mach-bf548/ports.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK 0x00000003
-#define PORT_x_MUX_1_MASK 0x0000000C
-#define PORT_x_MUX_2_MASK 0x00000030
-#define PORT_x_MUX_3_MASK 0x000000C0
-#define PORT_x_MUX_4_MASK 0x00000300
-#define PORT_x_MUX_5_MASK 0x00000C00
-#define PORT_x_MUX_6_MASK 0x00003000
-#define PORT_x_MUX_7_MASK 0x0000C000
-#define PORT_x_MUX_8_MASK 0x00030000
-#define PORT_x_MUX_9_MASK 0x000C0000
-#define PORT_x_MUX_10_MASK 0x00300000
-#define PORT_x_MUX_11_MASK 0x00C00000
-#define PORT_x_MUX_12_MASK 0x03000000
-#define PORT_x_MUX_13_MASK 0x0C000000
-#define PORT_x_MUX_14_MASK 0x30000000
-#define PORT_x_MUX_15_MASK 0xC0000000
-
-#define PORT_x_MUX_FUNC_1 (0x0)
-#define PORT_x_MUX_FUNC_2 (0x1)
-#define PORT_x_MUX_FUNC_3 (0x2)
-#define PORT_x_MUX_FUNC_4 (0x3)
-#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
-#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
-#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
-#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
-#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
-#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
-#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
-#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
-#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
-#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
-#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
-#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
-#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
-#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
-#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
-#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
-#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
-#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
-#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
-#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
-#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
-#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
-#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
-#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
-#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
-#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
-#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
-#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
-#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
-#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
-#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
-#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
-
-#include "../mach-common/bits/ports-a.h"
-#include "../mach-common/bits/ports-b.h"
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-#include "../mach-common/bits/ports-i.h"
-#include "../mach-common/bits/ports-j.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
deleted file mode 100644
index 211ba884edc9..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
+++ /dev/null
@@ -1,1410 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF561_proc__
-#define __BFIN_CDEF_ADSP_BF561_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val)
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val)
-#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val)
-#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val)
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
-#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
-#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
-#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
-#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
-#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
-#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
-#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
-#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
-#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
-#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
-#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
-#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
-#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
-#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
-#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
-#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val)
-#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val)
-#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val)
-#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val)
-#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val)
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val)
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val)
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
-#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val)
-#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
-#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val)
-#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0)
-#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0, val)
-#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1)
-#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1, val)
-#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0)
-#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0, val)
-#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1)
-#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1, val)
-#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0)
-#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0, val)
-#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1)
-#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1, val)
-#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0)
-#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0, val)
-#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1)
-#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1, val)
-#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2)
-#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2, val)
-#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3)
-#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3, val)
-#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4)
-#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4, val)
-#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5)
-#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5, val)
-#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6)
-#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6, val)
-#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
-#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val)
-#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
-#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val)
-#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val)
-#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0, val)
-#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1, val)
-#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0, val)
-#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1, val)
-#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0, val)
-#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1, val)
-#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0, val)
-#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1, val)
-#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2, val)
-#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3, val)
-#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4, val)
-#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5, val)
-#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6, val)
-#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7, val)
-#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL, val)
-#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS, val)
-#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY, val)
-#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT, val)
-#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME, val)
-#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL, val)
-#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS, val)
-#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY, val)
-#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT, val)
-#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME, val)
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
-#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR, val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
-#define bfin_read_UART_GBL() bfin_read16(UART_GBL)
-#define bfin_write_UART_GBL(val) bfin_write16(UART_GBL, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
deleted file mode 100644
index 8fd552f2a12f..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h
+++ /dev/null
@@ -1,719 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF561_proc__
-#define __BFIN_DEF_ADSP_BF561_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL 0xFFC00000
-#define PLL_DIV 0xFFC00004
-#define VR_CTL 0xFFC00008
-#define PLL_STAT 0xFFC0000C
-#define PLL_LOCKCNT 0xFFC00010
-#define CHIPID 0xFFC00014
-#define SPI_CTL 0xFFC00500
-#define SPI_FLG 0xFFC00504
-#define SPI_STAT 0xFFC00508
-#define SPI_TDBR 0xFFC0050C
-#define SPI_RDBR 0xFFC00510
-#define SPI_BAUD 0xFFC00514
-#define SPI_SHADOW 0xFFC00518
-#define WDOGA_CTL 0xFFC00200
-#define WDOGA_CNT 0xFFC00204
-#define WDOGA_STAT 0xFFC00208
-#define WDOGB_CTL 0xFFC01200
-#define WDOGB_CNT 0xFFC01204
-#define WDOGB_STAT 0xFFC01208
-#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */
-#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA1_0_CONFIG 0xFFC01C08
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00
-#define DMA1_0_START_ADDR 0xFFC01C04
-#define DMA1_0_X_COUNT 0xFFC01C10
-#define DMA1_0_Y_COUNT 0xFFC01C18
-#define DMA1_0_X_MODIFY 0xFFC01C14
-#define DMA1_0_Y_MODIFY 0xFFC01C1C
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20
-#define DMA1_0_CURR_ADDR 0xFFC01C24
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38
-#define DMA1_0_IRQ_STATUS 0xFFC01C28
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C
-#define DMA1_1_CONFIG 0xFFC01C48
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40
-#define DMA1_1_START_ADDR 0xFFC01C44
-#define DMA1_1_X_COUNT 0xFFC01C50
-#define DMA1_1_Y_COUNT 0xFFC01C58
-#define DMA1_1_X_MODIFY 0xFFC01C54
-#define DMA1_1_Y_MODIFY 0xFFC01C5C
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60
-#define DMA1_1_CURR_ADDR 0xFFC01C64
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78
-#define DMA1_1_IRQ_STATUS 0xFFC01C68
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C
-#define DMA1_2_CONFIG 0xFFC01C88
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80
-#define DMA1_2_START_ADDR 0xFFC01C84
-#define DMA1_2_X_COUNT 0xFFC01C90
-#define DMA1_2_Y_COUNT 0xFFC01C98
-#define DMA1_2_X_MODIFY 0xFFC01C94
-#define DMA1_2_Y_MODIFY 0xFFC01C9C
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0
-#define DMA1_2_CURR_ADDR 0xFFC01CA4
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC
-#define DMA1_3_CONFIG 0xFFC01CC8
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0
-#define DMA1_3_START_ADDR 0xFFC01CC4
-#define DMA1_3_X_COUNT 0xFFC01CD0
-#define DMA1_3_Y_COUNT 0xFFC01CD8
-#define DMA1_3_X_MODIFY 0xFFC01CD4
-#define DMA1_3_Y_MODIFY 0xFFC01CDC
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0
-#define DMA1_3_CURR_ADDR 0xFFC01CE4
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC
-#define DMA1_4_CONFIG 0xFFC01D08
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00
-#define DMA1_4_START_ADDR 0xFFC01D04
-#define DMA1_4_X_COUNT 0xFFC01D10
-#define DMA1_4_Y_COUNT 0xFFC01D18
-#define DMA1_4_X_MODIFY 0xFFC01D14
-#define DMA1_4_Y_MODIFY 0xFFC01D1C
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20
-#define DMA1_4_CURR_ADDR 0xFFC01D24
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38
-#define DMA1_4_IRQ_STATUS 0xFFC01D28
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C
-#define DMA1_5_CONFIG 0xFFC01D48
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40
-#define DMA1_5_START_ADDR 0xFFC01D44
-#define DMA1_5_X_COUNT 0xFFC01D50
-#define DMA1_5_Y_COUNT 0xFFC01D58
-#define DMA1_5_X_MODIFY 0xFFC01D54
-#define DMA1_5_Y_MODIFY 0xFFC01D5C
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60
-#define DMA1_5_CURR_ADDR 0xFFC01D64
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78
-#define DMA1_5_IRQ_STATUS 0xFFC01D68
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C
-#define DMA1_6_CONFIG 0xFFC01D88
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80
-#define DMA1_6_START_ADDR 0xFFC01D84
-#define DMA1_6_X_COUNT 0xFFC01D90
-#define DMA1_6_Y_COUNT 0xFFC01D98
-#define DMA1_6_X_MODIFY 0xFFC01D94
-#define DMA1_6_Y_MODIFY 0xFFC01D9C
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0
-#define DMA1_6_CURR_ADDR 0xFFC01DA4
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC
-#define DMA1_7_CONFIG 0xFFC01DC8
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0
-#define DMA1_7_START_ADDR 0xFFC01DC4
-#define DMA1_7_X_COUNT 0xFFC01DD0
-#define DMA1_7_Y_COUNT 0xFFC01DD8
-#define DMA1_7_X_MODIFY 0xFFC01DD4
-#define DMA1_7_Y_MODIFY 0xFFC01DDC
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0
-#define DMA1_7_CURR_ADDR 0xFFC01DE4
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC
-#define DMA1_8_CONFIG 0xFFC01E08
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00
-#define DMA1_8_START_ADDR 0xFFC01E04
-#define DMA1_8_X_COUNT 0xFFC01E10
-#define DMA1_8_Y_COUNT 0xFFC01E18
-#define DMA1_8_X_MODIFY 0xFFC01E14
-#define DMA1_8_Y_MODIFY 0xFFC01E1C
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20
-#define DMA1_8_CURR_ADDR 0xFFC01E24
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38
-#define DMA1_8_IRQ_STATUS 0xFFC01E28
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C
-#define DMA1_9_CONFIG 0xFFC01E48
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40
-#define DMA1_9_START_ADDR 0xFFC01E44
-#define DMA1_9_X_COUNT 0xFFC01E50
-#define DMA1_9_Y_COUNT 0xFFC01E58
-#define DMA1_9_X_MODIFY 0xFFC01E54
-#define DMA1_9_Y_MODIFY 0xFFC01E5C
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60
-#define DMA1_9_CURR_ADDR 0xFFC01E64
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78
-#define DMA1_9_IRQ_STATUS 0xFFC01E68
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C
-#define DMA1_10_CONFIG 0xFFC01E88
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80
-#define DMA1_10_START_ADDR 0xFFC01E84
-#define DMA1_10_X_COUNT 0xFFC01E90
-#define DMA1_10_Y_COUNT 0xFFC01E98
-#define DMA1_10_X_MODIFY 0xFFC01E94
-#define DMA1_10_Y_MODIFY 0xFFC01E9C
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0
-#define DMA1_10_CURR_ADDR 0xFFC01EA4
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC
-#define DMA1_11_CONFIG 0xFFC01EC8
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0
-#define DMA1_11_START_ADDR 0xFFC01EC4
-#define DMA1_11_X_COUNT 0xFFC01ED0
-#define DMA1_11_Y_COUNT 0xFFC01ED8
-#define DMA1_11_X_MODIFY 0xFFC01ED4
-#define DMA1_11_Y_MODIFY 0xFFC01EDC
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0
-#define DMA1_11_CURR_ADDR 0xFFC01EE4
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC
-#define DMA2_TC_PER 0xFFC00B0C
-#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */
-#define DMA2_0_CONFIG 0xFFC00C08
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00
-#define DMA2_0_START_ADDR 0xFFC00C04
-#define DMA2_0_X_COUNT 0xFFC00C10
-#define DMA2_0_Y_COUNT 0xFFC00C18
-#define DMA2_0_X_MODIFY 0xFFC00C14
-#define DMA2_0_Y_MODIFY 0xFFC00C1C
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20
-#define DMA2_0_CURR_ADDR 0xFFC00C24
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38
-#define DMA2_0_IRQ_STATUS 0xFFC00C28
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C
-#define DMA2_1_CONFIG 0xFFC00C48
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40
-#define DMA2_1_START_ADDR 0xFFC00C44
-#define DMA2_1_X_COUNT 0xFFC00C50
-#define DMA2_1_Y_COUNT 0xFFC00C58
-#define DMA2_1_X_MODIFY 0xFFC00C54
-#define DMA2_1_Y_MODIFY 0xFFC00C5C
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60
-#define DMA2_1_CURR_ADDR 0xFFC00C64
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78
-#define DMA2_1_IRQ_STATUS 0xFFC00C68
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C
-#define DMA2_2_CONFIG 0xFFC00C88
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80
-#define DMA2_2_START_ADDR 0xFFC00C84
-#define DMA2_2_X_COUNT 0xFFC00C90
-#define DMA2_2_Y_COUNT 0xFFC00C98
-#define DMA2_2_X_MODIFY 0xFFC00C94
-#define DMA2_2_Y_MODIFY 0xFFC00C9C
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0
-#define DMA2_2_CURR_ADDR 0xFFC00CA4
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC
-#define DMA2_3_CONFIG 0xFFC00CC8
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0
-#define DMA2_3_START_ADDR 0xFFC00CC4
-#define DMA2_3_X_COUNT 0xFFC00CD0
-#define DMA2_3_Y_COUNT 0xFFC00CD8
-#define DMA2_3_X_MODIFY 0xFFC00CD4
-#define DMA2_3_Y_MODIFY 0xFFC00CDC
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0
-#define DMA2_3_CURR_ADDR 0xFFC00CE4
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC
-#define DMA2_4_CONFIG 0xFFC00D08
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00
-#define DMA2_4_START_ADDR 0xFFC00D04
-#define DMA2_4_X_COUNT 0xFFC00D10
-#define DMA2_4_Y_COUNT 0xFFC00D18
-#define DMA2_4_X_MODIFY 0xFFC00D14
-#define DMA2_4_Y_MODIFY 0xFFC00D1C
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20
-#define DMA2_4_CURR_ADDR 0xFFC00D24
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38
-#define DMA2_4_IRQ_STATUS 0xFFC00D28
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C
-#define DMA2_5_CONFIG 0xFFC00D48
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40
-#define DMA2_5_START_ADDR 0xFFC00D44
-#define DMA2_5_X_COUNT 0xFFC00D50
-#define DMA2_5_Y_COUNT 0xFFC00D58
-#define DMA2_5_X_MODIFY 0xFFC00D54
-#define DMA2_5_Y_MODIFY 0xFFC00D5C
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60
-#define DMA2_5_CURR_ADDR 0xFFC00D64
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78
-#define DMA2_5_IRQ_STATUS 0xFFC00D68
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C
-#define DMA2_6_CONFIG 0xFFC00D88
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80
-#define DMA2_6_START_ADDR 0xFFC00D84
-#define DMA2_6_X_COUNT 0xFFC00D90
-#define DMA2_6_Y_COUNT 0xFFC00D98
-#define DMA2_6_X_MODIFY 0xFFC00D94
-#define DMA2_6_Y_MODIFY 0xFFC00D9C
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0
-#define DMA2_6_CURR_ADDR 0xFFC00DA4
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC
-#define DMA2_7_CONFIG 0xFFC00DC8
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0
-#define DMA2_7_START_ADDR 0xFFC00DC4
-#define DMA2_7_X_COUNT 0xFFC00DD0
-#define DMA2_7_Y_COUNT 0xFFC00DD8
-#define DMA2_7_X_MODIFY 0xFFC00DD4
-#define DMA2_7_Y_MODIFY 0xFFC00DDC
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0
-#define DMA2_7_CURR_ADDR 0xFFC00DE4
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC
-#define DMA2_8_CONFIG 0xFFC00E08
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00
-#define DMA2_8_START_ADDR 0xFFC00E04
-#define DMA2_8_X_COUNT 0xFFC00E10
-#define DMA2_8_Y_COUNT 0xFFC00E18
-#define DMA2_8_X_MODIFY 0xFFC00E14
-#define DMA2_8_Y_MODIFY 0xFFC00E1C
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20
-#define DMA2_8_CURR_ADDR 0xFFC00E24
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38
-#define DMA2_8_IRQ_STATUS 0xFFC00E28
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C
-#define DMA2_9_CONFIG 0xFFC00E48
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40
-#define DMA2_9_START_ADDR 0xFFC00E44
-#define DMA2_9_X_COUNT 0xFFC00E50
-#define DMA2_9_Y_COUNT 0xFFC00E58
-#define DMA2_9_X_MODIFY 0xFFC00E54
-#define DMA2_9_Y_MODIFY 0xFFC00E5C
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60
-#define DMA2_9_CURR_ADDR 0xFFC00E64
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78
-#define DMA2_9_IRQ_STATUS 0xFFC00E68
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C
-#define DMA2_10_CONFIG 0xFFC00E88
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80
-#define DMA2_10_START_ADDR 0xFFC00E84
-#define DMA2_10_X_COUNT 0xFFC00E90
-#define DMA2_10_Y_COUNT 0xFFC00E98
-#define DMA2_10_X_MODIFY 0xFFC00E94
-#define DMA2_10_Y_MODIFY 0xFFC00E9C
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0
-#define DMA2_10_CURR_ADDR 0xFFC00EA4
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC
-#define DMA2_11_CONFIG 0xFFC00EC8
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0
-#define DMA2_11_START_ADDR 0xFFC00EC4
-#define DMA2_11_X_COUNT 0xFFC00ED0
-#define DMA2_11_Y_COUNT 0xFFC00ED8
-#define DMA2_11_X_MODIFY 0xFFC00ED4
-#define DMA2_11_Y_MODIFY 0xFFC00EDC
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0
-#define DMA2_11_CURR_ADDR 0xFFC00EE4
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC
-#define IMDMA_S0_CONFIG 0xFFC01848
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840
-#define IMDMA_S0_START_ADDR 0xFFC01844
-#define IMDMA_S0_X_COUNT 0xFFC01850
-#define IMDMA_S0_Y_COUNT 0xFFC01858
-#define IMDMA_S0_X_MODIFY 0xFFC01854
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860
-#define IMDMA_S0_CURR_ADDR 0xFFC01864
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868
-#define IMDMA_D0_CONFIG 0xFFC01808
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800
-#define IMDMA_D0_START_ADDR 0xFFC01804
-#define IMDMA_D0_X_COUNT 0xFFC01810
-#define IMDMA_D0_Y_COUNT 0xFFC01818
-#define IMDMA_D0_X_MODIFY 0xFFC01814
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820
-#define IMDMA_D0_CURR_ADDR 0xFFC01824
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828
-#define IMDMA_S1_CONFIG 0xFFC018C8
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0
-#define IMDMA_S1_START_ADDR 0xFFC018C4
-#define IMDMA_S1_X_COUNT 0xFFC018D0
-#define IMDMA_S1_Y_COUNT 0xFFC018D8
-#define IMDMA_S1_X_MODIFY 0xFFC018D4
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8
-#define IMDMA_D1_CONFIG 0xFFC01888
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880
-#define IMDMA_D1_START_ADDR 0xFFC01884
-#define IMDMA_D1_X_COUNT 0xFFC01890
-#define IMDMA_D1_Y_COUNT 0xFFC01898
-#define IMDMA_D1_X_MODIFY 0xFFC01894
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8
-#define MDMA1_S0_CONFIG 0xFFC01F48
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40
-#define MDMA1_S0_START_ADDR 0xFFC01F44
-#define MDMA1_S0_X_COUNT 0xFFC01F50
-#define MDMA1_S0_Y_COUNT 0xFFC01F58
-#define MDMA1_S0_X_MODIFY 0xFFC01F54
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C
-#define MDMA1_D0_CONFIG 0xFFC01F08
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00
-#define MDMA1_D0_START_ADDR 0xFFC01F04
-#define MDMA1_D0_X_COUNT 0xFFC01F10
-#define MDMA1_D0_Y_COUNT 0xFFC01F18
-#define MDMA1_D0_X_MODIFY 0xFFC01F14
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C
-#define MDMA1_S1_CONFIG 0xFFC01FC8
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0
-#define MDMA1_S1_START_ADDR 0xFFC01FC4
-#define MDMA1_S1_X_COUNT 0xFFC01FD0
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC
-#define MDMA1_D1_CONFIG 0xFFC01F88
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80
-#define MDMA1_D1_START_ADDR 0xFFC01F84
-#define MDMA1_D1_X_COUNT 0xFFC01F90
-#define MDMA1_D1_Y_COUNT 0xFFC01F98
-#define MDMA1_D1_X_MODIFY 0xFFC01F94
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC
-#define MDMA2_S0_CONFIG 0xFFC00F48
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40
-#define MDMA2_S0_START_ADDR 0xFFC00F44
-#define MDMA2_S0_X_COUNT 0xFFC00F50
-#define MDMA2_S0_Y_COUNT 0xFFC00F58
-#define MDMA2_S0_X_MODIFY 0xFFC00F54
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C
-#define MDMA2_D0_CONFIG 0xFFC00F08
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00
-#define MDMA2_D0_START_ADDR 0xFFC00F04
-#define MDMA2_D0_X_COUNT 0xFFC00F10
-#define MDMA2_D0_Y_COUNT 0xFFC00F18
-#define MDMA2_D0_X_MODIFY 0xFFC00F14
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C
-#define MDMA2_S1_CONFIG 0xFFC00FC8
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0
-#define MDMA2_S1_START_ADDR 0xFFC00FC4
-#define MDMA2_S1_X_COUNT 0xFFC00FD0
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC
-#define MDMA2_D1_CONFIG 0xFFC00F88
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80
-#define MDMA2_D1_START_ADDR 0xFFC00F84
-#define MDMA2_D1_X_COUNT 0xFFC00F90
-#define MDMA2_D1_Y_COUNT 0xFFC00F98
-#define MDMA2_D1_X_MODIFY 0xFFC00F94
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC
-#define TIMER0_CONFIG 0xFFC00600
-#define TIMER0_COUNTER 0xFFC00604
-#define TIMER0_PERIOD 0xFFC00608
-#define TIMER0_WIDTH 0xFFC0060C
-#define TIMER1_CONFIG 0xFFC00610
-#define TIMER1_COUNTER 0xFFC00614
-#define TIMER1_PERIOD 0xFFC00618
-#define TIMER1_WIDTH 0xFFC0061C
-#define TIMER2_CONFIG 0xFFC00620
-#define TIMER2_COUNTER 0xFFC00624
-#define TIMER2_PERIOD 0xFFC00628
-#define TIMER2_WIDTH 0xFFC0062C
-#define TIMER3_CONFIG 0xFFC00630
-#define TIMER3_COUNTER 0xFFC00634
-#define TIMER3_PERIOD 0xFFC00638
-#define TIMER3_WIDTH 0xFFC0063C
-#define TIMER4_CONFIG 0xFFC00640
-#define TIMER4_COUNTER 0xFFC00644
-#define TIMER4_PERIOD 0xFFC00648
-#define TIMER4_WIDTH 0xFFC0064C
-#define TIMER5_CONFIG 0xFFC00650
-#define TIMER5_COUNTER 0xFFC00654
-#define TIMER5_PERIOD 0xFFC00658
-#define TIMER5_WIDTH 0xFFC0065C
-#define TIMER6_CONFIG 0xFFC00660
-#define TIMER6_COUNTER 0xFFC00664
-#define TIMER6_PERIOD 0xFFC00668
-#define TIMER6_WIDTH 0xFFC0066C
-#define TIMER7_CONFIG 0xFFC00670
-#define TIMER7_COUNTER 0xFFC00674
-#define TIMER7_PERIOD 0xFFC00678
-#define TIMER7_WIDTH 0xFFC0067C
-#define TIMER8_CONFIG 0xFFC01600
-#define TIMER8_COUNTER 0xFFC01604
-#define TIMER8_PERIOD 0xFFC01608
-#define TIMER8_WIDTH 0xFFC0160C
-#define TIMER9_CONFIG 0xFFC01610
-#define TIMER9_COUNTER 0xFFC01614
-#define TIMER9_PERIOD 0xFFC01618
-#define TIMER9_WIDTH 0xFFC0161C
-#define TIMER10_CONFIG 0xFFC01620
-#define TIMER10_COUNTER 0xFFC01624
-#define TIMER10_PERIOD 0xFFC01628
-#define TIMER10_WIDTH 0xFFC0162C
-#define TIMER11_CONFIG 0xFFC01630
-#define TIMER11_COUNTER 0xFFC01634
-#define TIMER11_PERIOD 0xFFC01638
-#define TIMER11_WIDTH 0xFFC0163C
-#define TMRS4_ENABLE 0xFFC01640
-#define TMRS4_DISABLE 0xFFC01644
-#define TMRS4_STATUS 0xFFC01648
-#define TMRS8_ENABLE 0xFFC00680
-#define TMRS8_DISABLE 0xFFC00684
-#define TMRS8_STATUS 0xFFC00688
-#define FIO0_FLAG_D 0xFFC00700
-#define FIO0_FLAG_C 0xFFC00704
-#define FIO0_FLAG_S 0xFFC00708
-#define FIO0_FLAG_T 0xFFC0070C
-#define FIO0_MASKA_D 0xFFC00710
-#define FIO0_MASKA_C 0xFFC00714
-#define FIO0_MASKA_S 0xFFC00718
-#define FIO0_MASKA_T 0xFFC0071C
-#define FIO0_MASKB_D 0xFFC00720
-#define FIO0_MASKB_C 0xFFC00724
-#define FIO0_MASKB_S 0xFFC00728
-#define FIO0_MASKB_T 0xFFC0072C
-#define FIO0_DIR 0xFFC00730
-#define FIO0_POLAR 0xFFC00734
-#define FIO0_EDGE 0xFFC00738
-#define FIO0_BOTH 0xFFC0073C
-#define FIO0_INEN 0xFFC00740
-#define FIO1_FLAG_D 0xFFC01500
-#define FIO1_FLAG_C 0xFFC01504
-#define FIO1_FLAG_S 0xFFC01508
-#define FIO1_FLAG_T 0xFFC0150C
-#define FIO1_MASKA_D 0xFFC01510
-#define FIO1_MASKA_C 0xFFC01514
-#define FIO1_MASKA_S 0xFFC01518
-#define FIO1_MASKA_T 0xFFC0151C
-#define FIO1_MASKB_D 0xFFC01520
-#define FIO1_MASKB_C 0xFFC01524
-#define FIO1_MASKB_S 0xFFC01528
-#define FIO1_MASKB_T 0xFFC0152C
-#define FIO1_DIR 0xFFC01530
-#define FIO1_POLAR 0xFFC01534
-#define FIO1_EDGE 0xFFC01538
-#define FIO1_BOTH 0xFFC0153C
-#define FIO1_INEN 0xFFC01540
-#define FIO2_FLAG_D 0xFFC01700
-#define FIO2_FLAG_C 0xFFC01704
-#define FIO2_FLAG_S 0xFFC01708
-#define FIO2_FLAG_T 0xFFC0170C
-#define FIO2_MASKA_D 0xFFC01710
-#define FIO2_MASKA_C 0xFFC01714
-#define FIO2_MASKA_S 0xFFC01718
-#define FIO2_MASKA_T 0xFFC0171C
-#define FIO2_MASKB_D 0xFFC01720
-#define FIO2_MASKB_C 0xFFC01724
-#define FIO2_MASKB_S 0xFFC01728
-#define FIO2_MASKB_T 0xFFC0172C
-#define FIO2_DIR 0xFFC01730
-#define FIO2_POLAR 0xFFC01734
-#define FIO2_EDGE 0xFFC01738
-#define FIO2_BOTH 0xFFC0173C
-#define FIO2_INEN 0xFFC01740
-#define SPORT0_TCR1 0xFFC00800
-#define SPORT0_TCR2 0xFFC00804
-#define SPORT0_TCLKDIV 0xFFC00808
-#define SPORT0_TFSDIV 0xFFC0080C
-#define SPORT0_TX 0xFFC00810
-#define SPORT0_RX 0xFFC00818
-#define SPORT0_RCR1 0xFFC00820
-#define SPORT0_RCR2 0xFFC00824
-#define SPORT0_RCLKDIV 0xFFC00828
-#define SPORT0_RFSDIV 0xFFC0082C
-#define SPORT0_STAT 0xFFC00830
-#define SPORT0_CHNL 0xFFC00834
-#define SPORT0_MCMC1 0xFFC00838
-#define SPORT0_MCMC2 0xFFC0083C
-#define SPORT0_MTCS0 0xFFC00840
-#define SPORT0_MTCS1 0xFFC00844
-#define SPORT0_MTCS2 0xFFC00848
-#define SPORT0_MTCS3 0xFFC0084C
-#define SPORT0_MRCS0 0xFFC00850
-#define SPORT0_MRCS1 0xFFC00854
-#define SPORT0_MRCS2 0xFFC00858
-#define SPORT0_MRCS3 0xFFC0085C
-#define SPORT1_TCR1 0xFFC00900
-#define SPORT1_TCR2 0xFFC00904
-#define SPORT1_TCLKDIV 0xFFC00908
-#define SPORT1_TFSDIV 0xFFC0090C
-#define SPORT1_TX 0xFFC00910
-#define SPORT1_RX 0xFFC00918
-#define SPORT1_RCR1 0xFFC00920
-#define SPORT1_RCR2 0xFFC00924
-#define SPORT1_RCLKDIV 0xFFC00928
-#define SPORT1_RFSDIV 0xFFC0092C
-#define SPORT1_STAT 0xFFC00930
-#define SPORT1_CHNL 0xFFC00934
-#define SPORT1_MCMC1 0xFFC00938
-#define SPORT1_MCMC2 0xFFC0093C
-#define SPORT1_MTCS0 0xFFC00940
-#define SPORT1_MTCS1 0xFFC00944
-#define SPORT1_MTCS2 0xFFC00948
-#define SPORT1_MTCS3 0xFFC0094C
-#define SPORT1_MRCS0 0xFFC00950
-#define SPORT1_MRCS1 0xFFC00954
-#define SPORT1_MRCS2 0xFFC00958
-#define SPORT1_MRCS3 0xFFC0095C
-#define SICA_SWRST 0xFFC00100
-#define SICA_SYSCR 0xFFC00104
-#define SICA_RVECT 0xFFC00108
-#define SICA_IMASK0 0xFFC0010C
-#define SICA_IMASK1 0xFFC00110
-#define SICA_ISR0 0xFFC00114
-#define SICA_ISR1 0xFFC00118
-#define SICA_IWR0 0xFFC0011C
-#define SICA_IWR1 0xFFC00120
-#define SICA_IAR0 0xFFC00124
-#define SICA_IAR1 0xFFC00128
-#define SICA_IAR2 0xFFC0012C
-#define SICA_IAR3 0xFFC00130
-#define SICA_IAR4 0xFFC00134
-#define SICA_IAR5 0xFFC00138
-#define SICA_IAR6 0xFFC0013C
-#define SICA_IAR7 0xFFC00140
-#define SICB_SWRST 0xFFC01100
-#define SICB_SYSCR 0xFFC01104
-#define SICB_RVECT 0xFFC01108
-#define SICB_IMASK0 0xFFC0110C
-#define SICB_IMASK1 0xFFC01110
-#define SICB_ISR0 0xFFC01114
-#define SICB_ISR1 0xFFC01118
-#define SICB_IWR0 0xFFC0111C
-#define SICB_IWR1 0xFFC01120
-#define SICB_IAR0 0xFFC01124
-#define SICB_IAR1 0xFFC01128
-#define SICB_IAR2 0xFFC0112C
-#define SICB_IAR3 0xFFC01130
-#define SICB_IAR4 0xFFC01134
-#define SICB_IAR5 0xFFC01138
-#define SICB_IAR6 0xFFC0113C
-#define SICB_IAR7 0xFFC01140
-#define PPI0_CONTROL 0xFFC01000
-#define PPI0_STATUS 0xFFC01004
-#define PPI0_DELAY 0xFFC0100C
-#define PPI0_COUNT 0xFFC01008
-#define PPI0_FRAME 0xFFC01010
-#define PPI1_CONTROL 0xFFC01300
-#define PPI1_STATUS 0xFFC01304
-#define PPI1_DELAY 0xFFC0130C
-#define PPI1_COUNT 0xFFC01308
-#define PPI1_FRAME 0xFFC01310
-#define UART_THR 0xFFC00400
-#define UART_RBR 0xFFC00400
-#define UART0_RBR UART_RBR
-#define UART_DLL 0xFFC00400
-#define UART_DLH 0xFFC00404
-#define UART_IER 0xFFC00404
-#define UART_IIR 0xFFC00408
-#define UART_LCR 0xFFC0040C
-#define UART_MCR 0xFFC00410
-#define UART_LSR 0xFFC00414
-#define UART_MSR 0xFFC00418
-#define UART_SCR 0xFFC0041C
-#define UART_GCTL 0xFFC00424
-#define UART_GBL 0xFFC00424
-#define EBIU_AMGCTL 0xFFC00A00
-#define EBIU_AMBCTL0 0xFFC00A04
-#define EBIU_AMBCTL1 0xFFC00A08
-#define EBIU_SDGCTL 0xFFC00A10
-#define EBIU_SDBCTL 0xFFC00A14
-#define EBIU_SDRRC 0xFFC00A18
-#define EBIU_SDSTAT 0xFFC00A1C
-
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#define COREB_L1_CODE_START 0xFF600000
-
-#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h
deleted file mode 100644
index b27173cf03a8..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/anomaly.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate@Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event@Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up@CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h
deleted file mode 100644
index 08e37e5e16de..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/def_local.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#define SWRST SICA_SWRST
-#define SYSCR SICA_SYSCR
-#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
-#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
-
-#define WDOG_CNT WDOGA_CNT
-#define WDOG_CTL WDOGA_CTL
-#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
-#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
-#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
-
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF561_FAMILY 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf561/gpio.h b/arch/blackfin/include/asm/mach-bf561/gpio.h
deleted file mode 100644
index 4f8aa5d08802..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/gpio.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PF16 16
-#define GPIO_PF17 17
-#define GPIO_PF18 18
-#define GPIO_PF19 19
-#define GPIO_PF20 20
-#define GPIO_PF21 21
-#define GPIO_PF22 22
-#define GPIO_PF23 23
-#define GPIO_PF24 24
-#define GPIO_PF25 25
-#define GPIO_PF26 26
-#define GPIO_PF27 27
-#define GPIO_PF28 28
-#define GPIO_PF29 29
-#define GPIO_PF30 30
-#define GPIO_PF31 31
-#define GPIO_PF32 32
-#define GPIO_PF33 33
-#define GPIO_PF34 34
-#define GPIO_PF35 35
-#define GPIO_PF36 36
-#define GPIO_PF37 37
-#define GPIO_PF38 38
-#define GPIO_PF39 39
-#define GPIO_PF40 40
-#define GPIO_PF41 41
-#define GPIO_PF42 42
-#define GPIO_PF43 43
-#define GPIO_PF44 44
-#define GPIO_PF45 45
-#define GPIO_PF46 46
-#define GPIO_PF47 47
-
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/portmux.h b/arch/blackfin/include/asm/mach-bf561/portmux.h
deleted file mode 100644
index 2339ffd0dde8..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/portmux.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DONTCARE)
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DONTCARE)
-#define P_PPI0_D5 (P_DONTCARE)
-#define P_PPI0_D6 (P_DONTCARE)
-#define P_PPI0_D7 (P_DONTCARE)
-#define P_PPI1_CLK (P_DONTCARE)
-#define P_PPI1_FS1 (P_DONTCARE)
-#define P_PPI1_FS2 (P_DONTCARE)
-#define P_PPI1_FS3 (P_DONTCARE)
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0 (P_DONTCARE)
-#define P_PPI1_D1 (P_DONTCARE)
-#define P_PPI1_D2 (P_DONTCARE)
-#define P_PPI1_D3 (P_DONTCARE)
-#define P_PPI1_D4 (P_DONTCARE)
-#define P_PPI1_D5 (P_DONTCARE)
-#define P_PPI1_D6 (P_DONTCARE)
-#define P_PPI1_D7 (P_DONTCARE)
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11 (P_DONTCARE)
-#define P_TMR10 (P_DONTCARE)
-#define P_TMR9 (P_DONTCARE)
-#define P_TMR8 (P_DONTCARE)
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf561/ports.h b/arch/blackfin/include/asm/mach-bf561/ports.h
deleted file mode 100644
index 194d4a3eb14b..000000000000
--- a/arch/blackfin/include/asm/mach-bf561/ports.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-f.h"
-
-/* The non-standard PF16+ */
-#define PF16 (1 << 0)
-#define PF17 (1 << 1)
-#define PF18 (1 << 2)
-#define PF19 (1 << 3)
-#define PF20 (1 << 4)
-#define PF21 (1 << 5)
-#define PF22 (1 << 6)
-#define PF23 (1 << 7)
-#define PF24 (1 << 8)
-#define PF25 (1 << 9)
-#define PF26 (1 << 10)
-#define PF27 (1 << 11)
-#define PF28 (1 << 12)
-#define PF29 (1 << 13)
-#define PF30 (1 << 14)
-#define PF31 (1 << 15)
-#define PF32 (1 << 0)
-#define PF33 (1 << 1)
-#define PF34 (1 << 2)
-#define PF35 (1 << 3)
-#define PF36 (1 << 4)
-#define PF37 (1 << 5)
-#define PF38 (1 << 6)
-#define PF39 (1 << 7)
-#define PF40 (1 << 8)
-#define PF41 (1 << 9)
-#define PF42 (1 << 10)
-#define PF43 (1 << 11)
-#define PF44 (1 << 12)
-#define PF45 (1 << 13)
-#define PF46 (1 << 14)
-#define PF47 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
deleted file mode 100644
index c5900319f226..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF609_proc__
-#define __BFIN_CDEF_ADSP_BF609_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT)
-#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL)
-#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL)
-#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val)
-#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV)
-#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val)
-
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-#define bfin_read_SEC_CCTL() bfin_read32(SEC0_CCTL0)
-#define bfin_write_SEC_CCTL(val) bfin_write32(SEC0_CCTL0, val)
-#define bfin_read_SEC_GCTL() bfin_read32(SEC0_GCTL)
-#define bfin_write_SEC_GCTL(val) bfin_write32(SEC0_GCTL, val)
-
-#define bfin_read_SEC_FCTL() bfin_read32(SEC0_FCTL)
-#define bfin_write_SEC_FCTL(val) bfin_write32(SEC0_FCTL, val)
-#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC0_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC0_SCTL0 \
- + (sid) * 8), val)
-
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read8(USB_DMA_IRQ)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val)
-
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val)
-
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT() bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val) bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK() bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val) bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
deleted file mode 100644
index fd0d86d39e55..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF609_proc__
-#define __BFIN_DEF_ADSP_BF609_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Ack Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Id Register */
-#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Id Register */
-#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Id Register */
-#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Id Register */
-
-#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
-
-#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP 0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */
-#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */
-#define UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */
-#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP 0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */
-#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */
-#define UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */
-
-#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable */
-#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set */
-#define PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear */
-#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control */
-#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable */
-#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set */
-#define PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear */
-#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control */
-#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable */
-#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set */
-#define PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear */
-#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control */
-#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable */
-#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set */
-#define PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear */
-#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control */
-#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable */
-#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set */
-#define PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear */
-#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control */
-#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable */
-#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set */
-#define PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear */
-#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control */
-#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable */
-#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set */
-#define PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear */
-#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control */
-
-#define SMC_GCTL 0xFFC16004 /* SMC Control Register */
-#define SMC_GSTAT 0xFFC16008 /* SMC Status Register */
-#define SMC_B0CTL 0xFFC1600C /* SMC Bank0 Control Register */
-#define SMC_B0TIM 0xFFC16010 /* SMC Bank0 Timing Register */
-#define SMC_B0ETIM 0xFFC16014 /* SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL 0xFFC1601C /* SMC BANK1 Control Register */
-#define SMC_B1TIM 0xFFC16020 /* SMC BANK1 Timing Register */
-#define SMC_B1ETIM 0xFFC16024 /* SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL 0xFFC1602C /* SMC BANK2 Control Register */
-#define SMC_B2TIM 0xFFC16030 /* SMC BANK2 Timing Register */
-#define SMC_B2ETIM 0xFFC16034 /* SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL 0xFFC1603C /* SMC BANK3 Control Register */
-#define SMC_B3TIM 0xFFC16040 /* SMC BANK3 Timing Register */
-#define SMC_B3ETIM 0xFFC16044 /* SMC BANK3 Extended Timing Register */
-
-#define WDOG_CTL 0xFFC17000 /* WDOG0 Control Register */
-#define WDOG_CNT 0xFFC17004 /* WDOG0 Count Register */
-#define WDOG_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
-
-#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
-
-#define SPI0_REGBASE 0xFFC40400 /* SPI0 Base Address */
-#define SPI1_REGBASE 0xFFC40500 /* SPI1 Base Address */
-
-#define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
-#define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */
-#define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value */
-#define DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment */
-#define DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Desc Pointer */
-#define DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */
-#define DMA10_STAT 0xFFC05030 /* DMA10 Status Register */
-#define DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/
-#define DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Curr Row Count (2D only) */
-#define DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/
-
-#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
-#define DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Desc */
-#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
-#define DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Desc */
-
-#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define SEC0_CCTL0 0xFFCA4400 /* SEC0 Core Control Register n */
-#define SEC0_CCTL1 0xFFCA4440 /* SEC0 Core Control Register n */
-#define SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */
-#define SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */
-#define SEC0_SCTL0 0xFFCA4800 /* SEC0 IRQ Source Control Register n */
-
-#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS 0xFFCA6010 /* RCU0 Sys Interface Disable Register */
-#define RCU0_SISTAT 0xFFCA6014 /* RCU0 Sys Interface Status Register */
-#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
-
-#define CGU_CTL 0xFFCA8000 /* CGU0 Control Register */
-#define CGU_STAT 0xFFCA8004 /* CGU0 Status Register */
-#define CGU_DIV 0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable */
-#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable */
-#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */
-#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable */
-#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
-
-#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode*/
-#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
-#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
-#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
-#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE 0x8000
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE 0x4000
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */
-#define L1_INST_SRAM_SIZE 0x8000
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#define COREB_L1_CODE_START 0xFF600000
-
-#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/anomaly.h b/arch/blackfin/include/asm/mach-bf609/anomaly.h
deleted file mode 100644
index 0a70f082afca..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/anomaly.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */
-#define ANOMALY_16000021 (1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (1)
-/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */
-#define ANOMALY_16000027 (1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h
deleted file mode 100644
index d4250e6f99c3..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/def_local.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF60x 1 /* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf609/gpio.h b/arch/blackfin/include/asm/mach-bf609/gpio.h
deleted file mode 100644
index e297bcc8330c..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/gpio.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46
-#define GPIO_PC15 47
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned long port_fer;
- unsigned long port_fer_set;
- unsigned long port_fer_clear;
- unsigned long data;
- unsigned long data_set;
- unsigned long data_clear;
- unsigned long dir;
- unsigned long dir_set;
- unsigned long dir_clear;
- unsigned long inen;
- unsigned long inen_set;
- unsigned long inen_clear;
- unsigned long port_mux;
- unsigned long toggle;
- unsigned long polar;
- unsigned long polar_set;
- unsigned long polar_clear;
- unsigned long lock;
- unsigned long spare;
- unsigned long revid;
-};
-
-#endif
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h
deleted file mode 100644
index 757570f2eff6..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/portmux.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_PTP0_PPS, \
- P_PTP1_PPS, \
- P_MII0_MDIO, 0}
-
-#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-
-#define P_RMII1 {\
- P_MII1_ETxD0, \
- P_MII1_ETxD1, \
- P_MII1_ETxEN, \
- P_MII1_ERxD0, \
- P_MII1_ERxD1, \
- P_MII1_ERxER, \
- P_MII1_TxCLK, \
- P_MII1_PHYINT, \
- P_MII1_CRS, \
- P_MII1_MDC, \
- P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-#define P_ABE0 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
-#define P_ABE1 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
-
-/* CAN */
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h
deleted file mode 100644
index b361c7bcbe79..000000000000
--- a/arch/blackfin/include/asm/mach-bf609/ports.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK 0x00000003
-#define PORT_x_MUX_1_MASK 0x0000000C
-#define PORT_x_MUX_2_MASK 0x00000030
-#define PORT_x_MUX_3_MASK 0x000000C0
-#define PORT_x_MUX_4_MASK 0x00000300
-#define PORT_x_MUX_5_MASK 0x00000C00
-#define PORT_x_MUX_6_MASK 0x00003000
-#define PORT_x_MUX_7_MASK 0x0000C000
-#define PORT_x_MUX_8_MASK 0x00030000
-#define PORT_x_MUX_9_MASK 0x000C0000
-#define PORT_x_MUX_10_MASK 0x00300000
-#define PORT_x_MUX_11_MASK 0x00C00000
-#define PORT_x_MUX_12_MASK 0x03000000
-#define PORT_x_MUX_13_MASK 0x0C000000
-#define PORT_x_MUX_14_MASK 0x30000000
-#define PORT_x_MUX_15_MASK 0xC0000000
-
-#define PORT_x_MUX_FUNC_1 (0x0)
-#define PORT_x_MUX_FUNC_2 (0x1)
-#define PORT_x_MUX_FUNC_3 (0x2)
-#define PORT_x_MUX_FUNC_4 (0x3)
-#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
-#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
-#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
-#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
-#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
-#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
-#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
-#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
-#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
-#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
-#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
-#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
-#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
-#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
-#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
-#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
-#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
-#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
-#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
-#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
-#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
-#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
-#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
-#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
-#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
-#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
-#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
-#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
-#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
-#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
-#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
-#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
-
-#include "../mach-common/bits/ports-a.h"
-#include "../mach-common/bits/ports-b.h"
-#include "../mach-common/bits/ports-c.h"
-#include "../mach-common/bits/ports-d.h"
-#include "../mach-common/bits/ports-e.h"
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
deleted file mode 100644
index 3acf94b0bfae..000000000000
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_EDN_core__
-#define __BFIN_CDEF_ADSP_EDN_core__
-
-#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
-#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-
-#define bfin_read_EVT0() bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define bfin_read_EVT1() bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define bfin_read_EVT2() bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define bfin_read_EVT3() bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define bfin_read_EVT4() bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define bfin_read_EVT5() bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define bfin_read_EVT6() bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define bfin_read_EVT7() bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define bfin_read_EVT8() bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define bfin_read_EVT9() bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define bfin_read_EVT10() bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define bfin_read_EVT11() bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define bfin_read_EVT12() bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define bfin_read_EVT13() bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define bfin_read_EVT14() bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define bfin_read_EVT15() bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
-
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF() bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-
-#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val)
-#define bfin_read_WPIA0() bfin_readPTR(WPIA0)
-#define bfin_write_WPIA0(val) bfin_writePTR(WPIA0, val)
-#define bfin_read_WPIA1() bfin_readPTR(WPIA1)
-#define bfin_write_WPIA1(val) bfin_writePTR(WPIA1, val)
-#define bfin_read_WPIA2() bfin_readPTR(WPIA2)
-#define bfin_write_WPIA2(val) bfin_writePTR(WPIA2, val)
-#define bfin_read_WPIA3() bfin_readPTR(WPIA3)
-#define bfin_write_WPIA3(val) bfin_writePTR(WPIA3, val)
-#define bfin_read_WPIA4() bfin_readPTR(WPIA4)
-#define bfin_write_WPIA4(val) bfin_writePTR(WPIA4, val)
-#define bfin_read_WPIA5() bfin_readPTR(WPIA5)
-#define bfin_write_WPIA5(val) bfin_writePTR(WPIA5, val)
-#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val)
-#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val)
-#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val)
-#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val)
-#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val)
-#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val)
-#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val)
-#define bfin_read_WPDA0() bfin_readPTR(WPDA0)
-#define bfin_write_WPDA0(val) bfin_writePTR(WPDA0, val)
-#define bfin_read_WPDA1() bfin_readPTR(WPDA1)
-#define bfin_write_WPDA1(val) bfin_writePTR(WPDA1, val)
-#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val)
-#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val)
-#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
-
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-
-#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
deleted file mode 100644
index cf28b8ea2770..000000000000
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_EDN_core__
-#define __BFIN_DEF_ADSP_EDN_core__
-
-#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_FAULT_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-
-#define EVT_OVERRIDE 0xFFE02100
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-#define DSPID 0xFFE05000
-#define DBGSTAT 0xFFE05008
-
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-#define WPIACTL 0xFFE07000
-#define WPIA0 0xFFE07040
-#define WPIA1 0xFFE07044
-#define WPIA2 0xFFE07048
-#define WPIA3 0xFFE0704C
-#define WPIA4 0xFFE07050
-#define WPIA5 0xFFE07054
-#define WPIACNT0 0xFFE07080
-#define WPIACNT1 0xFFE07084
-#define WPIACNT2 0xFFE07088
-#define WPIACNT3 0xFFE0708C
-#define WPIACNT4 0xFFE07090
-#define WPIACNT5 0xFFE07094
-#define WPDACTL 0xFFE07100
-#define WPDA0 0xFFE07140
-#define WPDA1 0xFFE07144
-#define WPDACNT0 0xFFE07180
-#define WPDACNT1 0xFFE07184
-#define WPSTAT 0xFFE07200
-
-#define PFCTL 0xFFE08000
-#define PFCNTR0 0xFFE08100
-#define PFCNTR1 0xFFE08104
-
-#endif /* __BFIN_DEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/bootrom.h b/arch/blackfin/include/asm/mach-common/bits/bootrom.h
deleted file mode 100644
index 0e2cacb3937a..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/bootrom.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Boot ROM Entry Points and such
- */
-
-/* These Blackfins all have a Boot ROM that is not reusable (at all):
- * BF531 / BF532 / BF533
- * BF538 / BF539
- * BF561
- * So there is nothing for us to export ;(
- *
- * These Blackfins started to roll with the idea that the Boot ROM can
- * provide useful functions, but still only a few (and not really useful):
- * BF534 / BF536 / BF537
- *
- * Looking forward, Boot ROM's on newer Blackfins have quite a few
- * nice entry points that are usable at runtime and beyond. We'll
- * only define known legacy parts (listed above) and otherwise just
- * assume it's a newer part.
- *
- * These entry points are accomplished by placing a small jump table at
- * the start of the Boot ROM. This way the addresses are fixed forever.
- */
-
-#ifndef __BFIN_PERIPHERAL_BOOTROM__
-#define __BFIN_PERIPHERAL_BOOTROM__
-
-/* All Blackfin's have the Boot ROM entry point@the same address */
-#define _BOOTROM_RESET 0xEF000000
-
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
- defined(__ADSPBF538__) || defined(__ADSPBF539__) || \
- defined(__ADSPBF561__)
-
- /* Nothing to export */
-
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
-
- /* The BF537 family */
-
-#define _BOOTROM_FINAL_INIT 0xEF000002
-/* reserved 0xEF000004 */
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-/* reserved 0xEF00000E */
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-/* reserved 0xEF000016 */
-/* reserved 0xEF000018 */
-
- /* Glue to newer Boot ROMs */
-#define _BOOTROM_MDMA _BOOTROM_DO_MEMORY_DMA
-#define _BOOTROM_MEMBOOT _BOOTROM_BOOT_DXE_FLASH
-#define _BOOTROM_SPIBOOT _BOOTROM_BOOT_DXE_FLASH
-#define _BOOTROM_TWIBOOT _BOOTROM_BOOT_DXE_TWI
-
-#else
-
- /* All the newer Boot ROMs */
-
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_PDMA 0xEF000004
-#define _BOOTROM_MDMA 0xEF000006
-#define _BOOTROM_MEMBOOT 0xEF000008
-#define _BOOTROM_SPIBOOT 0xEF00000A
-#define _BOOTROM_TWIBOOT 0xEF00000C
-/* reserved 0xEF00000E */
-/* reserved 0xEF000010 */
-/* reserved 0xEF000012 */
-/* reserved 0xEF000014 */
-/* reserved 0xEF000016 */
-#define _BOOTROM_OTP_COMMAND 0xEF000018
-#define _BOOTROM_OTP_READ 0xEF00001A
-#define _BOOTROM_OTP_WRITE 0xEF00001C
-#define _BOOTROM_ECC_TABLE 0xEF00001E
-#define _BOOTROM_BOOTKERNEL 0xEF000020
-#define _BOOTROM_GETPORT 0xEF000022
-#define _BOOTROM_NMI 0xEF000024
-#define _BOOTROM_HWERROR 0xEF000026
-#define _BOOTROM_EXCEPTION 0xEF000028
-#define _BOOTROM_CRC32 0xEF000030
-#define _BOOTROM_CRC32POLY 0xEF000032
-#define _BOOTROM_CRC32CALLBACK 0xEF000034
-#define _BOOTROM_CRC32INITCODE 0xEF000036
-#define _BOOTROM_SYSCONTROL 0xEF000038
-#define _BOOTROM_REV 0xEF000040
-#define _BOOTROM_SESR 0xEF001000
-
-#define BOOTROM_FOLLOWS_C_ABI 1
-
-#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
-
-#endif
-
-#ifndef BOOTROM_FOLLOWS_C_ABI
-#define BOOTROM_FOLLOWS_C_ABI 0
-#endif
-#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
-#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
-#endif
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
-#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
-
-#ifndef __ASSEMBLY__
-
-#if BOOTROM_FOLLOWS_C_ABI
-# define BOOTROM_CALLED_FUNC_ATTR
-#else
-# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall))
-#endif
-
-/* Structures for the syscontrol() function */
-typedef struct ADI_SYSCTRL_VALUES {
- uint16_t uwVrCtl;
- uint16_t uwPllCtl;
- uint16_t uwPllDiv;
- uint16_t uwPllLockCnt;
- uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-#ifndef _BOOTROM_SYSCONTROL
-#define _BOOTROM_SYSCONTROL 0
-#endif
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting. The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
- while (1)
- __asm__ __volatile__(
- "sp = %[stack];"
- "jump (%[bfrom_syscontrol]);"
- : : [bfrom_syscontrol] "p"(bfrom_SysControl),
- "q0"(SYSCTRL_SOFTRESET),
- "q1"(0),
- "q2"(NULL),
- [stack] "p"(new_stack)
- );
-}
-
-/* Structures for working with LDRs and boot rom callbacks */
-typedef struct ADI_BOOT_HEADER {
- int32_t dBlockCode;
- void *pTargetAddress;
- int32_t dByteCount;
- int32_t dArgument;
-} ADI_BOOT_HEADER;
-
-typedef struct ADI_BOOT_BUFFER {
- void *pSource;
- int32_t dByteCount;
-} ADI_BOOT_BUFFER;
-
-typedef struct ADI_BOOT_DATA {
- void *pSource;
- void *pDestination;
- int16_t *pControlRegister;
- int16_t *pDmaControlRegister;
- int32_t dControlValue;
- int32_t dByteCount;
- int32_t dFlags;
- int16_t uwDataWidth;
- int16_t uwSrcModifyMult;
- int16_t uwDstModifyMult;
- int16_t uwHwait;
- int16_t uwSsel;
- int16_t uwUserShort;
- int32_t dUserLong;
- int32_t dReserved2;
- void *pErrorFunction;
- void *pLoadFunction;
- void *pCallBackFunction;
- ADI_BOOT_HEADER *pHeader;
- void *pTempBuffer;
- void *pTempCurrent;
- int32_t dTempByteCount;
- int32_t dBlockCount;
- int32_t dClock;
- void *pLogBuffer;
- void *pLogCurrent;
- int32_t dLogByteCount;
-} ADI_BOOT_DATA;
-
-typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *);
-
-#ifndef _BOOTROM_MEMBOOT
-#define _BOOTROM_MEMBOOT 0
-#endif
-static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT;
-
-#ifndef _BOOTROM_TWIBOOT
-#define _BOOTROM_TWIBOOT 0
-#endif
-static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT;
-
-#ifndef _BOOTROM_SPIBOOT
-#define _BOOTROM_SPIBOOT 0
-#endif
-static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT;
-
-#ifndef _BOOTROM_OTPBOOT
-#define _BOOTROM_OTPBOOT 0
-#endif
-static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT;
-
-#ifndef _BOOTROM_NANDBOOT
-#define _BOOTROM_NANDBOOT 0
-#endif
-static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT;
-
-#endif /* __ASSEMBLY__ */
-
-/* Bit defines for BF53x block flags */
-#define BFLAG_53X_ZEROFILL 0x0001
-#define BFLAG_53X_RESVECT 0x0002
-#define BFLAG_53X_INIT 0x0008
-#define BFLAG_53X_IGNORE 0x0010
-#define BFLAG_53X_PFLAG_MASK 0x01E0
-#define BFLAG_53X_PFLAG_SHIFT 5
-#define BFLAG_53X_PPORT_MASK 0x0600
-#define BFLAG_53X_PPORT_SHIFT 9
-#define BFLAG_53X_COMPRESSED 0x2000
-#define BFLAG_53X_FINAL 0x8000
-
-/* Bit defines for BF56x global header */
-#define GFLAG_56X_16BIT_FLASH 0x00000001
-#define GFLAG_56X_WAIT_MASK 0x0000001E
-#define GFLAG_56X_WAIT_SHIFT 1
-#define GFLAG_56X_HOLD_MASK 0x000000C0
-#define GFLAG_56X_HOLD_SHIFT 6
-#define GFLAG_56X_SPI_MASK 0x00000700
-#define GFLAG_56X_SPI_SHIFT 8
-#define GFLAG_56X_SPI_500K 0x0
-#define GFLAG_56X_SPI_1M 0x1
-#define GFLAG_56X_SPI_2M 0x2
-#define GFLAG_56X_SIGN_MASK 0xFF000000
-#define GFLAG_56X_SIGN_SHIFT 28
-#define GFLAG_56X_SIGN_MAGIC 0xA
-
-/* Bit defines for ADI_BOOT_DATA->dFlags */
-#define BFLAG_DMACODE_MASK 0x0000000F
-#define BFLAG_SAFE 0x00000010
-#define BFLAG_AUX 0x00000020
-#define BFLAG_FILL 0x00000100
-#define BFLAG_QUICKBOOT 0x00000200
-#define BFLAG_CALLBACK 0x00000400
-#define BFLAG_INIT 0x00000800
-#define BFLAG_IGNORE 0x00001000
-#define BFLAG_INDIRECT 0x00002000
-#define BFLAG_FIRST 0x00004000
-#define BFLAG_FINAL 0x00008000
-#define BFLAG_HDRSIGN_MASK 0xFF000000
-#define BFLAG_HDRSIGN_SHIFT 24
-#define BFLAG_HDRSIGN_MAGIC 0xAD
-#define BFLAG_HDRCHK_MASK 0x00FF0000
-#define BFLAG_HDRCHK_SHIFT 16
-#define BFLAG_HOOK 0x00400000
-#define BFLAG_HDRINDIRECT 0x00800000
-#define BFLAG_TYPE_MASK 0x00300000
-#define BFLAG_TYPE_1 0x00000000
-#define BFLAG_TYPE_2 0x00100000
-#define BFLAG_TYPE_3 0x00200000
-#define BFLAG_TYPE_4 0x00300000
-#define BFLAG_FASTREAD 0x00400000
-#define BFLAG_NOAUTO 0x01000000
-#define BFLAG_PERIPHERAL 0x02000000
-#define BFLAG_SLAVE 0x04000000
-#define BFLAG_WAKEUP 0x08000000
-#define BFLAG_NEXTDXE 0x10000000
-#define BFLAG_RETURN 0x20000000
-#define BFLAG_RESET 0x40000000
-#define BFLAG_NONRESTORE 0x80000000
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h
deleted file mode 100644
index cdf7349925cf..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/cgu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * CGU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_CGU__
-#define __BFIN_PERIPHERAL_CGU__
-
-/* CGU_CTL Masks */
-#define DF (1 << 0)
-#define MSEL (0x7f << MSEL_P)
-#define WIDLE (1 << WIDLE_P)
-#define LOCK (1 << LOCK_P)
-
-#define DF_P 0
-#define MSEL_P 8
-#define WIDLE_P 30
-#define LOCK_P 31
-#define MSEL_MASK 0x7F00
-#define DF_MASK 0x1
-
-/* CGU_STAT Masks */
-#define PLLEN (1 << 0)
-#define PLLBP (1 << 1)
-#define PLLLK (1 << 2)
-#define CLKSALGN (1 << 3)
-#define CCBF0EN (1 << 4)
-#define CCBF1EN (1 << 5)
-#define SCBF0EN (1 << 6)
-#define SCBF1EN (1 << 7)
-#define DCBFEN (1 << 8)
-#define OCBFEN (1 << 9)
-#define ADRERR (1 << 16)
-#define LWERR (1 << 17)
-#define DIVERR (1 << 18)
-#define WDFMSERR (1 << 19)
-#define WDIVERR (1 << 20)
-#define PLLLKERR (1 << 21)
-
-/* CGU_DIV Masks */
-#define CSEL (0x1f << CSEL_P)
-#define S0SEL (3 << S0SEL_P)
-#define SYSSEL (0x1f << SYSSEL_P)
-#define S1SEL (3 << S1SEL_P)
-#define DSEL (0x1f << DSEL_P)
-#define OSEL (0x7f << OSEL_P)
-#define ALGN (1 << ALGN_P)
-#define UPDT (1 << UPDT_P)
-#define LOCK (1 << LOCK_P)
-
-#define CSEL_P 0
-#define S0SEL_P 5
-#define SYSSEL_P 8
-#define S1SEL_P 13
-#define DSEL_P 16
-#define OSEL_P 22
-#define ALGN_P 29
-#define UPDT_P 30
-#define LOCK_P 31
-
-/* CGU_CLKOUTSEL Masks */
-#define CLKOUTSEL (0xf << 0)
-#define USBCLKSEL (0x3f << 16)
-#define LOCK (1 << LOCK_P)
-
-#define LOCK_P 31
-
-#define CLKOUTSEL_CLKIN 0x0
-#define CLKOUTSEL_CCLK 0x1
-#define CLKOUTSEL_SYSCLK 0x2
-#define CLKOUTSEL_SCLK0 0x3
-#define CLKOUTSEL_SCLK1 0x4
-#define CLKOUTSEL_DCLK 0x5
-#define CLKOUTSEL_USB_PLL 0x6
-#define CLKOUTSEL_OUTCLK 0x7
-#define CLKOUTSEL_USB_CLKIN 0x8
-#define CLKOUTSEL_WDOG 0x9
-#define CLKOUTSEL_PMON 0xA
-#define CLKOUTSEL_GND 0xB
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/core.h b/arch/blackfin/include/asm/mach-common/bits/core.h
deleted file mode 100644
index 6db4f8182683..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/core.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Misc Core Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_CORE__
-#define __BFIN_PERIPHERAL_CORE__
-
-/*
- * EVT registers (ILAT, IMASK, and IPEND).
- */
-
-#define EVT_EMU_P 0 /* Emulator interrupt bit position */
-#define EVT_RST_P 1 /* Reset interrupt bit position */
-#define EVT_NMI_P 2 /* Non Maskable interrupt bit position */
-#define EVT_EVX_P 3 /* Exception bit position */
-#define EVT_IRPTEN_P 4 /* Global interrupt enable bit position */
-#define EVT_IVHW_P 5 /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P 6 /* Timer interrupt bit position */
-#define EVT_IVG7_P 7 /* IVG7 interrupt bit position */
-#define EVT_IVG8_P 8 /* IVG8 interrupt bit position */
-#define EVT_IVG9_P 9 /* IVG9 interrupt bit position */
-#define EVT_IVG10_P 10 /* IVG10 interrupt bit position */
-#define EVT_IVG11_P 11 /* IVG11 interrupt bit position */
-#define EVT_IVG12_P 12 /* IVG12 interrupt bit position */
-#define EVT_IVG13_P 13 /* IVG13 interrupt bit position */
-#define EVT_IVG14_P 14 /* IVG14 interrupt bit position */
-#define EVT_IVG15_P 15 /* IVG15 interrupt bit position */
-
-#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
-#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
-#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
-#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
-#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
-#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
-#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
-#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/*
- * SEQSTAT register
- */
-
-#define EXCAUSE_P 0 /* Last exception cause bit positions */
-#define EXCAUSE0_P 0 /* Last exception cause bit 0 */
-#define EXCAUSE1_P 1 /* Last exception cause bit 1 */
-#define EXCAUSE2_P 2 /* Last exception cause bit 2 */
-#define EXCAUSE3_P 3 /* Last exception cause bit 3 */
-#define EXCAUSE4_P 4 /* Last exception cause bit 4 */
-#define EXCAUSE5_P 5 /* Last exception cause bit 5 */
-#define IDLE_REQ_P 12 /* Pending idle mode request, set by IDLE instruction */
-#define SFTRESET_P 13 /* Indicates whether the last reset was a software reset (=1) */
-#define HWERRCAUSE_P 14 /* Last hw error cause bit positions */
-#define HWERRCAUSE0_P 14 /* Last hw error cause bit 0 */
-#define HWERRCAUSE1_P 15 /* Last hw error cause bit 1 */
-#define HWERRCAUSE2_P 16 /* Last hw error cause bit 2 */
-#define HWERRCAUSE3_P 17 /* Last hw error cause bit 3 */
-#define HWERRCAUSE4_P 18 /* Last hw error cause bit 4 */
-#define HWERRCAUSE5_P 19 /* Last hw error cause bit 5 */
-#define HWERRCAUSE6_P 20 /* Last hw error cause bit 6 */
-#define HWERRCAUSE7_P 21 /* Last hw error cause bit 7 */
-
-#define EXCAUSE \
- ( MK_BMSK_(EXCAUSE0_P) | \
- MK_BMSK_(EXCAUSE1_P) | \
- MK_BMSK_(EXCAUSE2_P) | \
- MK_BMSK_(EXCAUSE3_P) | \
- MK_BMSK_(EXCAUSE4_P) | \
- MK_BMSK_(EXCAUSE5_P) )
-#define SFTRESET \
- ( MK_BMSK_(SFTRESET_P) )
-#define HWERRCAUSE \
- ( MK_BMSK_(HWERRCAUSE0_P) | \
- MK_BMSK_(HWERRCAUSE1_P) | \
- MK_BMSK_(HWERRCAUSE2_P) | \
- MK_BMSK_(HWERRCAUSE3_P) | \
- MK_BMSK_(HWERRCAUSE4_P) )
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#ifdef __ADSPBF561__
-# define DOUBLE_FAULT_A 0x0008
-# define DOUBLE_FAULT_B 0x0010
-# define DOUBLE_FAULT 0x0018 /* Core [A|B] Double Fault Causes Reset */
-# define RESET_DOUBLE_A 0x0800
-# define RESET_DOUBLE_B 0x1000
-# define RESET_DOUBLE 0x1800 /* SW Reset Generated By Core [A|B] Double-Fault */
-# define RESET_WDOG_B 0x2000
-# define RESET_WDOG_A 0x4000
-# define RESET_WDOG 0x6000 /* SW Reset Generated By Watchdog [A|B] Timer */
-#else
-# define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-# define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-# define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#endif
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCFG Masks */
-#define SSSTEP 0x00000001 /* Supervisor Single Step */
-#define CCEN 0x00000002 /* Cycle Counter Enable */
-#define SNEN 0x00000004 /* Self-Nesting Interrupt Enable */
-#define SYSCFG_SSSTEP_P 0
-#define SYSCFG_CCEN_P 1
-#define SYSCFG_SCEN_P 2
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h
deleted file mode 100644
index f7b0bb90f358..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/dde.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Distributed DMA Engine (DDE) Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_DDE__
-#define __BFIN_PERIPHERAL_DDE__
-
-/* DMA_CONFIG Masks */
-#define DMAEN (1 << DMAEN_P) /* DMA Channel Enable */
-#define WNR (1 << WNR_P) /* Channel Direction (W/R*) */
-#define SYNC (1 << SYNC_P) /* Sync Work Unit Transitions */
-#define CADDR (1 << CADDR_P) /* Use Current Address */
-#define PSIZE (7 << PSIZE_P) /* Peripheral Word Size */
-#define PSIZE_1 (0 << PSIZE_P)
-#define PSIZE_2 (1 << PSIZE_P)
-#define PSIZE_4 (2 << PSIZE_P)
-#define PSIZE_8 (3 << PSIZE_P)
-#define MSIZE (7 << MSIZE_P) /* Memory Transfer Size */
-#define MSIZE_1 (0 << MSIZE_P)
-#define MSIZE_2 (1 << MSIZE_P)
-#define MSIZE_4 (2 << MSIZE_P)
-#define MSIZE_8 (3 << MSIZE_P)
-#define MSIZE_16 (4 << MSIZE_P)
-#define MSIZE_32 (5 << MSIZE_P)
-#define FLOW (7 << FLOW_P) /* Next Operation */
-#define FLOW_STOP (0 << FLOW_P) /* Stop Mode */
-#define FLOW_AUTO (1 << FLOW_P) /* Autobuffer Mode */
-#define FLOW_DSCL (4 << FLOW_P) /* Descriptor List */
-#define FLOW_DSCA (5 << FLOW_P) /* Descriptor Array */
-#define FLOW_DSDL (6 << FLOW_P) /* Descriptor On Demand List */
-#define FLOW_DSDA (7 << FLOW_P) /* Descriptor On Demand Array */
-#define NDSIZE (7 << NDSIZE_P) /* Next Descriptor Set Size */
-#define NDSIZE_1 (0 << NDSIZE_P)
-#define NDSIZE_2 (1 << NDSIZE_P)
-#define NDSIZE_3 (2 << NDSIZE_P)
-#define NDSIZE_4 (3 << NDSIZE_P)
-#define NDSIZE_5 (4 << NDSIZE_P)
-#define NDSIZE_6 (5 << NDSIZE_P)
-#define NDSIZE_7 (6 << NDSIZE_P)
-#define DI_EN_X (1 << INT_P)
-#define DI_EN_Y (2 << INT_P)
-#define DI_EN_P (3 << INT_P)
-#define DI_EN (DI_EN_X)
-#define DI_XCOUNT_EN (1 << INT_P) /* xcount expires interrupt */
-#define TRIG (3 << TRIG_P) /* Generate Trigger */
-#define TOVEN (1 << TOVEN_P)
-#define DESCIDCPY (1 << DESCIDCPY_P)
-#define TWOD (1 << TWOD_P)
-#define PDRF (1 << PDRF_P)
-
-#define DMAEN_P 0
-#define WNR_P 1
-#define SYNC_P 2
-#define CADDR_P 3
-#define PSIZE_P 4
-#define MSIZE_P 8
-#define FLOW_P 12
-#define TWAIT_P 15
-#define NDSIZE_P 16
-#define INT_P 20
-#define TRIG_P 22
-#define TOVEN_P 24
-#define DESCIDCPY_P 25
-#define TWOD_P 26
-#define PDRF_P 28
-
-/* DMA_STATUS Masks */
-#define DMA_DONE (1 << DMA_DONE_P) /* Work Unit/Row Done */
-#define DMA_ERR (1 << DMA_ERR_P) /* Error Interrupt */
-#define DMA_PIRQ (1 << DMA_PIRQ_P) /* Peri Intr Request */
-#define DMA_ERRC (7 << DMA_ERRC_P) /* Error Cause */
-#define DMA_RUN (7 << DMA_RUN_P) /* Run Status */
-#define DMA_PBWIDTH (3 << DMA_PBWIDTH_P) /* Peri Bus Width */
-#define DMA_MBWIDTH (3 << DMA_MBWIDTH_P) /* Memory Bus Width */
-#define DMA_FIFOFILL (7 << DMA_FIFOFILL_P) /* FIFO Fill Status */
-#define DMA_TWAIT (1 << DMA_TWAIT_P) /* Trigger Wait Stat */
-
-#define DMA_DONE_P 0
-#define DMA_ERR_P 1
-#define DMA_PIRQ_P 2
-#define DMA_ERRC_P 4
-#define DMA_RUN_P 8
-#define DMA_PBWIDTH_P 12
-#define DMA_MBWIDTH_P 14
-#define DMA_FIFOFILL_P 16
-#define DMA_TWAIT_P 20
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h
deleted file mode 100644
index ac426addd4ed..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/dma.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * DMA Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_DMA__
-#define __BFIN_PERIPHERAL_DMA__
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN 0x0001 /* DMA Channel Enable */
-#define WNR 0x0002 /* Channel Direction (W/R*) */
-#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
-#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
-#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
-#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
-#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
-#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
-#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
-#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
-#define DI_EN_X 0x00100000 /* Data Int Enable in X count */
-#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */
-#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */
-#define DI_EN DI_EN_X /* Data Int Enable */
-#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */
-#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */
-#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */
-#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */
-#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */
-#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */
-#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */
-#define NDSIZE 0x00070000 /* Next Desc Size */
-#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */
-#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */
-#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */
-#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */
-#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */
-#define DMA_RUN 0x00000200 /* DMA Channel Run */
-#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/
-#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */
-
-#else
-
-#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
-#define PSIZE_16 WDSIZE_16
-#define PSIZE_32 WDSIZE_32
-#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
-#define RESTART 0x0020 /* DMA Buffer Clear */
-#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
-#define DI_EN 0x0080 /* Data Interrupt Enable */
-#define NDSIZE 0x0F00 /* Next Descriptor bitmask */
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */
-#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
-#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
-#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
-#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
-#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
-#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
-#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
-#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
-#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
-#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
-#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
-
-#define DMAEN_P 0 /* Channel Enable */
-#define WNR_P 1 /* Channel Direction (W/R*) */
-#define WDSIZE_P 2 /* Transfer Word Size */
-#define DMA2D_P 4 /* 2D/1D* Mode */
-#define RESTART_P 5 /* Restart */
-#define DI_SEL_P 6 /* Data Interrupt Select */
-#define DI_EN_P 7 /* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
-#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
-#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW 0x7000 /* Flow Control */
-#define FLOW_STOP 0x0000 /* Stop Mode */
-#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
-
-#define DMA_DONE_P 0 /* DMA Done Indicator */
-#define DMA_ERR_P 1 /* DMA Error Indicator */
-#define DFETCH_P 2 /* Descriptor Fetch Indicator */
-#define DMA_RUN_P 3 /* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */
-#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ebiu.h b/arch/blackfin/include/asm/mach-common/bits/ebiu.h
deleted file mode 100644
index 7c0c569acf9c..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ebiu.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * EBIU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_EBIU__
-#define __BFIN_PERIPHERAL_EBIU__
-
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0,/ 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
-#define CDPRIO 0x0100 /* Core has priority over DMA for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P 0x00000004 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P 0x00000005 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P 0x00000006 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P 0x00000007 /* Enable 16-bit packing Bank 3 */
-#define CDPRIO_P 0x00000008 /* Core has priority over DMA for external accesses */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* Only available on newer parts */
-#ifdef EBIU_MODE
-
-/* EBIU_MBSCTL Bit Positions */
-#define AMSB0CTL_P 0
-#define AMSB1CTL_P 2
-#define AMSB2CTL_P 4
-#define AMSB3CTL_P 6
-
-/* EBIU_MBSCTL Masks */
-#define AMSB0CTL_MASK (0x3 << AMSB0CTL_P) /* Async Memory Bank 0 Control Modes */
-#define AMSB0CTL_NONE (0x0 << AMSB0CTL_P) /* Control Mode - 00 - No logic */
-#define AMSB0CTL_ARE (0x1 << AMSB0CTL_P) /* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB0CTL_AOE (0x2 << AMSB0CTL_P) /* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB0CTL_AWE (0x3 << AMSB0CTL_P) /* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB1CTL_MASK (0x3 << AMSB1CTL_P) /* Async Memory Bank 1 Control Modes */
-#define AMSB1CTL_NONE (0x0 << AMSB1CTL_P) /* Control Mode - 00 - No logic */
-#define AMSB1CTL_ARE (0x1 << AMSB1CTL_P) /* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB1CTL_AOE (0x2 << AMSB1CTL_P) /* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB1CTL_AWE (0x3 << AMSB1CTL_P) /* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB2CTL_MASK (0x3 << AMSB2CTL_P) /* Async Memory Bank 2 Control Modes */
-#define AMSB2CTL_NONE (0x0 << AMSB2CTL_P) /* Control Mode - 00 - No logic */
-#define AMSB2CTL_ARE (0x1 << AMSB2CTL_P) /* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB2CTL_AOE (0x2 << AMSB2CTL_P) /* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB2CTL_AWE (0x3 << AMSB2CTL_P) /* Control Mode - 03 - OR-ed with /AWE */
-#define AMSB3CTL_MASK (0x3 << AMSB3CTL_P) /* Async Memory Bank 3 Control Modes */
-#define AMSB3CTL_NONE (0x0 << AMSB3CTL_P) /* Control Mode - 00 - No logic */
-#define AMSB3CTL_ARE (0x1 << AMSB3CTL_P) /* Control Mode - 01 - OR-ed with /ARE */
-#define AMSB3CTL_AOE (0x2 << AMSB3CTL_P) /* Control Mode - 02 - OR-ed with /AOE */
-#define AMSB3CTL_AWE (0x3 << AMSB3CTL_P) /* Control Mode - 03 - OR-ed with /AWE */
-
-/* EBIU_MODE Bit Positions */
-#define B0MODE_P 0
-#define B1MODE_P 2
-#define B2MODE_P 4
-#define B3MODE_P 6
-
-/* EBIU_MODE Masks */
-#define B0MODE_MASK (0x3 << B0MODE_P) /* Async Memory Bank 0 Access Mode */
-#define B0MODE_ASYNC (0x0 << B0MODE_P) /* Access Mode - 00 - Asynchronous Mode */
-#define B0MODE_FLASH (0x1 << B0MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */
-#define B0MODE_PAGE (0x2 << B0MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */
-#define B0MODE_BURST (0x3 << B0MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B1MODE_MASK (0x3 << B1MODE_P) /* Async Memory Bank 1 Access Mode */
-#define B1MODE_ASYNC (0x0 << B1MODE_P) /* Access Mode - 00 - Asynchronous Mode */
-#define B1MODE_FLASH (0x1 << B1MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */
-#define B1MODE_PAGE (0x2 << B1MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */
-#define B1MODE_BURST (0x3 << B1MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B2MODE_MASK (0x3 << B2MODE_P) /* Async Memory Bank 2 Access Mode */
-#define B2MODE_ASYNC (0x0 << B2MODE_P) /* Access Mode - 00 - Asynchronous Mode */
-#define B2MODE_FLASH (0x1 << B2MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */
-#define B2MODE_PAGE (0x2 << B2MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */
-#define B2MODE_BURST (0x3 << B2MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */
-#define B3MODE_MASK (0x3 << B3MODE_P) /* Async Memory Bank 3 Access Mode */
-#define B3MODE_ASYNC (0x0 << B3MODE_P) /* Access Mode - 00 - Asynchronous Mode */
-#define B3MODE_FLASH (0x1 << B3MODE_P) /* Access Mode - 01 - Asynchronous Flash Mode */
-#define B3MODE_PAGE (0x2 << B3MODE_P) /* Access Mode - 10 - Asynchronous Page Mode */
-#define B3MODE_BURST (0x3 << B3MODE_P) /* Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* EBIU_FCTL Bit Positions */
-#define TESTSETLOCK_P 0
-#define BCLK_P 1
-#define PGWS_P 3
-#define PGSZ_P 6
-#define RDDL_P 7
-
-/* EBIU_FCTL Masks */
-#define TESTSETLOCK (0x1 << TESTSETLOCK_P) /* Test set lock */
-#define BCLK_MASK (0x3 << BCLK_P) /* Burst clock frequency */
-#define BCLK_2 (0x1 << BCLK_P) /* Burst clock frequency - SCLK/2 */
-#define BCLK_3 (0x2 << BCLK_P) /* Burst clock frequency - SCLK/3 */
-#define BCLK_4 (0x3 << BCLK_P) /* Burst clock frequency - SCLK/4 */
-#define PGWS_MASK (0x7 << PGWS_P) /* Page wait states */
-#define PGWS_0 (0x0 << PGWS_P) /* Page wait states - 0 cycles */
-#define PGWS_1 (0x1 << PGWS_P) /* Page wait states - 1 cycles */
-#define PGWS_2 (0x2 << PGWS_P) /* Page wait states - 2 cycles */
-#define PGWS_3 (0x3 << PGWS_P) /* Page wait states - 3 cycles */
-#define PGWS_4 (0x4 << PGWS_P) /* Page wait states - 4 cycles */
-#define PGSZ (0x1 << PGSZ_P) /* Page size */
-#define PGSZ_4 (0x0 << PGSZ_P) /* Page size - 4 words */
-#define PGSZ_8 (0x1 << PGSZ_P) /* Page size - 8 words */
-#define RDDL (0x38 << RDDL_P) /* Read data delay */
-
-/* EBIU_ARBSTAT Masks */
-#define ARBSTAT 0x00000001 /* Arbitration status */
-#define BGSTAT 0x00000002 /* External Bus grant status */
-
-#endif /* EBIU_MODE */
-
-/* Only available on SDRAM based-parts */
-#ifdef EBIU_SDGCTL
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define SCK1E 0x00000002 /* Enable CLKOUT, /SCLK1 */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-#ifdef __ADSPBF561__
-
-#define EB0E (EBE<<0) /* Enable SDRAM external bank 0 */
-#define EB0SZ_16 (EBSZ_16<<0) /* SDRAM external bank size = 16MB */
-#define EB0SZ_32 (EBSZ_32<<0) /* SDRAM external bank size = 32MB */
-#define EB0SZ_64 (EBSZ_64<<0) /* SDRAM external bank size = 64MB */
-#define EB0SZ_128 (EBSZ_128<<0) /* SDRAM external bank size = 128MB */
-#define EB0CAW_8 (EBCAW_8<<0) /* SDRAM external bank column address width = 8 bits */
-#define EB0CAW_9 (EBCAW_9<<0) /* SDRAM external bank column address width = 9 bits */
-#define EB0CAW_10 (EBCAW_10<<0) /* SDRAM external bank column address width = 9 bits */
-#define EB0CAW_11 (EBCAW_11<<0) /* SDRAM external bank column address width = 9 bits */
-
-#define EB1E (EBE<<8) /* Enable SDRAM external bank 0 */
-#define EB1SZ_16 (EBSZ_16<<8) /* SDRAM external bank size = 16MB */
-#define EB1SZ_32 (EBSZ_32<<8) /* SDRAM external bank size = 32MB */
-#define EB1SZ_64 (EBSZ_64<<8) /* SDRAM external bank size = 64MB */
-#define EB1SZ_128 (EBSZ_128<<8) /* SDRAM external bank size = 128MB */
-#define EB1CAW_8 (EBCAW_8<<8) /* SDRAM external bank column address width = 8 bits */
-#define EB1CAW_9 (EBCAW_9<<8) /* SDRAM external bank column address width = 9 bits */
-#define EB1CAW_10 (EBCAW_10<<8) /* SDRAM external bank column address width = 9 bits */
-#define EB1CAW_11 (EBCAW_11<<8) /* SDRAM external bank column address width = 9 bits */
-
-#define EB2E (EBE<<16) /* Enable SDRAM external bank 0 */
-#define EB2SZ_16 (EBSZ_16<<16) /* SDRAM external bank size = 16MB */
-#define EB2SZ_32 (EBSZ_32<<16) /* SDRAM external bank size = 32MB */
-#define EB2SZ_64 (EBSZ_64<<16) /* SDRAM external bank size = 64MB */
-#define EB2SZ_128 (EBSZ_128<<16) /* SDRAM external bank size = 128MB */
-#define EB2CAW_8 (EBCAW_8<<16) /* SDRAM external bank column address width = 8 bits */
-#define EB2CAW_9 (EBCAW_9<<16) /* SDRAM external bank column address width = 9 bits */
-#define EB2CAW_10 (EBCAW_10<<16) /* SDRAM external bank column address width = 9 bits */
-#define EB2CAW_11 (EBCAW_11<<16) /* SDRAM external bank column address width = 9 bits */
-
-#define EB3E (EBE<<24) /* Enable SDRAM external bank 0 */
-#define EB3SZ_16 (EBSZ_16<<24) /* SDRAM external bank size = 16MB */
-#define EB3SZ_32 (EBSZ_32<<24) /* SDRAM external bank size = 32MB */
-#define EB3SZ_64 (EBSZ_64<<24) /* SDRAM external bank size = 64MB */
-#define EB3SZ_128 (EBSZ_128<<24) /* SDRAM external bank size = 128MB */
-#define EB3CAW_8 (EBCAW_8<<24) /* SDRAM external bank column address width = 8 bits */
-#define EB3CAW_9 (EBCAW_9<<24) /* SDRAM external bank column address width = 9 bits */
-#define EB3CAW_10 (EBCAW_10<<24) /* SDRAM external bank column address width = 9 bits */
-#define EB3CAW_11 (EBCAW_11<<24) /* SDRAM external bank column address width = 9 bits */
-
-#endif /* BF561 */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM controller is idle */
-#define SDSRA 0x0002 /* SDRAM self refresh is active */
-#define SDPUA 0x0004 /* SDRAM power up active */
-#define SDRS 0x0008 /* SDRAM is in reset state */
-#define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x0020 /* Bus granted */
-
-/* Only available on DDR based-parts */
-#else
-
-/* EBIU_ERRMST Masks */
-#define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */
-#define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */
-#define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */
-#define CORE_ERROR 0x0008 /* Core access on reserved memory */
-#define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */
-#define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */
-#define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */
-#define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */
-
-/* EBIU_RSTCTL Masks */
-#define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */
-#define SRREQ 0x0008 /* Self Refresh Request */
-#define SRACK 0x0010 /* Self Refresh Request Acknowledgement */
-#define MDDRENABLE 0x0020 /* Mobile DDR Enable */
-
-#endif /* EBIU_SDGCTL */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h
deleted file mode 100644
index 4c9bc9dc5715..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/emac.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Ethernet MAC Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_EMAC__
-#define __BFIN_PERIPHERAL_EMAC__
-
-/* EMAC_OPMODE Masks */
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x) & 0x1F) << 6) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x) & 0x1F) << 11) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x) & 0xFFFF) << 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x) & 0xFF) << 0) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x) & 0xFF) << 8) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x) & 0xFF) << 16) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x) & 0xFF) << 24) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x) & 0xFFFF) << 0) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x) & 0xFFFF) << 16) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x) & 0x3F) << 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-/*default value for EMAC_VLANx reg*/
-#define EMAC_VLANX_DEF_VAL 0xFFFF
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/eppi.h b/arch/blackfin/include/asm/mach-common/bits/eppi.h
deleted file mode 100644
index fb1456fc0e14..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/eppi.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Enhanced PPI (EPPI)
- */
-
-#ifndef __BFIN_PERIPHERAL_EPPI__
-#define __BFIN_PERIPHERAL_EPPI__
-
-/* Bit masks for EPPIx_STATUS */
-#define CFIFO_ERR 0x0001 /* Chroma FIFO Error */
-#define YFIFO_ERR 0x0002 /* Luma FIFO Error */
-#define LTERR_OVR 0x0004 /* Line Track Overflow */
-#define LTERR_UNDR 0x0008 /* Line Track Underflow */
-#define FTERR_OVR 0x0010 /* Frame Track Overflow */
-#define FTERR_UNDR 0x0020 /* Frame Track Underflow */
-#define ERR_NCOR 0x0040 /* Preamble Error Not Corrected */
-#define DMA1URQ 0x0080 /* DMA1 Urgent Request */
-#define DMA0URQ 0x0100 /* DMA0 Urgent Request */
-#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define FLD 0x8000 /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-#define EPPI_EN 0x00000001 /* Enable */
-#define EPPI_DIR 0x00000002 /* Direction */
-#define XFR_TYPE 0x0000000c /* Operating Mode */
-#define FS_CFG 0x00000030 /* Frame Sync Configuration */
-#define FLD_SEL 0x00000040 /* Field Select/Trigger */
-#define ITU_TYPE 0x00000080 /* ITU Interlaced or Progressive */
-#define BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN 0x00000200 /* Internal Clock Generation */
-#define IFSGEN 0x00000400 /* Internal Frame Sync Generation */
-#define POLC 0x00001800 /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS 0x00006000 /* Frame Sync Polarity */
-#define DLENGTH 0x00038000 /* Data Length */
-#define SKIP_EN 0x00040000 /* Skip Enable */
-#define SKIP_EO 0x00080000 /* Skip Even or Odd */
-#define PACKEN 0x00100000 /* Packing/Unpacking Enable */
-#define SWAPEN 0x00200000 /* Swap Enable */
-#define SIGN_EXT 0x00400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD 0x00800000 /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD 0x01000000 /* Sub-split Odd Samples */
-#define DMACFG 0x02000000 /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN 0x04000000 /* RGB Formatting Enable */
-#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
-#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8 (0 << 15) /* 000 - 8 bits */
-#define DLEN_10 (1 << 15) /* 001 - 10 bits */
-#define DLEN_12 (2 << 15) /* 010 - 12 bits */
-#define DLEN_14 (3 << 15) /* 011 - 14 bits */
-#define DLEN_16 (4 << 15) /* 100 - 16 bits */
-#define DLEN_18 (5 << 15) /* 101 - 18 bits */
-#define DLEN_24 (6 << 15) /* 110 - 24 bits */
-
-/* Bit masks for EPPIx_FS2W_LVB */
-#define F1VB_BD 0x000000ff /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD 0x0000ff00 /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD 0x00ff0000 /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-#define F1_ACT 0x0000ffff /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-#define LOW_ODD 0x000000ff /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD 0x0000ff00 /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN 0x00ff0000 /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
deleted file mode 100644
index cfde2364d771..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * MPU Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_MPU__
-#define __BFIN_PERIPHERAL_MPU__
-
-/*
- * DMEM_CONTROL Register
- */
-
-/* ** Bit Positions */
-#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */
-#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
-#define ENDCPLB_P 0x01 /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
-#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
-#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
-#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
-#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
-
-/* ** Masks */
-#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
-#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
-#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
-#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
-#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
-#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* ** Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
-#define ENICPLB_P 0x01 /* Enable ICPLB */
-#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
-#define IMC_P 0x02 /* Enable */
-#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0_P 0x03 /* Lock Way 0 */
-#define ILOC1_P 0x04 /* Lock Way 1 */
-#define ILOC2_P 0x05 /* Lock Way 2 */
-#define ILOC3_P 0x06 /* Lock Way 3 */
-#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
-
-/* ** Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
-#define ENICPLB 0x00000002 /* Enable ICPLB */
-#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0 0x00000008 /* Lock Way 0 */
-#define ILOC1 0x00000010 /* Lock Way 1 */
-#define ILOC2 0x00000020 /* Lock Way 2 */
-#define ILOC3 0x00000040 /* Lock Way 3 */
-#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* ** Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
-
-/* ** Masks */
-#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
-#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
-#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
-#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
-#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
-#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
-#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
-#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
-#define PAGE_SIZE_MASK 0x00070000 /* page_size field mask */
-#define PAGE_SIZE_SHIFT 16
-#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
-#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
-
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
-
-/* DCPLB_DATA only */
-#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
- /* 1= allocate cache lines on write-through writes. */
-#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* ** Masks */
-#define TEST_READ 0x00000000 /* Read Access */
-#define TEST_WRITE 0x00000002 /* Write Access */
-#define TEST_TAG 0x00000000 /* Access TAG */
-#define TEST_DATA 0x00000004 /* Access DATA */
-#define TEST_DW0 0x00000000 /* Select Double Word 0 */
-#define TEST_DW1 0x00000008 /* Select Double Word 1 */
-#define TEST_DW2 0x00000010 /* Select Double Word 2 */
-#define TEST_DW3 0x00000018 /* Select Double Word 3 */
-#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
-#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
-#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
-#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
-#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
-#define TEST_WAY0 0x00000000 /* Access Way0 */
-#define TEST_WAY1 0x04000000 /* Access Way1 */
-
-/* ** ITEST_COMMAND only */
-#define TEST_WAY2 0x08000000 /* Access Way2 */
-#define TEST_WAY3 0x0C000000 /* Access Way3 */
-
-/* ** DTEST_COMMAND only */
-#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
-#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/otp.h b/arch/blackfin/include/asm/mach-common/bits/otp.h
deleted file mode 100644
index 4e3f1afcfa0d..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/otp.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * OTP Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_OTP__
-#define __BFIN_PERIPHERAL_OTP__
-
-#ifndef __ASSEMBLY__
-
-#include "bootrom.h"
-
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
-
-#endif
-
-/* otp_command(): defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
-
-/* otp_{read,write}(): defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS 0x00000000
-#define OTP_MASTER_ERROR 0x001
-#define OTP_WRITE_ERROR 0x003
-#define OTP_READ_ERROR 0x005
-#define OTP_ACC_VIO_ERROR 0x009
-#define OTP_DATA_MULT_ERROR 0x011
-#define OTP_ECC_MULT_ERROR 0x021
-#define OTP_PREV_WR_ERROR 0x041
-#define OTP_DATA_SB_WARN 0x100
-#define OTP_ECC_SB_WARN 0x200
-
-/* Predefined otp pages: Factory Programmed Settings */
-#define FPS00 0x0004
-#define FPS01 0x0005
-#define FPS02 0x0006
-#define FPS03 0x0007
-#define FPS04 0x0008
-#define FPS05 0x0009
-#define FPS06 0x000A
-#define FPS07 0x000B
-#define FPS08 0x000C
-#define FPS09 0x000D
-#define FPS10 0x000E
-#define FPS11 0x000F
-
-/* Predefined otp pages: Customer Programmed Settings */
-#define CPS00 0x0010
-#define CPS01 0x0011
-#define CPS02 0x0012
-#define CPS03 0x0013
-#define CPS04 0x0014
-#define CPS05 0x0015
-#define CPS06 0x0016
-#define CPS07 0x0017
-
-/* Predefined otp pages: Pre-Boot Settings */
-#define PBS00 0x0018
-#define PBS01 0x0019
-#define PBS02 0x001A
-#define PBS03 0x001B
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/pata.h b/arch/blackfin/include/asm/mach-common/bits/pata.h
deleted file mode 100644
index 9b61824f18ec..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/pata.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * ATAPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PATA__
-#define __BFIN_PERIPHERAL_PATA__
-
-/* Bit masks for ATAPI_CONTROL */
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for ATAPI_CONTROL */
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-#endif /* __BFIN_PERIPHERAL_PATA__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
deleted file mode 100644
index fe0ba0f54366..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/pll.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * PLL Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PLL__
-#define __BFIN_PERIPHERAL_PLL__
-
-/* PLL_CTL Masks */
-#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF 0x0002 /* PLL Not Powered */
-#define STOPCK 0x0008 /* Core Clock Off */
-#define PDWN 0x0020 /* Enter Deep Sleep Mode */
-#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
-#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
-#define BYPASS 0x0100 /* Bypass the PLL */
-#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
-
-#define MSEL_P 9
-
-/* PLL_DIV Masks */
-#define SSEL 0x000F /* System Select */
-#define CSEL 0x0030 /* Core Select */
-#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
-#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
-#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
-#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
-
-#define CCLK_DIV1 CSEL_DIV1
-#define CCLK_DIV2 CSEL_DIV2
-#define CCLK_DIV4 CSEL_DIV4
-#define CCLK_DIV8 CSEL_DIV8
-
-#define SSEL_P 0
-#define CSEL_P 4
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON 0x0002 /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
-#define DEEP_SLEEP 0x0008 /* Processor In Deep Sleep Mode */
-#define SLEEP 0x0010 /* Processor In Sleep Mode */
-#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
-#define CORE_IDLE 0x0040 /* Processor In IDLE Mode */
-#define VSTAT 0x0080 /* Voltage Regulator Has Reached Programmed Voltage */
-
-/* VR_CTL Masks */
-#ifdef __ADSPBF52x__
-#define FREQ_MASK 0x3000 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
-#else
-#define FREQ_MASK 0x0003 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
-#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
-#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
-#endif
-
-#define GAIN_MASK 0x000C /* Voltage Level Gain */
-#define GAIN_5 0x0000 /* GAIN = 5 */
-#define GAIN_10 0x0004 /* GAIN = 10 */
-#define GAIN_20 0x0008 /* GAIN = 20 */
-#define GAIN_50 0x000C /* GAIN = 50 */
-
-#ifdef __ADSPBF52x__
-#define VLEV_MASK 0x00F0 /* Internal Voltage Level */
-#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_MASK 0x00F0 /* Internal Voltage Level */
-#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
-#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
-#define GPWE 0x0400 /* General-purpose Wakeup From Hibernate */
-#define MXVRWE 0x0400 /* MXVR Wakeup From Hibernate */
-#define USBWE 0x0800 /* USB Wakeup From Hibernate */
-#define KPADWE 0x1000 /* Keypad Wakeup From Hibernate */
-#define ROTWE 0x2000 /* Rotary Counter Wakeup From Hibernate */
-#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
-#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-a.h b/arch/blackfin/include/asm/mach-common/bits/ports-a.h
deleted file mode 100644
index 9f78a761c40a..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-a.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0 (1 << 0)
-#define PA1 (1 << 1)
-#define PA2 (1 << 2)
-#define PA3 (1 << 3)
-#define PA4 (1 << 4)
-#define PA5 (1 << 5)
-#define PA6 (1 << 6)
-#define PA7 (1 << 7)
-#define PA8 (1 << 8)
-#define PA9 (1 << 9)
-#define PA10 (1 << 10)
-#define PA11 (1 << 11)
-#define PA12 (1 << 12)
-#define PA13 (1 << 13)
-#define PA14 (1 << 14)
-#define PA15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-b.h b/arch/blackfin/include/asm/mach-common/bits/ports-b.h
deleted file mode 100644
index b81702f09ec6..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-b.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0 (1 << 0)
-#define PB1 (1 << 1)
-#define PB2 (1 << 2)
-#define PB3 (1 << 3)
-#define PB4 (1 << 4)
-#define PB5 (1 << 5)
-#define PB6 (1 << 6)
-#define PB7 (1 << 7)
-#define PB8 (1 << 8)
-#define PB9 (1 << 9)
-#define PB10 (1 << 10)
-#define PB11 (1 << 11)
-#define PB12 (1 << 12)
-#define PB13 (1 << 13)
-#define PB14 (1 << 14)
-#define PB15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-c.h b/arch/blackfin/include/asm/mach-common/bits/ports-c.h
deleted file mode 100644
index 3cc665e0ba08..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-c.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0 (1 << 0)
-#define PC1 (1 << 1)
-#define PC2 (1 << 2)
-#define PC3 (1 << 3)
-#define PC4 (1 << 4)
-#define PC5 (1 << 5)
-#define PC6 (1 << 6)
-#define PC7 (1 << 7)
-#define PC8 (1 << 8)
-#define PC9 (1 << 9)
-#define PC10 (1 << 10)
-#define PC11 (1 << 11)
-#define PC12 (1 << 12)
-#define PC13 (1 << 13)
-#define PC14 (1 << 14)
-#define PC15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-d.h b/arch/blackfin/include/asm/mach-common/bits/ports-d.h
deleted file mode 100644
index 868c6a01f1b2..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-d.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0 (1 << 0)
-#define PD1 (1 << 1)
-#define PD2 (1 << 2)
-#define PD3 (1 << 3)
-#define PD4 (1 << 4)
-#define PD5 (1 << 5)
-#define PD6 (1 << 6)
-#define PD7 (1 << 7)
-#define PD8 (1 << 8)
-#define PD9 (1 << 9)
-#define PD10 (1 << 10)
-#define PD11 (1 << 11)
-#define PD12 (1 << 12)
-#define PD13 (1 << 13)
-#define PD14 (1 << 14)
-#define PD15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-e.h b/arch/blackfin/include/asm/mach-common/bits/ports-e.h
deleted file mode 100644
index c88b0d0dd443..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-e.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0 (1 << 0)
-#define PE1 (1 << 1)
-#define PE2 (1 << 2)
-#define PE3 (1 << 3)
-#define PE4 (1 << 4)
-#define PE5 (1 << 5)
-#define PE6 (1 << 6)
-#define PE7 (1 << 7)
-#define PE8 (1 << 8)
-#define PE9 (1 << 9)
-#define PE10 (1 << 10)
-#define PE11 (1 << 11)
-#define PE12 (1 << 12)
-#define PE13 (1 << 13)
-#define PE14 (1 << 14)
-#define PE15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-f.h b/arch/blackfin/include/asm/mach-common/bits/ports-f.h
deleted file mode 100644
index d6af20633278..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-f.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0 (1 << 0)
-#define PF1 (1 << 1)
-#define PF2 (1 << 2)
-#define PF3 (1 << 3)
-#define PF4 (1 << 4)
-#define PF5 (1 << 5)
-#define PF6 (1 << 6)
-#define PF7 (1 << 7)
-#define PF8 (1 << 8)
-#define PF9 (1 << 9)
-#define PF10 (1 << 10)
-#define PF11 (1 << 11)
-#define PF12 (1 << 12)
-#define PF13 (1 << 13)
-#define PF14 (1 << 14)
-#define PF15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-g.h b/arch/blackfin/include/asm/mach-common/bits/ports-g.h
deleted file mode 100644
index 09355d333c0e..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-g.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0 (1 << 0)
-#define PG1 (1 << 1)
-#define PG2 (1 << 2)
-#define PG3 (1 << 3)
-#define PG4 (1 << 4)
-#define PG5 (1 << 5)
-#define PG6 (1 << 6)
-#define PG7 (1 << 7)
-#define PG8 (1 << 8)
-#define PG9 (1 << 9)
-#define PG10 (1 << 10)
-#define PG11 (1 << 11)
-#define PG12 (1 << 12)
-#define PG13 (1 << 13)
-#define PG14 (1 << 14)
-#define PG15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-h.h b/arch/blackfin/include/asm/mach-common/bits/ports-h.h
deleted file mode 100644
index fa3910c6fbd4..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-h.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0 (1 << 0)
-#define PH1 (1 << 1)
-#define PH2 (1 << 2)
-#define PH3 (1 << 3)
-#define PH4 (1 << 4)
-#define PH5 (1 << 5)
-#define PH6 (1 << 6)
-#define PH7 (1 << 7)
-#define PH8 (1 << 8)
-#define PH9 (1 << 9)
-#define PH10 (1 << 10)
-#define PH11 (1 << 11)
-#define PH12 (1 << 12)
-#define PH13 (1 << 13)
-#define PH14 (1 << 14)
-#define PH15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-i.h b/arch/blackfin/include/asm/mach-common/bits/ports-i.h
deleted file mode 100644
index f176f08af624..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-i.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0 (1 << 0)
-#define PI1 (1 << 1)
-#define PI2 (1 << 2)
-#define PI3 (1 << 3)
-#define PI4 (1 << 4)
-#define PI5 (1 << 5)
-#define PI6 (1 << 6)
-#define PI7 (1 << 7)
-#define PI8 (1 << 8)
-#define PI9 (1 << 9)
-#define PI10 (1 << 10)
-#define PI11 (1 << 11)
-#define PI12 (1 << 12)
-#define PI13 (1 << 13)
-#define PI14 (1 << 14)
-#define PI15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-j.h b/arch/blackfin/include/asm/mach-common/bits/ports-j.h
deleted file mode 100644
index 924123ecec5a..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ports-j.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0 (1 << 0)
-#define PJ1 (1 << 1)
-#define PJ2 (1 << 2)
-#define PJ3 (1 << 3)
-#define PJ4 (1 << 4)
-#define PJ5 (1 << 5)
-#define PJ6 (1 << 6)
-#define PJ7 (1 << 7)
-#define PJ8 (1 << 8)
-#define PJ9 (1 << 9)
-#define PJ10 (1 << 10)
-#define PJ11 (1 << 11)
-#define PJ12 (1 << 12)
-#define PJ13 (1 << 13)
-#define PJ14 (1 << 14)
-#define PJ15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ppi.h b/arch/blackfin/include/asm/mach-common/bits/ppi.h
deleted file mode 100644
index 523f2388e4fd..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/ppi.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * PPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PPI__
-#define __BFIN_PERIPHERAL_PPI__
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/rtc.h b/arch/blackfin/include/asm/mach-common/bits/rtc.h
deleted file mode 100644
index f5a0cdb9d2c7..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/rtc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * RTC Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_RTC__
-#define __BFIN_PERIPHERAL_RTC__
-
-/* RTC_STAT and RTC_ALARM Masks */
-#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
-#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
-#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
-#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
-
-#define RTC_SEC_P 0
-#define RTC_MIN_P 6
-#define RTC_HR_P 12
-#define RTC_DAY_P 17
-
-/*
- * RTC_ALARM Macro
- */
-#define SET_ALARM(day, hr, min, sec) \
- ( (((day) << RTC_DAY_P) & RTC_DAY) | \
- (((hr) << RTC_HR_P ) & RTC_HR ) | \
- (((min) << RTC_MIN_P) & RTC_MIN) | \
- (((sec) << RTC_SEC_P) & RTC_SEC) )
-
-/* RTC_ICTL and RTC_ISTAT Masks */
-#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
-#define ALARM 0x0002 /* Alarm Interrupt Enable */
-#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
-#define MINUTE 0x0008 /* Minutes Interrupt Enable */
-#define HOUR 0x0010 /* Hours Interrupt Enable */
-#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
-#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define WRITE_PENDING 0x4000 /* Write Pending Status */
-#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
-
-/* RTC_FAST / RTC_PREN Mask */
-#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h
deleted file mode 100644
index 1c60d4b83142..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/sdh.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * SDH Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SDH__
-#define __BFIN_PERIPHERAL_SDH__
-
-/* Bit masks for SDH_COMMAND */
-#define CMD_IDX 0x3f /* Command Index */
-#define CMD_RSP 0x40 /* Response */
-#define CMD_L_RSP 0x80 /* Long Response */
-#define CMD_INT_E 0x100 /* Command Interrupt */
-#define CMD_PEND_E 0x200 /* Command Pending */
-#define CMD_E 0x400 /* Command Enable */
-#ifdef RSI_BLKSZ
-#define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */
-#define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */
-#endif
-
-/* Bit masks for SDH_PWR_CTL */
-#ifndef RSI_BLKSZ
-#define PWR_ON 0x3 /* Power On */
-#define SD_CMD_OD 0x40 /* Open Drain Output */
-#define ROD_CTL 0x80 /* Rod Control */
-#endif
-
-/* Bit masks for SDH_CLK_CTL */
-#define CLKDIV 0xff /* MC_CLK Divisor */
-#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
-#define PWR_SV_E 0x200 /* Power Save Enable */
-#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
-#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
-#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
-#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
-#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
-#ifdef RSI_BLKSZ
-#define CARD_TYPE_MASK 0xe000 /* Card type mask */
-#define CARD_TYPE_OFFSET 13 /* Card type offset */
-#define CARD_TYPE_SDIO 0
-#define CARD_TYPE_eMMC 1
-#define CARD_TYPE_SD 2
-#define CARD_TYPE_CEATA 3
-#endif
-
-/* Bit masks for SDH_RESP_CMD */
-#define RESP_CMD 0x3f /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-#define DTX_E 0x1 /* Data Transfer Enable */
-#define DTX_DIR 0x2 /* Data Transfer Direction */
-#define DTX_MODE 0x4 /* Data Transfer Mode */
-#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
-#endif
-
-/* Bit masks for SDH_STATUS */
-#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
-#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define CMD_TIME_OUT 0x4 /* CMD Time Out */
-#define DAT_TIME_OUT 0x8 /* Data Time Out */
-#define TX_UNDERRUN 0x10 /* Transmit Underrun */
-#define RX_OVERRUN 0x20 /* Receive Overrun */
-#define CMD_RESP_END 0x40 /* CMD Response End */
-#define CMD_SENT 0x80 /* CMD Sent */
-#define DAT_END 0x100 /* Data End */
-#define START_BIT_ERR 0x200 /* Start Bit Error */
-#define DAT_BLK_END 0x400 /* Data Block End */
-#define CMD_ACT 0x800 /* CMD Active */
-#define TX_ACT 0x1000 /* Transmit Active */
-#define RX_ACT 0x2000 /* Receive Active */
-#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
-#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
-#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
-#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
-#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
-#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
-#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
-#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
-#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
-#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
-#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
-#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
-#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
-#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
-#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
-#define DAT_END_STAT 0x100 /* Data End Status */
-#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
-#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
-#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
-#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
-#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
-#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
-#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
-#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
-#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
-#define DAT_END_MASK 0x100 /* Data End Mask */
-#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
-#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
-#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
-#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
-#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
-#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
-#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
-#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
-#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
-#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
-#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
-#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
-#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-#define FIFO_COUNT 0x7fff /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
-#define SD_CARD_DET 0x10 /* SD Card Detect */
-#define SD_CARD_BUSYMODE 0x80000000 /* Card is in Busy mode */
-#define SD_CARD_SLPMODE 0x40000000 /* Card in Sleep Mode */
-#define SD_CARD_READY 0x00020000 /* Card Ready */
-
-/* Bit masks for SDH_E_MASK */
-#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
-#define SCD_MSK 0x10 /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-#define CLKS_EN 0x1 /* Clocks Enable */
-#define SD4E 0x4 /* SDIO 4-Bit Enable */
-#define MWE 0x8 /* Moving Window Enable */
-#define SD_RST 0x10 /* SDMMC Reset */
-#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
-#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
-#else
-#define PWR_ON 0x600 /* Power On */
-#define SD_CMD_OD 0x800 /* Open Drain Output */
-#define BOOT_EN 0x1000 /* Boot Enable */
-#define BOOT_MODE 0x2000 /* Alternate Boot Mode */
-#define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */
-#endif
-
-/* Bit masks for SDH_RD_WAIT_EN */
-#define RWR 0x1 /* Read Wait Request */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h
deleted file mode 100644
index 869dcb08f5fc..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/spi.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * SPI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_SPI__
-#define __BFIN_PERIPHERAL_SPI__
-
-/* SPI_CTL Masks */
-#define TIMOD 0x0003 /* Transfer Initiate Mode */
-#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
-#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
-#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
-#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
-#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
-#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
-#define PSSE 0x0010 /* Slave-Select Input Enable */
-#define EMISO 0x0020 /* Enable MISO As Output */
-#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
-#define LSBF 0x0200 /* LSB First */
-#define CPHA 0x0400 /* Clock Phase */
-#define CPOL 0x0800 /* Clock Polarity */
-#define MSTR 0x1000 /* Master/Slave* */
-#define WOM 0x2000 /* Write Open Drain Master */
-#define SPE 0x4000 /* SPI Enable */
-
-/* SPI_FLG Masks */
-#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
-#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
-#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
-#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
-#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
-#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
-#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h b/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
deleted file mode 100644
index 3368712e3f98..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/spi6xx.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Analog Devices bfin_spi3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#include <linux/types.h>
-
-/* SPI_CONTROL */
-#define SPI_CTL_EN 0x00000001 /* Enable */
-#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
-#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
-#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
-#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
-#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
-#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
-#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in transfers */
-#define SPI_CTL_EMISO 0x00000100 /*Enable MISO */
-#define SPI_CTL_SIZE 0x00000600 /*Word Transfer Size */
-#define SPI_CTL_SIZE08 0x00000000 /*SIZE: 8 bits */
-#define SPI_CTL_SIZE16 0x00000200 /*SIZE: 16 bits */
-#define SPI_CTL_SIZE32 0x00000400 /*SIZE: 32 bits */
-#define SPI_CTL_LSBF 0x00001000 /*LSB First */
-#define SPI_CTL_FCEN 0x00002000 /*Flow-Control Enable */
-#define SPI_CTL_FCCH 0x00004000 /*Flow-Control Channel Selection */
-#define SPI_CTL_FCPL 0x00008000 /*Flow-Control Polarity */
-#define SPI_CTL_FCWM 0x00030000 /*Flow-Control Water-Mark */
-#define SPI_CTL_FIFO0 0x00000000 /*FCWM: Tx empty or Rx Full */
-#define SPI_CTL_FIFO1 0x00010000 /*FCWM: Tx empty or Rx full (>=75%) */
-#define SPI_CTL_FIFO2 0x00020000 /*FCWM: Tx empty or Rx full (>=50%) */
-#define SPI_CTL_FMODE 0x00040000 /*Fast-mode Enable */
-#define SPI_CTL_MIOM 0x00300000 /*Multiple I/O Mode */
-#define SPI_CTL_MIO_DIS 0x00000000 /*MIOM: Disable */
-#define SPI_CTL_MIO_DUAL 0x00100000 /*MIOM: Enable DIOM (Dual I/O Mode) */
-#define SPI_CTL_MIO_QUAD 0x00200000 /*MIOM: Enable QUAD (Quad SPI Mode) */
-#define SPI_CTL_SOSI 0x00400000 /*Start on MOSI */
-/* SPI_RX_CONTROL */
-#define SPI_RXCTL_REN 0x00000001 /*Receive Channel Enable */
-#define SPI_RXCTL_RTI 0x00000004 /*Receive Transfer Initiate */
-#define SPI_RXCTL_RWCEN 0x00000008 /*Receive Word Counter Enable */
-#define SPI_RXCTL_RDR 0x00000070 /*Receive Data Request */
-#define SPI_RXCTL_RDR_DIS 0x00000000 /*RDR: Disabled */
-#define SPI_RXCTL_RDR_NE 0x00000010 /*RDR: RFIFO not empty */
-#define SPI_RXCTL_RDR_25 0x00000020 /*RDR: RFIFO 25% full */
-#define SPI_RXCTL_RDR_50 0x00000030 /*RDR: RFIFO 50% full */
-#define SPI_RXCTL_RDR_75 0x00000040 /*RDR: RFIFO 75% full */
-#define SPI_RXCTL_RDR_FULL 0x00000050 /*RDR: RFIFO full */
-#define SPI_RXCTL_RDO 0x00000100 /*Receive Data Over-Run */
-#define SPI_RXCTL_RRWM 0x00003000 /*FIFO Regular Water-Mark */
-#define SPI_RXCTL_RWM_0 0x00000000 /*RRWM: RFIFO Empty */
-#define SPI_RXCTL_RWM_25 0x00001000 /*RRWM: RFIFO 25% full */
-#define SPI_RXCTL_RWM_50 0x00002000 /*RRWM: RFIFO 50% full */
-#define SPI_RXCTL_RWM_75 0x00003000 /*RRWM: RFIFO 75% full */
-#define SPI_RXCTL_RUWM 0x00070000 /*FIFO Urgent Water-Mark */
-#define SPI_RXCTL_UWM_DIS 0x00000000 /*RUWM: Disabled */
-#define SPI_RXCTL_UWM_25 0x00010000 /*RUWM: RFIFO 25% full */
-#define SPI_RXCTL_UWM_50 0x00020000 /*RUWM: RFIFO 50% full */
-#define SPI_RXCTL_UWM_75 0x00030000 /*RUWM: RFIFO 75% full */
-#define SPI_RXCTL_UWM_FULL 0x00040000 /*RUWM: RFIFO full */
-/* SPI_TX_CONTROL */
-#define SPI_TXCTL_TEN 0x00000001 /*Transmit Channel Enable */
-#define SPI_TXCTL_TTI 0x00000004 /*Transmit Transfer Initiate */
-#define SPI_TXCTL_TWCEN 0x00000008 /*Transmit Word Counter Enable */
-#define SPI_TXCTL_TDR 0x00000070 /*Transmit Data Request */
-#define SPI_TXCTL_TDR_DIS 0x00000000 /*TDR: Disabled */
-#define SPI_TXCTL_TDR_NF 0x00000010 /*TDR: TFIFO not full */
-#define SPI_TXCTL_TDR_25 0x00000020 /*TDR: TFIFO 25% empty */
-#define SPI_TXCTL_TDR_50 0x00000030 /*TDR: TFIFO 50% empty */
-#define SPI_TXCTL_TDR_75 0x00000040 /*TDR: TFIFO 75% empty */
-#define SPI_TXCTL_TDR_EMPTY 0x00000050 /*TDR: TFIFO empty */
-#define SPI_TXCTL_TDU 0x00000100 /*Transmit Data Under-Run */
-#define SPI_TXCTL_TRWM 0x00003000 /*FIFO Regular Water-Mark */
-#define SPI_TXCTL_RWM_FULL 0x00000000 /*TRWM: TFIFO full */
-#define SPI_TXCTL_RWM_25 0x00001000 /*TRWM: TFIFO 25% empty */
-#define SPI_TXCTL_RWM_50 0x00002000 /*TRWM: TFIFO 50% empty */
-#define SPI_TXCTL_RWM_75 0x00003000 /*TRWM: TFIFO 75% empty */
-#define SPI_TXCTL_TUWM 0x00070000 /*FIFO Urgent Water-Mark */
-#define SPI_TXCTL_UWM_DIS 0x00000000 /*TUWM: Disabled */
-#define SPI_TXCTL_UWM_25 0x00010000 /*TUWM: TFIFO 25% empty */
-#define SPI_TXCTL_UWM_50 0x00020000 /*TUWM: TFIFO 50% empty */
-#define SPI_TXCTL_UWM_75 0x00030000 /*TUWM: TFIFO 75% empty */
-#define SPI_TXCTL_UWM_EMPTY 0x00040000 /*TUWM: TFIFO empty */
-/* SPI_CLOCK */
-#define SPI_CLK_BAUD 0x0000FFFF /*Baud Rate */
-/* SPI_DELAY */
-#define SPI_DLY_STOP 0x000000FF /*Transfer delay time */
-#define SPI_DLY_LEADX 0x00000100 /*Extended (1 SCK) LEAD Control */
-#define SPI_DLY_LAGX 0x00000200 /*Extended (1 SCK) LAG control */
-/* SPI_SSEL */
-#define SPI_SLVSEL_SSE1 0x00000002 /*SPISSEL1 Enable */
-#define SPI_SLVSEL_SSE2 0x00000004 /*SPISSEL2 Enable */
-#define SPI_SLVSEL_SSE3 0x00000008 /*SPISSEL3 Enable */
-#define SPI_SLVSEL_SSE4 0x00000010 /*SPISSEL4 Enable */
-#define SPI_SLVSEL_SSE5 0x00000020 /*SPISSEL5 Enable */
-#define SPI_SLVSEL_SSE6 0x00000040 /*SPISSEL6 Enable */
-#define SPI_SLVSEL_SSE7 0x00000080 /*SPISSEL7 Enable */
-#define SPI_SLVSEL_SSEL1 0x00000200 /*SPISSEL1 Value */
-#define SPI_SLVSEL_SSEL2 0x00000400 /*SPISSEL2 Value */
-#define SPI_SLVSEL_SSEL3 0x00000800 /*SPISSEL3 Value */
-#define SPI_SLVSEL_SSEL4 0x00001000 /*SPISSEL4 Value */
-#define SPI_SLVSEL_SSEL5 0x00002000 /*SPISSEL5 Value */
-#define SPI_SLVSEL_SSEL6 0x00004000 /*SPISSEL6 Value */
-#define SPI_SLVSEL_SSEL7 0x00008000 /*SPISSEL7 Value */
-/* SPI_RWC */
-#define SPI_RWC_VALUE 0x0000FFFF /*Received Word-Count */
-/* SPI_RWCR */
-#define SPI_RWCR_VALUE 0x0000FFFF /*Received Word-Count Reload */
-/* SPI_TWC */
-#define SPI_TWC_VALUE 0x0000FFFF /*Transmitted Word-Count */
-/* SPI_TWCR */
-#define SPI_TWCR_VALUE 0x0000FFFF /*Transmitted Word-Count Reload */
-/* SPI_IMASK */
-#define SPI_IMSK_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_MFM 0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_RSM 0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_TSM 0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_RFM 0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_IMASKCL */
-#define SPI_IMSK_CLR_RUW 0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_CLR_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_CLR_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_CLR_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_CLR_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_CLR_MFM 0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_CLR_RSM 0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_CLR_TSM 0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_CLR_RFM 0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_CLR_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_IMASKST */
-#define SPI_IMSK_SET_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */
-#define SPI_IMSK_SET_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
-#define SPI_IMSK_SET_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
-#define SPI_IMSK_SET_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
-#define SPI_IMSK_SET_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
-#define SPI_IMSK_SET_MFM 0x00000080 /*Mode Fault Interrupt Mask */
-#define SPI_IMSK_SET_RSM 0x00000100 /*Receive Start Interrupt Mask */
-#define SPI_IMSK_SET_TSM 0x00000200 /*Transmit Start Interrupt Mask */
-#define SPI_IMSK_SET_RFM 0x00000400 /*Receive Finish Interrupt Mask */
-#define SPI_IMSK_SET_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
-/* SPI_STATUS */
-#define SPI_STAT_SPIF 0x00000001 /*SPI Finished */
-#define SPI_STAT_RUWM 0x00000002 /*Receive Water-Mark Breached */
-#define SPI_STAT_TUWM 0x00000004 /*Transmit Water-Mark Breached */
-#define SPI_STAT_ROE 0x00000010 /*Receive Over-Run Indication */
-#define SPI_STAT_TUE 0x00000020 /*Transmit Under-Run Indication */
-#define SPI_STAT_TCE 0x00000040 /*Transmit Collision Indication */
-#define SPI_STAT_MODF 0x00000080 /*Mode Fault Indication */
-#define SPI_STAT_RS 0x00000100 /*Receive Start Indication */
-#define SPI_STAT_TS 0x00000200 /*Transmit Start Indication */
-#define SPI_STAT_RF 0x00000400 /*Receive Finish Indication */
-#define SPI_STAT_TF 0x00000800 /*Transmit Finish Indication */
-#define SPI_STAT_RFS 0x00007000 /*SPI_RFIFO status */
-#define SPI_STAT_RFIFO_EMPTY 0x00000000 /*RFS: RFIFO Empty */
-#define SPI_STAT_RFIFO_25 0x00001000 /*RFS: RFIFO 25% Full */
-#define SPI_STAT_RFIFO_50 0x00002000 /*RFS: RFIFO 50% Full */
-#define SPI_STAT_RFIFO_75 0x00003000 /*RFS: RFIFO 75% Full */
-#define SPI_STAT_RFIFO_FULL 0x00004000 /*RFS: RFIFO Full */
-#define SPI_STAT_TFS 0x00070000 /*SPI_TFIFO status */
-#define SPI_STAT_TFIFO_FULL 0x00000000 /*TFS: TFIFO full */
-#define SPI_STAT_TFIFO_25 0x00010000 /*TFS: TFIFO 25% empty */
-#define SPI_STAT_TFIFO_50 0x00020000 /*TFS: TFIFO 50% empty */
-#define SPI_STAT_TFIFO_75 0x00030000 /*TFS: TFIFO 75% empty */
-#define SPI_STAT_TFIFO_EMPTY 0x00040000 /*TFS: TFIFO empty */
-#define SPI_STAT_FCS 0x00100000 /*Flow-Control Stall Indication */
-#define SPI_STAT_RFE 0x00400000 /*SPI_RFIFO Empty */
-#define SPI_STAT_TFF 0x00800000 /*SPI_TFIFO Full */
-/* SPI_ILAT */
-#define SPI_ILAT_RUWMI 0x00000002 /*Receive Water Mark Interrupt */
-#define SPI_ILAT_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */
-#define SPI_ILAT_ROI 0x00000010 /*Receive Over-Run Indication */
-#define SPI_ILAT_TUI 0x00000020 /*Transmit Under-Run Indication */
-#define SPI_ILAT_TCI 0x00000040 /*Transmit Collision Indication */
-#define SPI_ILAT_MFI 0x00000080 /*Mode Fault Indication */
-#define SPI_ILAT_RSI 0x00000100 /*Receive Start Indication */
-#define SPI_ILAT_TSI 0x00000200 /*Transmit Start Indication */
-#define SPI_ILAT_RFI 0x00000400 /*Receive Finish Indication */
-#define SPI_ILAT_TFI 0x00000800 /*Transmit Finish Indication */
-/* SPI_ILATCL */
-#define SPI_ILAT_CLR_RUWMI 0x00000002 /*Receive Water Mark Interrupt */
-#define SPI_ILAT_CLR_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */
-#define SPI_ILAT_CLR_ROI 0x00000010 /*Receive Over-Run Indication */
-#define SPI_ILAT_CLR_TUI 0x00000020 /*Transmit Under-Run Indication */
-#define SPI_ILAT_CLR_TCI 0x00000040 /*Transmit Collision Indication */
-#define SPI_ILAT_CLR_MFI 0x00000080 /*Mode Fault Indication */
-#define SPI_ILAT_CLR_RSI 0x00000100 /*Receive Start Indication */
-#define SPI_ILAT_CLR_TSI 0x00000200 /*Transmit Start Indication */
-#define SPI_ILAT_CLR_RFI 0x00000400 /*Receive Finish Indication */
-#define SPI_ILAT_CLR_TFI 0x00000800 /*Transmit Finish Indication */
-
-/*
- * bfin spi3 registers layout
- */
-struct bfin_spi_regs {
- u32 revid;
- u32 control;
- u32 rx_control;
- u32 tx_control;
- u32 clock;
- u32 delay;
- u32 ssel;
- u32 rwc;
- u32 rwcr;
- u32 twc;
- u32 twcr;
- u32 reserved0;
- u32 emask;
- u32 emaskcl;
- u32 emaskst;
- u32 reserved1;
- u32 status;
- u32 elat;
- u32 elatcl;
- u32 reserved2;
- u32 rfifo;
- u32 reserved3;
- u32 tfifo;
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/timer.h b/arch/blackfin/include/asm/mach-common/bits/timer.h
deleted file mode 100644
index 9513f80c05fe..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/timer.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * General Purpose Timer Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TIMER__
-#define __BFIN_PERIPHERAL_TIMER__
-
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/trace.h b/arch/blackfin/include/asm/mach-common/bits/trace.h
deleted file mode 100644
index 13e2134ab323..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/trace.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Trace Unit Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TRACE__
-#define __BFIN_PERIPHERAL_TRACE__
-
-/* Trace Buffer Control (TBUFCTL) Register Masks */
-#define TBUFPWR 0x00000001
-#define TBUFEN 0x00000002
-#define TBUFOVF 0x00000004
-#define CMPLB_SINGLE 0x00000008
-#define CMPLP_DOUBLE 0x00000010
-#define CMPLB (CMPLB_SINGLE | CMPLP_DOUBLE)
-
-/* Trace Buffer Status (TBUFSTAT) Register Masks */
-#define TBUFCNT 0x0000001F
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/twi.h b/arch/blackfin/include/asm/mach-common/bits/twi.h
deleted file mode 100644
index 8fa7d9f3b5c5..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/twi.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * TWI Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_TWI__
-#define __BFIN_PERIPHERAL_TWI__
-
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
-#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA 0x0080 /* TWI Enable */
-#define SCCB 0x0200 /* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define SEN 0x0001 /* Slave Enable */
-#define SADD_LEN 0x0002 /* Slave Address Length */
-#define STDVAL 0x0004 /* Slave Transmit Data Valid */
-#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN 0x0010 /* General Call Adrress Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL 0x0002 /* General Call Indicator */
-
-/* TWI_MASTER_CTRL Masks */
-#define MEN 0x0001 /* Master Mode Enable */
-#define MADD_LEN 0x0002 /* Master Address Length */
-#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
-#define FAST 0x0008 /* Use Fast Mode Timing Specs */
-#define STOP 0x0010 /* Issue Stop Condition */
-#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT 0x3FC0 /* Data Bytes To Transfer */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG 0x0001 /* Master Transfer In Progress */
-#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK 0x0004 /* Address Not Acknowledged */
-#define DNAK 0x0008 /* Data Not Acknowledged */
-#define BUFRDERR 0x0010 /* Buffer Read Error */
-#define BUFWRERR 0x0020 /* Buffer Write Error */
-#define SDASEN 0x0040 /* Serial Data Sense */
-#define SCLSEN 0x0080 /* Serial Clock Sense */
-#define BUSBUSY 0x0100 /* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT 0x0001 /* Slave Transfer Initiated */
-#define SCOMP 0x0002 /* Slave Transfer Complete */
-#define SERR 0x0004 /* Slave Transfer Error */
-#define SOVF 0x0008 /* Slave Overflow */
-#define MCOMP 0x0010 /* Master Transfer Complete */
-#define MERR 0x0020 /* Master Transfer Error */
-#define XMTSERV 0x0040 /* Transmit FIFO Service */
-#define RCVSERV 0x0080 /* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
-#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT 0x0003 /* Transmit FIFO Status */
-#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
-#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT 0x000C /* Receive FIFO Status */
-#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
-#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/uart.h b/arch/blackfin/include/asm/mach-common/bits/uart.h
deleted file mode 100644
index ac1ba11f5a00..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/uart.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * UART Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_UART__
-#define __BFIN_PERIPHERAL_UART__
-
-/* UARTx_LCR Masks */
-#define WLS 0x03 /* Word Length Select */
-#define WLS_5 0x00 /* 5 bit word */
-#define WLS_6 0x01 /* 6 bit word */
-#define WLS_7 0x02 /* 7 bit word */
-#define WLS_8 0x03 /* 8 bit word */
-#define STB 0x04 /* Stop Bits */
-#define PEN 0x08 /* Parity Enable */
-#define EPS 0x10 /* Even Parity Select */
-#define STP 0x20 /* Stick Parity */
-#define SB 0x40 /* Set Break */
-#define DLAB 0x80 /* Divisor Latch Access */
-
-#define DLAB_P 0x07
-#define SB_P 0x06
-#define STP_P 0x05
-#define EPS_P 0x04
-#define PEN_P 0x03
-#define STB_P 0x02
-#define WLS_P1 0x01
-#define WLS_P0 0x00
-
-/* UARTx_MCR Mask */
-#define XOFF 0x01 /* Transmitter off */
-#define MRTS 0x02 /* Manual Request to Send */
-#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x08 /* Receive FIFO RTS Threshold */
-#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define ARTS 0x40 /* Auto RTS generation for RX handshake */
-#define ACTS 0x80 /* Auto CTS operation for TX handshake */
-
-#define XOFF_P 0
-#define MRTS_P 1
-#define RFIT_P 2
-#define RFRT_P 3
-#define LOOP_ENA_P 4
-#define FCPOL_P 5
-#define ARTS_P 6
-#define ACTS_P 7
-
-/* UARTx_LSR Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x40 /* TSR and UART_THR Empty */
-
-#define DR_P 0x00
-#define OE_P 0x01
-#define PE_P 0x02
-#define FE_P 0x03
-#define BI_P 0x04
-#define THRE_P 0x05
-#define TEMT_P 0x06
-
-/* UARTx_IER Masks */
-#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
-#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI 0x04 /* Enable RX Status Interrupt */
-
-#define ERBFI_P 0x00
-#define ETBEI_P 0x01
-#define ELSI_P 0x02
-
-/* UARTx_IIR Masks */
-#define NINT 0x01 /* Pending Interrupt */
-#define STATUS 0x06 /* Highest Priority Pending Interrupt */
-
-#define NINT_P 0x00
-#define STATUS_P0 0x01
-#define STATUS_P1 0x02
-
-/* UARTx_GCTL Masks */
-#define UCEN 0x01 /* Enable UARTx Clocks */
-#define IREN 0x02 /* Enable IrDA Mode */
-#define TPOLC 0x04 /* IrDA TX Polarity Change */
-#define RPOLC 0x08 /* IrDA RX Polarity Change */
-#define FPE 0x10 /* Force Parity Error On Transmit */
-#define FFE 0x20 /* Force Framing Error On Transmit */
-
-#define UCEN_P 0x00
-#define IREN_P 0x01
-#define TPOLC_P 0x02
-#define RPOLC_P 0x03
-#define FPE_P 0x04
-#define FFE_P 0x05
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/uart4.h b/arch/blackfin/include/asm/mach-common/bits/uart4.h
deleted file mode 100644
index 37808de243d2..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/uart4.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * UART4 Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_UART4__
-#define __BFIN_PERIPHERAL_UART4__
-
-/* UART_CONTROL */
-#define UEN (1 << 0)
-#define LOOP_ENA (1 << 1)
-#define UMOD (3 << 4)
-#define UMOD_UART (0 << 4)
-#define UMOD_MDB (1 << 4)
-#define UMOD_IRDA (1 << 4)
-#define WLS (3 << 8)
-#define WLS_5 (0 << 8)
-#define WLS_6 (1 << 8)
-#define WLS_7 (2 << 8)
-#define WLS_8 (3 << 8)
-#define STB (1 << 12)
-#define STBH (1 << 13)
-#define PEN (1 << 14)
-#define EPS (1 << 15)
-#define STP (1 << 16)
-#define FPE (1 << 17)
-#define FFE (1 << 18)
-#define SB (1 << 19)
-#define FCPOL (1 << 22)
-#define RPOLC (1 << 23)
-#define TPOLC (1 << 24)
-#define MRTS (1 << 25)
-#define XOFF (1 << 26)
-#define ARTS (1 << 27)
-#define ACTS (1 << 28)
-#define RFIT (1 << 29)
-#define RFRT (1 << 30)
-
-/* UART_STATUS */
-#define DR (1 << 0)
-#define OE (1 << 1)
-#define PE (1 << 2)
-#define FE (1 << 3)
-#define BI (1 << 4)
-#define THRE (1 << 5)
-#define TEMT (1 << 7)
-#define TFI (1 << 8)
-#define ASTKY (1 << 9)
-#define ADDR (1 << 10)
-#define RO (1 << 11)
-#define SCTS (1 << 12)
-#define CTS (1 << 16)
-#define RFCS (1 << 17)
-
-/* UART_EMASK */
-#define ERBFI (1 << 0)
-#define ETBEI (1 << 1)
-#define ELSI (1 << 2)
-#define EDSSI (1 << 3)
-#define EDTPTI (1 << 4)
-#define ETFI (1 << 5)
-#define ERFCI (1 << 6)
-#define EAWI (1 << 7)
-#define ERXS (1 << 8)
-#define ETXS (1 << 9)
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/usb.h b/arch/blackfin/include/asm/mach-common/bits/usb.h
deleted file mode 100644
index c6390589bc10..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/usb.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * USB Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_USB__
-#define __BFIN_PERIPHERAL_USB__
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */
-#define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */
-#define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x01 /* Suspend indicator */
-#define RESUME_B 0x02 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */
-#define SOF_B 0x08 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x01 /* Suspend indicator int enable */
-#define RESUME_BE 0x02 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */
-#define SOF_BE 0x08 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x0001 /* enables USB module */
-#define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/watchdog.h b/arch/blackfin/include/asm/mach-common/bits/watchdog.h
deleted file mode 100644
index 75924f92f99a..000000000000
--- a/arch/blackfin/include/asm/mach-common/bits/watchdog.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Watchdog Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_WATCHDOG__
-#define __BFIN_PERIPHERAL_WATCHDOG__
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV 0x0006 /* event generated on roll over */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
deleted file mode 100644
index 3e361d614a93..000000000000
--- a/arch/blackfin/include/asm/mem_map.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE 0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SRAM_SCRATCH
-# define L1_SRAM_SCRATCH 0xFFB00000
-# define L1_SRAM_SCRATCH_SIZE 0x1000
-# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
deleted file mode 100644
index 003694b515a0..000000000000
--- a/arch/blackfin/include/asm/portmux.h
+++ /dev/null
@@ -1,1193 +0,0 @@
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x) ((x) & 0x1FF)
-#define P_FUNCT(x) (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
-#define P_DEFINED 0x8000
-#define P_UNDEF 0x4000
-#define P_MAYSHARE 0x2000
-#define P_DONTCARE 0x1000
-
-#ifndef __ASSEMBLY__
-
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-
-#endif
-
-#include <asm/blackfin.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
deleted file mode 100644
index 8535235031e7..000000000000
--- a/arch/blackfin/include/asm/posix_types.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * U-Boot - posix_types.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
-#define __ARCH_BLACKFIN_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_dev_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef __FD_SET
-#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-
-#undef __FD_CLR
-#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-
-#undef __FD_ISSET
-#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-
-#undef __FD_ZERO
-#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-
-#endif /* defined(__KERNEL__) */
-
-#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index 1daf59bc875b..000000000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * U-Boot - processor.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * This file is based on
- * include/asm-m68k/processor.h
- * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
- * Copyright (C) 1995 Hamish Macdonald
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_BLACKFIN_PROCESSOR_H
-#define __ASM_BLACKFIN_PROCESSOR_H
-
-/* Stub to make stupid common code happy */
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index 251d5e60c820..000000000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- * -----------------------------
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- long orig_pc;
- long ipend;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc; /* PC == RETI */
- long rets;
- long reserved; /* Used as scratch during system calls */
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
- long orig_p0;
- long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#define PS_S (0x0002)
-
-#ifdef __KERNEL__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
- master interrupt enable. */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs) ((regs)->usp)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#define arch_has_single_step() (1)
-extern void user_enable_single_step(struct task_struct *);
-/* see arch/blackfin/kernel/ptrace.c about this redirect */
-#define user_disable_single_step(child) ptrace_disable(child)
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
- (struct pt_regs *) \
- ((unsigned long)task_stack_page(task) + \
- (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/sdh.h b/arch/blackfin/include/asm/sdh.h
deleted file mode 100644
index 2c2f63ed55fd..000000000000
--- a/arch/blackfin/include/asm/sdh.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * sdh.h, export bfin_mmc_init
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SDH_H__
-#define __ASM_SDH_H__
-
-#include <mmc.h>
-#include <asm/u-boot.h>
-
-int bfin_mmc_init(bd_t *bis);
-
-#endif
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index 1ea1c4184750..000000000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_BLACKFIN_SECTIONS_H
-#define __ASM_BLACKFIN_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
deleted file mode 100644
index 87a337d1b4e8..000000000000
--- a/arch/blackfin/include/asm/serial.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL_H__
-#define __BFIN_CPU_SERIAL_H__
-
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_UART_CONSOLE
-# define CONFIG_UART_CONSOLE 0
-#endif
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define BFIN_DEBUG_EARLY_SERIAL 1
-#else
-# define BFIN_DEBUG_EARLY_SERIAL 0
-#endif
-
-#if defined(__ADSPBF60x__)
-# define BFIN_UART_HW_VER 4
-#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
-# define BFIN_UART_HW_VER 2
-#else
-# define BFIN_UART_HW_VER 1
-#endif
-
-#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
-#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
-#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
-
-#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
-
-#ifndef __ASSEMBLY__
-__attribute__((always_inline))
-static inline void serial_do_portmux(void);
-#endif
-
-#if BFIN_UART_HW_VER < 4
-# include "serial1.h"
-#else
-# include "serial4.h"
-#endif
-
-#ifndef __ASSEMBLY__
-
-__attribute__((always_inline))
-static inline void serial_do_portmux(void)
-{
- if (!BFIN_DEBUG_EARLY_SERIAL) {
- const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
- peripheral_request_list(pins, "bfin-uart");
- return;
- }
-
- serial_early_do_portmux();
-}
-
-#ifndef BFIN_IN_INITCODE
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
- if (BFIN_DEBUG_EARLY_SERIAL) {
- serial_puts("Early: ");
- serial_puts(s);
- }
-}
-#endif
-
-#else
-
-.macro serial_early_init
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
- call __serial_early_init;
-#endif
-.endm
-
-.macro serial_early_set_baud
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
- R0.L = LO(CONFIG_BAUDRATE);
- R0.H = HI(CONFIG_BAUDRATE);
- call __serial_early_set_baud;
-#endif
-.endm
-
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-#define update_serial_early_string_addr \
- R1.L = _start; \
- R1.H = _start; \
- R0 = R0 - R1; \
- R1.L = 0; \
- R1.H = 0x2000; \
- R0 = R0 + R1;
-#else
-#define update_serial_early_string_addr
-#endif
-
-/* Since we embed the string right into our .text section, we need
- * to find its address. We do this by getting our PC and adding 2
- * bytes (which is the length of the jump instruction). Then we
- * pass this address to serial_puts().
- */
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define serial_early_puts(str) \
- .section .rodata; \
- 7: \
- .ascii "Early:"; \
- .ascii __FILE__; \
- .ascii ": "; \
- .ascii str; \
- .asciz "\n"; \
- .previous; \
- R0.L = 7b; \
- R0.H = 7b; \
- update_serial_early_string_addr \
- call _uart_early_puts;
-#else
-# define serial_early_puts(str)
-#endif
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/serial1.h b/arch/blackfin/include/asm/serial1.h
deleted file mode 100644
index 467d3817f169..000000000000
--- a/arch/blackfin/include/asm/serial1.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL1_H__
-#define __BFIN_CPU_SERIAL1_H__
-
-#include <asm/mach-common/bits/uart.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
-#ifdef UART_DLL
-# define UART0_DLL UART_DLL
-# if CONFIG_UART_CONSOLE != 0
-# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
-# endif
-#endif
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-#define LOB(x) ((x) & 0xFF)
-#define HIB(x) (((x) >> 8) & 0xFF)
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-struct bfin_mmr_serial {
-#if BFIN_UART_HW_VER == 2
- u16 dll;
- u16 __pad_0;
- u16 dlh;
- u16 __pad_1;
- u16 gctl;
- u16 __pad_2;
- u16 lcr;
- u16 __pad_3;
- u16 mcr;
- u16 __pad_4;
- u16 lsr;
- u16 __pad_5;
- u16 msr;
- u16 __pad_6;
- u16 scr;
- u16 __pad_7;
- u16 ier_set;
- u16 __pad_8;
- u16 ier_clear;
- u16 __pad_9;
- u16 thr;
- u16 __pad_10;
- u16 rbr;
- u16 __pad_11;
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __spad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __spad1;
- const u16 iir;
- u16 __pad_0;
- u16 lcr;
- u16 __pad_1;
- u16 mcr;
- u16 __pad_2;
- u16 lsr;
- u16 __pad_3;
- u16 msr;
- u16 __pad_4;
- u16 scr;
- u16 __pad_5;
- const u32 __spad2;
- u16 gctl;
- u16 __pad_6;
-#endif
-};
-
-#define uart_lsr_t uint32_t
-#define _lsr_read(p) bfin_read(&p->lsr)
-#define _lsr_write(p, v) bfin_write(&p->lsr, v)
-
-#if BFIN_UART_HW_VER == 2
-# define ACCESS_LATCH()
-# define ACCESS_PORT_IER()
-#else
-# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB)
-# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
- int mux_func, int port_pin)
-{
- switch (port) {
-#if defined(__ADSPBF54x__)
- case 'B':
- bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
- break;
- case 'E':
- bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
- break;
-#endif
-#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
- case 'F':
- bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
- break;
- case 'G':
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
- break;
- case 'H':
- bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
- break;
-#endif
- default:
- break;
- }
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF50x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
- break;
- case 1:
- serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
- serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
- break;
- }
-#elif defined(__ADSPBF51x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
- break;
- case 1:
- serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
- serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
- break;
- }
-#elif defined(__ADSPBF52x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
- PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
- PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
- break;
- case 1:
- serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
- serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
- break;
- }
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
- const uint16_t func[] = { PFDE, PFTE, };
- bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
- (1 << P_IDENT(P_UART(RX))) |
- (1 << P_IDENT(P_UART(TX))));
-#elif defined(__ADSPBF54x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
- serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
- PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
- break;
- case 1:
- serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
- PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
- serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
- PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
- break;
- case 2:
- serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
- PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
- serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
- break;
- case 3:
- serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
- PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
- serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
- break;
- }
-#elif defined(__ADSPBF561__)
- /* UART pins could be GPIO, but they aren't pin muxed. */
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-# error "missing portmux logic for UART"
-# endif
-#endif
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
- /* always enable UART -- avoids anomalies 05000309 and 05000350 */
- bfin_write(&pUART->gctl, UCEN);
-
- /* Set LCR to Word Lengh 8-bit word select */
- bfin_write(&pUART->lcr, WLS_8);
-
- SSYNC();
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
- return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
- /* disable the UART by clearing UCEN */
- bfin_write(&pUART->gctl, 0);
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->dll, LOB(divisor));
- bfin_write(&pUART->dlh, HIB(divisor));
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
- /* Translate from baud into divisor in terms of SCLK. The
- * weird multiplication is to make sure we over sample just
- * a little rather than under sample the incoming signals.
- */
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
- uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
- - ANOMALY_05000230;
-#else
- uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
- baud * 16) - ANOMALY_05000230;
-#endif
-
- serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint16_t divisor)
-{
- uint32_t uart_base = UART_BASE;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->dll, LOB(divisor));
- bfin_write(&pUART->dlh, HIB(divisor));
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
-{
- uint32_t uart_base = UART_BASE;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- uint8_t dll = bfin_read(&pUART->dll);
- uint8_t dlh = bfin_read(&pUART->dlh);
- uint16_t divisor = (dlh << 8) | dll;
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-
- return divisor;
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/serial4.h b/arch/blackfin/include/asm/serial4.h
deleted file mode 100644
index 65483960b9cb..000000000000
--- a/arch/blackfin/include/asm/serial4.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL4_H__
-#define __BFIN_CPU_SERIAL4_H__
-
-#include <asm/mach-common/bits/uart4.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-struct bfin_mmr_serial {
- u32 revid;
- u32 control;
- u32 status;
- u32 scr;
- u32 clock;
- u32 emask;
- u32 emaskst;
- u32 emaskcl;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv_cnt;
- u32 rxdiv_cnt;
-};
-#define uart_lsr_t uint32_t
-#define _lsr_read(p) bfin_read(&p->status)
-#define _lsr_write(p, v) bfin_write(&p->status, v)
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
- int mux_func, int port_pin)
-{
- switch (port) {
- case 'D':
- bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTD_FER_SET(port_pin);
- break;
- case 'G':
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTG_FER_SET(port_pin);
- break;
- }
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF60x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
- serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
- PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
- break;
- case 1:
- serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
- PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
- PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
- break;
- }
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-# error "missing portmux logic for UART"
-# endif
-#endif
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
- /* always enable UART to 8-bit mode */
- bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
-
- SSYNC();
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
- return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
- /* disable the UART by clearing UEN */
- bfin_write(&pUART->control, 0);
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->clock, divisor);
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
- uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
-
- /* Program the divisor to get the baud rate we want */
- serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint32_t divisor)
-{
- uint32_t uart_base = UART_BASE;
- bfin_write(&pUART->clock, divisor);
-}
-
-__attribute__((always_inline))
-static inline uint32_t serial_early_get_div(void)
-{
- uint32_t uart_base = UART_BASE;
- return bfin_read(&pUART->clock);
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/shared_resources.h b/arch/blackfin/include/asm/shared_resources.h
deleted file mode 100644
index 42dab9f12621..000000000000
--- a/arch/blackfin/include/asm/shared_resources.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * U-Boot - setup.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SHARED_RESOURCES_H_
-#define _SHARED_RESOURCES_H_
-
-void swap_to(int device_id);
-
-#define FLASH 0
-#define ETHERNET 1
-
-#endif /* _SHARED_RESOURCES_H_ */
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h
deleted file mode 100644
index 7b1573ce19de..000000000000
--- a/arch/blackfin/include/asm/signal.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/signal.h>
diff --git a/arch/blackfin/include/asm/soft_switch.h b/arch/blackfin/include/asm/soft_switch.h
deleted file mode 100644
index 321b0708257b..000000000000
--- a/arch/blackfin/include/asm/soft_switch.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __SOFT_SWITCH_H__
-#define __SOFT_SWITCH_H__
-
-#define IO_PORT_A 0
-#define IO_PORT_B 1
-#define IO_PORT_INPUT 0
-#define IO_PORT_OUTPUT 1
-
-int config_switch_bit(int num, int port, int bit, int dir, uchar value);
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 15f50f23cb70..000000000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * U-Boot - string.h String functions
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Changed by Lineo Inc. May 2001 */
-
-#ifndef _BLACKFINNOMMU_STRING_H_
-#define _BLACKFINNOMMU_STRING_H_
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRNCMP
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMMOVE
-
-extern char *strcpy(char *dest, const char *src);
-extern char *strncpy(char *dest, const char *src, size_t n);
-extern int strcmp(const char *cs, const char *ct);
-extern int strncmp(const char *cs, const char *ct, size_t count);
-extern void *memcpy(void *dest, const void *src, size_t count);
-extern void *memset(void *s, int c, size_t count);
-extern int memcmp(const void *, const void *, size_t);
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#else /* KERNEL */
-
-/*
- * let user libraries deal with these,
- * IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY 1
-#define __HAVE_ARCH_STRNCPY 1
-#define __HAVE_ARCH_STRCAT 1
-#define __HAVE_ARCH_STRNCAT 1
-#define __HAVE_ARCH_STRCMP 1
-#define __HAVE_ARCH_STRNCMP 1
-#define __HAVE_ARCH_STRNICMP 1
-#define __HAVE_ARCH_STRCHR 1
-#define __HAVE_ARCH_STRRCHR 1
-#define __HAVE_ARCH_STRSTR 1
-#define __HAVE_ARCH_STRLEN 1
-#define __HAVE_ARCH_STRNLEN 1
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-#define __HAVE_ARCH_MEMMOVE 1
-#define __HAVE_ARCH_MEMSCAN 1
-#define __HAVE_ARCH_MEMCMP 1
-#define __HAVE_ARCH_MEMCHR 1
-#define __HAVE_ARCH_STRTOK 1
-
-#endif /* KERNEL */
-
-#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
deleted file mode 100644
index f0c4ae260941..000000000000
--- a/arch/blackfin/include/asm/system.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * U-Boot - system.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-/*
- * Interrupt configuring macros.
- */
-
-extern int irq_flags;
-
-#define local_irq_enable() \
- __asm__ __volatile__ ( \
- "sti %0;" \
- : \
- : "d" (irq_flags) \
- )
-
-#define local_irq_disable() \
- do { \
- int __tmp_dummy; \
- __asm__ __volatile__ ( \
- "cli %0;" \
- : "=d" (__tmp_dummy) \
- ); \
- } while (0)
-
-# define local_irq_save(x) \
- __asm__ __volatile__ ( \
- "cli %0;" \
- : "=&d" (x) \
- )
-
-#define local_save_flags(x) \
- __asm__ __volatile__ ( \
- "cli %0;" \
- "sti %0;" \
- : "=d" (x) \
- )
-
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-
-#define local_irq_restore(x) \
- do { \
- if (irqs_enabled_from_flags(x)) \
- local_irq_enable(); \
- } while (0)
-
-/*
- * Force strict CPU ordering.
- */
-#define nop() asm volatile ("nop;\n\t"::)
-#define mb() asm volatile ("" : : :"memory")
-#define rmb() asm volatile ("" : : :"memory")
-#define wmb() asm volatile ("" : : :"memory")
-#define set_rmb(var, value) do { xchg(&var, value); } while (0)
-#define set_mb(var, value) set_rmb(var, value)
-#define set_wmb(var, value) do { var = value; wmb(); } while (0)
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy {
- unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp = 0;
- unsigned long flags = 0;
-
- local_irq_save(flags);
-
- switch (size) {
- case 1:
- __asm__ __volatile__
- ("%0 = b%2 (z);\n\t"
- "b%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 2:
- __asm__ __volatile__
- ("%0 = w%2 (z);\n\t"
- "w%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 4:
- __asm__ __volatile__
- ("%0 = %2;\n\t"
- "%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- }
- local_irq_restore(flags);
- return tmp;
-}
-
-void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif /* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index 7422d3d1be0a..000000000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2001 Lineo, Inc
- * Tony Kou
- * 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR (63)
-
-#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h
deleted file mode 100644
index 922cdbd892eb..000000000000
--- a/arch/blackfin/include/asm/twi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
- *
- * Copyright (c) 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_TWI_H
-#define __ARCH_TWI_H
-
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/twi.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index 4da64c450ebb..000000000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * U-Boot - types.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BLACKFIN_TYPES_H
-#define _BLACKFIN_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue. However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-/* HK0617 -- Changes to unsigned long temporarily */
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide. */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
deleted file mode 100644
index 1ada44edcdf8..000000000000
--- a/arch/blackfin/include/asm/u-boot.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * U-Boot - u-boot.h Structure declarations for board specific data
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_ 1
-
-typedef struct bd_info {
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- const char *bi_r_version;
- const char *bi_cpu;
- const char *bi_board_name;
- unsigned long bi_vco;
- unsigned long bi_cclk;
- unsigned long bi_sclk;
- unsigned char bi_enetaddr[6];
-} bd_t;
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_BLACKFIN
-
-int arch_misc_init(void);
-
-#endif /* _U_BOOT_H_ */
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb2111f..000000000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/lib/.gitignore b/arch/blackfin/lib/.gitignore
deleted file mode 100644
index 09f1be04eb56..000000000000
--- a/arch/blackfin/lib/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-u-boot.lds
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index de02c69dd26a..000000000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# U-Boot Makefile
-#
-# Copyright (c) 2005-2008 Analog Devices Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ins.o
-obj-y += memcmp.o
-obj-y += memcpy.o
-obj-y += memmove.o
-obj-y += memset.o
-obj-y += outs.o
-obj-$(CONFIG_CMD_KGDB) += __kgdb.o
-obj-y += boot.o
-obj-y += cache.o
-obj-y += clocks.o
-obj-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
-obj-$(CONFIG_CMD_KGDB) += kgdb.o
-obj-y += muldi3.o
-obj-$(CONFIG_HAS_POST) += post.o
-obj-y += string.o
-obj-y += sections.o
diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S
deleted file mode 100644
index 4e7b6a4eb5d4..000000000000
--- a/arch/blackfin/lib/__kgdb.S
+++ /dev/null
@@ -1,154 +0,0 @@
-#include <linux/linkage.h>
-
-/* save stack context for non-local goto
- * int kgdb_setjmp(long *buf)
- */
-
-ENTRY(_kgdb_setjmp)
- [--SP] = p0; /* Save P0 */
- p0 = r0;
- r0 = [SP++]; /* Load P0 into R0 */
-
- [p0 + 0x00] = r0; /* GP address registers */
- [p0 + 0x04] = p1;
- [p0 + 0x08] = p2;
- [p0 + 0x0C] = p3;
- [p0 + 0x10] = p4;
- [p0 + 0x14] = p5;
- [p0 + 0x18] = FP; /* frame pointer */
- [p0 + 0x1C] = SP; /* stack pointer */
-
- [p0 + 0x20] = p0; /* data regs */
- [p0 + 0x24] = r1;
- [p0 + 0x28] = r2;
- [p0 + 0x2C] = r3;
- [p0 + 0x30] = r4;
- [p0 + 0x34] = r5;
- [p0 + 0x38] = r6;
- [p0 + 0x3C] = r7;
-
- r0 = ASTAT; [p0 + 0x40] = r0;
-
- /* loop counters */
- r0 = LC0; [p0 + 0x44] = r0;
- r0 = LC1; [p0 + 0x48] = r0;
-
- /* Accumulator */
- r0 = A0.w; [p0 + 0x4C] = r0;
- r0.l = A0.x; [p0 + 0x50] = r0;
- r0 = A1.w; [p0 + 0x54] = r0;
- r0.l = A1.x; [p0 + 0x58] = r0;
-
- /* index registers */
- r0 = i0; [p0 + 0x5C] = r0;
- r0 = i1; [p0 + 0x60] = r0;
- r0 = i2; [p0 + 0x64] = r0;
- r0 = i3; [p0 + 0x68] = r0;
-
- /* modifier registers */
- r0 = m0; [p0 + 0x6C] = r0;
- r0 = m1; [p0 + 0x70] = r0;
- r0 = m2; [p0 + 0x74] = r0;
- r0 = m3; [p0 + 0x78] = r0;
-
- /* length registers */
- r0 = l0; [p0 + 0x7C] = r0;
- r0 = l1; [p0 + 0x80] = r0;
- r0 = l2; [p0 + 0x84] = r0;
- r0 = l3; [p0 + 0x88] = r0;
-
- /* base registers */
- r0 = b0; [p0 + 0x8C] = r0;
- r0 = b1; [p0 + 0x90] = r0;
- r0 = b2; [p0 + 0x94] = r0;
- r0 = b3; [p0 + 0x98] = r0;
-
- /* store return address */
- r0 = RETS; [p0 + 0x9C] = r0;
-
- R0 = 0;
- RTS;
-ENDPROC(_kgdb_setjmp)
-
-/*
- * non-local jump to a saved stack context
- * longjmp(long *buf, int val)
- */
-
-ENTRY(_kgdb_longjmp)
- p0 = r0;
- r0 = [p0 + 0x00];
- [--sp] = r0;
-
- /* GP address registers - skip p0 for now*/
- p1 = [p0 + 0x04];
- p2 = [p0 + 0x08];
- p3 = [p0 + 0x0C];
- p4 = [p0 + 0x10];
- p5 = [p0 + 0x14];
- /* frame pointer */
- fp = [p0 + 0x18];
- /* stack pointer */
- r0 = [sp++];
- sp = [p0 + 0x1C];
- [--sp] = r0;
- [--sp] = r1;
-
- /* data regs */
- r0 = [p0 + 0x20];
- r1 = [p0 + 0x24];
- r2 = [p0 + 0x28];
- r3 = [p0 + 0x2C];
- r4 = [p0 + 0x30];
- r5 = [p0 + 0x34];
- r6 = [p0 + 0x38];
- r7 = [p0 + 0x3C];
-
- r0 = [p0 + 0x40]; ASTAT = r0;
-
- /* loop counters */
- r0 = [p0 + 0x44]; LC0 = r0;
- r0 = [p0 + 0x48]; LC1 = r0;
-
- /* Accumulator */
- r0 = [p0 + 0x4C]; A0.w = r0;
- r0 = [p0 + 0x50]; A0.x = r0;
- r0 = [p0 + 0x54]; A1.w = r0;
- r0 = [p0 + 0x58]; A1.x = r0;
-
- /* index registers */
- r0 = [p0 + 0x5C]; i0 = r0;
- r0 = [p0 + 0x60]; i1 = r0;
- r0 = [p0 + 0x64]; i2 = r0;
- r0 = [p0 + 0x68]; i3 = r0;
-
- /* modifier registers */
- r0 = [p0 + 0x6C]; m0 = r0;
- r0 = [p0 + 0x70]; m1 = r0;
- r0 = [p0 + 0x74]; m2 = r0;
- r0 = [p0 + 0x78]; m3 = r0;
-
- /* length registers */
- r0 = [p0 + 0x7C]; l0 = r0;
- r0 = [p0 + 0x80]; l1 = r0;
- r0 = [p0 + 0x84]; l2 = r0;
- r0 = [p0 + 0x88]; l3 = r0;
-
- /* base registers */
- r0 = [p0 + 0x8C]; b0 = r0;
- r0 = [p0 + 0x90]; b1 = r0;
- r0 = [p0 + 0x94]; b2 = r0;
- r0 = [p0 + 0x98]; b3 = r0;
-
- /* store return address */
- r0 = [p0 + 0x9C]; RETS = r0;
-
- /* fixup R0 & P0 */
- r0 = [sp++];
- p0 = [sp++];
- CC = R0 == 0;
- IF !CC JUMP .Lfinished;
- R0 = 1;
-.Lfinished:
- RTS;
-ENDPROC(_kgdb_longjmp)
diff --git a/arch/blackfin/lib/boot.c b/arch/blackfin/lib/boot.c
deleted file mode 100644
index fd4c82e9c808..000000000000
--- a/arch/blackfin/lib/boot.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * U-Boot - boot.c - misc boot helper functions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <asm/blackfin.h>
-
-#ifdef SHARED_RESOURCES
-extern void swap_to(int device_id);
-#endif
-
-#ifdef CONFIG_VIDEO
-extern void video_stop(void);
-#endif
-
-static char *make_command_line(void)
-{
- char *dest = (char *)CONFIG_LINUX_CMDLINE_ADDR;
- char *bootargs = getenv("bootargs");
-
- if (bootargs == NULL)
- return NULL;
-
- strncpy(dest, bootargs, CONFIG_LINUX_CMDLINE_SIZE);
- dest[CONFIG_LINUX_CMDLINE_SIZE - 1] = 0;
- return dest;
-}
-
-extern ulong bfin_poweron_retx;
-
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
-{
- int (*appl) (char *cmdline);
- char *cmdline;
-
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
-#ifdef SHARED_RESOURCES
- swap_to(FLASH);
-#endif
-
-#ifdef CONFIG_VIDEO
- /* maybe this should be standardized and moved to bootm ... */
- video_stop();
-#endif
-
- appl = (int (*)(char *))images->ep;
-
- printf("Starting Kernel at = %p\n", appl);
- cmdline = make_command_line();
- icache_disable();
- dcache_disable();
- asm __volatile__(
- "RETX = %[retx];"
- "CALL (%0);"
- :
- : "p"(appl), "q0"(cmdline), [retx] "d"(bfin_poweron_retx)
- );
- /* does not return */
-
- return 1;
-}
diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c
deleted file mode 100644
index 8d933393b412..000000000000
--- a/arch/blackfin/lib/cache.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * U-Boot - cache.c
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- void *start_addr, *end_addr;
- int istatus, dstatus;
-
- /* no need to flush stuff in on chip memory (L1/L2/etc...) */
- if (addr >= 0xE0000000)
- return;
-
- start_addr = (void *)addr;
- end_addr = (void *)(addr + size);
- istatus = icache_status();
- dstatus = dcache_status();
-
- if (istatus) {
- if (dstatus)
- blackfin_icache_dcache_flush_range(start_addr, end_addr);
- else
- blackfin_icache_flush_range(start_addr, end_addr);
- } else if (dstatus)
- blackfin_dcache_flush_range(start_addr, end_addr);
-}
-
-#ifdef CONFIG_DCACHE_WB
-static void flushinv_all_dcache(void)
-{
- u32 way, bank, subbank, set;
- u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank)
- for (set = 0; set < 64; ++set) {
-
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* only worry about valid/dirty entries */
- if ((status & 0x3) != 0x3)
- continue;
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* flush it */
- __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
- }
- }
-}
-#endif
-
-void icache_enable(void)
-{
- bfin_write_IMEM_CONTROL(IMC | ENICPLB);
- SSYNC();
-}
-
-void icache_disable(void)
-{
- bfin_write_IMEM_CONTROL(0);
- SSYNC();
-}
-
-int icache_status(void)
-{
- return bfin_read_IMEM_CONTROL() & IMC;
-}
-
-void dcache_enable(void)
-{
- bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
- SSYNC();
-}
-
-void dcache_disable(void)
-{
-#ifdef CONFIG_DCACHE_WB
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
- flushinv_all_dcache();
-#endif
- bfin_write_DMEM_CONTROL(0);
- SSYNC();
-}
-
-int dcache_status(void)
-{
- return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
- blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
- blackfin_dcache_flush_range((const void *)start, (const void *)stop);
-}
diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c
deleted file mode 100644
index 7ed56a727427..000000000000
--- a/arch/blackfin/lib/clocks.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * clocks.c - figure out sclk/cclk/vco and such
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/clock.h>
-
-/* Get the voltage input multiplier */
-u_long get_vco(void)
-{
- static u_long cached_vco_pll_ctl, cached_vco;
-
- u_long msel, pll_ctl;
-
- pll_ctl = bfin_read_PLL_CTL();
- if (pll_ctl == cached_vco_pll_ctl)
- return cached_vco;
- else
- cached_vco_pll_ctl = pll_ctl;
-
- msel = (pll_ctl & MSEL) >> MSEL_P;
- if (0 == msel)
- msel = (MSEL >> MSEL_P) + 1;
-
- cached_vco = CONFIG_CLKIN_HZ;
- cached_vco >>= (pll_ctl & DF);
- cached_vco *= msel;
- return cached_vco;
-}
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
- static u_long cached_cclk_pll_div, cached_cclk;
- u_long div, csel;
-#ifndef CGU_DIV
- u_long ssel;
-#endif
-
- if (pll_is_bypassed())
- return CONFIG_CLKIN_HZ;
-
- div = bfin_read_PLL_DIV();
- if (div == cached_cclk_pll_div)
- return cached_cclk;
- else
- cached_cclk_pll_div = div;
-
- csel = (div & CSEL) >> CSEL_P;
-#ifndef CGU_DIV
- ssel = (div & SSEL) >> SSEL_P;
- if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
- cached_cclk = get_vco() / ssel;
- else
- cached_cclk = get_vco() >> csel;
-#else
- cached_cclk = get_vco() / csel;
-#endif
- return cached_cclk;
-}
-
-/* Get the System clock */
-#ifdef CGU_DIV
-
-static u_long cached_sclk_pll_div, cached_sclk;
-static u_long cached_sclk0, cached_sclk1, cached_dclk;
-static u_long _get_sclk(u_long *cache)
-{
- u_long div, ssel;
-
- if (pll_is_bypassed())
- return CONFIG_CLKIN_HZ;
-
- div = bfin_read_PLL_DIV();
- if (div == cached_sclk_pll_div)
- return *cache;
- else
- cached_sclk_pll_div = div;
-
- ssel = (div & SYSSEL) >> SYSSEL_P;
- cached_sclk = get_vco() / ssel;
-
- ssel = (div & S0SEL) >> S0SEL_P;
- cached_sclk0 = cached_sclk / ssel;
-
- ssel = (div & S1SEL) >> S1SEL_P;
- cached_sclk1 = cached_sclk / ssel;
-
- ssel = (div & DSEL) >> DSEL_P;
- cached_dclk = get_vco() / ssel;
-
- return *cache;
-}
-
-u_long get_sclk(void)
-{
- return _get_sclk(&cached_sclk);
-}
-
-u_long get_sclk0(void)
-{
- return _get_sclk(&cached_sclk0);
-}
-
-u_long get_sclk1(void)
-{
- return _get_sclk(&cached_sclk1);
-}
-
-u_long get_dclk(void)
-{
- return _get_sclk(&cached_dclk);
-}
-#else
-
-u_long get_sclk(void)
-{
- static u_long cached_sclk_pll_div, cached_sclk;
- u_long div, ssel;
-
- if (pll_is_bypassed())
- return CONFIG_CLKIN_HZ;
-
- div = bfin_read_PLL_DIV();
- if (div == cached_sclk_pll_div)
- return cached_sclk;
- else
- cached_sclk_pll_div = div;
-
- ssel = (div & SSEL) >> SSEL_P;
- cached_sclk = get_vco() / ssel;
-
- return cached_sclk;
-}
-
-#endif
diff --git a/arch/blackfin/lib/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c
deleted file mode 100644
index a4c799acb3e7..000000000000
--- a/arch/blackfin/lib/cmd_cache_dump.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * U-Boot - cmd_cache_dump.c
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/mpu.h>
-
-static int check_limit(const char *type, size_t start_limit, size_t end_limit, size_t start, size_t end)
-{
- if (start >= start_limit && start <= end_limit && \
- end <= end_limit && end >= start_limit && \
- start <= end)
- return 0;
-
- printf("%s limit violation: %zu <= (user:%zu) <= (user:%zu) <= %zu\n",
- type, start_limit, start, end, end_limit);
- return 1;
-}
-
-int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int cache_status = icache_status();
-
- if (cache_status)
- icache_disable();
-
- uint32_t cmd_base, tag, cache_upper, cache_lower;
-
- size_t way, way_start = 0, way_end = 3;
- size_t sbnk, sbnk_start = 0, sbnk_end = 3;
- size_t set, set_start = 0, set_end = 31;
- size_t dw;
-
- if (argc > 1) {
- way_start = way_end = simple_strtoul(argv[1], NULL, 10);
- if (argc > 2) {
- sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
- if (argc > 3)
- set_start = set_end = simple_strtoul(argv[3], NULL, 10);
- }
- }
-
- if (check_limit("way", 0, 3, way_start, way_end) || \
- check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
- check_limit("set", 0, 31, set_start, set_end))
- return 1;
-
- puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
-
- for (way = way_start; way <= way_end; ++way) {
- for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
- for (set = set_start; set <= set_end; ++set) {
- printf("%zu:%zu:%2zu: ", way, sbnk, set);
- for (dw = 0; dw < 4; ++dw) {
- if (ctrlc())
- return 1;
-
- cmd_base = \
- (way << 26) | \
- (sbnk << 16) | \
- (set << 5) | \
- (dw << 3);
-
- /* first read the tag */
- bfin_write_ITEST_COMMAND(cmd_base | 0x0);
- SSYNC();
- tag = bfin_read_ITEST_DATA0();
- printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
-
- /* grab the data at this loc */
- bfin_write_ITEST_COMMAND(cmd_base | 0x4);
- SSYNC();
- cache_lower = bfin_read_ITEST_DATA0();
- cache_upper = bfin_read_ITEST_DATA1();
- printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
- }
- puts("\n");
- }
- }
- }
-
- if (cache_status)
- icache_enable();
-
- return 0;
-}
-
-U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
- "icache_dump - dump current instruction cache\n",
- "[way] [subbank] [set]");
-
-int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u32 way, bank, subbank, set;
- u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank) {
- printf("%i:%i:%i:\t", bank, way, subbank);
- for (set = 0; set < 64; ++set) {
-
- if (ctrlc())
- return 1;
-
- /* retrieve a cache tag */
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* show it */
- if (set && !(set % 4))
- puts("\n\t");
- printf("%c%08x%c%08x%c ", (status & 0x1 ? '[' : '{'), status, (status & 0x2 ? 'd' : ' '), addr, (status & 0x1 ? ']' : '}'));
- }
- puts("\n");
- }
- }
-
- return 0;
-}
-
-U_BOOT_CMD(dcache_dump, 4, 0, do_dcache_dump,
- "dcache_dump - dump current data cache\n",
- "[bank] [way] [subbank] [set]");
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
deleted file mode 100644
index 3ac6d8454864..000000000000
--- a/arch/blackfin/lib/ins.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
- [--sp] = rets; \
- [--sp] = (P5:0); \
- sp += -12; \
- call ___ipipe_disable_root_irqs_hw; \
- sp += 12; \
- (P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
- sp += -12; \
- call ___ipipe_enable_root_irqs_hw; \
- sp += 12; \
-2: rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-# define STI_INNER nop; 2: nop;
-# else
-# define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- * - turns interrupts off every read (higher overhead, but lower latency)
- * - turns interrupts off every loop (low overhead, but longer latency)
- * - DMA version, which do not suffer from this issue. DMA versions have
- * different name (prefixed by dma_ ), and are located in
- * ../kernel/bfin_dma_5xx.c
- * Using the dma related functions are recommended for transfering large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-.section .text._ins##func; \
-ENTRY(_ins##func) \
- P0 = R0; /* P0 = port */ \
- CLI_OUTER; /* 3 instructions before first read access */ \
- P1 = R1; /* P1 = address */ \
- P2 = R2; /* P2 = count */ \
- SSYNC; \
- \
- LSETUP(1f, 2f) LC0 = P2; \
- CLI_INNER; \
- ops; \
- STI_INNER; \
- \
- STI_OUTER; \
- RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
- R0 = [P0]; \
- [P1++] = R0; \
-)
-
-COMMON_INS(w, \
- R0 = W[P0]; \
- W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
- R0 = W[P0]; \
- B[P1++] = R0; \
- R0 = R0 >> 8; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
- R0 = B[P0]; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
- R0 = [P0]; \
- W[P1++] = R0; \
- R0 = R0 >> 16; \
- W[P1++] = R0; \
-)
diff --git a/arch/blackfin/lib/kgdb.c b/arch/blackfin/lib/kgdb.c
deleted file mode 100644
index 2a7c0727f5c0..000000000000
--- a/arch/blackfin/lib/kgdb.c
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
- * U-Boot - architecture specific kgdb code
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-
-#include <kgdb.h>
-#include <asm/processor.h>
-#include <asm/mach-common/bits/core.h>
-#include "kgdb.h"
-#include <asm/deferred.h>
-#include <asm/traps.h>
-#include <asm/signal.h>
-
-void kgdb_enter(struct pt_regs *regs, kgdb_data *kdp)
-{
- /* disable interrupts */
- disable_interrupts();
-
- /* reply to host that an exception has occurred */
- kdp->sigval = kgdb_trap(regs);
-
- /* send the PC and the Stack Pointer */
- kdp->nregs = 2;
- kdp->regs[0].num = BFIN_PC;
- kdp->regs[0].val = regs->pc;
-
- kdp->regs[1].num = BFIN_SP;
- kdp->regs[1].val = (unsigned long)regs;
-
-}
-
-void kgdb_exit(struct pt_regs *regs, kgdb_data *kdp)
-{
- if (kdp->extype & KGDBEXIT_WITHADDR)
- printf("KGDBEXIT_WITHADDR\n");
-
- switch (kdp->extype & KGDBEXIT_TYPEMASK) {
- case KGDBEXIT_KILL:
- printf("KGDBEXIT_KILL:\n");
- break;
- case KGDBEXIT_CONTINUE:
- /* Make sure the supervisor single step bit is clear */
- regs->syscfg &= ~1;
- break;
- case KGDBEXIT_SINGLE:
- /* set the supervisor single step bit */
- regs->syscfg |= 1;
- break;
- default:
- printf("KGDBEXIT : %d\n", kdp->extype);
- }
-
- /* enable interrupts */
- enable_interrupts();
-}
-
-int kgdb_trap(struct pt_regs *regs)
-{
- /* ipend doesn't get filled in properly */
- switch (regs->seqstat & EXCAUSE) {
- case VEC_EXCPT01:
- return SIGTRAP;
- case VEC_EXCPT03:
- return SIGSEGV;
- case VEC_EXCPT02:
- return SIGTRAP;
- case VEC_EXCPT04 ... VEC_EXCPT15:
- return SIGILL;
- case VEC_STEP:
- return SIGTRAP;
- case VEC_OVFLOW:
- return SIGTRAP;
- case VEC_UNDEF_I:
- return SIGILL;
- case VEC_ILGAL_I:
- return SIGILL;
- case VEC_CPLB_VL:
- return SIGSEGV;
- case VEC_MISALI_D:
- return SIGBUS;
- case VEC_UNCOV:
- return SIGILL;
- case VEC_CPLB_MHIT:
- return SIGSEGV;
- case VEC_MISALI_I:
- return SIGBUS;
- case VEC_CPLB_I_VL:
- return SIGBUS;
- case VEC_CPLB_I_MHIT:
- return SIGSEGV;
- default:
- return SIGBUS;
- }
-}
-
-/*
- * getregs - gets the pt_regs, and gives them to kgdb's buffer
- */
-int kgdb_getregs(struct pt_regs *regs, char *buf, int max)
-{
- unsigned long *gdb_regs = (unsigned long *)buf;
-
- if (max < NUMREGBYTES)
- kgdb_error(KGDBERR_NOSPACE);
-
- if ((unsigned long)gdb_regs & 3)
- kgdb_error(KGDBERR_ALIGNFAULT);
-
- gdb_regs[BFIN_R0] = regs->r0;
- gdb_regs[BFIN_R1] = regs->r1;
- gdb_regs[BFIN_R2] = regs->r2;
- gdb_regs[BFIN_R3] = regs->r3;
- gdb_regs[BFIN_R4] = regs->r4;
- gdb_regs[BFIN_R5] = regs->r5;
- gdb_regs[BFIN_R6] = regs->r6;
- gdb_regs[BFIN_R7] = regs->r7;
- gdb_regs[BFIN_P0] = regs->p0;
- gdb_regs[BFIN_P1] = regs->p1;
- gdb_regs[BFIN_P2] = regs->p2;
- gdb_regs[BFIN_P3] = regs->p3;
- gdb_regs[BFIN_P4] = regs->p4;
- gdb_regs[BFIN_P5] = regs->p5;
- gdb_regs[BFIN_SP] = (unsigned long)regs;
- gdb_regs[BFIN_FP] = regs->fp;
- gdb_regs[BFIN_I0] = regs->i0;
- gdb_regs[BFIN_I1] = regs->i1;
- gdb_regs[BFIN_I2] = regs->i2;
- gdb_regs[BFIN_I3] = regs->i3;
- gdb_regs[BFIN_M0] = regs->m0;
- gdb_regs[BFIN_M1] = regs->m1;
- gdb_regs[BFIN_M2] = regs->m2;
- gdb_regs[BFIN_M3] = regs->m3;
- gdb_regs[BFIN_B0] = regs->b0;
- gdb_regs[BFIN_B1] = regs->b1;
- gdb_regs[BFIN_B2] = regs->b2;
- gdb_regs[BFIN_B3] = regs->b3;
- gdb_regs[BFIN_L0] = regs->l0;
- gdb_regs[BFIN_L1] = regs->l1;
- gdb_regs[BFIN_L2] = regs->l2;
- gdb_regs[BFIN_L3] = regs->l3;
- gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
- gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
- gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
- gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
- gdb_regs[BFIN_ASTAT] = regs->astat;
- gdb_regs[BFIN_RETS] = regs->rets;
- gdb_regs[BFIN_LC0] = regs->lc0;
- gdb_regs[BFIN_LT0] = regs->lt0;
- gdb_regs[BFIN_LB0] = regs->lb0;
- gdb_regs[BFIN_LC1] = regs->lc1;
- gdb_regs[BFIN_LT1] = regs->lt1;
- gdb_regs[BFIN_LB1] = regs->lb1;
- gdb_regs[BFIN_CYCLES] = 0;
- gdb_regs[BFIN_CYCLES2] = 0;
- gdb_regs[BFIN_USP] = regs->usp;
- gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
- gdb_regs[BFIN_SYSCFG] = regs->syscfg;
- gdb_regs[BFIN_RETI] = regs->pc;
- gdb_regs[BFIN_RETX] = regs->retx;
- gdb_regs[BFIN_RETN] = regs->retn;
- gdb_regs[BFIN_RETE] = regs->rete;
- gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = 0;
- gdb_regs[BFIN_EXTRA1] = 0;
- gdb_regs[BFIN_EXTRA2] = 0;
- gdb_regs[BFIN_EXTRA3] = 0;
- gdb_regs[BFIN_IPEND] = regs->ipend;
-
- return NUMREGBYTES;
-}
-
-/*
- * putreg - put kgdb's reg (regno) into the pt_regs
- */
-void kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length)
-{
- unsigned long *ptr = (unsigned long *)buf;
-
- if (regno < 0 || regno > BFIN_NUM_REGS)
- kgdb_error(KGDBERR_BADPARAMS);
-
- if (length < 4)
- kgdb_error(KGDBERR_NOSPACE);
-
- if ((unsigned long)ptr & 3)
- kgdb_error(KGDBERR_ALIGNFAULT);
-
- switch (regno) {
- case BFIN_R0:
- regs->r0 = *ptr;
- break;
- case BFIN_R1:
- regs->r1 = *ptr;
- break;
- case BFIN_R2:
- regs->r2 = *ptr;
- break;
- case BFIN_R3:
- regs->r3 = *ptr;
- break;
- case BFIN_R4:
- regs->r4 = *ptr;
- break;
- case BFIN_R5:
- regs->r5 = *ptr;
- break;
- case BFIN_R6:
- regs->r6 = *ptr;
- break;
- case BFIN_R7:
- regs->r7 = *ptr;
- break;
- case BFIN_P0:
- regs->p0 = *ptr;
- break;
- case BFIN_P1:
- regs->p1 = *ptr;
- break;
- case BFIN_P2:
- regs->p2 = *ptr;
- break;
- case BFIN_P3:
- regs->p3 = *ptr;
- break;
- case BFIN_P4:
- regs->p4 = *ptr;
- break;
- case BFIN_P5:
- regs->p5 = *ptr;
- break;
- case BFIN_SP:
- regs->reserved = *ptr;
- break;
- case BFIN_FP:
- regs->fp = *ptr;
- break;
- case BFIN_I0:
- regs->i0 = *ptr;
- break;
- case BFIN_I1:
- regs->i1 = *ptr;
- break;
- case BFIN_I2:
- regs->i2 = *ptr;
- break;
- case BFIN_I3:
- regs->i3 = *ptr;
- break;
- case BFIN_M0:
- regs->m0 = *ptr;
- break;
- case BFIN_M1:
- regs->m1 = *ptr;
- break;
- case BFIN_M2:
- regs->m2 = *ptr;
- break;
- case BFIN_M3:
- regs->m3 = *ptr;
- break;
- case BFIN_B0:
- regs->b0 = *ptr;
- break;
- case BFIN_B1:
- regs->b1 = *ptr;
- break;
- case BFIN_B2:
- regs->b2 = *ptr;
- break;
- case BFIN_B3:
- regs->b3 = *ptr;
- break;
- case BFIN_L0:
- regs->l0 = *ptr;
- break;
- case BFIN_L1:
- regs->l1 = *ptr;
- break;
- case BFIN_L2:
- regs->l2 = *ptr;
- break;
- case BFIN_L3:
- regs->l3 = *ptr;
- break;
- case BFIN_A0_DOT_X:
- regs->a0x = *ptr;
- break;
- case BFIN_A0_DOT_W:
- regs->a0w = *ptr;
- break;
- case BFIN_A1_DOT_X:
- regs->a1x = *ptr;
- break;
- case BFIN_A1_DOT_W:
- regs->a1w = *ptr;
- break;
- case BFIN_ASTAT:
- regs->astat = *ptr;
- break;
- case BFIN_RETS:
- regs->rets = *ptr;
- break;
- case BFIN_LC0:
- regs->lc0 = *ptr;
- break;
- case BFIN_LT0:
- regs->lt0 = *ptr;
- break;
- case BFIN_LB0:
- regs->lb0 = *ptr;
- break;
- case BFIN_LC1:
- regs->lc1 = *ptr;
- break;
- case BFIN_LT1:
- regs->lt1 = *ptr;
- break;
- case BFIN_LB1:
- regs->lb1 = *ptr;
- break;
-/*
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
-*/
- case BFIN_RETX:
- regs->retx = *ptr;
- break;
- case BFIN_RETN:
- regs->retn = *ptr;
- break;
- case BFIN_RETE:
- regs->rete = *ptr;
- break;
- case BFIN_PC:
- regs->pc = *ptr;
- break;
-
- default:
- kgdb_error(KGDBERR_BADPARAMS);
- }
-}
-
-void kgdb_putregs(struct pt_regs *regs, char *buf, int length)
-{
- unsigned long *gdb_regs = (unsigned long *)buf;
-
- if (length != BFIN_NUM_REGS)
- kgdb_error(KGDBERR_NOSPACE);
-
- if ((unsigned long)gdb_regs & 3)
- kgdb_error(KGDBERR_ALIGNFAULT);
-
- regs->r0 = gdb_regs[BFIN_R0];
- regs->r1 = gdb_regs[BFIN_R1];
- regs->r2 = gdb_regs[BFIN_R2];
- regs->r3 = gdb_regs[BFIN_R3];
- regs->r4 = gdb_regs[BFIN_R4];
- regs->r5 = gdb_regs[BFIN_R5];
- regs->r6 = gdb_regs[BFIN_R6];
- regs->r7 = gdb_regs[BFIN_R7];
- regs->p0 = gdb_regs[BFIN_P0];
- regs->p1 = gdb_regs[BFIN_P1];
- regs->p2 = gdb_regs[BFIN_P2];
- regs->p3 = gdb_regs[BFIN_P3];
- regs->p4 = gdb_regs[BFIN_P4];
- regs->p5 = gdb_regs[BFIN_P5];
- regs->fp = gdb_regs[BFIN_FP];
-/* regs->sp = gdb_regs[BFIN_ ]; */
- regs->i0 = gdb_regs[BFIN_I0];
- regs->i1 = gdb_regs[BFIN_I1];
- regs->i2 = gdb_regs[BFIN_I2];
- regs->i3 = gdb_regs[BFIN_I3];
- regs->m0 = gdb_regs[BFIN_M0];
- regs->m1 = gdb_regs[BFIN_M1];
- regs->m2 = gdb_regs[BFIN_M2];
- regs->m3 = gdb_regs[BFIN_M3];
- regs->b0 = gdb_regs[BFIN_B0];
- regs->b1 = gdb_regs[BFIN_B1];
- regs->b2 = gdb_regs[BFIN_B2];
- regs->b3 = gdb_regs[BFIN_B3];
- regs->l0 = gdb_regs[BFIN_L0];
- regs->l1 = gdb_regs[BFIN_L1];
- regs->l2 = gdb_regs[BFIN_L2];
- regs->l3 = gdb_regs[BFIN_L3];
- regs->a0x = gdb_regs[BFIN_A0_DOT_X];
- regs->a0w = gdb_regs[BFIN_A0_DOT_W];
- regs->a1x = gdb_regs[BFIN_A1_DOT_X];
- regs->a1w = gdb_regs[BFIN_A1_DOT_W];
- regs->rets = gdb_regs[BFIN_RETS];
- regs->lc0 = gdb_regs[BFIN_LC0];
- regs->lt0 = gdb_regs[BFIN_LT0];
- regs->lb0 = gdb_regs[BFIN_LB0];
- regs->lc1 = gdb_regs[BFIN_LC1];
- regs->lt1 = gdb_regs[BFIN_LT1];
- regs->lb1 = gdb_regs[BFIN_LB1];
- regs->usp = gdb_regs[BFIN_USP];
- regs->syscfg = gdb_regs[BFIN_SYSCFG];
- regs->retx = gdb_regs[BFIN_PC];
- regs->retn = gdb_regs[BFIN_RETN];
- regs->rete = gdb_regs[BFIN_RETE];
- regs->pc = gdb_regs[BFIN_PC];
-
-#if 0 /* can't change these */
- regs->astat = gdb_regs[BFIN_ASTAT];
- regs->seqstat = gdb_regs[BFIN_SEQSTAT];
- regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-
-}
-
-void kgdb_breakpoint(int argc, char * const argv[])
-{
- asm volatile ("excpt 0x1\n");
-}
diff --git a/arch/blackfin/lib/kgdb.h b/arch/blackfin/lib/kgdb.h
deleted file mode 100644
index 18f1f493cc87..000000000000
--- a/arch/blackfin/lib/kgdb.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-enum regnames {
- /* Core Registers */
- BFIN_R0 = 0,
- BFIN_R1,
- BFIN_R2,
- BFIN_R3,
- BFIN_R4,
- BFIN_R5,
- BFIN_R6,
- BFIN_R7,
- BFIN_P0,
- BFIN_P1,
- BFIN_P2,
- BFIN_P3,
- BFIN_P4,
- BFIN_P5,
- BFIN_SP,
- BFIN_FP,
- BFIN_I0,
- BFIN_I1,
- BFIN_I2,
- BFIN_I3,
- BFIN_M0,
- BFIN_M1,
- BFIN_M2,
- BFIN_M3,
- BFIN_B0,
- BFIN_B1,
- BFIN_B2,
- BFIN_B3,
- BFIN_L0,
- BFIN_L1,
- BFIN_L2,
- BFIN_L3,
- BFIN_A0_DOT_X,
- BFIN_A0_DOT_W,
- BFIN_A1_DOT_X,
- BFIN_A1_DOT_W,
- BFIN_ASTAT,
- BFIN_RETS,
- BFIN_LC0,
- BFIN_LT0,
- BFIN_LB0,
- BFIN_LC1,
- BFIN_LT1,
- BFIN_LB1,
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
- BFIN_RETI,
- BFIN_RETX,
- BFIN_RETN,
- BFIN_RETE,
-
- /* Pseudo Registers */
- BFIN_PC,
- BFIN_CC,
- BFIN_EXTRA1, /* Address of .text section. */
- BFIN_EXTRA2, /* Address of .data section. */
- BFIN_EXTRA3, /* Address of .bss section. */
- BFIN_FDPIC_EXEC,
- BFIN_FDPIC_INTERP,
-
- /* MMRs */
- BFIN_IPEND,
-
- /* LAST ENTRY SHOULD NOT BE CHANGED. */
- BFIN_NUM_REGS /* The number of all registers. */
-};
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES (BFIN_NUM_REGS * 4)
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm volatile ("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE 2
-#define CACHE_FLUSH_IS_SAFE 1
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM 6
-#define HW_WATCHPOINT_NUM 8
-#define TYPE_INST_WATCHPOINT 0
-#define TYPE_DATA_WATCHPOINT 1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR 0x1
-#define WPIREN01 0x2
-#define WPIRINV01 0x4
-#define WPIAEN0 0x8
-#define WPIAEN1 0x10
-#define WPICNTEN0 0x20
-#define WPICNTEN1 0x40
-#define EMUSW0 0x80
-#define EMUSW1 0x100
-#define WPIREN23 0x200
-#define WPIRINV23 0x400
-#define WPIAEN2 0x800
-#define WPIAEN3 0x1000
-#define WPICNTEN2 0x2000
-#define WPICNTEN3 0x4000
-#define EMUSW2 0x8000
-#define EMUSW3 0x10000
-#define WPIREN45 0x20000
-#define WPIRINV45 0x40000
-#define WPIAEN4 0x80000
-#define WPIAEN5 0x100000
-#define WPICNTEN4 0x200000
-#define WPICNTEN5 0x400000
-#define EMUSW4 0x800000
-#define EMUSW5 0x1000000
-#define WPAND 0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01 0x1
-#define WPDRINV01 0x2
-#define WPDAEN0 0x4
-#define WPDAEN1 0x8
-#define WPDCNTEN0 0x10
-#define WPDCNTEN1 0x20
-
-#define WPDSRC0 0xc0
-#define WPDACC0_OFFSET 8
-#define WPDSRC1 0xc00
-#define WPDACC1_OFFSET 12
-
-/* Watchpoint status register bits mask */
-#define STATIA0 0x1
-#define STATIA1 0x2
-#define STATIA2 0x4
-#define STATIA3 0x8
-#define STATIA4 0x10
-#define STATIA5 0x20
-#define STATDA0 0x40
-#define STATDA1 0x80
-
-#endif
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
deleted file mode 100644
index c8a5bed65185..000000000000
--- a/arch/blackfin/lib/memcmp.S
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * File: memcmp.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMCMP
- * R0 = First Address
- * R1 = Second Address
- * R2 = count
- * Favours word aligned data.
- */
-
-.globl _memcmp;
-.type _memcmp, STT_FUNC;
-_memcmp:
- I1 = P3;
- P0 = R0; /* P0 = s1 address */
- P3 = R1; /* P3 = s2 Address */
- P2 = R2 ; /* P2 = count */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- I0 = R1; /* s2 */
- R1 = R1 | R0; /* OR addresses together */
- R1 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero. */
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
-
- P1 = P2 >> 2; /* count = n/4 */
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
-
- LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
- NOP;
- R0 = [P0++];
- R1 = [I0++];
- CC = R0 == R1;
- IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
- NOP;
-
- P3 = I0; /* s2 */
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely*/
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
- R1 = B[P3++](Z); /* *s2 */
- R0 = B[P0++](Z); /* *s1 */
- CC = R0 == R1;
- IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
- NOP;
-
-.Ldifferent:
- R0 = R0 - R1;
- P3 = I1;
- RTS;
-
-.Lquad_different:
-/* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
- P0 += -4; /* back up to the start of the */
- P3 = I0; /* quads, and increase the*/
- P2 += 4; /* remainder count*/
- P3 += -4;
- JUMP .Lbytes;
-
-.Lfinished:
- R0 = 0;
- P3 = I1;
- RTS;
-
-.size _memcmp, .-_memcmp
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
deleted file mode 100644
index 596ff1ca25d5..000000000000
--- a/arch/blackfin/lib/memcpy.S
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * File: memcpy.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.align 2
-
-.globl _memcpy_ASM;
-.type _memcpy_ASM, STT_FUNC;
-_memcpy_ASM:
- CC = R2 <= 0; /* length not positive?*/
- IF CC JUMP .L_P1L2147483647; /* Nothing to do */
-
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
- P2 = R2 ; /* length */
-
- /* check for overlapping data */
- CC = R1 < R0; /* src < dst */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 < R3; /* and dst < src+len */
- IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
- /* Check for aligned data.*/
-
- R3 = R1 | R0;
- R0 = 0x3;
- R3 = R3 & R0;
- CC = R3; /* low bits set on either address? */
- IF CC JUMP .Lnot_aligned;
-
- /* Both addresses are word-aligned, so we can copy
- at least part of the data using word copies.*/
- P2 = P2 >> 2;
- CC = P2 <= 2;
- IF !CC JUMP .Lmore_than_seven;
- /* less than eight bytes... */
- P2 = R2;
- LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
- R0 = R1; /* setup src address for return */
-.Lthree_start:
- R3 = B[P1++] (X);
-.Lthree_end:
- B[P0++] = R3;
-
- RTS;
-
-.Lmore_than_seven:
- /* There's at least eight bytes to copy. */
- P2 += -1; /* because we unroll one iteration */
- LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
- R0 = R1;
- I1 = P1;
- R3 = [I1++];
-.Lword_loop:
- MNOP || [P0++] = R3 || R3 = [I1++];
-
- [P0++] = R3;
- /* Any remaining bytes to copy? */
- R3 = 0x3;
- R3 = R2 & R3;
- CC = R3 == 0;
- P1 = I1; /* in case there's something left, */
- IF !CC JUMP .Lbytes_left;
- RTS;
-.Lbytes_left: P2 = R3;
-.Lnot_aligned:
- /* From here, we're copying byte-by-byte. */
- LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
- R0 = R1; /* Save src address for return */
-.Lbyte_start:
- R1 = B[P1++] (X);
-.Lbyte_end:
- B[P0++] = R1;
-
-.L_P1L2147483647:
- RTS;
-
-.Lhas_overlap:
-/* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
- R0 = R1; /* save src for later. */
- P0 = P0 + P2;
- P0 += -1;
- P1 = P1 + P2;
- P1 += -1;
- LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
- R1 = B[P1--] (X);
-.Lover_end:
- B[P0--] = R1;
-
- RTS;
-
-.size _memcpy_ASM, .-_memcpy_ASM
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
deleted file mode 100644
index 9ab20770d0bc..000000000000
--- a/arch/blackfin/lib/memmove.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File: memmove.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs@http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-.globl _memmove;
-.type _memmove, STT_FUNC;
-_memmove:
- I1 = P3;
- P0 = R0; /* P0 = To address */
- P3 = R1; /* P3 = From Address */
- P2 = R2 ; /* P2 = count */
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely */
-
- CC = R1 < R0 (IU); /* From < To */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 <= R3 (IU); /* (From+len) >= To */
- IF CC JUMP .Loverlap;
-.Lno_overlap:
- R3 = 11;
- CC = R2 <= R3;
- IF CC JUMP .Lbytes;
- R3 = R1 | R0; /* OR addresses together */
- R3 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero.*/
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned.*/
-
- I0 = P3;
- P1 = P2 >> 2; /* count = n/4 */
- P1 += -1;
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
- R1 = [I0++];
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
- [P0++] = R1;
-
- CC = P2 == 0; /* any remaining bytes? */
- P3 = I0; /* Ammend P3 to updated ptr. */
- IF !CC JUMP .Lbytes;
- P3 = I1;
- RTS;
-
-.Lbytes: LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
-.Lbyte2_s: R1 = B[P3++](Z);
-.Lbyte2_e: B[P0++] = R1;
-
-.Lfinished: P3 = I1;
- RTS;
-
-.Loverlap:
- P2 += -1;
- P0 = P0 + P2;
- P3 = P3 + P2;
- R1 = B[P3--] (Z);
- CC = P2 == 0;
- IF CC JUMP .Lno_loop;
- LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s: B[P0--] = R1;
-.Lol_e: R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
- P3 = I1;
- RTS;
-
-.size _memmove, .-_memmove
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
deleted file mode 100644
index 21cbabd5822a..000000000000
--- a/arch/blackfin/lib/memset.S
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File: memset.S
- *
- * Copyright 2004-2007 Analog Devices Inc.
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.align 2
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- */
-
-.globl _memset;
-.type _memset, STT_FUNC;
-_memset:
- P0 = R0 ; /* P0 = address */
- P2 = R2 ; /* P2 = count */
- R3 = R0 + R2; /* end */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- R1 = R1.B (Z); /* R1 = fill char */
- R2 = 3;
- R2 = R0 & R2; /* addr bottom two bits */
- CC = R2 == 0; /* AZ set if zero. */
- IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
-
-.Laligned:
- P1 = P2 >> 2; /* count = n/4 */
- R2 = R1 << 8; /* create quad filler */
- R2.L = R2.L + R1.L(NS);
- R2.H = R2.L + R1.H(NS);
- P2 = R3;
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
- [P0++] = R2;
-
- CC = P0 == P2;
- IF !CC JUMP .Lbytes_left;
- RTS;
-
-.Lbytes_left:
- R2 = R3; /* end point */
- R3 = P0; /* current position */
- R2 = R2 - R3; /* bytes left */
- P2 = R2;
-
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count */
- IF CC JUMP .Lfinished; /* Unusual */
-
-.Lbytes:
- LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
- B[P0++] = R1;
-
-.Lfinished:
- RTS;
-
-.Lforce_align:
- CC = BITTST (R0, 0); /* odd byte */
- R0 = 4;
- R0 = R0 - R2;
- P1 = R0;
- R0 = P0; /* Recover return address */
- IF !CC JUMP .Lskip1;
- B[P0++] = R1;
-.Lskip1:
- CC = R2 <= 2; /* 2 bytes */
- P2 -= P1; /* reduce count */
- IF !CC JUMP .Laligned;
- B[P0++] = R1;
- B[P0++] = R1;
- JUMP .Laligned;
-
-.size _memset, .-_memset
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c
deleted file mode 100644
index 9f6f60d05f04..000000000000
--- a/arch/blackfin/lib/muldi3.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * U-Boot - muldi3.c contains routines for mult and div
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Generic function got from GNU gcc package, libgcc2.c */
-#ifndef SI_TYPE_SIZE
-#define SI_TYPE_SIZE 32
-#endif
-#define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
-#define BITS_PER_UNIT 8
-
-#if !defined (umul_ppmm)
-#define umul_ppmm(w1, w0, u, v) \
-do { \
- USItype __x0, __x1, __x2, __x3; \
- USItype __ul, __vl, __uh, __vh; \
- \
- __ul = __ll_lowpart (u); \
- __uh = __ll_highpart (u); \
- __vl = __ll_lowpart (v); \
- __vh = __ll_highpart (v); \
- \
- __x0 = (USItype) __ul * __vl; \
- __x1 = (USItype) __ul * __vh; \
- __x2 = (USItype) __uh * __vl; \
- __x3 = (USItype) __uh * __vh; \
- \
- __x1 += __ll_highpart (__x0);/* this can't give carry */ \
- __x1 += __x2; /* but this indeed can */ \
- if (__x1 < __x2) /* did we get it? */ \
- __x3 += __ll_B; /* yes, add it in the proper pos. */ \
- \
- (w1) = __x3 + __ll_highpart (__x1); \
- (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
-} while (0)
-#endif
-
-#if !defined (__umulsidi3)
-#define __umulsidi3(u, v) \
- ({DIunion __w; \
- umul_ppmm (__w.s.high, __w.s.low, u, v); \
- __w.ll; })
-#endif
-
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-
-struct DIstruct {
- SItype low, high;
-};
-typedef union {
- struct DIstruct s;
- DItype ll;
-} DIunion;
-
-DItype __muldi3(DItype u, DItype v)
-{
- DIunion w;
- DIunion uu, vv;
-
- uu.ll = u, vv.ll = v;
- /* panic("kernel panic for __muldi3"); */
- w.ll = __umulsidi3(uu.s.low, vv.s.low);
- w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
- + (USItype) uu.s.high * (USItype) vv.s.low);
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 39d5332615ab..000000000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-.section .text._outsl
-ENTRY(_outsl)
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
- RTS;
-ENDPROC(_outsl)
-
-.section .text._outsw
-ENTRY(_outsw)
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
- RTS;
-ENDPROC(_outsw)
-
-.section .text._outsb
-ENTRY(_outsb)
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
- RTS;
-ENDPROC(_outsb)
-
-.section .text._outsw_8
-ENTRY(_outsw_8)
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
- RTS;
-ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/post.c b/arch/blackfin/lib/post.c
deleted file mode 100644
index b3c5fab57652..000000000000
--- a/arch/blackfin/lib/post.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Blackfin POST code
- *
- * Copyright (c) 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <post.h>
-
-#include <asm/gpio.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-int led_post_test(int flags)
-{
- unsigned leds[] = { CONFIG_POST_BSPEC1_GPIO_LEDS };
- int i;
-
- /* First turn them all off */
- for (i = 0; i < ARRAY_SIZE(leds); ++i) {
- if (gpio_request(leds[i], "post")) {
- printf("could not request gpio %u\n", leds[i]);
- continue;
- }
- gpio_direction_output(leds[i], 0);
- }
-
- /* Now turn them on one by one */
- for (i = 0; i < ARRAY_SIZE(leds); ++i) {
- printf("LED%i on", i + 1);
- gpio_set_value(leds[i], 1);
- udelay(1000000);
- printf("\b\b\b\b\b\b\b");
- gpio_free(leds[i]);
- }
-
- return 0;
-}
-#endif
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
-int button_post_test(int flags)
-{
- unsigned buttons[] = { CONFIG_POST_BSPEC2_GPIO_BUTTONS };
- unsigned int sws[] = { CONFIG_POST_BSPEC2_GPIO_NAMES };
- int i, delay = 5;
- unsigned short value = 0;
- int result = 0;
-
- for (i = 0; i < ARRAY_SIZE(buttons); ++i) {
- if (gpio_request(buttons[i], "post")) {
- printf("could not request gpio %u\n", buttons[i]);
- continue;
- }
- gpio_direction_input(buttons[i]);
-
- delay = 5;
- printf("\n--------Press SW%i: %2d ", sws[i], delay);
- while (delay--) {
- int j;
- for (j = 0; j < 100; j++) {
- value = gpio_get_value(buttons[i]);
- if (value != 0)
- break;
- udelay(10000);
- }
- printf("\b\b\b%2d ", delay);
- }
- if (value != 0)
- puts("\b\bOK");
- else {
- result = -1;
- puts("\b\bfailed");
- }
-
- gpio_free(buttons[i]);
- }
-
- puts("\n");
-
- return result;
-}
-#endif
diff --git a/arch/blackfin/lib/sections.c b/arch/blackfin/lib/sections.c
deleted file mode 100644
index 86fc4df06181..000000000000
--- a/arch/blackfin/lib/sections.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * U-Boot - section.c
- *
- * Copyright (c) 2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-char __bss_start[0] __attribute__((section(".__bss_start")));
-char __bss_end[0] __attribute__((section(".__bss_end")));
-char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c
deleted file mode 100644
index c904a88916ac..000000000000
--- a/arch/blackfin/lib/string.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * U-Boot - string.c Contains library routines.
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-
-char *strcpy(char *dest, const char *src)
-{
- char *xdest = dest;
- char temp = 0;
-
- __asm__ __volatile__ (
- "1:\t%2 = B [%1++] (Z);\n\t"
- "B [%0++] = %2;\n\t"
- "CC = %2;\n\t"
- "if cc jump 1b (bp);\n"
- : "=a"(dest), "=a"(src), "=d"(temp)
- : "0"(dest), "1"(src), "2"(temp)
- : "memory");
-
- return xdest;
-}
-
-char *strncpy(char *dest, const char *src, size_t n)
-{
- char *xdest = dest;
- char temp = 0;
-
- if (n == 0)
- return xdest;
-
- __asm__ __volatile__ (
- "1:\t%3 = B [%1++] (Z);\n\t"
- "B [%0++] = %3;\n\t"
- "CC = %3;\n\t"
- "if ! cc jump 2f;\n\t"
- "%2 += -1;\n\t"
- "CC = %2 == 0;\n\t"
- "if ! cc jump 1b (bp);\n"
- "2:\n"
- : "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
- : "0"(dest), "1"(src), "2"(n), "3"(temp)
- : "memory");
-
- return xdest;
-}
-
-int strcmp(const char *cs, const char *ct)
-{
- char __res1, __res2;
-
- __asm__ (
- "1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
- "%3 = B[%1++] (Z);\n\t" /* get *ct */
- "CC = %2 == %3;\n\t" /* compare a byte */
- "if ! cc jump 2f;\n\t" /* not equal, break out */
- "CC = %2;\n\t" /* at end of cs? */
- "if cc jump 1b (bp);\n\t" /* no, keep going */
- "jump.s 3f;\n" /* strings are equal */
- "2:\t%2 = %2 - %3;\n" /* *cs - *ct */
- "3:\n"
- : "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
- : "0"(cs), "1"(ct));
-
- return __res1;
-}
-
-int strncmp(const char *cs, const char *ct, size_t count)
-{
- char __res1, __res2;
-
- if (!count)
- return 0;
-
- __asm__(
- "1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
- "%4 = B[%1++] (Z);\n\t" /* get *ct */
- "CC = %3 == %4;\n\t" /* compare a byte */
- "if ! cc jump 3f;\n\t" /* not equal, break out */
- "CC = %3;\n\t" /* at end of cs? */
- "if ! cc jump 4f;\n\t" /* yes, all done */
- "%2 += -1;\n\t" /* no, adjust count */
- "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n" /* more to do, keep going */
- "2:\t%3 = 0;\n\t" /* strings are equal */
- "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n" /* *cs - *ct */
- "4:"
- : "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
- : "0"(cs), "1"(ct), "2"(count));
-
- return __res1;
-}
-
-#ifdef MDMA1_D0_NEXT_DESC_PTR
-# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
-# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
-#endif
-
-static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count,
- unsigned long *dshift, unsigned long *bpos)
-{
- unsigned long limit;
-
-#ifdef MSIZE
- /* The max memory DMA memory transfer size is 32 bytes. */
- limit = 5;
- *dshift = MSIZE_P;
-#else
- /* The max memory DMA memory transfer size is 4 bytes. */
- limit = 2;
- *dshift = WDSIZE_P;
-#endif
-
- *bpos = min(limit, (unsigned long)ffs(ldst | lsrc | count)) - 1;
-}
-
-/* This version misbehaves for count values of 0 and 2^16+.
- * Perhaps we should detect that ? Nowhere do we actually
- * use dma memcpy for those types of lengths though ...
- */
-void dma_memcpy_nocache(void *dst, const void *src, size_t count)
-{
- struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR;
- struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR;
- unsigned long ldst = (unsigned long)dst;
- unsigned long lsrc = (unsigned long)src;
- unsigned long dshift, bpos;
- uint32_t dsize, mod;
-
- /* Disable DMA in case it's still running (older u-boot's did not
- * always turn them off). Do it before the if statement below so
- * we can be cheap and not do a SSYNC() due to the forced abort.
- */
- bfin_write(&mdma_d0->config, 0);
- bfin_write(&mdma_s0->config, 0);
- bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
-
- /* Scratchpad cannot be a DMA source or destination */
- if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) ||
- (ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END))
- hang();
-
- dma_calc_size(ldst, lsrc, count, &dshift, &bpos);
- dsize = bpos << dshift;
- count >>= bpos;
- mod = 1 << bpos;
-
-#ifdef PSIZE
- /* The max memory DMA peripheral transfer size is 4 bytes. */
- dsize |= min(2UL, bpos) << PSIZE_P;
-#endif
-
- /* Copy sram functions from sdram to sram */
- /* Setup destination start address */
- bfin_write(&mdma_d0->start_addr, ldst);
- /* Setup destination xcount */
- bfin_write(&mdma_d0->x_count, count);
- /* Setup destination xmodify */
- bfin_write(&mdma_d0->x_modify, mod);
-
- /* Setup Source start address */
- bfin_write(&mdma_s0->start_addr, lsrc);
- /* Setup Source xcount */
- bfin_write(&mdma_s0->x_count, count);
- /* Setup Source xmodify */
- bfin_write(&mdma_s0->x_modify, mod);
-
- /* Enable source DMA */
- bfin_write(&mdma_s0->config, dsize | DMAEN);
- bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN);
- SSYNC();
-
- while (!(bfin_read(&mdma_d0->status) & DMA_DONE))
- continue;
-
- bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
- bfin_write(&mdma_d0->config, 0);
- bfin_write(&mdma_s0->config, 0);
-}
-/* We should do a dcache invalidate on the destination after the dma, but since
- * we lack such hardware capability, we'll flush/invalidate the destination
- * before the dma and bank on the idea that u-boot is single threaded.
- */
-void *dma_memcpy(void *dst, const void *src, size_t count)
-{
- if (dcache_status()) {
- blackfin_dcache_flush_range(src, src + count);
- blackfin_dcache_flush_invalidate_range(dst, dst + count);
- }
-
- dma_memcpy_nocache(dst, src, count);
-
- if (icache_status())
- blackfin_icache_flush_range(dst, dst + count);
-
- return dst;
-}
-
-/*
- * memcpy - Copy one area of memory to another
- * @dest: Where to copy to
- * @src: Where to copy from
- * @count: The size of the area.
- *
- * We need to have this wrapper in memcpy() as common code may call memcpy()
- * to load up L1 regions. Consider loading an ELF which has sections with
- * LMA's pointing to L1. The common code ELF loader will simply use memcpy()
- * to move the ELF's sections into the right place. We need to catch that
- * here and redirect to dma_memcpy().
- */
-extern void *memcpy_ASM(void *dst, const void *src, size_t count);
-void *memcpy(void *dst, const void *src, size_t count)
-{
- if (!count)
- return dst;
-
-#ifdef CONFIG_CMD_KGDB
- if (src >= (void *)SYSMMR_BASE) {
- if (count == 2 && (unsigned long)src % 2 == 0) {
- u16 mmr = bfin_read16(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return dst;
- }
- if (count == 4 && (unsigned long)src % 4 == 0) {
- u32 mmr = bfin_read32(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return dst;
- }
- /* Failed for some reason */
- memset(dst, 0xad, count);
- return dst;
- }
- if (dst >= (void *)SYSMMR_BASE) {
- if (count == 2 && (unsigned long)dst % 2 == 0) {
- u16 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write16(dst, mmr);
- return dst;
- }
- if (count == 4 && (unsigned long)dst % 4 == 0) {
- u32 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write32(dst, mmr);
- return dst;
- }
- /* Failed for some reason */
- memset(dst, 0xad, count);
- return dst;
- }
-#endif
-
- /* if L1 is the source or dst, use DMA */
- if (addr_bfin_on_chip_mem(dst) || addr_bfin_on_chip_mem(src))
- return dma_memcpy(dst, src, count);
- else
- /* No L1 is involved, so just call regular memcpy */
- return memcpy_ASM(dst, src, count);
-}
diff --git a/board/bct-brettl2/Kconfig b/board/bct-brettl2/Kconfig
deleted file mode 100644
index 9c5407e7b20f..000000000000
--- a/board/bct-brettl2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BCT_BRETTL2
-
-config SYS_BOARD
- default "bct-brettl2"
-
-config SYS_CONFIG_NAME
- default "bct-brettl2"
-
-endif
diff --git a/board/bct-brettl2/MAINTAINERS b/board/bct-brettl2/MAINTAINERS
deleted file mode 100644
index 32245d4bcd5b..000000000000
--- a/board/bct-brettl2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCT-BRETTL2 BOARD
-M: Peter Meerwald <devel@bct-electronic.com>
-S: Maintained
-F: board/bct-brettl2/
-F: include/configs/bct-brettl2.h
-F: configs/bct-brettl2_defconfig
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
deleted file mode 100644
index 28fccc0dcb95..000000000000
--- a/board/bct-brettl2/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bct-brettl2.o gpio_cfi_flash.o cled.o
-obj-$(CONFIG_BFIN_MAC) += smsc9303.o
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
deleted file mode 100644
index adb8605bb922..000000000000
--- a/board/bct-brettl2/bct-brettl2.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * U-Boot - main board file for BCT brettl2
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/gpio.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-
-#include "../cm-bf537e/gpio_cfi_flash.h"
-#include "smsc9303.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: bct-brettl2 board\n");
- printf(" Support: http://www.bct-electronic.com/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- int retry = 3;
- int ret;
-
- ret = bfin_EMAC_initialize(bis);
-
- uchar enetaddr[6];
- if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
- printf("setting MAC %pM\n", enetaddr);
- }
- puts(" ");
-
- puts("initialize SMSC LAN9303i ethernet switch\n");
-
- while (retry-- > 0) {
- if (init_smsc9303i_mii())
- return ret;
- }
-
- return ret;
-}
-#endif
-
-static void init_tlv320aic31(void)
-{
- puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
- peripheral_request(P_TMR0, "tlv320aic31 clock");
- bfin_write_TIMER0_CONFIG(0x020d);
- bfin_write_TIMER0_PERIOD(0x0008);
- bfin_write_TIMER0_WIDTH(0x0008/2);
- bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
- SSYNC();
- udelay(10000);
-
- puts(" resetting tlv320aic31\n");
-
- gpio_request(GPIO_PF2, "tlv320aic31");
- gpio_direction_output(GPIO_PF2, 0);
- udelay(10000);
- gpio_direction_output(GPIO_PF2, 1);
- udelay(10000);
- gpio_free(GPIO_PF2);
-}
-
-static void init_mute_pin(void)
-{
- printf(" unmute class D amplifier\n");
-
- gpio_request(GPIO_PF5, "mute");
- gpio_direction_output(GPIO_PF5, 1);
- gpio_free(GPIO_PF5);
-}
-
-/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
-static void turn_leds_off(void)
-{
- printf(" turn LEDs off\n");
-
- gpio_request(GPIO_PF6, "led");
- gpio_direction_output(GPIO_PF6, 0);
- gpio_free(GPIO_PF6);
-
- gpio_request(GPIO_PF15, "led");
- gpio_direction_output(GPIO_PF15, 0);
- gpio_free(GPIO_PF15);
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
- gpio_cfi_flash_init();
- init_tlv320aic31();
- init_mute_pin();
- turn_leds_off();
-
- return 0;
-}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
deleted file mode 100644
index dcb91bdffad7..000000000000
--- a/board/bct-brettl2/cled.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * cled.c - control color led
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-
-int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr = 0x20000000 + 0x200000; /* AMS2 */
- uchar data;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- data = simple_strtoul(argv[1], NULL, 10);
- outb(data, addr);
-
- printf("cled, write %02x\n", data);
-
- return 0;
-}
-
-U_BOOT_CMD(cled, 2, 0, do_cled,
- "set/clear color LED",
- "");
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
deleted file mode 100644
index b385c7fc0ed9..000000000000
--- a/board/bct-brettl2/gpio_cfi_flash.c
+++ /dev/null
@@ -1,4 +0,0 @@
-#define GPIO_PIN_1 GPIO_PG5
-#define GPIO_PIN_2 GPIO_PG6
-#define GPIO_PIN_3 GPIO_PG7
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
deleted file mode 100644
index 15eea7a48416..000000000000
--- a/board/bct-brettl2/smsc9303.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * smsc9303.c - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <miiphy.h>
-
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-
-static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
-{
- const char *devname = miiphy_get_current_dev();
-
- if (!devname)
- return 0;
-
- if (miiphy_write(devname, addr, reg, data) != 0)
- return 0;
-
- return 1;
-}
-
-static int smc9303i_write_reg(unsigned short reg, unsigned int data)
-{
- const char *devname = miiphy_get_current_dev();
- unsigned char mii_addr = 0x10 | (reg >> 6);
- unsigned char mii_reg = (reg & 0x3c) >> 1;
-
- if (!devname)
- return 0;
-
- if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
- return 0;
-
- if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
- return 0;
-
- return 1;
-}
-
-static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
-{
- const char *devname = miiphy_get_current_dev();
- unsigned char mii_addr = 0x10 | (reg >> 6);
- unsigned char mii_reg = (reg & 0x3c) >> 1;
- unsigned short tmp1, tmp2;
-
- if (!devname)
- return 0;
-
- if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
- return 0;
-
- if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
- return 0;
-
- *data = (tmp2 << 16) | tmp1;
-
- return 1;
-}
-
-#if 0
-static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
-{
- const char *devname = miiphy_get_current_dev();
-
- if (!devname)
- return 0;
-
- if (miiphy_read(devname, addr, reg, data) != 0)
- return 0;
-
- return 1;
-}
-#endif
-
-typedef struct {
- unsigned short reg;
- unsigned int value;
-} smsc9303i_config_entry1_t;
-
-static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
-{
- {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
- {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
- {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
-};
-
-typedef struct
-{
- unsigned char addr;
- unsigned char reg;
- unsigned short value;
-} smsc9303i_config_entry2_t;
-
-static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
-{
- {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
- {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
- {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
-
- {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
- {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
- {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
-
- {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
- {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
- {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
-
- {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
- {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
- {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
- {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
- {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
- {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
- {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
- {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
- {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
-};
-
-int init_smsc9303i_mii(void)
-{
- unsigned int data;
- unsigned int i;
-
- printf(" reset SMSC LAN9303i\n");
-
- gpio_request(GPIO_PG10, "smsc9303");
- gpio_direction_output(GPIO_PG10, 0);
- udelay(10000);
- gpio_direction_output(GPIO_PG10, 1);
- udelay(10000);
-
- gpio_free(GPIO_PG10);
-
-#if defined(CONFIG_MII_INIT)
- mii_init();
-#endif
-
- printf(" write SMSC LAN9303i configuration\n");
-
- if (!smc9303i_read_reg(0x50, &data))
- return 0;
-
- if ((data >> 16) != 0x9303) {
- /* chip id not found */
- printf(" error identifying SMSC LAN9303i\n");
- return 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
- const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
-
- if (!smc9303i_write_reg(entry->reg, entry->value)) {
- printf(" error writing SMSC LAN9303i configuration\n");
- return 0;
- }
- }
-
- for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
- const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
-
- if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
- printf(" error writing SMSC LAN9303i configuration\n");
- return 0;
- }
- }
-
- return 1;
-}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
deleted file mode 100644
index a4ba40ef7303..000000000000
--- a/board/bct-brettl2/smsc9303.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * smsc9303.h - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-int init_smsc9303i_mii(void);
diff --git a/board/bf506f-ezkit/Kconfig b/board/bf506f-ezkit/Kconfig
deleted file mode 100644
index e6fc12ccb2f0..000000000000
--- a/board/bf506f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF506F_EZKIT
-
-config SYS_BOARD
- default "bf506f-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf506f-ezkit"
-
-endif
diff --git a/board/bf506f-ezkit/MAINTAINERS b/board/bf506f-ezkit/MAINTAINERS
deleted file mode 100644
index aaf1b7eaaf2e..000000000000
--- a/board/bf506f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF506F-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf506f-ezkit/
-F: include/configs/bf506f-ezkit.h
-F: configs/bf506f-ezkit_defconfig
diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile
deleted file mode 100644
index 7efe1bc20ec3..000000000000
--- a/board/bf506f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf506f-ezkit.o
diff --git a/board/bf506f-ezkit/bf506f-ezkit.c b/board/bf506f-ezkit/bf506f-ezkit.c
deleted file mode 100644
index 77e40ae15d02..000000000000
--- a/board/bf506f-ezkit/bf506f-ezkit.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-
-int checkboard(void)
-{
- printf("Board: ADI BF506F EZ-Kit board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
- bfin_write_EBIU_MODE(1);
- SSYNC();
- bfin_write_FLASH_CONTROL_CLEAR(1);
- udelay(1);
- bfin_write_FLASH_CONTROL_SET(1);
- return 0;
-}
diff --git a/board/bf518f-ezbrd/Kconfig b/board/bf518f-ezbrd/Kconfig
deleted file mode 100644
index a0e80a8bde88..000000000000
--- a/board/bf518f-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF518F_EZBRD
-
-config SYS_BOARD
- default "bf518f-ezbrd"
-
-config SYS_CONFIG_NAME
- default "bf518f-ezbrd"
-
-endif
diff --git a/board/bf518f-ezbrd/MAINTAINERS b/board/bf518f-ezbrd/MAINTAINERS
deleted file mode 100644
index 6727ae4e8a98..000000000000
--- a/board/bf518f-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF518F-EZBRD BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf518f-ezbrd/
-F: include/configs/bf518f-ezbrd.h
-F: configs/bf518f-ezbrd_defconfig
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
deleted file mode 100644
index e9e23ed41f0b..000000000000
--- a/board/bf518f-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf518f-ezbrd.o
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
deleted file mode 100644
index 30d528557587..000000000000
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF518F EZ-Board board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we cram the MAC in the last flash sector */
- uchar *board_mac_addr = (uchar *)0x203F0096;
- if (is_valid_ethaddr(board_mac_addr)) {
- memcpy(mac_addr, board_mac_addr, 6);
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-#endif
-}
-
-/* Only the first run of boards had a KSZ switch */
-#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0
-# define KSZ_POSSIBLE 1
-#else
-# define KSZ_POSSIBLE 0
-#endif
-
-#define KSZ_MAX_HZ 5000000
-
-#define KSZ_WRITE 0x02
-#define KSZ_READ 0x03
-
-#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */
-#define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */
-#define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */
-#define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */
-
-static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
- uchar data, uchar result[3])
-{
- unsigned char dout[3] = { dir, reg, data, };
- return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
-{
- unsigned char din[3];
- return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
-}
-
-static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
-{
- int ret;
- unsigned char din[3];
- ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
- return ret ? ret : din[2];
-}
-
-static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
-{
- return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
-}
-
-static int ksz8893m_reset(struct spi_slave *slave)
-{
- int ret = 0;
-
- /* Disable STPID mode */
- ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
-
- /* Disable VLAN tag insert on Port3 */
- ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
-
- /* Start switch */
- ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
-
- return ret;
-}
-
-static bool board_ksz_init(void)
-{
- static bool switch_is_alive = false;
-
- if (!switch_is_alive) {
- struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
- if (slave) {
- if (!spi_claim_bus(slave)) {
- bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
- int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
- switch_is_alive = (ret == 0);
- spi_release_bus(slave);
- }
- spi_free_slave(slave);
- }
- }
-
- return switch_is_alive;
-}
-
-int board_eth_init(bd_t *bis)
-{
- if (KSZ_POSSIBLE) {
- if (!board_ksz_init())
- return 0;
- }
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we use the last sector for the MAC address / POST LDR */
- extern flash_info_t flash_info[];
- flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* connect async banks by default */
- const unsigned short pins[] = {
- P_AMS2, P_AMS3, 0,
- };
- return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
- return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/bf525-ucr2/Kconfig b/board/bf525-ucr2/Kconfig
deleted file mode 100644
index cd52daaacddd..000000000000
--- a/board/bf525-ucr2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF525_UCR2
-
-config SYS_BOARD
- default "bf525-ucr2"
-
-config SYS_CONFIG_NAME
- default "bf525-ucr2"
-
-endif
diff --git a/board/bf525-ucr2/MAINTAINERS b/board/bf525-ucr2/MAINTAINERS
deleted file mode 100644
index f2e9575a7a10..000000000000
--- a/board/bf525-ucr2/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF525-UCR2 BOARD
-M: Haitao Zhang <hzhang@ucrobotics.com>
-M: Chong Huang <chuang@ucrobotics.com>
-S: Maintained
-F: board/bf525-ucr2/
-F: include/configs/bf525-ucr2.h
-F: configs/bf525-ucr2_defconfig
diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile
deleted file mode 100644
index 1be1d3117b6c..000000000000
--- a/board/bf525-ucr2/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf525-ucr2.o
diff --git a/board/bf525-ucr2/bf525-ucr2.c b/board/bf525-ucr2/bf525-ucr2.c
deleted file mode 100644
index 36a725c83bf0..000000000000
--- a/board/bf525-ucr2/bf525-ucr2.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* U-Boot - bf525-ucr2.c board specific routines
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-int checkboard(void)
-{
- printf("Board: bf525-ucr2\n");
- printf("Support: http://www.ucrobotics.com/\n");
- return 0;
-}
diff --git a/board/bf526-ezbrd/Kconfig b/board/bf526-ezbrd/Kconfig
deleted file mode 100644
index e138ea554572..000000000000
--- a/board/bf526-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF526_EZBRD
-
-config SYS_BOARD
- default "bf526-ezbrd"
-
-config SYS_CONFIG_NAME
- default "bf526-ezbrd"
-
-endif
diff --git a/board/bf526-ezbrd/MAINTAINERS b/board/bf526-ezbrd/MAINTAINERS
deleted file mode 100644
index f7c2d1891385..000000000000
--- a/board/bf526-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF526-EZBRD BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf526-ezbrd/
-F: include/configs/bf526-ezbrd.h
-F: configs/bf526-ezbrd_defconfig
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
deleted file mode 100644
index c4882c934653..000000000000
--- a/board/bf526-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf526-ezbrd.o
diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c
deleted file mode 100644
index ae7552081f6d..000000000000
--- a/board/bf526-ezbrd/bf526-ezbrd.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF526 EZ-Board board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we cram the MAC in the last flash sector */
- uchar *board_mac_addr = (uchar *)0x203F0096;
- if (is_valid_ethaddr(board_mac_addr)) {
- memcpy(mac_addr, board_mac_addr, 6);
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we use the last sector for the MAC address / POST LDR */
- extern flash_info_t flash_info[];
- flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
- return 0;
-}
diff --git a/board/bf527-ad7160-eval/Kconfig b/board/bf527-ad7160-eval/Kconfig
deleted file mode 100644
index fe56241212c6..000000000000
--- a/board/bf527-ad7160-eval/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_AD7160_EVAL
-
-config SYS_BOARD
- default "bf527-ad7160-eval"
-
-config SYS_CONFIG_NAME
- default "bf527-ad7160-eval"
-
-endif
diff --git a/board/bf527-ad7160-eval/MAINTAINERS b/board/bf527-ad7160-eval/MAINTAINERS
deleted file mode 100644
index e93de1a23432..000000000000
--- a/board/bf527-ad7160-eval/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-AD7160-EVAL BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf527-ad7160-eval/
-F: include/configs/bf527-ad7160-eval.h
-F: configs/bf527-ad7160-eval_defconfig
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
deleted file mode 100644
index c225f7201aae..000000000000
--- a/board/bf527-ad7160-eval/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf527-ad7160-eval.o
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
deleted file mode 100644
index 9180630ee74d..000000000000
--- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
- printf("Board: ADI BF527 AD7160-EVAL board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-int misc_init_r(void)
-{
- /* CLKIN Buffer Output Enable */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
- return 0;
-}
diff --git a/board/bf527-ezkit/Kconfig b/board/bf527-ezkit/Kconfig
deleted file mode 100644
index df49d7a60d27..000000000000
--- a/board/bf527-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_EZKIT
-
-config SYS_BOARD
- default "bf527-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf527-ezkit"
-
-endif
diff --git a/board/bf527-ezkit/MAINTAINERS b/board/bf527-ezkit/MAINTAINERS
deleted file mode 100644
index 7a953960d4d0..000000000000
--- a/board/bf527-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF527-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf527-ezkit/
-F: include/configs/bf527-ezkit.h
-F: configs/bf527-ezkit_defconfig
-F: configs/bf527-ezkit-v2_defconfig
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
deleted file mode 100644
index 53ec9e7aa6f6..000000000000
--- a/board/bf527-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf527-ezkit.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
deleted file mode 100644
index c4f58fa3b568..000000000000
--- a/board/bf527-ezkit/bf527-ezkit.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF527 EZ-Kit board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- uint32_t ret;
- uint64_t otp_mac;
-
- ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
- if (!(ret & OTP_MASTER_ERROR)) {
- uchar *otp_mac_p = (uchar *)&otp_mac;
-
- for (ret = 0; ret < 6; ++ret)
- mac_addr[ret] = otp_mac_p[5 - ret];
-
- if (is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
- /*
- * BF527 EZ-KITs require PG13 to be high for HOST mode
- */
- gpio_request(GPIO_PG13, "musb-vbus");
- gpio_direction_output(GPIO_PG13, 1);
-}
-#endif
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
deleted file mode 100644
index a57f9fecafa8..000000000000
--- a/board/bf527-ezkit/video.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <spi.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#include <asm/mach-common/bits/ppi.h>
-#include <asm/mach-common/bits/timer.h>
-
-#define LCD_X_RES 320 /* Horizontal Resolution */
-#define LCD_Y_RES 240 /* Vertical Resolution */
-#define DMA_BUS_SIZE 16
-
-#include EASYLOGO_HEADER
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
-
-/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
- * small Programmable Logic Device (CPLD)
- * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
- */
-
-#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#define LCD_BPP 16 /* Bit Per Pixel */
-#define CLOCKS_PPIX 2 /* Clocks per pixel */
-#define CPLD_DELAY 3 /* RGB565 pipeline delay */
-#endif
-
-#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#define LCD_BPP 24 /* Bit Per Pixel */
-#define CLOCKS_PPIX 3 /* Clocks per pixel */
-#define CPLD_DELAY 5 /* RGB888 pipeline delay */
-#endif
-
-/*
- * HS and VS timing parameters (all in number of PPI clk ticks)
- */
-
-#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
-#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
-#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
-#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
-
-#define U_LINE 4 /* Blanking Lines */
-
-#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
-#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
-
-/*
- * LCD Modes
- */
-#define LQ035_RL (0 << 8) /* Right -> Left Scan */
-#define LQ035_LR (1 << 8) /* Left -> Right Scan */
-#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
-#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
-#define LQ035_BGR (1 << 11) /* Use BGR format */
-#define LQ035_RGB (0 << 11) /* Use RGB format */
-#define LQ035_NORM (1 << 13) /* Reversal */
-#define LQ035_REV (0 << 13) /* Reversal */
-
-#define LQ035_INDEX 0x74
-#define LQ035_DATA 0x76
-
-#define LQ035_DRIVER_OUTPUT_CTL 0x1
-#define LQ035_SHUT_CTL 0x11
-
-#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
-#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
-
-#define LQ035_SHUT (1 << 0) /* Shutdown */
-#define LQ035_ON (0 << 0) /* Shutdown */
-
-#ifndef CONFIG_LQ035Q1_LCD_MODE
-#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
-#endif
-
-#else /* t350mcqb */
-
-#define LCD_BPP 24 /* Bit Per Pixel */
-#define CLOCKS_PPIX 3 /* Clocks per pixel */
-
-/* HS and VS timing parameters (all in number of PPI clk ticks) */
-#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
-#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
-#define H_PULSE 90 /* HS pulse width */
-#define H_START 204 /* first valid pixel */
-
-#define U_LINE 1 /* Blanking Lines */
-
-#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
-#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
-#endif
-
-#define LCD_PIXEL_SIZE (LCD_BPP / 8)
-#define DMA_SIZE16 2
-
-#define PPI_TX_MODE 0x2
-#define PPI_XFER_TYPE_11 0xC
-#define PPI_PORT_CFG_01 0x10
-#define PPI_PACK_EN 0x80
-#define PPI_POLS_1 0x8000
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-static struct spi_slave *slave;
-static int lq035q1_control(unsigned char reg, unsigned short value)
-{
- int ret;
- u8 regs[3] = {LQ035_INDEX, 0, 0};
- u8 data[3] = {LQ035_DATA, 0, 0};
- u8 dummy[3];
-
- regs[2] = reg;
- data[1] = value >> 8;
- data[2] = value & 0xFF;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
- CONFIG_LQ035Q1_SPI_CS, 20000000,
- SPI_MODE_3);
- if (!slave)
- return -1;
- }
-
- if (spi_claim_bus(slave))
- return -1;
-
- ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
- ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
- spi_release_bus(slave);
-
- return ret;
-}
-#endif
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-void DisablePPI(void)
-{
- bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-void Init_Ports(void)
-{
- const unsigned short pins[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
- P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
- };
- peripheral_request_list(pins, "lcd");
-}
-
-void Init_PPI(void)
-{
-
- bfin_write_PPI_DELAY(H_START);
- bfin_write_PPI_COUNT(H_ACTPIX - 1);
- bfin_write_PPI_FRAME(V_LINES);
-
- /* PPI control, to be replaced with definitions */
- bfin_write_PPI_CONTROL(
- PPI_TX_MODE | /* output mode , PORT_DIR */
- PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
- PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
- PPI_PACK_EN | /* packing enabled PACK_EN */
- PPI_POLS_1 /* faling edge syncs POLS */
- );
-}
-
-void Init_DMA(void *dst)
-{
- bfin_write_DMA0_START_ADDR(dst);
-
- /* X count */
- bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
- bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
-
- /* Y count */
- bfin_write_DMA0_Y_COUNT(V_LINES);
- bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
-
- /* DMA Config */
- bfin_write_DMA0_CONFIG(
- WDSIZE_16 | /* 16 bit DMA */
- DMA2D | /* 2D DMA */
- FLOW_AUTO /* autobuffer mode */
- );
-}
-
-void EnableDMA(void)
-{
- bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
- bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
-}
-
-/* Init TIMER0 as Frame Sync 1 generator */
-void InitTIMER0(void)
-{
- bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */
- SSYNC();
- bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */
- SSYNC();
-
- bfin_write_TIMER0_PERIOD(H_PERIOD);
- SSYNC();
- bfin_write_TIMER0_WIDTH(H_PULSE);
- SSYNC();
-
- bfin_write_TIMER0_CONFIG(
- PWM_OUT |
- PERIOD_CNT |
- TIN_SEL |
- CLK_SEL |
- EMU_RUN
- );
- SSYNC();
-}
-
-void EnableTIMER0(void)
-{
- bfin_write_TIMER_ENABLE(TIMEN0);
- SSYNC();
-}
-
-void DisableTIMER0(void)
-{
- bfin_write_TIMER_DISABLE(TIMDIS0);
- SSYNC();
-}
-
-
-void InitTIMER1(void)
-{
- bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */
- SSYNC();
- bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */
- SSYNC();
-
- bfin_write_TIMER1_PERIOD(V_PERIOD);
- SSYNC();
- bfin_write_TIMER1_WIDTH(V_PULSE);
- SSYNC();
-
- bfin_write_TIMER1_CONFIG(
- PWM_OUT |
- PERIOD_CNT |
- TIN_SEL |
- CLK_SEL |
- EMU_RUN
- );
- SSYNC();
-}
-
-void EnableTIMER1(void)
-{
- bfin_write_TIMER_ENABLE(TIMEN1);
- SSYNC();
-}
-
-void DisableTIMER1(void)
-{
- bfin_write_TIMER_DISABLE(TIMDIS1);
- SSYNC();
-}
-
-void EnableTIMER12(void)
-{
- bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
- SSYNC();
-}
-
-int video_init(void *dst)
-{
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
- lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
- lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
- LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
-#endif
- Init_Ports();
- Init_DMA(dst);
- EnableDMA();
- InitTIMER0();
- InitTIMER1();
- Init_PPI();
- EnablePPI();
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
- EnableTIMER12();
-#else
- /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
- EnableTIMER1();
- /* Add Some Delay ... */
- SSYNC();
- SSYNC();
- SSYNC();
- SSYNC();
-
- /* now start frame sync 1 */
- EnableTIMER0();
-#endif
-
- return 0;
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
- if (dcache_status())
- blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- /* Setup destination start address */
- bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
- + (y * LCD_X_RES * LCD_PIXEL_SIZE));
- /* Setup destination xcount */
- bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup destination xmodify */
- bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
- /* Setup destination ycount */
- bfin_write_MDMA_D0_Y_COUNT(logo->height);
- /* Setup destination ymodify */
- bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
- /* Setup Source start address */
- bfin_write_MDMA_S0_START_ADDR(logo->data);
- /* Setup Source xcount */
- bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup Source xmodify */
- bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
- /* Setup Source ycount */
- bfin_write_MDMA_S0_Y_COUNT(logo->height);
- /* Setup Source ymodify */
- bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
- /* Enable source DMA */
- bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
- SSYNC();
- bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
-
- while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
- bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-void video_stop(void)
-{
- DisablePPI();
- DisableDMA();
- DisableTIMER0();
- DisableTIMER1();
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
- lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
-#endif
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
- struct stdio_dev videodev;
-
- u8 *dst;
- u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
- dst = malloc(fbmem_size);
-
- if (dst == NULL) {
- printf("Failed to alloc FB memory\n");
- return -1;
- }
-
-#ifdef EASYLOGO_ENABLE_GZIP
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- unsigned long src_len = EASYLOGO_ENABLE_GZIP;
- error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
- bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- SizeT lzma_len = bfin_logo.size;
- error = lzmaBuffToBuffDecompress(data, &lzma_len,
- bfin_logo.data, EASYLOGO_ENABLE_LZMA);
- bfin_logo.data = data;
-#else
- error = 0;
-#endif
-
- if (error) {
- puts("Failed to decompress logo\n");
- free(dst);
- return -1;
- }
-
- memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
- dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
- (LCD_X_RES - bfin_logo.width) / 2,
- (LCD_Y_RES - bfin_logo.height) / 2);
-
- video_init(dst); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
-
- error = stdio_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
diff --git a/board/bf527-sdp/Kconfig b/board/bf527-sdp/Kconfig
deleted file mode 100644
index 928bd776b9e7..000000000000
--- a/board/bf527-sdp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_SDP
-
-config SYS_BOARD
- default "bf527-sdp"
-
-config SYS_CONFIG_NAME
- default "bf527-sdp"
-
-endif
diff --git a/board/bf527-sdp/MAINTAINERS b/board/bf527-sdp/MAINTAINERS
deleted file mode 100644
index 32ccfc5e9058..000000000000
--- a/board/bf527-sdp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-SDP BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf527-sdp/
-F: include/configs/bf527-sdp.h
-F: configs/bf527-sdp_defconfig
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
deleted file mode 100644
index 77acb423a587..000000000000
--- a/board/bf527-sdp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf527-sdp.o
diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c
deleted file mode 100644
index 0c6094b1e46d..000000000000
--- a/board/bf527-sdp/bf527-sdp.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
- printf("Board: ADI BF527 SDP board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
-
- /* Enable access to parallel flash */
- gpio_request(GPIO_PG0, "parallel-flash");
- gpio_direction_output(GPIO_PG0, 0);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- /* CLKIN Buffer Output Enable */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- return 0;
-}
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
deleted file mode 100644
index 1d46cfcd48ec..000000000000
--- a/board/bf527-sdp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/Kconfig b/board/bf533-ezkit/Kconfig
deleted file mode 100644
index 555ab298f24d..000000000000
--- a/board/bf533-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_EZKIT
-
-config SYS_BOARD
- default "bf533-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf533-ezkit"
-
-endif
diff --git a/board/bf533-ezkit/MAINTAINERS b/board/bf533-ezkit/MAINTAINERS
deleted file mode 100644
index bfa7c3cb29f2..000000000000
--- a/board/bf533-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf533-ezkit/
-F: include/configs/bf533-ezkit.h
-F: configs/bf533-ezkit_defconfig
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
deleted file mode 100644
index bf7a2c4477aa..000000000000
--- a/board/bf533-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf533-ezkit.o flash.o
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
deleted file mode 100644
index 6879319a70fa..000000000000
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include "psd4256.h"
-#include "flash-defines.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF533 EZ-Kit Lite board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
- /* Set direction bits for Video en/decoder reset as output */
- *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
- PSDA_VDEC_RST | PSDA_VENC_RST;
- /* Deactivate Video en/decoder reset lines */
- *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
- PSDA_VDEC_RST | PSDA_VENC_RST;
-
- return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/bf533-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
deleted file mode 100644
index 7822a9dfd724..000000000000
--- a/board/bf533-ezkit/flash-defines.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * U-Boot - flash-defines.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FLASHDEFINES_H__
-#define __FLASHDEFINES_H__
-
-#include <common.h>
-
-#define V_ULONG(a) (*(volatile unsigned long *)( a ))
-#define V_BYTE(a) (*(volatile unsigned char *)( a ))
-#define BUFFER_SIZE 0x80000
-#define NO_COMMAND 0
-#define GET_CODES 1
-#define RESET 2
-#define WRITE 3
-#define FILL 4
-#define ERASE_ALL 5
-#define ERASE_SECT 6
-#define READ 7
-#define GET_SECTNUM 8
-#define FLASH_START_L 0x0000
-#define FLASH_START_H 0x2000
-#define FLASH_TOT_SECT 40
-#define FLASH_SIZE 0x220000
-#define FLASH_MAN_ST 2
-#define CONFIG_SYS_FLASH0_BASE 0x20000000
-#define CONFIG_SYS_FLASH1_BASE 0x20200000
-#define RESET_VAL 0xF0
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int get_codes(void);
-int poll_toggle_bit(long lOffset);
-void reset_flash(void);
-int erase_flash(void);
-int erase_block_flash(int, unsigned long);
-void unlock_flash(long lOffset);
-int write_data(long lStart, long lCount, uchar *pnData);
-int FillData(long lStart, long lCount, long lStride, int *pnData);
-int read_data(long lStart, long lCount, long lStride, int *pnData);
-int read_flash(long nOffset, int *pnValue);
-int write_flash(long nOffset, int nValue);
-void get_sector_number(long lOffset, int *pnSector);
-int GetSectorProtectionStatus(flash_info_t * info, int nSector);
-int GetOffset(int nBlock);
-
-#define WRITESEQ1 0x0AAA
-#define WRITESEQ2 0x0554
-#define WRITESEQ3 0x0AAA
-#define WRITESEQ4 0x0AAA
-#define WRITESEQ5 0x0554
-#define WRITESEQ6 0x0AAA
-#define WRITEDATA1 0xaa
-#define WRITEDATA2 0x55
-#define WRITEDATA3 0x80
-#define WRITEDATA4 0xaa
-#define WRITEDATA5 0x55
-#define WRITEDATA6 0x10
-#define PriFlashABegin 0
-#define SecFlashABegin 32
-#define SecFlashBBegin 36
-#define PriFlashAOff 0x0
-#define PriFlashBOff 0x100000
-#define SecFlashAOff 0x200000
-#define SecFlashBOff 0x280000
-#define INVALIDLOCNSTART 0x20270000
-#define INVALIDLOCNEND 0x20280000
-#define BlockEraseVal 0x30
-#define UNLOCKDATA1 0xaa
-#define UNLOCKDATA2 0x55
-#define UNLOCKDATA3 0xa0
-#define GETCODEDATA1 0xaa
-#define GETCODEDATA2 0x55
-#define GETCODEDATA3 0x90
-#define SecFlashASec1Off 0x200000
-#define SecFlashASec2Off 0x204000
-#define SecFlashASec3Off 0x206000
-#define SecFlashASec4Off 0x208000
-#define SecFlashAEndOff 0x210000
-#define SecFlashBSec1Off 0x280000
-#define SecFlashBSec2Off 0x284000
-#define SecFlashBSec3Off 0x286000
-#define SecFlashBSec4Off 0x288000
-#define SecFlashBEndOff 0x290000
-
-#define SECT32 32
-#define SECT33 33
-#define SECT34 34
-#define SECT35 35
-#define SECT36 36
-#define SECT37 37
-#define SECT38 38
-#define SECT39 39
-
-#define FLASH_SUCCESS 0
-#define FLASH_FAIL -1
-
-#endif
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
deleted file mode 100644
index a7b3519d9505..000000000000
--- a/board/bf533-ezkit/flash.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * U-Boot - flash.c Flash driver for PSD4256GV
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include "flash-defines.h"
-
-int AFP_NumSectors = 40;
-long AFP_SectorSize1 = 0x10000;
-int AFP_SectorSize2 = 0x4000;
-
-void flash_reset(void)
-{
- reset_flash();
-}
-
-unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
-{
- int id = 0, i = 0;
- static int FlagDev = 1;
-
- id = get_codes();
- if (FlagDev) {
-#ifdef DEBUG
- printf("Device ID of the Flash is %x\n", id);
-#endif
- FlagDev = 0;
- }
- info->flash_id = id;
-
- switch (bank_flag) {
- case 0:
- for (i = PriFlashABegin; i < SecFlashABegin; i++)
- info->start[i] = (baseaddr + (i * AFP_SectorSize1));
- info->size = 0x200000;
- info->sector_count = 32;
- break;
- case 1:
- info->start[0] = baseaddr + SecFlashASec1Off;
- info->start[1] = baseaddr + SecFlashASec2Off;
- info->start[2] = baseaddr + SecFlashASec3Off;
- info->start[3] = baseaddr + SecFlashASec4Off;
- info->size = 0x10000;
- info->sector_count = 4;
- break;
- case 2:
- info->start[0] = baseaddr + SecFlashBSec1Off;
- info->start[1] = baseaddr + SecFlashBSec2Off;
- info->start[2] = baseaddr + SecFlashBSec3Off;
- info->start[3] = baseaddr + SecFlashBSec4Off;
- info->size = 0x10000;
- info->sector_count = 4;
- break;
- }
- return (info->size);
-}
-
-unsigned long flash_init(void)
-{
- unsigned long size_b0, size_b1, size_b2;
- int i;
-
- size_b0 = size_b1 = size_b2 = 0;
-#ifdef DEBUG
- printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
- printf("Memory Map for the Flash\n");
- printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
- printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
- printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
- printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
- printf("Please type command flinfo for information on Sectors \n");
-#endif
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
- size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
- size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 >> 20);
- }
-
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
- (flash_info[0].start[2] - 1), &flash_info[0]);
-
- return (size_b0 + size_b1 + size_b2);
-}
-
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id) {
- case FLASH_PSD4256GV:
- printf("ST Microelectronics ");
- break;
- default:
- printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
- break;
- }
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
- return;
-}
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- int cnt = 0, i;
- int prot, sect;
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot)
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- else
- printf("\n");
-
- cnt = s_last - s_first + 1;
-
- if (cnt == FLASH_TOT_SECT) {
- printf("Erasing flash, Please Wait \n");
- if (erase_flash() < 0) {
- printf("Erasing flash failed \n");
- return FLASH_FAIL;
- }
- } else {
- printf("Erasing Flash locations, Please Wait\n");
- for (i = s_first; i <= s_last; i++) {
- if (info->protect[i] == 0) { /* not protected */
- if (erase_block_flash(i, info->start[i]) < 0) {
- printf("Error Sector erasing \n");
- return FLASH_FAIL;
- }
- }
- }
- }
- return FLASH_SUCCESS;
-}
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- int ret;
- int d;
- if (addr % 2) {
- read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
- d = (int)((d & 0x00FF) | (*src++ << 8));
- ret = write_data(addr - 1, 2, (uchar *) & d);
- if (ret == FLASH_FAIL)
- return ERR_NOT_ERASED;
- ret = write_data(addr + 1, cnt - 1, src);
- } else
- ret = write_data(addr, cnt, src);
- if (ret == FLASH_FAIL)
- return ERR_NOT_ERASED;
- return FLASH_SUCCESS;
-}
-
-int write_data(long lStart, long lCount, uchar * pnData)
-{
- long i = 0;
- unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
- int d;
- int nSector = 0;
- int flag = 0;
-
- if (lCount % 2) {
- flag = 1;
- lCount = lCount - 1;
- }
-
- for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
- get_sector_number(ulOffset, &nSector);
- read_flash(ulOffset, &d);
- if (d != 0xffff) {
- printf
- ("Flash not erased@offset 0x%lx Please erase to reprogram\n",
- ulOffset);
- return FLASH_FAIL;
- }
- unlock_flash(ulOffset);
- d = (int)(pnData[i] | pnData[i + 1] << 8);
- write_flash(ulOffset, d);
- if (poll_toggle_bit(ulOffset) < 0) {
- printf("Error programming the flash \n");
- return FLASH_FAIL;
- }
- if ((i > 0) && (!(i % AFP_SectorSize2)))
- printf(".");
- }
- if (flag) {
- get_sector_number(ulOffset, &nSector);
- read_flash(ulOffset, &d);
- if (d != 0xffff) {
- printf
- ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
- ulOffset);
- return FLASH_FAIL;
- }
- unlock_flash(ulOffset);
- d = (int)(pnData[i] | (d & 0xFF00));
- write_flash(ulOffset, d);
- if (poll_toggle_bit(ulOffset) < 0) {
- printf("Error programming the flash \n");
- return FLASH_FAIL;
- }
- }
- return FLASH_SUCCESS;
-}
-
-int read_data(long ulStart, long lCount, long lStride, int *pnData)
-{
- long i = 0;
- int j = 0;
- long ulOffset = ulStart;
- int iShift = 0;
- int iNumWords = 2;
- int nLeftover = lCount % 4;
- int nHi, nLow;
- int nSector = 0;
-
- for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
- for (iShift = 0, j = 0; j < iNumWords; j += 2) {
- if ((ulOffset >= INVALIDLOCNSTART)
- && (ulOffset < INVALIDLOCNEND))
- return FLASH_FAIL;
-
- get_sector_number(ulOffset, &nSector);
- read_flash(ulOffset, &nLow);
- ulOffset += (lStride * 2);
- read_flash(ulOffset, &nHi);
- ulOffset += (lStride * 2);
- pnData[i] = (nHi << 16) | nLow;
- }
- }
- if (nLeftover > 0) {
- if ((ulOffset >= INVALIDLOCNSTART)
- && (ulOffset < INVALIDLOCNEND))
- return FLASH_FAIL;
-
- get_sector_number(ulOffset, &nSector);
- read_flash(ulOffset, &pnData[i]);
- }
- return FLASH_SUCCESS;
-}
-
-int write_flash(long nOffset, int nValue)
-{
- long addr;
-
- addr = (CONFIG_SYS_FLASH_BASE + nOffset);
- SSYNC();
- *(unsigned volatile short *)addr = nValue;
- SSYNC();
- if (poll_toggle_bit(nOffset) < 0)
- return FLASH_FAIL;
- return FLASH_SUCCESS;
-}
-
-int read_flash(long nOffset, int *pnValue)
-{
- int nValue = 0x0;
- long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
-
- if (nOffset != 0x2)
- reset_flash();
- SSYNC();
- nValue = *(volatile unsigned short *)addr;
- SSYNC();
- *pnValue = nValue;
- return true;
-}
-
-int poll_toggle_bit(long lOffset)
-{
- unsigned int u1, u2;
- unsigned long timeout = 0xFFFFFFFF;
- volatile unsigned long *FB =
- (volatile unsigned long *)(0x20000000 + lOffset);
- while (1) {
- if (timeout < 0)
- break;
- u1 = *(volatile unsigned short *)FB;
- u2 = *(volatile unsigned short *)FB;
- if ((u1 & 0x0040) == (u2 & 0x0040))
- return FLASH_SUCCESS;
- if ((u2 & 0x0020) == 0x0000)
- continue;
- u1 = *(volatile unsigned short *)FB;
- if ((u2 & 0x0040) == (u1 & 0x0040))
- return FLASH_SUCCESS;
- else {
- reset_flash();
- return FLASH_FAIL;
- }
- timeout--;
- }
- printf("Time out occurred \n");
- if (timeout < 0)
- return FLASH_FAIL;
-}
-
-void reset_flash(void)
-{
- write_flash(WRITESEQ1, RESET_VAL);
- /* Wait for 10 micro seconds */
- udelay(10);
-}
-
-int erase_flash(void)
-{
- write_flash(WRITESEQ1, WRITEDATA1);
- write_flash(WRITESEQ2, WRITEDATA2);
- write_flash(WRITESEQ3, WRITEDATA3);
- write_flash(WRITESEQ4, WRITEDATA4);
- write_flash(WRITESEQ5, WRITEDATA5);
- write_flash(WRITESEQ6, WRITEDATA6);
-
- if (poll_toggle_bit(0x0000) < 0)
- return FLASH_FAIL;
-
- write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
- write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
- write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
- write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
- write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
- write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
-
- if (poll_toggle_bit(SecFlashASec1Off) < 0)
- return FLASH_FAIL;
-
- write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
- write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
- write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
- write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
- write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
- write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
-
- if (poll_toggle_bit(PriFlashBOff) < 0)
- return FLASH_FAIL;
-
- write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
- write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
- write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
- write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
- write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
- write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
-
- if (poll_toggle_bit(SecFlashBOff) < 0)
- return FLASH_FAIL;
-
- return FLASH_SUCCESS;
-}
-
-int erase_block_flash(int nBlock, unsigned long address)
-{
- long ulSectorOff = 0x0;
-
- if ((nBlock < 0) || (nBlock > AFP_NumSectors))
- return false;
-
- ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
-
- write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
- write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
- write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
- write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
- write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
-
- write_flash(ulSectorOff, BlockEraseVal);
-
- if (poll_toggle_bit(ulSectorOff) < 0)
- return FLASH_FAIL;
-
- return FLASH_SUCCESS;
-}
-
-void unlock_flash(long ulOffset)
-{
- unsigned long ulOffsetAddr = ulOffset;
- ulOffsetAddr &= 0xFFFF0000;
-
- write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
- write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
- write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
-}
-
-int get_codes()
-{
- int dev_id = 0;
-
- write_flash(WRITESEQ1, GETCODEDATA1);
- write_flash(WRITESEQ2, GETCODEDATA2);
- write_flash(WRITESEQ3, GETCODEDATA3);
-
- read_flash(0x0002, &dev_id);
- dev_id &= 0x00FF;
-
- reset_flash();
-
- return dev_id;
-}
-
-void get_sector_number(long ulOffset, int *pnSector)
-{
- int nSector = 0;
-
- if (ulOffset >= SecFlashAOff) {
- if ((ulOffset < SecFlashASec1Off)
- && (ulOffset < SecFlashASec2Off)) {
- nSector = SECT32;
- } else if ((ulOffset >= SecFlashASec2Off)
- && (ulOffset < SecFlashASec3Off)) {
- nSector = SECT33;
- } else if ((ulOffset >= SecFlashASec3Off)
- && (ulOffset < SecFlashASec4Off)) {
- nSector = SECT34;
- } else if ((ulOffset >= SecFlashASec4Off)
- && (ulOffset < SecFlashAEndOff)) {
- nSector = SECT35;
- }
- } else if (ulOffset >= SecFlashBOff) {
- if ((ulOffset < SecFlashBSec1Off)
- && (ulOffset < SecFlashBSec2Off)) {
- nSector = SECT36;
- }
- if ((ulOffset < SecFlashBSec2Off)
- && (ulOffset < SecFlashBSec3Off)) {
- nSector = SECT37;
- }
- if ((ulOffset < SecFlashBSec3Off)
- && (ulOffset < SecFlashBSec4Off)) {
- nSector = SECT38;
- }
- if ((ulOffset < SecFlashBSec4Off)
- && (ulOffset < SecFlashBEndOff)) {
- nSector = SECT39;
- }
- } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
- nSector = ulOffset & 0xffff0000;
- nSector = ulOffset >> 16;
- nSector = nSector & 0x000ff;
- }
-
- if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
- *pnSector = nSector;
- }
-}
diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h
deleted file mode 100644
index 925669644e16..000000000000
--- a/board/bf533-ezkit/psd4256.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * U-Boot - psd4256.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Flash A/B Port A configuration registers.
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define PSD_PORTA_DIN 0x070000
-#define PSD_PORTA_DOUT 0x070004
-#define PSD_PORTA_DIR 0x070006
-
-/*
- * Flash A/B Port B configuration registers
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define PSD_PORTB_DIN 0x070001
-#define PSD_PORTB_DOUT 0x070005
-#define PSD_PORTB_DIR 0x070007
-
-/*
- * Flash A Port A Bit definitions
- */
-
-#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
-#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
-#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
-#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
-#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
-
-/*
- * Flash A Port B Bit definitions
- */
-
-#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
-#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
-#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
-#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
-#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
-#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */
diff --git a/board/bf533-stamp/Kconfig b/board/bf533-stamp/Kconfig
deleted file mode 100644
index 0cffde3b47b6..000000000000
--- a/board/bf533-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_STAMP
-
-config SYS_BOARD
- default "bf533-stamp"
-
-config SYS_CONFIG_NAME
- default "bf533-stamp"
-
-endif
diff --git a/board/bf533-stamp/MAINTAINERS b/board/bf533-stamp/MAINTAINERS
deleted file mode 100644
index c7aeefaee0e9..000000000000
--- a/board/bf533-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-STAMP BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf533-stamp/
-F: include/configs/bf533-stamp.h
-F: configs/bf533-stamp_defconfig
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
deleted file mode 100644
index 041c98e19cb8..000000000000
--- a/board/bf533-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf533-stamp.o
-obj-$(CONFIG_STAMP_CF) += ide-cf.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
deleted file mode 100644
index 185a651bec8e..000000000000
--- a/board/bf533-stamp/bf533-stamp.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF533 Stamp board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-/* PF0 and PF1 are used to switch between the ethernet and flash:
- * PF0 PF1
- * flash: 0 0
- * ether: 1 0
- */
-void swap_to(int device_id)
-{
- gpio_request(GPIO_PF0, "eth_flash_swap");
- gpio_request(GPIO_PF1, "eth_flash_swap");
- gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
- gpio_direction_output(GPIO_PF1, 0);
- SSYNC();
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_STAMP_CF
- cf_ide_init();
-#endif
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_LED_STATUS_OFF 0
-#define CONFIG_LED_STATUS_ON 1
-
-static int gpio_setup;
-
-static void stamp_led_set(int LED1, int LED2, int LED3)
-{
- if (!gpio_setup) {
- gpio_request(GPIO_PF2, "boot_progress");
- gpio_request(GPIO_PF3, "boot_progress");
- gpio_request(GPIO_PF4, "boot_progress");
- gpio_direction_output(GPIO_PF2, LED1);
- gpio_direction_output(GPIO_PF3, LED2);
- gpio_direction_output(GPIO_PF4, LED3);
- gpio_setup = 1;
- } else {
- gpio_set_value(GPIO_PF2, LED1);
- gpio_set_value(GPIO_PF3, LED2);
- gpio_set_value(GPIO_PF4, LED3);
- }
-}
-
-void show_boot_progress(int status)
-{
- switch (status) {
- case BOOTSTAGE_ID_CHECK_MAGIC:
- stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF,
- CONFIG_LED_STATUS_ON);
- break;
- case BOOTSTAGE_ID_CHECK_HEADER:
- stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_ON,
- CONFIG_LED_STATUS_OFF);
- break;
- case BOOTSTAGE_ID_CHECK_CHECKSUM:
- stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_ON,
- CONFIG_LED_STATUS_ON);
- break;
- case BOOTSTAGE_ID_CHECK_ARCH:
- stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_OFF,
- CONFIG_LED_STATUS_OFF);
- break;
- case BOOTSTAGE_ID_CHECK_IMAGETYPE:
- case BOOTSTAGE_ID_DECOMP_IMAGE:
- stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_OFF,
- CONFIG_LED_STATUS_ON);
- break;
- case BOOTSTAGE_ID_KERNEL_LOADED:
- case BOOTSTAGE_ID_CHECK_BOOT_OS:
- stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_ON,
- CONFIG_LED_STATUS_OFF);
- break;
- case BOOTSTAGE_ID_BOOT_OS_RETURNED:
- case BOOTSTAGE_ID_RD_MAGIC:
- case BOOTSTAGE_ID_RD_HDR_CHECKSUM:
- case BOOTSTAGE_ID_RD_CHECKSUM:
- case BOOTSTAGE_ID_RAMDISK:
- case BOOTSTAGE_ID_NO_RAMDISK:
- case BOOTSTAGE_ID_RUN_OS:
- stamp_led_set(CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF,
- CONFIG_LED_STATUS_OFF);
- break;
- default:
- stamp_led_set(CONFIG_LED_STATUS_ON, CONFIG_LED_STATUS_ON,
- CONFIG_LED_STATUS_ON);
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/bf533-stamp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c
deleted file mode 100644
index 3e4080e28fb2..000000000000
--- a/board/bf533-stamp/ide-cf.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
- /* "ETHERNET" means the expansion memory banks */
- swap_to(ETHERNET);
-
- *addr = val;
- SSYNC();
-
- swap_to(FLASH);
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
- unsigned char c;
-
- swap_to(ETHERNET);
-
- c = *addr;
- SSYNC();
-
- swap_to(FLASH);
-
- return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
- int i;
-
- swap_to(ETHERNET);
-
- for (i = 0; i < words; i++) {
- *(sect_buf + i) = *addr;
- SSYNC();
- }
-
- swap_to(FLASH);
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
- int i;
-
- swap_to(ETHERNET);
-
- for (i = 0; i < words; i++) {
- *addr = *(sect_buf + i);
- SSYNC();
- }
-
- swap_to(FLASH);
-}
-
-/* Definitions used in Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS 0x0000
-#define FIO_POLAR_CF_BITS 0x0000
-#define FIO_EDGE_BITS 0x1E0
-#define FIO_POLAR_BITS 0x160
-
-/* Compact flash status bits in status register */
-#define CF_STAT_BITS 0x00000060
-
-void cf_ide_init(void)
-{
- int i, cf_stat;
-
- /* Check whether CF card is inserted */
- bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
- bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
- for (i = 0; i < 0x300; i++)
- asm volatile("nop;");
-
- cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
-
- bfin_write_FIO_EDGE(FIO_EDGE_BITS);
- bfin_write_FIO_POLAR(FIO_POLAR_BITS);
-
- if (!cf_stat) {
- for (i = 0; i < 0x3000; i++)
- asm volatile("nop;");
-
- ide_init();
- }
-}
diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c
deleted file mode 100644
index e9b9a9abdfdd..000000000000
--- a/board/bf533-stamp/video.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * BF533-STAMP splash driver
- *
- * Copyright (c) 2006-2008 Analog Devices Inc.
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio at tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#define DMA_SIZE16 2
-
-#include <asm/mach-common/bits/ppi.h>
-
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE 720 * 240 */
-#define VERTICAL 2
-#define HORIZONTAL 4
-
-int is_vblank_line(const int line)
-{
- /*
- * This array contains a single bit for each line in
- * an NTSC frame.
- */
- if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
- return true;
-
- return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
- const int NTSC_frames = 1;
- const int NTSC_lines = 525;
- char *dest = base_address;
- int frame_num, line_num;
-
- for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
- for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
- unsigned int code;
- int offset = 0;
- int i;
-
- if (is_vblank_line(line_num))
- offset++;
-
- if (line_num > 266 || line_num < 3)
- offset += 2;
-
- /* Output EAV code */
- code = system_code_map[offset].eav;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output horizontal blanking */
- for (i = 0; i < 67 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
-
- /* Output SAV */
- code = system_code_map[offset].sav;
- write_dest_byte((char)(code >> 24) & 0xff);
- write_dest_byte((char)(code >> 16) & 0xff);
- write_dest_byte((char)(code >> 8) & 0xff);
- write_dest_byte((char)(code) & 0xff);
-
- /* Output empty horizontal data */
- for (i = 0; i < 360 * 2; ++i) {
- write_dest_byte(0x80);
- write_dest_byte(0x10);
- }
- }
- }
-
- return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
- int *OddPtr32;
- int OddLine;
- int *EvenPtr32;
- int EvenLine;
- int i;
- int *data;
- int m, n;
-
- /* fill odd and even frames */
- for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
- OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
- EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
- for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
- *OddPtr32 = Value;
- *EvenPtr32 = Value;
- }
- }
-
- for (m = 0; m < VERTICAL; m++) {
- data = (int *)u_boot_logo.data;
- for (OddLine = (22 + m), EvenLine = (285 + m);
- OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
- OddLine += VERTICAL, EvenLine += VERTICAL) {
- OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
- EvenPtr32 =
- (int *)((Frame + ((EvenLine) * 1716)) + 276);
- for (i = 0; i < u_boot_logo.width / 2; i++) {
- /* enlarge one pixel to m x n */
- for (n = 0; n < HORIZONTAL; n++) {
- *OddPtr32++ = *data;
- *EvenPtr32++ = *data;
- }
- data++;
- }
- }
- }
-}
-
-static void video_init(char *NTSCFrame)
-{
- NTSC_framebuffer_init(NTSCFrame);
- fill_frame(NTSCFrame, BLUE);
-
- bfin_write_PPI_CONTROL(0x0082);
- bfin_write_PPI_FRAME(0x020D);
-
- bfin_write_DMA0_START_ADDR(NTSCFrame);
- bfin_write_DMA0_X_COUNT(0x035A);
- bfin_write_DMA0_X_MODIFY(0x0002);
- bfin_write_DMA0_Y_COUNT(0x020D);
- bfin_write_DMA0_Y_MODIFY(0x0002);
- bfin_write_DMA0_CONFIG(0x1015);
- bfin_write_PPI_CONTROL(0x0083);
-}
-
-void video_stop(void)
-{
- bfin_write_PPI_CONTROL(0);
- bfin_write_DMA0_CONFIG(0);
-}
-
-int drv_video_init(void)
-{
- struct stdio_dev videodev;
-
- video_init((void *)NTSC_FRAME_ADDR);
-
- memset(&videodev, 0, sizeof(videodev));
- strcpy(videodev.name, "video");
-
- return stdio_register(&videodev);
-}
diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h
deleted file mode 100644
index 949c3d8f3f7c..000000000000
--- a/board/bf533-stamp/video.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK (0x01800180) /* black pixel pattern */
-#define BLUE (0x296E29F0) /* blue pixel pattern */
-#define RED (0x51F0515A) /* red pixel pattern */
-#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
-#define GREEN (0x91229136) /* green pixel pattern */
-#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
-#define YELLOW (0xD292D210) /* yellow pixel pattern */
-#define WHITE (0xFE80FE80) /* white pixel pattern */
-
-typedef struct {
- unsigned int sav;
- unsigned int eav;
-} system_code_type;
-
-const system_code_type system_code_map[] = {
- { 0xFF000080, 0xFF00009D },
- { 0xFF0000AB, 0xFF0000B6 },
- { 0xFF0000C7, 0xFF0000DA },
- { 0xFF0000EC, 0xFF0000F1 },
-};
diff --git a/board/bf537-minotaur/Kconfig b/board/bf537-minotaur/Kconfig
deleted file mode 100644
index 204f609e0905..000000000000
--- a/board/bf537-minotaur/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_MINOTAUR
-
-config SYS_BOARD
- default "bf537-minotaur"
-
-config SYS_CONFIG_NAME
- default "bf537-minotaur"
-
-endif
diff --git a/board/bf537-minotaur/MAINTAINERS b/board/bf537-minotaur/MAINTAINERS
deleted file mode 100644
index 04643b1afdf1..000000000000
--- a/board/bf537-minotaur/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-MINOTAUR BOARD
-M: Martin Strubel <strubel@section5.ch>
-S: Maintained
-F: board/bf537-minotaur/
-F: include/configs/bf537-minotaur.h
-F: configs/bf537-minotaur_defconfig
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
deleted file mode 100644
index 13ed8bfa220b..000000000000
--- a/board/bf537-minotaur/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf537-minotaur.o
diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c
deleted file mode 100644
index 34750eca5133..000000000000
--- a/board/bf537-minotaur/bf537-minotaur.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: CSP BF537 Minotaur board\n");
- printf(" Support: http://www.camsig.co.uk/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk
deleted file mode 100644
index 7402f449b021..000000000000
--- a/board/bf537-minotaur/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-pnav/Kconfig b/board/bf537-pnav/Kconfig
deleted file mode 100644
index acb1f8923300..000000000000
--- a/board/bf537-pnav/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_PNAV
-
-config SYS_BOARD
- default "bf537-pnav"
-
-config SYS_CONFIG_NAME
- default "bf537-pnav"
-
-endif
diff --git a/board/bf537-pnav/MAINTAINERS b/board/bf537-pnav/MAINTAINERS
deleted file mode 100644
index b8b22a3d4601..000000000000
--- a/board/bf537-pnav/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-PNAV BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf537-pnav/
-F: include/configs/bf537-pnav.h
-F: configs/bf537-pnav_defconfig
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
deleted file mode 100644
index f7af8cd5ae3e..000000000000
--- a/board/bf537-pnav/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf537-pnav.o
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
deleted file mode 100644
index c3b06f09fc1d..000000000000
--- a/board/bf537-pnav/bf537-pnav.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF537 PNAV board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/Kconfig b/board/bf537-srv1/Kconfig
deleted file mode 100644
index 2ddcd69482c3..000000000000
--- a/board/bf537-srv1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_SRV1
-
-config SYS_BOARD
- default "bf537-srv1"
-
-config SYS_CONFIG_NAME
- default "bf537-srv1"
-
-endif
diff --git a/board/bf537-srv1/MAINTAINERS b/board/bf537-srv1/MAINTAINERS
deleted file mode 100644
index c8f1458656e8..000000000000
--- a/board/bf537-srv1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-SRV1 BOARD
-M: Martin Strubel <strubel@section5.ch>
-S: Maintained
-F: board/bf537-srv1/
-F: include/configs/bf537-srv1.h
-F: configs/bf537-srv1_defconfig
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
deleted file mode 100644
index 1815fc5f8ba0..000000000000
--- a/board/bf537-srv1/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf537-srv1.o
diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c
deleted file mode 100644
index fc22c0710251..000000000000
--- a/board/bf537-srv1/bf537-srv1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Surveyor SRV1 board\n");
- printf(" Support: http://www.surveyor.com/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk
deleted file mode 100644
index 7402f449b021..000000000000
--- a/board/bf537-srv1/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/Kconfig b/board/bf537-stamp/Kconfig
deleted file mode 100644
index 4f86128e9cc7..000000000000
--- a/board/bf537-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_STAMP
-
-config SYS_BOARD
- default "bf537-stamp"
-
-config SYS_CONFIG_NAME
- default "bf537-stamp"
-
-endif
diff --git a/board/bf537-stamp/MAINTAINERS b/board/bf537-stamp/MAINTAINERS
deleted file mode 100644
index 7d9c1334bf50..000000000000
--- a/board/bf537-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-STAMP BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf537-stamp/
-F: include/configs/bf537-stamp.h
-F: configs/bf537-stamp_defconfig
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
deleted file mode 100644
index 4008e3a2d43d..000000000000
--- a/board/bf537-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf537-stamp.o
-obj-$(CONFIG_BFIN_IDE) += ide-cf.o
-obj-$(CONFIG_HAS_POST) += post-memory.o
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
deleted file mode 100644
index 1f90c003bc2a..000000000000
--- a/board/bf537-stamp/bf537-stamp.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF537 stamp board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we cram the MAC in the last flash sector */
- uchar *board_mac_addr = (uchar *)0x203F0000;
- if (is_valid_ethaddr(board_mac_addr)) {
- memcpy(mac_addr, board_mac_addr, 6);
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we use the last sector for the MAC address / POST LDR */
- extern flash_info_t flash_info[];
- flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_BFIN_IDE
- cf_ide_init();
-#endif
-
- return 0;
-}
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
deleted file mode 100644
index ab0fbecab93b..000000000000
--- a/board/bf537-stamp/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/ide-cf.c b/board/bf537-stamp/ide-cf.c
deleted file mode 100644
index 5a3720de5a8d..000000000000
--- a/board/bf537-stamp/ide-cf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
- *(addr) = val;
- SSYNC();
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
- volatile unsigned char c;
-
- c = *(addr);
- SSYNC();
-
- return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
- int i;
-
- for (i = 0; i < words; i++)
- *(sect_buf + i) = *(addr);
- SSYNC();
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
- int i;
-
- for (i = 0; i < words; i++)
- *(addr) = *(sect_buf + i);
- SSYNC();
-}
-
-void cf_ide_init(void)
-{
-#if defined(CONFIG_BFIN_TRUE_IDE)
- /* Enable ATASEL when in True IDE mode */
- printf("Using CF True IDE Mode\n");
- cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
- udelay(1000);
-#elif defined(CONFIG_BFIN_CF_IDE)
- /* Disable ATASEL when we're in Common Memory Mode */
- printf("Using CF Common Memory Mode\n");
- cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
- udelay(1000);
-#elif defined(CONFIG_BFIN_HDD_IDE)
- printf("Using HDD IDE Mode\n");
-#endif
- ide_init();
-}
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
deleted file mode 100644
index 2dea92fbe9b8..000000000000
--- a/board/bf537-stamp/post-memory.c
+++ /dev/null
@@ -1,257 +0,0 @@
-#include <common.h>
-#include <asm/io.h>
-
-#include <post.h>
-#include <watchdog.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
-#define CLKIN 25000000
-#define PATTERN1 0x5A5A5A5A
-#define PATTERN2 0xAAAAAAAA
-
-#define CCLK_NUM 4
-#define SCLK_NUM 3
-
-void post_out_buff(char *buff);
-void post_init_pll(int mult, int div);
-int post_init_sdram(int sclk);
-void post_init_uart(int sclk);
-
-const int pll[CCLK_NUM][SCLK_NUM][2] = {
- { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
- { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */
- { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */
- { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */
-};
-const char *const log[CCLK_NUM][SCLK_NUM] = {
- {"CCLK-500MHz SCLK-125MHz: Writing...\0",
- "CCLK-500MHz SCLK-100MHz: Writing...\0",
- "CCLK-500MHz SCLK- 50MHz: Writing...\0",},
- {"CCLK-400MHz SCLK-100MHz: Writing...\0",
- "CCLK-400MHz SCLK- 80MHz: Writing...\0",
- "CCLK-400MHz SCLK- 50MHz: Writing...\0",},
- {"CCLK-200MHz SCLK-100MHz: Writing...\0",
- "CCLK-200MHz SCLK- 50MHz: Writing...\0",
- "CCLK-200MHz SCLK- 40MHz: Writing...\0",},
- {"CCLK-100MHz SCLK-100MHz: Writing...\0",
- "CCLK-100MHz SCLK- 50MHz: Writing...\0",
- "CCLK-100MHz SCLK- 25MHz: Writing...\0",},
-};
-
-int memory_post_test(int flags)
-{
- int addr;
- int m, n;
- int sclk, sclk_temp;
- int ret = 1;
-
- sclk_temp = CLKIN / 1000000;
- sclk_temp = sclk_temp * CONFIG_VCO_MULT;
- for (sclk = 0; sclk_temp > 0; sclk++)
- sclk_temp -= CONFIG_SCLK_DIV;
- sclk = sclk * 1000000;
- post_init_uart(sclk);
- if (post_hotkeys_pressed() == 0)
- return 0;
-
- for (m = 0; m < CCLK_NUM; m++) {
- for (n = 0; n < SCLK_NUM; n++) {
- /* Calculate the sclk */
- sclk_temp = CLKIN / 1000000;
- sclk_temp = sclk_temp * pll[m][n][0];
- for (sclk = 0; sclk_temp > 0; sclk++)
- sclk_temp -= pll[m][n][1];
- sclk = sclk * 1000000;
-
- post_init_pll(pll[m][n][0], pll[m][n][1]);
- post_init_sdram(sclk);
- post_init_uart(sclk);
- post_out_buff("\n\r\0");
- post_out_buff(log[m][n]);
- for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
- *(unsigned long *)addr = PATTERN1;
- post_out_buff("Reading...\0");
- for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
- if ((*(unsigned long *)addr) != PATTERN1) {
- post_out_buff("Error\n\r\0");
- ret = 0;
- }
- }
- post_out_buff("OK\n\r\0");
- }
- }
- if (ret)
- post_out_buff("memory POST passed\n\r\0");
- else
- post_out_buff("memory POST failed\n\r\0");
-
- post_out_buff("\n\r\n\r\0");
- return 1;
-}
-
-void post_init_uart(int sclk)
-{
- int divisor;
-
- for (divisor = 0; sclk > 0; divisor++)
- sclk -= 57600 * 16;
-
- bfin_write_PORTF_FER(0x000F);
- bfin_write_PORTH_FER(0xFFFF);
-
- bfin_write_UART_GCTL(0x00);
- bfin_write_UART_LCR(0x83);
- SSYNC();
- bfin_write_UART_DLL(divisor & 0xFF);
- SSYNC();
- bfin_write_UART_DLH((divisor >> 8) & 0xFF);
- SSYNC();
- bfin_write_UART_LCR(0x03);
- SSYNC();
- bfin_write_UART_GCTL(0x01);
- SSYNC();
-}
-
-void post_out_buff(char *buff)
-{
-
- int i = 0;
- for (i = 0; i < 0x80000; i++)
- ;
- i = 0;
- while ((buff[i] != '\0') && (i != 100)) {
- while (!(bfin_read_pUART_LSR() & 0x20)) ;
- bfin_write_UART_THR(buff[i]);
- SSYNC();
- i++;
- }
- for (i = 0; i < 0x80000; i++)
- ;
-}
-
-void post_init_pll(int mult, int div)
-{
-
- bfin_write_SIC_IWR(0x01);
- bfin_write_PLL_CTL((mult << 9));
- bfin_write_PLL_DIV(div);
- asm("CLI R2;");
- asm("IDLE;");
- asm("STI R2;");
- while (!(bfin_read_PLL_STAT() & 0x20)) ;
-}
-
-int post_init_sdram(int sclk)
-{
- int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
- SDRAM_tWR;
- int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
- mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
-
- if ((sclk > 119402985)) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_7;
- SDRAM_tRAS_num = 7;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 104477612) && (sclk <= 119402985)) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_6;
- SDRAM_tRAS_num = 6;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 89552239) && (sclk <= 104477612)) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_5;
- SDRAM_tRAS_num = 5;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 74626866) && (sclk <= 89552239)) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_4;
- SDRAM_tRAS_num = 4;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 66666667) && (sclk <= 74626866)) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_3;
- SDRAM_tRAS_num = 3;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 59701493) && (sclk <= 66666667)) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_4;
- SDRAM_tRAS_num = 4;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 44776119) && (sclk <= 59701493)) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_3;
- SDRAM_tRAS_num = 3;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
- } else if ((sclk > 29850746) && (sclk <= 44776119)) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_2;
- SDRAM_tRAS_num = 2;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
- } else if (sclk <= 29850746) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_1;
- SDRAM_tRAS_num = 1;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
- } else {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_1;
- SDRAM_tRAS_num = 1;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
- }
- /*SDRAM INFORMATION: */
- SDRAM_Tref = 64; /* Refresh period in milliseconds */
- SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
- SDRAM_CL = CL_3; /* 2 */
-
- SDRAM_SIZE = EBSZ_64;
- SDRAM_WIDTH = EBCAW_10;
-
- mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
-
- /* Equation from section 17 (p17-46) of BF533 HRM */
- mem_SDRRC =
- (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
- (SDRAM_tRAS_num + SDRAM_tRP_num);
-
- /* Enable SCLK Out */
- mem_SDGCTL =
- (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
- | PSS);
-
- SSYNC();
-
- bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
- /* Set the SDRAM Refresh Rate control register based on SSCLK value */
- bfin_write_EBIU_SDRRC(mem_SDRRC);
-
- /* SDRAM Memory Bank Control Register */
- bfin_write_EBIU_SDBCTL(mem_SDBCTL);
-
- /* SDRAM Memory Global Control Register */
- bfin_write_EBIU_SDGCTL(mem_SDGCTL);
- SSYNC();
- return mem_SDRRC;
-}
-
-#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
diff --git a/board/bf538f-ezkit/Kconfig b/board/bf538f-ezkit/Kconfig
deleted file mode 100644
index e40fcdb2a258..000000000000
--- a/board/bf538f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF538F_EZKIT
-
-config SYS_BOARD
- default "bf538f-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf538f-ezkit"
-
-endif
diff --git a/board/bf538f-ezkit/MAINTAINERS b/board/bf538f-ezkit/MAINTAINERS
deleted file mode 100644
index 7964735e6d6f..000000000000
--- a/board/bf538f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF538F-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf538f-ezkit/
-F: include/configs/bf538f-ezkit.h
-F: configs/bf538f-ezkit_defconfig
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
deleted file mode 100644
index eb1703e89717..000000000000
--- a/board/bf538f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf538f-ezkit.o
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
deleted file mode 100644
index 2dd4c0c4d17e..000000000000
--- a/board/bf538f-ezkit/bf538f-ezkit.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF538F EZ-Kit Lite board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/bf538f-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/Kconfig b/board/bf548-ezkit/Kconfig
deleted file mode 100644
index 550227fa3083..000000000000
--- a/board/bf548-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF548_EZKIT
-
-config SYS_BOARD
- default "bf548-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf548-ezkit"
-
-endif
diff --git a/board/bf548-ezkit/MAINTAINERS b/board/bf548-ezkit/MAINTAINERS
deleted file mode 100644
index e2683bb474fa..000000000000
--- a/board/bf548-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF548-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf548-ezkit/
-F: include/configs/bf548-ezkit.h
-F: configs/bf548-ezkit_defconfig
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
deleted file mode 100644
index e4d0caaac41d..000000000000
--- a/board/bf548-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf548-ezkit.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
deleted file mode 100644
index 31d6eeec0cef..000000000000
--- a/board/bf548-ezkit/bf548-ezkit.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF548 EZ-Kit board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* Set async addr lines as peripheral */
- const unsigned short pins[] = {
- P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
- P_A21, P_A22, P_A23, P_A24, 0
- };
- return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
- return bfin_mmc_init(bis);
-}
-#endif
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
- /*
- * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
- * and OTG host modes, while rev 1.1 and greater require PE7 to
- * be low for device mode and high for host mode. We set it high
- * here because we are in host mode.
- */
- gpio_request(GPIO_PE7, "musb-vbus");
- gpio_direction_output(GPIO_PE7, 1);
-}
-#endif
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
deleted file mode 100644
index 7bb8e9c9ee56..000000000000
--- a/board/bf548-ezkit/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART := --dma 1
-LDR_FLAGS-BFIN_BOOT_NAND := --dma 6
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
deleted file mode 100644
index 37659932f204..000000000000
--- a/board/bf548-ezkit/video.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16 2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES 480 /*Horizontal Resolution */
-#define LCD_Y_RES 272 /* Vertical Resolution */
-
-#define LCD_BPP 24 /* Bit Per Pixel */
-#define LCD_PIXEL_SIZE (LCD_BPP / 8)
-#define DMA_BUS_SIZE 32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* -- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period TH - 525 - Clock
- * Pulse width THp - 41 - Clock
- * Horizontal period THd - 480 - Clock
- * Back porch THb - 2 - Clock
- * Front porch THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period TV - 286 - Line
- * Pulse width TVp - 10 - Line
- * Vertical period TVd - 272 - Line
- * Back porch TVb - 2 - Line
- * Front porch TVf - 2 - Line
- */
-
-#define LCD_CLK (8*1000*1000) /* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE 525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME 286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL 41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY 43
-
-/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB (EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY 12
-
-#define EPPI_CLIP 0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL (0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
- u32 sclk = get_sclk();
-
- /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
- return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
- u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
- bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
- bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
- bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
- bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
- bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
- bfin_write_EPPI0_FRAME(EPPI_FRAME);
- bfin_write_EPPI0_LINE(EPPI_LINE);
-
- bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
- bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
- bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
- bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
- bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
- bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
- RGB_FMT_EN);
-#else
- bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
- ~RGB_FMT_EN);
-#endif
-
-}
-
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
- bfin_write_DMA12_START_ADDR(dst);
-
- /* X count */
- bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
- bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
- /* Y count */
- bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
- bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
- /* DMA Config */
- bfin_write_DMA12_CONFIG(
- WDSIZE_32 | /* 32 bit DMA */
- DMA2D | /* 2D DMA */
- FLOW_AUTO /* autobuffer mode */
- );
-}
-
-void Init_Ports(void)
-{
- const unsigned short pins[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
- P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
- P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
- P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
- P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
- P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
- };
- peripheral_request_list(pins, "lcd");
-
- gpio_request(GPIO_PE3, "lcd-disp");
- gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
- bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
- bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
- Init_Ports();
- Init_DMA(dst);
- EnableDMA();
- Init_PPI();
- EnablePPI();
-
- return 0;
-}
-
-void video_stop(void)
-{
- DisablePPI();
- DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
- if (dcache_status())
- blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- /* Setup destination start address */
- bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
- + (y * LCD_X_RES * LCD_PIXEL_SIZE));
- /* Setup destination xcount */
- bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup destination xmodify */
- bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
- /* Setup destination ycount */
- bfin_write_MDMA_D0_Y_COUNT(logo->height);
- /* Setup destination ymodify */
- bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
- /* Setup Source start address */
- bfin_write_MDMA_S0_START_ADDR(logo->data);
- /* Setup Source xcount */
- bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup Source xmodify */
- bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
- /* Setup Source ycount */
- bfin_write_MDMA_S0_Y_COUNT(logo->height);
- /* Setup Source ymodify */
- bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
- /* Enable source DMA */
- bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
- SSYNC();
- bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
-
- while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
- bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
- struct stdio_dev videodev;
-
- u8 *dst;
- u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
- dst = malloc(fbmem_size);
-
- if (dst == NULL) {
- printf("Failed to alloc FB memory\n");
- return -1;
- }
-
-#ifdef EASYLOGO_ENABLE_GZIP
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- unsigned long src_len = EASYLOGO_ENABLE_GZIP;
- error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
- bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- SizeT lzma_len = bfin_logo.size;
- error = lzmaBuffToBuffDecompress(data, &lzma_len,
- bfin_logo.data, EASYLOGO_ENABLE_LZMA);
- bfin_logo.data = data;
-#else
- error = 0;
-#endif
-
- if (error) {
- puts("Failed to decompress logo\n");
- free(dst);
- return -1;
- }
-
- memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
- dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
- (LCD_X_RES - bfin_logo.width) / 2,
- (LCD_Y_RES - bfin_logo.height) / 2);
-
- video_init(dst); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
-
- error = stdio_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
diff --git a/board/bf561-acvilon/Kconfig b/board/bf561-acvilon/Kconfig
deleted file mode 100644
index ba1580d87be7..000000000000
--- a/board/bf561-acvilon/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_ACVILON
-
-config SYS_BOARD
- default "bf561-acvilon"
-
-config SYS_CONFIG_NAME
- default "bf561-acvilon"
-
-endif
diff --git a/board/bf561-acvilon/MAINTAINERS b/board/bf561-acvilon/MAINTAINERS
deleted file mode 100644
index 056ee0bdb749..000000000000
--- a/board/bf561-acvilon/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-ACVILON BOARD
-M: Valentin Yakovenkov <yakovenkov@niistt.ru>
-S: Maintained
-F: board/bf561-acvilon/
-F: include/configs/bf561-acvilon.h
-F: configs/bf561-acvilon_defconfig
diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile
deleted file mode 100644
index 08e2fad61e76..000000000000
--- a/board/bf561-acvilon/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf561-acvilon.o
diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c
deleted file mode 100644
index da4c8444e12b..000000000000
--- a/board/bf561-acvilon/bf561-acvilon.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * File: board/bf561-acvilon/bf561-acvilon.c
- * Based on: board/bf561-ezkit/bf561-ezkit.c
- * Author:
- *
- * Created: 2009-06-23
- * Description: Acvilon System On Module board file
- *
- * Modified:
- * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Bugs:
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
- printf(" Support: http://www.niistt.ru/\n");
- return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
deleted file mode 100644
index 854d7dbb8632..000000000000
--- a/board/bf561-acvilon/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/Kconfig b/board/bf561-ezkit/Kconfig
deleted file mode 100644
index 495a5c51eb9c..000000000000
--- a/board/bf561-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_EZKIT
-
-config SYS_BOARD
- default "bf561-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf561-ezkit"
-
-endif
diff --git a/board/bf561-ezkit/MAINTAINERS b/board/bf561-ezkit/MAINTAINERS
deleted file mode 100644
index 5ced3bb7d6e6..000000000000
--- a/board/bf561-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf561-ezkit/
-F: include/configs/bf561-ezkit.h
-F: configs/bf561-ezkit_defconfig
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
deleted file mode 100644
index 3d534d24861c..000000000000
--- a/board/bf561-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf561-ezkit.o
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
deleted file mode 100644
index 534c39ca89a5..000000000000
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: ADI BF561 EZ-Kit Lite board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
deleted file mode 100644
index 854d7dbb8632..000000000000
--- a/board/bf561-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/Kconfig b/board/bf609-ezkit/Kconfig
deleted file mode 100644
index 7992e1ec8681..000000000000
--- a/board/bf609-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF609_EZKIT
-
-config SYS_BOARD
- default "bf609-ezkit"
-
-config SYS_CONFIG_NAME
- default "bf609-ezkit"
-
-endif
diff --git a/board/bf609-ezkit/MAINTAINERS b/board/bf609-ezkit/MAINTAINERS
deleted file mode 100644
index acfc6c7a86cf..000000000000
--- a/board/bf609-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF609-EZKIT BOARD
-M: Sonic Zhang <sonic.adi@gmail.com>
-S: Maintained
-F: board/bf609-ezkit/
-F: include/configs/bf609-ezkit.h
-F: configs/bf609-ezkit_defconfig
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
deleted file mode 100644
index e4184ee2b617..000000000000
--- a/board/bf609-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := bf609-ezkit.o
-obj-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
deleted file mode 100644
index c993ca6d9106..000000000000
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <asm/sdh.h>
-#include <asm/portmux.h>
-#include "soft_switch.h"
-
-int checkboard(void)
-{
- printf("Board: ADI BF609 EZ-Kit board\n");
- printf(" Support: http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
- static const unsigned short pins[] = {
- P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
- P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
- };
- peripheral_request_list(pins, "smc0");
-
- return 0;
-}
-
-#ifdef CONFIG_ETH_DESIGNWARE
-int board_eth_init(bd_t *bis)
-{
- int ret = 0;
-
- if (CONFIG_DW_PORTS & 1) {
- static const unsigned short pins[] = P_RMII0;
- if (!peripheral_request_list(pins, "emac0"))
- ret += designware_initialize(EMAC0_MACCFG, 0);
- }
- if (CONFIG_DW_PORTS & 2) {
- static const unsigned short pins[] = P_RMII1;
- if (!peripheral_request_list(pins, "emac1"))
- ret += designware_initialize(EMAC1_MACCFG, 0);
- }
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
- return bfin_mmc_init(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
- printf("other init\n");
- return setup_board_switches();
-}
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
deleted file mode 100644
index 7c117ea997ed..000000000000
--- a/board/bf609-ezkit/soft_switch.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "soft_switch.h"
-
-struct switch_config {
- uchar dir0; /* IODIRA */
- uchar dir1; /* IODIRB */
- uchar value0; /* OLATA */
- uchar value1; /* OLATB */
-};
-
-static struct switch_config switch_config_array[NUM_SWITCH] = {
- {
-/*
- U45 Port A U45 Port B
-
- 7--------------- RMII_CLK_EN | 7--------------- ~TEMP_THERM_EN
- | 6------------- ~CNT0ZM_EN | | 6------------- ~TEMP_IRQ_EN
- | | 5----------- ~CNT0DG_EN | | | 5----------- ~UART0CTS_146_EN
- | | | 4--------- ~CNT0UD_EN | | | | 4--------- ~UART0CTS_RST_EN
- | | | | 3------- ~CAN0RX_EN | | | | | 3------- ~UART0CTS_RTS_LPBK
- | | | | | 2----- ~CAN0_ERR_EN | | | | | | 2----- ~UART0CTS_EN
- | | | | | | 1--- ~CAN_STB | | | | | | | 1--- ~UART0RX_EN
- | | | | | | | 0- CAN_EN | | | | | | | | 0- ~UART0RTS_EN
- | | | | | | | | | | | | | | | | |
- O O O O O O O O | O O O O O O O O (I/O direction)
- 1 0 0 0 0 0 1 1 | 1 1 1 1 1 0 0 0 (value being set)
-*/
- .dir0 = 0x0, /* all output */
- .dir1 = 0x0, /* all output */
- .value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
- .value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
- | UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
- },
- {
-/*
- U46 Port A U46 Port B
-
- 7--------------- ~LED4_GPIO_EN | 7--------------- EMPTY
- | 6------------- ~LED3_GPIO_EN | | 6------------- ~SPI0D3_EN
- | | 5----------- ~LED2_GPIO_EN | | | 5----------- ~SPI0D2_EN
- | | | 4--------- ~LED1_GPIO_EN | | | | 4--------- ~SPIFLASH_CS_EN
- | | | | 3------- SMC0_LP0_EN | | | | | 3------- ~SD_WP_EN
- | | | | | 2----- EMPTY | | | | | | 2----- ~SD_CD_EN
- | | | | | | 1--- SMC0_EPPI2 | | | | | | | 1--- ~PUSHBUTTON2_EN
- _LP1_SWITCH
- | | | | | | | 0- OVERRIDE_SMC0 | | | | | | | | 0- ~PUSHBUTTON1_EN
- _LP0_BOOT
- | | | | | | | | | | | | | | | | |
- O O O O O O O O | O O O O O O O O (I/O direction)
- 0 0 0 0 0 X 0 1 | X 0 0 0 0 0 0 0 (value being set)
-*/
- .dir0 = 0x0, /* all output */
- .dir1 = 0x0, /* all output */
-#ifdef CONFIG_BFIN_LINKPORT
- .value0 = OVERRIDE_SMC0_LP0_BOOT,
-#else
- .value0 = SMC0_EPPI2_LP1_SWITCH,
-#endif
- .value1 = 0x0,
- },
- {
-/*
- U47 Port A U47 Port B
-
- 7--------------- ~PD2_SPI0MISO | 7--------------- EMPTY
- _EI3_EN
- | 6------------- ~PD1_SPI0D3 | | 6------------- EMPTY
- _EPPI1D17
- _SPI0SEL2
- _EI3_EN
- | | 5----------- ~PD0_SPI0D2 | | | 5----------- EMPTY
- _EPPI1D16
- _SPI0SEL3
- _EI3_EN
- | | | 4--------- ~WAKE_PUSH | | | | 4--------- EMPTY
- BUTTON_EN
- | | | | 3------- ~ETHERNET_EN | | | | | 3------- EMPTY
- | | | | | 2----- PHYAD0 | | | | | | 2----- EMPTY
- | | | | | | 1--- PHY_PWR | | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
- _DWN_INT
- | | | | | | | 0- ~PHYINT_EN | | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
- | | | | | | | | | | | | | | | | |
- O O O O O I I O | O O O O O O O O (I/O direction)
- 1 1 1 0 0 0 0 0 | X X X X X X 1 1 (value being set)
-*/
- .dir0 = 0x6, /* bits 1 and 2 input, all others output */
- .dir1 = 0x0, /* all output */
- .value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
- .value1 = 0,
- },
-};
-
-static int setup_soft_switch(int addr, struct switch_config *config)
-{
- int ret = 0;
-
- ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
- if (ret)
- return ret;
- ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
- if (ret)
- return ret;
-
- ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
- if (ret)
- return ret;
- return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
-}
-
-int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
-{
- int ret, data_reg, dir_reg;
- uchar tmp;
-
- if (port == IO_PORT_A) {
- data_reg = OLATA;
- dir_reg = IODIRA;
- } else {
- data_reg = OLATB;
- dir_reg = IODIRB;
- }
-
- if (dir == IO_PORT_INPUT) {
- ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
- if (ret)
- return ret;
- tmp |= bit;
- return i2c_write(addr, dir_reg, 1, &tmp, 1);
- } else {
- ret = i2c_read(addr, data_reg, 1, &tmp, 1);
- if (ret)
- return ret;
- if (value)
- tmp |= bit;
- else
- tmp &= ~bit;
- ret = i2c_write(addr, data_reg, 1, &tmp, 1);
- if (ret)
- return ret;
- ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
- if (ret)
- return ret;
- tmp &= ~bit;
- return i2c_write(addr, dir_reg, 1, &tmp, 1);
- }
-}
-
-int setup_board_switches(void)
-{
- int ret;
- int i;
-
- for (i = 0; i < NUM_SWITCH; i++) {
- ret = setup_soft_switch(SWITCH_ADDR + i,
- &switch_config_array[i]);
- if (ret)
- return ret;
- }
- return 0;
-}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
deleted file mode 100644
index 75d64e279a22..000000000000
--- a/board/bf609-ezkit/soft_switch.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BOARD_SOFT_SWITCH_H__
-#define __BOARD_SOFT_SWITCH_H__
-
-#include <asm/soft_switch.h>
-
-/* switch 0 port A */
-#define CAN_EN 0x1
-#define CAN_STB 0x2
-#define CAN0_ERR_EN 0x4
-#define CAN0RX_EN 0x8
-#define CNT0UD_EN 0x10
-#define CNT0DG_EN 0x20
-#define CNT0ZM_EN 0x40
-#define RMII_CLK_EN 0x80
-
-/* switch 0 port B */
-#define UART0RTS_EN 0x1
-#define UART0RX_EN 0x2
-#define UART0CTS_EN 0x4
-#define UART0CTS_RTS_LPBK 0x8
-#define UART0CTS_RST_EN 0x10
-#define UART0CTS_146_EN 0x20
-#define TEMP_IRQ_EN 0x40
-#define TEMP_THERM_EN 0x80
-
-/* switch 1 port A */
-#define OVERRIDE_SMC0_LP0_BOOT 0x1
-#define SMC0_EPPI2_LP1_SWITCH 0x2
-#define SMC0_LP0_EN 0x8
-#define LED1_GPIO_EN 0x10
-#define LED2_GPIO_EN 0x20
-#define LED3_GPIO_EN 0x40
-#define LED4_GPIO_EN 0x80
-
-/* switch 1 port B */
-#define PUSHBUTTON1_EN 0x1
-#define PUSHBUTTON2_EN 0x2
-#define SD_CD_EN 0x4
-#define SD_WP_EN 0x8
-#define SPIFLASH_CS_EN 0x10
-#define SPI0D2_EN 0x20
-#define SPI0D3_EN 0x40
-
-/* switch 2 port A */
-#define PHYINT_EN 0x1
-#define PHY_PWR_DWN_INT 0x2
-#define PHYAD0 0x4
-#define ETHERNET_EN 0x8
-#define WAKE_PUSHBUTTON_EN 0x10
-#define PD0_SPI0D2_EN 0x20
-#define PD1_SPI0D3_EN 0x40
-#define PD2_SPI0MISO_EN 0x80
-
-/* switch 2 port B */
-#define PD3_SPI0MOSI_EN 0x1
-#define PD4_SPI0CK_EN 0x2
-
-#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
-#define SWITCH_ADDR 0x21
-#else
-#define SWITCH_ADDR 0x20
-#endif
-
-#define NUM_SWITCH 3
-#define IODIRA 0x0
-#define IODIRB 0x1
-#define OLATA 0x14
-#define OLATB 0x15
-
-int setup_board_switches(void);
-
-#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/blackstamp/Kconfig b/board/blackstamp/Kconfig
deleted file mode 100644
index 7ce086a78fa4..000000000000
--- a/board/blackstamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKSTAMP
-
-config SYS_BOARD
- default "blackstamp"
-
-config SYS_CONFIG_NAME
- default "blackstamp"
-
-endif
diff --git a/board/blackstamp/MAINTAINERS b/board/blackstamp/MAINTAINERS
deleted file mode 100644
index a0d72c6e2015..000000000000
--- a/board/blackstamp/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKSTAMP BOARD
-M: Wojtek Skulski <skulski@pas.rochester.edu>
-M: Wojtek Skulski <info@skutek.com>
-M: Benjamin Matthews <mben12@gmail.com>
-S: Maintained
-F: board/blackstamp/
-F: include/configs/blackstamp.h
-F: configs/blackstamp_defconfig
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
deleted file mode 100644
index 2ae79da0715b..000000000000
--- a/board/blackstamp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := blackstamp.o
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
deleted file mode 100644
index d233b8a7fc0b..000000000000
--- a/board/blackstamp/blackstamp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * U-Boot - blackstamp.c BlackStamp board specific routines
- * Most code stolen from boards/bf533-stamp/bf533-stamp.c
- * Edited to the BlackStamp by Ben Matthews for UR LLE
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: BlackStamp\n");
- printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
- return 0;
-}
-
-#ifdef SHARED_RESOURCES
-void swap_to(int device_id)
-{
- gpio_request(GPIO_PF0, "eth_flash_swap");
- gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
- SSYNC();
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/blackvme/Kconfig b/board/blackvme/Kconfig
deleted file mode 100644
index 5e73f84effba..000000000000
--- a/board/blackvme/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKVME
-
-config SYS_BOARD
- default "blackvme"
-
-config SYS_CONFIG_NAME
- default "blackvme"
-
-endif
diff --git a/board/blackvme/MAINTAINERS b/board/blackvme/MAINTAINERS
deleted file mode 100644
index 3f8b32c8844f..000000000000
--- a/board/blackvme/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKVME BOARD
-M: Wojtek Skulski <skulski@pas.rochester.edu>
-M: Wojtek Skulski <info@skutek.com>
-M: Benjamin Matthews <mben12@gmail.com>
-S: Maintained
-F: board/blackvme/
-F: include/configs/blackvme.h
-F: configs/blackvme_defconfig
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
deleted file mode 100644
index 9a617757ea92..000000000000
--- a/board/blackvme/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := blackvme.o
diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c
deleted file mode 100644
index d8932ed91025..000000000000
--- a/board/blackvme/blackvme.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* U-Boot - blackvme.c board specific routines
- * (c) Wojtek Skulski 2010 info at skutek.com
- * Board info: http://www.skutek.com
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- printf("Board: BlackVME\n");
- printf("Support: http://www.skutek.com/\n");
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_AX88180
-/*
- * The ax88180 driver had to be patched to work around a bug
- * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
- */
-int board_eth_init(bd_t *bis)
-{
- return ax88180_initialize(bis);
-}
-#endif /* CONFIG_DRIVER_AX88180 */
diff --git a/board/br4/Kconfig b/board/br4/Kconfig
deleted file mode 100644
index a10a06053af5..000000000000
--- a/board/br4/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BR4
-
-config SYS_BOARD
- default "br4"
-
-config SYS_CONFIG_NAME
- default "br4"
-
-endif
diff --git a/board/br4/MAINTAINERS b/board/br4/MAINTAINERS
deleted file mode 100644
index 4085da545234..000000000000
--- a/board/br4/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BR4 BOARD
-M: Dimitar Penev <dpn@switchfin.org>
-S: Maintained
-F: board/br4/
-F: include/configs/br4.h
-F: configs/br4_defconfig
diff --git a/board/br4/Makefile b/board/br4/Makefile
deleted file mode 100644
index c6c03aba09fa..000000000000
--- a/board/br4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := br4.o
diff --git a/board/br4/br4.c b/board/br4/br4.c
deleted file mode 100644
index 6f3f170a3250..000000000000
--- a/board/br4/br4.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- printf("Board: Switchvoice BR4 Appliance\n");
- printf(" Support: http://www.switchvoice.com/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/cm-bf527/Kconfig b/board/cm-bf527/Kconfig
deleted file mode 100644
index 8d1417912432..000000000000
--- a/board/cm-bf527/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF527
-
-config SYS_BOARD
- default "cm-bf527"
-
-config SYS_CONFIG_NAME
- default "cm-bf527"
-
-endif
diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS
deleted file mode 100644
index fefcfcfb7db5..000000000000
--- a/board/cm-bf527/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF527 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf527/
-F: include/configs/cm-bf527.h
-F: configs/cm-bf527_defconfig
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
deleted file mode 100644
index 1d662c66844b..000000000000
--- a/board/cm-bf527/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf527.o gpio_cfi_flash.o
diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c
deleted file mode 100644
index 0c2138b082c5..000000000000
--- a/board/cm-bf527/cm-bf527.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF527 board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- uint32_t ret;
- uint64_t otp_mac;
-
- ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
- if (!(ret & OTP_MASTER_ERROR)) {
- uchar *otp_mac_p = (uchar *)&otp_mac;
-
- for (ret = 0; ret < 6; ++ret)
- mac_addr[ret] = otp_mac_p[5 - ret];
-
- if (is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
- gpio_cfi_flash_init();
-
- return 0;
-}
diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c
deleted file mode 100644
index 6e62fff230d4..000000000000
--- a/board/cm-bf527/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH9
-#define GPIO_PIN_2 GPIO_PG11
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf533/Kconfig b/board/cm-bf533/Kconfig
deleted file mode 100644
index cedd7529d5ea..000000000000
--- a/board/cm-bf533/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF533
-
-config SYS_BOARD
- default "cm-bf533"
-
-config SYS_CONFIG_NAME
- default "cm-bf533"
-
-endif
diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS
deleted file mode 100644
index 0bf51fb1eaa1..000000000000
--- a/board/cm-bf533/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF533 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf533/
-F: include/configs/cm-bf533.h
-F: configs/cm-bf533_defconfig
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
deleted file mode 100644
index 41e100da1bd8..000000000000
--- a/board/cm-bf533/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf533.o
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
deleted file mode 100644
index 02ef076735e7..000000000000
--- a/board/cm-bf533/cm-bf533.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF533 board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
- return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/cm-bf533/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/Kconfig b/board/cm-bf537e/Kconfig
deleted file mode 100644
index af2e548cb9f4..000000000000
--- a/board/cm-bf537e/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537E
-
-config SYS_BOARD
- default "cm-bf537e"
-
-config SYS_CONFIG_NAME
- default "cm-bf537e"
-
-endif
diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS
deleted file mode 100644
index 63d242893e3a..000000000000
--- a/board/cm-bf537e/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537E BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf537e/
-F: include/configs/cm-bf537e.h
-F: configs/cm-bf537e_defconfig
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
deleted file mode 100644
index 317098cf2ed4..000000000000
--- a/board/cm-bf537e/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf537e.o gpio_cfi_flash.o
diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
deleted file mode 100644
index 7e4cfc21165b..000000000000
--- a/board/cm-bf537e/cm-bf537e.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF537E board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
- /* return ok if at least 1 eth device works */
- return bfin_EMAC_initialize(bis) &
- smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
- gpio_cfi_flash_init();
-
- return 0;
-}
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/cm-bf537e/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c
deleted file mode 100644
index 1075cc41127d..000000000000
--- a/board/cm-bf537e/gpio_cfi_flash.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-/* Allow this driver to be shared among boards */
-#ifndef GPIO_PIN_1
-#define GPIO_PIN_1 GPIO_PF4
-#endif
-#define GPIO_MASK_1 (1 << 21)
-#ifndef GPIO_PIN_2
-#define GPIO_MASK_2 (0)
-#else
-#define GPIO_MASK_2 (1 << 22)
-#endif
-#ifndef GPIO_PIN_3
-#define GPIO_MASK_3 (0)
-#else
-#define GPIO_MASK_3 (1 << 23)
-#endif
-#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
- unsigned long addr = (unsigned long)vaddr;
-
- gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_PIN_2
- gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
-#ifdef GPIO_PIN_3
- gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
-#endif
-
- SSYNC();
- udelay(1);
-
- return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
- __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
- return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
- gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
- gpio_direction_output(GPIO_PIN_1, 0);
-#ifdef GPIO_PIN_2
- gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
- gpio_direction_output(GPIO_PIN_2, 0);
-#endif
-#ifdef GPIO_PIN_3
- gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
- gpio_direction_output(GPIO_PIN_3, 0);
-#endif
-}
diff --git a/board/cm-bf537e/gpio_cfi_flash.h b/board/cm-bf537e/gpio_cfi_flash.h
deleted file mode 100644
index 5211e972ad2d..000000000000
--- a/board/cm-bf537e/gpio_cfi_flash.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
diff --git a/board/cm-bf537u/Kconfig b/board/cm-bf537u/Kconfig
deleted file mode 100644
index baf9e8cf611e..000000000000
--- a/board/cm-bf537u/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537U
-
-config SYS_BOARD
- default "cm-bf537u"
-
-config SYS_CONFIG_NAME
- default "cm-bf537u"
-
-endif
diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS
deleted file mode 100644
index a89cfcae747a..000000000000
--- a/board/cm-bf537u/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537U BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf537u/
-F: include/configs/cm-bf537u.h
-F: configs/cm-bf537u_defconfig
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
deleted file mode 100644
index 835d5b73f07f..000000000000
--- a/board/cm-bf537u/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf537u.o gpio_cfi_flash.o
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
deleted file mode 100644
index aad72a978323..000000000000
--- a/board/cm-bf537u/cm-bf537u.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF537U board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
- /* return ok if at least 1 eth device works */
- return bfin_EMAC_initialize(bis) &
- smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
- gpio_cfi_flash_init();
-
- return 0;
-}
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/cm-bf537u/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
deleted file mode 100644
index ef5ea8b793db..000000000000
--- a/board/cm-bf537u/gpio_cfi_flash.c
+++ /dev/null
@@ -1,2 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH0
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf548/Kconfig b/board/cm-bf548/Kconfig
deleted file mode 100644
index b96cb5f153c6..000000000000
--- a/board/cm-bf548/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF548
-
-config SYS_BOARD
- default "cm-bf548"
-
-config SYS_CONFIG_NAME
- default "cm-bf548"
-
-endif
diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS
deleted file mode 100644
index b7f5779cef17..000000000000
--- a/board/cm-bf548/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF548 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf548/
-F: include/configs/cm-bf548.h
-F: configs/cm-bf548_defconfig
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
deleted file mode 100644
index 1e11b8cdb129..000000000000
--- a/board/cm-bf548/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf548.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
deleted file mode 100644
index d9d018bfbcd1..000000000000
--- a/board/cm-bf548/cm-bf548.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF548 board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* Set async addr lines as peripheral */
- const unsigned short pins[] = {
- P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
- P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
- P_A21, P_A22, P_A23, P_A24, 0
- };
- return peripheral_request_list(pins, "async");
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
deleted file mode 100644
index beb983464955..000000000000
--- a/board/cm-bf548/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART := --dma 1
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
deleted file mode 100644
index b8cc87386368..000000000000
--- a/board/cm-bf548/video.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16 2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES 480 /*Horizontal Resolution */
-#define LCD_Y_RES 272 /* Vertical Resolution */
-
-#define LCD_BPP 24 /* Bit Per Pixel */
-#define LCD_PIXEL_SIZE (LCD_BPP / 8)
-#define DMA_BUS_SIZE 32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* -- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period TH - 525 - Clock
- * Pulse width THp - 41 - Clock
- * Horizontal period THd - 480 - Clock
- * Back porch THb - 2 - Clock
- * Front porch THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period TV - 286 - Line
- * Pulse width TVp - 10 - Line
- * Vertical period TVd - 272 - Line
- * Back porch TVb - 2 - Line
- * Front porch TVf - 2 - Line
- */
-
-#define LCD_CLK (8*1000*1000) /* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE 525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME 286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL 41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY 43
-
-/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB (EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY 12
-
-#define EPPI_CLIP 0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL (0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
- u32 sclk = get_sclk();
-
- /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
- return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
- u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
- bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
- bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
- bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
- bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
- bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
- bfin_write_EPPI0_FRAME(EPPI_FRAME);
- bfin_write_EPPI0_LINE(EPPI_LINE);
-
- bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
- bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
- bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
- bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
- bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
- bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
- RGB_FMT_EN);
-#else
- bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
- ~RGB_FMT_EN);
-#endif
-
-}
-
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
- bfin_write_DMA12_START_ADDR(dst);
-
- /* X count */
- bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
- bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
- /* Y count */
- bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
- bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
- /* DMA Config */
- bfin_write_DMA12_CONFIG(
- WDSIZE_32 | /* 32 bit DMA */
- DMA2D | /* 2D DMA */
- FLOW_AUTO /* autobuffer mode */
- );
-}
-
-void Init_Ports(void)
-{
- const unsigned short pins[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
- P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
- P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
- P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
- P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
- P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
- };
- peripheral_request_list(pins, "lcd");
-
- gpio_request(GPIO_PE3, "lcd-disp");
- gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
- bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
- bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
- bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
- Init_Ports();
- Init_DMA(dst);
- EnableDMA();
- Init_PPI();
- EnablePPI();
-
- return 0;
-}
-
-void video_stop(void)
-{
- DisablePPI();
- DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
- if (dcache_status())
- blackfin_dcache_flush_range(logo->data,
- logo->data + logo->size);
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- /* Setup destination start address */
- bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
- + (y * LCD_X_RES * LCD_PIXEL_SIZE));
- /* Setup destination xcount */
- bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup destination xmodify */
- bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
- /* Setup destination ycount */
- bfin_write_MDMA_D0_Y_COUNT(logo->height);
- /* Setup destination ymodify */
- bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
- DMA_SIZE16);
-
- /* Setup Source start address */
- bfin_write_MDMA_S0_START_ADDR(logo->data);
- /* Setup Source xcount */
- bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
- /* Setup Source xmodify */
- bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
- /* Setup Source ycount */
- bfin_write_MDMA_S0_Y_COUNT(logo->height);
- /* Setup Source ymodify */
- bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
- /* Enable source DMA */
- bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
- SSYNC();
- bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
-
- while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
-
- bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
- | DMA_ERR);
- bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
- | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
- int error, devices = 1;
- struct stdio_dev videodev;
-
- u8 *dst;
- u32 fbmem_size =
- LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
- dst = malloc(fbmem_size);
-
- if (dst == NULL) {
- printf("Failed to alloc FB memory\n");
- return -1;
- }
-
-#ifdef EASYLOGO_ENABLE_GZIP
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- unsigned long src_len = EASYLOGO_ENABLE_GZIP;
- error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
- bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
- unsigned char *data = EASYLOGO_DECOMP_BUFFER;
- SizeT lzma_len = bfin_logo.size;
- error = lzmaBuffToBuffDecompress(data, &lzma_len,
- bfin_logo.data, EASYLOGO_ENABLE_LZMA);
- bfin_logo.data = data;
-#else
- error = 0;
-#endif
-
- if (error) {
- puts("Failed to decompress logo\n");
- free(dst);
- return -1;
- }
-
- memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
- fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
- dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
- (LCD_X_RES - bfin_logo.width) / 2,
- (LCD_Y_RES - bfin_logo.height) / 2);
-
- video_init(dst); /* Video initialization */
-
- memset(&videodev, 0, sizeof(videodev));
-
- strcpy(videodev.name, "video");
-
- error = stdio_register(&videodev);
-
- return (error == 0) ? devices : error;
-}
diff --git a/board/cm-bf561/Kconfig b/board/cm-bf561/Kconfig
deleted file mode 100644
index 8b302a5c8f77..000000000000
--- a/board/cm-bf561/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF561
-
-config SYS_BOARD
- default "cm-bf561"
-
-config SYS_CONFIG_NAME
- default "cm-bf561"
-
-endif
diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS
deleted file mode 100644
index 9c86c8d39acf..000000000000
--- a/board/cm-bf561/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF561 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/cm-bf561/
-F: include/configs/cm-bf561.h
-F: configs/cm-bf561_defconfig
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
deleted file mode 100644
index e0f0c34095ea..000000000000
--- a/board/cm-bf561/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm-bf561.o
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
deleted file mode 100644
index 99b7eb261210..000000000000
--- a/board/cm-bf561/cm-bf561.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix CM-BF561 core module\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
deleted file mode 100644
index 854d7dbb8632..000000000000
--- a/board/cm-bf561/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/dnp5370/Kconfig b/board/dnp5370/Kconfig
deleted file mode 100644
index 797081d5f276..000000000000
--- a/board/dnp5370/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_DNP5370
-
-config SYS_BOARD
- default "dnp5370"
-
-config SYS_CONFIG_NAME
- default "dnp5370"
-
-endif
diff --git a/board/dnp5370/MAINTAINERS b/board/dnp5370/MAINTAINERS
deleted file mode 100644
index 8333891a40b2..000000000000
--- a/board/dnp5370/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DNP5370 BOARD
-M: M.Hasewinkel (MHA) <info@ssv-embedded.de>
-S: Maintained
-F: board/dnp5370/
-F: include/configs/dnp5370.h
-F: configs/dnp5370_defconfig
diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile
deleted file mode 100644
index c0271da01b7f..000000000000
--- a/board/dnp5370/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dnp5370.o
diff --git a/board/dnp5370/README b/board/dnp5370/README
deleted file mode 100644
index 0172698e96dc..000000000000
--- a/board/dnp5370/README
+++ /dev/null
@@ -1,67 +0,0 @@
-This document describes the board support for
-Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module.
-The distributor is SSV (http://www.ssv-embedded.de),
-
-The module used to develop the support files contains:
-
-* Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM)
-
-* RAM: 32 MB SDRAM
- Hynix HY57V561620FTP-H 810EA
- Connected to Blackfin via "Expansion Bus"
- Address range 0x0000.0000 - 0x1fff.ffff
-
-* NOR flash: 32 MBit (4 MByte)
- Exel Semiconductor ES29LVS320EB
- Connected to Blackfin via "Expansion Bus",
- Chip Selects 0, 1 and 2, each is connected
- to a 1 MB memory bank at Blackfin, therefore
- only 3 MB accessible.
- Address range 0x2000.0000 - 0x202f.ffff
- CFI compatible
-
- Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com).
-
-* NAND flash: 64 MBit (8 MByte)
- Atmel 45DB642D-CNU
- Connected to Blackfin via SPI
- CFI compatible
-
-* Davicom DM9161EP Ethernet PHY
-
-* A SD card reader, connected via SPI
-
-* Hardware watchdog MAX823 or TPS3823
-
-(other devices not listed here)
-
-To run it, the module must be inserted in a 64 pin DIL socket
-on another board, e.g. DNP/EVA13 (together: SSV SK28).
-
-The Blackfin is booted from NOR flash. The NOR flash data begins
-with the U-Boot code and is then followed by the Linux code.
-Finally, the MAC is stored in the last sector.
-You may need to adjust these settings to your needs.
-The memory map used to develop the board support is:
-
-Memory map:
-0x00000000 .. 0x01ffffff SDRAM
-0x20000000 .. 0x202fffff NOR flash
-
-RAM use:
-0x01f9bffc .. 0x01fbbffb U-Boot stack
-0x01f9c000 .. 0x01f9ffff U-Boot global data
-0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM
-0x01fc0000 .. 0x01ffffff U-Boot execution RAM
-
-NOR flash use:
-0x20000000 .. 0x0002ffff U-Boot
-0x20004000 .. 0x20005fff U-Boot environment
-0x20030000 .. 0x202effff Linux kernel image
-0x202f0000 .. 0x202fffff MAC address sector
-
-NOR flash is 0x00300000 (3145728) bytes large (3 MB).
-Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB)
-Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB)
-
-The module is hardwired to BYPASS boot mode.
diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c
deleted file mode 100644
index 719203db0cdc..000000000000
--- a/board/dnp5370/dnp5370.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * (C) Copyright 2010 3ality Digital Systems
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-static void disable_external_watchdog(void)
-{
-#ifdef CONFIG_DNP5370_EXT_WD_DISABLE
- /* disable external HW watchdog with PH13 = WD1 = 1 */
- gpio_request(GPIO_PH13, "ext_wd");
- gpio_direction_output(GPIO_PH13, 1);
-#endif
-}
-
-int checkboard(void)
-{
- printf("Board: SSV DilNet DNP5370\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we cram the MAC in the last flash sector */
- uchar *board_mac_addr = (uchar *)0x202F0000;
- if (is_valid_ethaddr(board_mac_addr)) {
- memcpy(mac_addr, board_mac_addr, 6);
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
- disable_external_watchdog();
-
-#ifdef CONFIG_BFIN_MAC
- uchar enetaddr[6];
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
- board_init_enetaddr(enetaddr);
-#endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
- /* we use the last sector for the MAC address / POST LDR */
- extern flash_info_t flash_info[];
- flash_protect(FLAG_PROTECT_SET, 0x202F0000, 0x202FFFFF, &flash_info[0]);
-#endif
-
- return 0;
-}
diff --git a/board/ip04/Kconfig b/board/ip04/Kconfig
deleted file mode 100644
index 670bf8992258..000000000000
--- a/board/ip04/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IP04
-
-config SYS_BOARD
- default "ip04"
-
-config SYS_CONFIG_NAME
- default "ip04"
-
-endif
diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS
deleted file mode 100644
index c37b0110f22c..000000000000
--- a/board/ip04/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IP04 BOARD
-#M: Brent Kandetzki <brentk@teleco.com>
-S: Orphan (since 2014-06)
-F: board/ip04/
-F: include/configs/ip04.h
-F: configs/ip04_defconfig
diff --git a/board/ip04/Makefile b/board/ip04/Makefile
deleted file mode 100644
index 44fa684729fb..000000000000
--- a/board/ip04/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2010 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ip04.o
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
deleted file mode 100644
index ab0fbecab93b..000000000000
--- a/board/ip04/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c
deleted file mode 100644
index c7bc33434e22..000000000000
--- a/board/ip04/ip04.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2007 David Rowe,
- * (c) 2006 Ivan Danov
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- printf("Board: IP04 IP-PBX\n");
- printf(" http://www.rowetel.com/ucasterisk/ip04.html\n");
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
diff --git a/board/pr1/Kconfig b/board/pr1/Kconfig
deleted file mode 100644
index fb04648716f8..000000000000
--- a/board/pr1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PR1
-
-config SYS_BOARD
- default "pr1"
-
-config SYS_CONFIG_NAME
- default "pr1"
-
-endif
diff --git a/board/pr1/MAINTAINERS b/board/pr1/MAINTAINERS
deleted file mode 100644
index 23fdbc7a7601..000000000000
--- a/board/pr1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PR1 BOARD
-M: Dimitar Penev <dpn@switchfin.org>
-S: Maintained
-F: board/pr1/
-F: include/configs/pr1.h
-F: configs/pr1_defconfig
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
deleted file mode 100644
index 8caa3601f433..000000000000
--- a/board/pr1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pr1.o
diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c
deleted file mode 100644
index 3fffabdefb27..000000000000
--- a/board/pr1/pr1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- printf("Board: Switchvoice PR1 Appliance\n");
- printf(" Support: http://www.switchvoice.com/\n");
- return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/tcm-bf518/Kconfig b/board/tcm-bf518/Kconfig
deleted file mode 100644
index 558c2fe495fd..000000000000
--- a/board/tcm-bf518/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF518
-
-config SYS_BOARD
- default "tcm-bf518"
-
-config SYS_CONFIG_NAME
- default "tcm-bf518"
-
-endif
diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS
deleted file mode 100644
index 169012269f7d..000000000000
--- a/board/tcm-bf518/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF518 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/tcm-bf518/
-F: include/configs/tcm-bf518.h
-F: configs/tcm-bf518_defconfig
diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile
deleted file mode 100644
index 1ce8f64a08f6..000000000000
--- a/board/tcm-bf518/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tcm-bf518.o
diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c
deleted file mode 100644
index 7923eae5d51a..000000000000
--- a/board/tcm-bf518/tcm-bf518.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix TCM-BF518 board\n");
- printf(" Support: http://www.bluetechnix.com/\n");
- printf(" http://blackfin.uclinux.org/\n");
- return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-int board_eth_init(bd_t *bis)
-{
- return bfin_EMAC_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
- return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/tcm-bf537/Kconfig b/board/tcm-bf537/Kconfig
deleted file mode 100644
index e0127c641e91..000000000000
--- a/board/tcm-bf537/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF537
-
-config SYS_BOARD
- default "tcm-bf537"
-
-config SYS_CONFIG_NAME
- default "tcm-bf537"
-
-endif
diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS
deleted file mode 100644
index 1cd48451df17..000000000000
--- a/board/tcm-bf537/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF537 BOARD
-#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S: Orphan (since 2014-03)
-F: board/tcm-bf537/
-F: include/configs/tcm-bf537.h
-F: configs/tcm-bf537_defconfig
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
deleted file mode 100644
index 0fe25e80dc43..000000000000
--- a/board/tcm-bf537/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tcm-bf537.o gpio_cfi_flash.o
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
deleted file mode 100644
index 7f9138b09bee..000000000000
--- a/board/tcm-bf537/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c
deleted file mode 100644
index c4fef9f5e70e..000000000000
--- a/board/tcm-bf537/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PF4
-#define GPIO_PIN_2 GPIO_PF5
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
deleted file mode 100644
index 19df51adabe6..000000000000
--- a/board/tcm-bf537/tcm-bf537.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- printf("Board: Bluetechnix TCM-BF537 board\n");
- printf(" Support: http://www.bluetechnix.at/\n");
- return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
- /* return ok if at least 1 eth device works */
- return bfin_EMAC_initialize(bis) &
- smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
- gpio_cfi_flash_init();
-
- return 0;
-}
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index ae3027a297bf..20a92320bde1 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -338,24 +338,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
-#elif defined(CONFIG_BLACKFIN)
-
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- bd_t *bd = gd->bd;
-
- printf("U-Boot = %s\n", bd->bi_r_version);
- printf("CPU = %s\n", bd->bi_cpu);
- printf("Board = %s\n", bd->bi_board_name);
- print_mhz("VCO", bd->bi_vco);
- print_mhz("CCLK", bd->bi_cclk);
- print_mhz("SCLK", bd->bi_sclk);
-
- print_std_bdinfo(bd);
-
- return 0;
-}
-
#elif defined(CONFIG_MIPS)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/cmd/mem.c b/cmd/mem.c
index 83d34faf2d88..b6e200b97c09 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -112,27 +112,6 @@ static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
} while (nbytes > 0);
#else
-
-# if defined(CONFIG_BLACKFIN)
- /* See if we're trying to display L1 inst */
- if (addr_bfin_on_chip_mem(addr)) {
- char linebuf[DISP_LINE_LEN];
- ulong linebytes, nbytes = length * size;
- do {
- linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
- memcpy(linebuf, (void *)addr, linebytes);
- print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size);
-
- nbytes -= linebytes;
- addr += linebytes;
- if (ctrlc()) {
- rc = 1;
- break;
- }
- } while (nbytes > 0);
- } else
-# endif
-
{
ulong bytes = size * length;
const void *buf = map_sysmem(addr, bytes);
@@ -314,13 +293,6 @@ static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
#endif
-#ifdef CONFIG_BLACKFIN
- if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) {
- puts ("Comparison with L1 instruction memory not supported.\n\r");
- return 0;
- }
-#endif
-
bytes = size * count;
base = buf1 = map_sysmem(addr1, bytes);
buf2 = map_sysmem(addr2, bytes);
@@ -455,14 +427,6 @@ static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
#endif
-#ifdef CONFIG_BLACKFIN
- /* See if we're copying to/from L1 inst */
- if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) {
- memcpy((void *)dest, (void *)addr, count * size);
- return 0;
- }
-#endif
-
memcpy((void *)dest, (void *)addr, count * size);
return 0;
@@ -1115,13 +1079,6 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
}
#endif
-#ifdef CONFIG_BLACKFIN
- if (addr_bfin_on_chip_mem(addr)) {
- puts ("Can't modify L1 instruction in place. Use cp instead.\n\r");
- return 0;
- }
-#endif
-
/* Print the address, followed by value. Then accept input for
* the next value. A non-converted value exits.
*/
diff --git a/cmd/reginfo.c b/cmd/reginfo.c
index 5f19e7911b30..a3696d1b0077 100644
--- a/cmd/reginfo.c
+++ b/cmd/reginfo.c
@@ -172,64 +172,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
#elif defined(CONFIG_MPC85xx)
mpc85xx_reginfo();
-
-#elif defined(CONFIG_BLACKFIN)
- puts("\nSystem Configuration registers\n");
-#ifndef __ADSPBF60x__
- puts("\nPLL Registers\n");
- printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
- bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
- printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
- bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
- printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
-
- puts("\nEBIU AMC Registers\n");
- printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
- printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
- bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
-# ifdef EBIU_MODE
- printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
- bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
- printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
- bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
-# endif
-
-# ifdef EBIU_RSTCTL
- puts("\nEBIU DDR Registers\n");
- printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
- bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
- printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
- bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
- printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
- bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
- printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
- bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
-# else
- puts("\nEBIU SDC Registers\n");
- printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
- bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
- printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
- bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
-# endif
-#else
- puts("\nCGU Registers\n");
- printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n",
- bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
- printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n",
- bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
-
- puts("\nSMC DDR Registers\n");
- printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n",
- bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
- printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n",
- bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
- printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n",
- bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
- printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n",
- bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
- printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
#endif
-#endif /* CONFIG_BLACKFIN */
return 0;
}
diff --git a/common/Kconfig b/common/Kconfig
index 8f73c8f757bf..0beeb0eff0bb 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -379,7 +379,7 @@ config BOARD_LATE_INIT
config DISPLAY_CPUINFO
bool "Display information about the CPU during start up"
- default y if ARM || BLACKFIN || NIOS2 || X86 || XTENSA || MPC5xxx
+ default y if ARM || NIOS2 || X86 || XTENSA || MPC5xxx
help
Display information about the CPU that U-Boot is running on
when U-Boot starts up. The function print_cpuinfo() is called
diff --git a/common/board_f.c b/common/board_f.c
index ae6cd8528c60..1be0211d873f 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -116,8 +116,8 @@ __weak void blue_led_off(void) {}
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
static int init_func_watchdog_init(void)
{
-# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \
- defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
+# if defined(CONFIG_HW_WATCHDOG) && \
+ (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
defined(CONFIG_DESIGNWARE_WATCHDOG) || \
defined(CONFIG_IMX_WATCHDOG))
@@ -273,8 +273,7 @@ static int setup_mon_len(void)
gd->mon_len = (ulong)&__bss_end - (ulong)_start;
#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
gd->mon_len = (ulong)&_end - (ulong)_init;
-#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) || \
- defined(CONFIG_XTENSA)
+#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
@@ -487,7 +486,7 @@ static int reserve_lcd(void)
# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
- !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
+ !defined(CONFIG_M68K)
static int reserve_legacy_video(void)
{
/* reserve memory for video display (always full pages) */
@@ -881,8 +880,8 @@ static const init_fnc_t init_sequence_f[] = {
init_timebase,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
- defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
- defined(CONFIG_SH) || defined(CONFIG_SPARC)
+ defined(CONFIG_NDS32) || defined(CONFIG_SH) || \
+ defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_BOARD_POSTCLK_INIT)
@@ -970,7 +969,7 @@ static const init_fnc_t init_sequence_f[] = {
* - board info struct
*/
setup_dest_addr,
-#if defined(CONFIG_BLACKFIN) || defined(CONFIG_XTENSA)
+#if defined(CONFIG_XTENSA)
/* Blackfin u-boot monitor should be on top of the ram */
reserve_uboot,
#endif
@@ -997,12 +996,12 @@ static const init_fnc_t init_sequence_f[] = {
/* TODO: Why the dependency on CONFIG_8xx? */
# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
- !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
+ !defined(CONFIG_M68K)
reserve_legacy_video,
# endif
#endif /* CONFIG_DM_VIDEO */
reserve_trace,
-#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_XTENSA)
+#if !defined(CONFIG_XTENSA)
reserve_uboot,
#endif
#ifndef CONFIG_SPL_BUILD
diff --git a/configs/bct-brettl2_defconfig b/configs/bct-brettl2_defconfig
deleted file mode 100644
index 4aab03be5e27..000000000000
--- a/configs/bct-brettl2_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BCT_BRETTL2=y
-CONFIG_BOOTDELAY=1
-CONFIG_SILENT_CONSOLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/bf506f-ezkit_defconfig b/configs/bf506f-ezkit_defconfig
deleted file mode 100644
index 942d50cdb474..000000000000
--- a/configs/bf506f-ezkit_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF506F_EZKIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
diff --git a/configs/bf518f-ezbrd_defconfig b/configs/bf518f-ezbrd_defconfig
deleted file mode 100644
index ef83ac810e7d..000000000000
--- a/configs/bf518f-ezbrd_defconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF518F_EZBRD=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig
deleted file mode 100644
index 68d2f48b451b..000000000000
--- a/configs/bf525-ucr2_defconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF525_UCR2=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_EON=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
deleted file mode 100644
index 92cdb3c64433..000000000000
--- a/configs/bf526-ezbrd_defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF526_EZBRD=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/bf527-ad7160-eval_defconfig b/configs/bf527-ad7160-eval_defconfig
deleted file mode 100644
index 9f75eb02925e..000000000000
--- a/configs/bf527-ad7160-eval_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_AD7160_EVAL=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
deleted file mode 100644
index c2f8df9f4be5..000000000000
--- a/configs/bf527-ezkit-v2_defconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_EZKIT=y
-CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
deleted file mode 100644
index 9325984f748f..000000000000
--- a/configs/bf527-ezkit_defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_NET_TFTP_VARS is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/bf527-sdp_defconfig b/configs/bf527-sdp_defconfig
deleted file mode 100644
index 21377a857eb6..000000000000
--- a/configs/bf527-sdp_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF527_SDP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig
deleted file mode 100644
index e95d1343eaaf..000000000000
--- a/configs/bf533-ezkit_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF533_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig
deleted file mode 100644
index 35c69f092e2d..000000000000
--- a/configs/bf533-stamp_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF533_STAMP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
deleted file mode 100644
index fea8c3240f22..000000000000
--- a/configs/bf537-minotaur_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_MINOTAUR=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_PROMPT="minotaur> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-pnav_defconfig b/configs/bf537-pnav_defconfig
deleted file mode 100644
index 4c479fe7de48..000000000000
--- a/configs/bf537-pnav_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_PNAV=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
deleted file mode 100644
index dc88c44fa56d..000000000000
--- a/configs/bf537-srv1_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_SRV1=y
-CONFIG_BOOTDELAY=5
-CONFIG_SYS_PROMPT="srv1> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/bf537-stamp_defconfig b/configs/bf537-stamp_defconfig
deleted file mode 100644
index 0b38c523ab87..000000000000
--- a/configs/bf537-stamp_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF537_STAMP=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig
deleted file mode 100644
index 417728ee93dd..000000000000
--- a/configs/bf538f-ezkit_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF538F_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
deleted file mode 100644
index 05d5e261501c..000000000000
--- a/configs/bf548-ezkit_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF548_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig
deleted file mode 100644
index 744eb1c7675e..000000000000
--- a/configs/bf561-acvilon_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF561_ACVILON=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="Acvilon> "
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig
deleted file mode 100644
index 88169c30f0de..000000000000
--- a/configs/bf561-ezkit_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF561_EZKIT=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig
deleted file mode 100644
index 11c000044dba..000000000000
--- a/configs/bf609-ezkit_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BF609_EZKIT=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_NETDEVICES=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_LIB_RAND=y
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
deleted file mode 100644
index 7aa5a52f9b40..000000000000
--- a/configs/blackstamp_defconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BLACKSTAMP=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
deleted file mode 100644
index 7c3eb9dc6b1a..000000000000
--- a/configs/blackvme_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BLACKVME=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/br4_defconfig b/configs/br4_defconfig
deleted file mode 100644
index 90ce839b4313..000000000000
--- a/configs/br4_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_BR4=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="br4>"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf527_defconfig b/configs/cm-bf527_defconfig
deleted file mode 100644
index 080fc15dde7d..000000000000
--- a/configs/cm-bf527_defconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF527=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig
deleted file mode 100644
index abac6d9a63e1..000000000000
--- a/configs/cm-bf533_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF533=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf537e_defconfig b/configs/cm-bf537e_defconfig
deleted file mode 100644
index 86af79755f80..000000000000
--- a/configs/cm-bf537e_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF537E=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf537u_defconfig b/configs/cm-bf537u_defconfig
deleted file mode 100644
index e5e0a8d188f2..000000000000
--- a/configs/cm-bf537u_defconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF537U=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig
deleted file mode 100644
index 373895e78f72..000000000000
--- a/configs/cm-bf548_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF548=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-# CONFIG_REGEX is not set
-CONFIG_LIB_RAND=y
diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig
deleted file mode 100644
index 59f7c41db55c..000000000000
--- a/configs/cm-bf561_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_CM_BF561=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/dnp5370_defconfig b/configs/dnp5370_defconfig
deleted file mode 100644
index 2d0d779c9c52..000000000000
--- a/configs/dnp5370_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_DNP5370=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig
deleted file mode 100644
index 13a7b19c613d..000000000000
--- a/configs/ibf-dsp561_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_IBF_DSP561=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_LIB_RAND=y
diff --git a/configs/ip04_defconfig b/configs/ip04_defconfig
deleted file mode 100644
index 1e05d3e39c2f..000000000000
--- a/configs/ip04_defconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_IP04=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig
deleted file mode 100644
index a26ba618c02c..000000000000
--- a/configs/pr1_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_PR1=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_PROMPT="pr1>"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
-CONFIG_LIB_RAND=y
diff --git a/configs/tcm-bf518_defconfig b/configs/tcm-bf518_defconfig
deleted file mode 100644
index 448521005ae6..000000000000
--- a/configs/tcm-bf518_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_TCM_BF518=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/configs/tcm-bf537_defconfig b/configs/tcm-bf537_defconfig
deleted file mode 100644
index eaeeb53152b7..000000000000
--- a/configs/tcm-bf537_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-CONFIG_BLACKFIN=y
-CONFIG_TARGET_TCM_BF537=y
-CONFIG_BOOTDELAY=5
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 6f1c419c7a70..ed9659ad9797 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -4,7 +4,6 @@
obj-y += bootcount.o
obj-$(CONFIG_AT91SAM9XE) += bootcount_at91.o
-obj-$(CONFIG_BLACKFIN) += bootcount_blackfin.o
obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
diff --git a/drivers/bootcount/bootcount_blackfin.c b/drivers/bootcount/bootcount_blackfin.c
deleted file mode 100644
index 6cf6dd58b62d..000000000000
--- a/drivers/bootcount/bootcount_blackfin.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * functions for handling bootcount support
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-/* This version uses one 32bit storage and combines the magic/count */
-
-#include <common.h>
-
-/* We abuse the EVT0 MMR for bootcount storage by default */
-#ifndef CONFIG_SYS_BOOTCOUNT_ADDR
-# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0
-#endif
-
-#define MAGIC_MASK 0xffff0000
-#define COUNT_MASK 0x0000ffff
-
-void bootcount_store(ulong cnt)
-{
- ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK);
- bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic);
-}
-
-ulong bootcount_load(void)
-{
- ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR);
- if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK))
- return magic & COUNT_MASK;
- else
- return 0;
-}
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863c4..fe2815933441 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c
deleted file mode 100644
index 4ed0923e62ef..000000000000
--- a/drivers/i2c/pca9564_i2c.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * File: drivers/i2c/pca9564.c
- * Based on: drivers/i2c/s3c44b0_i2c.c
- * Author:
- *
- * Created: 2009-06-23
- * Description: PCA9564 i2c bridge driver
- *
- * Modified:
- * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *
- * Bugs:
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <pca9564.h>
-#include <asm/io.h>
-
-#define PCA_STA (CONFIG_PCA9564_BASE + 0)
-#define PCA_TO (CONFIG_PCA9564_BASE + 0)
-#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2))
-#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2))
-#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2))
-
-static unsigned char pca_read_reg(unsigned int reg)
-{
- return readb((void *)reg);
-}
-
-static void pca_write_reg(unsigned int reg, unsigned char value)
-{
- writeb(value, (void *)reg);
-}
-
-static int pca_wait_busy(void)
-{
- unsigned int timeout = 10000;
-
- while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout)
- udelay(1);
-
- if (timeout == 0)
- debug("I2C timeout!\n");
-
- debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON),
- pca_read_reg(PCA_STA));
-
- return timeout ? 0 : 1;
-}
-
-/*=====================================================================*/
-/* Public Functions */
-/*=====================================================================*/
-
-/*-----------------------------------------------------------------------
- * Initialization
- */
-void i2c_init(int speed, int slaveaddr)
-{
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed);
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-
-int i2c_probe(uchar chip)
-{
- unsigned char res;
-
- pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
- pca_wait_busy();
-
- pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1) | 1);
- res = pca_wait_busy();
-
- if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48))
- res = 1;
-
- pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
- return res;
-}
-
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int i;
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1));
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- if (alen > 0) {
- pca_write_reg(PCA_DAT, addr);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
- udelay(500);
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, (chip << 1) | 1);
- pca_wait_busy();
-
- for (i = 0; i < len; ++i) {
- if (i == len - 1)
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- else
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA);
-
- pca_wait_busy();
- buffer[i] = pca_read_reg(PCA_DAT);
-
- }
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO);
-
- return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int i;
-
- pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- pca_write_reg(PCA_DAT, chip << 1);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
-
- if (alen > 0) {
- pca_write_reg(PCA_DAT, addr);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- for (i = 0; i < len; ++i) {
- pca_write_reg(PCA_DAT, buffer[i]);
- pca_wait_busy();
- pca_write_reg(PCA_CON, PCA_CON_ENSIO);
- }
-
- pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO);
-
- return 0;
-}
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d9e5fc95f5c8..b025001337e1 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -241,7 +241,6 @@ static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
chip->write_buf(mtd, (uint8_t *)&word, 2);
}
-#if !defined(CONFIG_BLACKFIN)
static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
{
int i;
@@ -274,7 +273,6 @@ static void iowrite16_rep(void *addr, void *buf, int len)
for (i = 0; i < len; i++)
writew(p[i], addr);
}
-#endif
/**
* nand_write_buf - [DEFAULT] write buffer to chip
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 5197f36039f6..a31f6f6db0e3 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -253,8 +253,6 @@ struct smc91111_priv{
#ifdef CONFIG_ADNPESC1
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
-#elif CONFIG_BLACKFIN
-#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#elif CONFIG_ARM64
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
@@ -264,11 +262,6 @@ struct smc91111_priv{
#ifdef CONFIG_ADNPESC1
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
-#elif CONFIG_BLACKFIN
-#define SMC_outw(a, d, r) \
- ({ (*((volatile word*)((a)->iobase+((r)))) = d); \
- SSYNC(); \
- })
#elif CONFIG_ARM64
#define SMC_outw(a, d, r) \
(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8430668bf982..612e544235cf 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
-obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
diff --git a/drivers/serial/serial_bfin.c b/drivers/serial/serial_bfin.c
deleted file mode 100644
index 1d5be2a7a26e..000000000000
--- a/drivers/serial/serial_bfin.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * U-Boot - serial.c Blackfin Serial Driver
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* Anomaly notes:
- * 05000086 - we don't support autobaud
- * 05000099 - we only use DR bit, so losing others is not a problem
- * 05000100 - we don't use the UART_IIR register
- * 05000215 - we poll the uart (no dma/interrupts)
- * 05000225 - no workaround possible, but this shouldnt cause errors ...
- * 05000230 - we tweak the baud rate calculation slightly
- * 05000231 - we always use 1 stop bit
- * 05000309 - we always enable the uart before we modify it in anyway
- * 05000350 - we always enable the uart regardless of boot mode
- * 05000363 - we don't support break signals, so don't generate one
- */
-
-#include <common.h>
-#include <post.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_UART_CONSOLE
-
-#ifdef CONFIG_DEBUG_SERIAL
-static uart_lsr_t cached_lsr[256];
-static uart_lsr_t cached_rbr[256];
-static size_t cache_count;
-
-/* The LSR is read-to-clear on some parts, so we have to make sure status
- * bits aren't inadvertently lost when doing various tests. This also
- * works around anomaly 05000099 at the same time by keeping a cumulative
- * tally of all the status bits.
- */
-static uart_lsr_t uart_lsr_save;
-static uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- uart_lsr_t lsr = _lsr_read(pUART);
- uart_lsr_save |= (lsr & (OE|PE|FE|BI));
- return lsr | uart_lsr_save;
-}
-/* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(uint32_t uart_base)
-{
- uart_lsr_save = 0;
- _lsr_write(pUART, -1);
-}
-#else
-/* When debugging is disabled, we only care about the DR bit, so if other
- * bits get set/cleared, we don't really care since we don't read them
- * anyways (and thus anomaly 05000099 is irrelevant).
- */
-static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- return _lsr_read(pUART);
-}
-static void uart_lsr_clear(uint32_t uart_base)
-{
- _lsr_write(pUART, -1);
-}
-#endif
-
-static void uart_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- serial_putc('\r');
-
- WATCHDOG_RESET();
-
- /* wait for the hardware fifo to clear up */
- while (!(uart_lsr_read(uart_base) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-
- WATCHDOG_RESET();
-}
-
-static int uart_tstc(uint32_t uart_base)
-{
- WATCHDOG_RESET();
- return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
-}
-
-static int uart_getc(uint32_t uart_base)
-{
- uint16_t uart_rbr_val;
-
- /* wait for data ! */
- while (!uart_tstc(uart_base))
- continue;
-
- /* grab the new byte */
- uart_rbr_val = bfin_read(&pUART->rbr);
-
-#ifdef CONFIG_DEBUG_SERIAL
- /* grab & clear the LSR */
- uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
-
- cached_lsr[cache_count] = uart_lsr_val;
- cached_rbr[cache_count] = uart_rbr_val;
- cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- printf("\n[SERIAL ERROR]\n");
- do {
- --cache_count;
- printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
- cached_rbr[cache_count], cached_lsr[cache_count]);
- } while (cache_count > 0);
- return -1;
- }
-#endif
- uart_lsr_clear(uart_base);
-
- return uart_rbr_val;
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-# define LOOP(x) x
-#else
-# define LOOP(x)
-#endif
-
-#if BFIN_UART_HW_VER < 4
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u16 mcr;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- mcr = bfin_read(&pUART->mcr);
- if (state)
- mcr |= LOOP_ENA | MRTS;
- else
- mcr &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->mcr, mcr);
-}
-)
-
-#else
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u32 control;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- control = bfin_read(&pUART->control);
- if (state)
- control |= LOOP_ENA | MRTS;
- else
- control &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->control, control);
-}
-)
-
-#endif
-
-static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- serial_early_set_baud(uart_base, baud);
-#else
- uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
- - ANOMALY_05000230;
-
- /* Program the divisor to get the baud rate we want */
- serial_set_divisor(uart_base, divisor);
-#endif
-}
-
-static void uart_puts(uint32_t uart_base, const char *s)
-{
- while (*s)
- uart_putc(uart_base, *s++);
-}
-
-#define DECL_BFIN_UART(n) \
-static int uart##n##_init(void) \
-{ \
- const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
- peripheral_request_list(pins, "bfin-uart"); \
- uart_init(MMR_UART(n)); \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
- uart_lsr_clear(MMR_UART(n)); \
- return 0; \
-} \
-\
-static int uart##n##_uninit(void) \
-{ \
- return serial_early_uninit(MMR_UART(n)); \
-} \
-\
-static void uart##n##_setbrg(void) \
-{ \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
-} \
-\
-static int uart##n##_getc(void) \
-{ \
- return uart_getc(MMR_UART(n)); \
-} \
-\
-static int uart##n##_tstc(void) \
-{ \
- return uart_tstc(MMR_UART(n)); \
-} \
-\
-static void uart##n##_putc(const char c) \
-{ \
- uart_putc(MMR_UART(n), c); \
-} \
-\
-static void uart##n##_puts(const char *s) \
-{ \
- uart_puts(MMR_UART(n), s); \
-} \
-\
-LOOP( \
-static void uart##n##_loop(int state) \
-{ \
- uart_loop(MMR_UART(n), state); \
-} \
-) \
-\
-struct serial_device bfin_serial##n##_device = { \
- .name = "bfin_uart"#n, \
- .start = uart##n##_init, \
- .stop = uart##n##_uninit, \
- .setbrg = uart##n##_setbrg, \
- .getc = uart##n##_getc, \
- .tstc = uart##n##_tstc, \
- .putc = uart##n##_putc, \
- .puts = uart##n##_puts, \
- LOOP(.loop = uart##n##_loop) \
-};
-
-#ifdef UART0_RBR
-DECL_BFIN_UART(0)
-#endif
-#ifdef UART1_RBR
-DECL_BFIN_UART(1)
-#endif
-#ifdef UART2_RBR
-DECL_BFIN_UART(2)
-#endif
-#ifdef UART3_RBR
-DECL_BFIN_UART(3)
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if CONFIG_UART_CONSOLE == 0
- return &bfin_serial0_device;
-#elif CONFIG_UART_CONSOLE == 1
- return &bfin_serial1_device;
-#elif CONFIG_UART_CONSOLE == 2
- return &bfin_serial2_device;
-#elif CONFIG_UART_CONSOLE == 3
- return &bfin_serial3_device;
-#endif
-}
-
-void bfin_serial_initialize(void)
-{
-#ifdef UART0_RBR
- serial_register(&bfin_serial0_device);
-#endif
-#ifdef UART1_RBR
- serial_register(&bfin_serial1_device);
-#endif
-#ifdef UART2_RBR
- serial_register(&bfin_serial2_device);
-#endif
-#ifdef UART3_RBR
- serial_register(&bfin_serial3_device);
-#endif
-}
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-inline void uart_early_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- uart_early_putc(uart_base, '\r');
-
- /* wait for the hardware fifo to clear up */
- while (!(_lsr_read(pUART) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-}
-
-void uart_early_puts(const char *s)
-{
- while (*s)
- uart_early_putc(UART_BASE, *s++);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_set_baud(uint32_t baud)
-{
- serial_early_set_baud(UART_BASE, baud);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_init(void)
-{
- serial_early_init(UART_BASE);
-}
-#endif
-
-#elif defined(CONFIG_UART_MEM)
-
-char serial_logbuf[CONFIG_UART_MEM];
-char *serial_logbuf_head = serial_logbuf;
-
-int serial_mem_init(void)
-{
- serial_logbuf_head = serial_logbuf;
- return 0;
-}
-
-void serial_mem_setbrg(void)
-{
-}
-
-int serial_mem_tstc(void)
-{
- return 0;
-}
-
-int serial_mem_getc(void)
-{
- return 0;
-}
-
-void serial_mem_putc(const char c)
-{
- *serial_logbuf_head = c;
- if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
- serial_logbuf_head = serial_logbuf;
-}
-
-void serial_mem_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-struct serial_device bfin_serial_mem_device = {
- .name = "bfin_uart_mem",
- .start = serial_mem_init,
- .setbrg = serial_mem_setbrg,
- .getc = serial_mem_getc,
- .tstc = serial_mem_tstc,
- .putc = serial_mem_putc,
- .puts = serial_mem_puts,
-};
-
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &bfin_serial_mem_device;
-}
-
-void bfin_serial_initialize(void)
-{
- serial_register(&bfin_serial_mem_device);
-}
-#endif /* CONFIG_UART_MEM */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fa9a1d2496c6..c090562c7732 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,8 +19,6 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
-obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
-obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
deleted file mode 100644
index 9a6fc781515a..000000000000
--- a/drivers/spi/bfin_spi.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Driver for Blackfin On-Chip SPI device
- *
- * Copyright (c) 2005-2010 Analog Devices Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*#define DEBUG*/
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi.h>
-
-struct bfin_spi_slave {
- struct spi_slave slave;
- void *mmr_base;
- u16 ctl, baud, flg;
-};
-
-#define MAKE_SPI_FUNC(mmr, off) \
-static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
-static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
-MAKE_SPI_FUNC(SPI_CTL, 0x00)
-MAKE_SPI_FUNC(SPI_FLG, 0x04)
-MAKE_SPI_FUNC(SPI_STAT, 0x08)
-MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
-MAKE_SPI_FUNC(SPI_RDBR, 0x10)
-MAKE_SPI_FUNC(SPI_BAUD, 0x14)
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (is_gpio_cs(cs))
- return gpio_is_valid(gpio_cs(cs));
- else
- return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, bss->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
- } else {
- write_SPI_FLG(bss,
- (read_SPI_FLG(bss) &
- ~((!bss->flg << 8) << slave->cs)) |
- (1 << slave->cs));
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
- }
-
- SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, !bss->flg);
- debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
- } else {
- u16 flg;
-
- /* make sure we force the cs to deassert rather than let the
- * pin float back up. otherwise, exact timings may not be
- * met some of the time leading to random behavior (ugh).
- */
- flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
- write_SPI_FLG(bss, flg);
- SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
-
- flg &= ~(1 << slave->cs);
- write_SPI_FLG(bss, flg);
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
- }
-
- SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
-
-#define SPI_PINS(n) \
- [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_CTL
- SPI_PINS(0),
-#endif
-#ifdef SPI1_CTL
- SPI_PINS(1),
-#endif
-#ifdef SPI2_CTL
- SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
- [n] = { \
- P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
- P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
- P_SPI##n##_SSEL7, \
- }
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_CTL
- SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_CTL
- SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_CTL
- SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong clk;
- u32 baud;
-
- clk = get_spi_clk();
- /* baud should be rounded up */
- baud = DIV_ROUND_UP(clk, 2 * hz);
- if (baud < 2)
- baud = 2;
- else if (baud > (u16)-1)
- baud = -1;
- bss->baud = baud;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct bfin_spi_slave *bss;
- u32 mmr_base;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- switch (bus) {
-#ifdef SPI0_CTL
- case 0:
- mmr_base = SPI0_CTL; break;
-#endif
-#ifdef SPI1_CTL
- case 1:
- mmr_base = SPI1_CTL; break;
-#endif
-#ifdef SPI2_CTL
- case 2:
- mmr_base = SPI2_CTL; break;
-#endif
- default:
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
-
- bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
- if (!bss)
- return NULL;
-
- bss->mmr_base = (void *)mmr_base;
- bss->ctl = SPE | MSTR | TDBR_CORE;
- if (mode & SPI_CPHA) bss->ctl |= CPHA;
- if (mode & SPI_CPOL) bss->ctl |= CPOL;
- if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
- bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(&bss->slave, max_hz);
-
- debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
- bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
-
- return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_request(cs, "bfin-spi");
- gpio_direction_output(cs, !bss->flg);
- pins[slave->bus][0] = P_DONTCARE;
- } else
- pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
- peripheral_request_list(pins[slave->bus], "bfin-spi");
-
- write_SPI_CTL(bss, bss->ctl);
- write_SPI_BAUD(bss, bss->baud);
- SSYNC();
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- peripheral_free_list(pins[slave->bus]);
- if (is_gpio_cs(slave->cs))
- gpio_free(gpio_cs(slave->cs));
-
- write_SPI_CTL(bss, 0);
- SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
- uint bytes)
-{
- /* discard invalid data and clear RXS */
- read_SPI_RDBR(bss);
- /* todo: take advantage of hardware fifos */
- while (bytes--) {
- u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
- debug("%s: tx:%x ", __func__, value);
- write_SPI_TDBR(bss, value);
- SSYNC();
- while ((read_SPI_STAT(bss) & TXS))
- if (ctrlc())
- return -1;
- while (!(read_SPI_STAT(bss) & SPIF))
- if (ctrlc())
- return -1;
- while (!(read_SPI_STAT(bss) & RXS))
- if (ctrlc())
- return -1;
- value = read_SPI_RDBR(bss);
- if (rx)
- *rx++ = value;
- debug("rx:%x\n", value);
- }
-
- return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- const u8 *tx = dout;
- u8 *rx = din;
- uint bytes = bitlen / 8;
- int ret = 0;
-
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return ret;
-}
diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c
deleted file mode 100644
index 9a27b78f6417..000000000000
--- a/drivers/spi/bfin_spi6xx.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Analog Devices SPI3 controller driver
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/spi6xx.h>
-
-struct bfin_spi_slave {
- struct spi_slave slave;
- u32 control, clock;
- struct bfin_spi_regs *regs;
- int cs_pol;
-};
-
-#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-
-#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
-#ifdef CONFIG_BFIN_SPI_GPIO_CS
-# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
-#else
-# define is_gpio_cs(cs) 0
-#endif
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (is_gpio_cs(cs))
- return gpio_is_valid(gpio_cs(cs));
- else
- return (cs >= 1 && cs <= MAX_CTRL_CS);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, bss->cs_pol);
- } else {
- u32 ssel;
- ssel = bfin_read32(&bss->regs->ssel);
- ssel |= 1 << slave->cs;
- if (bss->cs_pol)
- ssel |= BIT(8) << slave->cs;
- else
- ssel &= ~(BIT(8) << slave->cs);
- bfin_write32(&bss->regs->ssel, ssel);
- }
-
- SSYNC();
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_set_value(cs, !bss->cs_pol);
- } else {
- u32 ssel;
- ssel = bfin_read32(&bss->regs->ssel);
- if (bss->cs_pol)
- ssel &= ~(BIT(8) << slave->cs);
- else
- ssel |= BIT(8) << slave->cs;
- /* deassert cs */
- bfin_write32(&bss->regs->ssel, ssel);
- SSYNC();
- /* disable cs */
- ssel &= ~(1 << slave->cs);
- bfin_write32(&bss->regs->ssel, ssel);
- }
-
- SSYNC();
-}
-
-void spi_init()
-{
-}
-
-#define SPI_PINS(n) \
- { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
-static unsigned short pins[][5] = {
-#ifdef SPI0_REGBASE
- [0] = SPI_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
- [1] = SPI_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
- [2] = SPI_PINS(2),
-#endif
-};
-
-#define SPI_CS_PINS(n) \
- { \
- P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
- P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
- P_SPI##n##_SSEL7, \
- }
-static const unsigned short cs_pins[][7] = {
-#ifdef SPI0_REGBASE
- [0] = SPI_CS_PINS(0),
-#endif
-#ifdef SPI1_REGBASE
- [1] = SPI_CS_PINS(1),
-#endif
-#ifdef SPI2_REGBASE
- [2] = SPI_CS_PINS(2),
-#endif
-};
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- ulong clk;
- u32 clock;
-
- clk = get_spi_clk();
- clock = clk / hz;
- if (clock)
- clock--;
- bss->clock = clock;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct bfin_spi_slave *bss;
- u32 reg_base;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- switch (bus) {
-#ifdef SPI0_REGBASE
- case 0:
- reg_base = SPI0_REGBASE;
- break;
-#endif
-#ifdef SPI1_REGBASE
- case 1:
- reg_base = SPI1_REGBASE;
- break;
-#endif
-#ifdef SPI2_REGBASE
- case 2:
- reg_base = SPI2_REGBASE;
- break;
-#endif
- default:
- debug("%s: invalid bus %u\n", __func__, bus);
- return NULL;
- }
-
- bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
- if (!bss)
- return NULL;
-
- bss->regs = (struct bfin_spi_regs *)reg_base;
- bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
- if (mode & SPI_CPHA)
- bss->control |= SPI_CTL_CPHA;
- if (mode & SPI_CPOL)
- bss->control |= SPI_CTL_CPOL;
- if (mode & SPI_LSB_FIRST)
- bss->control |= SPI_CTL_LSBF;
- bss->control &= ~SPI_CTL_ASSEL;
- bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(&bss->slave, max_hz);
-
- return &bss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- free(bss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- if (is_gpio_cs(slave->cs)) {
- unsigned int cs = gpio_cs(slave->cs);
- gpio_request(cs, "bfin-spi");
- gpio_direction_output(cs, !bss->cs_pol);
- pins[slave->bus][0] = P_DONTCARE;
- } else
- pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
- peripheral_request_list(pins[slave->bus], "bfin-spi");
-
- bfin_write32(&bss->regs->control, bss->control);
- bfin_write32(&bss->regs->clock, bss->clock);
- bfin_write32(&bss->regs->delay, 0x0);
- bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN);
- bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI);
- SSYNC();
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-
- debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
-
- peripheral_free_list(pins[slave->bus]);
- if (is_gpio_cs(slave->cs))
- gpio_free(gpio_cs(slave->cs));
-
- bfin_write32(&bss->regs->rx_control, 0x0);
- bfin_write32(&bss->regs->tx_control, 0x0);
- bfin_write32(&bss->regs->control, 0x0);
- SSYNC();
-}
-
-#ifndef CONFIG_BFIN_SPI_IDLE_VAL
-# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
-#endif
-
-static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
- uint bytes)
-{
- /* discard invalid rx data and empty rfifo */
- while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE))
- bfin_read32(&bss->regs->rfifo);
-
- while (bytes--) {
- u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
- debug("%s: tx:%x ", __func__, value);
- bfin_write32(&bss->regs->tfifo, value);
- SSYNC();
- while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE)
- if (ctrlc())
- return -1;
- value = bfin_read32(&bss->regs->rfifo);
- if (rx)
- *rx++ = value;
- debug("rx:%x\n", value);
- }
-
- return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- const u8 *tx = dout;
- u8 *rx = din;
- uint bytes = bitlen / 8;
- int ret = 0;
-
- debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
-
- if (bitlen == 0)
- goto done;
-
- /* we can only do 8 bit transfers */
- if (bitlen % 8) {
- flags |= SPI_XFER_END;
- goto done;
- }
-
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
-
- ret = spi_pio_xfer(bss, tx, rx, bytes);
-
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
- return ret;
-}
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index 84cb21b0d6ce..79e118ef856c 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -116,12 +116,9 @@ static inline struct musb *dev_to_musb(struct device *dev)
{
return dev_get_drvdata(dev);
}
-#endif
/*-------------------------------------------------------------------------*/
-#ifndef __UBOOT__
-#ifndef CONFIG_BLACKFIN
static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
{
void __iomem *addr = phy->io_priv;
@@ -203,10 +200,6 @@ out:
return ret;
}
-#else
-#define musb_ulpi_read NULL
-#define musb_ulpi_write NULL
-#endif
static struct usb_phy_io_ops musb_ulpi_access = {
.read = musb_ulpi_read,
@@ -216,7 +209,7 @@ static struct usb_phy_io_ops musb_ulpi_access = {
/*-------------------------------------------------------------------------*/
-#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
+#if !defined(CONFIG_USB_MUSB_TUSB6010)
/*
* Load an endpoint's FIFO
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index 4ae0ae26593b..6394bb052b61 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -152,8 +152,7 @@ enum musb_g_ep0_state {
*/
#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
- || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
- || defined(CONFIG_ARCH_OMAP4)
+ || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_ARCH_OMAP4)
/* REVISIT indexed access seemed to
* misbehave (on DaVinci) for at least peripheral IN ...
*/
@@ -455,34 +454,6 @@ static inline struct musb *gadget_to_musb(struct usb_gadget *g)
return container_of(g, struct musb, g);
}
-#ifdef CONFIG_BLACKFIN
-static inline int musb_read_fifosize(struct musb *musb,
- struct musb_hw_ep *hw_ep, u8 epnum)
-{
- musb->nr_endpoints++;
- musb->epmask |= (1 << epnum);
-
- if (epnum < 5) {
- hw_ep->max_packet_sz_tx = 128;
- hw_ep->max_packet_sz_rx = 128;
- } else {
- hw_ep->max_packet_sz_tx = 1024;
- hw_ep->max_packet_sz_rx = 1024;
- }
- hw_ep->is_shared_fifo = false;
-
- return 0;
-}
-
-static inline void musb_configure_ep0(struct musb *musb)
-{
- musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
- musb->endpoints[0].is_shared_fifo = true;
-}
-
-#else
-
static inline int musb_read_fifosize(struct musb *musb,
struct musb_hw_ep *hw_ep, u8 epnum)
{
@@ -519,8 +490,6 @@ static inline void musb_configure_ep0(struct musb *musb)
musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
musb->endpoints[0].is_shared_fifo = true;
}
-#endif /* CONFIG_BLACKFIN */
-
/***************************** Glue it together *****************************/
diff --git a/drivers/usb/musb-new/musb_dma.h b/drivers/usb/musb-new/musb_dma.h
index 30e39f5ed2b8..c94abb8de343 100644
--- a/drivers/usb/musb-new/musb_dma.h
+++ b/drivers/usb/musb-new/musb_dma.h
@@ -56,17 +56,6 @@ struct musb_hw_ep;
#define tusb_dma_omap() 0
#endif
-/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
- * Only allow DMA mode 1 to be used when the USB will actually generate the
- * interrupts we expect.
- */
-#ifdef CONFIG_BLACKFIN
-# undef USE_MODE1
-# if !ANOMALY_05000456
-# define USE_MODE1
-# endif
-#endif
-
/*
* DMA channel status ... updated by the dma controller driver whenever that
* status changes, and protected by the overall controller spinlock.
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index ea8efb32a708..76682120f48c 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -23,8 +23,8 @@
#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
&& !defined(CONFIG_AVR32) && !defined(CONFIG_PPC32) \
- && !defined(CONFIG_PPC64) && !defined(CONFIG_BLACKFIN) \
- && !defined(CONFIG_MIPS) && !defined(CONFIG_M68K)
+ && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
+ && !defined(CONFIG_M68K)
static inline void readsl(const void __iomem *addr, void *buf, int len)
{ insl((unsigned long)addr, buf, len); }
static inline void readsw(const void __iomem *addr, void *buf, int len)
@@ -41,8 +41,6 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len)
#endif
-#ifndef CONFIG_BLACKFIN
-
/* NOTE: these offsets are all in bytes */
static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
@@ -101,26 +99,4 @@ static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
#endif /* CONFIG_USB_MUSB_TUSB6010 */
-#else
-
-static inline u8 musb_readb(const void __iomem *addr, unsigned offset)
- { return (u8) (bfin_read16(addr + offset)); }
-
-static inline u16 musb_readw(const void __iomem *addr, unsigned offset)
- { return bfin_read16(addr + offset); }
-
-static inline u32 musb_readl(const void __iomem *addr, unsigned offset)
- { return (u32) (bfin_read16(addr + offset)); }
-
-static inline void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
- { bfin_write16(addr + offset, (u16) data); }
-
-static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data)
- { bfin_write16(addr + offset, data); }
-
-static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data)
- { bfin_write16(addr + offset, (u16) data); }
-
-#endif /* CONFIG_BLACKFIN */
-
#endif
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 0f18dd7f7eec..a3cc38e3b921 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -190,8 +190,6 @@
#define MUSB_HUBADDR_MULTI_TT 0x80
-#ifndef CONFIG_BLACKFIN
-
/* SUNXI has different reg addresses, but identical r/w functions */
#ifndef CONFIG_ARCH_SUNXI
@@ -526,193 +524,4 @@ static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT));
}
-#else /* CONFIG_BLACKFIN */
-
-#define USB_BASE USB_FADDR
-#define USB_OFFSET(reg) (reg - USB_BASE)
-
-/*
- * Common USB registers
- */
-#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
-#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
-#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
-#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
-#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
-#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
-#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
-#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
-#define MUSB_FRAME USB_OFFSET(USB_FRAME)
-#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
-#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
-
-/* Get offset for a given FIFO from musb->mregs */
-#define MUSB_FIFO_OFFSET(epnum) \
- (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
-
-/*
- * Additional Control Registers
- */
-
-#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
-
-#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
-#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
-#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
-#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
-#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
-
-/* Offsets to endpoint registers */
-#define MUSB_TXMAXP 0x00
-#define MUSB_TXCSR 0x04
-#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
-#define MUSB_RXMAXP 0x08
-#define MUSB_RXCSR 0x0C
-#define MUSB_RXCOUNT 0x10
-#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
-#define MUSB_TXTYPE 0x14
-#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
-#define MUSB_TXINTERVAL 0x18
-#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
-#define MUSB_RXTYPE 0x1C
-#define MUSB_RXINTERVAL 0x20
-#define MUSB_TXCOUNT 0x28
-
-/* Offsets to endpoint registers in indexed model (using INDEX register) */
-#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
- (0x40 + (_offset))
-
-/* Offsets to endpoint registers in flat models */
-#define MUSB_FLAT_OFFSET(_epnum, _offset) \
- (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
-
-/* Not implemented - HW has separate Tx/Rx FIFO */
-#define MUSB_TXCSR_MODE 0x0000
-
-static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
-{
-}
-
-static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
-{
-}
-
-static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
-{
-}
-
-static inline u8 musb_read_txfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_txfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxfifosz(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_rxfifoadd(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u8 musb_read_configdata(void __iomem *mbase)
-{
- return 0;
-}
-
-static inline u16 musb_read_hwvers(void __iomem *mbase)
-{
- /*
- * This register is invisible on Blackfin, actually the MUSB
- * RTL version of Blackfin is 1.9, so just harcode its value.
- */
- return MUSB_HWVERS_1900;
-}
-
-static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
-{
- return NULL;
-}
-
-static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
- u8 qh_addr_req)
-{
-}
-
-static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
- u8 qh_h_addr_reg)
-{
-}
-
-static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
- u8 qh_h_port_reg)
-{
-}
-
-static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
- u8 qh_addr_reg)
-{
-}
-
-static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
- u8 qh_h_port_reg)
-{
-}
-
-static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum)
-{
- return 0;
-}
-
-#endif /* CONFIG_BLACKFIN */
-
#endif /* __MUSB_REGS_H__ */
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index bd2b7c521fce..9554eddb2988 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -7,7 +7,6 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
-obj-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
obj-$(CONFIG_USB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
obj-$(CONFIG_USB_DA8XX) += da8xx.o
diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c
deleted file mode 100644
index 65fff887d3ee..000000000000
--- a/drivers/usb/musb/blackfin_usb.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-#include <usb.h>
-
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/usb.h>
-
-#include "musb_core.h"
-
-#ifndef CONFIG_USB_BLACKFIN_CLKIN
-#define CONFIG_USB_BLACKFIN_CLKIN 24
-#endif
-
-/* MUSB platform configuration */
-struct musb_config musb_cfg = {
- .regs = (struct musb_regs *)USB_FADDR,
- .timeout = 0x3FFFFFF,
- .musb_speed = 0,
-};
-
-/*
- * This function read or write data to endpoint fifo
- * Blackfin use DMA polling method to avoid buffer alignment issues
- *
- * ep - Endpoint number
- * length - Number of bytes to write to FIFO
- * fifo_data - Pointer to data buffer to be read/write
- * is_write - Flag for read or write
- */
-void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
-{
- struct bfin_musb_dma_regs *regs;
- u32 val = (u32)fifo_data;
-
- blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
-
- regs = (void *)USB_DMA_INTERRUPT;
- regs += ep;
-
- /* Setup DMA address register */
- bfin_write16(®s->addr_low, val);
- SSYNC();
-
- bfin_write16(®s->addr_high, val >> 16);
- SSYNC();
-
- /* Setup DMA count register */
- bfin_write16(®s->count_low, length);
- bfin_write16(®s->count_high, 0);
- SSYNC();
-
- /* Enable the DMA */
- val = (ep << 4) | DMA_ENA | INT_ENA;
- if (is_write)
- val |= DIRECTION;
- bfin_write16(®s->control, val);
- SSYNC();
-
- /* Wait for compelete */
- while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
- continue;
-
- /* acknowledge dma interrupt */
- bfin_write_USB_DMA_INTERRUPT(1 << ep);
- SSYNC();
-
- /* Reset DMA */
- bfin_write16(®s->control, 0);
- SSYNC();
-}
-
-void write_fifo(u8 ep, u32 length, void *fifo_data)
-{
- rw_fifo(ep, length, fifo_data, 1);
-}
-
-void read_fifo(u8 ep, u32 length, void *fifo_data)
-{
- rw_fifo(ep, length, fifo_data, 0);
-}
-
-
-/*
- * CPU and board-specific MUSB initializations. Aliased function
- * signals caller to move on.
- */
-static void __def_musb_init(void)
-{
-}
-void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
-
-static void bfin_anomaly_init(void)
-{
- u32 revid;
-
- if (!ANOMALY_05000346 && !ANOMALY_05000347)
- return;
-
- revid = bfin_revid();
-
-#ifdef __ADSPBF54x__
- if (revid > 0)
- return;
-#endif
-#ifdef __ADSPBF52x__
- if (ANOMALY_BF526 && revid > 0)
- return;
- if (ANOMALY_BF527 && revid > 1)
- return;
-#endif
-
- if (ANOMALY_05000346) {
- bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
- SSYNC();
- }
-
- if (ANOMALY_05000347) {
- bfin_write_USB_APHY_CNTRL(0x0);
- SSYNC();
- }
-}
-
-int musb_platform_init(void)
-{
- /* board specific initialization */
- board_musb_init();
-
- bfin_anomaly_init();
-
- /* Configure PLL oscillator register */
- bfin_write_USB_PLLOSC_CTRL(0x3080 |
- ((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
- SSYNC();
-
- bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
- SSYNC();
-
- bfin_write_USB_EP_NI0_RXMAXP(64);
- SSYNC();
-
- bfin_write_USB_EP_NI0_TXMAXP(64);
- SSYNC();
-
- /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
- bfin_write_USB_GLOBINTR(0x7);
- SSYNC();
-
- bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
- EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
- EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
- EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
- EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
- SSYNC();
-
- return 0;
-}
-
-/*
- * This function performs Blackfin platform specific deinitialization for usb.
-*/
-void musb_platform_deinit(void)
-{
-}
diff --git a/drivers/usb/musb/blackfin_usb.h b/drivers/usb/musb/blackfin_usb.h
deleted file mode 100644
index de994bf33610..000000000000
--- a/drivers/usb/musb/blackfin_usb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Blackfin MUSB HCD (Host Controller Driver) for u-boot
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_USB_H__
-#define __BLACKFIN_USB_H__
-
-#include <linux/types.h>
-
-/* Every register is 32bit aligned, but only 16bits in size */
-#define ureg(name) u16 name; u16 __pad_##name;
-
-#define musb_regs musb_regs
-struct musb_regs {
- /* common registers */
- ureg(faddr)
- ureg(power)
- ureg(intrtx)
- ureg(intrrx)
- ureg(intrtxe)
- ureg(intrrxe)
- ureg(intrusb)
- ureg(intrusbe)
- ureg(frame)
- ureg(index)
- ureg(testmode)
- ureg(globintr)
- ureg(global_ctl)
- u32 reserved0[3];
- /* indexed registers */
- ureg(txmaxp)
- ureg(txcsr)
- ureg(rxmaxp)
- ureg(rxcsr)
- ureg(rxcount)
- ureg(txtype)
- ureg(txinterval)
- ureg(rxtype)
- ureg(rxinterval)
- u32 reserved1;
- ureg(txcount)
- u32 reserved2[5];
- /* fifo */
- u16 fifox[32];
- /* OTG, dynamic FIFO, version & vendor registers */
- u32 reserved3[16];
- ureg(devctl)
- ureg(vbus_irq)
- ureg(vbus_mask)
- u32 reserved4[15];
- ureg(linkinfo)
- ureg(vplen)
- ureg(hseof1)
- ureg(fseof1)
- ureg(lseof1)
- u32 reserved5[41];
- /* target address registers */
- struct musb_tar_regs {
- ureg(txmaxp)
- ureg(txcsr)
- ureg(rxmaxp)
- ureg(rxcsr)
- ureg(rxcount)
- ureg(txtype)
- ureg(txinternal)
- ureg(rxtype)
- ureg(rxinternal)
- u32 reserved6;
- ureg(txcount)
- u32 reserved7[5];
- } tar[8];
-} __attribute__((packed));
-
-struct bfin_musb_dma_regs {
- ureg(interrupt);
- ureg(control);
- ureg(addr_low);
- ureg(addr_high);
- ureg(count_low);
- ureg(count_high);
- u32 reserved0[2];
-};
-
-#undef ureg
-
-/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
-#define MUSB_BULK_EP 5
-
-/* Blackfin FIFO's are static */
-#define MUSB_NO_DYNAMIC_FIFO
-
-/* No HUB support :( */
-#define MUSB_NO_MULTIPOINT
-
-#endif
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index dc863bdd2809..ae352ce80714 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -13,10 +13,6 @@
#include <usb_defs.h>
#include <asm/io.h>
-#ifdef CONFIG_USB_BLACKFIN
-# include "blackfin_usb.h"
-#endif
-
#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
/* EP0 */
@@ -336,28 +332,6 @@ extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
-#if defined(CONFIG_USB_BLACKFIN)
-/* Every USB register is accessed as a 16-bit even if the value itself
- * is only 8-bits in size. Fun stuff.
- */
-# undef readb
-# define readb(addr) (u8)bfin_read16(addr)
-# undef writeb
-# define writeb(b, addr) bfin_write16(addr, b)
-# undef MUSB_TXCSR_MODE /* not supported */
-# define MUSB_TXCSR_MODE 0
-/*
- * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
- * However, it has no ULPI support - so there are no registers at all.
- * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
- */
-static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
-{
- return 0;
-}
-static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
-{}
-#else
static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
{
return readb(&musbr->ulpi_busctl);
@@ -366,6 +340,5 @@ static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
{
writeb(val, &musbr->ulpi_busctl);
}
-#endif
#endif /* __MUSB_HDRC_DEFS_H__ */
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 49479368d215..fee0848adec1 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -913,11 +913,6 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
(len-txlen) : dev->epmaxpacketout[ep];
-#ifdef CONFIG_USB_BLACKFIN
- /* Set the transfer data size */
- writew(nextlen, &musbr->txcount);
-#endif
-
/* Write the data to the FIFO */
write_fifo(MUSB_BULK_EP, nextlen,
(void *)(((u8 *)buffer) + txlen));
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index a8b7e14c0490..f7c973432ec9 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -141,19 +141,6 @@ gd_t *global_data;
" lwi r5, r5, %1\n" \
" bra r5\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r5");
-#elif defined(CONFIG_BLACKFIN)
-/*
- * P3 holds the pointer to the global_data, P0 is a call-clobbered
- * register
- */
-#define EXPORT_FUNC(f, a, x, ...) \
- asm volatile ( \
-" .globl _" #x "\n_" \
-#x ":\n" \
-" P0 = [P3 + %0]\n" \
-" P0 = [P0 + %1]\n" \
-" JUMP (P0)\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "P0");
#elif defined(CONFIG_AVR32)
/*
* r6 holds the pointer to the global_data. r8 is call clobbered.
diff --git a/include/common.h b/include/common.h
index fbbc2cbc521a..833b90482d56 100644
--- a/include/common.h
+++ b/include/common.h
@@ -76,9 +76,6 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_4xx
#include <asm/ppc4xx.h>
#endif
-#ifdef CONFIG_BLACKFIN
-#include <asm/blackfin.h>
-#endif
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
deleted file mode 100644
index de60bb10358a..000000000000
--- a/include/configs/bct-brettl2.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * U-Boot - Configuration file for BF536 brettl2 board
- */
-
-#ifndef __CONFIG_BCT_BRETTL2_H__
-#define __CONFIG_BCT_BRETTL2_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf536-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 16384000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 24
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 3
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-/*
- * SDRAM Settings
- */
-#define CONFIG_EBIU_SDRRC_VAL 0x07f6
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC 1
-#define CONFIG_NETCONSOLE 1
-#define CONFIG_HOSTNAME brettl2
-#define CONFIG_IPADDR 192.168.233.224
-#define CONFIG_GATEWAYIP 192.168.233.1
-#define CONFIG_SERVERIP 192.168.233.53
-#define CONFIG_ROOTPATH "/romfs/brettl2"
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x12000
-
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_LOADADDR 0x800000
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/* disable unnecessary features */
-#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_BZIP2
-#undef CONFIG_KALLSYMS
-
-#endif
diff --git a/include/configs/bf506f-ezkit.h b/include/configs/bf506f-ezkit.h
deleted file mode 100644
index 6cad00fd7cfa..000000000000
--- a/include/configs/bf506f-ezkit.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * U-Boot - Configuration file for BF506F EZ-Kit board
- */
-
-#ifndef __CONFIG_BF506F_EZKIT_H__
-#define __CONFIG_BF506F_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf506-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 16
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE 0
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
-
-#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END)
-#define CONFIG_SYS_MONITOR_LEN (4 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024)
-
-/*
- * Flash Settings
- */
-/*
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-#define CONFIG_MONITOR_IS_IN_RAM
-*/
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x400
-
-/*
- * Misc Settings
- */
-#define CONFIG_ICACHE_OFF
-#define CONFIG_DCACHE_OFF
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BFIN_SERIAL
-
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
-#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_BOOTM_LINUX
-
-#endif
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
deleted file mode 100644
index e3c22869bc26..000000000000
--- a/include/configs/bf518f-ezbrd.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * U-Boot - Configuration file for BF518F EZBrd board
- */
-
-#ifndef __CONFIG_BF518F_EZBRD_H__
-#define __CONFIG_BF518F_EZBRD_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf518-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 16
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-/* This board has a 64meg MT48H32M16 */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x0096
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_BFIN_MAC_PINS \
- { \
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, \
- 0 }
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME bf518f-ezbrd
-#define CONFIG_PHY_ADDR 3
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SDH Settings
- */
-#if !defined(__ADSPBF512__)
-#define CONFIG_BFIN_SDH
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
deleted file mode 100644
index b58c1db96083..000000000000
--- a/include/configs/bf525-ucr2.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * U-Boot - Configuration file for bf525-ucr2 board
- * The board includes ADSP-BF525 rev. 0.2,
- * 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
- * USB 2.0 High Speed OTG USB WIFI,
- * SPI flash (cFeon EN25Q128 16 MB),
- * Support PPI and ITU-R656,
- * See http://www.ucrobotics.com/?q=cn/ucr2
- */
-
-#ifndef __CONFIG_BF525_UCR2_H__
-#define __CONFIG_BF525_UCR2_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf525-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-/*
- * SDRAM reference page
- * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
- */
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (320 * 1024)
-
-/* support for serial flash */
-#define CONFIG_BFIN_SPI
-#define CONFIG_SF_DEFAULT_HZ 30000000
-
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE 0
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BFIN_SERIAL
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-#define CONFIG_BOOTCOMMAND "run sfboot"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "sfboot=sf probe 1;" \
- "sf read 0x1000000 0x20000 0x300000;" \
- "bootm 0x1000000\0"
-
-#endif
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
deleted file mode 100644
index 7d75e73f7264..000000000000
--- a/include/configs/bf526-ezbrd.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * U-Boot - Configuration file for BF526 EZBrd board
- */
-
-#ifndef __CONFIG_BF526_EZBRD_H__
-#define __CONFIG_BF526_EZBRD_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf526-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 16
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-/* This board has a 64meg MT48H32M16 */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x0267
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
- !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME bf526-ezbrd
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 1
-
-/* define to enable run status via led */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
deleted file mode 100644
index e433aaa91d3e..000000000000
--- a/include/configs/bf527-ad7160-eval.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * U-Boot - Configuration file for BF527 AD7160-EVAL board
- */
-
-#ifndef __CONFIG_BF527_AD7160_EVAL_H__
-#define __CONFIG_BF527_AD7160_EVAL_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf527-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 25
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x03F6
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
deleted file mode 100644
index d945b8d7bfc0..000000000000
--- a/include/configs/bf527-ezkit.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 STAMP board
- */
-
-#ifndef __CONFIG_BF527_EZKIT_H__
-#define __CONFIG_BF527_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf527-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x03F6
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
-/*
- * NAND Settings
- * (can't be used same time as ethernet)
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
- !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME bf527-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/* Don't waste time transferring a logo over the UART */
-
-/*
- * Video Settings
- */
-#ifdef CONFIG_VIDEO
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-# define CONFIG_LQ035Q1_SPI_BUS 0
-# define CONFIG_LQ035Q1_SPI_CS 7
-# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#else
-# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#endif
-
-#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h>
-#else
-# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
-#endif
-#endif /* CONFIG_VIDEO */
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 1
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
deleted file mode 100644
index 6b7d19e639e3..000000000000
--- a/include/configs/bf527-sdp.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * U-Boot - Configuration file for BF527 SDP board
- */
-
-#ifndef __CONFIG_BF527_SDP_H__
-#define __CONFIG_BF527_SDP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf527-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 24000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 25
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-#define CONFIG_PLL_LOCKCNT_VAL 0x0200
-#define CONFIG_PLL_CTL_VAL 0x2a00
-#define CONFIG_VR_CTL_VAL 0x7090
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x00FE
-#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
deleted file mode 100644
index e154812abd6a..000000000000
--- a/include/configs/bf533-ezkit.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * U-Boot - Configuration file for BF533 EZKIT board
- */
-
-#ifndef __CONFIG_BF533_EZKIT_H__
-#define __CONFIG_BF533_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 27000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 22
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE 32
-/* Early EZKITs had 32megs, but later have 64megs */
-#if (CONFIG_MEM_SIZE == 64)
-# define CONFIG_MEM_ADD_WDTH 10
-#else
-# define CONFIG_MEM_ADD_WDTH 9
-#endif
-
-#define CONFIG_EBIU_SDRRC_VAL 0x398
-#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20310300
-#define SMC91111_EEPROM_INIT() \
- do { \
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
- bfin_write_FIO_FLAG_C(PF1); \
- bfin_write_FIO_FLAG_S(PF0); \
- SSYNC(); \
- } while (0)
-#define CONFIG_HOSTNAME bf533-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 3
-#define CONFIG_SYS_MAX_FLASH_SECT 40
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR 0x20030000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define FLASH_TOT_SECT 40
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
deleted file mode 100644
index 516fe2d02153..000000000000
--- a/include/configs/bf533-stamp.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * U-Boot - Configuration file for BF533 STAMP board
- */
-
-#ifndef __CONFIG_BF533_STAMP_H__
-#define __CONFIG_BF533_STAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 11059200
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 45
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 11
-#define CONFIG_MEM_SIZE 128
-
-#define CONFIG_EBIU_SDRRC_VAL 0x268
-#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20300300
-#define SMC91111_EEPROM_INIT() \
- do { \
- bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
- bfin_write_FIO_FLAG_C(PF1); \
- bfin_write_FIO_FLAG_S(PF0); \
- SSYNC(); \
- } while (0)
-#define CONFIG_HOSTNAME bf533-stamp
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-/*
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_ALL
-*/
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-#endif
-
-/*
- * Compact Flash / IDE / ATA Settings
- */
-
-/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF */
-#if defined(CONFIG_STAMP_CF)
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
-
-#define CONFIG_SYS_ATA_STRIDE 2
-
-#undef CONFIG_EBIU_AMBCTL1_VAL
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/* FLASH/ETHERNET uses the same async bank */
-#define SHARED_RESOURCES 1
-
-/* define to enable boot progress via leds */
-/* #define CONFIG_SHOW_BOOT_PROGRESS */
-
-/* define to enable run status via led */
-
-/* define to enable splash screen support */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
deleted file mode 100644
index cabbe371218f..000000000000
--- a/include/configs/bf537-minotaur.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * U-Boot - Configuration file for CSP Minotaur board
- *
- * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
- * Minotaur config, brushed up for official uClinux dist.
- * Parallel flash support disabled, SPI flash boot command
- * added ('run flashboot').
- *
- * Flash image map:
- *
- * 0x00000000 u-boot bootstrap
- * 0x00010000 environment
- * 0x00020000 u-boot code
- * 0x00030000 uImage.initramfs
- *
- */
-
-#ifndef __CONFIG_BF537_MINOTAUR_H__
-#define __CONFIG_BF537_MINOTAUR_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE 32
-#define CONFIG_MEM_ADD_WDTH 9
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (128 << 10)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE 1
-#endif
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME bf537-minotaur
-#endif
-
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_ROOTPATH "/romfs"
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-/*
- * Misc Settings
- */
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_ENV_OVERWRITE 1
-
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-
-#define CONFIG_PANIC_HANG 1
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_LOADS_ECHO 1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-
-#define BOOT_ENV_SETTINGS \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 0x30000;" \
- "sf write $(loadaddr) 0 $(filesize)" \
- "flashboot=sf read 0x1000000 0x30000 0x320000;" \
- "bootm 0x1000000\0"
-#ifdef CONFIG_BFIN_MAC
-# define NETWORK_ENV_SETTINGS \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- NETWORK_ENV_SETTINGS \
- "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
- BOOT_ENV_SETTINGS
-
-#endif
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
deleted file mode 100644
index bced1df12c78..000000000000
--- a/include/configs/bf537-pnav.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 PNAV board
- */
-
-#ifndef __CONFIG_BF537_PNAV_H__
-#define __CONFIG_BF537_PNAV_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 24576000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3b7
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#endif
-#define CONFIG_HOSTNAME bf537-pnav
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#else
-#define ENV_IS_EMBEDDED
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_OFFSET 0x4000
-#endif
-#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-
-#define CONFIG_SYS_NAND_BASE 0x20100000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
-
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
deleted file mode 100644
index 4b23aa8ab871..000000000000
--- a/include/configs/bf537-srv1.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * U-Boot - Configuration file for CSP Minotaur board
- *
- * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
- * Minotaur config, brushed up for official uClinux dist.
- * Parallel flash support disabled, SPI flash boot command
- * added ('run flashboot').
- *
- * Flash image map:
- *
- * 0x00000000 u-boot bootstrap
- * 0x00010000 environment
- * 0x00020000 u-boot code
- * 0x00030000 uImage.initramfs
- *
- */
-
-#ifndef __CONFIG_BF537_SRV1_H__
-#define __CONFIG_BF537_SRV1_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 22118400
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE 32
-#define CONFIG_MEM_ADD_WDTH 9
-
-#define CONFIG_EBIU_SDRRC_VAL 0x2ac
-#define CONFIG_EBIU_SDGCTL_VAL 0x91110d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (384 << 10)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE 1
-#endif
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME bf537-srv1
-#endif
-
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_ROOTPATH "/romfs"
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-/*
- * Misc Settings
- */
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_ENV_OVERWRITE 1
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-
-#define CONFIG_PANIC_HANG 1
-#define CONFIG_RTC_BFIN 1
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_LOADS_ECHO 1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-
-#define BOOT_ENV_SETTINGS \
- "update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 0x30000;" \
- "sf write $(loadaddr) 0 $(filesize)" \
- "flashboot=sf read 0x1000000 0x30000 0x320000;" \
- "bootm 0x1000000\0"
-#ifdef CONFIG_BFIN_MAC
-# define NETWORK_ENV_SETTINGS \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath)\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
- ":$(hostname):eth0:off\0" \
- "ramboot=tftpboot $(loadaddr) linux;" \
- "run ramargs;run addip;bootelf\0" \
- "nfsboot=tftpboot $(loadaddr) linux;" \
- "run nfsargs;run addip;bootelf\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- NETWORK_ENV_SETTINGS \
- "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
- BOOT_ENV_SETTINGS
-
-#endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
deleted file mode 100644
index 685815372062..000000000000
--- a/include/configs/bf537-stamp.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * U-Boot - Configuration file for BF537 STAMP board
- */
-
-#ifndef __CONFIG_BF537_STAMP_H__
-#define __CONFIG_BF537_STAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME bf537-stamp
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * NAND Settings
- */
-/* #define CONFIG_NAND_PLAT */
-#ifdef CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE 0x20212000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
-#endif /* CONFIG_NAND_PLAT */
-
-/*
- * CF-CARD IDE-HDD Support
- */
-
-/*
- * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
- * Strange address mapping Blackfin A13 connects to CF_A0
- */
-
-/* #define CONFIG_BFIN_TRUE_IDE */
-
-/*
- * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
- * This should be the preferred mode
- */
-
-/* #define CONFIG_BFIN_CF_IDE */
-
-/*
- * Add IDE Disk Drive (HDD) support
- * See example interface here:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
- */
-
-/* #define CONFIG_BFIN_HDD_IDE */
-
-#if defined(CONFIG_BFIN_CF_IDE) || \
- defined(CONFIG_BFIN_HDD_IDE) || \
- defined(CONFIG_BFIN_TRUE_IDE)
-# define CONFIG_BFIN_IDE 1
-# define CONFIG_CMD_IDE
-#endif
-
-#if defined(CONFIG_BFIN_IDE)
-
-/*
- * IDE/ATA stuff
- */
-#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
-#undef CONFIG_IDE_LED /* no led for ide supported */
-#undef CONFIG_IDE_RESET /* no reset for ide supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
-
-#undef CONFIG_EBIU_AMBCTL1_VAL
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
-
-#define CONFIG_CF_ATASEL_DIS 0x20311800
-#define CONFIG_CF_ATASEL_ENA 0x20311802
-
-#if defined(CONFIG_BFIN_TRUE_IDE)
-/*
- * Note that these settings aren't for the most part used in include/ata.h
- * when all of the ATA registers are setup
- */
-#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
-
-#elif defined(CONFIG_BFIN_CF_IDE)
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
-
-#elif defined(CONFIG_BFIN_HDD_IDE)
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
-#undef CONFIG_SCLK_DIV
-#define CONFIG_SCLK_DIV 8
-#endif
-
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
-#define CONFIG_POST_BSPEC1_GPIO_LEDS \
- GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
-#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
- GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
-#define CONFIG_POST_BSPEC2_GPIO_NAMES \
- 10, 11, 12, 13,
-#define CONFIG_SYS_POST_FLASH_START 11
-#define CONFIG_SYS_POST_FLASH_END 71
-#endif
-
-/* These are for board tests */
-#if 0
-#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
deleted file mode 100644
index a6d039c96d1f..000000000000
--- a/include/configs/bf538f-ezkit.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * U-Boot - Configuration file for BF538F EZ-Kit Lite board
- */
-
-#ifndef __CONFIG_BF538F_EZKIT_H__
-#define __CONFIG_BF538F_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf538-0.4
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20310300
-#define CONFIG_HOSTNAME bf538f-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-/*
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_ALL
-*/
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
deleted file mode 100644
index 35cbebdfb80e..000000000000
--- a/include/configs/bf548-ezkit.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * U-Boot - Configuration file for BF548 STAMP board
- */
-
-#ifndef __CONFIG_BF548_EZKIT_H__
-#define __CONFIG_BF548_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf548-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
-#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
-#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
-
-/* Default EZ-Kit bank mapping:
- * Async Bank 0 - 32MB Burst Flash
- * Async Bank 1 - Ethernet
- * Async Bank 2 - Nothing
- * Async Bank 3 - Nothing
- */
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
-#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
-
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x24000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME bf548-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_SIZE 0x20000
-#else
-/* The BF548-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#endif
-
-/*
- * NAND Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
-#define CONFIG_BFIN_NFC_BOOTROM_ECC
-#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SATA
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_LIBATA
-#define CONFIG_SYS_SATA_MAX_DEVICE 1
-#define CONFIG_LBA48
-#define CONFIG_PATA_BFIN
-#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
-#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
-#endif
-
-/*
- * SDH Settings
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_BFIN_SDH
-#endif
-
-/*
- * USB Settings
- */
-#if !defined(__ADSPBF544__)
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_BLACKFIN
-#define CONFIG_USB_MUSB_TIMEOUT 100000
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-
-#define CONFIG_ADI_GPIO2
-
-#ifdef CONFIG_VIDEO
-#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
-#define CONFIG_DEB_DMA_URGENT
-#endif
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define CONFIG_POST_BSPEC1_GPIO_LEDS \
- GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
-#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
- GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
-#define CONFIG_POST_BSPEC2_GPIO_NAMES \
- 13, 12, 11, 10,
-#define CONFIG_SYS_POST_FLASH_START 10
-#define CONFIG_SYS_POST_FLASH_END 127
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
deleted file mode 100644
index 3a4631e4fee6..000000000000
--- a/include/configs/bf561-acvilon.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * U-Boot - Configuration file for BF561 Acvilon System On Module
- * For more information please go to http://www.niistt.ru/
- */
-
-#ifndef __CONFIG_BF561_ACVILON_H__
-#define __CONFIG_BF561_ACVILON_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 12000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 50
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 128
-
-#define CONFIG_EBIU_SDRRC_VAL 0x300
-#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189
-
-#define CONFIG_EBIU_AMGCTL_VAL 0x4e
-#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * RTC Settings
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_I2C_DTT_ADDR 0x49
-/*#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3*/
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DTT
-
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_32_BIT
-/* #define CONFIG_SMC911X_16_BIT */
-#define CONFIG_SMC911X_BASE 0x28000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-#define CONFIG_HOSTNAME bf561-acvilon
-
-/*
- * I2C Settings
- */
-#define CONFIG_HARD_I2C
-/* Use 300kHz speed by default */
-#define CONFIG_SYS_I2C_SPEED 0x00
-#define CONFIG_PCA9564_I2C
-#define CONFIG_PCA9564_BASE 0x2c000000
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 10000000
-#define CONFIG_SF_DEFAULT_SPEED 10000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SECT_SIZE (1056 * 8)
-#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
-#define CONFIG_ENV_SIZE (8 * 1056)
-
-/*
- * NAND Settings
- * We're using NAND_PLAT driver to make things simplier
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BASE 0x24000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BAUDRATE 57600
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif /* __CONFIG_BF561_ACVILON_H__ */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
deleted file mode 100644
index 2fefe98f85e6..000000000000
--- a/include/configs/bf561-ezkit.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * U-Boot - Configuration file for BF561 EZKIT board
- */
-
-#ifndef __CONFIG_BF561_EZKIT_H__
-#define __CONFIG_BF561_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 30000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 6
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x2C010300
-#define CONFIG_SMC_USE_32_BIT 1
-#define CONFIG_HOSTNAME bf561-ezkit
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-/* The BF561-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE 0x2000
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C_SOFT
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-#endif
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Run core 1 from L1 SRAM start address when init uboot on core 0
- */
-/* #define CONFIG_CORE1_RUN 1 */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
deleted file mode 100644
index 5791810b3529..000000000000
--- a/include/configs/bf609-ezkit.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * U-Boot - Configuration file for BF609 EZ-Kit board
- */
-
-#ifndef __CONFIG_BF609_EZKIT_H__
-#define __CONFIG_BF609_EZKIT_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf609-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/* For ez-board version 1.0, else undef this */
-#define CONFIG_BFIN_BOARD_VERSION_1_0
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
- * SCLK0 = SCLK / SCLK0_DIV
- * SCLK1 = SCLK / SCLK1_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ (25000000)
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF (0)
-
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-127 (where 0 means 128) */
-#define CONFIG_VCO_MULT (20)
-
-/* CCLK_DIV controls the core clock divider */
-/* Values can range from 0-31 (where 0 means 32) */
-#define CONFIG_CCLK_DIV (1)
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 0-31 (where 0 means 32) */
-#define CONFIG_SCLK_DIV (4)
-/* Values can range from 0-7 (where 0 means 8) */
-#define CONFIG_SCLK0_DIV (1)
-#define CONFIG_SCLK1_DIV (1)
-/* DCLK_DIV controls the DDR clock divider */
-/* Values can range from 0-31 (where 0 means 32) */
-#define CONFIG_DCLK_DIV (2)
-/* OCLK_DIV controls the output clock divider */
-/* Values can range from 0-127 (where 0 means 128) */
-#define CONFIG_OCLK_DIV (16)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_SIZE 128
-
-#define CONFIG_SMC_GCTL_VAL 0x00000010
-#define CONFIG_SMC_B0CTL_VAL 0x01007011
-#define CONFIG_SMC_B0TIM_VAL 0x08170977
-#define CONFIG_SMC_B0ETIM_VAL 0x00092231
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-#define CONFIG_HW_WATCHDOG
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK
-#define CONFIG_NETCONSOLE
-#define CONFIG_HOSTNAME "bf609-ezkit"
-#define CONFIG_PHY_ADDR 1
-#define CONFIG_DW_PORTS 1
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-
-/* i2c Settings */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Flash Settings
- */
-#undef CONFIG_CMD_JFFS2
-#define CONFIG_SYS_FLASH_CFI_WIDTH 2
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0xb0000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 131
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI6XX
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-#define CONFIG_SPI_FLASH_ALL
-
-/*
- * Env Storage Settings
- */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
-
-/*
- * SDH Settings
- */
-#define CONFIG_BFIN_SDH
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE 0
-
-#define CONFIG_CMD_SOFTSWITCH
-
-#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
-#define CONFIG_BFIN_SOFT_SWITCH
-
-#define CONFIG_ADI_GPIO2
-
-#if 0
-#define CONFIG_UART_MEM 1024
-#undef CONFIG_UART_CONSOLE
-#undef CONFIG_JTAG_CONSOLE
-#undef CONFIG_UART_CONSOLE_IS_JTAG
-#endif
-
-#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
-
-/*
- * Run core 1 from L1 SRAM start address when init uboot on core 0
- */
-/* #define CONFIG_CORE1_RUN 1 */
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-#endif
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
deleted file mode 100644
index 5d61f99871bc..000000000000
--- a/include/configs/bfin_adi_common.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * U-Boot - Common settings for Analog Devices boards
- */
-
-#ifndef __CONFIG_BFIN_ADI_COMMON_H__
-#define __CONFIG_BFIN_ADI_COMMON_H__
-
-/*
- * Command Settings
- */
-#ifndef _CONFIG_CMD_DEFAULT_H
-# ifdef ADI_CMDS_NETWORK
-# define CONFIG_BOOTP_SUBNETMASK
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_DNS
-# define CONFIG_BOOTP_NTPSERVER
-# define CONFIG_BOOTP_RANDOM_DELAY
-# define CONFIG_KEEP_SERVERADDR
-# ifdef CONFIG_BFIN_MAC
-# endif
-# endif
-# ifdef CONFIG_LIBATA
-# define CONFIG_CMD_SATA
-# endif
-# ifdef CONFIG_MMC
-# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-# endif
-# ifdef CONFIG_MMC_SPI
-# define CONFIG_CMD_MMC_SPI
-# endif
-# ifdef CONFIG_USB
-# define CONFIG_CMD_USB_STORAGE
-# endif
-# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
-# define CONFIG_CMD_NAND
-# define CONFIG_CMD_NAND_LOCK_UNLOCK
-# endif
-# ifdef CONFIG_POST
-# define CONFIG_CMD_DIAG
-# endif
-# ifdef CONFIG_RTC_BFIN
-# define CONFIG_CMD_DATE
-# ifdef ADI_CMDS_NETWORK
-# endif
-# endif
-# ifdef CONFIG_SPI
-# define CONFIG_CMD_EEPROM
-# endif
-# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-# define CONFIG_SOFT_I2C_READ_REPEATED_START
-# endif
-# ifdef CONFIG_MTD_NOR_FLASH
-# define CONFIG_CMD_JFFS2
-# endif
-# ifdef CONFIG_CMD_JFFS2
-# define CONFIG_JFFS2_SUMMARY
-# endif
-# define CONFIG_CMD_BOOTLDR
-# define CONFIG_CMD_CPLBINFO
-# define CONFIG_CMD_KGDB
-# define CONFIG_CMD_LDRINFO
-# define CONFIG_CMD_REGINFO
-# define CONFIG_CMD_STRINGS
-# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
-# define CONFIG_CMD_OTP
-# define CONFIG_CMD_SPIBOOTLDR
-# endif
-#endif
-
-/*
- * Console Settings
- */
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_JTAG_CONSOLE
-#ifndef CONFIG_BAUDRATE
-# define CONFIG_BAUDRATE 57600
-#endif
-#ifdef CONFIG_UART_CONSOLE
-# define CONFIG_BFIN_SERIAL
-#endif
-
-/*
- * Debug Settings
- */
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_DEBUG_DUMP 1
-#define CONFIG_KALLSYMS 1
-#define CONFIG_PANIC_HANG 1
-
-/*
- * Env Settings
- */
-#ifndef CONFIG_BOOTCOMMAND
-# define CONFIG_BOOTCOMMAND "run ramboot"
-#endif
-#ifdef CONFIG_VIDEO
-# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
-#else
-# define CONFIG_BOOTARGS_VIDEO ""
-#endif
-#ifndef CONFIG_BOOTARGS_ROOT
-# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw"
-#endif
-#ifndef FLASHBOOT_ENV_SETTINGS
-# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0"
-#endif
-#define CONFIG_BOOTARGS \
- "root=" CONFIG_BOOTARGS_ROOT " " \
- "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
- "earlyprintk=" \
- "serial," \
- "uart" __stringify(CONFIG_UART_CONSOLE) "," \
- __stringify(CONFIG_BAUDRATE) " " \
- CONFIG_BOOTARGS_VIDEO \
- "console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \
- __stringify(CONFIG_BAUDRATE)
-#if defined(CONFIG_CMD_NAND)
-# define NAND_ENV_SETTINGS \
- "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
- "nandboot=" \
- "nand read $(loadaddr) 0x20000 0x100000;" \
- "run nandargs;" \
- "bootm" \
- "\0"
-#else
-# define NAND_ENV_SETTINGS
-#endif
-#if defined(CONFIG_CMD_NET)
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-# define UBOOT_ENV_FILE "u-boot.bin"
-# else
-# define UBOOT_ENV_FILE "u-boot.ldr"
-# endif
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-# ifdef CONFIG_SPI
-# define UBOOT_ENV_UPDATE \
- "eeprom write $(loadaddr) 0x0 $(filesize)"
-# else
-# ifndef CONFIG_BFIN_SPI_IMG_SIZE
-# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
-# endif
-# define UBOOT_ENV_UPDATE \
- "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
- "sf write $(loadaddr) 0 $(filesize)"
-# endif
-# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define UBOOT_ENV_UPDATE \
- "nand unlock 0 0x40000;" \
- "nand erase 0 0x40000;" \
- "nand write $(loadaddr) 0 0x40000"
-# else
-# ifndef UBOOT_ENV_UPDATE
-# define UBOOT_ENV_UPDATE \
- "protect off 0x20000000 +$(filesize);" \
- "erase 0x20000000 +$(filesize);" \
- "cp.b $(loadaddr) 0x20000000 $(filesize)"
-# endif
-# endif
-# ifdef CONFIG_NETCONSOLE
-# define NETCONSOLE_ENV \
- "nc=" \
- "set ncip ${serverip};" \
- "set stdin nc;" \
- "set stdout nc;" \
- "set stderr nc" \
- "\0"
-# else
-# define NETCONSOLE_ENV
-# endif
-# define NETWORK_ENV_SETTINGS \
- NETCONSOLE_ENV \
- \
- "ubootfile=" UBOOT_ENV_FILE "\0" \
- "update=" \
- "tftp $(loadaddr) $(ubootfile);" \
- UBOOT_ENV_UPDATE \
- "\0" \
- "addip=set bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
- "$(hostname):eth0:off" \
- "\0" \
- \
- "ramfile=uImage\0" \
- "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
- "ramboot=" \
- "tftp $(loadaddr) $(ramfile);" \
- "run ramargs;" \
- "run addip;" \
- "bootm" \
- "\0" \
- \
- "nfsfile=vmImage\0" \
- "nfsargs=set bootargs " \
- "root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
- "\0" \
- "nfsboot=" \
- "tftp $(loadaddr) $(nfsfile);" \
- "run nfsargs;" \
- "run addip;" \
- "bootm" \
- "\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-#ifndef BOARD_ENV_SETTINGS
-# define BOARD_ENV_SETTINGS
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- NAND_ENV_SETTINGS \
- NETWORK_ENV_SETTINGS \
- FLASHBOOT_ENV_SETTINGS \
- BOARD_ENV_SETTINGS
-
-/*
- * Network Settings
- */
-#ifdef CONFIG_CMD_NET
-# define CONFIG_NETMASK 255.255.255.0
-# ifndef CONFIG_IPADDR
-# define CONFIG_IPADDR 192.168.0.15
-# define CONFIG_GATEWAYIP 192.168.0.1
-# define CONFIG_SERVERIP 192.168.0.2
-# endif
-# ifndef CONFIG_ROOTPATH
-# define CONFIG_ROOTPATH "/romfs"
-# endif
-# ifdef CONFIG_CMD_DHCP
-# ifndef CONFIG_SYS_AUTOLOAD
-# define CONFIG_SYS_AUTOLOAD "no"
-# endif
-# endif
-# define CONFIG_IP_DEFRAG
-# define CONFIG_NET_RETRY_COUNT 20
-#endif
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-/*
- * SPI Settings
- */
-#ifdef CONFIG_SPI_FLASH_ALL
-#endif
-
-/*
- * I2C Settings
- */
-#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-# ifndef CONFIG_SYS_I2C_SPEED
-# define CONFIG_SYS_I2C_SPEED 50000
-# endif
-# ifndef CONFIG_SYS_I2C_SLAVE
-# define CONFIG_SYS_I2C_SLAVE 0
-# endif
-#endif
-
-/*
- * Misc Settings
- */
-#ifndef CONFIG_BOARD_SIZE_LIMIT
-# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
-#endif
-#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
-#define CONFIG_LZMA
-#define CONFIG_MONITOR_IS_IN_RAM
-#ifdef CONFIG_HW_WATCHDOG
-# define CONFIG_BFIN_WATCHDOG
-# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
-# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
-# endif
-#endif
-#ifndef CONFIG_ADI_GPIO2
-# define CONFIG_ADI_GPIO1
-#endif
-#endif
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
deleted file mode 100644
index 5044f73b065d..000000000000
--- a/include/configs/blackstamp.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * U-Boot - Configuration file for BlackStamp board
- * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
- * as a template
- * See http://blackfin.uclinux.org/gf/project/blackstamp/
- */
-
-#ifndef __CONFIG_BLACKSTAMP_H__
-#define __CONFIG_BLACKSTAMP_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Debugging: Set these options if you're having problems
- */
-/*
- * #define CONFIG_DEBUG_EARLY_SERIAL
- * #define DEBUG
- * #define CONFIG_DEBUG_DUMP
- * #define CONFIG_DEBUG_DUMP_SYMS
-*/
-#define CONFIG_PANIC_HANG 0
-
-/* CPU Options
- * Be sure to set the Silicon Revision Correctly
- */
-#define CONFIG_BFIN_CPU bf532-0.5
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Board settings
- */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20300300
-
-/* FLASH/ETHERNET uses the same address range
- * Depending on what you have the CPLD doing
- * this probably isn't needed
- */
-#define SHARED_RESOURCES 1
-
-/* Is I2C bit-banged? */
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 16
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 3
-
-/*
- * Network settings
- */
-
-#ifdef CONFIG_SMC91111
-#define CONFIG_IPADDR 192.168.0.15
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_HOSTNAME blackstamp
-#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs"
-#define CONFIG_SYS_AUTOLOAD "no"
-#endif
-
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (384 << 10)
-
-/*
- * Command settings
- */
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_ENV_OVERWRITE 1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CPLBINFO
-#define CONFIG_CMD_DATE
-
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock0 rw " \
- "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
- "earlyprintk=" \
- "serial," \
- "uart" __stringify(CONFIG_UART_CONSOLE) "," \
- __stringify(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," __stringify(CONFIG_BAUDRATE)
-
-#if defined(CONFIG_CMD_NET)
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-# define UBOOT_ENV_FILE "u-boot.bin"
-# else
-# define UBOOT_ENV_FILE "u-boot.ldr"
-# endif
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-# ifdef CONFIG_SPI
-# define UBOOT_ENV_UPDATE \
- "eeprom write $(loadaddr) 0x0 $(filesize)"
-# else
-# define UBOOT_ENV_UPDATE \
- "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 0x40000;" \
- "sf write $(loadaddr) 0 $(filesize)"
-# endif
-# else
-# define UBOOT_ENV_UPDATE \
- "protect off 0x20000000 0x2003FFFF;" \
- "erase 0x20000000 0x2003FFFF;" \
- "cp.b $(loadaddr) 0x20000000 $(filesize)"
-# endif
-# define NETWORK_ENV_SETTINGS \
- "ubootfile=" UBOOT_ENV_FILE "\0" \
- "update=" \
- "tftp $(loadaddr) $(ubootfile);" \
- UBOOT_ENV_UPDATE \
- "\0" \
- "addip=set bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
- "$(hostname):eth0:off" \
- "\0" \
- "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
- "ramboot=" \
- "tftp $(loadaddr) uImage;" \
- "run ramargs;" \
- "run addip;" \
- "bootm" \
- "\0" \
- "nfsargs=set bootargs " \
- "root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
- "\0" \
- "nfsboot=" \
- "tftp $(loadaddr) vmImage;" \
- "run nfsargs;" \
- "run addip;" \
- "bootm" \
- "\0"
-#else
-# define NETWORK_ENV_SETTINGS
-#endif
-
-/*
- * Console settings
- */
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-
-/*
- * I2C settings
- * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
- * Located on the expansion connector on pins 86/85
- * Note these pins are arbitrarily chosen because we aren't using
- * them yet. You can (and probably should) change these values!
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_RTC_BFIN 1
-
-/*
- * Serial Flash Infomation
- */
-#define CONFIG_BFIN_SPI
-/* For the M25P64 SCK Should be Kept < 15Mhz */
-#define CONFIG_ENV_SPI_MAX_HZ 15000000
-#define CONFIG_SF_DEFAULT_SPEED 15000000
-
-/*
- * FLASH organization and environment definitions
- */
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
-#define CONFIG_EBIU_SDRRC_VAL 0x268
-#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-
-#undef CONFIG_CMD_JFFS2
-
-#endif
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
deleted file mode 100644
index 0b8f4c042894..000000000000
--- a/include/configs/blackvme.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* U-Boot for BlackVME. (C) Wojtek Skulski 2010.
- * The board includes ADSP-BF561 rev. 0.5,
- * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
- * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
- * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
- * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
- * Spartan6-LX150 (memory-mapped; both PPIs also connected).
- * See http://www.skutek.com
- */
-
-#ifndef __CONFIG_BLACKVME_H__
-#define __CONFIG_BLACKVME_H__
-
-#include <asm/config-pre.h>
-
-/* Debugging: Set these options if you're having problems
- * #define CONFIG_DEBUG_EARLY_SERIAL
- * #define DEBUG
- * #define CONFIG_DEBUG_DUMP
- * #define CONFIG_DEBUG_DUMP_SYMS
- * CONFIG_PANIC_HANG means that the board will not auto-reboot
- */
-#define CONFIG_PANIC_HANG 0
-
-/* CPU Options */
-#define CONFIG_BFIN_CPU bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * CLOCK SETTINGS CAVEAT
- * You CANNOT just change the clock settings, esp. the SCLK.
- * The SDRAM timing, SPI baud, and the serial UART baud
- * use SCLK frequency to set their own frequencies. Therefore,
- * if you change the SCLK_DIV, you may also have to adjust
- * SDRAM refresh and other timings.
- * --------------------------------------------------------------
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * 25 * 8 / 1 = 200 MHz
- * 25 * 16 / 1 = 400 MHz
- * 25 * 24 / 1 = 600 MHz
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- * 25 * 8 / 2 = 100 MHz
- * 25 * 24 / 6 = 100 MHz
- * 25 * 24 / 5 = 120 MHz
- * 25 * 16 / 3 = 133 MHz
- * 25 MHz because the oscillator also feeds the ether chip.
- * CONFIG_CLKIN_HZ is 25 MHz written in Hz
- * CLKIN_HALF controls the DF bit in PLL_CTL
- * 0 = CLKIN 1 = CLKIN / 2
- * PLL_BYPASS controls the BYPASS bit in PLL_CTL
- * 0 = do not bypass 1 = bypass PLL
- * VCO_MULT = MSEL (multiplier) in PLL_CTL
- * Values can range from 0-63 (where 0 means 64)
- * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
- * SCLK_DIV = system clock divider, 1 to 15
- */
-#define CONFIG_CLKIN_HZ 25000000
-#define CONFIG_CLKIN_HALF 0
-#define CONFIG_PLL_BYPASS 0
-#define CONFIG_VCO_MULT 8
-#define CONFIG_CCLK_DIV 1
-#define CONFIG_SCLK_DIV 2
-
-/*
- * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
- * Used in 32-bit mode. 16-bit mode not supported.
- * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
- */
-/*
- * Network settings using a dedicated 2nd ether card in PC
- * Windows will automatically acquire IP of that card
- * Then use the dedicated card IP + 1 for the board
- * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
- */
-#define CONFIG_DRIVER_AX88180 1
-#define AX88180_BASE 0x2c000000
-
-#define CONFIG_HOSTNAME blackvme /* Bfin board */
-#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */
-#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */
-#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/
-#define CFG_AUTOLOAD "no"
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
-/*
- * SDRAM reference page
- * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
- * NOTE: BlackVME populates only SDRAM bank 0
- */
-/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */
-#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */
-
-/* Async memory global settings. (ASRAM, not SDRAM)
- * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
- * CLKOUT enabled, all async banks enabled, core has priority
- * bank 0&1 16 bit (FPGA)
- * bank 2&3 32 bit (ether and USB chips)
- */
-#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */
-
-/* Async mem timing: BF561 HRM page 16-12 and 16-15.
- * Default values 0xFFC2 FFC2 are the slowest supported.
- * Example settings of CONFIG_EBIU_AMBCTL1_VAL
- * 1. EZ-KIT settings: 0xFFC2 7BB0
- * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
- * See the following page:
- * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
- * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
- * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
- * One extra clock needed because AX88180 is asynchronous to CPU.
- */
- /* bank 1 0 */
-#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
- /* bank 3 2 */
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
-
-/* memory layout */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (384 << 10)
-
-/*
- * Serial SPI Flash
- * For the M25P64 SCK should be kept < 15 MHz
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-
-#define CONFIG_ENV_SPI_MAX_HZ 15000000
-#define CONFIG_SF_DEFAULT_SPEED 15000000
-
-/*
- * Interactive command settings
- */
-
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-
-#define CONFIG_CMD_BOOTLDR
-#define CONFIG_CMD_CPLBINFO
-
-/*
- * Default: boot from SPI flash.
- * "sfboot" is a composite command defined in extra settings
- */
-#define CONFIG_BOOTCOMMAND "run sfboot"
-
-/*
- * Console settings
- */
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_LOADS_ECHO 1
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-
-/*
- * U-Boot environment variables. Use "printenv" to examine.
- * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
- */
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock0 rw " \
- "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
- "earlyprintk=serial,uart0," \
- __stringify(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
-
-/* Convenience env variables & commands.
- * Reserve kernstart = 0x20000 = 128 kB for U-Boot.
- * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size).
- * U-Boot image is saved at flash offset=0.
- * Kernel image is saved at flash offset=$kernstart.
- * Instructions. Ksave takes about a minute to complete.
- * 1. Update U-Boot: run uget; run usave
- * 2. Update kernel: run kget; run ksave
- * After updating U-Boot also update the kernel per above instructions
- * to make the saved environment consistent with the flash.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernstart=0x20000\0" \
- "kernarea=0x500000\0" \
- "uget=tftp u-boot.ldr\0" \
- "kget=tftp uImage\0" \
- "usave=sf probe 2; " \
- "sf erase 0 $(kernstart); " \
- "sf write $(fileaddr) 0 $(filesize)\0" \
- "ksave=sf probe 2; " \
- "saveenv; " \
- "echo Now patiently wait for the prompt...; " \
- "sf erase $(kernstart) $(kernarea); " \
- "sf write $(fileaddr) $(kernstart) $(filesize)\0" \
- "sfboot=sf probe 2; " \
- "sf read $(loadaddr) $(kernstart) $(filesize); " \
- "run addip; bootm\0" \
- "addip=setenv bootargs $(bootargs) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):" \
- "$(netmask):$(hostname):eth0:off\0"
-
-/*
- * Soft I2C settings (BF561 does not have hard I2C)
- * PF12,13 on SPI connector 0.
- */
-#ifdef CONFIG_SYS_I2C_SOFT
-# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
-# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
-# define CONFIG_SYS_I2C_SPEED 50000
-# define CONFIG_SYS_I2C_SLAVE 0xFE
-#endif
-
-#undef CONFIG_CMD_JFFS2
-
-#endif
diff --git a/include/configs/br4.h b/include/configs/br4.h
deleted file mode 100644
index 64b379a979f9..000000000000
--- a/include/configs/br4.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * U-Boot - Configuration file for BR4 Appliance
- *
- * based on bf537-stamp.h
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- */
-
-#ifndef __CONFIG_BR4_H__
-#define __CONFIG_BR4_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 24
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE
-#endif
-#define CONFIG_HOSTNAME br4
-#define CONFIG_TFTP_BLOCKSIZE 4404
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE 0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_LOADADDR 0x2000000
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/*
- * Overwrite some settings defined in bfin_adi_common.h
- */
-#undef NAND_ENV_SETTINGS
-#define NAND_ENV_SETTINGS \
- "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
- "nandboot=" \
- "nand read $(loadaddr) 0x0 0x900000;" \
- "run nandargs;" \
- "bootm" \
- "\0"
-
-#endif
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
deleted file mode 100644
index 0b31dc95d796..000000000000
--- a/include/configs/cm-bf527.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF527 board
- */
-
-#ifndef __CONFIG_CM_BF527_H__
-#define __CONFIG_CM_BF527_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf527-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * NAND Settings
- * (can't be used sametime as ethernet)
- */
-/* #define CONFIG_BFIN_NFC */
-#ifdef CONFIG_BFIN_NFC
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_CMD_NAND
-#endif
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
- !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_RMII
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME cm-bf527
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20008000
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
- "flashboot=flread 20040000 1000000 300000;" \
- "bootm 0x1000000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
deleted file mode 100644
index 7039cbaaea6c..000000000000
--- a/include/configs/cm-bf533.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF533 board
- */
-
-#ifndef __CONFIG_CM_BF533_H__
-#define __CONFIG_CM_BF533_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 22
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2))
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20200300
-#define CONFIG_HOSTNAME cm-bf533
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 16
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x10000
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
deleted file mode 100644
index cc31a30dbb93..000000000000
--- a/include/configs/cm-bf537e.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF537E board
- */
-
-#ifndef __CONFIG_CM_BF537E_H__
-#define __CONFIG_CM_BF537E_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME cm-bf537e
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 35
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
- "flashboot=flread 20040000 1000000 3c0000;" \
- "bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
deleted file mode 100644
index 282eb4f0b290..000000000000
--- a/include/configs/cm-bf537u.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF537U board
- */
-
-#ifndef __CONFIG_CM_BF537U_H__
-#define __CONFIG_CM_BF537U_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 30000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 18
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-/* Core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME cm-bf537u
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 35
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
- "flashboot=flread 20040000 1000000 300000;" \
- "bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
deleted file mode 100644
index 02a46cae3d89..000000000000
--- a/include/configs/cm-bf548.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * U-Boot - Configuration file for cm-bf548 board
- */
-
-#ifndef __CONFIG_CM_BF548_H__
-#define __CONFIG_CM_BF548_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf548-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
-#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
-#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
-
-/* Default bank mapping:
- * Async Bank 0 - 32MB Burst Flash
- * Async Bank 1 - Ethernet
- * Async Bank 2 - Nothing
- * Async Bank 3 - Nothing
- */
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
-#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x24000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME cm-bf548
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 259
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20008000
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 1
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
-#define CONFIG_ADI_GPIO2
-
-#ifndef __ADSPBF542__
-/* Don't waste time transferring a logo over the UART */
-# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
-# endif
-# define CONFIG_DEB_DMA_URGENT
-#endif
-
-/* Define if want to do post memory test */
-#undef CONFIG_POST
-#ifdef CONFIG_POST
-#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
-#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
-#endif
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
deleted file mode 100644
index 3860e0e258fa..000000000000
--- a/include/configs/cm-bf561.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * U-Boot - Configuration file for CM-BF561 board
- */
-
-#ifndef __CONFIG_CM_BF561_H__
-#define __CONFIG_CM_BF561_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 20
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
-#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
-
-#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_HOSTNAME cm-bf561
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h
deleted file mode 100644
index 0a7bc8a08bc1..000000000000
--- a/include/configs/dnp5370.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * U-Boot - Configuration file for SSV DNP5370 board
- */
-
-#ifndef __CONFIG_DNP5370_H__
-#define __CONFIG_DNP5370_H__
-
-/* this must come first */
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-#define CONFIG_CLKIN_HZ 25000000
-#define CONFIG_CLKIN_HALF 0
-#define CONFIG_PLL_BYPASS 0
-#define CONFIG_VCO_MULT 24
-#define CONFIG_CCLK_DIV 1
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x03a0
-#define CONFIG_EBIU_SDBCTL_VAL 0x0013
-#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xF7
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define CONFIG_ROOTPATH "/romfs"
-
-#define CONFIG_BFIN_MAC 1
-#define CONFIG_PHY_ADDR 0
-#define CONFIG_RMII 1
-
-#endif
-
-/*
- * Flash Settings
- *
- * Only 3 MB of the 4 MB NOR flash are addressable.
- * But limiting the flash size does not seem to work.
- * It seems the CFI detection has precedence.
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */
-
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20004000
-#define CONFIG_ENV_SIZE 0x00002000
-#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */
-
-#define ENV_IS_EMBEDDED
-#define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-
-/*
- * Misc Settings
- */
-#define CONFIG_CMD_STRINGS
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_SYS_LONGHELP
-
-/* This disables the hardware watchdog (not inside the bfin) */
-#define CONFIG_DNP5370_EXT_WD_DISABLE 1
-
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BFIN_SERIAL
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTCOMMAND "bootm 0x20030000"
-#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2"
-
-/* Convenience commands to update Linux in NOR flash */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "fetchme=tftpboot 0x01000000 uImage;" \
- "iminfo\0" \
- "flashme=protect off 0x20030000 0x2003ffff;" \
- "erase 0x20030000 0x202effff;" \
- "cp.b 0x01000000 0x20030000 0x2c0000\0" \
- "runme=bootm 0x01000000\0"
-
-#endif
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
deleted file mode 100644
index 4cd0f771462d..000000000000
--- a/include/configs/ibf-dsp561.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * U-Boot - Configuration file for IBF-DSP561 board
- */
-
-#ifndef __CONFIG_IBF_DSP561__H__
-#define __CONFIG_IBF_DSP561__H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf561-0.5
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 24
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x377
-#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
-#define CONFIG_EBIU_SDBCTL_VAL 0x15
-
-#define CONFIG_EBIU_AMGCTL_VAL 0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_AX88180 1
-#define AX88180_BASE 0x2c000000
-#define CONFIG_HOSTNAME ibf-dsp561
-
-/*
- * Flash Settings
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
-/* The BF561-EZKIT uses a top boot flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x12000 /* Total Size of Environment Sector */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#else
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
-#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
-
-/*
- * Misc Settings
- */
-#define CONFIG_UART_CONSOLE 0
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
deleted file mode 100644
index ff8d43295046..000000000000
--- a/include/configs/ip04.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * U-Boot - Configuration file for IP04 board (having BF532 processor)
- *
- * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov at gmail.com
- *
- * Copyright (c) 2005-2010 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __CONFIG_IP04_H__
-#define __CONFIG_IP04_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf532-0.5
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 10000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 40
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 3
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 10
-#define CONFIG_MEM_SIZE 64
-
-#define CONFIG_EBIU_SDRRC_VAL 0x408
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
-#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_HOSTNAME IP04
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_NO_SROM
-#define CONFIG_DM9000_BASE 0x20100000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
-
-/*
- * Flash Settings
- */
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_PREBOOT "echo starting from spi flash"
-#define CONFIG_ENV_OFFSET 0x30000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE 0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_UART_CONSOLE 0
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-/* Enable this if bootretry required; currently it's disabled */
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_BOOTCOMMAND "run nandboot"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
deleted file mode 100644
index 500d7156c7ea..000000000000
--- a/include/configs/pr1.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * U-Boot - Configuration file for PR1 Appliance
- *
- * based on bf537-stamp.h
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- */
-
-#ifndef __CONFIG_PR1_H__
-#define __CONFIG_PR1_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 24
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 5
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 11
-#define CONFIG_MEM_SIZE 128
-
-#define CONFIG_EBIU_SDRRC_VAL 0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
-
-#define CONFIG_EBIU_AMGCTL_VAL 0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE
-#endif
-#define CONFIG_HOSTNAME pr1
-#define CONFIG_TFTP_BLOCKSIZE 4404
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET 0x10000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * NAND Settings
- */
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_NAND_BASE 0x20000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
-#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_WRITE(addr, cmd) \
- do { \
- bfin_write8(addr, cmd); \
- SSYNC(); \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_LOADADDR 0x2000000
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-/*
- * Overwrite some settings defined in bfin_adi_common.h
- */
-#undef NAND_ENV_SETTINGS
-#define NAND_ENV_SETTINGS \
- "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
- "nandboot=" \
- "nand read $(loadaddr) 0x0 0x900000;" \
- "run nandargs;" \
- "bootm" \
- "\0"
-
-#endif
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
deleted file mode 100644
index e017ba92caa6..000000000000
--- a/include/configs/tcm-bf518.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * U-Boot - Configuration file for Bluetechnix TCM-BF518 board
- */
-
-#ifndef __CONFIG_TCM_BF518_H__
-#define __CONFIG_TCM_BF518_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf518-0.0
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 16
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/*
- * Memory Settings
- */
-/* This board has a 32meg MT48H16M16 */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
-
-/*
- * Network Settings
- */
-#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME tcm-bf518
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 19
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
deleted file mode 100644
index 4d1cdb507b5c..000000000000
--- a/include/configs/tcm-bf537.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * U-Boot - Configuration file for TCM-BF537 board
- */
-
-#ifndef __CONFIG_TCM_BF537_H__
-#define __CONFIG_TCM_BF537_H__
-
-#include <asm/config-pre.h>
-
-/*
- * Processor Settings
- */
-#define CONFIG_BFIN_CPU bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/*
- * Clock Settings
- * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
- * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
- */
-/* CONFIG_CLKIN_HZ is any value in Hz */
-#define CONFIG_CLKIN_HZ 25000000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
-#define CONFIG_CLKIN_HALF 0
-/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
-#define CONFIG_PLL_BYPASS 0
-/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
-/* Values can range from 0-63 (where 0 means 64) */
-#define CONFIG_VCO_MULT 21
-/* CCLK_DIV controls the core clock divider */
-/* Values can be 1, 2, 4, or 8 ONLY */
-#define CONFIG_CCLK_DIV 1
-/* SCLK_DIV controls the system clock divider */
-/* Values can range from 1-15 */
-#define CONFIG_SCLK_DIV 4
-
-/* Decrease core voltage */
-#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
-
-/*
- * Memory Settings
- */
-#define CONFIG_MEM_ADD_WDTH 9
-#define CONFIG_MEM_SIZE 32
-
-#define CONFIG_EBIU_SDRRC_VAL 0x3f8
-#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
-
-#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
-#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
-#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-
-/*
- * Network Settings
- */
-#ifndef __ADSPBF534__
-#define ADI_CMDS_NETWORK 1
-#define CONFIG_BFIN_MAC
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE 0x20308000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_NETCONSOLE 1
-#endif
-#define CONFIG_HOSTNAME tcm-bf537
-
-/*
- * Flash Settings
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 67
-
-/*
- * SPI Settings
- */
-#define CONFIG_BFIN_SPI
-#define CONFIG_ENV_SPI_MAX_HZ 30000000
-
-/*
- * Env Storage Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x8000
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
-#define ENV_IS_EMBEDDED
-#endif
-#ifdef ENV_IS_EMBEDDED
-/* WARNING - the following is hand-optimized to fit within
- * the sector before the environment sector. If it throws
- * an error during compilation remove an object here to get
- * it linked after the configuration sector.
- */
-# define LDS_BOARD_TEXT \
- arch/blackfin/lib/built-in.o (.text*); \
- arch/blackfin/cpu/built-in.o (.text*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text*);
-#endif
-
-/*
- * I2C Settings
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_ADI
-
-/*
- * SPI_MMC Settings
- */
-#define CONFIG_MMC_SPI
-
-/*
- * Misc Settings
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MISC_INIT_R
-#define CONFIG_RTC_BFIN
-#define CONFIG_UART_CONSOLE 0
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define FLASHBOOT_ENV_SETTINGS \
- "flashboot=flread 20040000 1000000 300000;" \
- "bootm 0x1000000\0"
-#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
-/*
- * Pull in common ADI header for remaining command/environment setup
- */
-#include <configs/bfin_adi_common.h>
-
-#endif
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
index 075d222195ff..e1fdab0c0f0a 100644
--- a/include/linux/usb/musb.h
+++ b/include/linux/usb/musb.h
@@ -91,14 +91,6 @@ struct musb_hdrc_config {
u8 ram_bits; /* ram address size */
struct musb_hdrc_eps_bits *eps_bits __deprecated;
-#ifdef CONFIG_BLACKFIN
- /* A GPIO controlling VRSEL in Blackfin */
- unsigned int gpio_vrsel;
- unsigned int gpio_vrsel_active;
- /* musb CLKIN in Blackfin in MHZ */
- unsigned char clkin;
-#endif
-
};
struct musb_hdrc_platform_data {
diff --git a/post/post.c b/post/post.c
index 4194edb89e86..8c2c822acbd2 100644
--- a/post/post.c
+++ b/post/post.c
@@ -474,7 +474,7 @@ void post_reloc(void)
*/
unsigned long post_time_ms(unsigned long base)
{
-#if defined(CONFIG_PPC) || defined(CONFIG_BLACKFIN) || defined(CONFIG_ARM)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
return (unsigned long)lldiv(get_ticks(), get_tbclk() / CONFIG_SYS_HZ)
- base;
#else
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f38e56cbe3c8..3bb8bc06bd4c 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -66,8 +66,6 @@ CONFIG_ADDRESS
CONFIG_ADDR_AUTO_INCR_BIT
CONFIG_ADDR_MAP
CONFIG_ADDR_STREAMING
-CONFIG_ADI_GPIO1
-CONFIG_ADI_GPIO2
CONFIG_ADNPESC1
CONFIG_ADP_AG101P
CONFIG_AEABI
@@ -236,45 +234,10 @@ CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
CONFIG_BD_NUM_CPUS
-CONFIG_BF506_UART0_PORTF
-CONFIG_BF506_UART1_PORTG
-CONFIG_BF50x
-CONFIG_BF51x
-CONFIG_BF527_EZKIT_REV_2_1
-CONFIG_BF52x
-CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-CONFIG_BF54x
-CONFIG_BF60x
-CONFIG_BFIN_ATAPI_BASE_ADDR
CONFIG_BFIN_ATA_MODE
-CONFIG_BFIN_BOARD_VERSION_1_0
-CONFIG_BFIN_BOOTROM_USES_EVT1
-CONFIG_BFIN_BOOT_MODE
-CONFIG_BFIN_CF_IDE
-CONFIG_BFIN_CPU
-CONFIG_BFIN_GET_DCLK_M
-CONFIG_BFIN_GPIO_TRACK
-CONFIG_BFIN_HDD_IDE
-CONFIG_BFIN_IDE
-CONFIG_BFIN_INS_LOWOVERHEAD
-CONFIG_BFIN_LINKPORT
-CONFIG_BFIN_MAC
CONFIG_BFIN_MAC_PINS
-CONFIG_BFIN_NFC
CONFIG_BFIN_NFC_BOOTROM_ECC
-CONFIG_BFIN_NFC_CTL_VAL
CONFIG_BFIN_NFC_NO_HW_ECC
-CONFIG_BFIN_SCRATCH_REG
-CONFIG_BFIN_SDH
-CONFIG_BFIN_SERIAL
-CONFIG_BFIN_SOFT_SWITCH
-CONFIG_BFIN_SPI
-CONFIG_BFIN_SPI6XX
-CONFIG_BFIN_SPI_GPIO_CS
-CONFIG_BFIN_SPI_IDLE_VAL
-CONFIG_BFIN_SPI_IMG_SIZE
-CONFIG_BFIN_TRUE_IDE
-CONFIG_BFIN_WATCHDOG
CONFIG_BIOSEMU
CONFIG_BITBANGMII_MULTI
CONFIG_BKUP_FLASH
@@ -312,9 +275,7 @@ CONFIG_BOOGER
CONFIG_BOOM
CONFIG_BOOTARGS
CONFIG_BOOTARGS_AXM
-CONFIG_BOOTARGS_ROOT
CONFIG_BOOTARGS_TAURUS
-CONFIG_BOOTARGS_VIDEO
CONFIG_BOOTBLOCK
CONFIG_BOOTCOMMAND
CONFIG_BOOTCOUNT_ALEN
@@ -385,17 +346,12 @@ CONFIG_BUILD_ENVCRC
CONFIG_BUILD_TARGET
CONFIG_BUS_WIDTH
CONFIG_BZIP2
-CONFIG_CACHELINE_ALIGNED_L1
CONFIG_CADDY2
CONFIG_CALXEDA_XGMAC
CONFIG_CAM5200
CONFIG_CAM5200_NIOSFLASH
CONFIG_CANMB
CONFIG_CAN_DRIVER
-CONFIG_CCLK_ACT_DIV
-CONFIG_CCLK_DIV
-CONFIG_CCLK_DIV_not_defined_properly
-CONFIG_CCLK_HZ
CONFIG_CDP_APPLIANCE_VLAN_TYPE
CONFIG_CDP_CAPABILITIES
CONFIG_CDP_DEVICE_ID
@@ -409,8 +365,6 @@ CONFIG_CFG_DATA_SECTOR
CONFIG_CFG_FAT
CONFIG_CFG_USB
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-CONFIG_CF_ATASEL_DIS
-CONFIG_CF_ATASEL_ENA
CONFIG_CF_DSPI
CONFIG_CF_SBF
CONFIG_CF_SPI
@@ -418,8 +372,6 @@ CONFIG_CF_V2
CONFIG_CF_V3
CONFIG_CF_V4
CONFIG_CF_V4E
-CONFIG_CGU_CTL_VAL
-CONFIG_CGU_DIV_VAL
CONFIG_CHAIN_BOOT_CMD
CONFIG_CHARON
CONFIG_CHIP_SELECTS_PER_CTRL
@@ -429,8 +381,6 @@ CONFIG_CIS8201_PHY
CONFIG_CI_UDC_HAS_HOSTPC
CONFIG_CLK0_DIV
CONFIG_CLK0_EN
-CONFIG_CLKIN_HALF
-CONFIG_CLKIN_HZ
CONFIG_CLK_1000_200_200
CONFIG_CLK_1000_330_165
CONFIG_CLK_1000_400_200
@@ -451,13 +401,11 @@ CONFIG_CMD_BEDBUG
CONFIG_CMD_BLOB
CONFIG_CMD_BMODE
CONFIG_CMD_BMP
-CONFIG_CMD_BOOTLDR
CONFIG_CMD_BSP
CONFIG_CMD_CBFS
CONFIG_CMD_CHIP_CONFIG
CONFIG_CMD_CLEAR
CONFIG_CMD_CLK
-CONFIG_CMD_CPLBINFO
CONFIG_CMD_CRAMFS
CONFIG_CMD_DATE
CONFIG_CMD_DEFAULTENV_VARS
@@ -505,7 +453,6 @@ CONFIG_CMD_IOTRACE
CONFIG_CMD_IRQ
CONFIG_CMD_JFFS2
CONFIG_CMD_KGDB
-CONFIG_CMD_LDRINFO
CONFIG_CMD_LOADY
CONFIG_CMD_LZMADEC
CONFIG_CMD_MAX6957
@@ -519,7 +466,6 @@ CONFIG_CMD_NAND_LOCK_UNLOCK
CONFIG_CMD_NAND_TORTURE
CONFIG_CMD_NAND_TRIMFFS
CONFIG_CMD_ONENAND
-CONFIG_CMD_OTP
CONFIG_CMD_PCA953X
CONFIG_CMD_PCA953X_INFO
CONFIG_CMD_PCI
@@ -536,8 +482,6 @@ CONFIG_CMD_SCSI
CONFIG_CMD_SDRAM
CONFIG_CMD_SF_TEST
CONFIG_CMD_SH_ZIMAGEBOOT
-CONFIG_CMD_SOFTSWITCH
-CONFIG_CMD_SPIBOOTLDR
CONFIG_CMD_SPL
CONFIG_CMD_SPL_NAND_OFS
CONFIG_CMD_SPL_WRITE_SIZE
@@ -551,7 +495,6 @@ CONFIG_CMD_TRACE
CONFIG_CMD_TSI148
CONFIG_CMD_UBIFS
CONFIG_CMD_UNIVERSE
-CONFIG_CMD_USB_STORAGE
CONFIG_CMD_UUID
CONFIG_CMD_ZBOOT
CONFIG_CMD_ZFS
@@ -590,7 +533,6 @@ CONFIG_CONS_SCIF7
CONFIG_CONTROL
CONFIG_CONTROLCENTERD
CONFIG_CON_ROT
-CONFIG_CORE1_RUN
CONFIG_CORE_COUNT
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
@@ -672,9 +614,7 @@ CONFIG_DBG_MONITOR
CONFIG_DB_784MP_GP
CONFIG_DCACHE
CONFIG_DCACHE_OFF
-CONFIG_DCACHE_WB
CONFIG_DCFG_ADDR
-CONFIG_DCLK_DIV
CONFIG_DDR_
CONFIG_DDR_2HCLK
CONFIG_DDR_2T_TIMING
@@ -704,19 +644,13 @@ CONFIG_DDR_RFDC_FIXED
CONFIG_DDR_RQDC_FIXED
CONFIG_DDR_SPD
CONFIG_DEBUG
-CONFIG_DEBUG_DUMP
-CONFIG_DEBUG_DUMP_SYMS
-CONFIG_DEBUG_EARLY_SERIAL
CONFIG_DEBUG_FS
CONFIG_DEBUG_LED
CONFIG_DEBUG_LOCK_ALLOC
-CONFIG_DEBUG_NULL_PTR
CONFIG_DEBUG_SECTION_MISMATCH
CONFIG_DEBUG_SEMIHOSTING
-CONFIG_DEBUG_SERIAL
CONFIG_DEBUG_UART_LINFLEXUART
CONFIG_DEBUG_WRITECOUNT
-CONFIG_DEB_DMA_URGENT
CONFIG_DEEP_SLEEP
CONFIG_DEFAULT
CONFIG_DEFAULT_CONSOLE
@@ -766,15 +700,7 @@ CONFIG_DMA_COHERENT_SIZE
CONFIG_DMA_LPC32XX
CONFIG_DMA_NONCOHERENT
CONFIG_DMA_REQ_BIT
-CONFIG_DMC_DDRCFG
-CONFIG_DMC_DDRCTL
-CONFIG_DMC_DDREMR1
-CONFIG_DMC_DDRMR
-CONFIG_DMC_DDRTR0
-CONFIG_DMC_DDRTR1
-CONFIG_DMC_DDRTR2
CONFIG_DNET_AUTONEG_TIMEOUT
-CONFIG_DNP5370_EXT_WD_DISABLE
CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
CONFIG_DP_DDR_NUM_CTRLS
@@ -789,7 +715,6 @@ CONFIG_DRIVER_AX88796L
CONFIG_DRIVER_DM9000
CONFIG_DRIVER_EP93XX_MAC
CONFIG_DRIVER_ETHER
-CONFIG_DRIVER_NAND_BFIN
CONFIG_DRIVER_NE2000
CONFIG_DRIVER_NE2000_BASE
CONFIG_DRIVER_NE2000_CCR
@@ -852,7 +777,6 @@ CONFIG_DW_ALTDESCRIPTOR
CONFIG_DW_AXI_BURST_LEN
CONFIG_DW_GMAC_DEFAULT_DMA_PBL
CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
-CONFIG_DW_PORTS
CONFIG_DW_SERIAL
CONFIG_DW_UDC
CONFIG_DW_WDT_BASE
@@ -861,24 +785,7 @@ CONFIG_DYNAMIC_MMC_DEVNO
CONFIG_E1000_NO_NVM
CONFIG_E300
CONFIG_E5500
-CONFIG_EBCAW_VAL
CONFIG_EBC_PPC4xx_IBM_VER1
-CONFIG_EBIU_AMBCTL0_VAL
-CONFIG_EBIU_AMBCTL1_VAL
-CONFIG_EBIU_AMGCTL_VAL
-CONFIG_EBIU_DDRCTL0_VAL
-CONFIG_EBIU_DDRCTL1_VAL
-CONFIG_EBIU_DDRCTL2_VAL
-CONFIG_EBIU_DDRCTL3_VAL
-CONFIG_EBIU_DDRQUE_VAL
-CONFIG_EBIU_FCTL_VAL
-CONFIG_EBIU_MBSCTL_VAL
-CONFIG_EBIU_MODE_VAL
-CONFIG_EBIU_RSTCTL_VAL
-CONFIG_EBIU_SDBCTL_VAL
-CONFIG_EBIU_SDGCTL_VAL
-CONFIG_EBIU_SDRRC_VAL
-CONFIG_EBSZ_VAL
CONFIG_ECC
CONFIG_ECC_INIT_VIA_DDRCONTROLLER
CONFIG_ECC_MODE_MASK
@@ -940,7 +847,6 @@ CONFIG_ENV_FLAGS_LIST_DEFAULT
CONFIG_ENV_FLAGS_LIST_STATIC
CONFIG_ENV_FLASHBOOT
CONFIG_ENV_IS_EMBEDDED
-CONFIG_ENV_IS_EMBEDDED_IN_LDR
CONFIG_ENV_IS_IN_
CONFIG_ENV_IS_IN_DATAFLASH
CONFIG_ENV_IS_IN_EEPROM
@@ -1024,7 +930,6 @@ CONFIG_ETHER_ON_SCC
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
-CONFIG_EXCEPTION_DEFER
CONFIG_EXT4_WRITE
CONFIG_EXTRA_BOOTARGS
CONFIG_EXTRA_CLOCK
@@ -1310,7 +1215,6 @@ CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
CONFIG_HAS_FSL_XHCI_USB
CONFIG_HAS_POST
-CONFIG_HAS_VR
CONFIG_HAVE_ACPI_RESUME
CONFIG_HAVE_OWN_RESET
CONFIG_HCLK_FREQ
@@ -1479,7 +1383,6 @@ CONFIG_HVBOOT
CONFIG_HWCONFIG
CONFIG_HW_ENV_SETTINGS
CONFIG_HW_WATCHDOG
-CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
CONFIG_HW_WATCHDOG_TIMEOUT_MS
CONFIG_I2C
CONFIG_I2CFAST
@@ -1507,7 +1410,6 @@ CONFIG_I2C_RTC_ADDR
CONFIG_I2C_TIMEOUT
CONFIG_IBM_EMAC4_V4
CONFIG_ICACHE
-CONFIG_ICACHE_OFF
CONFIG_ICON
CONFIG_ICS307_REFCLK_HZ
CONFIG_IDE_8xx_DIRECT
@@ -1568,7 +1470,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE
CONFIG_IPAM390_GPIO_LED_GREEN
CONFIG_IPAM390_GPIO_LED_RED
CONFIG_IPEK01
-CONFIG_IPIPE
CONFIG_IPROC
CONFIG_IPUV3_CLK
CONFIG_IP_DEFRAG
@@ -1594,9 +1495,7 @@ CONFIG_JFFS2_PART_SIZE
CONFIG_JFFS2_SUMMARY
CONFIG_JRSTARTR_JR0
CONFIG_JTAG_CONSOLE
-CONFIG_JTAG_CONSOLE_TIMEOUT
CONFIG_JUPITER
-CONFIG_KALLSYMS
CONFIG_KASAN
CONFIG_KATMAI
CONFIG_KCLK_DIS
@@ -1762,8 +1661,6 @@ CONFIG_LIBATA
CONFIG_LIB_HW_RAND
CONFIG_LIB_UUID
CONFIG_LINUX
-CONFIG_LINUX_CMDLINE_ADDR
-CONFIG_LINUX_CMDLINE_SIZE
CONFIG_LINUX_RESET_VEC
CONFIG_LITTLETON_LCD
CONFIG_LMB
@@ -1802,11 +1699,6 @@ CONFIG_LPC_BASE
CONFIG_LPC_IO_BASE
CONFIG_LPUART
CONFIG_LPUART_32B_REG
-CONFIG_LQ035Q1_LCD_MODE
-CONFIG_LQ035Q1_SPI_BUS
-CONFIG_LQ035Q1_SPI_CS
-CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
CONFIG_LQ038J7DH53
CONFIG_LS102XA
CONFIG_LS102XA_STREAM_ID
@@ -1889,11 +1781,9 @@ CONFIG_MECP5123
CONFIG_MEMSIZE
CONFIG_MEMSIZE_IN_BYTES
CONFIG_MEMSIZE_MASK
-CONFIG_MEM_ADD_WDTH
CONFIG_MEM_HOLE_16M
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
-CONFIG_MEM_SIZE
CONFIG_MENUKEY
CONFIG_MENUPROMPT
CONFIG_MENU_SHOW
@@ -2113,7 +2003,6 @@ CONFIG_NAND_OMAP_ELM
CONFIG_NAND_OMAP_GPMC
CONFIG_NAND_OMAP_GPMC_PREFETCH
CONFIG_NAND_OMAP_GPMC_WSCFG
-CONFIG_NAND_PLAT
CONFIG_NAND_SECBOOT
CONFIG_NAND_SPL
CONFIG_NAND_U_BOOT
@@ -2162,7 +2051,6 @@ CONFIG_NS8382X
CONFIG_NS87308
CONFIG_NUM_DSP_CPUS
CONFIG_NUM_PAMU
-CONFIG_OCLK_DIV
CONFIG_ODROID_REV_AIN
CONFIG_OFF_PADCONF
CONFIG_OF_
@@ -2213,15 +2101,12 @@ CONFIG_PALMAS_SMPS7_FPWM
CONFIG_PALMAS_USB_SS_PWR
CONFIG_PANIC_HANG
CONFIG_PARAVIRT
-CONFIG_PATA_BFIN
CONFIG_PATI
CONFIG_PB1000
CONFIG_PB1100
CONFIG_PB1500
CONFIG_PB1X00
CONFIG_PCA953X
-CONFIG_PCA9564_BASE
-CONFIG_PCA9564_I2C
CONFIG_PCA9698
CONFIG_PCI1
CONFIG_PCI2
@@ -2342,10 +2227,6 @@ CONFIG_PLATINUM_TITANIUM
CONFIG_PLL
CONFIG_PLL1_CLK_FREQ
CONFIG_PLL1_DIV2_CLK_FREQ
-CONFIG_PLL_BYPASS
-CONFIG_PLL_CTL_VAL
-CONFIG_PLL_DIV_VAL
-CONFIG_PLL_LOCKCNT_VAL
CONFIG_PLU405
CONFIG_PM
CONFIG_PM9261
@@ -2384,10 +2265,7 @@ CONFIG_POST
CONFIG_POSTBOOTMENU
CONFIG_POST_ALT_LIST
CONFIG_POST_BSPEC1
-CONFIG_POST_BSPEC1_GPIO_LEDS
CONFIG_POST_BSPEC2
-CONFIG_POST_BSPEC2_GPIO_BUTTONS
-CONFIG_POST_BSPEC2_GPIO_NAMES
CONFIG_POST_BSPEC3
CONFIG_POST_BSPEC4
CONFIG_POST_BSPEC5
@@ -2559,7 +2437,6 @@ CONFIG_ROOTPATH
CONFIG_RSK7203
CONFIG_RSK7264
CONFIG_RSK7269
-CONFIG_RTC_BFIN
CONFIG_RTC_DS1307
CONFIG_RTC_DS1337
CONFIG_RTC_DS1338
@@ -2644,10 +2521,6 @@ CONFIG_SCIF_A
CONFIG_SCIF_CONSOLE
CONFIG_SCIF_EXT_CLOCK
CONFIG_SCIF_USE_EXT_CLK
-CONFIG_SCLK0_DIV
-CONFIG_SCLK1_DIV
-CONFIG_SCLK_DIV
-CONFIG_SCLK_HZ
CONFIG_SCSI
CONFIG_SCSI_AHCI
CONFIG_SCSI_AHCI_PLAT
@@ -2697,7 +2570,6 @@ CONFIG_SFIO
CONFIG_SF_DATAFLASH
CONFIG_SF_DEFAULT_BUS
CONFIG_SF_DEFAULT_CS
-CONFIG_SF_DEFAULT_HZ
CONFIG_SF_DEFAULT_MODE
CONFIG_SF_DEFAULT_SPEED
CONFIG_SF_DUAL_FLASH
@@ -2782,19 +2654,6 @@ CONFIG_SMC911X_BASE
CONFIG_SMC911X_NO_EEPROM
CONFIG_SMC_91111_EXT_PHY
CONFIG_SMC_AUTONEG_TIMEOUT
-CONFIG_SMC_B0CTL_VAL
-CONFIG_SMC_B0ETIM_VAL
-CONFIG_SMC_B0TIM_VAL
-CONFIG_SMC_B1CTL_VAL
-CONFIG_SMC_B1ETIM_VAL
-CONFIG_SMC_B1TIM_VAL
-CONFIG_SMC_B2CTL_VAL
-CONFIG_SMC_B2ETIM_VAL
-CONFIG_SMC_B2TIM_VAL
-CONFIG_SMC_B3CTL_VAL
-CONFIG_SMC_B3ETIM_VAL
-CONFIG_SMC_B3TIM_VAL
-CONFIG_SMC_GCTL_VAL
CONFIG_SMC_USE_32_BIT
CONFIG_SMC_USE_IOFUNCS
CONFIG_SMDK5420
@@ -2880,11 +2739,9 @@ CONFIG_SPEAR_USBBOOT
CONFIG_SPEAR_USBTTY
CONFIG_SPI
CONFIG_SPI_ADDR
-CONFIG_SPI_BAUD_INITBLOCK
CONFIG_SPI_BOOTING
CONFIG_SPI_CS_IS_VALID
CONFIG_SPI_DATAFLASH_WRITE_VERIFY
-CONFIG_SPI_FLASH_ALL
CONFIG_SPI_FLASH_ISSI
CONFIG_SPI_FLASH_QUAD
CONFIG_SPI_FLASH_SIZE
@@ -3010,7 +2867,6 @@ CONFIG_STACKBASE
CONFIG_STACKSIZE
CONFIG_STACKSIZE_FIQ
CONFIG_STACKSIZE_IRQ
-CONFIG_STAMP_CF
CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STATIC_BOARD_REV
CONFIG_STATIC_RELA
@@ -3153,7 +3009,6 @@ CONFIG_SYS_BCSR_ADDR
CONFIG_SYS_BCSR_BASE
CONFIG_SYS_BCSR_BASE_PHYS
CONFIG_SYS_BCSR_SIZE
-CONFIG_SYS_BD_INFO_ADDR
CONFIG_SYS_BD_REV
CONFIG_SYS_BFTIC3_BASE
CONFIG_SYS_BFTIC3_SIZE
@@ -3826,7 +3681,6 @@ CONFIG_SYS_FLASH1
CONFIG_SYS_FLASH1_BASE
CONFIG_SYS_FLASH1_BASE_PHYS
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH2_BASE
CONFIG_SYS_FLASHBOOT
CONFIG_SYS_FLASH_2ND_16BIT_DEV
CONFIG_SYS_FLASH_2ND_ADDR
@@ -4510,7 +4364,6 @@ CONFIG_SYS_I2C_8574A_ADDR1
CONFIG_SYS_I2C_8574A_ADDR2
CONFIG_SYS_I2C_8574_ADDR1
CONFIG_SYS_I2C_8574_ADDR2
-CONFIG_SYS_I2C_ADI
CONFIG_SYS_I2C_BASE
CONFIG_SYS_I2C_BASE0
CONFIG_SYS_I2C_BASE1
@@ -6534,9 +6387,6 @@ CONFIG_TZSW_RESERVED_DRAM_SIZE
CONFIG_T_SH7706LSR
CONFIG_UART_BASE
CONFIG_UART_BR_PRELIM
-CONFIG_UART_CONSOLE
-CONFIG_UART_CONSOLE_IS_JTAG
-CONFIG_UART_MEM
CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
CONFIG_UBIFS_SILENCE_MSG
@@ -6607,8 +6457,6 @@ CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_BIN_FIXUP
-CONFIG_USB_BLACKFIN
-CONFIG_USB_BLACKFIN_CLKIN
CONFIG_USB_BOOTING
CONFIG_USB_CABLE_CHECK
CONFIG_USB_CLOCK
@@ -6736,8 +6584,6 @@ CONFIG_U_QE
CONFIG_V38B
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
-CONFIG_VCO_HZ
-CONFIG_VCO_MULT
CONFIG_VCT_NOR
CONFIG_VE8313
CONFIG_VERY_BIG_RAM
@@ -6778,10 +6624,6 @@ CONFIG_VOL_MONITOR_INA220
CONFIG_VOL_MONITOR_IR36021_READ
CONFIG_VOL_MONITOR_IR36021_SET
CONFIG_VOM405
-CONFIG_VR_CTL_CLKBUF
-CONFIG_VR_CTL_FREQ
-CONFIG_VR_CTL_VAL
-CONFIG_VR_CTL_VLEV
CONFIG_VSC7385_ENET
CONFIG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 2/3] SPARC: Remove
2017-03-14 15:08 [U-Boot] [PATCH 1/3] Blackfin: Remove Tom Rini
@ 2017-03-14 15:08 ` Tom Rini
2017-04-06 16:23 ` [U-Boot] [U-Boot,2/3] " Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 3/3] OpenRISC: Remove Tom Rini
2017-04-06 16:23 ` [U-Boot] [U-Boot,1/3] Blackfin: Remove Tom Rini
2 siblings, 1 reply; 7+ messages in thread
From: Tom Rini @ 2017-03-14 15:08 UTC (permalink / raw)
To: u-boot
The SPARC architecture is currently unmaintained, remove.
Cc: Francois Retief <fgretief@spaceteq.co.za>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Kconfig | 2 +-
MAINTAINERS | 6 -
README | 1 -
arch/Kconfig | 5 -
arch/sparc/Kconfig | 70 --
arch/sparc/Makefile | 8 -
arch/sparc/config.mk | 25 -
arch/sparc/cpu/leon2/Makefile | 9 -
arch/sparc/cpu/leon2/cpu.c | 60 --
arch/sparc/cpu/leon2/cpu_init.c | 95 ---
arch/sparc/cpu/leon2/interrupts.c | 187 -----
arch/sparc/cpu/leon2/prom.c | 1032 --------------------------
arch/sparc/cpu/leon2/serial.c | 147 ----
arch/sparc/cpu/leon2/start.S | 695 ------------------
arch/sparc/cpu/leon3/Makefile | 10 -
arch/sparc/cpu/leon3/ambapp.c | 316 --------
arch/sparc/cpu/leon3/ambapp_low.S | 784 --------------------
arch/sparc/cpu/leon3/ambapp_low_c.S | 113 ---
arch/sparc/cpu/leon3/cpu.c | 113 ---
arch/sparc/cpu/leon3/cpu_init.c | 175 -----
arch/sparc/cpu/leon3/interrupts.c | 193 -----
arch/sparc/cpu/leon3/memcfg.c | 237 ------
arch/sparc/cpu/leon3/memcfg.h | 90 ---
arch/sparc/cpu/leon3/memcfg_low.S | 253 -------
arch/sparc/cpu/leon3/prom.c | 1067 ---------------------------
arch/sparc/cpu/leon3/serial.c | 189 -----
arch/sparc/cpu/leon3/start.S | 681 ------------------
arch/sparc/cpu/leon3/usb_uhci.c | 1195 -------------------------------
arch/sparc/cpu/leon3/usb_uhci.h | 167 -----
arch/sparc/cpu/u-boot.lds | 142 ----
arch/sparc/include/asm/arch-leon2/asi.h | 19 -
arch/sparc/include/asm/arch-leon3/asi.h | 19 -
arch/sparc/include/asm/asi.h | 15 -
arch/sparc/include/asm/asmmacro.h | 28 -
arch/sparc/include/asm/atomic.h | 12 -
arch/sparc/include/asm/bitops.h | 17 -
arch/sparc/include/asm/byteorder.h | 21 -
arch/sparc/include/asm/cache.h | 23 -
arch/sparc/include/asm/config.h | 21 -
arch/sparc/include/asm/global_data.h | 30 -
arch/sparc/include/asm/io.h | 96 ---
arch/sparc/include/asm/irq.h | 38 -
arch/sparc/include/asm/leon.h | 28 -
arch/sparc/include/asm/leon2.h | 222 ------
arch/sparc/include/asm/leon3.h | 35 -
arch/sparc/include/asm/linkage.h | 0
arch/sparc/include/asm/machines.h | 78 --
arch/sparc/include/asm/page.h | 28 -
arch/sparc/include/asm/posix_types.h | 125 ----
arch/sparc/include/asm/processor.h | 102 ---
arch/sparc/include/asm/prom.h | 283 --------
arch/sparc/include/asm/psr.h | 83 ---
arch/sparc/include/asm/ptrace.h | 167 -----
arch/sparc/include/asm/sections.h | 11 -
arch/sparc/include/asm/srmmu.h | 287 --------
arch/sparc/include/asm/stack.h | 148 ----
arch/sparc/include/asm/string.h | 41 --
arch/sparc/include/asm/types.h | 60 --
arch/sparc/include/asm/u-boot.h | 24 -
arch/sparc/include/asm/unaligned.h | 10 -
arch/sparc/include/asm/winmacro.h | 138 ----
arch/sparc/lib/Makefile | 9 -
arch/sparc/lib/bootm.c | 166 -----
arch/sparc/lib/cache.c | 17 -
arch/sparc/lib/interrupts.c | 68 --
cmd/Kconfig | 14 -
cmd/Makefile | 1 -
cmd/ambapp.c | 575 ---------------
cmd/bdinfo.c | 32 -
common/Kconfig | 2 +-
common/board_f.c | 20 +-
common/board_r.c | 31 +-
configs/gr_cpci_ax2000_defconfig | 9 -
configs/gr_ep2s60_defconfig | 9 -
configs/gr_xc3s_1500_defconfig | 9 -
configs/grsim_defconfig | 22 -
configs/grsim_leon2_defconfig | 17 -
disk/Kconfig | 5 +-
drivers/net/Makefile | 1 -
drivers/net/greth.c | 677 -----------------
drivers/net/greth.h | 81 ---
examples/standalone/stubs.c | 15 -
include/ambapp.h | 225 ------
include/ambapp_ids.h | 250 -------
include/configs/gr_cpci_ax2000.h | 340 ---------
include/configs/gr_ep2s60.h | 305 --------
include/configs/gr_xc3s_1500.h | 272 -------
include/configs/grsim.h | 314 --------
include/configs/grsim_leon2.h | 284 --------
include/grlib/apbuart.h | 47 --
include/grlib/gptimer.h | 34 -
include/grlib/greth.h | 87 ---
include/grlib/irqmp.h | 23 -
include/netdev.h | 1 -
94 files changed, 6 insertions(+), 14232 deletions(-)
delete mode 100644 arch/sparc/Kconfig
delete mode 100644 arch/sparc/Makefile
delete mode 100644 arch/sparc/config.mk
delete mode 100644 arch/sparc/cpu/leon2/Makefile
delete mode 100644 arch/sparc/cpu/leon2/cpu.c
delete mode 100644 arch/sparc/cpu/leon2/cpu_init.c
delete mode 100644 arch/sparc/cpu/leon2/interrupts.c
delete mode 100644 arch/sparc/cpu/leon2/prom.c
delete mode 100644 arch/sparc/cpu/leon2/serial.c
delete mode 100644 arch/sparc/cpu/leon2/start.S
delete mode 100644 arch/sparc/cpu/leon3/Makefile
delete mode 100644 arch/sparc/cpu/leon3/ambapp.c
delete mode 100644 arch/sparc/cpu/leon3/ambapp_low.S
delete mode 100644 arch/sparc/cpu/leon3/ambapp_low_c.S
delete mode 100644 arch/sparc/cpu/leon3/cpu.c
delete mode 100644 arch/sparc/cpu/leon3/cpu_init.c
delete mode 100644 arch/sparc/cpu/leon3/interrupts.c
delete mode 100644 arch/sparc/cpu/leon3/memcfg.c
delete mode 100644 arch/sparc/cpu/leon3/memcfg.h
delete mode 100644 arch/sparc/cpu/leon3/memcfg_low.S
delete mode 100644 arch/sparc/cpu/leon3/prom.c
delete mode 100644 arch/sparc/cpu/leon3/serial.c
delete mode 100644 arch/sparc/cpu/leon3/start.S
delete mode 100644 arch/sparc/cpu/leon3/usb_uhci.c
delete mode 100644 arch/sparc/cpu/leon3/usb_uhci.h
delete mode 100644 arch/sparc/cpu/u-boot.lds
delete mode 100644 arch/sparc/include/asm/arch-leon2/asi.h
delete mode 100644 arch/sparc/include/asm/arch-leon3/asi.h
delete mode 100644 arch/sparc/include/asm/asi.h
delete mode 100644 arch/sparc/include/asm/asmmacro.h
delete mode 100644 arch/sparc/include/asm/atomic.h
delete mode 100644 arch/sparc/include/asm/bitops.h
delete mode 100644 arch/sparc/include/asm/byteorder.h
delete mode 100644 arch/sparc/include/asm/cache.h
delete mode 100644 arch/sparc/include/asm/config.h
delete mode 100644 arch/sparc/include/asm/global_data.h
delete mode 100644 arch/sparc/include/asm/io.h
delete mode 100644 arch/sparc/include/asm/irq.h
delete mode 100644 arch/sparc/include/asm/leon.h
delete mode 100644 arch/sparc/include/asm/leon2.h
delete mode 100644 arch/sparc/include/asm/leon3.h
delete mode 100644 arch/sparc/include/asm/linkage.h
delete mode 100644 arch/sparc/include/asm/machines.h
delete mode 100644 arch/sparc/include/asm/page.h
delete mode 100644 arch/sparc/include/asm/posix_types.h
delete mode 100644 arch/sparc/include/asm/processor.h
delete mode 100644 arch/sparc/include/asm/prom.h
delete mode 100644 arch/sparc/include/asm/psr.h
delete mode 100644 arch/sparc/include/asm/ptrace.h
delete mode 100644 arch/sparc/include/asm/sections.h
delete mode 100644 arch/sparc/include/asm/srmmu.h
delete mode 100644 arch/sparc/include/asm/stack.h
delete mode 100644 arch/sparc/include/asm/string.h
delete mode 100644 arch/sparc/include/asm/types.h
delete mode 100644 arch/sparc/include/asm/u-boot.h
delete mode 100644 arch/sparc/include/asm/unaligned.h
delete mode 100644 arch/sparc/include/asm/winmacro.h
delete mode 100644 arch/sparc/lib/Makefile
delete mode 100644 arch/sparc/lib/bootm.c
delete mode 100644 arch/sparc/lib/cache.c
delete mode 100644 arch/sparc/lib/interrupts.c
delete mode 100644 cmd/ambapp.c
delete mode 100644 configs/gr_cpci_ax2000_defconfig
delete mode 100644 configs/gr_ep2s60_defconfig
delete mode 100644 configs/gr_xc3s_1500_defconfig
delete mode 100644 configs/grsim_defconfig
delete mode 100644 configs/grsim_leon2_defconfig
delete mode 100644 drivers/net/greth.c
delete mode 100644 drivers/net/greth.h
delete mode 100644 include/ambapp.h
delete mode 100644 include/ambapp_ids.h
delete mode 100644 include/configs/gr_cpci_ax2000.h
delete mode 100644 include/configs/gr_ep2s60.h
delete mode 100644 include/configs/gr_xc3s_1500.h
delete mode 100644 include/configs/grsim.h
delete mode 100644 include/configs/grsim_leon2.h
delete mode 100644 include/grlib/apbuart.h
delete mode 100644 include/grlib/gptimer.h
delete mode 100644 include/grlib/greth.h
delete mode 100644 include/grlib/irqmp.h
diff --git a/Kconfig b/Kconfig
index 81b4226463ae..af0a30355bf0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -283,7 +283,7 @@ config SYS_EXTRA_OPTIONS
new boards should not use this option.
config SYS_TEXT_BASE
- depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
+ depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
ARCH_ZYNQ
depends on !EFI_APP
diff --git a/MAINTAINERS b/MAINTAINERS
index c1aa594449fa..d628eb715aef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -408,12 +408,6 @@ S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/sh/
-SPARC
-#M: Francois Retief <fgretief@spaceteq.co.za>
-S: Orphaned (Since 2016-02)
-T: git git://git.denx.de/u-boot-sparc.git
-F: arch/sparc/
-
SPI
M: Jagan Teki <jagan@openedev.com>
S: Maintained
diff --git a/README b/README
index 486a71ebef6e..d0e1121a49b0 100644
--- a/README
+++ b/README
@@ -146,7 +146,6 @@ Directory Hierarchy:
/powerpc Files generic to PowerPC architecture
/sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
- /sparc Files generic to SPARC architecture
/x86 Files generic to x86 architecture
/api Machine/arch independent API for external apps
/board Board dependent files
diff --git a/arch/Kconfig b/arch/Kconfig
index 73e419223b5e..6750b5ddf640 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -73,10 +73,6 @@ config SH
bool "SuperH architecture"
select HAVE_PRIVATE_LIBGCC
-config SPARC
- bool "SPARC architecture"
- select CREATE_ARCH_SYMLINK
-
config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
@@ -164,6 +160,5 @@ source "arch/openrisc/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
-source "arch/sparc/Kconfig"
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
deleted file mode 100644
index 1d1347b16753..000000000000
--- a/arch/sparc/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-menu "SPARC architecture"
- depends on SPARC
-
-config LEON
- bool
-
-config LEON2
- bool
- select LEON
-
-config LEON3
- bool
- select LEON
-
-config SYS_SPARC_NWINDOWS
- int "Number of SPARC register windows"
- range 2 32
- default "8"
- help
- Specify the number of SPARC register windows implemented by this
- processor. A SPARC implementation can have from 2 to 32 windows.
- If unsure, choose 8.
-
-choice
- prompt "Board select"
- optional
-
-config TARGET_GRSIM_LEON2
- bool "GRSIM simulating a LEON2 board"
- select LEON2
-
-config TARGET_GR_CPCI_AX2000
- bool "Gaisler GR-CPCI-AX2000 board"
- select LEON3
-
-config TARGET_GR_EP2S60
- bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
- select LEON3
- help
- Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
- 96MHz) for Altera NIOS Development board Stratix II edition,
- with the FPGA device EP2S60.
-
-config TARGET_GR_XC3S_1500
- bool "Gaisler GR-XC3S-1500 spartan board"
- select LEON3
-
-config TARGET_GRSIM
- bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
- select LEON3
-
-endchoice
-
-config SYS_ARCH
- default "sparc"
-
-config SYS_CPU
- default "leon2" if LEON2
- default "leon3" if LEON3
-
-config SYS_VENDOR
- default "gaisler"
-
-source "board/gaisler/gr_cpci_ax2000/Kconfig"
-source "board/gaisler/gr_ep2s60/Kconfig"
-source "board/gaisler/gr_xc3s_1500/Kconfig"
-source "board/gaisler/grsim/Kconfig"
-source "board/gaisler/grsim_leon2/Kconfig"
-
-endmenu
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
deleted file mode 100644
index 2d4c9715a615..000000000000
--- a/arch/sparc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-head-y := arch/sparc/cpu/$(CPU)/start.o
-
-libs-y += arch/sparc/cpu/$(CPU)/
-libs-y += arch/sparc/lib/
diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk
deleted file mode 100644
index 43faad48ceb1..000000000000
--- a/arch/sparc/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2015
-# Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := sparc-linux-
-endif
-
-# This GCC compiler is known to work:
-# https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
-
-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \
- -T $(srctree)/examples/standalone/sparc.lds
-
-cpuflags-$(CONFIG_LEON2) := -mcpu=leon
-cpuflags-$(CONFIG_LEON3) := -mcpu=leon3
-
-PLATFORM_CPPFLAGS += $(cpuflags-y)
-
-PLATFORM_RELFLAGS += -fPIC
diff --git a/arch/sparc/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile
deleted file mode 100644
index 8c95ca56707a..000000000000
--- a/arch/sparc/cpu/leon2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu_init.o serial.o cpu.o interrupts.o prom.o
diff --git a/arch/sparc/cpu/leon2/cpu.c b/arch/sparc/cpu/leon2/cpu.c
deleted file mode 100644
index d044c3abc72f..000000000000
--- a/arch/sparc/cpu/leon2/cpu.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* CPU specific code for the LEON2 CPU
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void _reset_reloc(void);
-
-int checkcpu(void)
-{
- /* check LEON version here */
- printf("CPU: LEON2\n");
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-int print_cpuinfo(void)
-{
- printf("CPU: LEON2\n");
- return 0;
-}
-
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-void cpu_reset(void)
-{
- /* Interrupts off */
- disable_interrupts();
-
- /* jump to restart in flash */
- _reset_reloc();
-}
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- cpu_reset();
-
- return 1;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_GRETH
-int cpu_eth_init(bd_t *bis)
-{
- return greth_initialize(bis);
-}
-#endif
diff --git a/arch/sparc/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c
deleted file mode 100644
index 9dfb99cb0f76..000000000000
--- a/arch/sparc/cpu/leon2/cpu_init.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* Initializes CPU and basic hardware such as memory
- * controllers, IRQ controller and system timer 0.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/asi.h>
-#include <asm/leon.h>
-#include <asm/io.h>
-
-#include <config.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers.
- *
- * Run from FLASH/PROM:
- * - until memory controller is set up, only registers available
- * - no global variables available for writing
- * - constants available
- */
-
-void cpu_init_f(void)
-{
- LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
- /* initialize the IRQMP */
- leon2->Interrupt_Force = 0;
- leon2->Interrupt_Pending = 0;
- leon2->Interrupt_Clear = 0xfffe; /* clear all old pending interrupts */
- leon2->Interrupt_Mask = 0xfffe0000; /* mask all IRQs */
-
- /* cache */
-
- /* I/O port setup */
-#ifdef LEON2_IO_PORT_DIR
- leon2->PIO_Direction = LEON2_IO_PORT_DIR;
-#endif
-#ifdef LEON2_IO_PORT_DATA
- leon2->PIO_Data = LEON2_IO_PORT_DATA;
-#endif
-#ifdef LEON2_IO_PORT_INT
- leon2->PIO_Interrupt = LEON2_IO_PORT_INT;
-#else
- leon2->PIO_Interrupt = 0;
-#endif
-
- /* disable timers */
- leon2->Timer_Control_1 = leon2->Timer_Control_2 = 0;
-}
-
-int arch_cpu_init(void)
-{
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
-
-/*
- * initialize higher level parts of CPU
- */
-int cpu_init_r(void)
-{
- return 0;
-}
-
-/* initiate and setup timer0 to configured HZ. Base clock is 1MHz.
- */
-int timer_init(void)
-{
- LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS;
-
- /* initialize prescaler common to all timers to 1MHz */
- leon2->Scaler_Counter = leon2->Scaler_Reload =
- (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1;
-
- /* SYS_HZ ticks per second */
- leon2->Timer_Counter_1 = 0;
- leon2->Timer_Reload_1 = (CONFIG_SYS_TIMER_RATE / CONFIG_SYS_HZ) - 1;
- leon2->Timer_Control_1 = LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS |
- LEON2_TIMER_CTRL_LD;
-
- CONFIG_SYS_TIMER_COUNTER = (void *)&leon2->Timer_Counter_1;
- return 0;
-}
diff --git a/arch/sparc/cpu/leon2/interrupts.c b/arch/sparc/cpu/leon2/interrupts.c
deleted file mode 100644
index 602e4a67ba85..000000000000
--- a/arch/sparc/cpu/leon2/interrupts.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com
- *
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu at denx.de
- *
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/stack.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <asm/irq.h>
-
-#include <asm/leon.h>
-
-/* 15 normal irqs and a non maskable interrupt */
-#define NR_IRQS 15
-
-struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- unsigned int count;
-};
-
-static struct irq_action irq_handlers[NR_IRQS] = { {0}, };
-static int spurious_irq_cnt = 0;
-static int spurious_irq = 0;
-
-static inline unsigned int leon2_get_irqmask(unsigned int irq)
-{
- if ((irq < 0) || (irq >= NR_IRQS)) {
- return 0;
- } else {
- return (1 << irq);
- }
-}
-
-static void leon2_ic_disable(unsigned int irq)
-{
- unsigned int mask, pil;
- LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
- pil = intLock();
-
- /* get mask of interrupt */
- mask = leon2_get_irqmask(irq);
-
- /* set int level */
- leon2->Interrupt_Mask =
- SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) & (~mask);
-
- intUnlock(pil);
-}
-
-static void leon2_ic_enable(unsigned int irq)
-{
- unsigned int mask, pil;
- LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
- pil = intLock();
-
- /* get mask of interrupt */
- mask = leon2_get_irqmask(irq);
-
- /* set int level */
- leon2->Interrupt_Mask =
- SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) | mask;
-
- intUnlock(pil);
-}
-
-void handler_irq(int irq, struct pt_regs *regs)
-{
- if (irq_handlers[irq].handler) {
- if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
- ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
- ) {
- printf("handler_irq: bad handler: %x, irq number %d\n",
- (unsigned int)irq_handlers[irq].handler, irq);
- return;
- }
- irq_handlers[irq].handler(irq_handlers[irq].arg);
- irq_handlers[irq].count++;
- } else {
- spurious_irq_cnt++;
- spurious_irq = irq;
- }
-}
-
-void leon2_force_int(int irq)
-{
- LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
- if ((irq >= NR_IRQS) || (irq < 0))
- return;
- printf("Forcing interrupt %d\n", irq);
-
- leon2->Interrupt_Force =
- SPARC_NOCACHE_READ(&leon2->Interrupt_Force) | (1 << irq);
-}
-
-/****************************************************************************/
-
-int interrupt_init_cpu(void)
-{
- return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
-{
- if (irq < 0 || irq >= NR_IRQS) {
- printf("irq_install_handler: bad irq number %d\n", irq);
- return;
- }
-
- if (irq_handlers[irq].handler != NULL)
- printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
- (ulong) handler, (ulong) irq_handlers[irq].handler);
-
- if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
- ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
- ) {
- printf("irq_install_handler: bad handler: %x, irq number %d\n",
- (unsigned int)handler, irq);
- return;
- }
- irq_handlers[irq].handler = handler;
- irq_handlers[irq].arg = arg;
-
- /* enable irq on LEON2 hardware */
- leon2_ic_enable(irq);
-
-}
-
-void irq_free_handler(int irq)
-{
- if (irq < 0 || irq >= NR_IRQS) {
- printf("irq_free_handler: bad irq number %d\n", irq);
- return;
- }
-
- /* disable irq on LEON2 hardware */
- leon2_ic_disable(irq);
-
- irq_handlers[irq].handler = NULL;
- irq_handlers[irq].arg = NULL;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_IRQ)
-void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
- int irq;
- unsigned int pil = get_pil();
- printf("PIL level: %u\n\r", pil);
- printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
- spurious_irq_cnt, spurious_irq);
-
- puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
-
- for (irq = 0; irq < NR_IRQS; irq++) {
- if (irq_handlers[irq].handler != NULL) {
- printf("%02d %p %p %d\n", irq,
- irq_handlers[irq].handler,
- irq_handlers[irq].arg,
- irq_handlers[irq].count);
- }
- }
-}
-#endif
diff --git a/arch/sparc/cpu/leon2/prom.c b/arch/sparc/cpu/leon2/prom.c
deleted file mode 100644
index 7829e7abb2e8..000000000000
--- a/arch/sparc/cpu/leon2/prom.c
+++ /dev/null
@@ -1,1032 +0,0 @@
-/* prom.c - emulates a sparc v0 PROM for the linux kernel.
- *
- * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de>
- * Copyright (C) 2004 Stefan Holst <mail@s-holst.de>
- * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/prom.h>
-#include <asm/machines.h>
-#include <asm/srmmu.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/leon.h>
-
-#include <config.h>
-/*
-#define PRINT_ROM_VEC
-*/
-extern struct linux_romvec *kernel_arg_promvec;
-
-#define PROM_PGT __attribute__ ((__section__ (".prom.pgt")))
-#define PROM_TEXT __attribute__ ((__section__ (".prom.text")))
-#define PROM_DATA __attribute__ ((__section__ (".prom.data")))
-
-void *__prom_start_reloc; /* relocated prom_start address */
-
-/* for __va */
-extern int __prom_start;
-#define PAGE_OFFSET 0xf0000000
-#define phys_base CONFIG_SYS_SDRAM_BASE
-#define PROM_OFFS 8192
-#define PROM_SIZE_MASK (PROM_OFFS-1)
-#define __va(x) ( \
- (void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
- )
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
-
-struct property {
- char *name;
- char *value;
- int length;
-};
-
-struct node {
- int level;
- struct property *properties;
-};
-
-static void leon_reboot(char *bcommand);
-static void leon_halt(void);
-static int leon_nbputchar(int c);
-static int leon_nbgetchar(void);
-
-static int no_nextnode(int node);
-static int no_child(int node);
-static int no_proplen(int node, char *name);
-static int no_getprop(int node, char *name, char *value);
-static int no_setprop(int node, char *name, char *value, int len);
-static char *no_nextprop(int node, char *name);
-
-static struct property PROM_TEXT *find_property(int node, char *name);
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2);
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n);
-static void PROM_TEXT leon_reboot_physical(char *bcommand);
-
-void __inline__ leon_flush_cache_all(void)
-{
- __asm__ __volatile__(" flush ");
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-void __inline__ leon_flush_tlb_all(void)
-{
- leon_flush_cache_all();
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),
- "i"(ASI_MMUFLUSH):"memory");
-}
-
-typedef struct {
- unsigned int ctx_table[256];
- unsigned int pgd_table[256];
-} sparc_srmmu_setup;
-
-sparc_srmmu_setup srmmu_tables PROM_PGT = {
- {0},
- {0x1e,
- 0x10001e,
- 0x20001e,
- 0x30001e,
- 0x40001e,
- 0x50001e,
- 0x60001e,
- 0x70001e,
- 0x80001e,
- 0x90001e,
- 0xa0001e,
- 0xb0001e,
- 0xc0001e,
- 0xd0001e,
- 0xe0001e,
- 0xf0001e,
- 0x100001e,
- 0x110001e,
- 0x120001e,
- 0x130001e,
- 0x140001e,
- 0x150001e,
- 0x160001e,
- 0x170001e,
- 0x180001e,
- 0x190001e,
- 0x1a0001e,
- 0x1b0001e,
- 0x1c0001e,
- 0x1d0001e,
- 0x1e0001e,
- 0x1f0001e,
- 0x200001e,
- 0x210001e,
- 0x220001e,
- 0x230001e,
- 0x240001e,
- 0x250001e,
- 0x260001e,
- 0x270001e,
- 0x280001e,
- 0x290001e,
- 0x2a0001e,
- 0x2b0001e,
- 0x2c0001e,
- 0x2d0001e,
- 0x2e0001e,
- 0x2f0001e,
- 0x300001e,
- 0x310001e,
- 0x320001e,
- 0x330001e,
- 0x340001e,
- 0x350001e,
- 0x360001e,
- 0x370001e,
- 0x380001e,
- 0x390001e,
- 0x3a0001e,
- 0x3b0001e,
- 0x3c0001e,
- 0x3d0001e,
- 0x3e0001e,
- 0x3f0001e,
- 0x400001e,
- 0x410001e,
- 0x420001e,
- 0x430001e,
- 0x440001e,
- 0x450001e,
- 0x460001e,
- 0x470001e,
- 0x480001e,
- 0x490001e,
- 0x4a0001e,
- 0x4b0001e,
- 0x4c0001e,
- 0x4d0001e,
- 0x4e0001e,
- 0x4f0001e,
- 0x500001e,
- 0x510001e,
- 0x520001e,
- 0x530001e,
- 0x540001e,
- 0x550001e,
- 0x560001e,
- 0x570001e,
- 0x580001e,
- 0x590001e,
- 0x5a0001e,
- 0x5b0001e,
- 0x5c0001e,
- 0x5d0001e,
- 0x5e0001e,
- 0x5f0001e,
- 0x600001e,
- 0x610001e,
- 0x620001e,
- 0x630001e,
- 0x640001e,
- 0x650001e,
- 0x660001e,
- 0x670001e,
- 0x680001e,
- 0x690001e,
- 0x6a0001e,
- 0x6b0001e,
- 0x6c0001e,
- 0x6d0001e,
- 0x6e0001e,
- 0x6f0001e,
- 0x700001e,
- 0x710001e,
- 0x720001e,
- 0x730001e,
- 0x740001e,
- 0x750001e,
- 0x760001e,
- 0x770001e,
- 0x780001e,
- 0x790001e,
- 0x7a0001e,
- 0x7b0001e,
- 0x7c0001e,
- 0x7d0001e,
- 0x7e0001e,
- 0x7f0001e,
- 0x800001e,
- 0x810001e,
- 0x820001e,
- 0x830001e,
- 0x840001e,
- 0x850001e,
- 0x860001e,
- 0x870001e,
- 0x880001e,
- 0x890001e,
- 0x8a0001e,
- 0x8b0001e,
- 0x8c0001e,
- 0x8d0001e,
- 0x8e0001e,
- 0x8f0001e,
- 0x900001e,
- 0x910001e,
- 0x920001e,
- 0x930001e,
- 0x940001e,
- 0x950001e,
- 0x960001e,
- 0x970001e,
- 0x980001e,
- 0x990001e,
- 0x9a0001e,
- 0x9b0001e,
- 0x9c0001e,
- 0x9d0001e,
- 0x9e0001e,
- 0x9f0001e,
- 0xa00001e,
- 0xa10001e,
- 0xa20001e,
- 0xa30001e,
- 0xa40001e,
- 0xa50001e,
- 0xa60001e,
- 0xa70001e,
- 0xa80001e,
- 0xa90001e,
- 0xaa0001e,
- 0xab0001e,
- 0xac0001e,
- 0xad0001e,
- 0xae0001e,
- 0xaf0001e,
- 0xb00001e,
- 0xb10001e,
- 0xb20001e,
- 0xb30001e,
- 0xb40001e,
- 0xb50001e,
- 0xb60001e,
- 0xb70001e,
- 0xb80001e,
- 0xb90001e,
- 0xba0001e,
- 0xbb0001e,
- 0xbc0001e,
- 0xbd0001e,
- 0xbe0001e,
- 0xbf0001e,
- 0xc00001e,
- 0xc10001e,
- 0xc20001e,
- 0xc30001e,
- 0xc40001e,
- 0xc50001e,
- 0xc60001e,
- 0xc70001e,
- 0xc80001e,
- 0xc90001e,
- 0xca0001e,
- 0xcb0001e,
- 0xcc0001e,
- 0xcd0001e,
- 0xce0001e,
- 0xcf0001e,
- 0xd00001e,
- 0xd10001e,
- 0xd20001e,
- 0xd30001e,
- 0xd40001e,
- 0xd50001e,
- 0xd60001e,
- 0xd70001e,
- 0xd80001e,
- 0xd90001e,
- 0xda0001e,
- 0xdb0001e,
- 0xdc0001e,
- 0xdd0001e,
- 0xde0001e,
- 0xdf0001e,
- 0xe00001e,
- 0xe10001e,
- 0xe20001e,
- 0xe30001e,
- 0xe40001e,
- 0xe50001e,
- 0xe60001e,
- 0xe70001e,
- 0xe80001e,
- 0xe90001e,
- 0xea0001e,
- 0xeb0001e,
- 0xec0001e,
- 0xed0001e,
- 0xee0001e,
- 0xef0001e,
- 0x400001e /* default */
- }
-};
-
-/* a self contained prom info structure */
-struct leon_reloc_func {
- struct property *(*find_property) (int node, char *name);
- int (*strcmp) (char *s1, char *s2);
- void *(*memcpy) (void *dest, const void *src, size_t n);
- void (*reboot_physical) (char *cmd);
-};
-
-struct leon_prom_info {
- int freq_khz;
- int leon_nctx;
- int mids[32];
- int baudrates[2];
- struct leon_reloc_func reloc_funcs;
- struct property root_properties[4];
- struct property cpu_properties[7];
-#undef CPUENTRY
-#define CPUENTRY(idx) struct property cpu_properties##idx[4]
- CPUENTRY(1);
- CPUENTRY(2);
- CPUENTRY(3);
- CPUENTRY(4);
- CPUENTRY(5);
- CPUENTRY(6);
- CPUENTRY(7);
- CPUENTRY(8);
- CPUENTRY(9);
- CPUENTRY(10);
- CPUENTRY(11);
- CPUENTRY(12);
- CPUENTRY(13);
- CPUENTRY(14);
- CPUENTRY(15);
- CPUENTRY(16);
- CPUENTRY(17);
- CPUENTRY(18);
- CPUENTRY(19);
- CPUENTRY(20);
- CPUENTRY(21);
- CPUENTRY(22);
- CPUENTRY(23);
- CPUENTRY(24);
- CPUENTRY(25);
- CPUENTRY(26);
- CPUENTRY(27);
- CPUENTRY(28);
- CPUENTRY(29);
- CPUENTRY(30);
- CPUENTRY(31);
- struct idprom idprom;
- struct linux_nodeops nodeops;
- struct linux_mlist_v0 *totphys_p;
- struct linux_mlist_v0 totphys;
- struct linux_mlist_v0 *avail_p;
- struct linux_mlist_v0 avail;
- struct linux_mlist_v0 *prommap_p;
- void (*synchook) (void);
- struct linux_arguments_v0 *bootargs_p;
- struct linux_arguments_v0 bootargs;
- struct linux_romvec romvec;
- struct node nodes[35];
- char s_device_type[12];
- char s_cpu[4];
- char s_mid[4];
- char s_idprom[7];
- char s_compatability[14];
- char s_leon2[6];
- char s_mmu_nctx[9];
- char s_frequency[16];
- char s_uart1_baud[11];
- char s_uart2_baud[11];
- char arg[256];
-};
-
-/* static prom info */
-static struct leon_prom_info PROM_DATA spi = {
- CONFIG_SYS_CLK_FREQ / 1000,
- 256,
- {
-#undef CPUENTRY
-#define CPUENTRY(idx) idx
- CPUENTRY(0),
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- 31},
- {38400, 38400},
- {
- __va(find_property),
- __va(leon_strcmp),
- __va(leon_memcpy),
- __phy(leon_reboot_physical),
- },
- {
- {__va(spi.s_device_type), __va(spi.s_idprom), 4},
- {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)},
- {__va(spi.s_compatability), __va(spi.s_leon2), 5},
- {NULL, NULL, -1}
- },
- {
- {__va(spi.s_device_type), __va(spi.s_cpu), 4},
- {__va(spi.s_mid), __va(&spi.mids[0]), 4},
- {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4},
- {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},
- {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4},
- {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4},
- {NULL, NULL, -1}
- },
-#undef CPUENTRY
-#define CPUENTRY(idx) \
- { /* cpu_properties */ \
- {__va(spi.s_device_type), __va(spi.s_cpu), 4}, \
- {__va(spi.s_mid), __va(&spi.mids[idx]), 4}, \
- {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, \
- {NULL, NULL, -1} \
- }
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- CPUENTRY(31),
- {
- 0x01, /* format */
- M_LEON2 | M_LEON2_SOC, /* machine type */
- {0, 0, 0, 0, 0, 0}, /* eth */
- 0, /* date */
- 0, /* sernum */
- 0, /* checksum */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* reserved */
- },
- {
- __va(no_nextnode),
- __va(no_child),
- __va(no_proplen),
- __va(no_getprop),
- __va(no_setprop),
- __va(no_nextprop)
- },
- __va(&spi.totphys),
- {
- NULL,
- (char *)CONFIG_SYS_SDRAM_BASE,
- 0,
- },
- __va(&spi.avail),
- {
- NULL,
- (char *)CONFIG_SYS_SDRAM_BASE,
- 0,
- },
- NULL, /* prommap_p */
- NULL,
- __va(&spi.bootargs),
- {
- {NULL, __va(spi.arg), NULL /*... */ },
- /*... */
- },
- {
- 0,
- 0, /* sun4c v0 prom */
- 0, 0,
- {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)},
- __va(&spi.nodeops),
- NULL, {NULL /* ... */ },
- NULL, NULL,
- NULL, NULL, /* pv_getchar, pv_putchar */
- __va(leon_nbgetchar), __va(leon_nbputchar),
- NULL,
- __va(leon_reboot),
- NULL,
- NULL,
- NULL,
- __va(leon_halt),
- __va(&spi.synchook),
- {NULL},
- __va(&spi.bootargs_p)
- /*... */
- },
- {
- {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ },
- {0, __va(spi.root_properties)},
- /* cpu 0, must be spi.nodes[2] see leon_prom_init() */
- {1, __va(spi.cpu_properties)},
-
-#undef CPUENTRY
-#define CPUENTRY(idx) \
- {1, __va(spi.cpu_properties##idx) } /* cpu <idx> */
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- CPUENTRY(31),
- {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }
- },
- "device_type",
- "cpu",
- "mid",
- "idprom",
- "compatability",
- "leon2",
- "mmu-nctx",
- "clock-frequency",
- "uart1_baud",
- "uart2_baud",
- CONFIG_DEFAULT_KERNEL_COMMAND_LINE
-};
-
-/* from arch/sparc/kernel/setup.c */
-#define RAMDISK_LOAD_FLAG 0x4000
-extern unsigned short root_flags;
-extern unsigned short root_dev;
-extern unsigned short ram_flags;
-extern unsigned int sparc_ramdisk_image;
-extern unsigned int sparc_ramdisk_size;
-extern int root_mountflags;
-
-extern char initrd_end, initrd_start;
-
-/* Reboot the CPU = jump to beginning of flash again.
- *
- * Make sure that all function are inlined here.
- */
-static void PROM_TEXT leon_reboot(char *bcommand)
-{
- register char *arg = bcommand;
- void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd);
-
- /* get physical address */
- struct leon_prom_info *pspi =
- (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- unsigned int *srmmu_ctx_table;
-
- /* Turn of Interrupts */
- set_pil(0xf);
-
- /* Set kernel's context, context zero */
- srmmu_set_context(0);
-
- /* Get physical address of the MMU shutdown routine */
- reboot_physical = (void *)
- SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical);
-
- /* Now that we know the physical address of the function
- * we can make the MMU allow jumping to it.
- */
- srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr();
-
- srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table);
-
- /* get physical address of kernel's context table (assume ptd) */
- srmmu_ctx_table = (unsigned int *)
- (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4);
-
- /* enable access to physical address of MMU shutdown function */
- SPARC_BYPASS_WRITE(&srmmu_ctx_table
- [((unsigned int)reboot_physical) >> 24],
- (((unsigned int)reboot_physical & 0xff000000) >> 4) |
- 0x1e);
-
- /* flush TLB cache */
- leon_flush_tlb_all();
-
- /* flash instruction & data cache */
- sparc_icache_flush_all();
- sparc_dcache_flush_all();
-
- /* jump to physical address function
- * so that when the MMU is disabled
- * we can continue to execute
- */
- reboot_physical(arg);
-}
-
-static void PROM_TEXT leon_reboot_physical(char *bcommand)
-{
- void __attribute__ ((noreturn)) (*reset) (void);
-
- /* Turn off MMU */
- srmmu_set_mmureg(0);
-
- /* Hardcoded start address */
- reset = CONFIG_SYS_MONITOR_BASE;
-
- /* flush data cache */
- sparc_dcache_flush_all();
-
- /* flush instruction cache */
- sparc_icache_flush_all();
-
- /* Jump to start in Flash */
- reset();
-}
-
-static void PROM_TEXT leon_halt(void)
-{
- while (1) ;
-}
-
-/* get single char, don't care for blocking*/
-static int PROM_TEXT leon_nbgetchar(void)
-{
- return -1;
-}
-
-/* put single char, don't care for blocking*/
-static int PROM_TEXT leon_nbputchar(int c)
-{
- LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
-
- /***** put char in buffer... ***********
- * Make sure all functions are inline! *
- ***************************************/
-
- /* Wait for last character to go. */
- while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1)
- & LEON2_UART_STAT_THE)) ;
-
- /* Send data */
- SPARC_BYPASS_WRITE(&leon2->UART_Channel_1, c);
-
- /* Wait for data to be sent */
- while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1)
- & LEON2_UART_STAT_TSE)) ;
-
- return 0;
-}
-
-/* node ops */
-
-/*#define nodes ((struct node *)__va(&pspi->nodes))*/
-#define nodes ((struct node *)(pspi->nodes))
-
-static int PROM_TEXT no_nextnode(int node)
-{
- /* get physical address */
- struct leon_prom_info *pspi =
- (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (nodes[node].level == nodes[node + 1].level)
- return node + 1;
- return -1;
-}
-
-static int PROM_TEXT no_child(int node)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (nodes[node].level == nodes[node + 1].level - 1)
- return node + 1;
- return -1;
-}
-
-static struct property PROM_TEXT *find_property(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = &nodes[node].properties[0];
- while (prop && prop->name) {
- if (pspi->reloc_funcs.strcmp(prop->name, name) == 0)
- return prop;
- prop++;
- }
- return NULL;
-}
-
-static int PROM_TEXT no_proplen(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = pspi->reloc_funcs.find_property(node, name);
- if (prop)
- return prop->length;
- return -1;
-}
-
-static int PROM_TEXT no_getprop(int node, char *name, char *value)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = pspi->reloc_funcs.find_property(node, name);
- if (prop) {
- pspi->reloc_funcs.memcpy(value, prop->value, prop->length);
- return 1;
- }
- return -1;
-}
-
-static int PROM_TEXT no_setprop(int node, char *name, char *value, int len)
-{
- return -1;
-}
-
-static char PROM_TEXT *no_nextprop(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
- struct property *prop;
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (!name || !name[0])
- return nodes[node].properties[0].name;
-
- prop = pspi->reloc_funcs.find_property(node, name);
- if (prop)
- return prop[1].name;
- return NULL;
-}
-
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2)
-{
- register char result;
-
- while (1) {
- result = *s1 - *s2;
- if (result || !*s1)
- break;
- s2++;
- s1++;
- }
-
- return result;
-}
-
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n)
-{
- char *dst = (char *)dest, *source = (char *)src;
-
- while (n--) {
- *dst = *source;
- dst++;
- source++;
- }
- return dest;
-}
-
-#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp))
-
-void leon_prom_init(struct leon_prom_info *pspi)
-{
- unsigned long i;
- unsigned char cksum, *ptr;
- char *addr_str, *end;
- unsigned long sp;
- GETREGSP(sp);
-
- pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
-
- /* Set Available main memory size */
- pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
- pspi->avail.num_bytes = pspi->totphys.num_bytes;
-
-#undef nodes
- pspi->nodes[3].level = -1;
- pspi->nodes[3].properties = __va(spi.root_properties + 3);
-
- /* Set Ethernet MAC address from environment */
- if ((addr_str = getenv("ethaddr")) != NULL) {
- for (i = 0; i < 6; i++) {
- pspi->idprom.id_ethaddr[i] = addr_str ?
- simple_strtoul(addr_str, &end, 16) : 0;
- if (addr_str) {
- addr_str = (*end) ? end + 1 : end;
- }
- }
- } else {
- /* HW Address not found in environment,
- * Set default HW address
- */
- pspi->idprom.id_ethaddr[0] = 0;
- pspi->idprom.id_ethaddr[1] = 0;
- pspi->idprom.id_ethaddr[2] = 0;
- pspi->idprom.id_ethaddr[3] = 0;
- pspi->idprom.id_ethaddr[4] = 0;
- pspi->idprom.id_ethaddr[5] = 0;
- }
-
- ptr = (unsigned char *)&pspi->idprom;
- for (i = cksum = 0; i <= 0x0E; i++)
- cksum ^= *ptr++;
- pspi->idprom.id_cksum = cksum;
-}
-
-static inline void set_cache(unsigned long regval)
-{
- asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
-}
-
-extern unsigned short bss_start, bss_end;
-
-/* mark as section .img.main.text, to be referenced in linker script */
-int prom_init(void)
-{
- struct leon_prom_info *pspi = (void *)
- ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
-
- /* disable mmu */
- srmmu_set_mmureg(0x00000000);
- __asm__ __volatile__("flush\n\t");
-
- /* init prom info struct */
- leon_prom_init(pspi);
-
- kernel_arg_promvec = &pspi->romvec;
-#ifdef PRINT_ROM_VEC
- printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec));
-#endif
- return 0;
-}
-
-/* Copy current kernel boot argument to ROMvec */
-void prepare_bootargs(char *bootargs)
-{
- struct leon_prom_info *pspi;
- char *src, *dst;
- int left;
-
- /* if no bootargs set, skip copying ==> default bootline */
- if (bootargs && (*bootargs != '\0')) {
- pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
- CONFIG_SYS_PROM_OFFSET);
- src = bootargs;
- dst = &pspi->arg[0];
- left = 255; /* max len */
- while (*src && left > 0) {
- *dst++ = *src++;
- left--;
- }
- /* terminate kernel command line string */
- *dst = 0;
- }
-}
-
-void srmmu_init_cpu(unsigned int entry)
-{
- sparc_srmmu_setup *psrmmu_tables = (void *)
- ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
- CONFIG_SYS_PROM_OFFSET);
-
- /* Make context 0 (kernel's context) point
- * to our prepared memory mapping
- */
-#define PTD 1
- psrmmu_tables->ctx_table[0] =
- ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD;
-
- /* Set virtual kernel address 0xf0000000
- * to SRAM/SDRAM address.
- * Make it READ/WRITE/EXEC to SuperUser
- */
-#define PTE 2
-#define ACC_SU_ALL 0x1c
- psrmmu_tables->pgd_table[0xf0] =
- (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf1] =
- ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf2] =
- ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf3] =
- ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf4] =
- ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf5] =
- ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf6] =
- ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf7] =
- ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
-
- /* convert rom vec pointer to virtual address */
- kernel_arg_promvec = (struct linux_romvec *)
- (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000);
-
- /* Set Context pointer to point to context table
- * 256 contexts supported.
- */
- srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]);
-
- /* Set kernel's context, context zero */
- srmmu_set_context(0);
-
- /* Invalidate all Cache */
- __asm__ __volatile__("flush\n\t");
-
- srmmu_set_mmureg(0x00000001);
- leon_flush_tlb_all();
- leon_flush_cache_all();
-}
diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c
deleted file mode 100644
index 460abd1d9f5e..000000000000
--- a/arch/sparc/cpu/leon2/serial.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* GRLIB APBUART Serial controller driver
- *
- * (C) Copyright 2008, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned leon2_serial_calc_scaler(unsigned freq, unsigned baud)
-{
- return (((freq*10) / (baud*8)) - 5) / 10;
-}
-
-static int leon2_serial_init(void)
-{
- LEON2_regs *leon2 = (LEON2_regs *)LEON2_PREGS;
- LEON2_Uart_regs *regs;
- unsigned int tmp;
-
-#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1
- regs = (LEON2_Uart_regs *)&leon2->UART_Channel_1;
-#else
- regs = (LEON2_Uart_regs *)&leon2->UART_Channel_2;
-#endif
-
- /* Set scaler / baud rate */
- tmp = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, CONFIG_BAUDRATE);
- writel(tmp, ®s->UART_Scaler);
-
- /* Let bit 11 be unchanged (debug bit for GRMON) */
- tmp = readl(®s->UART_Control) & LEON2_UART_CTRL_DBG;
- tmp |= (LEON2_UART1_LOOPBACK_ENABLE << 7);
- tmp |= (LEON2_UART1_FLOWCTRL_ENABLE << 6);
- tmp |= (LEON2_UART1_PARITY_ENABLE << 5);
- tmp |= (LEON2_UART1_ODDPAR_ENABLE << 4);
- /* Receiver & transmitter enable */
- tmp |= (LEON2_UART_CTRL_RE | LEON2_UART_CTRL_TE);
- writel(tmp, ®s->UART_Control);
-
- gd->arch.uart = regs;
- return 0;
-}
-
-static inline LEON2_Uart_regs *leon2_get_uart_regs(void)
-{
- LEON2_Uart_regs *uart = gd->arch.uart;
-
- return uart;
-}
-
-static void leon2_serial_putc_raw(const char c)
-{
- LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
- if (!uart)
- return;
-
- /* Wait for last character to go. */
- while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_THE))
- WATCHDOG_RESET();
-
- /* Send data */
- writel(c, &uart->UART_Channel);
-
-#ifdef LEON_DEBUG
- /* Wait for data to be sent */
- while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_TSE))
- WATCHDOG_RESET();
-#endif
-}
-
-static void leon2_serial_putc(const char c)
-{
- if (c == '\n')
- leon2_serial_putc_raw('\r');
-
- leon2_serial_putc_raw(c);
-}
-
-static int leon2_serial_getc(void)
-{
- LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
- if (!uart)
- return 0;
-
- /* Wait for a character to arrive. */
- while (!(readl(&uart->UART_Status) & LEON2_UART_STAT_DR))
- WATCHDOG_RESET();
-
- /* Read character data */
- return readl(&uart->UART_Channel);
-}
-
-static int leon2_serial_tstc(void)
-{
- LEON2_Uart_regs *uart = leon2_get_uart_regs();
-
- if (!uart)
- return 0;
-
- return readl(&uart->UART_Status) & LEON2_UART_STAT_DR;
-}
-
-static void leon2_serial_setbrg(void)
-{
- LEON2_Uart_regs *uart = leon2_get_uart_regs();
- unsigned int scaler;
-
- if (!uart)
- return;
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
-
- scaler = leon2_serial_calc_scaler(CONFIG_SYS_CLK_FREQ, gd->baudrate);
-
- writel(scaler, &uart->UART_Scaler);
-}
-
-static struct serial_device leon2_serial_drv = {
- .name = "leon2_serial",
- .start = leon2_serial_init,
- .stop = NULL,
- .setbrg = leon2_serial_setbrg,
- .putc = leon2_serial_putc,
- .puts = default_serial_puts,
- .getc = leon2_serial_getc,
- .tstc = leon2_serial_tstc,
-};
-
-void leon2_serial_initialize(void)
-{
- serial_register(&leon2_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &leon2_serial_drv;
-}
diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S
deleted file mode 100644
index 1b404da36291..000000000000
--- a/arch/sparc/cpu/leon2/start.S
+++ /dev/null
@@ -1,695 +0,0 @@
-/* This is where the SPARC/LEON3 starts
- *
- * Copyright (C) 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asmmacro.h>
-#include <asm/winmacro.h>
-#include <asm/psr.h>
-#include <asm/stack.h>
-#include <asm/leon.h>
-
-/* Entry for traps which jump to a programmer-specified trap handler. */
-#define TRAPR(H) \
- wr %g0, 0xfe0, %psr; \
- mov %g0, %tbr; \
- ba (H); \
- mov %g0, %wim;
-
-#define TRAP(H) \
- mov %psr, %l0; \
- ba (H); \
- nop; nop;
-
-#define TRAPI(ilevel) \
- mov ilevel, %l7; \
- mov %psr, %l0; \
- b _irq_entry; \
- mov %wim, %l3
-
-/* Unexcpected trap will halt the processor by forcing it to error state */
-#undef BAD_TRAP
-#define BAD_TRAP ta 0; nop; nop; nop;
-
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
-
-#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */
-#define WIM_INIT 2
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-/* Macros to load address into a register. Uses GOT table for PIC */
-#ifdef __PIC__
-
-#define SPARC_PIC_THUNK_CALL(reg) \
- sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %##reg; \
- call __sparc_get_pc_thunk.reg; \
- add %##reg, %pc10(_GLOBAL_OFFSET_TABLE_+4), %##reg;
-
-#define SPARC_LOAD_ADDRESS(sym, got, reg) \
- sethi %gdop_hix22(sym), %##reg; \
- xor %##reg, %gdop_lox10(sym), %##reg; \
- ld [%##got + %##reg], %##reg, %gdop(sym);
-
-#else
-
-#define SPARC_PIC_THUNK_CALL(reg)
-#define SPARC_LOAD_ADDRESS(sym, got, tmp) \
- set sym, %##reg;
-
-#endif
-
-#define STACK_ALIGN 8
-#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
-
- .section ".start", "ax"
- .globl _start, start, _trap_table
- .globl _irq_entry, nmi_trap
- .globl _reset_reloc
-
-/* at address 0
- * Hardware traps
- */
-start:
-_start:
-_trap_table:
- TRAPR(_hardreset); ! 00 reset trap
- BAD_TRAP; ! 01 instruction_access_exception
- BAD_TRAP; ! 02 illegal_instruction
- BAD_TRAP; ! 03 priveleged_instruction
- BAD_TRAP; ! 04 fp_disabled
- TRAP(_window_overflow); ! 05 window_overflow
- TRAP(_window_underflow); ! 06 window_underflow
- BAD_TRAP; ! 07 Memory Address Not Aligned
- BAD_TRAP; ! 08 Floating Point Exception
- BAD_TRAP; ! 09 Data Miss Exception
- BAD_TRAP; ! 0a Tagged Instruction Ovrflw
- BAD_TRAP; ! 0b Watchpoint Detected
- BAD_TRAP; ! 0c
- BAD_TRAP; ! 0d
- BAD_TRAP; ! 0e
- BAD_TRAP; ! 0f
- BAD_TRAP; ! 10
- TRAPI(1); ! 11 IRQ level 1
- TRAPI(2); ! 12 IRQ level 2
- TRAPI(3); ! 13 IRQ level 3
- TRAPI(4); ! 14 IRQ level 4
- TRAPI(5); ! 15 IRQ level 5
- TRAPI(6); ! 16 IRQ level 6
- TRAPI(7); ! 17 IRQ level 7
- TRAPI(8); ! 18 IRQ level 8
- TRAPI(9); ! 19 IRQ level 9
- TRAPI(10); ! 1a IRQ level 10
- TRAPI(11); ! 1b IRQ level 11
- TRAPI(12); ! 1c IRQ level 12
- TRAPI(13); ! 1d IRQ level 13
- TRAPI(14); ! 1e IRQ level 14
- TRAP(_nmi_trap); ! 1f IRQ level 15 /
- ! NMI (non maskable interrupt)
- BAD_TRAP; ! 20 r_register_access_error
- BAD_TRAP; ! 21 instruction access error
- BAD_TRAP; ! 22
- BAD_TRAP; ! 23
- BAD_TRAP; ! 24 co-processor disabled
- BAD_TRAP; ! 25 uniplemented FLUSH
- BAD_TRAP; ! 26
- BAD_TRAP; ! 27
- BAD_TRAP; ! 28 co-processor exception
- BAD_TRAP; ! 29 data access error
- BAD_TRAP; ! 2a division by zero
- BAD_TRAP; ! 2b data store error
- BAD_TRAP; ! 2c data access MMU miss
- BAD_TRAP; ! 2d
- BAD_TRAP; ! 2e
- BAD_TRAP; ! 2f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f
-
- /* implementaion dependent */
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f
-
- /* Software traps, not handled */
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80-83
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84-87
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88-8b
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8c-8f
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90-93
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94-97
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98-9b
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9c-9f
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a0-a3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a4-a7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a8-ab
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ac-af
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b0-b3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b4-b7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b8-bb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! bc-bf
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c0-c3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c4-c7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c8-cb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! cc-cf
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d0-d3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d4-d7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d8-db
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! dc-df
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e0-e3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e4-e7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e8-eb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ec-ef
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f0-f3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff
-
- .section ".text"
- .align 4
-
-_hardreset:
-1000:
- flush
- nop
- nop
- nop
-
- /* Init Cache */
- set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
- set 0x0081000f, %g2
- st %g2, [%g1]
-
- mov %g0, %y
- clr %g1
- clr %g2
- clr %g3
- clr %g4
- clr %g5
- clr %g6
- clr %g7
-
- mov %asr17, %g3
- and %g3, 0x1f, %g3
-clear_window:
- mov %g0, %l0
- mov %g0, %l1
- mov %g0, %l2
- mov %g0, %l3
- mov %g0, %l4
- mov %g0, %l5
- mov %g0, %l6
- mov %g0, %l7
- mov %g0, %o0
- mov %g0, %o1
- mov %g0, %o2
- mov %g0, %o3
- mov %g0, %o4
- mov %g0, %o5
- mov %g0, %o6
- mov %g0, %o7
- subcc %g3, 1, %g3
- bge clear_window
- save
-
-leon2_init:
- /* LEON2 Register Base in g1 */
- set LEON2_PREGS, %g1
-
-leon2_init_cache:
- /* Set Cache control register */
- set 0x1000f, %g2
- st %g2, [%g1 + 0x14]
-
-leon2_init_clear:
-
- /* Clear LEON2 registers */
- st %g0, [%g1 + LEON2_ECTRL]
- st %g0, [%g1 + LEON2_IMASK]
- st %g0, [%g1 + LEON2_IPEND]
- st %g0, [%g1 + LEON2_IFORCE]
- st %g0, [%g1 + LEON2_ICLEAR]
- st %g0, [%g1 + LEON2_IOREG]
- st %g0, [%g1 + LEON2_IODIR]
- st %g0, [%g1 + LEON2_IOICONF]
- st %g0, [%g1 + LEON2_UCTRL0]
- st %g0, [%g1 + LEON2_UCTRL1]
-
-leon2_init_ioport:
- /* I/O port initialization */
- set 0xaa00, %g2
- st %g2, [%g1 + LEON2_IOREG]
-
-leon2_init_mctrl:
-
- /* memory config register 1 */
- set CONFIG_SYS_GRLIB_MEMCFG1, %g2
- ld [%g1], %g3 !
- and %g3, 0x300, %g3
- or %g2, %g3, %g2
- st %g2, [%g1 + LEON2_MCFG1]
- set CONFIG_SYS_GRLIB_MEMCFG2, %g2 ! Load memory config register 2
-#if !( defined(TSIM) || !defined(BZIMAGE))
- st %g2, [%g1 + LEON2_MCFG2] ! only for prom version, else done by "dumon -i"
-#endif
- set CONFIG_SYS_GRLIB_MEMCFG3, %g2 ! Init FT register
- st %g2, [%g1 + LEON2_ECTRL]
- ld [%g1 + LEON2_ECTRL], %g2
- srl %g2, 30, %g2
- andcc %g2, 3, %g6
- bne,a leon2_init_wim
- mov %g0, %asr16 ! clear err_reg
-
-leon2_init_wim:
- set WIM_INIT, %g3
- mov %g3, %wim
-
-leon2_init_psr:
- set 0x1000, %g3
- mov %psr, %g2
- wr %g2, %g3, %psr
- nop
- nop
- nop
-
-leon2_init_stackp:
- set CONFIG_SYS_INIT_SP_OFFSET, %fp
- andn %fp, 0x0f, %fp
- sub %fp, 64, %sp
-
-leon2_init_tbr:
- set CONFIG_SYS_TEXT_BASE, %g2
- wr %g0, %g2, %tbr
- nop
- nop
- nop
-
-cpu_init_unreloc:
- call cpu_init_f
- nop
-
-board_init_unreloc:
- call board_init_f
- clr %o0 ! boot_flags
-
-dead_unreloc:
- ba dead_unreloc ! infinte loop
- nop
-
-!-------------------------------------------------------------------------------
-
-/* void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM after
- * relocating the monitor code.
- *
- * %o0 = Relocated stack pointer
- * %o1 = Relocated global data pointer
- * %o2 = Relocated text pointer
- */
- .globl relocate_code
- .type relocate_code, #function
- .align 4
-relocate_code:
- SPARC_PIC_THUNK_CALL(l7)
-
-/* un relocated start address of monitor */
-#define TEXT_START _text
-
-/* un relocated end address of monitor */
-#define DATA_END __init_end
-
-reloc:
- SPARC_LOAD_ADDRESS(TEXT_START, l7, g2)
- SPARC_LOAD_ADDRESS(DATA_END, l7, g3)
- mov %o2, %g4 ! relocation address
- sub %g4, %g2, %g6 ! relocation offset
- /* copy .text & .data to relocated address */
-10: ldd [%g2], %l0
- ldd [%g2+8], %l2
- std %l0, [%g4]
- std %l2, [%g4+8]
- inc 16, %g2 ! src += 16
- cmp %g2, %g3
- bcs 10b ! while (src < end)
- inc 16, %g4 ! dst += 16
-
- clr %l0
- clr %l1
- clr %l2
- clr %l3
- clr %g2
-
-/* register g4 contain address to start
- * This means that BSS must be directly after data and code segments
- *
- * g3 is length of bss = (__bss_end-__bss_start)
- *
- */
-
- /* clear bss area (the relocated) */
-clr_bss:
- SPARC_LOAD_ADDRESS(__bss_start, l7, g2)
- SPARC_LOAD_ADDRESS(__bss_end, l7, g3)
- sub %g3,%g2,%g3 ! length of .bss area
- add %g3,%g4,%g3
- /* clearing 16byte a time ==> linker script need to align to 16 byte offset */
- clr %g1 /* std %g0 uses g0 and g1 */
-20:
- std %g0, [%g4]
- std %g0, [%g4+8]
- inc 16, %g4 ! ptr += 16
- cmp %g4, %g3
- bcs 20b ! while (ptr < end)
- nop
-
- /* add offsets to GOT table */
-fixup_got:
- SPARC_LOAD_ADDRESS(__got_start, l7, g4)
- add %g4, %g6, %g4
- SPARC_LOAD_ADDRESS(__got_end, l7, g3)
- add %g3, %g6, %g3
-30: ld [%g4], %l0 ! load old GOT-PTR
-#ifdef CONFIG_RELOC_GOT_SKIP_NULL
- cmp %l0, 0
- be 32f
-#endif
- add %l0, %g6, %l0 ! relocate GOT pointer
- st %l0, [%g4]
-32: inc 4, %g4 ! ptr += 4
- cmp %g4, %g3
- bcs 30b ! while (ptr < end)
- nop
-
-prom_relocate:
- SPARC_LOAD_ADDRESS(__prom_start, l7, g2)
- SPARC_LOAD_ADDRESS(__prom_end, l7, g3)
- /*
- * Calculated addres is stored in this variable by
- * reserve_prom() function in common/board_f.c
- */
- SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4)
- ld [%g4], %g4
-
-40: ldd [%g2], %l0
- ldd [%g2+8], %l2
- std %l0, [%g4]
- std %l2, [%g4+8]
- inc 16, %g2
- cmp %g2, %g3
- bcs 40b
- inc 16, %g4
-
-! %o0 = stack pointer (relocated)
-! %o1 = global data pointer (relocated)
-! %o2 = text pointer (relocated)
-
-! %g6 = relocation offset
-! %l7 = _GLOBAL_OFFSET_TABLE_
-
-/* Trap table has been moved, lets tell CPU about
- * the new trap table address
- */
-update_trap_table_address:
- wr %g0, %o2, %tbr
- nop
- nop
- nop
-
-update_stack_pointers:
- mov %o0, %fp
- andn %fp, 0x0f, %fp ! align to 16 bytes
- add %fp, -64, %fp ! make space for a window push
- mov %fp, %sp ! setup stack pointer
-
-jump_board_init_r:
- mov %o1, %o0 ! relocated global data pointer
- mov %o2, %o1 ! relocated text pointer
- SPARC_LOAD_ADDRESS(board_init_r, l7, o3)
- add %o3, %g6, %o3 ! add relocation offset
- call %o3
- nop
-
-dead: ta 0 ! if call returns...
- nop
-
-!------------------------------------------------------------------------------
-
-/* Interrupt handler caller,
- * reg L7: interrupt number
- * reg L0: psr after interrupt
- * reg L1: PC
- * reg L2: next PC
- * reg L3: wim
- */
-_irq_entry:
- SAVE_ALL
-
- or %l0, PSR_PIL, %g2
- wr %g2, 0x0, %psr
- WRITE_PAUSE
- wr %g2, PSR_ET, %psr
- WRITE_PAUSE
- mov %l7, %o0 ! irq level
- set handler_irq, %o1
- set (CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
- add %o1, %o2, %o1
- call %o1
- add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
- or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
- wr %g2, PSR_ET, %psr ! keep ET up
- WRITE_PAUSE
-
- RESTORE_ALL
-
-!------------------------------------------------------------------------------
-
-/*
- * Window overflow trap handler.
- */
- .global _window_overflow
-
-_window_overflow:
-
- mov %wim, %l3 ! Calculate next WIM
- mov %g1, %l7
- srl %l3, 1, %g1
- sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4
- or %l4, %g1, %g1
-
- save ! Get into window to be saved.
- mov %g1, %wim
- nop; nop; nop
- st %l0, [%sp + 0];
- st %l1, [%sp + 4];
- st %l2, [%sp + 8];
- st %l3, [%sp + 12];
- st %l4, [%sp + 16];
- st %l5, [%sp + 20];
- st %l6, [%sp + 24];
- st %l7, [%sp + 28];
- st %i0, [%sp + 32];
- st %i1, [%sp + 36];
- st %i2, [%sp + 40];
- st %i3, [%sp + 44];
- st %i4, [%sp + 48];
- st %i5, [%sp + 52];
- st %i6, [%sp + 56];
- st %i7, [%sp + 60];
- restore ! Go back to trap window.
- mov %l7, %g1
- jmp %l1 ! Re-execute save.
- rett %l2
-
-/*
- * Window underflow trap handler.
- */
- .global _window_underflow
-
-_window_underflow:
-
- mov %wim, %l3 ! Calculate next WIM
- sll %l3, 1, %l4
- srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
- or %l5, %l4, %l5
- mov %l5, %wim
- nop; nop; nop
- restore ! Two restores to get into the
- restore ! window to restore
- ld [%sp + 0], %l0; ! Restore window from the stack
- ld [%sp + 4], %l1;
- ld [%sp + 8], %l2;
- ld [%sp + 12], %l3;
- ld [%sp + 16], %l4;
- ld [%sp + 20], %l5;
- ld [%sp + 24], %l6;
- ld [%sp + 28], %l7;
- ld [%sp + 32], %i0;
- ld [%sp + 36], %i1;
- ld [%sp + 40], %i2;
- ld [%sp + 44], %i3;
- ld [%sp + 48], %i4;
- ld [%sp + 52], %i5;
- ld [%sp + 56], %i6;
- ld [%sp + 60], %i7;
- save ! Get back to the trap window.
- save
- jmp %l1 ! Re-execute restore.
- rett %l2
-
-!------------------------------------------------------------------------------
-
-_nmi_trap:
- nop
- jmp %l1
- rett %l2
-
-_hwerr:
- ta 0
- nop
- nop
- b _hwerr ! loop infinite
- nop
-
-/* Registers to not touch at all. */
-#define t_psr l0 /* Set by caller */
-#define t_pc l1 /* Set by caller */
-#define t_npc l2 /* Set by caller */
-#define t_wim l3 /* Set by caller */
-#define t_twinmask l4 /* Set at beginning of this entry routine. */
-#define t_kstack l5 /* Set right before pt_regs frame is built */
-#define t_retpc l6 /* If you change this, change winmacro.h header file */
-#define t_systable l7 /* Never touch this, could be the syscall table ptr. */
-#define curptr g6 /* Set after pt_regs frame is built */
-
-trap_setup:
-/* build a pt_regs trap frame. */
- sub %fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack
- PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
-
- /* See if we are in the trap window. */
- mov 1, %t_twinmask
- sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
- andcc %t_twinmask, %t_wim, %g0
- beq 1f ! in trap window, clean up
- nop
-
- /*-------------------------------------------------
- * Spill , adjust %wim and go.
- */
- srl %t_wim, 0x1, %g2 ! begin computation of new %wim
-
- set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
-
- sll %t_wim, %g3, %t_wim ! NWINDOWS-1
- or %t_wim, %g2, %g2
- and %g2, 0xff, %g2
-
- save %g0, %g0, %g0 ! get in window to be saved
-
- /* Set new %wim value */
- wr %g2, 0x0, %wim
-
- /* Save the kernel window onto the corresponding stack. */
- RW_STORE(sp)
-
- restore %g0, %g0, %g0
- /*-------------------------------------------------*/
-
-1:
- /* Trap from kernel with a window available.
- * Just do it...
- */
- jmpl %t_retpc + 0x8, %g0 ! return to caller
- mov %t_kstack, %sp ! jump onto new stack
-
-#define twin_tmp1 l4
-#define glob_tmp g4
-#define curptr g6
-ret_trap_entry:
- wr %t_psr, 0x0, %psr ! enable nesting again, clear ET
-
- /* Will the rett land us in the invalid window? */
- mov 2, %g1
- sll %g1, %t_psr, %g1
-
- set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
-
- srl %g1, %g2, %g2
- or %g1, %g2, %g1
- rd %wim, %g2
- andcc %g2, %g1, %g0
- be 1f ! Nope, just return from the trap
- sll %g2, 0x1, %g1
-
- /* We have to grab a window before returning. */
- set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
-
- srl %g2, %g3, %g2
- or %g1, %g2, %g1
- and %g1, 0xff, %g1
-
- wr %g1, 0x0, %wim
-
- /* Grrr, make sure we load from the right %sp... */
- PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-
- restore %g0, %g0, %g0
- RW_LOAD(sp)
- b 2f
- save %g0, %g0, %g0
-
- /* Reload the entire frame in case this is from a
- * kernel system call or whatever...
- */
-1:
- PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-2:
- wr %t_psr, 0x0, %psr
- nop;
- nop;
- nop
-
- jmp %t_pc
- rett %t_npc
-
-/* This is called from relocated C-code.
- * It resets the system by jumping to _start
- */
-_reset_reloc:
- set start, %l0
- call %l0
- nop
diff --git a/arch/sparc/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile
deleted file mode 100644
index f4cf43cfec32..000000000000
--- a/arch/sparc/cpu/leon3/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu_init.o serial.o cpu.o ambapp.o ambapp_low.o ambapp_low_c.o \
- interrupts.o prom.o usb_uhci.o memcfg.o memcfg_low.o
diff --git a/arch/sparc/cpu/leon3/ambapp.c b/arch/sparc/cpu/leon3/ambapp.c
deleted file mode 100644
index 47769cffd70a..000000000000
--- a/arch/sparc/cpu/leon3/ambapp.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/* GRLIB AMBA Plug&Play information scanning, relies on assembler
- * routines.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <malloc.h>
-#include <ambapp.h>
-#include <config.h>
-
-/************ C INTERFACE OF ASSEMBLER SCAN ROUTINES ************/
-struct ambapp_find_apb_info {
- /* Address of APB device Plug&Play information */
- struct ambapp_pnp_apb *pnp;
- /* AHB Bus index of where the APB-Master Bridge device was found */
- int ahb_bus_index;
- int dec_index;
-};
-
-struct ambapp_find_ahb_info {
- /* Address of AHB device Plug&Play information */
- struct ambapp_pnp_ahb *pnp;
- /* AHB Bus index of where the AHB device was found */
- int ahb_bus_index;
- int dec_index;
-};
-
-extern void ambapp_find_buses(unsigned int ioarea, struct ambapp_bus *abus);
-
-extern int ambapp_find_apb(struct ambapp_bus *abus, unsigned int dev_vend,
- int index, struct ambapp_find_apb_info *result);
-
-extern int ambapp_find_ahb(struct ambapp_bus *abus, unsigned int dev_vend,
- int index, int type, struct ambapp_find_ahb_info *result);
-
-/************ C ROUTINES USED BY U-BOOT AMBA CORE DRIVERS ************/
-struct ambapp_bus ambapp_plb __section(.data);
-
-void ambapp_bus_init(
- unsigned int ioarea,
- unsigned int freq,
- struct ambapp_bus *abus)
-{
- int i;
-
- ambapp_find_buses(ioarea, abus);
- for (i = 0; i < 6; i++)
- if (abus->ioareas[i] == 0)
- break;
- abus->buses = i;
- abus->freq = freq;
-}
-
-/* Parse APB PnP Information */
-void ambapp_apb_parse(struct ambapp_find_apb_info *info, ambapp_apbdev *dev)
-{
- struct ambapp_pnp_apb *apb = info->pnp;
- unsigned int apbbase = (unsigned int)apb & 0xfff00000;
-
- dev->vendor = amba_vendor(apb->id);
- dev->device = amba_device(apb->id);
- dev->irq = amba_irq(apb->id);
- dev->ver = amba_ver(apb->id);
- dev->address = (apbbase | (((apb->iobar & 0xfff00000) >> 12))) &
- (((apb->iobar & 0x0000fff0) << 4) | 0xfff00000);
- dev->mask = amba_apb_mask(apb->iobar);
- dev->ahb_bus_index = info->ahb_bus_index - 1;
-}
-
-/* Parse AHB PnP information */
-void ambapp_ahb_parse(struct ambapp_find_ahb_info *info, ambapp_ahbdev *dev)
-{
- struct ambapp_pnp_ahb *ahb = info->pnp;
- unsigned int ahbbase = (unsigned int)ahb & 0xfff00000;
- int i, type;
- unsigned int addr, mask, mbar;
-
- dev->vendor = amba_vendor(ahb->id);
- dev->device = amba_device(ahb->id);
- dev->irq = amba_irq(ahb->id);
- dev->ver = amba_ver(ahb->id);
- dev->userdef[0] = ahb->custom[0];
- dev->userdef[1] = ahb->custom[1];
- dev->userdef[2] = ahb->custom[2];
- dev->ahb_bus_index = info->ahb_bus_index - 1;
- for (i = 0; i < 4; i++) {
- mbar = ahb->mbar[i];
- addr = amba_membar_start(mbar);
- type = amba_membar_type(mbar);
- if (type == AMBA_TYPE_AHBIO) {
- addr = amba_ahbio_adr(addr, ahbbase);
- mask = (((unsigned int)
- (amba_membar_mask((~mbar))<<8)|0xff))+1;
- } else {
- /* AHB memory area, absolute address */
- mask = (~((unsigned int)
- (amba_membar_mask(mbar)<<20)))+1;
- }
- dev->address[i] = addr;
- dev->mask[i] = mask;
- dev->type[i] = type;
- }
-}
-
-int ambapp_apb_find(struct ambapp_bus *abus, int vendor, int device,
- int index, ambapp_apbdev *dev)
-{
- unsigned int devid = AMBA_PNP_ID(vendor, device);
- int found;
- struct ambapp_find_apb_info apbdev;
-
- found = ambapp_find_apb(abus, devid, index, &apbdev);
- if (found == 1)
- ambapp_apb_parse(&apbdev, dev);
-
- return found;
-}
-
-int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device)
-{
- unsigned int devid = AMBA_PNP_ID(vendor, device);
- int found;
- struct ambapp_find_apb_info apbdev;
-
- found = ambapp_find_apb(abus, devid, 63, &apbdev);
- if (found == 1)
- return 64;
- else
- return 63 - apbdev.dec_index;
-}
-
-int ambapp_ahb_find(struct ambapp_bus *abus, int vendor, int device,
- int index, ambapp_ahbdev *dev, int type)
-{
- int found;
- struct ambapp_find_ahb_info ahbdev;
- unsigned int devid = AMBA_PNP_ID(vendor, device);
-
- found = ambapp_find_ahb(abus, devid, index, type, &ahbdev);
- if (found == 1)
- ambapp_ahb_parse(&ahbdev, dev);
-
- return found;
-}
-
-int ambapp_ahbmst_find(struct ambapp_bus *abus, int vendor, int device,
- int index, ambapp_ahbdev *dev)
-{
- return ambapp_ahb_find(abus, vendor, device, index, dev, DEV_AHB_MST);
-}
-
-int ambapp_ahbslv_find(struct ambapp_bus *abus, int vendor, int device,
- int index, ambapp_ahbdev *dev)
-{
- return ambapp_ahb_find(abus, vendor, device, index, dev, DEV_AHB_SLV);
-}
-
-int ambapp_ahb_count(struct ambapp_bus *abus, int vendor, int device, int type)
-{
- int found;
- struct ambapp_find_ahb_info ahbdev;
- unsigned int devid = AMBA_PNP_ID(vendor, device);
-
- found = ambapp_find_ahb(abus, devid, 63, type, &ahbdev);
- if (found == 1)
- return 64;
- else
- return 63 - ahbdev.dec_index;
-}
-
-int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device)
-{
- return ambapp_ahb_count(abus, vendor, device, DEV_AHB_MST);
-}
-
-int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device)
-{
- return ambapp_ahb_count(abus, vendor, device, DEV_AHB_SLV);
-}
-
-/* The define CONFIG_SYS_GRLIB_SINGLE_BUS may be defined on GRLIB systems
- * where only one AHB Bus is available - no bridges are present. This option
- * is available only to reduce the footprint.
- *
- * Defining this on a multi-bus GRLIB system may also work depending on the
- * design.
- */
-
-#ifndef CONFIG_SYS_GRLIB_SINGLE_BUS
-
-/* GAISLER AHB2AHB Version 1 Bridge Definitions */
-#define AHB2AHB_V1_FLAG_FFACT 0x0f0 /* Frequency factor against top bus */
-#define AHB2AHB_V1_FLAG_FFACT_DIR 0x100 /* Factor direction, 0=down, 1=up */
-#define AHB2AHB_V1_FLAG_MBUS 0x00c /* Master bus number mask */
-#define AHB2AHB_V1_FLAG_SBUS 0x003 /* Slave bus number mask */
-
-/* Get Parent bus frequency. Note that since we go from a "child" bus
- * to a parent bus, the frequency factor direction is inverted.
- */
-unsigned int gaisler_ahb2ahb_v1_freq(ambapp_ahbdev *ahb, unsigned int freq)
-{
- int dir;
- unsigned char ffact;
-
- /* Get division/multiple factor */
- ffact = (ahb->userdef[0] & AHB2AHB_V1_FLAG_FFACT) >> 4;
- if (ffact != 0) {
- dir = ahb->userdef[0] & AHB2AHB_V1_FLAG_FFACT_DIR;
-
- /* Calculate frequency by dividing or
- * multiplying system frequency
- */
- if (dir)
- freq = freq * ffact;
- else
- freq = freq / ffact;
- }
-
- return freq;
-}
-
-/* AHB2AHB and L2CACHE ver 2 is not supported yet. */
-unsigned int gaisler_ahb2ahb_v2_freq(ambapp_ahbdev *ahb, unsigned int freq)
-{
- panic("gaisler_ahb2ahb_v2_freq: AHB2AHB ver 2 not supported\n");
- return -1;
-}
-#endif
-
-/* Return the frequency of a AHB bus identified by index found
- * note that this is not the AHB Bus number.
- */
-unsigned int ambapp_bus_freq(struct ambapp_bus *abus, int ahb_bus_index)
-{
- unsigned int freq = abus->freq;
-#ifndef CONFIG_SYS_GRLIB_SINGLE_BUS
- unsigned int ioarea, ioarea_parent, bridge_pnp_ofs;
- struct ambapp_find_ahb_info ahbinfo;
- ambapp_ahbdev ahb;
- int parent;
-
- debug("ambapp_bus_freq: get freq on bus %d\n", ahb_bus_index);
-
- while (ahb_bus_index != 0) {
- debug(" BUS[0]: 0x%08x\n", abus->ioareas[0]);
- debug(" BUS[1]: 0x%08x\n", abus->ioareas[1]);
- debug(" BUS[2]: 0x%08x\n", abus->ioareas[2]);
- debug(" BUS[3]: 0x%08x\n", abus->ioareas[3]);
- debug(" BUS[4]: 0x%08x\n", abus->ioareas[4]);
- debug(" BUS[5]: 0x%08x\n", abus->ioareas[5]);
-
- /* Get I/O area of AHB bus */
- ioarea = abus->ioareas[ahb_bus_index];
-
- debug(" IOAREA: 0x%08x\n", ioarea);
-
- /* Get parent bus */
- parent = (ioarea & 0x7);
- if (parent == 0) {
- panic("%s: parent=0 indicates no parent! Stopping.\n",
- __func__);
- return -1;
- }
- parent = parent - 1;
- bridge_pnp_ofs = ioarea & 0x7e0;
-
- debug(" PARENT: %d\n", parent);
- debug(" BRIDGE_OFS: 0x%08x\n", bridge_pnp_ofs);
-
- /* Get AHB/AHB bridge PnP address */
- ioarea_parent = (abus->ioareas[parent] & 0xfff00000) |
- AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA;
- ahbinfo.pnp = (struct ambapp_pnp_ahb *)
- (ioarea_parent | bridge_pnp_ofs);
-
- debug(" IOAREA PARENT: 0x%08x\n", ioarea_parent);
- debug(" BRIDGE PNP: 0x%p\n", ahbinfo.pnp);
-
- /* Parse the AHB information */
- ahbinfo.ahb_bus_index = parent;
- ambapp_ahb_parse(&ahbinfo, &ahb);
-
- debug(" BRIDGE ID: VENDOR=%d(0x%x), DEVICE=%d(0x%x)\n",
- ahb.vendor, ahb.vendor, ahb.device, ahb.device);
-
- /* Different bridges may convert frequency differently */
- if ((ahb.vendor == VENDOR_GAISLER) &&
- ((ahb.device == GAISLER_AHB2AHB) ||
- (ahb.device == GAISLER_L2CACHE))) {
- /* Get new frequency */
- if (ahb.ver > 1)
- freq = gaisler_ahb2ahb_v2_freq(&ahb, freq);
- else
- freq = gaisler_ahb2ahb_v1_freq(&ahb, freq);
-
- debug(" NEW FREQ: %dHz\n", freq);
- } else {
- panic("%s: unsupported AMBA bridge\n", __func__);
- return -1;
- }
-
- /* Step upwards towards system top bus */
- ahb_bus_index = parent;
- }
-#endif
-
- debug("ambapp_bus_freq: %dHz\n", freq);
-
- return freq;
-}
diff --git a/arch/sparc/cpu/leon3/ambapp_low.S b/arch/sparc/cpu/leon3/ambapp_low.S
deleted file mode 100644
index 2863586dc1b9..000000000000
--- a/arch/sparc/cpu/leon3/ambapp_low.S
+++ /dev/null
@@ -1,784 +0,0 @@
-/* GRLIB AMBA Plug&Play information scanning implemented without
- * using memory (stack) and one register window. The code scan
- * the PnP info and inserts the AHB bridges/buses into register
- * i0-i5.
- * The code support
- * - up to 6 AHB buses
- * - multiple APB buses
- * - support for AHB2AHB & L2CACHE bridges
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ambapp.h>
-
- .seg "text"
- .globl _nomem_amba_init
- .globl _nomem_ambapp_find_buses
- .globl _nomem_find_apb
- .globl _nomem_find_ahb
-
-/* Overview
- * ========
- *
- * _nomem_amba_init - Init AMBA bus and calls _nomem_ambapp_find_buses
- * _nomem_ambapp_find_buses - Scan AMBA PnP info for AHB buses/bridges and
- * place them in i0-i5, see below
- * _nomem_find_apb - Find one APB device identified by VENDOR:DEVICE
- * ID and an index.
- * _nomem_find_ahb - Find one AHB Master or Slave device identified
- * by VENDOR:DEVICE ID and an index.
- * init_ahb_bridges - Local function. Clears i0-i5
- * insert_ahb_bridge - Local function. Insert a new AHB bus into first
- * free register in i0-i5. It also checks that the
- * bus has not already been added.
- * get_ahb_bridge - Local function. Get AHB bus from registers,
- * return register iN, where N is defined by o0.
- *
- * The _nomem_find_apb and _nomem_find_ahb function requires that i0-i5
- * are populated with the AHB buses of the system. The registers are
- * initialized by _nomem_ambapp_find_buses.
- *
- * AHB Bus result and requirements of i0-i5
- * ========================================
- *
- * i0: AHB BUS0 IOAREA, no parent bus
- * i1: AHB BUS1 IOAREA, parent bus is always i0 (AHB BUS0) and bridge address
- * i2: AHB BUS2 IOAREA, 3-bit parent bus number and bridge address
- * i3: AHB BUS3 IOAREA, 3-bit parent bus number and bridge address
- * i4: AHB BUS4 IOAREA, 3-bit parent bus number and bridge address
- * i5: AHB BUS5 IOAREA, 3-bit parent bus number and bridge address
- *
- * AHB BUS
- * -------
- * Bits 31-20 (0xfff00000) contain the found bus I/O Area (AHB PnP area).
- *
- * 3-bit Parent bus
- * ----------------
- * Bits 2-0 (0x00000007) contain parent bus number. Zero if no parent
- * bus, 1 = parent is AHB BUS 0 (i0), 2 = parent is AHB BUS 1 (i1)..
- *
- * Bridge Address
- * --------------
- * Bits 10-5 (0x000007e0) contain the index of the Bridge's PnP
- * information on the parent. Since all bridges are found in the
- * PnP information they all have a PnP entry. Together with the
- * parent bus number the PnP entry can be found:
- * PnPEntry = (BRIDGE_ADDRESS + (iN & 0xfff00000)) | 0x000ff800
- * where N is the parent bus minus one.
- *
- */
-
-/* Function initializes the AHB Bridge I/O AREA storage. (Clears i0-i5)
- *
- * Arguments
- * none
- *
- * Results
- * none
- *
- * Clobbered
- * none
- */
-
-init_ahb_bridges:
- mov %g0, %i0
- mov %g0, %i1
- mov %g0, %i2
- mov %g0, %i3
- mov %g0, %i4
- retl
- mov %g0, %i5
-
-/* Function returns AHB Bridge I/O AREA for specified bus.
- *
- * Arguments
- * - o0 = bus number
- *
- * Results
- * - o0 = I/O AREA
- *
- * Clobbered
- * none
- */
-get_ahb_bridge:
- cmp %o0, 1
- be,a L1
- mov %i0, %o0
-
- cmp %o0, 2
- be,a L1
- mov %i1, %o0
-
- cmp %o0, 3
- be,a L1
- mov %i2, %o0
-
- cmp %o0, 4
- be,a L1
- mov %i3, %o0
-
- cmp %o0, 5
- be,a L1
- mov %i4, %o0
-
- cmp %o0, 6
- be,a L1
- mov %i5, %o0
-
- /* o0 > 6: only 6 buses supported */
- mov %g0, %o0
-L1:
- retl
- nop
-
-/* Function adds a AHB Bridge I/O AREA to the i0-i5 registers if
- * not already added. It stores the bus PnP start information.
- *
- * Arguments
- * - o0 = AHB Bridge I/O area
- *
- * Results
- * none
- *
- * Clobbered
- * o2, o3
- */
-insert_ahb_bridge:
- /* Check that bridge hasn't already been added */
- andn %o0, 0x7ff, %o2
- andn %i0, 0x7ff, %o3
- cmp %o3, %o2
- be L2
- andn %i1, 0x7ff, %o3
- cmp %o3, %o2
- be L2
- andn %i2, 0x7ff, %o3
- cmp %o3, %o2
- be L2
- andn %i3, 0x7ff, %o3
- cmp %o3, %o2
- be L2
- andn %i4, 0x7ff, %o3
- cmp %o3, %o2
- be L2
- andn %i5, 0x7ff, %o3
- cmp %o3, %o2
- be L2
-
- /* Insert into first free posistion */
- cmp %i0, %g0
- be,a L2
- mov %o0, %i0
-
- cmp %i1, %g0
- be,a L2
- mov %o0, %i1
-
- cmp %i2, %g0
- be,a L2
- mov %o0, %i2
-
- cmp %i3, %g0
- be,a L2
- mov %o0, %i3
-
- cmp %i4, %g0
- be,a L2
- mov %o0, %i4
-
- cmp %i5, %g0
- be,a L2
- mov %o0, %i5
-L2:
- retl
- nop
-
-/* FUNCTION int _nomem_find_ahb_bus(
- * unsigned int bridge,
- * int vendor_device,
- * int index,
- * void **pconf,
- * int not_used,
- * int option
- * )
- *
- * Scans the AHB Master or Slave area for a matching VENDOR:DEVICE, the
- * index is decremented when a matching device is found but index is
- * greater than zero. When index is zero and a matching DEVICE:VENDOR
- * is found the AHB configuration address and AHB I/O area is returned.
- *
- * i0-i7,l0,l1,l2,l3,l4,g2,o6 is not available for use.
- * o1,o5 Must be left untouched
- *
- * Results
- * - o0 Number of found devices (1 or 0)
- * - o2 is decremented for each matching VENDOR:DEVICE found, zero if found
- * - o3 Address of the AHB PnP configuration entry (Only valid if o0=1)
- *
- * Clobbered
- * - o3 (Clobbered when no device was found)
- * - o4 (Number of Devices left to search)
- * - o0 (Bus ID, PnP ID, Device)
- */
-_nomem_find_ahb_bus:
-
- /* Get the number of Slaves/Masters.
- * Only AHB Bus 0 has 64 AHB Masters/Slaves the
- * other AHB buses has 16 slaves and 16 masters.
- */
- add %g0, 16, %o4 /* Defaulting to 16 */
- andcc %o0, 0x7, %g0 /* 3-bit bus id */
- be,a .L_maxloops_detected
- add %g0, 64, %o4 /* AHB Bus 0 has 64 AHB Masters/Slaves */
-.L_maxloops_detected:
-
- /* Get start address of AHB Slave or AHB Master area depending on what
- * we are searching for.
- */
- andn %o0, 0x7ff, %o0 /* Remove Bus ID and 5-bit AHB/AHB
- * Bridge PnP Address to get I/O Area */
- set AMBA_CONF_AREA, %o3
- or %o3, %o0, %o3 /* Master area address */
-
- cmp %o5, DEV_AHB_SLV
- be,a .L_conf_area_calculated
- or %o3, AMBA_AHB_SLAVE_CONF_AREA, %o3 /* Add 0x800 to get to slave area */
-.L_conf_area_calculated:
-
- /* Iterate over all AHB device and try to find matching DEVICE:VENDOR
- * o1 - VENDOR|DEVICE
- * o2 - Index
- * o3 - Current AHB Device Configuration address
- * o5 - Type (leave untouched)
- *
- * o4 - Number of AHB device left to process
- * o0 - tmp
- */
-.L_process_one_conf:
- ld [%o3], %o0
- andn %o0, 0xfff, %o0
- cmp %o0, 0 /* No device if zero */
- beq .L_next_conf
- cmp %o1, 0 /* If VENDOR:DEVICE==0, consider all matching */
- beq .L_process_ahb_dev_found
- cmp %o0, %o1 /* Does VENDOR and DEVICE Match? */
- bne .L_next_conf
- nop
-.L_process_ahb_dev_found:
- /* Found a Matching VENDOR:DEVICE, index must also match */
- cmp %o2, %g0
- bne .L_next_conf
- dec %o2
- /* Index matches also, return happy with o3 set to AHB Conf Address */
- mov %g0, %o2
- retl
- add %g0, 1, %o0
-
-.L_next_conf:
- subcc %o4, 1, %o4 /* One device has been processed,
- * Are there more devices to process? */
- bne .L_process_one_conf
- add %o3, AMBA_AHB_CONF_LENGH, %o3 /* Next Configuration entry */
- /* No Matching device found */
- retl
- mov %g0, %o0
-
-/* FUNCTION int _nomem_find_ahb(
- * int unused,
- * int vendor_device,
- * int index,
- * void **pconf,
- * int *ahb_bus_index,
- * int option,
- * )
- *
- * Find a AHB Master or AHB Slave device, it puts the address of the AHB PnP
- * configuration in o3 (pconf), the I/O Area base address in o4 (pioarea).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus.
- *
- * i0-i7, l0, l1, o6, g1, g4-g7 is not available for use.
- *
- * Arguments
- * - o0 Unused
- *
- * Results
- * - o0 Number of found devices (1 or 0)
- * - o2 Decremented Index (Zero if found)
- * - o3 Address of the AHB PnP configuration entry
- * - o4 AHB Bus index the device was found on (if o0=1)
- * - o5 Left untouched
- *
- * Clobbered
- * - o0 (AHB Bridge and used by _nomem_find_ahb_bus)
- * - o2 (index is decremented)
- * - l2 (Current AHB Bus index)
- * - g2 (return address)
- */
-_nomem_find_ahb:
- mov %o7, %g2 /* Save return address */
- /* Scan all AHB Buses found for the AHB Master/Slave matching VENDOR:DEVICE */
- clr %l2
-.L_search_next_ahb_bus:
- add %l2, 1, %l2
- call get_ahb_bridge /* Get bus %l0 I/O Area */
- mov %l2, %o0
- cmp %o0, %g0
- be .L_no_device_found /* If no more AHB bus is left to be scanned, proceed */
- nop
- call _nomem_find_ahb_bus /* Scan AHB bus %o0 for VENDOR:DEVICE. Index in o3 is decremented */
- nop
- cmp %o0, %g0 /* If VENDOR:DEVICE was not found scan next AHB Bus */
- be .L_search_next_ahb_bus /* Do next bus is o0=0 (not found) */
- nop
- /* The device was found, o0 is 1 */
- mov %g2, %o7 /* Restore return address */
- retl
- mov %l2, %o4 /* The AHB bus index the device was found on */
-
- /* No device found matching */
-.L_no_device_found:
- mov %g2, %o7 /* Restore return address */
- retl
- mov %g0, %o0
-
-
-/* FUNCTION int _nomem_find_apb_bus(
- * int apbmst,
- * int vendor_device,
- * int index,
- * void **pconf
- * )
- *
- * Find a APB Slave device, it puts the address of the APB PnP configuration
- * in o3 (pconf).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus searching for AHB/APB Bridges.
- * The AHB/APB bridges are AHB Slaves with ID GAISLER_APBMST.
- *
- * Results
- * - o0 Number of found devices (1 or 0)
- * - o2 Decremented Index
- * - o3 Address of the found APB device PnP configuration entry
- *
- * Clobbered
- * - o5 PnP VENDOR:DEVICE ID
- */
-
-_nomem_find_apb_bus:
- set AMBA_CONF_AREA, %o3
- or %o0, %o3, %o3 /* Calc start of APB device PnP info */
- add %g0, 16, %o0 /* o0, number of APB Slaves left to scan */
-.L_process_one_apb_conf:
- ld [%o3], %o5
- andn %o5, 0xfff, %o5
- cmp %o5, 0 /* No device if zero */
- beq .L_process_apb_dev_not_found
- cmp %o1, 0 /* If VENDOR:DEVICE == -1, consider all matching */
- beq .L_process_apb_dev_found
- cmp %o1, %o5 /* Found VENDOR:DEVICE */
- bne .L_process_apb_dev_not_found
- nop
-
-.L_process_apb_dev_found:
- /* Found matching device, compare index */
- cmp %o2, %g0
- bne .L_process_apb_dev_not_found
- dec %o2
- /* Matching index and VENDOR:DEVICE */
- retl
- add %g0, 1, %o0
-
-.L_process_apb_dev_not_found:
- subcc %o0, 1, %o0
- bne .L_process_one_apb_conf
- add %o3, 8, %o3
- retl
- mov %g0, %o0
-
-/* FUNCTION int _nomem_find_apb(
- * int unused,
- * int vendor_device,
- * int index,
- * void **pconf,
- * int *ahb_bus_index
- * )
- *
- * Find a APB Slave device, it puts the address of the APB PnP configuration
- * in o3 (pconf), the APB Master I/O Area base address in o4 (papbarea).
- *
- * Calls _nomem_find_ahb_bus for every AHB bus searching for AHB/APB Bridges.
- * The AHB/APB bridges are AHB Slaves with ID GAISLER_APBMST.
- *
- * i0-i7, l0, l1, o6 is not available for use.
- *
- * Arguments
- * - o0 Unused
- *
- * Results
- * - o0 Number of found devices (1 or 0)
- * - o2 Decremented Index if not found
- * - o3 Address of the APB PnP configuration entry
- * - o4 AHB Bus index of APB Bridge/APB Device
- *
- * Clobbered
- * - o0 (AHB Bridge)
- * - o2 (index is decremented)
- * - l2 (APB DEV Index [7..4] : APBMST AHB Index [3..0])
- * - l3 (Current AHB Bus index)
- * - l4 (temporary storage for APB VENDOR:DEVICE)
- * - o5 (AHB Slave ID)
- * - o0 (clobbered by _nomem_find_ahb_bus)
- * - g2 (Return address)
- */
-_nomem_find_apb:
- /* Scan all AHB Buses found for AHB/APB Bridges */
- mov %o7, %g2 /* Save return address */
- mov %o1, %l4 /* Save APB VENDOR:DEVICE */
- sll %o2, 4, %l2 /* APB MST index = 0 */
- add %g0, 1, %l3 /* AHB Bus index = 0 */
-.L2_search_next_ahb_bus:
- call get_ahb_bridge /* Get bus %l3 I/O Area */
- mov %l3, %o0
- cmp %o0, %g0
- be .L2_no_device_found /* If no more AHB bus is left to be scanned, proceed */
- add %g0, DEV_AHB_SLV, %o5 /* Search for AHB Slave */
- sethi %hi(AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_APBMST)), %o1
- call _nomem_find_ahb_bus /* Scan AHB bus %o0 for VENDOR:DEVICE. Index in o3 is decremented */
- and %l2, 0xf, %o2 /* Set APBMST index */
- cmp %o0, %g0 /* If no AHB/APB Bridge was not found, scan next AHB Bus */
- be .L_no_apb_bridge_found /* Do next bus */
- nop
-
- /* The AHB/APB Bridge was found.
- * Search for the requested APB Device on the APB bus using
- * find_apb_bus, it will decrement the index.
- */
- ld [%o3 + AMBA_AHB_MBAR0_OFS], %o3
- sll %o3, 16, %o0
- and %o0, %o3, %o0 /* Address AND Address Mask */
- sethi %hi(0xfff00000), %o3
- and %o0, %o3, %o0 /* AHB/APB Bridge address */
-
- srl %l2, 4, %o2 /* APB DEV Index */
- call _nomem_find_apb_bus
- mov %l4, %o1 /* APB VENDOR:DEVICE */
- cmp %o0, %g0
- be .L_apb_dev_not_found
- mov %g2, %o7 /* Restore return address */
- /* APB Device found
- * o0 1
- * o2 Index is decremented to zero
- * o3 APB configuration address,
- * o4 APB Bridge Configuration address.
- */
- mov %g0, %o2
- retl
- mov %l3, %o4
-
-.L_apb_dev_not_found:
- /* Update APB DEV Index by saving output from find_apb_bus
- * (index parameter) into bits [31..4] in L2.
- */
- sll %o2, 4, %o2
- and %l2, 0xf, %l2
- or %o2, %l2, %l2
- /* Try finding the next AHB/APB Bridge on the same AHB bus
- * to find more APB devices
- */
- ba .L2_search_next_ahb_bus /* Find next AHB/APB bridge */
- inc %l2
-
-.L_no_apb_bridge_found:
- inc %l3 /* Next AHB Bus */
- ba .L2_search_next_ahb_bus /* Process next AHB bus */
- andn %l2, 0xf, %l2 /* Start at APB Bridge index 0 at every AHB Bus */
- /* No device found matching */
-.L2_no_device_found:
- mov %g2, %o7 /* Restore return address */
- srl %l2, 4, %o2 /* APB DEV Index */
- retl
- mov %g0, %o0
-
-
-
-/* FUNCTION _nomem_amba_scan_gaisler_ahb2ahb_bridge(unsigned int bridge, int bus)
- *
- * Constraints:
- * - o1 may not be used
- * - o0, o2, o3 may be used.
- *
- * Arguments
- * - o0 PnP Address of Bridge AHB device
- * - o2 PnP ID of AHB device
- *
- * Results
- * - o0 Address of new bus PnP area or a 1 if AHB device is no bridge
- *
- * Clobbered
- * - o0, o2
- *
- */
-_nomem_amba_scan_gaisler_ahb2ahb_bridge:
- andn %o2, 0xfff, %o2
- sethi %hi(AMBA_PNP_ID(VENDOR_GAISLER,GAISLER_AHB2AHB)), %o3
- cmp %o2, %o3
- beq .L_is_ahb2ahb_bridge
- nop
-
- retl
- add %g0, 1, %o0
-
-.L_is_ahb2ahb_bridge:
- /* Found a GAISLER AHB2AHB bridge */
- retl
- ld [%o0 + AMBA_AHB_CUSTOM1_OFS], %o0 /* Get address of bridge PnP area */
-
-
-/* FUNCTION _nomem_amba_scan_gaisler_l2cache_bridge(unsigned int bridge, int bus)
- *
- * Constraints:
- * - o1 may not be used
- * - o0, o2, o3 may be used.
- *
- * Arguments
- * - o0 PnP Address of Bridge AHB device
- * - o2 PnP ID of AHB device
- *
- * Results
- * - o0 Address of new bus PnP area or a 1 if AHB device is no bridge
- *
- * Clobbered
- * - o0, o2
- *
- */
-_nomem_amba_scan_gaisler_l2cache_bridge:
- andn %o2, 0xfff, %o2
- sethi %hi(AMBA_PNP_ID(VENDOR_GAISLER,GAISLER_L2CACHE)), %o3
- cmp %o2, %o3
- beq .L_is_l2cache_bridge
- nop
-
- retl
- add %g0, 1, %o0
-
-.L_is_l2cache_bridge:
- /* Found a GAISLER l2cache bridge */
- retl
- ld [%o0 + AMBA_AHB_CUSTOM1_OFS], %o0 /* Get address of bridge PnP area */
-
-
-/* FUNCTION _nomem_amba_scan(unsigned int bridge, int bus)
- *
- * Constraints:
- * i0-i7, l0 is used by caller
- * o5-o7 may not be used.
- *
- * Arguments
- * - o0 Bridge Information: I/O AREA and parent bus
- * - o1 Bus
- *
- * Results
- * - o0 Number of AHB bridges found
- *
- * Clobbered
- * - o0 (Current AHB slave conf address)
- * - o2 (Used by insert_bridge)
- * - o3 (Used by insert_bridge)
- * - l1 (Number of AHB Slaves left to process)
- * - l2 (Current AHB slave conf address)
- * - g2 (Return address)
- */
-_nomem_amba_scan:
- mov %o7, %g2 /* Save return address */
- set 16, %l1
- cmp %o1, 1
- be,a .L2_maxloops_detected
- add %g0, 64, %l1
-.L2_maxloops_detected:
-
- /* Clear 3-bit parent bus from bridge to get I/O AREA, then or
- * (AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA) to get first AHB slave
- * conf address.
- */
- andn %o0, 0x7ff, %o0
- set (AMBA_CONF_AREA | AMBA_AHB_SLAVE_CONF_AREA), %l2
- or %o0, %l2, %l2
-
- /* Scan AHB Slave area for AHB<->AHB bridges. For each AHB device
- * all "bridge drivers" are called, the driver function interface:
- *
- * Input:
- * - o0 PnP Address of Bridge AHB device
- * - o2 PnP ID of AHB device
- * Return values:
- * - o0 Address of new bus PnP area, returning a 1 in o2 means not found
- *
- * Constraints:
- * - o1 may not be used
- * - o0, o2, o3 may be used.
- *
- */
-.L_scan_one_ahb_slave:
- ld [%l2], %o2
-
- cmp %o2, %g0
- beq .L_scan_next_ahb_slave
- nop
-
- /* Call the GAISLER AHB2AHB bridge driver */
- call _nomem_amba_scan_gaisler_ahb2ahb_bridge
- mov %l2, %o0
- cmp %o0, 1
- bne .L_found_bridge
- ld [%l2], %o2
-
- /* Call the GAISLER L2CACHE bridge driver */
- call _nomem_amba_scan_gaisler_l2cache_bridge
- mov %l2, %o0
- cmp %o0, 1
- bne .L_found_bridge
- ld [%l2], %o2
-
- /* Insert next bridge "driver" function here */
-
-
- /* The PnP ID did not match a bridge - a new bus was not found ==>
- * step to next AHB device */
- ba .L_scan_next_ahb_slave
- nop
-
- /* Add Found bus */
-.L_found_bridge:
- and %l2, 0x7e0, %o2
- or %o2, %o0, %o0 /* Add AHB/AHB Bridge PnP address */
- call insert_ahb_bridge /* Insert Bridge into found buses storage */
- or %o1, %o0, %o0 /* Add parent bus LSB 3-bits */
-
-.L_scan_next_ahb_slave:
- /* More Slaves to process? */
- subcc %l1, 1, %l1
- bne .L_scan_one_ahb_slave
- add %l2, AMBA_AHB_CONF_LENGH, %l2
-
- /* No more AHB devices to process */
- mov %g2, %o7 /* Restore return address */
- retl
- nop
-
-/* FUNCTION _nomem_ambapp_find_buses(unsigned int ioarea)
- *
- * Find AMBA AHB buses.
- *
- * Constraints:
- * i6-i7, l7 is used by caller
- *
- * Arguments
- * - o0 Bridge Information: I/O AREA and parent bus
- *
- * Results
- * - o0 Number of AHB bridges found
- * - i0-i5 initialized
- *
- * Clobbered
- * - o0 (Current AHB slave conf address)
- * - o2 (Used by insert_bridge)
- * - o3 (Used by insert_bridge)
- * - l0 (Current AHB Bus)
- * - l1 (Used by nomem_amba_scan)
- * - l2 (Used by nomem_amba_scan)
- * - l3 (Used by nomem_amba_scan)
- * - l4 (Used by nomem_amba_scan)
- *
- * - g1 (level 1 return address)
- * - g2 (Used by nomem_amba_scan)
- */
-_nomem_ambapp_find_buses:
- mov %o7, %g1 /* Save return address */
-
- /* Initialize AHB Bus storage */
- call init_ahb_bridges
- nop
-
- /* Insert AHB Bus 0 */
- call insert_ahb_bridge
- nop /* Argument already prepared by caller */
-
- /* Scan AHB Bus 0 for AHB Bridges */
- call _nomem_amba_scan
- add %g0, 1, %o1
-
- /* Scan all AHB Buses found for more AHB Bridges */
- add %g0, 2, %l0
-.L100_search_next_ahb_bus:
- call get_ahb_bridge /* Get bus %l0 I/O Area */
- mov %l0, %o0
- cmp %o0, %g0
- be .L100_return /* If no more AHB bus is left to be scanned, proceed */
- nop
- call _nomem_amba_scan /* Scan bus %l0 for AHB Bridges. i0-i7,l0 is used */
- mov %l0, %o1 /* I/O AREA untouched in o0 */
- ba .L100_search_next_ahb_bus /* Do next bus */
- add %l0, 1, %l0
-
-.L100_return:
- mov %g1, %o7
- retl
- nop
-
-
-/* FUNCTION _nomem_amba_init(unsigned int ioarea)
- *
- * Find all AHB buses
- *
- * Constraints:
- * i6, i7, o6, o7, l7, l6, g3, g4, g5, g6, g7 is used by caller
- *
- * Arguments
- * - o0 Bridge Information: I/O AREA and parent bus
- *
- * Results
- * - o0 Number of AHB bridges found
- *
- * Clobbered
- * - l0, l1, l2, l3, l4, g1, g2 (used by _nomem_ambapp_find_buses)
- * - o0, o1, o2, o3 (Used as arguments)
- * - o5 (return address)
- * - g1 (level 1 return address)
- * - g2 (level 2 return address)
- */
-_nomem_amba_init:
- mov %o7, %o5 /* Save return address, o5 not used */
-
- /* Scan for buses, it will init i0-i5 */
- call _nomem_ambapp_find_buses
- nop
-
- mov %o5, %o7
- retl
- nop
-
-/* Call tree and their return address register
- *
- *_nomem_amba_scan (g1)
- * -> init_ahb_bridges (o7)
- * -> insert_ahb_bridge (o7)
- * -> _nomem_amba_scan (g2)
- * -> insert_ahb_bridge (o7)
- * -> get_ahb_bridge (o7)
- *
- *
- * -> _nomem_find_apb (g2)
- * -> get_ahb_bridge (o7)
- * -> _nomem_find_ahb_bus (o7)
- * -> _nomem_find_apb_bus (o7)
- * -> _nomem_find_ahb (g2)
- * -> get_ahb_bridge (o7)
- * -> _nomem_find_ahb_bus (o7)
- * -> mem_handler.func() (o7)
- *
- */
diff --git a/arch/sparc/cpu/leon3/ambapp_low_c.S b/arch/sparc/cpu/leon3/ambapp_low_c.S
deleted file mode 100644
index 42288fac598f..000000000000
--- a/arch/sparc/cpu/leon3/ambapp_low_c.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/* C-interface for AMBA PnP scanning functions implemented in
- * ambapp_low.S. At the point the memory and stack can be
- * used.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
- .seg "text"
- .extern _nomem_ambapp_find_buses
- .extern _nomem_find_apb
- .extern _nomem_find_ahb
-
- .globl ambapp_find_buses
- .globl ambapp_find_apb
- .globl ambapp_find_ahb
-
-
-/* C-interface for _nomem_ambapp_find_buses used when memory is available.
- */
-ambapp_find_buses:
- save %sp, -104, %sp
- mov %i1, %l7 /* Save second argument */
- call _nomem_ambapp_find_buses
- mov %i0, %o0
-
- /* Store result */
- st %g0, [%l7+0x00]
- st %i0, [%l7+0x04]
- st %i1, [%l7+0x08]
- st %i2, [%l7+0x0c]
- st %i3, [%l7+0x10]
- st %i4, [%l7+0x14]
- st %i5, [%l7+0x18]
-
- ret
- restore
-
-/* C-interface for _nomem_find_apb used when memory is available.
- *
- * void ambapp_find_apb(
- * struct ambapp_bus *abus,
- * unsigned int dev_vend,
- * int index,
- * struct ambapp_find_apb_info *result
- * );
- *
- */
-ambapp_find_apb:
- save %sp, -104, %sp
-
- mov %i3, %l7 /* Save second argument */
- mov %i1, %o1
- mov %i2, %o2
-
- /* Initialize buses available in system */
- ld [%i0+0x08], %i1
- ld [%i0+0x0c], %i2
- ld [%i0+0x10], %i3
- ld [%i0+0x14], %i4
- ld [%i0+0x18], %i5
-
- call _nomem_find_apb
- ld [%i0+0x04], %i0
-
- st %o2, [%l7+0x08] /* Decremented Index */
- st %o3, [%l7] /* PnP configuration address of APB Device */
- st %o4, [%l7+0x04] /* AHB Bus Index of AHB/APB bridge and APB Device */
- mov %o0, %i0
- ret
- restore
-
-/* C-interface for _nomem_find_ahb used when memory is available.
- *
- * void ambapp_find_ahb(
- * struct ambapp_bus *abus,
- * unsigned int dev_vend,
- * int index,
- * int type,
- * struct ambapp_find_ahb_info *result
- * );
- *
- */
-ambapp_find_ahb:
- save %sp, -104, %sp
-
- mov %i4, %l7 /* Save second argument */
- clr %o0
- mov %i1, %o1
- mov %i2, %o2
- clr %o3
- clr %o4
- mov %i3, %o5
-
- /* Initialize buses available in system */
- ld [%i0+0x08], %i1
- ld [%i0+0x0c], %i2
- ld [%i0+0x10], %i3
- ld [%i0+0x14], %i4
- ld [%i0+0x18], %i5
-
- call _nomem_find_ahb
- ld [%i0+0x04], %i0
-
- st %o2, [%l7+0x08] /* Decremented Index */
- st %o3, [%l7] /* PnP configuration address of AHB Device */
- st %o4, [%l7+0x04] /* AHB Bus Index of AHB Device */
- mov %o0, %i0
- ret
- restore
diff --git a/arch/sparc/cpu/leon3/cpu.c b/arch/sparc/cpu/leon3/cpu.c
deleted file mode 100644
index 149e5c69e631..000000000000
--- a/arch/sparc/cpu/leon3/cpu.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* CPU specific code for the LEON3 CPU
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <ambapp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void _reset_reloc(void);
-
-int leon_cpu_cnt = 1;
-int leon_ver = 3;
-unsigned int leon_cpu_freq = CONFIG_SYS_CLK_FREQ;
-
-int cpu_freq(void)
-{
- ambapp_ahbdev dev;
-
- if (leon_ver == 3) {
- ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER,
- GAISLER_LEON3, 0, &dev);
- } else {
- ambapp_ahbmst_find(&ambapp_plb, VENDOR_GAISLER,
- GAISLER_LEON4, 0, &dev);
- }
-
- leon_cpu_freq = ambapp_bus_freq(&ambapp_plb, dev.ahb_bus_index);
-
- return 0;
-}
-
-int checkcpu(void)
-{
- int cnt;
- char str[4];
-
- /* check LEON version here */
- cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER, GAISLER_LEON3);
- if (cnt <= 0) {
- cnt = ambapp_ahbmst_count(&ambapp_plb, VENDOR_GAISLER,
- GAISLER_LEON4);
- if (cnt > 0)
- leon_ver = 4;
- }
-
- cpu_freq();
-
- str[0] = '\0';
- if (cnt > 1) {
- leon_cpu_cnt = cnt;
- str[0] = '0' + cnt;
- str[1] = 'x';
- str[2] = '\0';
- }
- printf("CPU: %sLEON%d @ %dMHz\n", str, leon_ver,
- leon_cpu_freq / 1000000);
-
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-int print_cpuinfo(void)
-{
- printf("CPU: LEON3\n");
- return 0;
-}
-
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-void cpu_reset(void)
-{
- /* Interrupts off */
- disable_interrupts();
-
- /* jump to restart in flash */
- _reset_reloc();
-}
-
-int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- cpu_reset();
-
- return 1;
-
-}
-
-u64 flash_read64(void *addr)
-{
- return __raw_readq(addr);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_GRETH
-int cpu_eth_init(bd_t *bis)
-{
- return greth_initialize(bis);
-}
-#endif
diff --git a/arch/sparc/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c
deleted file mode 100644
index f25388cf8411..000000000000
--- a/arch/sparc/cpu/leon3/cpu_init.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Initializes CPU and basic hardware such as memory
- * controllers, IRQ controller and system timer 0.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/asi.h>
-#include <asm/leon.h>
-#include <asm/io.h>
-#include <ambapp.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-#include <debug_uart.h>
-
-#include <config.h>
-
-/* Default Plug&Play I/O area */
-#ifndef CONFIG_AMBAPP_IOAREA
-#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
-#endif
-
-/* Select which TIMER that will become the time base */
-#ifndef CONFIG_SYS_GRLIB_GPTIMER_INDEX
-#define CONFIG_SYS_GRLIB_GPTIMER_INDEX 0
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ambapp_dev_irqmp *irqmp = NULL;
-
-/*
- * Breath some life into the CPU...
- *
- * Run from FLASH/PROM:
- * - until memory controller is set up, only registers available
- * - memory controller has already been setup up, stack can be used
- * - no global variables available for writing
- * - constants available
- */
-void cpu_init_f(void)
-{
-#ifdef CONFIG_DEBUG_UART
- debug_uart_init();
-#endif
-}
-
-/* If cache snooping is available in hardware the result will be set
- * to 0x800000, otherwise 0.
- */
-static unsigned int snoop_detect(void)
-{
- unsigned int result;
- asm("lda [%%g0] 2, %0" : "=r"(result));
- return result & 0x00800000;
-}
-
-int arch_cpu_init(void)
-{
- ambapp_apbdev apbdev;
- int index;
-
- gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
- gd->arch.snooping_available = snoop_detect();
-
- /* Initialize the AMBA Plug & Play bus structure, the bus
- * structure represents the AMBA bus that the CPU is located at.
- */
- ambapp_bus_init(CONFIG_AMBAPP_IOAREA, CONFIG_SYS_CLK_FREQ, &ambapp_plb);
-
- /* Initialize/clear all the timers in the system.
- */
- for (index = 0; ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER,
- GAISLER_GPTIMER, index, &apbdev) == 1; index++) {
- ambapp_dev_gptimer *timer;
- unsigned int bus_freq;
- int i, ntimers;
-
- timer = (ambapp_dev_gptimer *)apbdev.address;
-
- /* Different buses may have different frequency, the
- * frequency of the bus tell in which frequency the timer
- * prescaler operates.
- */
- bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
- /* Initialize prescaler common to all timers to 1MHz */
- timer->scalar = timer->scalar_reload =
- (((bus_freq / 1000) + 500) / 1000) - 1;
-
- /* Clear all timers */
- ntimers = timer->config & 0x7;
- for (i = 0; i < ntimers; i++) {
- timer->e[i].ctrl = GPTIMER_CTRL_IP;
- timer->e[i].rld = 0;
- timer->e[i].ctrl = GPTIMER_CTRL_LD;
- }
- }
-
- return 0;
-}
-
-/*
- * initialize higher level parts of CPU like time base and timers
- */
-int cpu_init_r(void)
-{
- ambapp_apbdev apbdev;
- int cpu;
-
- /*
- * Find AMBA APB IRQMP Controller,
- */
- if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER,
- GAISLER_IRQMP, 0, &apbdev) != 1) {
- panic("%s: IRQ controller not found\n", __func__);
- return -1;
- }
- irqmp = (ambapp_dev_irqmp *)apbdev.address;
-
- /* initialize the IRQMP */
- irqmp->ilevel = 0xf; /* all IRQ off */
- irqmp->iforce = 0;
- irqmp->ipend = 0;
- irqmp->iclear = 0xfffe; /* clear all old pending interrupts */
- for (cpu = 0; cpu < 16; cpu++) {
- /* mask and clear force for all IRQs on CPU[N] */
- irqmp->cpu_mask[cpu] = 0;
- irqmp->cpu_force[cpu] = 0;
- }
-
- return 0;
-}
-
- ;
-int timer_init(void)
-{
- ambapp_dev_gptimer_element *tmr;
- ambapp_dev_gptimer *gptimer;
- ambapp_apbdev apbdev;
- unsigned bus_freq;
-
- if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER,
- CONFIG_SYS_GRLIB_GPTIMER_INDEX, &apbdev) != 1) {
- panic("%s: gptimer not found!\n", __func__);
- return -1;
- }
-
- gptimer = (ambapp_dev_gptimer *) apbdev.address;
-
- /* Different buses may have different frequency, the
- * frequency of the bus tell in which frequency the timer
- * prescaler operates.
- */
- bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
- /* initialize prescaler common to all timers to 1MHz */
- gptimer->scalar = gptimer->scalar_reload =
- (((bus_freq / 1000) + 500) / 1000) - 1;
-
- tmr = (ambapp_dev_gptimer_element *)&gptimer->e[0];
-
- tmr->val = 0;
- tmr->rld = ~0;
- tmr->ctrl = GPTIMER_CTRL_EN | GPTIMER_CTRL_RS | GPTIMER_CTRL_LD;
-
- CONFIG_SYS_TIMER_COUNTER = (void *)&tmr->val;
- return 0;
-}
diff --git a/arch/sparc/cpu/leon3/interrupts.c b/arch/sparc/cpu/leon3/interrupts.c
deleted file mode 100644
index 00c3288774fb..000000000000
--- a/arch/sparc/cpu/leon3/interrupts.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com
- *
- * (C) Copyright 2006
- * Detlev Zundel, DENX Software Engineering, dzu at denx.de
- *
- * (C) Copyright -2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/stack.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <asm/irq.h>
-
-#include <asm/leon.h>
-#include <ambapp.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-
-/* 15 normal irqs and a non maskable interrupt */
-#define NR_IRQS 15
-
-struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- unsigned int count;
-};
-
-extern ambapp_dev_irqmp *irqmp;
-extern ambapp_dev_gptimer *gptimer;
-
-static struct irq_action irq_handlers[NR_IRQS] = { {0}, };
-static int spurious_irq_cnt = 0;
-static int spurious_irq = 0;
-
-static inline unsigned int irqmp_get_irqmask(unsigned int irq)
-{
- if ((irq < 0) || (irq >= NR_IRQS)) {
- return 0;
- } else {
- return (1 << irq);
- }
-
-}
-
-static void leon3_ic_disable(unsigned int irq)
-{
- unsigned int mask, pil;
- if (!irqmp)
- return;
-
- pil = intLock();
-
- /* get mask of interrupt */
- mask = irqmp_get_irqmask(irq);
-
- /* set int level */
- irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) & (~mask);
-
- intUnlock(pil);
-}
-
-static void leon3_ic_enable(unsigned int irq)
-{
- unsigned int mask, pil;
- if (!irqmp)
- return;
-
- pil = intLock();
-
- /* get mask of interrupt */
- mask = irqmp_get_irqmask(irq);
-
- /* set int level */
- irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) | mask;
-
- intUnlock(pil);
-
-}
-
-void handler_irq(int irq, struct pt_regs *regs)
-{
- if (irq_handlers[irq].handler) {
- if (((unsigned int)irq_handlers[irq].handler > CONFIG_SYS_RAM_END) ||
- ((unsigned int)irq_handlers[irq].handler < CONFIG_SYS_RAM_BASE)
- ) {
- printf("handler_irq: bad handler: %x, irq number %d\n",
- (unsigned int)irq_handlers[irq].handler, irq);
- return;
- }
- irq_handlers[irq].handler(irq_handlers[irq].arg);
- irq_handlers[irq].count++;
- } else {
- spurious_irq_cnt++;
- spurious_irq = irq;
- }
-}
-
-void leon3_force_int(int irq)
-{
- if (!irqmp || (irq >= NR_IRQS) || (irq < 0))
- return;
- printf("Forcing interrupt %d\n", irq);
-
- irqmp->iforce = SPARC_NOCACHE_READ(&irqmp->iforce) | (1 << irq);
-}
-
-/****************************************************************************/
-
-int interrupt_init_cpu(void)
-{
-
- return (0);
-}
-
-/****************************************************************************/
-
-/*
- * Install and free a interrupt handler.
- */
-
-void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
-{
- if (irq < 0 || irq >= NR_IRQS) {
- printf("irq_install_handler: bad irq number %d\n", irq);
- return;
- }
-
- if (irq_handlers[irq].handler != NULL)
- printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
- (ulong) handler, (ulong) irq_handlers[irq].handler);
-
- if (((unsigned int)handler > CONFIG_SYS_RAM_END) ||
- ((unsigned int)handler < CONFIG_SYS_RAM_BASE)
- ) {
- printf("irq_install_handler: bad handler: %x, irq number %d\n",
- (unsigned int)handler, irq);
- return;
- }
- irq_handlers[irq].handler = handler;
- irq_handlers[irq].arg = arg;
-
- /* enable irq on IRQMP hardware */
- leon3_ic_enable(irq);
-
-}
-
-void irq_free_handler(int irq)
-{
- if (irq < 0 || irq >= NR_IRQS) {
- printf("irq_free_handler: bad irq number %d\n", irq);
- return;
- }
-
- /* disable irq on IRQMP hardware */
- leon3_ic_disable(irq);
-
- irq_handlers[irq].handler = NULL;
- irq_handlers[irq].arg = NULL;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_IRQ)
-void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
-{
- int irq;
- unsigned int pil = get_pil();
- printf("PIL level: %u\n\r", pil);
- printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
- spurious_irq_cnt, spurious_irq);
-
- puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
-
- for (irq = 0; irq < NR_IRQS; irq++) {
- if (irq_handlers[irq].handler != NULL) {
- printf("%02d %p %p %d\n", irq,
- irq_handlers[irq].handler,
- irq_handlers[irq].arg,
- irq_handlers[irq].count);
- }
- }
-}
-#endif
diff --git a/arch/sparc/cpu/leon3/memcfg.c b/arch/sparc/cpu/leon3/memcfg.c
deleted file mode 100644
index b9eda440e226..000000000000
--- a/arch/sparc/cpu/leon3/memcfg.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* GRLIB Memory controller setup. The register values are used
- * from the associated low level assembler routine implemented
- * in memcfg_low.S.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ambapp.h>
-#include "memcfg.h"
-#include <config.h>
-
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
-struct mctrl_setup esa_mctrl1_cfg = {
- .reg_mask = 0x7,
- .regs = {
- {
- .mask = 0x00000300,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3,
- },
- }
-};
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
-struct mctrl_setup esa_mctrl2_cfg = {
- .reg_mask = 0x7,
- .regs = {
- {
- .mask = 0x00000300,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG1,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG2,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_ESA_MCTRL2_CFG3,
- },
- }
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-struct mctrl_setup gaisler_ftmctrl1_cfg = {
- .reg_mask = 0x7,
- .regs = {
- {
- .mask = 0x00000300,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3,
- },
- }
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
-struct mctrl_setup gaisler_ftmctrl2_cfg = {
- .reg_mask = 0x7,
- .regs = {
- {
- .mask = 0x00000300,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG1,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG2,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2_CFG3,
- },
- }
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-struct mctrl_setup gaisler_sdctrl1_cfg = {
- .reg_mask = 0x1,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL1_CTRL,
- },
- }
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
-struct mctrl_setup gaisler_sdctrl2_cfg = {
- .reg_mask = 0x1,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_SDCTRL2_CTRL,
- },
- }
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-struct ahbmctrl_setup gaisler_ddr2spa1_cfg = {
- .ahb_mbar_no = 1,
- .reg_mask = 0xd,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG1,
- },
- { 0x00000000, 0},
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG3,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1_CFG4,
- },
- }
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
-struct ahbmctrl_setup gaisler_ddr2spa2_cfg = {
- .ahb_mbar_no = 1,
- .reg_mask = 0xd,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG1,
- },
- { 0x00000000, 0},
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG3,
- },
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2_CFG4,
- },
- }
-};
-#endif
-#endif
-
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-struct ahbmctrl_setup gaisler_ddrspa1_cfg = {
- .ahb_mbar_no = 1,
- .reg_mask = 0x1,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL,
- },
- }
-};
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
-struct ahbmctrl_setup gaisler_ddrspa2_cfg = {
- .ahb_mbar_no = 1,
- .reg_mask = 0x1,
- .regs = {
- {
- .mask = 0x00000000,
- .value = CONFIG_SYS_GRLIB_GAISLER_DDRSPA2_CTRL,
- },
- }
-};
-#endif
-#endif
-
-struct grlib_mctrl_handler grlib_mctrl_handlers[] = {
-/* ESA MCTRL (PROM/FLASH/IO/SRAM/SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL1
- {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
- _nomem_mctrl_init, (void *)&esa_mctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_ESA_MCTRL2
- {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_ESA, ESA_MCTRL),
- _nomem_mctrl_init, (void *)&esa_mctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER Fault Tolerant Memory controller (PROM/FLASH/IO/SRAM/SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
- {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
- _nomem_mctrl_init, (void *)&gaisler_ftmctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_FTMCTRL2
- {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_FTMCTRL),
- _nomem_mctrl_init, (void *)&gaisler_ftmctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER SDRAM-only Memory controller (SDRAM) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
- {DEV_APB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
- _nomem_mctrl_init, (void *)&gaisler_sdctrl1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_SDCTRL2
- {DEV_APB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_SDCTRL),
- _nomem_mctrl_init, (void *)&gaisler_sdctrl2_cfg},
-#endif
-#endif
-
-/* GAISLER DDR Memory controller (DDR) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
- {DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
- _nomem_ahbmctrl_init, (void *)&gaisler_ddrspa1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDRSPA2
- {DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDRSP),
- _nomem_ahbmctrl_init, (void *)&gaisler_ddrspa2_cfg},
-#endif
-#endif
-
-/* GAISLER DDR2 Memory controller (DDR2) */
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
- {DEV_AHB_SLV, 0, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
- _nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa1_cfg},
-#ifdef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA2
- {DEV_AHB_SLV, 1, MH_UNUSED, AMBA_PNP_ID(VENDOR_GAISLER, GAISLER_DDR2SP),
- _nomem_ahbmctrl_init, (void *)&gaisler_ddr2spa2_cfg},
-#endif
-#endif
-
- /* Mark end */
- MH_END
-};
diff --git a/arch/sparc/cpu/leon3/memcfg.h b/arch/sparc/cpu/leon3/memcfg.h
deleted file mode 100644
index a524896e5ad0..000000000000
--- a/arch/sparc/cpu/leon3/memcfg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* GRLIB Memory controller setup structures
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MEMCFG_H__
-#define __MEMCFG_H__
-
-/*********** Low Level Memory Controller Initalization ***********/
-
-#ifndef __ASSEMBLER__
-
-struct grlib_mctrl_handler;
-
-typedef void (*mctrl_handler_t)(
- struct grlib_mctrl_handler *dev,
- void *conf,
- unsigned int ioarea
- );
-
-/* Memory Controller Handler Structure */
-struct grlib_mctrl_handler {
- unsigned char type; /* 0x00. MASK: AHB MST&SLV, APB SLV */
- char index; /* 0x01. Unit number, 0, 1, 2... */
- char unused[2]; /* 0x02 */
- unsigned int ven_dev; /* 0x04. Device and Vendor */
- mctrl_handler_t func; /* 0x08. Memory Controller Handler */
- void *priv; /* 0x0c. Optional private data, ptr to
- * info how to set up controller */
-};
-
-extern struct grlib_mctrl_handler grlib_mctrl_handlers[];
-
-#endif
-
-#define MH_STRUCT_SIZE (4*4)
-#define MH_TYPE 0x00
-#define MH_INDEX 0x01
-#define MH_VENDOR_DEVICE 0x04
-#define MH_FUNC 0x08
-#define MH_PRIV 0x0c
-
-#define MH_TYPE_NONE DEV_NONE
-#define MH_TYPE_AHB_MST DEV_AHB_MST
-#define MH_TYPE_AHB_SLV DEV_AHB_SLV
-#define MH_TYPE_APB_SLV DEV_APB_SLV
-
-#define MH_UNUSED {0, 0}
-#define MH_END {DEV_NONE, 0, MH_UNUSED, AMBA_PNP_ID(0, 0), 0, 0}
-
-/*********** Low Level Memory Controller Initalization Handlers ***********/
-
-#ifndef __ASSEMBLER__
-extern void _nomem_mctrl_init(
- struct grlib_mctrl_handler *dev,
- void *conf,
- unsigned int ioarea_apbmst);
-
-struct mctrl_setup {
- unsigned int reg_mask; /* Which registers to write */
- struct {
- unsigned int mask; /* Mask used keep reg bits unchanged */
- unsigned int value; /* Value written to register */
- } regs[8];
-};
-
-extern void _nomem_ahbmctrl_init(
- struct grlib_mctrl_handler *dev,
- void *conf,
- unsigned int ioarea_apbmst);
-
-struct ahbmctrl_setup {
- int ahb_mbar_no; /* MBAR to get register address from */
- unsigned int reg_mask; /* Which registers to write */
- struct {
- unsigned int mask; /* Mask used keep reg bits unchanged */
- unsigned int value; /* Value written to register */
- } regs[8];
-};
-#endif
-
-/* mctrl_setup data structure defines */
-#define NREGS_OFS 0
-#define REGS_OFS 0x4
-#define REGS_SIZE 8
-
-#endif
diff --git a/arch/sparc/cpu/leon3/memcfg_low.S b/arch/sparc/cpu/leon3/memcfg_low.S
deleted file mode 100644
index 84a81a90a9af..000000000000
--- a/arch/sparc/cpu/leon3/memcfg_low.S
+++ /dev/null
@@ -1,253 +0,0 @@
-/* This is the memory initialization functions, the function
- * implemented below initializes each memory controller
- * found and specified by the input grlib_mctrl_handler structure.
- *
- * After the memory controllers have been initialized the stack
- * can be used.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <ambapp.h>
-#include "memcfg.h"
-#include <config.h>
-
- .seg "text"
- .globl _nomem_memory_ctrl_init
- .globl _nomem_mctrl_init, _nomem_ahbmctrl_init
- .extern _nomem_find_apb
- .extern _nomem_find_ahb
-
-
-/* FUNCTION
- * _nomem_memory_controller_init(struct grlib_mctrl_handler *mem_handlers)
- *
- * Initialize AMBA devices, _nomem_amba_init() has prepared i0-i5
- * with the AHB buses on the system.
- *
- * For each entry in mem_handlers find the VENDOR:DEVICE and handle it
- * by calling the handler function pointer.
- *
- * Constraints:
- * i6, i7, o6, l7, l6, g3, g4, g5, g6, g7 is used by caller
- * o7 is return address
- * l5 reserved for this function for future use.
- *
- * Arguments
- * - o0 Pointer to memory handler array
- *
- * Results
- * - o0 Number of memory controllers found
- *
- * Clobbered
- * - o0 (Current AHB slave conf address)
- * - l0 (mem handler entry address)
- * - l1 (Return value, number of memory controllers found)
- * - o7 (function pointer)
- * - l0, l1, l2, l3, l4, g1, g2 (used by _nomem_ambapp_find_buses)
- * - o0, o1, o2, o3, o4, o5 (Used as arguments)
- *
- * - g1 ( level 1 return address)
- * - g2 ( level 2 return address)
- */
-
-_nomem_memory_ctrl_init:
- /* At this point all AHB buses has been found and the I/O Areas of
- * all AHB buses is stored in the i0-i5 registers. Max 6 buses. Next,
- * memory controllers are found by searching all buses for matching
- * VENDOR:DEVICE. The VENDOR:DEVICE to search for are taken from the
- * mem_handlers array. For each match the function pointer stored in
- * the mem_handler entry is called to handle the hardware setup.
- */
- mov %o7, %g1 /* Save return address */
- mov %o0, %l0
- mov %g0, %l1 /* The return value */
-
-.L_do_one_mem_handler:
- ld [%l0 + MH_FUNC], %o7
- cmp %o7, %g0
- be .L_all_mctrl_handled
- nop
-
- /*** Scan for memory controller ***/
-
- /* Set up argments, o5 not used by _nomem_find_apb */
- ldub [%l0 + MH_TYPE], %o5
- clr %o4
- clr %o3
- ldub [%l0 + MH_INDEX], %o2
- ld [%l0 + MH_VENDOR_DEVICE], %o1
-
- /* An empty config? */
- cmp %o5, DEV_NONE
- beq .L_all_mctrl_next
-
- /* Select function (APB or AHB) */
- cmp %o5, DEV_APB_SLV
- bne .L_find_ahb_memctrl
- clr %o0
-.L_find_apb_memctrl:
- call _nomem_find_apb /* Scan for APB slave device */
- nop
-
- /* o3 = iobar address
- * o4 = AHB Bus index
- *
- * REG ADR = ((iobar >> 12) & (iobar << 4) & 0xfff00) | "APB Base"
- */
- ld [%o3 + AMBA_APB_IOBAR_OFS], %o5
- srl %o5, 12, %o2
- sll %o5, 4, %o5
- and %o2, %o5, %o5
- set 0xfff00, %o2
- and %o2, %o5, %o5
- sethi %hi(0xfff00000), %o2
- and %o3, %o2, %o2
- or %o5, %o2, %o5 /* Register base address */
-
- ba .L_call_one_mem_handler
- nop
-
-.L_find_ahb_memctrl:
- call _nomem_find_ahb /* Scan for AHB Slave or Master.
- * o5 determine type. */
- nop
- clr %o5
-
- /* Call the handler function if the hardware was found
- *
- * o0 = mem_handler
- * o1 = Configuration address
- * o2 = AHB Bus index
- * o3 = APB Base register (if APB Slave)
- *
- * Constraints:
- * i0-i7, l0, l1, l5, g1, g3-g7 may no be used.
- */
-.L_call_one_mem_handler:
- cmp %o0, %g0
- be .L_all_mctrl_next
- mov %l0, %o0 /* Mem handler pointer */
- mov %o3, %o1 /* AMBA PnP Configuration address */
- mov %o4, %o2 /* AHB Bus index */
- ld [%l0 + MH_FUNC], %o7 /* Get Function pointer */
- call %o7
- mov %o5, %o3 /* APB Register Base Address */
-
- inc %l1 /* Number of Memory controllers
- * handled. */
-
- /* Do next entry in mem_handlers */
-.L_all_mctrl_next:
- ba .L_do_one_mem_handler
- add %l0, MH_STRUCT_SIZE, %l0
-
-.L_all_mctrl_handled:
- mov %g1, %o7 /* Restore return address */
- retl
- mov %l1, %o0
-
-
-
-/* Generic Memory controller initialization routine (APB Registers)
- *
- * o0 = mem_handler structure pointer
- * o1 = Configuration address
- * o2 = AHB Bus index
- * o3 = APB Base register
- *
- * Clobbered
- * o0-o4
- */
-_nomem_mctrl_init:
- ld [%o0 + MH_PRIV], %o0 /* Get Private structure */
- ld [%o0], %o1 /* Get Reg Mask */
- and %o1, 0xff, %o1
- add %o0, REGS_OFS, %o0 /* Point to first reg */
-.L_do_one_reg:
- andcc %o1, 0x1, %g0
- beq .L_do_next_reg
- ld [%o0], %o2
- ld [%o3], %o4
- and %o4, %o2, %o4
- ld [%o0 + 4], %o2
- or %o4, %o2, %o4
- st %o4, [%o3]
-
-.L_do_next_reg:
- add %o0, REGS_SIZE, %o0
- add %o3, 4, %o3
- srl %o1, 1, %o1
- cmp %o1, 0
- bne .L_do_one_reg
- nop
-
- /* No more registers to write */
- retl
- nop
-
-
-
-/* Generic Memory controller initialization routine (AHB Registers)
- *
- * o0 = mem_handler structure pointer
- * o1 = Configuration address of memory controller
- * o2 = AHB Bus index
- *
- * Clobbered
- * o0-o5
- */
-_nomem_ahbmctrl_init:
- ld [%o0 + MH_PRIV], %o0 /* Get Private structure */
-
- /* Get index of AHB MBAR to get registers from */
- ld [%o0], %o5
- add %o0, 4, %o0
-
- /* Get Address of MBAR in PnP info */
- add %o5, 4, %o5
- sll %o5, 2, %o5
- add %o5, %o1, %o5 /* Address of MBAR */
-
- /* Get Address of registers from PnP information
- * Address is in AHB I/O format, i.e. relative to bus
- *
- * ADR = (iobar & (iobar << 16) & 0xfff00000)
- * IOADR = (ADR >> 12) | "APB Base"
- */
- ld [%o5], %o5
- sll %o5, 16, %o4
- and %o5, %o4, %o5
- sethi %hi(0xfff00000), %o4
- and %o5, %o4, %o5 /* ADR */
- and %o4, %o1, %o4
- srl %o5, 12, %o5
- or %o5, %o4, %o3 /* IOADR in o3 */
-
- ld [%o0], %o1 /* Get Reg Mask */
- and %o1, 0xff, %o1
- add %o0, REGS_OFS, %o0 /* Point to first reg */
-.L_do_one_ahbreg:
- andcc %o1, 0x1, %g0
- beq .L_do_next_reg
- ld [%o0], %o2
- ld [%o3], %o4
- and %o4, %o2, %o4
- ld [%o0 + 4], %o2
- or %o4, %o2, %o4
- st %o4, [%o3]
-
-.L_do_next_ahbreg:
- add %o0, REGS_SIZE, %o0
- add %o3, 4, %o3
- srl %o1, 1, %o1
- cmp %o1, 0
- bne .L_do_one_reg
- nop
-
- /* No more registers to write */
- retl
- nop
diff --git a/arch/sparc/cpu/leon3/prom.c b/arch/sparc/cpu/leon3/prom.c
deleted file mode 100644
index 1f185b776b48..000000000000
--- a/arch/sparc/cpu/leon3/prom.c
+++ /dev/null
@@ -1,1067 +0,0 @@
-/* prom.c - emulates a sparc v0 PROM for the linux kernel.
- *
- * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de>
- * Copyright (C) 2004 Stefan Holst <mail@s-holst.de>
- * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/prom.h>
-#include <asm/machines.h>
-#include <asm/srmmu.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/leon.h>
-#include <ambapp.h>
-#include <grlib/apbuart.h>
-#include <grlib/irqmp.h>
-#include <grlib/gptimer.h>
-
-#include <config.h>
-/*
-#define PRINT_ROM_VEC
-*/
-extern struct linux_romvec *kernel_arg_promvec;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PROM_PGT __attribute__ ((__section__ (".prom.pgt")))
-#define PROM_TEXT __attribute__ ((__section__ (".prom.text")))
-#define PROM_DATA __attribute__ ((__section__ (".prom.data")))
-
-ambapp_dev_gptimer *gptimer;
-
-void *__prom_start_reloc; /* relocated prom_start address */
-
-/* for __va */
-extern int __prom_start;
-#define PAGE_OFFSET 0xf0000000
-#define phys_base CONFIG_SYS_SDRAM_BASE
-#define PROM_OFFS 8192
-#define PROM_SIZE_MASK (PROM_OFFS-1)
-#define __va(x) ( \
- (void *)( ((unsigned long)(x))-PROM_OFFS+ \
- (CONFIG_SYS_PROM_OFFSET-phys_base)+PAGE_OFFSET-CONFIG_SYS_TEXT_BASE ) \
- )
-#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CONFIG_SYS_PROM_OFFSET-CONFIG_SYS_TEXT_BASE))
-
-struct property {
- char *name;
- char *value;
- int length;
-};
-
-struct node {
- int level;
- struct property *properties;
-};
-
-static void leon_reboot(char *bcommand);
-static void leon_halt(void);
-static int leon_nbputchar(int c);
-static int leon_nbgetchar(void);
-
-static int no_nextnode(int node);
-static int no_child(int node);
-static int no_proplen(int node, char *name);
-static int no_getprop(int node, char *name, char *value);
-static int no_setprop(int node, char *name, char *value, int len);
-static char *no_nextprop(int node, char *name);
-
-static struct property PROM_TEXT *find_property(int node, char *name);
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2);
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n);
-static void PROM_TEXT leon_reboot_physical(char *bcommand);
-
-void __inline__ leon_flush_cache_all(void)
-{
- __asm__ __volatile__(" flush ");
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-void __inline__ leon_flush_tlb_all(void)
-{
- leon_flush_cache_all();
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400),
- "i"(ASI_MMUFLUSH):"memory");
-}
-
-typedef struct {
- unsigned int ctx_table[256];
- unsigned int pgd_table[256];
-} sparc_srmmu_setup;
-
-sparc_srmmu_setup srmmu_tables PROM_PGT = {
- {0},
- {0x1e,
- 0x10001e,
- 0x20001e,
- 0x30001e,
- 0x40001e,
- 0x50001e,
- 0x60001e,
- 0x70001e,
- 0x80001e,
- 0x90001e,
- 0xa0001e,
- 0xb0001e,
- 0xc0001e,
- 0xd0001e,
- 0xe0001e,
- 0xf0001e,
- 0x100001e,
- 0x110001e,
- 0x120001e,
- 0x130001e,
- 0x140001e,
- 0x150001e,
- 0x160001e,
- 0x170001e,
- 0x180001e,
- 0x190001e,
- 0x1a0001e,
- 0x1b0001e,
- 0x1c0001e,
- 0x1d0001e,
- 0x1e0001e,
- 0x1f0001e,
- 0x200001e,
- 0x210001e,
- 0x220001e,
- 0x230001e,
- 0x240001e,
- 0x250001e,
- 0x260001e,
- 0x270001e,
- 0x280001e,
- 0x290001e,
- 0x2a0001e,
- 0x2b0001e,
- 0x2c0001e,
- 0x2d0001e,
- 0x2e0001e,
- 0x2f0001e,
- 0x300001e,
- 0x310001e,
- 0x320001e,
- 0x330001e,
- 0x340001e,
- 0x350001e,
- 0x360001e,
- 0x370001e,
- 0x380001e,
- 0x390001e,
- 0x3a0001e,
- 0x3b0001e,
- 0x3c0001e,
- 0x3d0001e,
- 0x3e0001e,
- 0x3f0001e,
- 0x400001e,
- 0x410001e,
- 0x420001e,
- 0x430001e,
- 0x440001e,
- 0x450001e,
- 0x460001e,
- 0x470001e,
- 0x480001e,
- 0x490001e,
- 0x4a0001e,
- 0x4b0001e,
- 0x4c0001e,
- 0x4d0001e,
- 0x4e0001e,
- 0x4f0001e,
- 0x500001e,
- 0x510001e,
- 0x520001e,
- 0x530001e,
- 0x540001e,
- 0x550001e,
- 0x560001e,
- 0x570001e,
- 0x580001e,
- 0x590001e,
- 0x5a0001e,
- 0x5b0001e,
- 0x5c0001e,
- 0x5d0001e,
- 0x5e0001e,
- 0x5f0001e,
- 0x600001e,
- 0x610001e,
- 0x620001e,
- 0x630001e,
- 0x640001e,
- 0x650001e,
- 0x660001e,
- 0x670001e,
- 0x680001e,
- 0x690001e,
- 0x6a0001e,
- 0x6b0001e,
- 0x6c0001e,
- 0x6d0001e,
- 0x6e0001e,
- 0x6f0001e,
- 0x700001e,
- 0x710001e,
- 0x720001e,
- 0x730001e,
- 0x740001e,
- 0x750001e,
- 0x760001e,
- 0x770001e,
- 0x780001e,
- 0x790001e,
- 0x7a0001e,
- 0x7b0001e,
- 0x7c0001e,
- 0x7d0001e,
- 0x7e0001e,
- 0x7f0001e,
- 0x800001e,
- 0x810001e,
- 0x820001e,
- 0x830001e,
- 0x840001e,
- 0x850001e,
- 0x860001e,
- 0x870001e,
- 0x880001e,
- 0x890001e,
- 0x8a0001e,
- 0x8b0001e,
- 0x8c0001e,
- 0x8d0001e,
- 0x8e0001e,
- 0x8f0001e,
- 0x900001e,
- 0x910001e,
- 0x920001e,
- 0x930001e,
- 0x940001e,
- 0x950001e,
- 0x960001e,
- 0x970001e,
- 0x980001e,
- 0x990001e,
- 0x9a0001e,
- 0x9b0001e,
- 0x9c0001e,
- 0x9d0001e,
- 0x9e0001e,
- 0x9f0001e,
- 0xa00001e,
- 0xa10001e,
- 0xa20001e,
- 0xa30001e,
- 0xa40001e,
- 0xa50001e,
- 0xa60001e,
- 0xa70001e,
- 0xa80001e,
- 0xa90001e,
- 0xaa0001e,
- 0xab0001e,
- 0xac0001e,
- 0xad0001e,
- 0xae0001e,
- 0xaf0001e,
- 0xb00001e,
- 0xb10001e,
- 0xb20001e,
- 0xb30001e,
- 0xb40001e,
- 0xb50001e,
- 0xb60001e,
- 0xb70001e,
- 0xb80001e,
- 0xb90001e,
- 0xba0001e,
- 0xbb0001e,
- 0xbc0001e,
- 0xbd0001e,
- 0xbe0001e,
- 0xbf0001e,
- 0xc00001e,
- 0xc10001e,
- 0xc20001e,
- 0xc30001e,
- 0xc40001e,
- 0xc50001e,
- 0xc60001e,
- 0xc70001e,
- 0xc80001e,
- 0xc90001e,
- 0xca0001e,
- 0xcb0001e,
- 0xcc0001e,
- 0xcd0001e,
- 0xce0001e,
- 0xcf0001e,
- 0xd00001e,
- 0xd10001e,
- 0xd20001e,
- 0xd30001e,
- 0xd40001e,
- 0xd50001e,
- 0xd60001e,
- 0xd70001e,
- 0xd80001e,
- 0xd90001e,
- 0xda0001e,
- 0xdb0001e,
- 0xdc0001e,
- 0xdd0001e,
- 0xde0001e,
- 0xdf0001e,
- 0xe00001e,
- 0xe10001e,
- 0xe20001e,
- 0xe30001e,
- 0xe40001e,
- 0xe50001e,
- 0xe60001e,
- 0xe70001e,
- 0xe80001e,
- 0xe90001e,
- 0xea0001e,
- 0xeb0001e,
- 0xec0001e,
- 0xed0001e,
- 0xee0001e,
- 0xef0001e,
- 0x400001e /* default */
- }
-};
-
-/* a self contained prom info structure */
-struct leon_reloc_func {
- struct property *(*find_property) (int node, char *name);
- int (*strcmp) (char *s1, char *s2);
- void *(*memcpy) (void *dest, const void *src, size_t n);
- void (*reboot_physical) (char *cmd);
- ambapp_dev_apbuart *leon3_apbuart;
-};
-
-struct leon_prom_info {
- int freq_khz;
- int leon_nctx;
- int mids[32];
- int baudrates[2];
- struct leon_reloc_func reloc_funcs;
- struct property root_properties[4];
- struct property cpu_properties[7];
-#undef CPUENTRY
-#define CPUENTRY(idx) struct property cpu_properties##idx[4]
- CPUENTRY(1);
- CPUENTRY(2);
- CPUENTRY(3);
- CPUENTRY(4);
- CPUENTRY(5);
- CPUENTRY(6);
- CPUENTRY(7);
- CPUENTRY(8);
- CPUENTRY(9);
- CPUENTRY(10);
- CPUENTRY(11);
- CPUENTRY(12);
- CPUENTRY(13);
- CPUENTRY(14);
- CPUENTRY(15);
- CPUENTRY(16);
- CPUENTRY(17);
- CPUENTRY(18);
- CPUENTRY(19);
- CPUENTRY(20);
- CPUENTRY(21);
- CPUENTRY(22);
- CPUENTRY(23);
- CPUENTRY(24);
- CPUENTRY(25);
- CPUENTRY(26);
- CPUENTRY(27);
- CPUENTRY(28);
- CPUENTRY(29);
- CPUENTRY(30);
- CPUENTRY(31);
- struct idprom idprom;
- struct linux_nodeops nodeops;
- struct linux_mlist_v0 *totphys_p;
- struct linux_mlist_v0 totphys;
- struct linux_mlist_v0 *avail_p;
- struct linux_mlist_v0 avail;
- struct linux_mlist_v0 *prommap_p;
- void (*synchook) (void);
- struct linux_arguments_v0 *bootargs_p;
- struct linux_arguments_v0 bootargs;
- struct linux_romvec romvec;
- struct node nodes[35];
- char s_device_type[12];
- char s_cpu[4];
- char s_mid[4];
- char s_idprom[7];
- char s_compatability[14];
- char s_leon2[6];
- char s_mmu_nctx[9];
- char s_frequency[16];
- char s_uart1_baud[11];
- char s_uart2_baud[11];
- char arg[256];
-};
-
-/* static prom info */
-static struct leon_prom_info PROM_DATA spi = {
- CONFIG_SYS_CLK_FREQ / 1000,
- 256,
- {
-#undef CPUENTRY
-#define CPUENTRY(idx) idx
- CPUENTRY(0),
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- 31},
- {38400, 38400},
- {
- __va(find_property),
- __va(leon_strcmp),
- __va(leon_memcpy),
- __phy(leon_reboot_physical),
- },
- {
- {__va(spi.s_device_type), __va(spi.s_idprom), 4},
- {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)},
- {__va(spi.s_compatability), __va(spi.s_leon2), 5},
- {NULL, NULL, -1}
- },
- {
- {__va(spi.s_device_type), __va(spi.s_cpu), 4},
- {__va(spi.s_mid), __va(&spi.mids[0]), 4},
- {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4},
- {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4},
- {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4},
- {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4},
- {NULL, NULL, -1}
- },
-#undef CPUENTRY
-#define CPUENTRY(idx) \
- { /* cpu_properties */ \
- {__va(spi.s_device_type), __va(spi.s_cpu), 4}, \
- {__va(spi.s_mid), __va(&spi.mids[idx]), 4}, \
- {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, \
- {NULL, NULL, -1} \
- }
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- CPUENTRY(31),
- {
- 0x01, /* format */
- M_LEON2 | M_LEON2_SOC, /* machine type */
- {0, 0, 0, 0, 0, 0}, /* eth */
- 0, /* date */
- 0, /* sernum */
- 0, /* checksum */
- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* reserved */
- },
- {
- __va(no_nextnode),
- __va(no_child),
- __va(no_proplen),
- __va(no_getprop),
- __va(no_setprop),
- __va(no_nextprop)
- },
- __va(&spi.totphys),
- {
- NULL,
- (char *)CONFIG_SYS_SDRAM_BASE,
- 0,
- },
- __va(&spi.avail),
- {
- NULL,
- (char *)CONFIG_SYS_SDRAM_BASE,
- 0,
- },
- NULL, /* prommap_p */
- NULL,
- __va(&spi.bootargs),
- {
- {NULL, __va(spi.arg), NULL /*... */ },
- /*... */
- },
- {
- 0,
- 0, /* sun4c v0 prom */
- 0, 0,
- {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)},
- __va(&spi.nodeops),
- NULL, {NULL /* ... */ },
- NULL, NULL,
- NULL, NULL, /* pv_getchar, pv_putchar */
- __va(leon_nbgetchar), __va(leon_nbputchar),
- NULL,
- __va(leon_reboot),
- NULL,
- NULL,
- NULL,
- __va(leon_halt),
- __va(&spi.synchook),
- {NULL},
- __va(&spi.bootargs_p)
- /*... */
- },
- {
- {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ },
- {0, __va(spi.root_properties)},
- /* cpu 0, must be spi.nodes[2] see leon_prom_init() */
- {1, __va(spi.cpu_properties)},
-
-#undef CPUENTRY
-#define CPUENTRY(idx) \
- {1, __va(spi.cpu_properties##idx) } /* cpu <idx> */
- CPUENTRY(1),
- CPUENTRY(2),
- CPUENTRY(3),
- CPUENTRY(4),
- CPUENTRY(5),
- CPUENTRY(6),
- CPUENTRY(7),
- CPUENTRY(8),
- CPUENTRY(9),
- CPUENTRY(10),
- CPUENTRY(11),
- CPUENTRY(12),
- CPUENTRY(13),
- CPUENTRY(14),
- CPUENTRY(15),
- CPUENTRY(16),
- CPUENTRY(17),
- CPUENTRY(18),
- CPUENTRY(19),
- CPUENTRY(20),
- CPUENTRY(21),
- CPUENTRY(22),
- CPUENTRY(23),
- CPUENTRY(24),
- CPUENTRY(25),
- CPUENTRY(26),
- CPUENTRY(27),
- CPUENTRY(28),
- CPUENTRY(29),
- CPUENTRY(30),
- CPUENTRY(31),
- {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }
- },
- "device_type",
- "cpu",
- "mid",
- "idprom",
- "compatability",
- "leon2",
- "mmu-nctx",
- "clock-frequency",
- "uart1_baud",
- "uart2_baud",
- CONFIG_DEFAULT_KERNEL_COMMAND_LINE
-};
-
-/* from arch/sparc/kernel/setup.c */
-#define RAMDISK_LOAD_FLAG 0x4000
-extern unsigned short root_flags;
-extern unsigned short root_dev;
-extern unsigned short ram_flags;
-extern unsigned int sparc_ramdisk_image;
-extern unsigned int sparc_ramdisk_size;
-extern int root_mountflags;
-
-extern char initrd_end, initrd_start;
-
-/* Reboot the CPU = jump to beginning of flash again.
- *
- * Make sure that all function are inlined here.
- */
-static void PROM_TEXT leon_reboot(char *bcommand)
-{
- register char *arg = bcommand;
- void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd);
-
- /* get physical address */
- struct leon_prom_info *pspi =
- (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- unsigned int *srmmu_ctx_table;
-
- /* Turn of Interrupts */
- set_pil(0xf);
-
- /* Set kernel's context, context zero */
- srmmu_set_context(0);
-
- /* Get physical address of the MMU shutdown routine */
- reboot_physical = (void *)
- SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical);
-
- /* Now that we know the physical address of the function
- * we can make the MMU allow jumping to it.
- */
- srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr();
-
- srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table);
-
- /* get physical address of kernel's context table (assume ptd) */
- srmmu_ctx_table = (unsigned int *)
- (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4);
-
- /* enable access to physical address of MMU shutdown function */
- SPARC_BYPASS_WRITE(&srmmu_ctx_table
- [((unsigned int)reboot_physical) >> 24],
- (((unsigned int)reboot_physical & 0xff000000) >> 4) |
- 0x1e);
-
- /* flush TLB cache */
- leon_flush_tlb_all();
-
- /* flash instruction & data cache */
- sparc_icache_flush_all();
- sparc_dcache_flush_all();
-
- /* jump to physical address function
- * so that when the MMU is disabled
- * we can continue to execute
- */
- reboot_physical(arg);
-}
-
-static void PROM_TEXT leon_reboot_physical(char *bcommand)
-{
- void __attribute__ ((noreturn)) (*reset) (void);
-
- /* Turn off MMU */
- srmmu_set_mmureg(0);
-
- /* Hardcoded start address */
- reset = CONFIG_SYS_MONITOR_BASE;
-
- /* flush data cache */
- sparc_dcache_flush_all();
-
- /* flush instruction cache */
- sparc_icache_flush_all();
-
- /* Jump to start in Flash */
- reset();
-}
-
-static void PROM_TEXT leon_halt(void)
-{
- while (1) ;
-}
-
-/* get single char, don't care for blocking*/
-static int PROM_TEXT leon_nbgetchar(void)
-{
- return -1;
-}
-
-/* put single char, don't care for blocking*/
-static int PROM_TEXT leon_nbputchar(int c)
-{
- ambapp_dev_apbuart *uart;
-
- /* get physical address */
- struct leon_prom_info *pspi =
- (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- uart = (ambapp_dev_apbuart *)
- SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart);
-
- /* no UART? */
- if (!uart)
- return 0;
-
- /***** put char in buffer... ***********
- * Make sure all functions are inline! *
- ***************************************/
-
- /* Wait for last character to go. */
- while (!(SPARC_BYPASS_READ(&uart->status)
- & APBUART_STATUS_THE));
-
- /* Send data */
- SPARC_BYPASS_WRITE(&uart->data, c);
-
- /* Wait for data to be sent */
- while (!(SPARC_BYPASS_READ(&uart->status)
- & APBUART_STATUS_TSE));
-
- return 0;
-}
-
-/* node ops */
-
-/*#define nodes ((struct node *)__va(&pspi->nodes))*/
-#define nodes ((struct node *)(pspi->nodes))
-
-static int PROM_TEXT no_nextnode(int node)
-{
- /* get physical address */
- struct leon_prom_info *pspi =
- (void *)(CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (nodes[node].level == nodes[node + 1].level)
- return node + 1;
- return -1;
-}
-
-static int PROM_TEXT no_child(int node)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (nodes[node].level == nodes[node + 1].level - 1)
- return node + 1;
- return -1;
-}
-
-static struct property PROM_TEXT *find_property(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = &nodes[node].properties[0];
- while (prop && prop->name) {
- if (pspi->reloc_funcs.strcmp(prop->name, name) == 0)
- return prop;
- prop++;
- }
- return NULL;
-}
-
-static int PROM_TEXT no_proplen(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = pspi->reloc_funcs.find_property(node, name);
- if (prop)
- return prop->length;
- return -1;
-}
-
-static int PROM_TEXT no_getprop(int node, char *name, char *value)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- struct property *prop = pspi->reloc_funcs.find_property(node, name);
- if (prop) {
- pspi->reloc_funcs.memcpy(value, prop->value, prop->length);
- return 1;
- }
- return -1;
-}
-
-static int PROM_TEXT no_setprop(int node, char *name, char *value, int len)
-{
- return -1;
-}
-
-static char PROM_TEXT *no_nextprop(int node, char *name)
-{
- /* get physical address */
- struct leon_prom_info *pspi = (struct leon_prom_info *)
- (CONFIG_SYS_PROM_OFFSET + sizeof(srmmu_tables));
- struct property *prop;
-
- /* convert into virtual address */
- pspi = (struct leon_prom_info *)
- (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET);
-
- if (!name || !name[0])
- return nodes[node].properties[0].name;
-
- prop = pspi->reloc_funcs.find_property(node, name);
- if (prop)
- return prop[1].name;
- return NULL;
-}
-
-static int PROM_TEXT leon_strcmp(const char *s1, const char *s2)
-{
- register char result;
-
- while (1) {
- result = *s1 - *s2;
- if (result || !*s1)
- break;
- s2++;
- s1++;
- }
-
- return result;
-}
-
-static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n)
-{
- char *dst = (char *)dest, *source = (char *)src;
-
- while (n--) {
- *dst = *source;
- dst++;
- source++;
- }
- return dest;
-}
-
-#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp))
-
-void leon_prom_init(struct leon_prom_info *pspi)
-{
- unsigned long i;
- unsigned char cksum, *ptr;
- char *addr_str, *end;
- unsigned long sp;
- GETREGSP(sp);
-
- pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000;
-
- /* Set Available main memory size */
- pspi->totphys.num_bytes = CONFIG_SYS_PROM_OFFSET - CONFIG_SYS_SDRAM_BASE;
- pspi->avail.num_bytes = pspi->totphys.num_bytes;
-
- /* Set the pointer to the Console UART in romvec */
- pspi->reloc_funcs.leon3_apbuart = gd->arch.uart;
-
- {
- int j = 1;
-#ifdef CONFIG_SMP
- ambapp_dev_irqmp *b;
- b = (ambapp_dev_irqmp *) leon3_getapbbase(VENDOR_GAISLER,
- GAISLER_IRQMP);
- if (b) {
- j = 1 + ((LEON3_BYPASS_LOAD_PA(&(b->mpstatus))
- >> LEON3_IRQMPSTATUS_CPUNR) & 0xf);
- }
-#endif
-#undef nodes
- pspi->nodes[2 + j].level = -1;
- pspi->nodes[2 + j].properties = __va(spi.root_properties + 3);
- }
-
- /* Set Ethernet MAC address from environment */
- if ((addr_str = getenv("ethaddr")) != NULL) {
- for (i = 0; i < 6; i++) {
- pspi->idprom.id_ethaddr[i] = addr_str ?
- simple_strtoul(addr_str, &end, 16) : 0;
- if (addr_str) {
- addr_str = (*end) ? end + 1 : end;
- }
- }
- } else {
- /* HW Address not found in environment,
- * Set default HW address
- */
- pspi->idprom.id_ethaddr[0] = 0;
- pspi->idprom.id_ethaddr[1] = 0;
- pspi->idprom.id_ethaddr[2] = 0;
- pspi->idprom.id_ethaddr[3] = 0;
- pspi->idprom.id_ethaddr[4] = 0;
- pspi->idprom.id_ethaddr[5] = 0;
- }
-
- ptr = (unsigned char *)&pspi->idprom;
- for (i = cksum = 0; i <= 0x0E; i++)
- cksum ^= *ptr++;
- pspi->idprom.id_cksum = cksum;
-}
-
-static inline void set_cache(unsigned long regval)
-{
- asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
-}
-
-extern unsigned short bss_start, bss_end;
-
-/* mark as section .img.main.text, to be referenced in linker script */
-int prom_init(void)
-{
- struct leon_prom_info *pspi = (void *)
- ((((unsigned int)&spi) & PROM_SIZE_MASK) + CONFIG_SYS_PROM_OFFSET);
-
- /* disable mmu */
- srmmu_set_mmureg(0x00000000);
- __asm__ __volatile__("flush\n\t");
-
- /* init prom info struct */
- leon_prom_init(pspi);
-
- kernel_arg_promvec = &pspi->romvec;
-#ifdef PRINT_ROM_VEC
- printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec));
-#endif
- return 0;
-}
-
-/* Copy current kernel boot argument to ROMvec */
-void prepare_bootargs(char *bootargs)
-{
- struct leon_prom_info *pspi;
- char *src, *dst;
- int left;
-
- /* if no bootargs set, skip copying ==> default bootline */
- if (bootargs && (*bootargs != '\0')) {
- pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) +
- CONFIG_SYS_PROM_OFFSET);
- src = bootargs;
- dst = &pspi->arg[0];
- left = 255; /* max len */
- while (*src && left > 0) {
- *dst++ = *src++;
- left--;
- }
- /* terminate kernel command line string */
- *dst = 0;
- }
-}
-
-void srmmu_init_cpu(unsigned int entry)
-{
- sparc_srmmu_setup *psrmmu_tables = (void *)
- ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) +
- CONFIG_SYS_PROM_OFFSET);
-
- /* Make context 0 (kernel's context) point
- * to our prepared memory mapping
- */
-#define PTD 1
- psrmmu_tables->ctx_table[0] =
- ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD;
-
- /* Set virtual kernel address 0xf0000000
- * to SRAM/SDRAM address.
- * Make it READ/WRITE/EXEC to SuperUser
- */
-#define PTE 2
-#define ACC_SU_ALL 0x1c
- psrmmu_tables->pgd_table[0xf0] =
- (CONFIG_SYS_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf1] =
- ((CONFIG_SYS_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf2] =
- ((CONFIG_SYS_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf3] =
- ((CONFIG_SYS_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf4] =
- ((CONFIG_SYS_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf5] =
- ((CONFIG_SYS_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf6] =
- ((CONFIG_SYS_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE;
- psrmmu_tables->pgd_table[0xf7] =
- ((CONFIG_SYS_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE;
-
- /* convert rom vec pointer to virtual address */
- kernel_arg_promvec = (struct linux_romvec *)
- (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000);
-
- /* Set Context pointer to point to context table
- * 256 contexts supported.
- */
- srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]);
-
- /* Set kernel's context, context zero */
- srmmu_set_context(0);
-
- /* Invalidate all Cache */
- __asm__ __volatile__("flush\n\t");
-
- srmmu_set_mmureg(0x00000001);
- leon_flush_tlb_all();
- leon_flush_cache_all();
-}
diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c
deleted file mode 100644
index bc6e7a172e5f..000000000000
--- a/arch/sparc/cpu/leon3/serial.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* GRLIB APBUART Serial controller driver
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <ambapp.h>
-#include <grlib/apbuart.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Select which UART that will become u-boot console */
-#ifndef CONFIG_SYS_GRLIB_APBUART_INDEX
-/* Try to use CONFIG_CONS_INDEX, if available, it is numbered from 1 */
-#ifdef CONFIG_CONS_INDEX
-#define CONFIG_SYS_GRLIB_APBUART_INDEX (CONFIG_CONS_INDEX - 1)
-#else
-#define CONFIG_SYS_GRLIB_APBUART_INDEX 0
-#endif
-#endif
-
-static unsigned apbuart_calc_scaler(unsigned apbuart_freq, unsigned baud)
-{
- return (((apbuart_freq * 10) / (baud * 8)) - 5) / 10;
-}
-
-static int leon3_serial_init(void)
-{
- ambapp_dev_apbuart *uart;
- ambapp_apbdev apbdev;
- unsigned int tmp;
-
- /* find UART */
- if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_APBUART,
- CONFIG_SYS_GRLIB_APBUART_INDEX, &apbdev) != 1) {
- gd->flags &= ~GD_FLG_SERIAL_READY;
- panic("%s: apbuart not found!\n", __func__);
- return -1; /* didn't find hardware */
- }
-
- /* found apbuart, let's init .. */
- uart = (ambapp_dev_apbuart *) apbdev.address;
-
- /* APBUART Frequency is equal to bus frequency */
- gd->arch.uart_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
-
- /* Set scaler / baud rate */
- tmp = apbuart_calc_scaler(gd->arch.uart_freq, CONFIG_BAUDRATE);
- writel(tmp, &uart->scaler);
-
- /* Let bit 11 be unchanged (debug bit for GRMON) */
- tmp = readl(&uart->ctrl) & APBUART_CTRL_DBG;
- /* Receiver & transmitter enable */
- tmp |= APBUART_CTRL_RE | APBUART_CTRL_TE;
- writel(tmp, &uart->ctrl);
-
- gd->arch.uart = uart;
- return 0;
-}
-
-static inline ambapp_dev_apbuart *leon3_get_uart_regs(void)
-{
- ambapp_dev_apbuart *uart = gd->arch.uart;
- return uart;
-}
-
-static void leon3_serial_putc_raw(const char c)
-{
- ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
- if (!uart)
- return;
-
- /* Wait for last character to go. */
- while (!(readl(&uart->status) & APBUART_STATUS_THE))
- WATCHDOG_RESET();
-
- /* Send data */
- writel(c, &uart->data);
-
-#ifdef LEON_DEBUG
- /* Wait for data to be sent */
- while (!(readl(&uart->status) & APBUART_STATUS_TSE))
- WATCHDOG_RESET();
-#endif
-}
-
-static void leon3_serial_putc(const char c)
-{
- if (c == '\n')
- leon3_serial_putc_raw('\r');
-
- leon3_serial_putc_raw(c);
-}
-
-static int leon3_serial_getc(void)
-{
- ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
- if (!uart)
- return 0;
-
- /* Wait for a character to arrive. */
- while (!(readl(&uart->status) & APBUART_STATUS_DR))
- WATCHDOG_RESET();
-
- /* Read character data */
- return readl(&uart->data);
-}
-
-static int leon3_serial_tstc(void)
-{
- ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
-
- if (!uart)
- return 0;
-
- return readl(&uart->status) & APBUART_STATUS_DR;
-}
-
-/* set baud rate for uart */
-static void leon3_serial_setbrg(void)
-{
- ambapp_dev_apbuart * const uart = leon3_get_uart_regs();
- unsigned int scaler;
-
- if (!uart)
- return;
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
-
- if (!gd->arch.uart_freq)
- gd->arch.uart_freq = CONFIG_SYS_CLK_FREQ;
-
- scaler = apbuart_calc_scaler(gd->arch.uart_freq, gd->baudrate);
-
- writel(scaler, &uart->scaler);
-}
-
-static struct serial_device leon3_serial_drv = {
- .name = "leon3_serial",
- .start = leon3_serial_init,
- .stop = NULL,
- .setbrg = leon3_serial_setbrg,
- .putc = leon3_serial_putc,
- .puts = default_serial_puts,
- .getc = leon3_serial_getc,
- .tstc = leon3_serial_tstc,
-};
-
-void leon3_serial_initialize(void)
-{
- serial_register(&leon3_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &leon3_serial_drv;
-}
-
-#ifdef CONFIG_DEBUG_UART_APBUART
-
-#include <debug_uart.h>
-
-static inline void _debug_uart_init(void)
-{
- ambapp_dev_apbuart *uart = (ambapp_dev_apbuart *)CONFIG_DEBUG_UART_BASE;
- uart->scaler = apbuart_calc_scaler(CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
- uart->ctrl = APBUART_CTRL_RE | APBUART_CTRL_TE;
-}
-
-static inline void _debug_uart_putc(int ch)
-{
- ambapp_dev_apbuart *uart = (ambapp_dev_apbuart *)CONFIG_DEBUG_UART_BASE;
- while (!(readl(&uart->status) & APBUART_STATUS_THE))
- WATCHDOG_RESET();
- writel(ch, &uart->data);
-}
-
-DEBUG_UART_FUNCS
-
-#endif
diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S
deleted file mode 100644
index 1527d72a6d79..000000000000
--- a/arch/sparc/cpu/leon3/start.S
+++ /dev/null
@@ -1,681 +0,0 @@
-/* This is where the SPARC/LEON3 starts
- *
- * Copyright (C) 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asmmacro.h>
-#include <asm/winmacro.h>
-#include <asm/psr.h>
-#include <asm/stack.h>
-#include <asm/leon.h>
-#include <ambapp.h>
-
-/* Default Plug&Play I/O area */
-#ifndef CONFIG_AMBAPP_IOAREA
-#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
-#endif
-
-/* Default number of SPARC register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#define CONFIG_SYS_SPARC_NWINDOWS 8
-#endif
-
-/* Entry for traps which jump to a programmer-specified trap handler. */
-#define TRAPR(H) \
- wr %g0, 0xfe0, %psr; \
- mov %g0, %tbr; \
- ba (H); \
- mov %g0, %wim;
-
-#define TRAP(H) \
- mov %psr, %l0; \
- ba (H); \
- nop; nop;
-
-#define TRAPI(ilevel) \
- mov ilevel, %l7; \
- mov %psr, %l0; \
- b _irq_entry; \
- mov %wim, %l3
-
-/* Unexcpected trap will halt the processor by forcing it to error state */
-#undef BAD_TRAP
-#define BAD_TRAP ta 0; nop; nop; nop;
-
-/* Software trap. Treat as BAD_TRAP for the time being... */
-#define SOFT_TRAP TRAP(_hwerr)
-
-#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */
-#define WIM_INIT 2
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#define WRITE_PAUSE nop;nop;nop
-
-WINDOWSIZE = (16 * 4)
-ARGPUSHSIZE = (6 * 4)
-ARGPUSH = (WINDOWSIZE + 4)
-MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
-
-/* Number of register windows */
-#ifndef CONFIG_SYS_SPARC_NWINDOWS
-#error Must define number of SPARC register windows, default is 8
-#endif
-
-/* Macros to load address into a register. Uses GOT table for PIC */
-#ifdef __PIC__
-
-#define SPARC_PIC_THUNK_CALL(reg) \
- sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %##reg; \
- call __sparc_get_pc_thunk.reg; \
- add %##reg, %pc10(_GLOBAL_OFFSET_TABLE_+4), %##reg;
-
-#define SPARC_LOAD_ADDRESS(sym, got, reg) \
- sethi %gdop_hix22(sym), %##reg; \
- xor %##reg, %gdop_lox10(sym), %##reg; \
- ld [%##got + %##reg], %##reg, %gdop(sym);
-
-#else
-
-#define SPARC_PIC_THUNK_CALL(reg)
-#define SPARC_LOAD_ADDRESS(sym, got, tmp) \
- set sym, %##reg;
-
-#endif
-
-#define STACK_ALIGN 8
-#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
-
- .section ".start", "ax"
- .globl _start, start, _trap_table
- .globl _irq_entry, nmi_trap
- .globl _reset_reloc
-
-/* at address 0
- * Hardware traps
- */
-start:
-_start:
-_trap_table:
- TRAPR(_hardreset); ! 00 reset trap
- BAD_TRAP; ! 01 instruction_access_exception
- BAD_TRAP; ! 02 illegal_instruction
- BAD_TRAP; ! 03 priveleged_instruction
- BAD_TRAP; ! 04 fp_disabled
- TRAP(_window_overflow); ! 05 window_overflow
- TRAP(_window_underflow); ! 06 window_underflow
- BAD_TRAP; ! 07 Memory Address Not Aligned
- BAD_TRAP; ! 08 Floating Point Exception
- BAD_TRAP; ! 09 Data Miss Exception
- BAD_TRAP; ! 0a Tagged Instruction Ovrflw
- BAD_TRAP; ! 0b Watchpoint Detected
- BAD_TRAP; ! 0c
- BAD_TRAP; ! 0d
- BAD_TRAP; ! 0e
- BAD_TRAP; ! 0f
- BAD_TRAP; ! 10
- TRAPI(1); ! 11 IRQ level 1
- TRAPI(2); ! 12 IRQ level 2
- TRAPI(3); ! 13 IRQ level 3
- TRAPI(4); ! 14 IRQ level 4
- TRAPI(5); ! 15 IRQ level 5
- TRAPI(6); ! 16 IRQ level 6
- TRAPI(7); ! 17 IRQ level 7
- TRAPI(8); ! 18 IRQ level 8
- TRAPI(9); ! 19 IRQ level 9
- TRAPI(10); ! 1a IRQ level 10
- TRAPI(11); ! 1b IRQ level 11
- TRAPI(12); ! 1c IRQ level 12
- TRAPI(13); ! 1d IRQ level 13
- TRAPI(14); ! 1e IRQ level 14
- TRAP(_nmi_trap); ! 1f IRQ level 15 /
- ! NMI (non maskable interrupt)
- BAD_TRAP; ! 20 r_register_access_error
- BAD_TRAP; ! 21 instruction access error
- BAD_TRAP; ! 22
- BAD_TRAP; ! 23
- BAD_TRAP; ! 24 co-processor disabled
- BAD_TRAP; ! 25 uniplemented FLUSH
- BAD_TRAP; ! 26
- BAD_TRAP; ! 27
- BAD_TRAP; ! 28 co-processor exception
- BAD_TRAP; ! 29 data access error
- BAD_TRAP; ! 2a division by zero
- BAD_TRAP; ! 2b data store error
- BAD_TRAP; ! 2c data access MMU miss
- BAD_TRAP; ! 2d
- BAD_TRAP; ! 2e
- BAD_TRAP; ! 2f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f
-
- /* implementaion dependent */
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b
- BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f
-
- /* Software traps, not handled */
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80-83
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84-87
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88-8b
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8c-8f
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90-93
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94-97
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98-9b
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9c-9f
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a0-a3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a4-a7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a8-ab
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ac-af
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b0-b3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b4-b7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b8-bb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! bc-bf
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c0-c3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c4-c7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c8-cb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! cc-cf
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d0-d3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d4-d7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d8-db
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! dc-df
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e0-e3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e4-e7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e8-eb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ec-ef
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f0-f3
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb
- SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff
-
- .section ".text"
- .extern _nomem_amba_init, _nomem_memory_ctrl_init
- .align 4
-
-_hardreset:
-1000:
- flush
-
- /* Enable I/D-Cache and Snooping */
- set 0x0081000f, %g2
- sta %g2, [%g0] 2
-
- mov %g0, %y
- clr %g1
- clr %g2
- clr %g3
- clr %g4
- clr %g5
- clr %g6
- clr %g7
-
- mov %asr17, %g3
- and %g3, 0x1f, %g3
-clear_window:
- mov %g0, %l0
- mov %g0, %l1
- mov %g0, %l2
- mov %g0, %l3
- mov %g0, %l4
- mov %g0, %l5
- mov %g0, %l6
- mov %g0, %l7
- mov %g0, %o0
- mov %g0, %o1
- mov %g0, %o2
- mov %g0, %o3
- mov %g0, %o4
- mov %g0, %o5
- mov %g0, %o6
- mov %g0, %o7
- subcc %g3, 1, %g3
- bge clear_window
- save
-
-wiminit:
- set WIM_INIT, %g3
- mov %g3, %wim
-
-stackinit:
- set CONFIG_SYS_INIT_SP_OFFSET, %fp
- andn %fp, 0x0f, %fp
- sub %fp, 64, %sp
-
-tbrinit:
- set CONFIG_SYS_TEXT_BASE, %g2
- wr %g0, %g2, %tbr
- nop
- nop
- nop
-
-/* Obtain the address of _GLOBAL_OFFSET_TABLE_ */
- SPARC_PIC_THUNK_CALL(l7)
-
-/* Scan AMBA Bus for AMBA buses using PnP information. All found
- * AMBA buses I/O area will be located in i0-i5 upon return.
- * The i0-i5 registers are later used by _nomem_amba_init2
- */
-ambainit:
- call _nomem_amba_init
- sethi %hi(CONFIG_AMBAPP_IOAREA), %o0
-
-/* Scan AMBA Buses for memory controllers, then initialize the
- * memory controllers. Note that before setting up the memory controller
- * the stack can not be used.
- */
-memory_ctrl_init:
- SPARC_LOAD_ADDRESS(grlib_mctrl_handlers, l7, o0)
-
- call _nomem_memory_ctrl_init
- nop
-
-/* The return valu indicate how many memory controllers where found and
- * initialized, if no memory controller was initialized, we can not continue
- * because from here on we expect memory to be working.
- */
- cmp %o0, 0
-memory_ctrl_init_failed:
- beq memory_ctrl_init_failed
- nop
-
-/*** From now on the stack can be used. ***/
-
-cpu_init_unreloc:
- call cpu_init_f
- nop
-
-board_init_unreloc:
- call board_init_f
- clr %o0 ! boot_flags
-
-dead_unreloc:
- mov 1, %g1 ! For GRMON2 to exit normally.
- ta 0 ! If board_init_f call returns.. (unlikely)
- nop
- nop
- ba dead_unreloc ! infinte loop
- nop
-
-!-------------------------------------------------------------------------------
-
-/* void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM after
- * relocating the monitor code.
- *
- * %o0 = Relocated stack pointer
- * %o1 = Relocated global data pointer
- * %o2 = Relocated text pointer
- *
- * %l7 = _GLOBAL_OFFSET_TABLE_ address
- */
- .globl relocate_code
- .type relocate_code, #function
- .align 4
-relocate_code:
- !SPARC_PIC_THUNK_CALL(l7)
-reloc:
- SPARC_LOAD_ADDRESS(_text, l7, g2) ! start address of monitor
- SPARC_LOAD_ADDRESS(__init_end, l7, g3) ! end address of monitor
- mov %o2, %g4 ! relocation address
- sub %g4, %g2, %g6 ! relocation offset
- /* copy .text & .data to relocated address */
-10: ldd [%g2], %l0
- ldd [%g2+8], %l2
- std %l0, [%g4]
- std %l2, [%g4+8]
- inc 16, %g2 ! src += 16
- cmp %g2, %g3
- bcs 10b ! while (src < end)
- inc 16, %g4 ! dst += 16
-
- clr %l0
- clr %l1
- clr %l2
- clr %l3
- clr %g2
-
-/* register g4 contain address to start
- * This means that BSS must be directly after data and code segments
- *
- * g3 is length of bss = (__bss_end-__bss_start)
- *
- */
-
- /* clear the relocated .bss area */
-clr_bss:
- SPARC_LOAD_ADDRESS(__bss_start, l7, g2)
- SPARC_LOAD_ADDRESS(__bss_end, l7, g3)
- sub %g3,%g2,%g3 ! length of .bss area
- add %g3,%g4,%g3
- /* clearing 16byte a time ==> linker script need to align to 16 byte offset */
- clr %g1 /* std %g0 uses g0 and g1 */
-20:
- std %g0, [%g4]
- std %g0, [%g4+8]
- inc 16, %g4 ! ptr += 16
- cmp %g4, %g3
- bcs 20b ! while (ptr < end)
- nop
-
- /* add offsets to GOT table */
-fixup_got:
- SPARC_LOAD_ADDRESS(__got_start, l7, g4)
- add %g4, %g6, %g4
- SPARC_LOAD_ADDRESS(__got_end, l7, g3)
- add %g3, %g6, %g3
-30: ld [%g4], %l0
-#ifdef CONFIG_RELOC_GOT_SKIP_NULL
- cmp %l0, 0
- be 32f
-#endif
- add %l0, %g6, %l0 ! relocate GOT pointer
- st %l0, [%g4]
-32: inc 4, %g4 ! ptr += 4
- cmp %g4, %g3
- bcs 30b ! while (ptr < end)
- nop
-
-prom_relocate:
- SPARC_LOAD_ADDRESS(__prom_start, l7, g2)
- SPARC_LOAD_ADDRESS(__prom_end, l7, g3)
- /*
- * Calculated addres is stored in this variable by
- * reserve_prom() function in common/board_f.c
- */
- SPARC_LOAD_ADDRESS(__prom_start_reloc, l7, g4)
- ld [%g4], %g4
-
-40: ldd [%g2], %l0
- ldd [%g2+8], %l2
- std %l0, [%g4]
- std %l2, [%g4+8]
- inc 16, %g2
- cmp %g2, %g3
- bcs 40b
- inc 16, %g4
-
-! %o0 = stack pointer (relocated)
-! %o1 = global data pointer (relocated)
-! %o2 = text pointer (relocated)
-
-! %g6 = relocation offset
-! %l7 = _GLOBAL_OFFSET_TABLE_
-
-/* Trap table has been moved, lets tell CPU about
- * the new trap table address
- */
-update_trap_table_address:
- wr %g0, %o2, %tbr
- nop
- nop
- nop
-
-update_stack_pointers:
- mov %o0, %fp
- andn %fp, 0x0f, %fp ! align to 16 bytes
- add %fp, -64, %fp ! make space for a window push
- mov %fp, %sp ! setup stack pointer
-
-jump_board_init_r:
- mov %o1, %o0 ! relocated global data pointer
- mov %o2, %o1 ! relocated text pointer
- SPARC_LOAD_ADDRESS(board_init_r, l7, o3)
- add %o3, %g6, %o3 ! add relocation offset
- call %o3
- nop
-
-dead:
- mov 1, %g1 ! For GRMON2 to exit normally.
- ta 0 ! if call returns.. (unlikely)
- nop
- b dead ! infinte loop
- nop
-
-!------------------------------------------------------------------------------
-
-/* Interrupt handler caller,
- * reg L7: interrupt number
- * reg L0: psr after interrupt
- * reg L1: PC
- * reg L2: next PC
- * reg L3: wim
- */
-_irq_entry:
- SAVE_ALL
-
- or %l0, PSR_PIL, %g2
- wr %g2, 0x0, %psr
- WRITE_PAUSE
- wr %g2, PSR_ET, %psr
- WRITE_PAUSE
- mov %l7, %o0 ! irq level
- set handler_irq, %o1
- set (CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE), %o2
- add %o1, %o2, %o1
- call %o1
- add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr
- or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq
- wr %g2, PSR_ET, %psr ! keep ET up
- WRITE_PAUSE
-
- RESTORE_ALL
-
-!------------------------------------------------------------------------------
-
-/*
- * Window overflow trap handler
- */
- .global _window_overflow
-
-_window_overflow:
-
- mov %wim, %l3 ! Calculate next WIM
- mov %g1, %l7
- srl %l3, 1, %g1
- sll %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l4
- or %g1, %l4, %g1
- save ! Get into window to be saved.
- mov %g1, %wim
- nop; nop; nop
- st %l0, [%sp + 0] ! Save window to the stack
- st %l1, [%sp + 4]
- st %l2, [%sp + 8]
- st %l3, [%sp + 12]
- st %l4, [%sp + 16]
- st %l5, [%sp + 20]
- st %l6, [%sp + 24]
- st %l7, [%sp + 28]
- st %i0, [%sp + 32]
- st %i1, [%sp + 36]
- st %i2, [%sp + 40]
- st %i3, [%sp + 44]
- st %i4, [%sp + 48]
- st %i5, [%sp + 52]
- st %i6, [%sp + 56]
- st %i7, [%sp + 60]
- restore ! Go back to trap window.
- mov %l7, %g1
- jmp %l1 ! Re-execute save.
- rett %l2
-
-/*
- * Window underflow trap handler
- */
- .global _window_underflow
-
-_window_underflow:
-
- mov %wim, %l3 ! Calculate next WIM
- srl %l3, (CONFIG_SYS_SPARC_NWINDOWS-1), %l5
- sll %l3, 1, %l4
- or %l5, %l4, %l5
- mov %l5, %wim
- nop; nop; nop
- restore ! Two restores to get into the
- restore ! window to restore
- ld [%sp + 0], %l0; ! Restore window from the stack
- ld [%sp + 4], %l1;
- ld [%sp + 8], %l2;
- ld [%sp + 12], %l3;
- ld [%sp + 16], %l4;
- ld [%sp + 20], %l5;
- ld [%sp + 24], %l6;
- ld [%sp + 28], %l7;
- ld [%sp + 32], %i0;
- ld [%sp + 36], %i1;
- ld [%sp + 40], %i2;
- ld [%sp + 44], %i3;
- ld [%sp + 48], %i4;
- ld [%sp + 52], %i5;
- ld [%sp + 56], %i6;
- ld [%sp + 60], %i7;
- save ! Get back to the trap window.
- save
- jmp %l1 ! Re-execute restore.
- rett %l2
-
-!------------------------------------------------------------------------------
-
-_nmi_trap:
- nop
- jmp %l1
- rett %l2
-
-_hwerr:
- ta 0
- nop
- nop
- b _hwerr ! loop infinite
- nop
-
-/* Registers to not touch at all. */
-#define t_psr l0 /* Set by caller */
-#define t_pc l1 /* Set by caller */
-#define t_npc l2 /* Set by caller */
-#define t_wim l3 /* Set by caller */
-#define t_twinmask l4 /* Set at beginning of this entry routine. */
-#define t_kstack l5 /* Set right before pt_regs frame is built */
-#define t_retpc l6 /* If you change this, change winmacro.h header file */
-#define t_systable l7 /* Never touch this, could be the syscall table ptr. */
-#define curptr g6 /* Set after pt_regs frame is built */
-
-trap_setup:
-/* build a pt_regs trap frame. */
- sub %fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack
- PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2)
-
- /* See if we are in the trap window. */
- mov 1, %t_twinmask
- sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
- andcc %t_twinmask, %t_wim, %g0
- beq 1f ! in trap window, clean up
- nop
-
- /*-------------------------------------------------
- * Spill , adjust %wim and go.
- */
- srl %t_wim, 0x1, %g2 ! begin computation of new %wim
-
- set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
-
- sll %t_wim, %g3, %t_wim ! NWINDOWS-1
- or %t_wim, %g2, %g2
- and %g2, 0xff, %g2
-
- save %g0, %g0, %g0 ! get in window to be saved
-
- /* Set new %wim value */
- wr %g2, 0x0, %wim
-
- /* Save the kernel window onto the corresponding stack. */
- RW_STORE(sp)
-
- restore %g0, %g0, %g0
- /*-------------------------------------------------*/
-
-1:
- /* Trap from kernel with a window available.
- * Just do it...
- */
- jmpl %t_retpc + 0x8, %g0 ! return to caller
- mov %t_kstack, %sp ! jump onto new stack
-
-#define twin_tmp1 l4
-#define glob_tmp g4
-#define curptr g6
-ret_trap_entry:
- wr %t_psr, 0x0, %psr ! enable nesting again, clear ET
-
- /* Will the rett land us in the invalid window? */
- mov 2, %g1
- sll %g1, %t_psr, %g1
-
- set CONFIG_SYS_SPARC_NWINDOWS, %g2 !NWINDOWS
-
- srl %g1, %g2, %g2
- or %g1, %g2, %g1
- rd %wim, %g2
- andcc %g2, %g1, %g0
- be 1f ! Nope, just return from the trap
- sll %g2, 0x1, %g1
-
- /* We have to grab a window before returning. */
- set (CONFIG_SYS_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1
-
- srl %g2, %g3, %g2
- or %g1, %g2, %g1
- and %g1, 0xff, %g1
-
- wr %g1, 0x0, %wim
-
- /* Grrr, make sure we load from the right %sp... */
- PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-
- restore %g0, %g0, %g0
- RW_LOAD(sp)
- b 2f
- save %g0, %g0, %g0
-
- /* Reload the entire frame in case this is from a
- * kernel system call or whatever...
- */
-1:
- PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1)
-2:
- wr %t_psr, 0x0, %psr
- nop;
- nop;
- nop
-
- jmp %t_pc
- rett %t_npc
-
-/* This is called from relocated C-code.
- * It resets the system by jumping to _start
- */
-_reset_reloc:
- set start, %l0
- call %l0
- nop
diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c
deleted file mode 100644
index 67bd1241bd27..000000000000
--- a/arch/sparc/cpu/leon3/usb_uhci.c
+++ /dev/null
@@ -1,1195 +0,0 @@
-/*
- * Part of this code has been derived from linux:
- * Universal Host Controller Interface driver for USB (take II).
- *
- * (c) 1999-2001 Georg Acher, acher at in.tum.de (executive slave) (base guitar)
- * Deti Fliegl, deti at fliegl.de (executive slave) (lead voice)
- * Thomas Sailer, sailer at ife.ee.ethz.ch (chief consultant) (cheer leader)
- * Roman Weissgaerber, weissg at vienna.at (virt root hub) (studio porter)
- * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support
- * from usb-ohci.c by Adam Richter, adam at yggdrasil.com).
- * (C) 2000 David Brownell, david-b at pacbell.net (usb-ohci.c)
- *
- * HW-initalization based on material of
- *
- * (C) Copyright 1999 Linus Torvalds
- * (C) Copyright 1999 Johannes Erdfelt
- * (C) Copyright 1999 Randy Dunlap
- * (C) Copyright 1999 Gregory P. Smith
- *
- *
- * Adapted for U-Boot:
- * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
- * (C) Copyright 2008, Daniel Hellström, daniel@gaisler.com
- * Added AMBA Plug&Play detection of GRUSB, modified interrupt handler.
- * Added cache flushes where needed.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/**********************************************************************
- * How it works:
- * -------------
- * The framelist / Transfer descriptor / Queue Heads are similar like
- * in the linux usb_uhci.c.
- *
- * During initialization, the following skeleton is allocated in init_skel:
- *
- * framespecific | common chain
- *
- * framelist[]
- * [ 0 ]-----> TD ---------\
- * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
- * ... TD ---------/
- * [1023]-----> TD --------/
- *
- * ^^ ^^ ^^ ^^ ^^
- * 7 TDs for 1 TD for Start of Start of End Chain
- * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain
- *
- *
- * Since this is a bootloader, the isochronous transfer descriptor have been removed.
- *
- * Interrupt Transfers.
- * --------------------
- * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
- * will be inserted after the appropriate (depending the interval setting) skeleton TD.
- * If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
- * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
- * the interrupt TD will be reactivated.
- *
- * Control Transfers
- * -----------------
- * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- * Bulk Transfers
- * --------------
- * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- *
- */
-
-#include <common.h>
-#include <ambapp.h>
-#include <asm/leon.h>
-#include <asm/leon3.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_USB_UHCI
-
-#include <usb.h>
-#include "usb_uhci.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */
-#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */
-
-/*
-#define out16r(address,data) (*(unsigned short *)(address) = \
- (unsigned short)( \
- (((unsigned short)(data)&0xff)<<8) | \
- (((unsigned short)(data)&0xff00)>>8) \
- ))
- */
-#define out16r(address,data) _out16r((unsigned int)(address), (unsigned short)(data))
-void _out16r(unsigned int address, unsigned short data)
-{
- unsigned short val = (unsigned short)((((unsigned short)(data) & 0xff)
- << 8) | (((unsigned short)(data)
- & 0xff00) >> 8));
-#ifdef UHCI_DEBUG_REGS
- printf("out16r(0x%lx,0x%04x = 0x%04x)\n", address, val, data);
-#endif
- *(unsigned short *)(address) = val;
-}
-
-#define out32r(address,data) _out32r((unsigned int)(address), (unsigned int)(data))
-void _out32r(unsigned int address, unsigned int data)
-{
- unsigned int val = (unsigned int)((((unsigned int)(data) & 0x000000ff)
- << 24) | (((unsigned int)(data) &
- 0x0000ff00) << 8) |
- (((unsigned int)(data) & 0x00ff0000)
- >> 8) | (((unsigned int)(data) &
- 0xff000000) >> 24));
-#ifdef UHCI_DEBUG_REGS
- printf("out32r(0x%lx,0x%lx = 0x%lx)\n", address, val, data);
-#endif
- *(unsigned int *)address = val;
-}
-
-#define in16r(address) _in16r((unsigned int)(address))
-unsigned short _in16r(unsigned int address)
-{
- unsigned short val = sparc_load_reg_cachemiss_word(address);
- val = ((val << 8) & 0xff00) | ((val >> 8) & 0xff);
-#ifdef UHCI_DEBUG_REGS
- printf("in16r(0x%lx): 0x%04x\n", address, val);
-#endif
- return val;
-}
-
-#define in32r(address) _in32r((unsigned int)(address))
-unsigned int _in32r(unsigned int address)
-{
- unsigned int val = sparc_load_reg_cachemiss(address);
- val =
- ((val << 24) & 0xff000000) | ((val << 8) & 0xff0000) | ((val >> 8) &
- 0xff00) |
- ((val >> 24) & 0xff);
-#ifdef UHCI_DEBUG_REGS
- printf("in32r(0x%lx): 0x%08x\n", address, val);
-#endif
- return val;
-}
-
-#define READ32(address) sparc_load_reg_cachemiss((unsigned int)(address))
-
-/*#define USB_UHCI_DEBUG*/
-#undef USB_UHCI_DEBUG
-
-void usb_show_td(int max);
-#ifdef USB_UHCI_DEBUG
-void grusb_show_regs(void);
-#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define USB_UHCI_PRINTF(fmt,args...)
-#endif
-
-static int grusb_irq = -1; /* irq vector, if -1 uhci is stopped / reseted */
-unsigned int usb_base_addr; /* base address */
-
-static uhci_td_t td_int[8] __attribute__ ((aligned(16))); /* Interrupt Transfer descriptors */
-static uhci_qh_t qh_cntrl __attribute__ ((aligned(16))); /* control Queue Head */
-static uhci_qh_t qh_bulk __attribute__ ((aligned(16))); /* bulk Queue Head */
-static uhci_qh_t qh_end __attribute__ ((aligned(16))); /* end Queue Head */
-static uhci_td_t td_last __attribute__ ((aligned(16))); /* last TD (linked with end chain) */
-
-/* temporary tds */
-static uhci_td_t tmp_td[USB_MAX_TEMP_TD] __attribute__ ((aligned(16))); /* temporary bulk/control td's */
-static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD] __attribute__ ((aligned(16))); /* temporary interrupt td's */
-
-static unsigned long framelist[1024] __attribute__ ((aligned(0x1000))); /* frame list */
-
-static struct virt_root_hub rh; /* struct for root hub */
-
-/**********************************************************************
- * some forward decleration
- */
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len,
- struct devrequest *setup);
-
-/* fill a td with the approproiate data. Link, status, info and buffer
- * are used by the USB controller itselfes, dev is used to identify the
- * "connected" device
- */
-void usb_fill_td(uhci_td_t * td, unsigned long link, unsigned long status,
- unsigned long info, unsigned long buffer, unsigned long dev)
-{
- td->link = swap_32(link);
- td->status = swap_32(status);
- if ((info & UHCI_PID) == 0)
- info |= USB_PID_OUT;
- td->info = swap_32(info);
- td->buffer = swap_32(buffer);
- td->dev_ptr = dev;
-}
-
-/* fill a qh with the approproiate data. Head and element are used by the USB controller
- * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
- * Please note, that after completion of the td chain, the entry element is removed /
- * marked invalid by the USB controller.
- */
-void usb_fill_qh(uhci_qh_t * qh, unsigned long head, unsigned long element)
-{
- qh->head = swap_32(head);
- qh->element = swap_32(element);
- qh->dev_ptr = 0L;
-}
-
-/* get the status of a td->status
- */
-unsigned long usb_uhci_td_stat(unsigned long status)
-{
- unsigned long result = 0;
- result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0;
- result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0;
- result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0;
- result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0;
- result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
- result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
- result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0;
- return result;
-}
-
-/* get the status and the transferred len of a td chain.
- * called from the completion handler
- */
-int usb_get_td_status(uhci_td_t * td, struct usb_device *dev)
-{
- unsigned long temp, info;
- unsigned long stat;
- uhci_td_t *mytd = td;
-
- if (dev->devnum == rh.devnum)
- return 0;
- dev->act_len = 0;
- stat = 0;
- do {
- temp = swap_32((unsigned long)READ32(&mytd->status));
- stat = usb_uhci_td_stat(temp);
- info = swap_32((unsigned long)READ32(&mytd->info));
- if (((info & 0xff) != USB_PID_SETUP) && (((info >> 21) & 0x7ff) != 0x7ff) && (temp & 0x7FF) != 0x7ff) { /* if not setup and not null data pack */
- dev->act_len += (temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
- }
- if (stat) { /* status no ok */
- dev->status = stat;
- return -1;
- }
- temp = swap_32((unsigned long)READ32(&mytd->link));
- mytd = (uhci_td_t *) (temp & 0xfffffff0);
- } while ((temp & 0x1) == 0); /* process all TDs */
- dev->status = stat;
- return 0; /* Ok */
-}
-
-/*-------------------------------------------------------------------
- * LOW LEVEL STUFF
- * assembles QHs und TDs for control, bulk and iso
- *-------------------------------------------------------------------*/
-int dummy(void)
-{
- USB_UHCI_PRINTF("DUMMY\n");
- return 0;
-}
-
-/* Submits a control message. That is a Setup, Data and Status transfer.
- * Routine does not wait for completion.
- */
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
-{
- unsigned long destination, status;
- int maxsze = usb_maxpacket(dev, pipe);
- unsigned long dataptr;
- int len;
- int pktsze;
- int i = 0;
-
- if (!maxsze) {
- USB_UHCI_PRINTF
- ("uhci_submit_control_urb: pipesize for pipe %lx is zero\n",
- pipe);
- return -1;
- }
- if (((pipe >> 8) & 0x7f) == rh.devnum) {
- /* this is the root hub -> redirect it */
- return uhci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
- }
- USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",
- transfer_len, maxsze);
- /* The "pipe" thing contains the destination in bits 8--18 */
- destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
- /* Build the TD for the control request, try forever, 8 bytes of data */
- usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | (7 << 21),
- (unsigned long)setup, (unsigned long)dev);
-#ifdef DEBUG_EXTRA
- {
- char *sp = (char *)setup;
- printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
- sp[0], sp[1], sp[2], sp[3], sp[4], sp[5], sp[6], sp[7]);
- }
-#endif
- dataptr = (unsigned long)buffer;
- len = transfer_len;
-
- /* If direction is "send", change the frame from SETUP (0x2D)
- to OUT (0xE1). Else change it from SETUP to IN (0x69). */
- destination =
- (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN) ==
- 0 ? USB_PID_OUT : USB_PID_IN);
- while (len > 0) {
- /* data stage */
- pktsze = len;
- i++;
- if (pktsze > maxsze)
- pktsze = maxsze;
- destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */
- usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21), dataptr, (unsigned long)dev); /* Status, pktsze bytes of data */
- tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]);
-
- dataptr += pktsze;
- len -= pktsze;
- }
-
- /* Build the final TD for control status */
- /* It's only IN if the pipe is out AND we aren't expecting data */
-
- destination &= ~UHCI_PID;
- if (((pipe & USB_DIR_IN) == 0) || (transfer_len == 0))
- destination |= USB_PID_IN;
- else
- destination |= USB_PID_OUT;
- destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */
- i++;
- status &= ~TD_CTRL_SPD;
- /* no limit on errors on final packet , 0 bytes of data */
- usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status | TD_CTRL_IOC,
- destination | (UHCI_NULL_DATA_SIZE << 21), 0,
- (unsigned long)dev);
- tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]); /* queue status td */
- /* usb_show_td(i+1); */
- USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n", i);
- /* first mark the control QH element terminated */
- qh_cntrl.element = 0xffffffffL;
- /* set qh active */
- qh_cntrl.dev_ptr = (unsigned long)dev;
- /* fill in tmp_td_chain */
- dummy();
- qh_cntrl.element = swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-/*-------------------------------------------------------------------
- * Prepare TDs for bulk transfers.
- */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
-{
- unsigned long destination, status, info;
- unsigned long dataptr;
- int maxsze = usb_maxpacket(dev, pipe);
- int len;
- int i = 0;
-
- if (transfer_len < 0) {
- printf("Negative transfer length in submit_bulk\n");
- return -1;
- }
- if (!maxsze)
- return -1;
- /* The "pipe" thing contains the destination in bits 8--18. */
- destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe);
- /* 3 errors */
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
- /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
- /* Build the TDs for the bulk request */
- len = transfer_len;
- dataptr = (unsigned long)buffer;
- do {
- int pktsze = len;
- if (pktsze > maxsze)
- pktsze = maxsze;
- /* pktsze bytes of data */
- info =
- destination | (((pktsze - 1) & UHCI_NULL_DATA_SIZE) << 21) |
- (usb_gettoggle
- (dev, usb_pipeendpoint(pipe),
- usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
-
- if ((len - pktsze) == 0)
- status |= TD_CTRL_IOC; /* last one generates INT */
-
- usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, info, dataptr, (unsigned long)dev); /* Status, pktsze bytes of data */
- if (i > 0)
- tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]);
- i++;
- dataptr += pktsze;
- len -= pktsze;
- usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
- } while (len > 0);
- /* first mark the bulk QH element terminated */
- qh_bulk.element = 0xffffffffL;
- /* set qh active */
- qh_bulk.dev_ptr = (unsigned long)dev;
- /* fill in tmp_td_chain */
- qh_bulk.element = swap_32((unsigned long)&tmp_td[0]);
- return 0;
-}
-
-/* search a free interrupt td
- */
-uhci_td_t *uhci_alloc_int_td(void)
-{
- int i;
- for (i = 0; i < USB_MAX_TEMP_INT_TD; i++) {
- if (tmp_int_td[i].dev_ptr == 0) /* no device assigned -> free TD */
- return &tmp_int_td[i];
- }
- return NULL;
-}
-
-/*-------------------------------------------------------------------
- * submits USB interrupt (ie. polling ;-)
- */
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
-{
- int nint, n;
- unsigned long status, destination;
- unsigned long info, tmp;
- uhci_td_t *mytd;
- if (interval < 0 || interval >= 256)
- return -1;
-
- if (interval == 0)
- nint = 0;
- else {
- for (nint = 0, n = 1; nint <= 8; nint++, n += n) { /* round interval down to 2^n */
- if (interval < n) {
- interval = n / 2;
- break;
- }
- }
- nint--;
- }
-
- USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint);
- mytd = uhci_alloc_int_td();
- if (mytd == NULL) {
- printf("No free INT TDs found\n");
- return -1;
- }
- status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
-/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
-*/
-
- destination =
- (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe) |
- (((transfer_len - 1) & 0x7ff) << 21);
-
- info =
- destination |
- (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) <<
- TD_TOKEN_TOGGLE);
- tmp = swap_32(td_int[nint].link);
- usb_fill_td(mytd, tmp, status, info, (unsigned long)buffer,
- (unsigned long)dev);
- /* Link it */
- tmp = swap_32((unsigned long)mytd);
- td_int[nint].link = tmp;
-
- usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
-
- return 0;
-}
-
-/**********************************************************************
- * Low Level functions
- */
-
-void reset_hc(void)
-{
-
- /* Global reset for 100ms */
- out16r(usb_base_addr + USBPORTSC1, 0x0204);
- out16r(usb_base_addr + USBPORTSC2, 0x0204);
- out16r(usb_base_addr + USBCMD, USBCMD_GRESET | USBCMD_RS);
- /* Turn off all interrupts */
- out16r(usb_base_addr + USBINTR, 0);
- mdelay(50);
- out16r(usb_base_addr + USBCMD, 0);
- mdelay(10);
-}
-
-void start_hc(void)
-{
- int timeout = 1000;
-
- while (in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
- if (!--timeout) {
- printf("USBCMD_HCRESET timed out!\n");
- break;
- }
- }
- /* Turn on all interrupts */
- out16r(usb_base_addr + USBINTR,
- USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
- /* Start@frame 0 */
- out16r(usb_base_addr + USBFRNUM, 0);
- /* set Framebuffer base address */
- out32r(usb_base_addr + USBFLBASEADD, (unsigned long)&framelist);
- /* Run and mark it configured with a 64-byte max packet */
- out16r(usb_base_addr + USBCMD, USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
-}
-
-/* Initialize the skeleton
- */
-void usb_init_skel(void)
-{
- unsigned long temp;
- int n;
-
- for (n = 0; n < USB_MAX_TEMP_INT_TD; n++)
- tmp_int_td[n].dev_ptr = 0L; /* no devices connected */
- /* last td */
- usb_fill_td(&td_last, UHCI_PTR_TERM, TD_CTRL_IOC, USB_PID_OUT, 0, 0L);
- /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
- /* End Queue Header */
- usb_fill_qh(&qh_end, UHCI_PTR_TERM, (unsigned long)&td_last);
- /* Bulk Queue Header */
- temp = (unsigned long)&qh_end;
- usb_fill_qh(&qh_bulk, temp | UHCI_PTR_QH, UHCI_PTR_TERM);
- /* Control Queue Header */
- temp = (unsigned long)&qh_bulk;
- usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH, UHCI_PTR_TERM);
- /* 1ms Interrupt td */
- temp = (unsigned long)&qh_cntrl;
- usb_fill_td(&td_int[0], temp | UHCI_PTR_QH, 0, USB_PID_OUT, 0, 0L);
- temp = (unsigned long)&td_int[0];
- for (n = 1; n < 8; n++)
- usb_fill_td(&td_int[n], temp, 0, USB_PID_OUT, 0, 0L);
- for (n = 0; n < 1024; n++) {
- /* link all framelist pointers to one of the interrupts */
- int m, o;
- if ((n & 127) == 127)
- framelist[n] = swap_32((unsigned long)&td_int[0]);
- else
- for (o = 1, m = 2; m <= 128; o++, m += m)
- if ((n & (m - 1)) == ((m - 1) / 2))
- framelist[n] =
- swap_32((unsigned long)&td_int[o]);
-
- }
-}
-
-/* check the common skeleton for completed transfers, and update the status
- * of the "connected" device. Called from the IRQ routine.
- */
-void usb_check_skel(void)
-{
- struct usb_device *dev;
- /* start with the control qh */
- if (qh_cntrl.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */
- dev = (struct usb_device *)qh_cntrl.dev_ptr;
- /* Flush cache now that hardware updated DATA and TDs/QHs */
- if (!gd->arch.snooping_avail)
- sparc_dcache_flush_all();
- usb_get_td_status(&tmp_td[0], dev); /* update status */
- if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_cntrl.dev_ptr = 0;
- }
- }
- /* now process the bulk */
- if (qh_bulk.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */
- dev = (struct usb_device *)qh_bulk.dev_ptr;
- /* Flush cache now that hardware updated DATA and TDs/QHs */
- if (!gd->arch.snooping_avail)
- sparc_dcache_flush_all();
- usb_get_td_status(&tmp_td[0], dev); /* update status */
- if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
- qh_bulk.dev_ptr = 0;
- }
- }
-}
-
-/* check the interrupt chain, ubdate the status of the appropriate device,
- * call the appropriate irqhandler and reactivate the TD if the irqhandler
- * returns with 1
- */
-void usb_check_int_chain(void)
-{
- int i, res;
- unsigned long link, status;
- struct usb_device *dev;
- uhci_td_t *td, *prevtd;
-
- for (i = 0; i < 8; i++) {
- prevtd = &td_int[i]; /* the first previous td is the skeleton td */
- link = swap_32(READ32(&td_int[i].link)) & 0xfffffff0; /* next in chain */
- td = (uhci_td_t *) link; /* assign it */
- /* all interrupt TDs are finally linked to the td_int[0].
- * so we process all until we find the td_int[0].
- * if int0 chain points to a QH, we're also done
- */
- while (((i > 0) && (link != (unsigned long)&td_int[0])) ||
- ((i == 0)
- && !(swap_32(READ32(&td->link)) & UHCI_PTR_QH))) {
- /* check if a device is assigned with this td */
- status = swap_32(READ32(&td->status));
- if ((td->dev_ptr != 0L) && !(status & TD_CTRL_ACTIVE)) {
- /* td is not active and a device is assigned -> call irqhandler */
- dev = (struct usb_device *)td->dev_ptr;
- dev->irq_act_len = ((status & 0x7FF) == 0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
- dev->irq_status = usb_uhci_td_stat(status); /* get status */
- res = dev->irq_handle(dev); /* call irqhandler */
- if (res == 1) {
- /* reactivate */
- status |= TD_CTRL_ACTIVE;
- td->status = swap_32(status);
- prevtd = td; /* previous td = this td */
- } else {
- prevtd->link = READ32(&td->link); /* link previous td directly to the nex td -> unlinked */
- /* remove device pointer */
- td->dev_ptr = 0L;
- }
- } /* if we call the irq handler */
- link = swap_32(READ32(&td->link)) & 0xfffffff0; /* next in chain */
- td = (uhci_td_t *) link; /* assign it */
- } /* process all td in this int chain */
- } /* next interrupt chain */
-}
-
-/* usb interrupt service routine.
- */
-void handle_usb_interrupt(void)
-{
- unsigned short status;
- static int error = 0;
-
- /*
- * Read the interrupt status, and write it back to clear the
- * interrupt cause
- */
-
- status = in16r(usb_base_addr + USBSTS);
-
- if (!status) /* shared interrupt, not mine */
- return;
- if (status != 1) {
- /* remove host controller halted state */
- if ((status & (USBSTS_HCPE | USBSTS_HCH)) ==
- (USBSTS_HCPE | USBSTS_HCH)) {
- /* Stop due to bug in driver, or hardware */
- out16r(usb_base_addr + USBSTS, status);
- out16r(usb_base_addr + USBCMD,
- USBCMD_HCRESET | USBCMD_GRESET);
- printf
- ("GRUSB: HW detected error(s) in USB Descriptors (STS: 0x%x)\n",
- status);
- usb_show_td(8);
- return;
- } else if ((status & 0x20)
- && ((in16r(usb_base_addr + USBCMD) & USBCMD_RS) ==
- 0)) {
- if (error < 10) {
- out16r(usb_base_addr + USBCMD,
- USBCMD_RS | in16r(usb_base_addr +
- USBCMD));
- error++;
- }
- } else
- error = 0;
- }
- usb_check_int_chain(); /* call interrupt handlers for int tds */
- usb_check_skel(); /* call completion handler for common transfer routines */
- out16r(usb_base_addr + USBSTS, status);
-}
-
-/* init uhci
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- ambapp_ahbdev ahbdev;
-
- /* Find GRUSB core using AMBA Plug&Play information */
- if (ambapp_ahbslv_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_UHCI,
- CONFIG_SYS_GRLIB_GRUSB_INDEX, &ahbdev) != 1) {
- printf("USB UHCI: Failed to find GRUSB controller\n");
- return -1;
- }
- usb_base_addr = ahbdev.address[0];
- grusb_irq = ahbdev.irq;
- /*
- usb_base_addr = 0xfffa0000;
- grusb_irq = 10;
- */
-#ifdef USB_UHCI_DEBUG
- grusb_show_regs();
-#endif
- memset(td_int, 0, sizeof(td_int));
- memset(tmp_td, 0, sizeof(tmp_td));
- memset(tmp_int_td, 0, sizeof(tmp_int_td));
- memset(&qh_cntrl, 0, sizeof(qh_cntrl));
- memset(&qh_end, 0, sizeof(qh_end));
- memset(&td_last, 0, sizeof(td_last));
-
- irq_free_handler(grusb_irq);
- USB_UHCI_PRINTF("GRUSB:@0x%lx irq %d\n", usb_base_addr, grusb_irq);
- rh.devnum = 0;
- usb_init_skel();
- reset_hc();
- start_hc();
- irq_install_handler(grusb_irq,
- (interrupt_handler_t *) handle_usb_interrupt, NULL);
- return 0;
-}
-
-/* stop uhci
- */
-int usb_lowlevel_stop(int index)
-{
- if (grusb_irq == -1)
- return 1;
- irq_free_handler(grusb_irq);
- reset_hc();
- grusb_irq = -1;
- return 0;
-}
-
-/*******************************************************************************************
- * Virtual Root Hub
- * Since the uhci does not have a real HUB, we simulate one ;-)
- */
-#undef USB_RH_DEBUG
-
-#ifdef USB_RH_DEBUG
-#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args)
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex);
-static void usb_display_Req(unsigned short req);
-#else
-#define USB_RH_PRINTF(fmt,args...)
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex)
-{
-}
-static void usb_display_Req(unsigned short req)
-{
-}
-#endif
-
-#define WANT_USB_ROOT_HUB_HUB_DES
-#include <usbroothubdes.h>
-#undef WANT_USB_ROOT_HUB_HUB_DES
-
-/*
- * Root Hub Control Pipe (interrupt Pipes are not supported)
- */
-
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *cmd)
-{
- void *data = buffer;
- int leni = transfer_len;
- int len = 0;
- int status = 0;
- int stat = 0;
- int i;
-
- unsigned short cstatus;
-
- unsigned short bmRType_bReq;
- unsigned short wValue;
- unsigned short wIndex;
- unsigned short wLength;
-
- if (usb_pipeint(pipe)) {
- printf("Root-Hub submit IRQ: NOT implemented\n");
- return 0;
- }
- bmRType_bReq = cmd->requesttype | cmd->request << 8;
- wValue = swap_16(cmd->value);
- wIndex = swap_16(cmd->index);
- wLength = swap_16(cmd->length);
- usb_display_Req(bmRType_bReq);
- for (i = 0; i < 8; i++)
- rh.c_p_r[i] = 0;
- USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
- dev->devnum, 8, cmd->requesttype, cmd->request, wValue,
- wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(unsigned short *)data = swap_16(1);
- len = 2;
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- *(unsigned short *)data = swap_16(0);
- len = 2;
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- *(unsigned short *)data = swap_16(0);
- len = 2;
- break;
- case RH_GET_STATUS | RH_CLASS:
- *(unsigned long *)data = swap_32(0);
- len = 4;
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-
- status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
- cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
- ((status & USBPORTSC_PEC) >> (3 - 1)) |
- (rh.c_p_r[wIndex - 1] << (0 + 4));
- status = (status & USBPORTSC_CCS) | ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | (1 << 8) | /* power on ** */
- ((status & USBPORTSC_LSDA) << (-8 + 9));
-
- *(unsigned short *)data = swap_16(status);
- *(unsigned short *)(data + 2) = swap_16(cstatus);
- len = 4;
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL):
- len = 0;
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case (RH_C_HUB_OVER_CURRENT):
- len = 0; /* hub power over current ** */
- break;
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue, wIndex);
- switch (wValue) {
- case (RH_PORT_ENABLE):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) & ~USBPORTSC_PE;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_PORT_SUSPEND):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) & ~USBPORTSC_SUSP;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_PORT_POWER):
- len = 0; /* port power ** */
- break;
- case (RH_C_PORT_CONNECTION):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) | USBPORTSC_CSC;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_C_PORT_ENABLE):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) | USBPORTSC_PEC;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_C_PORT_SUSPEND):
-/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
- len = 0;
- break;
- case (RH_C_PORT_OVER_CURRENT):
- len = 0;
- break;
- case (RH_C_PORT_RESET):
- rh.c_p_r[wIndex - 1] = 0;
- len = 0;
- break;
- }
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- usb_display_wValue(wValue, wIndex);
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) | USBPORTSC_SUSP;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_PORT_RESET):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) | USBPORTSC_PR;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- mdelay(10);
- status = (status & 0xfff5) & ~USBPORTSC_PR;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- udelay(10);
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- mdelay(10);
- status = (status & 0xfff5) | 0xa;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- case (RH_PORT_POWER):
- len = 0; /* port power ** */
- break;
- case (RH_PORT_ENABLE):
- status =
- in16r(usb_base_addr + USBPORTSC1 +
- 2 * (wIndex - 1));
- status = (status & 0xfff5) | USBPORTSC_PE;
- out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1),
- status);
- len = 0;
- break;
- }
- break;
-
- case RH_SET_ADDRESS:
- rh.devnum = wValue;
- len = 0;
- break;
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- i = sizeof(root_hub_config_des);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy(data, root_hub_dev_des, len);
- break;
- case (0x02): /* configuration descriptor */
- i = sizeof(root_hub_config_des);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy(data, root_hub_config_des, len);
- break;
- case (0x03): /*string descriptors */
- if (wValue == 0x0300) {
- i = sizeof(root_hub_str_index0);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy(data, root_hub_str_index0, len);
- break;
- }
- if (wValue == 0x0301) {
- i = sizeof(root_hub_str_index1);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy(data, root_hub_str_index1, len);
- break;
- }
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- root_hub_hub_des[2] = 2;
- i = sizeof(root_hub_hub_des);
- status = i > wLength ? wLength : i;
- len = leni > status ? status : leni;
- memcpy(data, root_hub_hub_des, len);
- break;
- case RH_GET_CONFIGURATION:
- *(unsigned char *)data = 0x01;
- len = 1;
- break;
- case RH_SET_CONFIGURATION:
- len = 0;
- break;
- default:
- stat = USB_ST_STALLED;
- }
- USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n", stat,
- in16r(usb_base_addr + USBPORTSC1),
- in16r(usb_base_addr + USBPORTSC2));
- dev->act_len = len;
- dev->status = stat;
- return stat;
-
-}
-
-/********************************************************************************
- * Some Debug Routines
- */
-
-#ifdef USB_RH_DEBUG
-
-static void usb_display_Req(unsigned short req)
-{
- USB_RH_PRINTF("- Root-Hub Request: ");
- switch (req) {
- case RH_GET_STATUS:
- USB_RH_PRINTF("Get Status ");
- break;
- case RH_GET_STATUS | RH_INTERFACE:
- USB_RH_PRINTF("Get Status Interface ");
- break;
- case RH_GET_STATUS | RH_ENDPOINT:
- USB_RH_PRINTF("Get Status Endpoint ");
- break;
- case RH_GET_STATUS | RH_CLASS:
- USB_RH_PRINTF("Get Status Class");
- break; /* hub power ** */
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Get Status Class Others");
- break;
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- USB_RH_PRINTF("Clear Feature Endpoint ");
- break;
- case RH_CLEAR_FEATURE | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Class ");
- break;
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Clear Feature Other Class ");
- break;
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- USB_RH_PRINTF("Set Feature Other Class ");
- break;
- case RH_SET_ADDRESS:
- USB_RH_PRINTF("Set Address ");
- break;
- case RH_GET_DESCRIPTOR:
- USB_RH_PRINTF("Get Descriptor ");
- break;
- case RH_GET_DESCRIPTOR | RH_CLASS:
- USB_RH_PRINTF("Get Descriptor Class ");
- break;
- case RH_GET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- case RH_SET_CONFIGURATION:
- USB_RH_PRINTF("Get Configuration ");
- break;
- default:
- USB_RH_PRINTF("****UNKNOWN**** 0x%04X ", req);
- }
- USB_RH_PRINTF("\n");
-
-}
-
-static void usb_display_wValue(unsigned short wValue, unsigned short wIndex)
-{
- switch (wValue) {
- case (RH_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: Enable Port %d\n", wIndex);
- break;
- case (RH_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: Suspend Port %d\n", wIndex);
- break;
- case (RH_PORT_POWER):
- USB_RH_PRINTF("Root-Hub: Port Power %d\n", wIndex);
- break;
- case (RH_C_PORT_CONNECTION):
- USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n", wIndex);
- break;
- case (RH_C_PORT_ENABLE):
- USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n", wIndex);
- break;
- case (RH_C_PORT_SUSPEND):
- USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n", wIndex);
- break;
- case (RH_C_PORT_OVER_CURRENT):
- USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",
- wIndex);
- break;
- case (RH_C_PORT_RESET):
- USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n", wIndex);
- break;
- default:
- USB_RH_PRINTF("Root-Hub: unknown %x %x\n", wValue, wIndex);
- break;
- }
-}
-
-#endif
-
-/*#ifdef USB_UHCI_DEBUG*/
-
-static int usb_display_td(uhci_td_t * td)
-{
- unsigned long tmp;
- int valid;
-
- printf("TD at %p:\n", td);
-
- tmp = swap_32(READ32(&td->link));
- printf("Link points to 0x%08lX, %s first, %s, %s\n", tmp & 0xfffffff0,
- ((tmp & 0x4) == 0x4) ? "Depth" : "Breath",
- ((tmp & 0x2) == 0x2) ? "QH" : "TD",
- ((tmp & 0x1) == 0x1) ? "invalid" : "valid");
- valid = ((tmp & 0x1) == 0x0);
- tmp = swap_32(READ32(&td->status));
- printf
- (" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n",
- (((tmp >> 29) & 0x1) == 0x1) ? "SPD Enable" : "SPD Disable",
- ((tmp >> 28) & 0x3),
- (((tmp >> 26) & 0x1) == 0x1) ? "Low Speed" : "Full Speed",
- (((tmp >> 25) & 0x1) == 0x1) ? "ISO " : "",
- (((tmp >> 24) & 0x1) == 0x1) ? "IOC " : "",
- (((tmp >> 23) & 0x1) == 0x1) ? "Active " : "Inactive ",
- (((tmp >> 22) & 0x1) == 0x1) ? "Stalled" : "",
- (((tmp >> 21) & 0x1) == 0x1) ? "Data Buffer Error" : "",
- (((tmp >> 20) & 0x1) == 0x1) ? "Babble" : "",
- (((tmp >> 19) & 0x1) == 0x1) ? "NAK" : "",
- (((tmp >> 18) & 0x1) == 0x1) ? "Bitstuff Error" : "",
- (tmp & 0x7ff));
- tmp = swap_32(READ32(&td->info));
- printf(" MaxLen 0x%lX\n", ((tmp >> 21) & 0x7FF));
- printf(" %sEndpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",
- ((tmp >> 19) & 0x1) == 0x1 ? "TOGGLE " : "", ((tmp >> 15) & 0xF),
- ((tmp >> 8) & 0x7F), tmp & 0xFF);
- tmp = swap_32(READ32(&td->buffer));
- printf(" Buffer 0x%08lX\n", tmp);
- printf(" DEV %08lX\n", td->dev_ptr);
- return valid;
-}
-
-void usb_show_td(int max)
-{
- int i;
- if (max > 0) {
- for (i = 0; i < max; i++) {
- usb_display_td(&tmp_td[i]);
- }
- } else {
- i = 0;
- do {
- printf("tmp_td[%d]\n", i);
- } while (usb_display_td(&tmp_td[i++]));
- }
-}
-
-void grusb_show_regs(void)
-{
- unsigned int tmp;
-
- tmp = in16r(usb_base_addr + USBCMD);
- printf(" USBCMD: 0x%04x\n", tmp);
- tmp = in16r(usb_base_addr + USBSTS);
- printf(" USBSTS: 0x%04x\n", tmp);
- tmp = in16r(usb_base_addr + USBINTR);
- printf(" USBINTR: 0x%04x\n", tmp);
- tmp = in16r(usb_base_addr + USBFRNUM);
- printf(" FRNUM: 0x%04x\n", tmp);
- tmp = in32r(usb_base_addr + USBFLBASEADD);
- printf(" FLBASEADD: 0x%08x\n", tmp);
- tmp = in16r(usb_base_addr + USBSOF);
- printf(" SOFMOD: 0x%04x\n", tmp);
- tmp = in16r(usb_base_addr + USBPORTSC1);
- printf(" PORTSC1: 0x%04x\n", tmp);
-}
-
-/*#endif*/
-#endif /* CONFIG_USB_UHCI */
-
-/* EOF */
diff --git a/arch/sparc/cpu/leon3/usb_uhci.h b/arch/sparc/cpu/leon3/usb_uhci.h
deleted file mode 100644
index 034814a48287..000000000000
--- a/arch/sparc/cpu/leon3/usb_uhci.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: Part of this code has been derived from linux
- */
-#ifndef _USB_UHCI_H_
-#define _USB_UHCI_H_
-
-/* Command register */
-#define USBCMD 0
-#define USBCMD_RS 0x0001 /* Run/Stop */
-#define USBCMD_HCRESET 0x0002 /* Host reset */
-#define USBCMD_GRESET 0x0004 /* Global reset */
-#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
-#define USBCMD_FGR 0x0010 /* Force Global Resume */
-#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
-#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
-#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
-
-/* Status register */
-#define USBSTS 2
-#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
-#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
-#define USBSTS_RD 0x0004 /* Resume Detect */
-#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
-#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
-#define USBSTS_HCH 0x0020 /* HC Halted */
-
-/* Interrupt enable register */
-#define USBINTR 4
-#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
-#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
-#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
-#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
-
-#define USBFRNUM 6
-#define USBFLBASEADD 8
-#define USBSOF 12
-
-/* USB port status and control registers */
-#define USBPORTSC1 16
-#define USBPORTSC2 18
-#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
-#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
-#define USBPORTSC_PE 0x0004 /* Port Enable */
-#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
-#define USBPORTSC_LS 0x0030 /* Line Status */
-#define USBPORTSC_RD 0x0040 /* Resume Detect */
-#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
-#define USBPORTSC_PR 0x0200 /* Port Reset */
-#define USBPORTSC_SUSP 0x1000 /* Suspend */
-
-/* Legacy support register */
-#define USBLEGSUP 0xc0
-#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
-
-#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
-#define UHCI_PID 0xff /* PID MASK */
-
-#define UHCI_PTR_BITS 0x000F
-#define UHCI_PTR_TERM 0x0001
-#define UHCI_PTR_QH 0x0002
-#define UHCI_PTR_DEPTH 0x0004
-
-/* for TD <status>: */
-#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
-#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
-#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
-#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
-#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
-#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
-#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
-#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
-#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
-#define TD_CTRL_NAK (1 << 19) /* NAK Received */
-#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
-#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
-#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
-
-#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
- TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
-
-#define TD_TOKEN_TOGGLE 19
-
-/* ------------------------------------------------------------------------------------
- Virtual Root HUB
- ------------------------------------------------------------------------------------ */
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-/* Our Vendor Specific feature */
-#define RH_REMOVE_EP 0x00
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-/* Transfer descriptor structure */
-typedef struct {
- unsigned long link; /* next td/qh (LE) */
- unsigned long status; /* status of the td */
- unsigned long info; /* Max Lenght / Endpoint / device address and PID */
- unsigned long buffer; /* pointer to data buffer (LE) */
- unsigned long dev_ptr; /* pointer to the assigned device (BE) */
- unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
-} uhci_td_t, *puhci_td_t;
-
-/* Queue Header structure */
-typedef struct {
- unsigned long head; /* Next QH (LE) */
- unsigned long element; /* Queue element pointer (LE) */
- unsigned long res[5]; /* reserved */
- unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
-} uhci_qh_t, *puhci_qh_t;
-
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- int numports; /* number of ports */
- int c_p_r[8]; /* C_PORT_RESET */
-};
-
-#endif /* _USB_UHCI_H_ */
diff --git a/arch/sparc/cpu/u-boot.lds b/arch/sparc/cpu/u-boot.lds
deleted file mode 100644
index 1ade3b344b67..000000000000
--- a/arch/sparc/cpu/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- */start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/arch/sparc/include/asm/arch-leon2/asi.h b/arch/sparc/include/asm/arch-leon2/asi.h
deleted file mode 100644
index 045bd77014be..000000000000
--- a/arch/sparc/include/asm/arch-leon2/asi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* asi.h: Address Space Identifier values for the LEON2 sparc.
- *
- * Copyright (C) 2008 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LEON2_ASI_H
-#define _LEON2_ASI_H
-
-#define ASI_CACHEMISS 0x01 /* Force D-Cache miss on load (lda) */
-#define ASI_M_FLUSH_PROBE 0x03 /* MMU Flush/Probe */
-#define ASI_IFLUSH 0x05 /* Flush I-Cache */
-#define ASI_DFLUSH 0x06 /* Flush D-Cache */
-#define ASI_BYPASS 0x1c /* Bypass MMU (Physical address) */
-#define ASI_MMUFLUSH 0x18 /* FLUSH TLB */
-#define ASI_M_MMUREGS 0x19 /* READ/Write MMU Registers */
-
-#endif /* _LEON2_ASI_H */
diff --git a/arch/sparc/include/asm/arch-leon3/asi.h b/arch/sparc/include/asm/arch-leon3/asi.h
deleted file mode 100644
index 61ffcc4f746e..000000000000
--- a/arch/sparc/include/asm/arch-leon3/asi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* asi.h: Address Space Identifier values for the LEON3 sparc.
- *
- * Copyright (C) 2008 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _LEON3_ASI_H
-#define _LEON3_ASI_H
-
-#define ASI_CACHEMISS 0x01 /* Force D-Cache miss on load (lda) */
-#define ASI_M_FLUSH_PROBE 0x03 /* MMU Flush/Probe */
-#define ASI_IFLUSH 0x10 /* Flush I-Cache */
-#define ASI_DFLUSH 0x11 /* Flush D-Cache */
-#define ASI_BYPASS 0x1c /* Bypass MMU (Physical address) */
-#define ASI_MMUFLUSH 0x18 /* FLUSH TLB */
-#define ASI_M_MMUREGS 0x19 /* READ/Write MMU Registers */
-
-#endif /* _LEON3_ASI_H */
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
deleted file mode 100644
index 16942f42db90..000000000000
--- a/arch/sparc/include/asm/asi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Address Space Identifier (ASI) values for sparc processors.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_ASI_H
-#define _SPARC_ASI_H
-
-/* ASI numbers are processor implementation specific */
-#include <asm/arch/asi.h>
-
-#endif /* _SPARC_ASI_H */
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
deleted file mode 100644
index 653f2e484858..000000000000
--- a/arch/sparc/include/asm/asmmacro.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Assembler macros for SPARC
- *
- * (C) Copyright 2007, taken from linux asm-sparc/asmmacro.h
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_ASMMACRO_H__
-#define __SPARC_ASMMACRO_H__
-
-#include <config.h>
-
-/* All trap entry points _must_ begin with this macro or else you
- * lose. It makes sure the kernel has a proper window so that
- * c-code can be called.
- */
-#define SAVE_ALL_HEAD \
- sethi %hi(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l4; \
- jmpl %l4 + %lo(trap_setup+(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE)), %l6;
-#define SAVE_ALL \
- SAVE_ALL_HEAD \
- nop;
-
-/* All traps low-level code here must end with this macro. */
-#define RESTORE_ALL b ret_trap_entry; clr %l6;
-
-#endif
diff --git a/arch/sparc/include/asm/atomic.h b/arch/sparc/include/asm/atomic.h
deleted file mode 100644
index 35236d01f8d0..000000000000
--- a/arch/sparc/include/asm/atomic.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPARC atomic operations
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_SPARC_ATOMIC_H_
-#define _ASM_SPARC_ATOMIC_H_
-
-#endif /* _ASM_SPARC_ATOMIC_H_ */
diff --git a/arch/sparc/include/asm/bitops.h b/arch/sparc/include/asm/bitops.h
deleted file mode 100644
index c66f730c8882..000000000000
--- a/arch/sparc/include/asm/bitops.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Bit string operations on the SPARC
- *
- * (C) Copyright 2007, taken from asm-ppc/bitops.h
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_BITOPS_H
-#define _SPARC_BITOPS_H
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#endif /* _SPARC_BITOPS_H */
diff --git a/arch/sparc/include/asm/byteorder.h b/arch/sparc/include/asm/byteorder.h
deleted file mode 100644
index bdc5e63f2188..000000000000
--- a/arch/sparc/include/asm/byteorder.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_BYTEORDER_H
-#define _SPARC_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-#define __BYTEORDER_HAS_U64__
-#define __SWAB_64_THRU_32__
-#endif
-#include <linux/byteorder/big_endian.h>
-#endif /* _SPARC_BYTEORDER_H */
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
deleted file mode 100644
index d9671d1c7497..000000000000
--- a/arch/sparc/include/asm/cache.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2008,
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_CACHE_H__
-#define __SPARC_CACHE_H__
-
-#include <asm/processor.h>
-
-/*
- * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
- * use 32-bytes, the cacheline size for Sparc.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 32
-#endif
-
-#endif
diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h
deleted file mode 100644
index 455fbc1b7329..000000000000
--- a/arch/sparc/include/asm/config.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2015,
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#define CONFIG_NEEDS_MANUAL_RELOC
-
-#define CONFIG_LMB
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
-#define CONFIG_SYS_TIMER_RATE 1000000 /* 1MHz */
-#define CONFIG_SYS_TIMER_COUNTER gd->arch.timer
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
-#endif
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
deleted file mode 100644
index af38d17b0dd3..000000000000
--- a/arch/sparc/include/asm/global_data.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2002-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham, Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include "asm/types.h"
-
-/* Architecture-specific global data */
-struct arch_global_data {
- void *timer;
- void *uart;
- unsigned int uart_freq;
-#ifdef CONFIG_LEON3
- unsigned int snooping_available;
-#endif
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/sparc/include/asm/io.h b/arch/sparc/include/asm/io.h
deleted file mode 100644
index a317d132be28..000000000000
--- a/arch/sparc/include/asm/io.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPARC I/O definitions
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_IO_H
-#define _SPARC_IO_H
-
-/* Nothing to sync, total store ordering (TSO)... */
-#define sync()
-
-/*
- * Generic virtual read/write.
- */
-
-#ifndef CONFIG_SYS_HAS_NO_CACHE
-
-/* Forces a cache miss on read/load.
- * On some architectures we need to bypass the cache when reading
- * I/O registers so that we are not reading the same status word
- * over and over again resulting in a hang (until an IRQ if lucky)
- */
-
-#define __arch_getb(a) SPARC_NOCACHE_READ_BYTE((unsigned int)(a))
-#define __arch_getw(a) SPARC_NOCACHE_READ_HWORD((unsigned int)(a))
-#define __arch_getl(a) SPARC_NOCACHE_READ((unsigned int)(a))
-#define __arch_getq(a) SPARC_NOCACHE_READ_DWORD((unsigned int)(a))
-
-#else
-
-#define __arch_getb(a) (*(volatile unsigned char *)(a))
-#define __arch_getw(a) (*(volatile unsigned short *)(a))
-#define __arch_getl(a) (*(volatile unsigned int *)(a))
-#define __arch_getq(a) (*(volatile unsigned long long *)(a))
-
-#endif /* CONFIG_SYS_HAS_NO_CACHE */
-
-#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
-
-#define __raw_writeb(v, a) __arch_putb(v, a)
-#define __raw_writew(v, a) __arch_putw(v, a)
-#define __raw_writel(v, a) __arch_putl(v, a)
-#define __raw_writeq(v, a) __arch_putq(v, a)
-
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
-#define __raw_readq(a) __arch_getq(a)
-
-#define writeb __raw_writeb
-#define writew __raw_writew
-#define writel __raw_writel
-#define writeq __raw_writeq
-
-#define readb __raw_readb
-#define readw __raw_readw
-#define readl __raw_readl
-#define readq __raw_readq
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-
-#define MAP_NOCACHE (0)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
-
-static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
- unsigned long flags)
-{
- return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
- return (phys_addr_t)(vaddr);
-}
-
-#endif
diff --git a/arch/sparc/include/asm/irq.h b/arch/sparc/include/asm/irq.h
deleted file mode 100644
index 5d0f7564e9b8..000000000000
--- a/arch/sparc/include/asm/irq.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* IRQ functions
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_IRQ_H__
-#define __SPARC_IRQ_H__
-
-#include <asm/psr.h>
-
-/* Set SPARC Processor Interrupt Level */
-static inline void set_pil(unsigned int level)
-{
- unsigned int psr = get_psr();
-
- put_psr((psr & ~PSR_PIL) | ((level & 0xf) << PSR_PIL_OFS));
-}
-
-/* Get SPARC Processor Interrupt Level */
-static inline unsigned int get_pil(void)
-{
- unsigned int psr = get_psr();
- return (psr & PSR_PIL) >> PSR_PIL_OFS;
-}
-
-/* Disables interrupts and return current PIL value */
-extern int intLock(void);
-
-/* Sets the PIL to oldLevel */
-extern void intUnlock(int oldLevel);
-
-/* Return non-zero if interrupts are currently enabled */
-extern int interrupt_is_enabled(void);
-
-#endif
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
deleted file mode 100644
index cc7c7f349d6e..000000000000
--- a/arch/sparc/include/asm/leon.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* LEON Header File select
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_LEON_H__
-#define __ASM_LEON_H__
-
-#if defined(CONFIG_LEON3)
-
-#include <asm/leon3.h>
-
-#elif defined(CONFIG_LEON2)
-
-#include <asm/leon2.h>
-
-#else
-
-#error Unknown LEON processor
-
-#endif
-
-/* Common stuff */
-
-#endif
diff --git a/arch/sparc/include/asm/leon2.h b/arch/sparc/include/asm/leon2.h
deleted file mode 100644
index ffac0de1d2e6..000000000000
--- a/arch/sparc/include/asm/leon2.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* LEON2 header file. LEON2 is a SOC processor.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LEON2_H__
-#define __LEON2_H__
-
-#ifdef CONFIG_LEON2
-
-/* LEON 2 I/O register definitions */
-#define LEON2_PREGS 0x80000000
-#define LEON2_MCFG1 0x00
-#define LEON2_MCFG2 0x04
-#define LEON2_ECTRL 0x08
-#define LEON2_FADDR 0x0C
-#define LEON2_MSTAT 0x10
-#define LEON2_CCTRL 0x14
-#define LEON2_PWDOWN 0x18
-#define LEON2_WPROT1 0x1C
-#define LEON2_WPROT2 0x20
-#define LEON2_LCONF 0x24
-#define LEON2_TCNT0 0x40
-#define LEON2_TRLD0 0x44
-#define LEON2_TCTRL0 0x48
-#define LEON2_TCNT1 0x50
-#define LEON2_TRLD1 0x54
-#define LEON2_TCTRL1 0x58
-#define LEON2_SCNT 0x60
-#define LEON2_SRLD 0x64
-#define LEON2_UART0 0x70
-#define LEON2_UDATA0 0x70
-#define LEON2_USTAT0 0x74
-#define LEON2_UCTRL0 0x78
-#define LEON2_USCAL0 0x7C
-#define LEON2_UART1 0x80
-#define LEON2_UDATA1 0x80
-#define LEON2_USTAT1 0x84
-#define LEON2_UCTRL1 0x88
-#define LEON2_USCAL1 0x8C
-#define LEON2_IMASK 0x90
-#define LEON2_IPEND 0x94
-#define LEON2_IFORCE 0x98
-#define LEON2_ICLEAR 0x9C
-#define LEON2_IOREG 0xA0
-#define LEON2_IODIR 0xA4
-#define LEON2_IOICONF 0xA8
-#define LEON2_IPEND2 0xB0
-#define LEON2_IMASK2 0xB4
-#define LEON2_ISTAT2 0xB8
-#define LEON2_ICLEAR2 0xBC
-
-#ifndef __ASSEMBLER__
-/*
- * Structure for LEON memory mapped registers.
- *
- * Source: Section 6.1 - On-chip registers
- *
- * NOTE: There is only one of these structures per CPU, its base address
- * is 0x80000000, and the variable LEON_REG is placed there by the
- * linkcmds file.
- */
-typedef struct {
- volatile unsigned int Memory_Config_1;
- volatile unsigned int Memory_Config_2;
- volatile unsigned int Edac_Control;
- volatile unsigned int Failed_Address;
- volatile unsigned int Memory_Status;
- volatile unsigned int Cache_Control;
- volatile unsigned int Power_Down;
- volatile unsigned int Write_Protection_1;
- volatile unsigned int Write_Protection_2;
- volatile unsigned int Leon_Configuration;
- volatile unsigned int dummy2;
- volatile unsigned int dummy3;
- volatile unsigned int dummy4;
- volatile unsigned int dummy5;
- volatile unsigned int dummy6;
- volatile unsigned int dummy7;
- volatile unsigned int Timer_Counter_1;
- volatile unsigned int Timer_Reload_1;
- volatile unsigned int Timer_Control_1;
- volatile unsigned int Watchdog;
- volatile unsigned int Timer_Counter_2;
- volatile unsigned int Timer_Reload_2;
- volatile unsigned int Timer_Control_2;
- volatile unsigned int dummy8;
- volatile unsigned int Scaler_Counter;
- volatile unsigned int Scaler_Reload;
- volatile unsigned int dummy9;
- volatile unsigned int dummy10;
- volatile unsigned int UART_Channel_1;
- volatile unsigned int UART_Status_1;
- volatile unsigned int UART_Control_1;
- volatile unsigned int UART_Scaler_1;
- volatile unsigned int UART_Channel_2;
- volatile unsigned int UART_Status_2;
- volatile unsigned int UART_Control_2;
- volatile unsigned int UART_Scaler_2;
- volatile unsigned int Interrupt_Mask;
- volatile unsigned int Interrupt_Pending;
- volatile unsigned int Interrupt_Force;
- volatile unsigned int Interrupt_Clear;
- volatile unsigned int PIO_Data;
- volatile unsigned int PIO_Direction;
- volatile unsigned int PIO_Interrupt;
-} LEON2_regs;
-
-typedef struct {
- volatile unsigned int UART_Channel;
- volatile unsigned int UART_Status;
- volatile unsigned int UART_Control;
- volatile unsigned int UART_Scaler;
-} LEON2_Uart_regs;
-
-#endif
-
-/*
- * The following constants are intended to be used ONLY in assembly
- * language files.
- *
- * NOTE: The intended style of usage is to load the address of LEON REGS
- * into a register and then use these as displacements from
- * that register.
- */
-#define LEON_REG_MEMCFG1_OFFSET 0x00
-#define LEON_REG_MEMCFG2_OFFSET 0x04
-#define LEON_REG_EDACCTRL_OFFSET 0x08
-#define LEON_REG_FAILADDR_OFFSET 0x0C
-#define LEON_REG_MEMSTATUS_OFFSET 0x10
-#define LEON_REG_CACHECTRL_OFFSET 0x14
-#define LEON_REG_POWERDOWN_OFFSET 0x18
-#define LEON_REG_WRITEPROT1_OFFSET 0x1C
-#define LEON_REG_WRITEPROT2_OFFSET 0x20
-#define LEON_REG_LEONCONF_OFFSET 0x24
-#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28
-#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C
-#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30
-#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34
-#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38
-#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C
-#define LEON_REG_TIMERCNT1_OFFSET 0x40
-#define LEON_REG_TIMERLOAD1_OFFSET 0x44
-#define LEON_REG_TIMERCTRL1_OFFSET 0x48
-#define LEON_REG_WDOG_OFFSET 0x4C
-#define LEON_REG_TIMERCNT2_OFFSET 0x50
-#define LEON_REG_TIMERLOAD2_OFFSET 0x54
-#define LEON_REG_TIMERCTRL2_OFFSET 0x58
-#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C
-#define LEON_REG_SCALERCNT_OFFSET 0x60
-#define LEON_REG_SCALER_LOAD_OFFSET 0x64
-#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68
-#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C
-#define LEON_REG_UARTDATA1_OFFSET 0x70
-#define LEON_REG_UARTSTATUS1_OFFSET 0x74
-#define LEON_REG_UARTCTRL1_OFFSET 0x78
-#define LEON_REG_UARTSCALER1_OFFSET 0x7C
-#define LEON_REG_UARTDATA2_OFFSET 0x80
-#define LEON_REG_UARTSTATUS2_OFFSET 0x84
-#define LEON_REG_UARTCTRL2_OFFSET 0x88
-#define LEON_REG_UARTSCALER2_OFFSET 0x8C
-#define LEON_REG_IRQMASK_OFFSET 0x90
-#define LEON_REG_IRQPEND_OFFSET 0x94
-#define LEON_REG_IRQFORCE_OFFSET 0x98
-#define LEON_REG_IRQCLEAR_OFFSET 0x9C
-#define LEON_REG_PIODATA_OFFSET 0xA0
-#define LEON_REG_PIODIR_OFFSET 0xA4
-#define LEON_REG_PIOIRQ_OFFSET 0xA8
-#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4
-#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8
-
-/*
- * Interrupt Sources
- *
- * The interrupt source numbers directly map to the trap type and to
- * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
- * and the Interrupt Pending Registers.
- */
-#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1
-#define LEON_INTERRUPT_UART_1_RX_TX 2
-#define LEON_INTERRUPT_UART_0_RX_TX 3
-#define LEON_INTERRUPT_EXTERNAL_0 4
-#define LEON_INTERRUPT_EXTERNAL_1 5
-#define LEON_INTERRUPT_EXTERNAL_2 6
-#define LEON_INTERRUPT_EXTERNAL_3 7
-#define LEON_INTERRUPT_TIMER1 8
-#define LEON_INTERRUPT_TIMER2 9
-#define LEON_INTERRUPT_EMPTY1 10
-#define LEON_INTERRUPT_EMPTY2 11
-#define LEON_INTERRUPT_OPEN_ETH 12
-#define LEON_INTERRUPT_EMPTY4 13
-#define LEON_INTERRUPT_EMPTY5 14
-#define LEON_INTERRUPT_EMPTY6 15
-
-/* Timer Bits */
-#define LEON2_TIMER_CTRL_EN 0x1 /* Timer enable */
-#define LEON2_TIMER_CTRL_RS 0x2 /* Timer reStart */
-#define LEON2_TIMER_CTRL_LD 0x4 /* Timer reLoad */
-#define LEON2_TIMER1_IRQNO 8 /* Timer 1 IRQ number */
-#define LEON2_TIMER2_IRQNO 9 /* Timer 2 IRQ number */
-#define LEON2_TIMER1_IE (1<<LEON2_TIMER1_IRQNO) /* Timer 1 interrupt enable */
-#define LEON2_TIMER2_IE (1<<LEON2_TIMER2_IRQNO) /* Timer 2 interrupt enable */
-
-/* UART bits */
-#define LEON2_UART_CTRL_RE 1 /* UART Receiver enable */
-#define LEON2_UART_CTRL_TE 2 /* UART Transmitter enable */
-#define LEON2_UART_CTRL_RI 4 /* UART Receiver Interrupt enable */
-#define LEON2_UART_CTRL_TI 8 /* UART Transmitter Interrupt enable */
-#define LEON2_UART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */
-
-#define LEON2_UART_STAT_DR 1 /* UART Data Ready */
-#define LEON2_UART_STAT_TSE 2 /* UART Transmit Shift Reg empty */
-#define LEON2_UART_STAT_THE 4 /* UART Transmit Hold Reg empty */
-
-#else
-#error Include LEON2 header file only if LEON2 processor
-#endif
-
-#endif
diff --git a/arch/sparc/include/asm/leon3.h b/arch/sparc/include/asm/leon3.h
deleted file mode 100644
index a9f32b9b9090..000000000000
--- a/arch/sparc/include/asm/leon3.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* LEON3 header file. LEON3 is a free GPL SOC processor available
- * at www.gaisler.com.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LEON3_H__
-#define __LEON3_H__
-
-#ifndef CONFIG_LEON3
-#error Include LEON3 header file only if LEON3 processor
-#endif
-
-/* Not much to define, most is Plug and Play and GRLIB dependent
- * not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
- * ctrl, memory controllers etc.
- */
-
-
-#ifndef __ASSEMBLER__
-/* The frequency of the CPU */
-extern unsigned int leon_cpu_freq;
-
-/* Number of LEON processors in system */
-extern int leon_cpu_cnt;
-
-/* Ver/subversion of CPU */
-extern int leon_ver;
-
-#endif /* __ASSEMBLER__ */
-
-#endif
diff --git a/arch/sparc/include/asm/linkage.h b/arch/sparc/include/asm/linkage.h
deleted file mode 100644
index e69de29bb2d1..000000000000
diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h
deleted file mode 100644
index e209f3fa608d..000000000000
--- a/arch/sparc/include/asm/machines.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* machines.h: Defines for taking apart the machine type value in the
- * idprom and determining the kind of machine we are on.
- *
- * Taken from the SPARC port of Linux.
- *
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_MACHINES_H__
-#define __SPARC_MACHINES_H__
-
-struct Sun_Machine_Models {
- char *name;
- unsigned char id_machtype;
-};
-
-/* Current number of machines we know about that has an IDPROM
- * machtype entry including one entry for the 0x80 OBP machines.
- */
-#define NUM_SUN_MACHINES 16
-
-extern struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES];
-
-/* The machine type in the idprom area looks like this:
- *
- * ---------------
- * | ARCH | MACH |
- * ---------------
- * 7 4 3 0
- *
- * The ARCH field determines the architecture line (sun4, sun4c, etc).
- * The MACH field determines the machine make within that architecture.
- */
-
-#define SM_ARCH_MASK 0xf0
-#define SM_SUN4 0x20
-#define M_LEON2 0x30
-#define SM_SUN4C 0x50
-#define SM_SUN4M 0x70
-#define SM_SUN4M_OBP 0x80
-
-#define SM_TYP_MASK 0x0f
-/* Sun4 machines */
-#define SM_4_260 0x01 /* Sun 4/200 series */
-#define SM_4_110 0x02 /* Sun 4/100 series */
-#define SM_4_330 0x03 /* Sun 4/300 series */
-#define SM_4_470 0x04 /* Sun 4/400 series */
-
-/* Leon machines */
-#define M_LEON2_SOC 0x01 /* Leon2 SoC */
-
-/* Sun4c machines Full Name - PROM NAME */
-#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
-#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
-#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
-#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
-#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
-#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
-#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
-
-/* Sun4m machines, these predate the OpenBoot. These values only mean
- * something if the value in the ARCH field is SM_SUN4M, if it is
- * SM_SUN4M_OBP then you have the following situation:
- * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
- * 2) You have to consult OpenBoot to determine which machine this is.
- */
-#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
-#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
-#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
-
-/* Sun4d machines -- N/A */
-/* Sun4e machines -- N/A */
-/* Sun4u machines -- N/A */
-
-#endif /* !(_SPARC_MACHINES_H) */
diff --git a/arch/sparc/include/asm/page.h b/arch/sparc/include/asm/page.h
deleted file mode 100644
index 181d1c195276..000000000000
--- a/arch/sparc/include/asm/page.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* page.h: Various defines and such for MMU operations on the Sparc for
- * the Linux kernel.
- *
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_PAGE_H
-#define _SPARC_PAGE_H
-
-#ifdef CONFIG_SUN4
-#define PAGE_SHIFT 13
-#else
-#define PAGE_SHIFT 12
-#endif
-
-#ifndef __ASSEMBLY__
-/* I have my suspicions... -DaveM */
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#endif
-
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#endif /* _SPARC_PAGE_H */
diff --git a/arch/sparc/include/asm/posix_types.h b/arch/sparc/include/asm/posix_types.h
deleted file mode 100644
index 61d3bbc9a19a..000000000000
--- a/arch/sparc/include/asm/posix_types.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007, taken from asm-ppc/posix_types.h
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_POSIX_TYPES_H__
-#define __SPARC_POSIX_TYPES_H__
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned int __kernel_dev_t;
-typedef unsigned int __kernel_ino_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef long __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned int __kernel_old_uid_t;
-typedef unsigned int __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
- int val[2];
-} __kernel_fsid_t;
-
-#ifndef __GNUC__
-
-#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-#define __FD_ZERO(set) \
- ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
-
-#else /* __GNUC__ */
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
- || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set * fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] |= (1UL << _rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set * fdsetp)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- fdsetp->fds_bits[_tmp] &= ~(1UL << _rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set * p)
-{
- unsigned long _tmp = fd / __NFDBITS;
- unsigned long _rem = fd % __NFDBITS;
- return (p->fds_bits[_tmp] & (1UL << _rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set * p)
-{
- unsigned int *tmp = (unsigned int *)p->fds_bits;
- int i;
-
- if (__builtin_constant_p(__FDSET_LONGS)) {
- switch (__FDSET_LONGS) {
- case 8:
- tmp[0] = 0;
- tmp[1] = 0;
- tmp[2] = 0;
- tmp[3] = 0;
- tmp[4] = 0;
- tmp[5] = 0;
- tmp[6] = 0;
- tmp[7] = 0;
- return;
- }
- }
- i = __FDSET_LONGS;
- while (i) {
- i--;
- *tmp = 0;
- tmp++;
- }
-}
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-#endif /* __GNUC__ */
-#endif /* _SPARC_POSIX_TYPES_H */
diff --git a/arch/sparc/include/asm/processor.h b/arch/sparc/include/asm/processor.h
deleted file mode 100644
index 9a6535d30df1..000000000000
--- a/arch/sparc/include/asm/processor.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPARC Processor specifics
- * taken from the SPARC port of Linux (ptrace.h).
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_SPARC_PROCESSOR_H
-#define __ASM_SPARC_PROCESSOR_H
-
-#include <asm/arch/asi.h>
-
-#ifdef CONFIG_LEON
-
-/* All LEON processors supported */
-#include <asm/leon.h>
-
-#else
-/* other processors */
-#error Unknown SPARC Processor
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* flush data cache */
-static __inline__ void sparc_dcache_flush_all(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
-}
-
-/* flush instruction cache */
-static __inline__ void sparc_icache_flush_all(void)
-{
- __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
-}
-
-/* do a cache miss load */
-static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
- long paddr)
-{
- unsigned long long retval;
- __asm__ __volatile__("ldda [%1] %2, %0\n\t":
- "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
- return retval;
-}
-
-static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
-{
- unsigned long retval;
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
- return retval;
-}
-
-static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
- paddr)
-{
- unsigned short retval;
- __asm__ __volatile__("lduha [%1] %2, %0\n\t":
- "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
- return retval;
-}
-
-static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
- paddr)
-{
- unsigned char retval;
- __asm__ __volatile__("lduba [%1] %2, %0\n\t":
- "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
- return retval;
-}
-
-/* do a physical address bypass write, i.e. for 0x80000000 */
-static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
- unsigned long value)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
- "i"(ASI_BYPASS):"memory");
-}
-
-static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
-{
- unsigned long retval;
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
- return retval;
-}
-
-/* Macros for bypassing cache when reading */
-#define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
-#define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address))
-#define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
-#define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address))
-
-#define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address))
-#define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
-
-#endif
-
-#endif /* __ASM_SPARC_PROCESSOR_H */
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
deleted file mode 100644
index 8906ef6cc79f..000000000000
--- a/arch/sparc/include/asm/prom.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* OpenProm defines mainly taken from linux kernel header files
- *
- * openprom.h: Prom structures and defines for access to the OPENBOOT
- * prom routines and data areas.
- *
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_OPENPROM_H__
-#define __SPARC_OPENPROM_H__
-
-/* Empirical constants... */
-#define LINUX_OPPROM_MAGIC 0x10010407
-
-#ifndef __ASSEMBLY__
-/* V0 prom device operations. */
-struct linux_dev_v0_funcs {
- int (*v0_devopen) (char *device_str);
- int (*v0_devclose) (int dev_desc);
- int (*v0_rdblkdev) (int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrblkdev) (int dev_desc, int num_blks, int blk_st, char *buf);
- int (*v0_wrnetdev) (int dev_desc, int num_bytes, char *buf);
- int (*v0_rdnetdev) (int dev_desc, int num_bytes, char *buf);
- int (*v0_rdchardev) (int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_wrchardev) (int dev_desc, int num_bytes, int dummy, char *buf);
- int (*v0_seekdev) (int dev_desc, long logical_offst, int from);
-};
-
-/* V2 and later prom device operations. */
-struct linux_dev_v2_funcs {
- int (*v2_inst2pkg) (int d); /* Convert ihandle to phandle */
- char *(*v2_dumb_mem_alloc) (char *va, unsigned sz);
- void (*v2_dumb_mem_free) (char *va, unsigned sz);
-
- /* To map devices into virtual I/O space. */
- char *(*v2_dumb_mmap) (char *virta, int which_io, unsigned paddr,
- unsigned sz);
- void (*v2_dumb_munmap) (char *virta, unsigned size);
-
- int (*v2_dev_open) (char *devpath);
- void (*v2_dev_close) (int d);
- int (*v2_dev_read) (int d, char *buf, int nbytes);
- int (*v2_dev_write) (int d, char *buf, int nbytes);
- int (*v2_dev_seek) (int d, int hi, int lo);
-
- /* Never issued (multistage load support) */
- void (*v2_wheee2) (void);
- void (*v2_wheee3) (void);
-};
-
-struct linux_mlist_v0 {
- struct linux_mlist_v0 *theres_more;
- char *start_adr;
- unsigned num_bytes;
-};
-
-struct linux_mem_v0 {
- struct linux_mlist_v0 **v0_totphys;
- struct linux_mlist_v0 **v0_prommap;
- struct linux_mlist_v0 **v0_available; /* What we can use */
-};
-
-/* Arguments sent to the kernel from the boot prompt. */
-struct linux_arguments_v0 {
- char * const argv[8];
- char args[100];
- char boot_dev[2];
- int boot_dev_ctrl;
- int boot_dev_unit;
- int dev_partition;
- char *kernel_file_name;
- void *aieee1; /* XXX */
-};
-
-/* V2 and up boot things. */
-struct linux_bootargs_v2 {
- char **bootpath;
- char **bootargs;
- int *fd_stdin;
- int *fd_stdout;
-};
-
-/* The top level PROM vector. */
-struct linux_romvec {
- /* Version numbers. */
- unsigned int pv_magic_cookie;
- unsigned int pv_romvers;
- unsigned int pv_plugin_revision;
- unsigned int pv_printrev;
-
- /* Version 0 memory descriptors. */
- struct linux_mem_v0 pv_v0mem;
-
- /* Node operations. */
- struct linux_nodeops *pv_nodeops;
-
- char **pv_bootstr;
- struct linux_dev_v0_funcs pv_v0devops;
-
- char *pv_stdin;
- char *pv_stdout;
-#define PROMDEV_KBD 0 /* input from keyboard */
-#define PROMDEV_SCREEN 0 /* output to screen */
-#define PROMDEV_TTYA 1 /* in/out to ttya */
-#define PROMDEV_TTYB 2 /* in/out to ttyb */
-
- /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
- int (*pv_getchar) (void);
- void (*pv_putchar) (int ch);
-
- /* Non-blocking variants. */
- int (*pv_nbgetchar) (void);
- int (*pv_nbputchar) (int ch);
-
- void (*pv_putstr) (char *str, int len);
-
- /* Miscellany. */
- void (*pv_reboot) (char *bootstr);
- void (*pv_printf) (__const__ char *fmt, ...);
- void (*pv_abort) (void);
- __volatile__ int *pv_ticks;
- void (*pv_halt) (void);
- void (**pv_synchook) (void);
-
- /* Evaluate a forth string, not different proto for V0 and V2->up. */
- union {
- void (*v0_eval) (int len, char *str);
- void (*v2_eval) (char *str);
- } pv_fortheval;
-
- struct linux_arguments_v0 **pv_v0bootargs;
-
- /* Get ether address. */
- unsigned int (*pv_enaddr) (int d, char *enaddr);
-
- struct linux_bootargs_v2 pv_v2bootargs;
- struct linux_dev_v2_funcs pv_v2devops;
-
- int filler[15];
-
- /* This one is sun4c/sun4 only. */
- void (*pv_setctxt) (int ctxt, char *va, int pmeg);
-
- /* Prom version 3 Multiprocessor routines. This stuff is crazy.
- * No joke. Calling these when there is only one cpu probably
- * crashes the machine, have to test this. :-)
- */
-
- /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
- * 'thiscontext' executing at address 'prog_counter'
- */
- int (*v3_cpustart) (unsigned int whichcpu, int ctxtbl_ptr,
- int thiscontext, char *prog_counter);
-
- /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
- * until a resume cpu call is made.
- */
- int (*v3_cpustop) (unsigned int whichcpu);
-
- /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
- * resume cpu call is made.
- */
- int (*v3_cpuidle) (unsigned int whichcpu);
-
- /* v3_cpuresume() will resume processor 'whichcpu' executing
- * starting with whatever 'pc' and 'npc' were left at the
- * last 'idle' or 'stop' call.
- */
- int (*v3_cpuresume) (unsigned int whichcpu);
-};
-
-/* Routines for traversing the prom device tree. */
-struct linux_nodeops {
- int (*no_nextnode) (int node);
- int (*no_child) (int node);
- int (*no_proplen) (int node, char *name);
- int (*no_getprop) (int node, char *name, char *val);
- int (*no_setprop) (int node, char *name, char *val, int len);
- char *(*no_nextprop) (int node, char *name);
-};
-
-/* More fun PROM structures for device probing. */
-#define PROMREG_MAX 16
-#define PROMVADDR_MAX 16
-#define PROMINTR_MAX 15
-
-struct linux_prom_registers {
- unsigned int which_io; /* is this in OBIO space? */
- unsigned int phys_addr; /* The physical address of this register */
- unsigned int reg_size; /* How many bytes does this register take up? */
-};
-
-struct linux_prom_irqs {
- int pri; /* IRQ priority */
- int vector; /* This is foobar, what does it do? */
-};
-
-/* Element of the "ranges" vector */
-struct linux_prom_ranges {
- unsigned int ot_child_space;
- unsigned int ot_child_base; /* Bus feels this */
- unsigned int ot_parent_space;
- unsigned int ot_parent_base; /* CPU looks from here */
- unsigned int or_size;
-};
-
-/* Ranges and reg properties are a bit different for PCI. */
-struct linux_prom_pci_registers {
- /*
- * We don't know what information this field contain.
- * We guess, PCI device function is in bits 15:8
- * So, ...
- */
- unsigned int which_io; /* Let it be which_io */
-
- unsigned int phys_hi;
- unsigned int phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_ranges {
- unsigned int child_phys_hi; /* Only certain bits are encoded here. */
- unsigned int child_phys_mid;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_pci_assigned_addresses {
- unsigned int which_io;
-
- unsigned int phys_hi;
- unsigned int phys_lo;
-
- unsigned int size_hi;
- unsigned int size_lo;
-};
-
-struct linux_prom_ebus_ranges {
- unsigned int child_phys_hi;
- unsigned int child_phys_lo;
-
- unsigned int parent_phys_hi;
- unsigned int parent_phys_mid;
- unsigned int parent_phys_lo;
-
- unsigned int size;
-};
-
-/* Offset into the EEPROM where the id PROM is located on the 4c */
-#define IDPROM_OFFSET 0x7d8
-
-/* On sun4m; physical. */
-/* MicroSPARC(-II) does not decode 31rd bit, but it works. */
-#define IDPROM_OFFSET_M 0xfd8
-
-struct idprom {
- unsigned char id_format; /* Format identifier (always 0x01) */
- unsigned char id_machtype; /* Machine type */
- unsigned char id_ethaddr[6]; /* Hardware ethernet address */
- long id_date; /* Date of manufacture */
- unsigned int id_sernum:24; /* Unique serial number */
- unsigned char id_cksum; /* Checksum - xor of the data bytes */
- unsigned char reserved[16];
-};
-
-extern struct idprom *idprom;
-extern void idprom_init(void);
-
-#define IDPROM_SIZE (sizeof(struct idprom))
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif
diff --git a/arch/sparc/include/asm/psr.h b/arch/sparc/include/asm/psr.h
deleted file mode 100644
index a91bdc903cb5..000000000000
--- a/arch/sparc/include/asm/psr.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* psr.h: This file holds the macros for masking off various parts of
- * the processor status register on the Sparc. This is valid
- * for Version 8. On the V9 this is renamed to the PSTATE
- * register and its members are accessed as fields like
- * PSTATE.PRIV for the current CPU privilege level.
- *
- * taken from the SPARC port of Linux,
- *
- * Copyright (C) 1994 David S. Miller (davem at caip.rutgers.edu)
- * Copyright (C) 2007 Daniel Hellstrom (daniel at gaisler.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_PSR_H__
-#define __SPARC_PSR_H__
-
-/* The Sparc PSR fields are laid out as the following:
- *
- * ------------------------------------------------------------------------
- * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
- * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
- * ------------------------------------------------------------------------
- */
-#define PSR_CWP 0x0000001f /* current window pointer */
-#define PSR_ET 0x00000020 /* enable traps field */
-#define PSR_PS 0x00000040 /* previous privilege level */
-#define PSR_S 0x00000080 /* current privilege level */
-#define PSR_PIL 0x00000f00 /* processor interrupt level */
-#define PSR_EF 0x00001000 /* enable floating point */
-#define PSR_EC 0x00002000 /* enable co-processor */
-#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
-#define PSR_ICC 0x00f00000 /* integer condition codes */
-#define PSR_C 0x00100000 /* carry bit */
-#define PSR_V 0x00200000 /* overflow bit */
-#define PSR_Z 0x00400000 /* zero bit */
-#define PSR_N 0x00800000 /* negative bit */
-#define PSR_VERS 0x0f000000 /* cpu-version field */
-#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
-
-#define PSR_PIL_OFS 8
-
-#ifndef __ASSEMBLY__
-/* Get the %psr register. */
-static __inline__ unsigned int get_psr(void)
-{
- unsigned int psr;
- __asm__ __volatile__("rd %%psr, %0\n\t"
- "nop\n\t" "nop\n\t" "nop\n\t":"=r"(psr)
- : /* no inputs */
- :"memory");
-
- return psr;
-}
-
-static __inline__ void put_psr(unsigned int new_psr)
-{
- __asm__ __volatile__("wr %0, 0x0, %%psr\n\t" "nop\n\t" "nop\n\t" "nop\n\t": /* no outputs */
- :"r"(new_psr)
- :"memory", "cc");
-}
-
-/* Get the %fsr register. Be careful, make sure the floating point
- * enable bit is set in the %psr when you execute this or you will
- * incur a trap.
- */
-
-extern unsigned int fsr_storage;
-
-static __inline__ unsigned int get_fsr(void)
-{
- unsigned int fsr = 0;
-
- __asm__ __volatile__("st %%fsr, %1\n\t"
- "ld %1, %0\n\t":"=r"(fsr)
- :"m"(fsr_storage));
-
- return fsr;
-}
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC_PSR_H__) */
diff --git a/arch/sparc/include/asm/ptrace.h b/arch/sparc/include/asm/ptrace.h
deleted file mode 100644
index 33cfbacb0c65..000000000000
--- a/arch/sparc/include/asm/ptrace.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Contain the Stack frame layout on interrupt. pt_regs.
- * taken from the SPARC port of Linux (ptrace.h).
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_PTRACE_H__
-#define __SPARC_PTRACE_H__
-
-#include <asm/psr.h>
-
-/* This struct defines the way the registers are stored on the
- * stack during a system call and basically all traps.
- */
-
-#ifndef __ASSEMBLY__
-
-struct pt_regs {
- unsigned long psr;
- unsigned long pc;
- unsigned long npc;
- unsigned long y;
- unsigned long u_regs[16]; /* globals and ins */
-};
-
-#define UREG_G0 0
-#define UREG_G1 1
-#define UREG_G2 2
-#define UREG_G3 3
-#define UREG_G4 4
-#define UREG_G5 5
-#define UREG_G6 6
-#define UREG_G7 7
-#define UREG_I0 8
-#define UREG_I1 9
-#define UREG_I2 10
-#define UREG_I3 11
-#define UREG_I4 12
-#define UREG_I5 13
-#define UREG_I6 14
-#define UREG_I7 15
-#define UREG_WIM UREG_G0
-#define UREG_FADDR UREG_G0
-#define UREG_FP UREG_I6
-#define UREG_RETPC UREG_I7
-
-/* A register window */
-struct reg_window {
- unsigned long locals[8];
- unsigned long ins[8];
-};
-
-/* A Sparc stack frame */
-struct sparc_stackf {
- unsigned long locals[8];
- unsigned long ins[6];
- struct sparc_stackf *fp;
- unsigned long callers_pc;
- char *structptr;
- unsigned long xargs[6];
- unsigned long xxargs[1];
-};
-
-#define TRACEREG_SZ sizeof(struct pt_regs)
-#define STACKFRAME_SZ sizeof(struct sparc_stackf)
-
-#else /* __ASSEMBLY__ */
-/* For assembly code. */
-#define TRACEREG_SZ 0x50
-#define STACKFRAME_SZ 0x60
-#endif
-
-/*
- * The asm_offsets.h is a generated file, so we cannot include it.
- * It may be OK for glibc headers, but it's utterly pointless for C code.
- * The assembly code using those offsets has to include it explicitly.
- */
-/* #include <asm/asm_offsets.h> */
-
-/* These are for pt_regs. */
-#define PT_PSR 0x0
-#define PT_PC 0x4
-#define PT_NPC 0x8
-#define PT_Y 0xc
-#define PT_G0 0x10
-#define PT_WIM PT_G0
-#define PT_G1 0x14
-#define PT_G2 0x18
-#define PT_G3 0x1c
-#define PT_G4 0x20
-#define PT_G5 0x24
-#define PT_G6 0x28
-#define PT_G7 0x2c
-#define PT_I0 0x30
-#define PT_I1 0x34
-#define PT_I2 0x38
-#define PT_I3 0x3c
-#define PT_I4 0x40
-#define PT_I5 0x44
-#define PT_I6 0x48
-#define PT_FP PT_I6
-#define PT_I7 0x4c
-
-/* Reg_window offsets */
-#define RW_L0 0x00
-#define RW_L1 0x04
-#define RW_L2 0x08
-#define RW_L3 0x0c
-#define RW_L4 0x10
-#define RW_L5 0x14
-#define RW_L6 0x18
-#define RW_L7 0x1c
-#define RW_I0 0x20
-#define RW_I1 0x24
-#define RW_I2 0x28
-#define RW_I3 0x2c
-#define RW_I4 0x30
-#define RW_I5 0x34
-#define RW_I6 0x38
-#define RW_I7 0x3c
-
-/* Stack_frame offsets */
-#define SF_L0 0x00
-#define SF_L1 0x04
-#define SF_L2 0x08
-#define SF_L3 0x0c
-#define SF_L4 0x10
-#define SF_L5 0x14
-#define SF_L6 0x18
-#define SF_L7 0x1c
-#define SF_I0 0x20
-#define SF_I1 0x24
-#define SF_I2 0x28
-#define SF_I3 0x2c
-#define SF_I4 0x30
-#define SF_I5 0x34
-#define SF_FP 0x38
-#define SF_PC 0x3c
-#define SF_RETP 0x40
-#define SF_XARG0 0x44
-#define SF_XARG1 0x48
-#define SF_XARG2 0x4c
-#define SF_XARG3 0x50
-#define SF_XARG4 0x54
-#define SF_XARG5 0x58
-#define SF_XXARG 0x5c
-
-/* Stuff for the ptrace system call */
-#define PTRACE_SUNATTACH 10
-#define PTRACE_SUNDETACH 11
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-#define PTRACE_READDATA 16
-#define PTRACE_WRITEDATA 17
-#define PTRACE_READTEXT 18
-#define PTRACE_WRITETEXT 19
-#define PTRACE_GETFPAREGS 20
-#define PTRACE_SETFPAREGS 21
-
-#define PTRACE_GETUCODE 29 /* stupid bsd-ism */
-
-#endif /* !(_SPARC_PTRACE_H) */
diff --git a/arch/sparc/include/asm/sections.h b/arch/sparc/include/asm/sections.h
deleted file mode 100644
index 65ad891ddecd..000000000000
--- a/arch/sparc/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_SPARC_SECTIONS_H
-#define __ASM_SPARC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/sparc/include/asm/srmmu.h b/arch/sparc/include/asm/srmmu.h
deleted file mode 100644
index 8da2f67f1ce9..000000000000
--- a/arch/sparc/include/asm/srmmu.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/* SRMMU page table defines and code,
- * taken from the SPARC port of Linux
- *
- * Copyright (C) 2007 Daniel Hellstrom (daniel at gaisler.com)
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_SRMMU_H__
-#define __SPARC_SRMMU_H__
-
-#include <asm/asi.h>
-#include <asm/page.h>
-
-/* Number of contexts is implementation-dependent; 64k is the most we support */
-#define SRMMU_MAX_CONTEXTS 65536
-
-/* PMD_SHIFT determines the size of the area a second-level page table entry can map */
-#define SRMMU_REAL_PMD_SHIFT 18
-#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
-#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
-#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SRMMU_PGDIR_SHIFT 24
-#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
-#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
-#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
-
-#define SRMMU_REAL_PTRS_PER_PTE 64
-#define SRMMU_REAL_PTRS_PER_PMD 64
-#define SRMMU_PTRS_PER_PGD 256
-
-#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
-#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
-#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
-
-/*
- * To support pagetables in highmem, Linux introduces APIs which
- * return struct page* and generally manipulate page tables when
- * they are not mapped into kernel space. Our hardware page tables
- * are smaller than pages. We lump hardware tabes into big, page sized
- * software tables.
- *
- * PMD_SHIFT determines the size of the area a second-level page table entry
- * can map, and our pmd_t is 16 times larger than normal. The values which
- * were once defined here are now generic for 4c and srmmu, so they're
- * found in pgtable.h.
- */
-#define SRMMU_PTRS_PER_PMD 4
-
-/* Definition of the values in the ET field of PTD's and PTE's */
-#define SRMMU_ET_MASK 0x3
-#define SRMMU_ET_INVALID 0x0
-#define SRMMU_ET_PTD 0x1
-#define SRMMU_ET_PTE 0x2
-#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
-
-/* Physical page extraction from PTP's and PTE's. */
-#define SRMMU_CTX_PMASK 0xfffffff0
-#define SRMMU_PTD_PMASK 0xfffffff0
-#define SRMMU_PTE_PMASK 0xffffff00
-
-/* The pte non-page bits. Some notes:
- * 1) cache, dirty, valid, and ref are frobbable
- * for both supervisor and user pages.
- * 2) exec and write will only give the desired effect
- * on user pages
- * 3) use priv and priv_readonly for changing the
- * characteristics of supervisor ptes
- */
-#define SRMMU_CACHE 0x80
-#define SRMMU_DIRTY 0x40
-#define SRMMU_REF 0x20
-#define SRMMU_NOREAD 0x10
-#define SRMMU_EXEC 0x08
-#define SRMMU_WRITE 0x04
-#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
-#define SRMMU_PRIV 0x1c
-#define SRMMU_PRIV_RDONLY 0x18
-
-#define SRMMU_FILE 0x40 /* Implemented in software */
-
-#define SRMMU_PTE_FILE_SHIFT 8 /* == 32-PTE_FILE_MAX_BITS */
-
-#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
-
-/* SRMMU swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset. This gives us
- * 32 swapfiles of 4GB each. Encoding looks like:
- *
- * oooooooooooooooooootttttRRRRRRRR
- * fedcba9876543210fedcba9876543210
- *
- * The bottom 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SRMMU_SWP_TYPE_MASK 0x1f
-#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
-#define SRMMU_SWP_OFF_MASK 0x7ffff
-#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
-
-/* Some day I will implement true fine grained access bits for
- * user pages because the SRMMU gives us the capabilities to
- * enforce all the protection levels that vma's can have.
- * XXX But for now...
- */
-#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
- SRMMU_PRIV | SRMMU_REF)
-#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
-#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
- SRMMU_EXEC | SRMMU_REF)
-#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
- SRMMU_DIRTY | SRMMU_REF)
-
-/* SRMMU Register addresses in ASI 0x4. These are valid for all
- * current SRMMU implementations that exist.
- */
-#define SRMMU_CTRL_REG 0x00000000
-#define SRMMU_CTXTBL_PTR 0x00000100
-#define SRMMU_CTX_REG 0x00000200
-#define SRMMU_FAULT_STATUS 0x00000300
-#define SRMMU_FAULT_ADDR 0x00000400
-
-#define WINDOW_FLUSH(tmp1, tmp2) \
- mov 0, tmp1; \
-98: ld [%g6 + TI_UWINMASK], tmp2; \
- orcc %g0, tmp2, %g0; \
- add tmp1, 1, tmp1; \
- bne 98b; \
- save %sp, -64, %sp; \
-99: subcc tmp1, 1, tmp1; \
- bne 99b; \
- restore %g0, %g0, %g0;
-
-#ifndef __ASSEMBLY__
-
-/* This makes sense. Honest it does - Anton */
-/* XXX Yes but it's ugly as sin. FIXME. -KMW */
-extern void *srmmu_nocache_pool;
-#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
-#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
-#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
-
-/* Accessing the MMU control register. */
-static __inline__ unsigned int srmmu_get_mmureg(void)
-{
- unsigned int retval;
- __asm__ __volatile__("lda [%%g0] %1, %0\n\t":
- "=r"(retval):"i"(ASI_M_MMUREGS));
- return retval;
-}
-
-static __inline__ void srmmu_set_mmureg(unsigned long regval)
-{
- __asm__ __volatile__("sta %0, [%%g0] %1\n\t"::"r"(regval),
- "i"(ASI_M_MMUREGS):"memory");
-
-}
-
-static __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
-{
- paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
- __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(paddr),
- "r"(SRMMU_CTXTBL_PTR),
- "i"(ASI_M_MMUREGS):"memory");
-}
-
-static __inline__ unsigned long srmmu_get_ctable_ptr(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):
- "r"(SRMMU_CTXTBL_PTR), "i"(ASI_M_MMUREGS));
- return (retval & SRMMU_CTX_PMASK) << 4;
-}
-
-static __inline__ void srmmu_set_context(int context)
-{
- __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(context),
- "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS):"memory");
-}
-
-static __inline__ int srmmu_get_context(void)
-{
- register int retval;
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):
- "r"(SRMMU_CTX_REG), "i"(ASI_M_MMUREGS));
- return retval;
-}
-
-static __inline__ unsigned int srmmu_get_fstatus(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):
- "r"(SRMMU_FAULT_STATUS), "i"(ASI_M_MMUREGS));
- return retval;
-}
-
-static __inline__ unsigned int srmmu_get_faddr(void)
-{
- unsigned int retval;
-
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):
- "r"(SRMMU_FAULT_ADDR), "i"(ASI_M_MMUREGS));
- return retval;
-}
-
-/* This is guaranteed on all SRMMU's. */
-static __inline__ void srmmu_flush_whole_tlb(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), /* Flush entire TLB!! */
- "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-/* These flush types are not available on all chips... */
-static __inline__ void srmmu_flush_tlb_ctx(void)
-{
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x300), /* Flush TLB ctx.. */
- "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_region(unsigned long addr)
-{
- addr &= SRMMU_PGDIR_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x200), /* Flush TLB region.. */
- "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
-{
- addr &= SRMMU_REAL_PMD_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(addr | 0x100), /* Flush TLB segment.. */
- "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ void srmmu_flush_tlb_page(unsigned long page)
-{
- page &= PAGE_MASK;
- __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(page), /* Flush TLB page.. */
- "i"(ASI_M_FLUSH_PROBE):"memory");
-
-}
-
-static __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
-{
- unsigned long retval;
-
- vaddr &= PAGE_MASK;
- __asm__ __volatile__("lda [%1] %2, %0\n\t":
- "=r"(retval):
- "r"(vaddr | 0x400), "i"(ASI_M_FLUSH_PROBE));
-
- return retval;
-}
-
-static __inline__ int srmmu_get_pte(unsigned long addr)
-{
- register unsigned long entry;
-
- __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t":
- "=r"(entry):
- "r"((addr & 0xfffff000) | 0x400),
- "i"(ASI_M_FLUSH_PROBE));
- return entry;
-}
-
-extern unsigned long (*srmmu_read_physical) (unsigned long paddr);
-extern void (*srmmu_write_physical) (unsigned long paddr, unsigned long word);
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC_SRMMU_H__) */
diff --git a/arch/sparc/include/asm/stack.h b/arch/sparc/include/asm/stack.h
deleted file mode 100644
index fcab92096b07..000000000000
--- a/arch/sparc/include/asm/stack.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPARC stack layout Macros and structures,
- * mainly taken from BCC (the Bare C compiler for
- * SPARC LEON2/3) sources.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_STACK_H__
-#define __SPARC_STACK_H__
-
-#include <asm/ptrace.h>
-
-#ifndef __ASSEMBLER__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PT_REGS_SZ sizeof(struct pt_regs)
-
-/* A Sparc stack frame */
- struct sparc_stackframe_regs {
- unsigned long sf_locals[8];
- unsigned long sf_ins[6];
- struct sparc_stackframe_regs *sf_fp;
- unsigned long sf_callers_pc;
- char *sf_structptr;
- unsigned long sf_xargs[6];
- unsigned long sf_xxargs[1];
- };
-#define SF_REGS_SZ sizeof(struct sparc_stackframe_regs)
-
-/* A register window */
- struct sparc_regwindow_regs {
- unsigned long locals[8];
- unsigned long ins[8];
- };
-#define RW_REGS_SZ sizeof(struct sparc_regwindow_regs)
-
-/* A fpu window */
- struct sparc_fpuwindow_regs {
- unsigned long locals[32];
- unsigned long fsr;
- unsigned long lastctx;
- };
-#define FW_REGS_SZ sizeof(struct sparc_fpuwindow_regs)
-
-#ifdef __cplusplus
-}
-#endif
-#else
-#define PT_REGS_SZ 0x50 /* 20*4 */
-#define SF_REGS_SZ 0x60 /* 24*4 */
-#define RW_REGS_SZ 0x20 /* 16*4 */
-#define FW_REGS_SZ 0x88 /* 34*4 */
-#endif /* !ASM */
-
-/* These are for pt_regs. */
-#define PT_PSR 0x0
-#define PT_PC 0x4
-#define PT_NPC 0x8
-#define PT_Y 0xc
-#define PT_G0 0x10
-#define PT_WIM PT_G0
-#define PT_G1 0x14
-#define PT_G2 0x18
-#define PT_G3 0x1c
-#define PT_G4 0x20
-#define PT_G5 0x24
-#define PT_G6 0x28
-#define PT_G7 0x2c
-#define PT_I0 0x30
-#define PT_I1 0x34
-#define PT_I2 0x38
-#define PT_I3 0x3c
-#define PT_I4 0x40
-#define PT_I5 0x44
-#define PT_I6 0x48
-#define PT_FP PT_I6
-#define PT_I7 0x4c
-
-/* Stack_frame offsets */
-#define SF_L0 0x00
-#define SF_L1 0x04
-#define SF_L2 0x08
-#define SF_L3 0x0c
-#define SF_L4 0x10
-#define SF_L5 0x14
-#define SF_L6 0x18
-#define SF_L7 0x1c
-#define SF_I0 0x20
-#define SF_I1 0x24
-#define SF_I2 0x28
-#define SF_I3 0x2c
-#define SF_I4 0x30
-#define SF_I5 0x34
-#define SF_FP 0x38
-#define SF_PC 0x3c
-#define SF_RETP 0x40
-#define SF_XARG0 0x44
-#define SF_XARG1 0x48
-#define SF_XARG2 0x4c
-#define SF_XARG3 0x50
-#define SF_XARG4 0x54
-#define SF_XARG5 0x58
-#define SF_XXARG 0x5c
-
-/* Reg_window offsets */
-#define RW_L0 0x00
-#define RW_L1 0x04
-#define RW_L2 0x08
-#define RW_L3 0x0c
-#define RW_L4 0x10
-#define RW_L5 0x14
-#define RW_L6 0x18
-#define RW_L7 0x1c
-#define RW_I0 0x20
-#define RW_I1 0x24
-#define RW_I2 0x28
-#define RW_I3 0x2c
-#define RW_I4 0x30
-#define RW_I5 0x34
-#define RW_I6 0x38
-#define RW_I7 0x3c
-
-/* Fpu_window offsets */
-#define FW_F0 0x00
-#define FW_F2 0x08
-#define FW_F4 0x10
-#define FW_F6 0x18
-#define FW_F8 0x20
-#define FW_F10 0x28
-#define FW_F12 0x30
-#define FW_F14 0x38
-#define FW_F16 0x40
-#define FW_F18 0x48
-#define FW_F20 0x50
-#define FW_F22 0x58
-#define FW_F24 0x60
-#define FW_F26 0x68
-#define FW_F28 0x70
-#define FW_F30 0x78
-#define FW_FSR 0x80
-
-#endif
diff --git a/arch/sparc/include/asm/string.h b/arch/sparc/include/asm/string.h
deleted file mode 100644
index d9cc5dba62e0..000000000000
--- a/arch/sparc/include/asm/string.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_STRING_H_
-#define _SPARC_STRING_H_
-
-/*
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_BCOPY
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCHR
-*/
-
-extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, __kernel_size_t);
-extern char *strcpy(char *, const char *);
-extern char *strncpy(char *, const char *, __kernel_size_t);
-extern __kernel_size_t strlen(const char *);
-extern int strcmp(const char *, const char *);
-extern char *strcat(char *, const char *);
-extern void *memset(void *, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void *memmove(void *, const void *, __kernel_size_t);
-extern int memcmp(const void *, const void *, __kernel_size_t);
-extern void *memchr(const void *, int, __kernel_size_t);
-
-#endif
diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h
deleted file mode 100644
index 72030b264ef7..000000000000
--- a/arch/sparc/include/asm/types.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SPARC_TYPES_H
-#define _SPARC_TYPES_H
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-typedef struct {
- __u32 u[4];
-} __attribute__((aligned(16))) vector128;
-
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h
deleted file mode 100644
index 75ac7dc62a27..000000000000
--- a/arch/sparc/include/asm/u-boot.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2000 - 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __U_BOOT_H__
-#define __U_BOOT_H__
-
-/* Currently, this board information is not passed to
- * Linux kernel from U-Boot, but may be passed to other
- * Operating systems. This is because U-Boot emulates
- * a SUN PROM loader (from Linux point of view).
- */
-#include <asm-generic/u-boot.h>
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_SPARC
-
-#endif
diff --git a/arch/sparc/include/asm/unaligned.h b/arch/sparc/include/asm/unaligned.h
deleted file mode 100644
index 0e646f7fa955..000000000000
--- a/arch/sparc/include/asm/unaligned.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ASM_SPARC_UNALIGNED_H
-#define _ASM_SPARC_UNALIGNED_H
-
-/*
- * The SPARC can not do unaligned accesses, it must be split into multiple
- * byte accesses. The SPARC is in big endian mode.
- */
-#include <asm-generic/unaligned.h>
-
-#endif /* _ASM_SPARC_UNALIGNED_H */
diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h
deleted file mode 100644
index 916ee9c5a3a9..000000000000
--- a/arch/sparc/include/asm/winmacro.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Added to U-Boot,
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com
- * Copyright (C) 2007
- *
- * LEON2/3 LIBIO low-level routines
- * Written by Jiri Gaisler.
- * Copyright (C) 2004 Gaisler Research AB
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __SPARC_WINMACRO_H__
-#define __SPARC_WINMACRO_H__
-
-#include <asm/asmmacro.h>
-#include <asm/stack.h>
-
-/* Store the register window onto the 8-byte aligned area starting
- * at %reg. It might be %sp, it might not, we don't care.
- */
-#define RW_STORE(reg) \
- std %l0, [%reg + RW_L0]; \
- std %l2, [%reg + RW_L2]; \
- std %l4, [%reg + RW_L4]; \
- std %l6, [%reg + RW_L6]; \
- std %i0, [%reg + RW_I0]; \
- std %i2, [%reg + RW_I2]; \
- std %i4, [%reg + RW_I4]; \
- std %i6, [%reg + RW_I6];
-
-/* Load a register window from the area beginning at %reg. */
-#define RW_LOAD(reg) \
- ldd [%reg + RW_L0], %l0; \
- ldd [%reg + RW_L2], %l2; \
- ldd [%reg + RW_L4], %l4; \
- ldd [%reg + RW_L6], %l6; \
- ldd [%reg + RW_I0], %i0; \
- ldd [%reg + RW_I2], %i2; \
- ldd [%reg + RW_I4], %i4; \
- ldd [%reg + RW_I6], %i6;
-
-/* Loading and storing struct pt_reg trap frames. */
-#define PT_LOAD_INS(base_reg) \
- ldd [%base_reg + SF_REGS_SZ + PT_I0], %i0; \
- ldd [%base_reg + SF_REGS_SZ + PT_I2], %i2; \
- ldd [%base_reg + SF_REGS_SZ + PT_I4], %i4; \
- ldd [%base_reg + SF_REGS_SZ + PT_I6], %i6;
-
-#define PT_LOAD_GLOBALS(base_reg) \
- ld [%base_reg + SF_REGS_SZ + PT_G1], %g1; \
- ldd [%base_reg + SF_REGS_SZ + PT_G2], %g2; \
- ldd [%base_reg + SF_REGS_SZ + PT_G4], %g4; \
- ldd [%base_reg + SF_REGS_SZ + PT_G6], %g6;
-
-#define PT_LOAD_YREG(base_reg, scratch) \
- ld [%base_reg + SF_REGS_SZ + PT_Y], %scratch; \
- wr %scratch, 0x0, %y;
-
-#define PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
- ld [%base_reg + SF_REGS_SZ + PT_PSR], %pt_psr; \
- ld [%base_reg + SF_REGS_SZ + PT_PC], %pt_pc; \
- ld [%base_reg + SF_REGS_SZ + PT_NPC], %pt_npc;
-
-#define PT_LOAD_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
- PT_LOAD_YREG(base_reg, scratch) \
- PT_LOAD_INS(base_reg) \
- PT_LOAD_GLOBALS(base_reg) \
- PT_LOAD_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
-
-#define PT_STORE_INS(base_reg) \
- std %i0, [%base_reg + SF_REGS_SZ + PT_I0]; \
- std %i2, [%base_reg + SF_REGS_SZ + PT_I2]; \
- std %i4, [%base_reg + SF_REGS_SZ + PT_I4]; \
- std %i6, [%base_reg + SF_REGS_SZ + PT_I6];
-
-#define PT_STORE_GLOBALS(base_reg) \
- st %g1, [%base_reg + SF_REGS_SZ + PT_G1]; \
- std %g2, [%base_reg + SF_REGS_SZ + PT_G2]; \
- std %g4, [%base_reg + SF_REGS_SZ + PT_G4]; \
- std %g6, [%base_reg + SF_REGS_SZ + PT_G6];
-
-#define PT_STORE_YREG(base_reg, scratch) \
- rd %y, %scratch; \
- st %scratch, [%base_reg + SF_REGS_SZ + PT_Y];
-
-#define PT_STORE_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
- st %pt_psr, [%base_reg + SF_REGS_SZ + PT_PSR]; \
- st %pt_pc, [%base_reg + SF_REGS_SZ + PT_PC]; \
- st %pt_npc, [%base_reg + SF_REGS_SZ + PT_NPC];
-
-#define PT_STORE_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
- PT_STORE_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
- PT_STORE_GLOBALS(base_reg) \
- PT_STORE_YREG(base_reg, g_scratch) \
- PT_STORE_INS(base_reg)
-
-/* Store the fpu register window*/
-#define FW_STORE(reg) \
- std %f0, [reg + FW_F0]; \
- std %f2, [reg + FW_F2]; \
- std %f4, [reg + FW_F4]; \
- std %f6, [reg + FW_F6]; \
- std %f8, [reg + FW_F8]; \
- std %f10, [reg + FW_F10]; \
- std %f12, [reg + FW_F12]; \
- std %f14, [reg + FW_F14]; \
- std %f16, [reg + FW_F16]; \
- std %f18, [reg + FW_F18]; \
- std %f20, [reg + FW_F20]; \
- std %f22, [reg + FW_F22]; \
- std %f24, [reg + FW_F24]; \
- std %f26, [reg + FW_F26]; \
- std %f28, [reg + FW_F28]; \
- std %f30, [reg + FW_F30]; \
- st %fsr, [reg + FW_FSR];
-
-/* Load a fpu register window from the area beginning at reg. */
-#define FW_LOAD(reg) \
- ldd [reg + FW_F0], %f0; \
- ldd [reg + FW_F2], %f2; \
- ldd [reg + FW_F4], %f4; \
- ldd [reg + FW_F6], %f6; \
- ldd [reg + FW_F8], %f8; \
- ldd [reg + FW_F10], %f10; \
- ldd [reg + FW_F12], %f12; \
- ldd [reg + FW_F14], %f14; \
- ldd [reg + FW_F16], %f16; \
- ldd [reg + FW_F18], %f18; \
- ldd [reg + FW_F20], %f20; \
- ldd [reg + FW_F22], %f22; \
- ldd [reg + FW_F24], %f24; \
- ldd [reg + FW_F26], %f26; \
- ldd [reg + FW_F28], %f28; \
- ldd [reg + FW_F30], %f30; \
- ld [reg + FW_FSR], %fsr;
-
-#endif
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
deleted file mode 100644
index 6b7ad6d1555a..000000000000
--- a/arch/sparc/lib/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2015
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cache.o interrupts.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/sparc/lib/bootm.c b/arch/sparc/lib/bootm.c
deleted file mode 100644
index 927a351013a2..000000000000
--- a/arch/sparc/lib/bootm.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* SPARC code for booting linux 2.6
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/byteorder.h>
-#include <asm/prom.h>
-#include <asm/cache.h>
-#include <image.h>
-
-#define PRINT_KERNEL_HEADER
-
-extern image_header_t header;
-extern void srmmu_init_cpu(unsigned int entry);
-extern void prepare_bootargs(char *bootargs);
-
-/* sparc kernel argument (the ROM vector) */
-struct linux_romvec *kernel_arg_promvec;
-
-/* page szie is 4k */
-#define PAGE_SIZE 0x1000
-#define RAMDISK_IMAGE_START_MASK 0x07FF
-#define RAMDISK_PROMPT_FLAG 0x8000
-#define RAMDISK_LOAD_FLAG 0x4000
-struct __attribute__ ((packed)) {
- char traptable[PAGE_SIZE];
- char swapper_pg_dir[PAGE_SIZE];
- char pg0[PAGE_SIZE];
- char pg1[PAGE_SIZE];
- char pg2[PAGE_SIZE];
- char pg3[PAGE_SIZE];
- char empty_bad_page[PAGE_SIZE];
- char empty_bad_page_table[PAGE_SIZE];
- char empty_zero_page[PAGE_SIZE];
- unsigned char hdr[4]; /* ascii "HdrS" */
- /* 00.02.06.0b is for Linux kernel 2.6.11 */
- unsigned char linuxver_mega_major;
- unsigned char linuxver_major;
- unsigned char linuxver_minor;
- unsigned char linuxver_revision;
- /* header version 0x0203 */
- unsigned short hdr_ver;
- union __attribute__ ((packed)) {
- struct __attribute__ ((packed)) {
- unsigned short root_flags;
- unsigned short root_dev;
- unsigned short ram_flags;
- unsigned int sparc_ramdisk_image;
- unsigned int sparc_ramdisk_size;
- unsigned int reboot_command;
- unsigned int resv[3];
- unsigned int end;
- } ver_0203;
- } hdr_input;
-} *linux_hdr;
-
-/* temporary initrd image holder */
-image_header_t ihdr;
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- /* Reserve the space used by PROM and stack. This is done
- * to avoid that the RAM image is copied over stack or
- * PROM.
- */
- lmb_reserve(lmb, CONFIG_SYS_RELOC_MONITOR_BASE, CONFIG_SYS_RAM_END);
-}
-
-/* boot the linux kernel */
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t * images)
-{
- char *bootargs;
- ulong rd_len;
- void (*kernel) (struct linux_romvec *, void *);
- int ret;
-
- /*
- * allow the PREP bootm subcommand, it is required for bootm to work
- */
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
-
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- /* Get virtual address of kernel start */
- linux_hdr = (void *)images->os.load;
-
- /* */
- kernel = (void (*)(struct linux_romvec *, void *))images->ep;
-
- /* check for a SPARC kernel */
- if ((linux_hdr->hdr[0] != 'H') ||
- (linux_hdr->hdr[1] != 'd') ||
- (linux_hdr->hdr[2] != 'r') || (linux_hdr->hdr[3] != 'S')) {
- puts("Error reading header of SPARC Linux kernel, aborting\n");
- goto error;
- }
-#ifdef PRINT_KERNEL_HEADER
- printf("## Found SPARC Linux kernel %d.%d.%d ...\n",
- linux_hdr->linuxver_major,
- linux_hdr->linuxver_minor, linux_hdr->linuxver_revision);
-#endif
-
- /* set basic boot params in kernel header now that it has been
- * extracted and is writeable.
- */
-
- ret = image_setup_linux(images);
- if (ret) {
- puts("### Failed to relocate RAM disk\n");
- goto error;
- }
-
- /* Calc length of RAM disk, if zero no ramdisk available */
- rd_len = images->rd_end - images->rd_start;
-
- if (rd_len) {
- /* Update SPARC kernel header so that Linux knows
- * what is going on and where to find RAM disk.
- *
- * Set INITRD Image address relative to RAM Start
- */
- linux_hdr->hdr_input.ver_0203.sparc_ramdisk_image =
- images->initrd_start - CONFIG_SYS_RAM_BASE;
- linux_hdr->hdr_input.ver_0203.sparc_ramdisk_size = rd_len;
- /* Clear READ ONLY flag if set to non-zero */
- linux_hdr->hdr_input.ver_0203.root_flags = 1;
- /* Set root device to: Root_RAM0 */
- linux_hdr->hdr_input.ver_0203.root_dev = 0x100;
- linux_hdr->hdr_input.ver_0203.ram_flags = 0;
- } else {
- /* NOT using RAMDISK image, overwriting kernel defaults */
- linux_hdr->hdr_input.ver_0203.sparc_ramdisk_image = 0;
- linux_hdr->hdr_input.ver_0203.sparc_ramdisk_size = 0;
- /* Leave to kernel defaults
- linux_hdr->hdr_input.ver_0203.root_flags = 1;
- linux_hdr->hdr_input.ver_0203.root_dev = 0;
- linux_hdr->hdr_input.ver_0203.ram_flags = 0;
- */
- }
-
- /* Copy bootargs from bootargs variable to kernel readable area */
- bootargs = getenv("bootargs");
- prepare_bootargs(bootargs);
-
- /* turn on mmu & setup context table & page table for process 0 (kernel) */
- srmmu_init_cpu((unsigned int)kernel);
-
- /* Enter SPARC Linux kernel
- * From now on the only code in u-boot that will be
- * executed is the PROM code.
- */
- kernel(kernel_arg_promvec, (void *)images->ep);
-
- /* It will never come to this... */
- while (1) ;
-
- error:
- return 1;
-}
diff --git a/arch/sparc/lib/cache.c b/arch/sparc/lib/cache.c
deleted file mode 100644
index fd17467f7078..000000000000
--- a/arch/sparc/lib/cache.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Sparc cache library
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-void flush_cache(ulong start_addr, ulong size)
-{
- /* Flush All Cache */
- sparc_dcache_flush_all();
- sparc_icache_flush_all();
-}
diff --git a/arch/sparc/lib/interrupts.c b/arch/sparc/lib/interrupts.c
deleted file mode 100644
index cb73d17999dc..000000000000
--- a/arch/sparc/lib/interrupts.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-
-/* Implemented by SPARC CPUs */
-extern int interrupt_init_cpu(void);
-extern void timer_interrupt_cpu(void *arg);
-extern int timer_interrupt_init_cpu(void);
-
-int intLock(void)
-{
- unsigned int pil;
-
- pil = get_pil();
-
- /* set PIL to 15 ==> no pending interrupts will interrupt CPU */
- set_pil(15);
-
- return pil;
-}
-
-void intUnlock(int oldLevel)
-{
- set_pil(oldLevel);
-}
-
-void enable_interrupts(void)
-{
- set_pil(0); /* enable all interrupts */
-}
-
-int disable_interrupts(void)
-{
- return intLock();
-}
-
-int interrupt_is_enabled(void)
-{
- if (get_pil() == 15)
- return 0;
- return 1;
-}
-
-int interrupt_init(void)
-{
- int ret;
-
- /* call cpu specific function from $(CPU)/interrupts.c */
- ret = interrupt_init_cpu();
-
- /* enable global interrupts */
- enable_interrupts();
-
- return ret;
-}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ef5315631476..586d15962945 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -608,20 +608,6 @@ endmenu
menu "Misc commands"
-config CMD_AMBAPP
- bool "ambapp"
- depends on LEON3
- default y
- help
- Lists AMBA Plug-n-Play information.
-
-config SYS_AMBAPP_PRINT_ON_STARTUP
- bool "Show AMBA PnP info on startup"
- depends on CMD_AMBAPP
- default n
- help
- Show AMBA Plug-n-Play information on startup.
-
config CMD_BKOPS_ENABLE
bool "mmc bkops enable"
depends on CMD_MMC
diff --git a/cmd/Makefile b/cmd/Makefile
index f13bb8c11ecb..ef1406b3f86a 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -14,7 +14,6 @@ obj-y += version.o
# command
obj-$(CONFIG_CMD_AES) += aes.o
-obj-$(CONFIG_CMD_AMBAPP) += ambapp.o
obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
obj-$(CONFIG_SOURCE) += source.o
obj-$(CONFIG_CMD_SOURCE) += source.o
diff --git a/cmd/ambapp.c b/cmd/ambapp.c
deleted file mode 100644
index 4b6d1741e9bf..000000000000
--- a/cmd/ambapp.c
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * AMBA Plug&Play information list command
- *
- */
-#include <common.h>
-#include <command.h>
-#include <ambapp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-typedef struct {
- int device_id;
- char *name;
- char *desc;
-} ambapp_device_name;
-
-typedef struct {
- unsigned int vendor_id;
- char *name;
- char *desc;
- ambapp_device_name *devices;
-} ambapp_vendor_devnames;
-
-/** Vendor GAISLER devices */
-static ambapp_device_name GAISLER_devices[] = {
- {GAISLER_LEON2DSU, "LEON2DSU", "Leon2 Debug Support Unit"},
- {GAISLER_LEON3, "LEON3", "Leon3 SPARC V8 Processor"},
- {GAISLER_LEON3DSU, "LEON3DSU", "Leon3 Debug Support Unit"},
- {GAISLER_ETHAHB, "ETHAHB", "OC ethernet AHB interface"},
- {GAISLER_APBMST, "APBMST", "AHB/APB Bridge"},
- {GAISLER_AHBUART, "AHBUART", "AHB Debug UART"},
- {GAISLER_SRCTRL, "SRCTRL", "Simple SRAM Controller"},
- {GAISLER_SDCTRL, "SDCTRL", "PC133 SDRAM Controller"},
- {GAISLER_SSRCTRL, "SSRCTRL", "Synchronous SRAM Controller"},
- {GAISLER_APBUART, "APBUART", "Generic UART"},
- {GAISLER_IRQMP, "IRQMP", "Multi-processor Interrupt Ctrl."},
- {GAISLER_AHBRAM, "AHBRAM", "Single-port AHB SRAM module"},
- {GAISLER_AHBDPRAM, "AHBDPRAM", "Dual-port AHB SRAM module"},
- {GAISLER_GPTIMER, "GPTIMER", "Modular Timer Unit"},
- {GAISLER_PCITRG, "PCITRG", "Simple 32-bit PCI Target"},
- {GAISLER_PCISBRG, "PCISBRG", "Simple 32-bit PCI Bridge"},
- {GAISLER_PCIFBRG, "PCIFBRG", "Fast 32-bit PCI Bridge"},
- {GAISLER_PCITRACE, "PCITRACE", "32-bit PCI Trace Buffer"},
- {GAISLER_DMACTRL, "DMACTRL", "AMBA DMA controller"},
- {GAISLER_AHBTRACE, "AHBTRACE", "AMBA Trace Buffer"},
- {GAISLER_DSUCTRL, "DSUCTRL", "DSU/ETH controller"},
- {GAISLER_CANAHB, "CANAHB", "OC CAN AHB interface"},
- {GAISLER_GPIO, "GPIO", "General Purpose I/O port"},
- {GAISLER_AHBROM, "AHBROM", "Generic AHB ROM"},
- {GAISLER_AHBJTAG, "AHBJTAG", "JTAG Debug Link"},
- {GAISLER_ETHMAC, "ETHMAC", "GR Ethernet MAC"},
- {GAISLER_SWNODE, "SWNODE", "SpaceWire Node Interface"},
- {GAISLER_SPW, "SPW", "SpaceWire Serial Link"},
- {GAISLER_AHB2AHB, "AHB2AHB", "AHB-to-AHB Bridge"},
- {GAISLER_USBDC, "USBDC", "GR USB 2.0 Device Controller"},
- {GAISLER_USB_DCL, "USB_DCL", "USB Debug Communication Link"},
- {GAISLER_DDRMP, "DDRMP", "Multi-port DDR controller"},
- {GAISLER_ATACTRL, "ATACTRL", "ATA controller"},
- {GAISLER_DDRSP, "DDRSP", "Single-port DDR266 controller"},
- {GAISLER_EHCI, "EHCI", "USB Enhanced Host Controller"},
- {GAISLER_UHCI, "UHCI", "USB Universal Host Controller"},
- {GAISLER_I2CMST, "I2CMST", "AMBA Wrapper for OC I2C-master"},
- {GAISLER_SPW2, "SPW2", "GRSPW2 SpaceWire Serial Link"},
- {GAISLER_AHBDMA, "AHBDMA", ""},
- {GAISLER_NUHOSP3, "NUHOSP3", "Nuhorizons Spartan3 IO I/F"},
- {GAISLER_CLKGATE, "CLKGATE", "Clock gating unit"},
- {GAISLER_SPICTRL, "SPICTRL", "SPI Controller"},
- {GAISLER_DDR2SP, "DDR2SP", "Single-port DDR2 controller"},
- {GAISLER_SLINK, "SLINK", "SLINK Master"},
- {GAISLER_GRTM, "GRTM", "CCSDS Telemetry Encoder"},
- {GAISLER_GRTC, "GRTC", "CCSDS Telecommand Decoder"},
- {GAISLER_GRPW, "GRPW", "PacketWire to AMBA AHB I/F"},
- {GAISLER_GRCTM, "GRCTM", "CCSDS Time Manager"},
- {GAISLER_GRHCAN, "GRHCAN", "ESA HurriCANe CAN with DMA"},
- {GAISLER_GRFIFO, "GRFIFO", "FIFO Controller"},
- {GAISLER_GRADCDAC, "GRADCDAC", "ADC / DAC Interface"},
- {GAISLER_GRPULSE, "GRPULSE", "General Purpose I/O with Pulses"},
- {GAISLER_GRTIMER, "GRTIMER", "Timer Unit with Latches"},
- {GAISLER_AHB2PP, "AHB2PP", "AMBA AHB to Packet Parallel I/F"},
- {GAISLER_GRVERSION, "GRVERSION", "Version and Revision Register"},
- {GAISLER_APB2PW, "APB2PW", "PacketWire Transmit Interface"},
- {GAISLER_PW2APB, "PW2APB", "PacketWire Receive Interface"},
- {GAISLER_GRCAN, "GRCAN", "CAN Controller with DMA"},
- {GAISLER_I2CSLV, "I2CSLV", "I2C Slave"},
- {GAISLER_U16550, "U16550", "Simple 16550 UART"},
- {GAISLER_AHBMST_EM, "AHBMST_EM", "AMBA Master Emulator"},
- {GAISLER_AHBSLV_EM, "AHBSLV_EM", "AMBA Slave Emulator"},
- {GAISLER_GRTESTMOD, "GRTESTMOD", "Test report module"},
- {GAISLER_ASCS, "ASCS", "ASCS Master"},
- {GAISLER_IPMVBCTRL, "IPMVBCTRL", "IPM-bus/MVBC memory controller"},
- {GAISLER_SPIMCTRL, "SPIMCTRL", "SPI Memory Controller"},
- {GAISLER_L4STAT, "L4STAT", "Leon4 Statistics Module"},
- {GAISLER_LEON4, "LEON4", "Leon4 SPARC V8 Processor"},
- {GAISLER_LEON4DSU, "LEON4DSU", "Leon4 Debug Support Unit"},
- {GAISLER_PWM, "PWM", "PWM generator"},
- {GAISLER_L2CACHE, "L2CACHE", "L2-Cache Controller"},
- {GAISLER_SDCTRL64, "SDCTRL64", "64-bit PC133 SDRAM Controller"},
- {GAISLER_GR1553B, "GR1553B", "MIL-STD-1553B Interface"},
- {GAISLER_1553TST, "1553TST", "MIL-STD-1553B Test Device"},
- {GAISLER_GRIOMMU, "GRIOMMU", "I/O Memory Management Unit"},
- {GAISLER_FTAHBRAM, "FTAHBRAM", "Generic FT AHB SRAM module"},
- {GAISLER_FTSRCTRL, "FTSRCTRL", "Simple FT SRAM Controller"},
- {GAISLER_AHBSTAT, "AHBSTAT", "AHB Status Register"},
- {GAISLER_LEON3FT, "LEON3FT", "Leon3-FT SPARC V8 Processor"},
- {GAISLER_FTMCTRL, "FTMCTRL", "Memory controller with EDAC"},
- {GAISLER_FTSDCTRL, "FTSDCTRL", "FT PC133 SDRAM Controller"},
- {GAISLER_FTSRCTRL8, "FTSRCTRL8", "FT 8-bit SRAM/16-bit IO Ctrl"},
- {GAISLER_MEMSCRUB, "MEMSCRUB", "AHB Memory Scrubber"},
- {GAISLER_FTSDCTRL64, "FTSDCTRL64", "64-bit FT SDRAM Controller"},
- {GAISLER_APBPS2, "APBPS2", "PS2 interface"},
- {GAISLER_VGACTRL, "VGACTRL", "VGA controller"},
- {GAISLER_LOGAN, "LOGAN", "On chip Logic Analyzer"},
- {GAISLER_SVGACTRL, "SVGACTRL", "SVGA frame buffer"},
- {GAISLER_T1AHB, "T1AHB", "Niagara T1 PCX/AHB bridge"},
- {GAISLER_MP7WRAP, "MP7WRAP", "CoreMP7 wrapper"},
- {GAISLER_GRSYSMON, "GRSYSMON", "AMBA wrapper for System Monitor"},
- {GAISLER_GRACECTRL, "GRACECTRL", "System ACE I/F Controller"},
- {GAISLER_ATAHBSLV, "ATAHBSLV", "AMBA Test Framework AHB Slave"},
- {GAISLER_ATAHBMST, "ATAHBMST", "AMBA Test Framework AHB Master"},
- {GAISLER_ATAPBSLV, "ATAPBSLV", "AMBA Test Framework APB Slave"},
- {GAISLER_B1553BC, "B1553BC", "AMBA Wrapper for Core1553BBC"},
- {GAISLER_B1553RT, "B1553RT", "AMBA Wrapper for Core1553BRT"},
- {GAISLER_B1553BRM, "B1553BRM", "AMBA Wrapper for Core1553BRM"},
- {GAISLER_AES, "AES", "Advanced Encryption Standard"},
- {GAISLER_ECC, "ECC", "Elliptic Curve Cryptography"},
- {GAISLER_PCIF, "PCIF", "AMBA Wrapper for CorePCIF"},
- {GAISLER_CLKMOD, "CLKMOD", "CPU Clock Switching Ctrl module"},
- {GAISLER_HAPSTRAK, "HAPSTRAK", "HAPS HapsTrak I/O Port"},
- {GAISLER_TEST_1X2, "TEST_1X2", "HAPS TEST_1x2 interface"},
- {GAISLER_WILD2AHB, "WILD2AHB", "WildCard CardBus interface"},
- {GAISLER_BIO1, "BIO1", "Basic I/O board BIO1"},
- {GAISLER_AESDMA, "AESDMA", "AES 256 DMA"},
- {GAISLER_SATCAN, "SATCAN", "SatCAN controller"},
- {GAISLER_CANMUX, "CANMUX", "CAN Bus multiplexer"},
- {GAISLER_GRTMRX, "GRTMRX", "CCSDS Telemetry Receiver"},
- {GAISLER_GRTCTX, "GRTCTX", "CCSDS Telecommand Transmitter"},
- {GAISLER_GRTMDESC, "GRTMDESC", "CCSDS Telemetry Descriptor"},
- {GAISLER_GRTMVC, "GRTMVC", "CCSDS Telemetry VC Generator"},
- {GAISLER_GEFFE, "GEFFE", "Geffe Generator"},
- {GAISLER_GPREG, "GPREG", "General Purpose Register"},
- {GAISLER_GRTMPAHB, "GRTMPAHB", "CCSDS Telemetry VC AHB Input"},
- {GAISLER_SPWCUC, "SPWCUC", "CCSDS CUC / SpaceWire I/F"},
- {GAISLER_SPW2_DMA, "SPW2_DMA", "GRSPW Router DMA interface"},
- {GAISLER_SPWROUTER, "SPWROUTER", "GRSPW Router"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor PENDER devices */
-static ambapp_device_name PENDER_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor ESA devices */
-static ambapp_device_name ESA_devices[] = {
- {ESA_LEON2, "LEON2", "Leon2 SPARC V8 Processor"},
- {ESA_LEON2APB, "LEON2APB", "Leon2 Peripheral Bus"},
- {ESA_IRQ, "IRQ", "Leon2 Interrupt Controller"},
- {ESA_TIMER, "TIMER", "Leon2 Timer"},
- {ESA_UART, "UART", "Leon2 UART"},
- {ESA_CFG, "CFG", "Leon2 Configuration Register"},
- {ESA_IO, "IO", "Leon2 Input/Output"},
- {ESA_MCTRL, "MCTRL", "Leon2 Memory Controller"},
- {ESA_PCIARB, "PCIARB", "PCI Arbiter"},
- {ESA_HURRICANE, "HURRICANE", "HurriCANe/HurryAMBA CAN Ctrl"},
- {ESA_SPW_RMAP, "SPW_RMAP", "UoD/Saab SpaceWire/RMAP link"},
- {ESA_AHBUART, "AHBUART", "Leon2 AHB Debug UART"},
- {ESA_SPWA, "SPWA", "ESA/ASTRIUM SpaceWire link"},
- {ESA_BOSCHCAN, "BOSCHCAN", "SSC/BOSCH CAN Ctrl"},
- {ESA_IRQ2, "IRQ2", "Leon2 Secondary Irq Controller"},
- {ESA_AHBSTAT, "AHBSTAT", "Leon2 AHB Status Register"},
- {ESA_WPROT, "WPROT", "Leon2 Write Protection"},
- {ESA_WPROT2, "WPROT2", "Leon2 Extended Write Protection"},
- {ESA_PDEC3AMBA, "PDEC3AMBA", "ESA CCSDS PDEC3AMBA TC Decoder"},
- {ESA_PTME3AMBA, "PTME3AMBA", "ESA CCSDS PTME3AMBA TM Encoder"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor ASTRIUM devices */
-static ambapp_device_name ASTRIUM_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor OPENCHIP devices */
-static ambapp_device_name OPENCHIP_devices[] = {
- {OPENCHIP_APBGPIO, "APBGPIO", "APB General Purpose IO"},
- {OPENCHIP_APBI2C, "APBI2C", "APB I2C Interface"},
- {OPENCHIP_APBSPI, "APBSPI", "APB SPI Interface"},
- {OPENCHIP_APBCHARLCD, "APBCHARLCD", "APB Character LCD"},
- {OPENCHIP_APBPWM, "APBPWM", "APB PWM"},
- {OPENCHIP_APBPS2, "APBPS2", "APB PS/2 Interface"},
- {OPENCHIP_APBMMCSD, "APBMMCSD", "APB MMC/SD Card Interface"},
- {OPENCHIP_APBNAND, "APBNAND", "APB NAND(SmartMedia) Interface"},
- {OPENCHIP_APBLPC, "APBLPC", "APB LPC Interface"},
- {OPENCHIP_APBCF, "APBCF", "APB CompactFlash (IDE)"},
- {OPENCHIP_APBSYSACE, "APBSYSACE", "APB SystemACE Interface"},
- {OPENCHIP_APB1WIRE, "APB1WIRE", "APB 1-Wire Interface"},
- {OPENCHIP_APBJTAG, "APBJTAG", "APB JTAG TAP Master"},
- {OPENCHIP_APBSUI, "APBSUI", "APB Simple User Interface"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor OPENCORES devices */
-static ambapp_device_name OPENCORES_devices[] = {
- {OPENCORES_PCIBR, "PCIBR", "PCI Bridge"},
- {OPENCORES_ETHMAC, "ETHMAC", "Ethernet MAC"},
- {0, NULL}
-};
-
-
-/** Vendor CONTRIB devices */
-static ambapp_device_name CONTRIB_devices[] = {
- {CONTRIB_CORE1, "CORE1", "Contributed core 1"},
- {CONTRIB_CORE2, "CORE2", "Contributed core 2"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor EONIC devices */
-static ambapp_device_name EONIC_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor RADIONOR devices */
-static ambapp_device_name RADIONOR_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor GLEICHMANN devices */
-static ambapp_device_name GLEICHMANN_devices[] = {
- {GLEICHMANN_CUSTOM, "CUSTOM", "Custom device"},
- {GLEICHMANN_GEOLCD01, "GEOLCD01", "GEOLCD01 graphics system"},
- {GLEICHMANN_DAC, "DAC", "Sigma delta DAC"},
- {GLEICHMANN_HPI, "HPI", "AHB-to-HPI bridge"},
- {GLEICHMANN_SPI, "SPI", "SPI master"},
- {GLEICHMANN_HIFC, "HIFC", "Human interface controller"},
- {GLEICHMANN_ADCDAC, "ADCDAC", "Sigma delta ADC/DAC"},
- {GLEICHMANN_SPIOC, "SPIOC", ""},
- {GLEICHMANN_AC97, "AC97", ""},
- {0, NULL, NULL}
-};
-
-
-/** Vendor MENTA devices */
-static ambapp_device_name MENTA_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor SUN devices */
-static ambapp_device_name SUN_devices[] = {
- {SUN_T1, "T1", "Niagara T1 SPARC V9 Processor"},
- {SUN_S1, "S1", "Niagara S1 SPARC V9 Processor"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor MOVIDIA devices */
-static ambapp_device_name MOVIDIA_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor ORBITA devices */
-static ambapp_device_name ORBITA_devices[] = {
- {ORBITA_1553B, "1553B", "MIL-STD-1553B Controller"},
- {ORBITA_429, "429", "429 Interface"},
- {ORBITA_SPI, "SPI", "SPI Interface"},
- {ORBITA_I2C, "I2C", "I2C Interface"},
- {ORBITA_SMARTCARD, "SMARTCARD", "Smart Card Reader"},
- {ORBITA_SDCARD, "SDCARD", "SD Card Reader"},
- {ORBITA_UART16550, "UART16550", "16550 UART"},
- {ORBITA_CRYPTO, "CRYPTO", "Crypto Engine"},
- {ORBITA_SYSIF, "SYSIF", "System Interface"},
- {ORBITA_PIO, "PIO", "Programmable IO module"},
- {ORBITA_RTC, "RTC", "Real-Time Clock"},
- {ORBITA_COLORLCD, "COLORLCD", "Color LCD Controller"},
- {ORBITA_PCI, "PCI", "PCI Module"},
- {ORBITA_DSP, "DSP", "DPS Co-Processor"},
- {ORBITA_USBHOST, "USBHOST", "USB Host"},
- {ORBITA_USBDEV, "USBDEV", "USB Device"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor SYNOPSYS devices */
-static ambapp_device_name SYNOPSYS_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor NASA devices */
-static ambapp_device_name NASA_devices[] = {
- {NASA_EP32, "EP32", "EP32 Forth processor"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor CAL devices */
-static ambapp_device_name CAL_devices[] = {
- {CAL_DDRCTRL, "DDRCTRL", ""},
- {0, NULL, NULL}
-};
-
-
-/** Vendor EMBEDDIT devices */
-static ambapp_device_name EMBEDDIT_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor CETON devices */
-static ambapp_device_name CETON_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor S3 devices */
-static ambapp_device_name S3_devices[] = {
- {0, NULL, NULL}
-};
-
-
-/** Vendor ACTEL devices */
-static ambapp_device_name ACTEL_devices[] = {
- {ACTEL_COREMP7, "COREMP7", "CoreMP7 Processor"},
- {0, NULL, NULL}
-};
-
-
-/** Vendor APPLECORE devices */
-static ambapp_device_name APPLECORE_devices[] = {
- {APPLECORE_UTLEON3, "UTLEON3", "AppleCore uT-LEON3 Processor"},
- {APPLECORE_UTLEON3DSU, "UTLEON3DSU", "AppleCore uT-LEON3 DSU"},
- {0, NULL, NULL}
-};
-
-
-/** Vendors and their devices */
-static ambapp_vendor_devnames vendors[] = {
- {VENDOR_GAISLER, "GAISLER", "Gaisler Research", GAISLER_devices},
- {VENDOR_PENDER, "PENDER", "", PENDER_devices},
- {VENDOR_ESA, "ESA", "European Space Agency", ESA_devices},
- {VENDOR_ASTRIUM, "ASTRIUM", "", ASTRIUM_devices},
- {VENDOR_OPENCHIP, "OPENCHIP", "OpenChip", OPENCHIP_devices},
- {VENDOR_OPENCORES, "OPENCORES", "OpenCores", OPENCORES_devices},
- {VENDOR_CONTRIB, "CONTRIB", "Various contributions", CONTRIB_devices},
- {VENDOR_EONIC, "EONIC", "Eonic BV", EONIC_devices},
- {VENDOR_RADIONOR, "RADIONOR", "Radionor Communications", RADIONOR_devices},
- {VENDOR_GLEICHMANN, "GLEICHMANN", "Gleichmann Electronics", GLEICHMANN_devices},
- {VENDOR_MENTA, "MENTA", "Menta", MENTA_devices},
- {VENDOR_SUN, "SUN", "Sun Microsystems", SUN_devices},
- {VENDOR_MOVIDIA, "MOVIDIA", "", MOVIDIA_devices},
- {VENDOR_ORBITA, "ORBITA", "Orbita", ORBITA_devices},
- {VENDOR_SYNOPSYS, "SYNOPSYS", "Synopsys Inc.", SYNOPSYS_devices},
- {VENDOR_NASA, "NASA", "NASA", NASA_devices},
- {VENDOR_S3, "S3", "S3 Group", S3_devices},
- {VENDOR_CAL, "CAL", "", CAL_devices},
- {VENDOR_EMBEDDIT, "EMBEDDIT", "Embedd.it", EMBEDDIT_devices},
- {VENDOR_CETON, "CETON", "Ceton Corporation", CETON_devices},
- {VENDOR_ACTEL, "ACTEL", "Actel Corporation", ACTEL_devices},
- {VENDOR_APPLECORE, "APPLECORE", "AppleCore", APPLECORE_devices},
- {0, NULL, NULL, NULL}
-};
-
-static ambapp_device_name *ambapp_get_dev(ambapp_device_name *devs, int id)
-{
- if (!devs)
- return NULL;
-
- while (devs->device_id > 0) {
- if (devs->device_id == id)
- return devs;
- devs++;
- }
- return NULL;
-}
-
-char *ambapp_device_id2str(int vendor, int id)
-{
- ambapp_vendor_devnames *ven = &vendors[0];
- ambapp_device_name *dev;
-
- while (ven->vendor_id > 0) {
- if (ven->vendor_id == vendor) {
- dev = ambapp_get_dev(ven->devices, id);
- if (!dev)
- return NULL;
- return dev->name;
- }
- ven++;
- }
- return NULL;
-}
-
-char *ambapp_device_id2desc(int vendor, int id)
-{
- ambapp_vendor_devnames *ven = &vendors[0];
- ambapp_device_name *dev;
-
- while (ven->vendor_id > 0) {
- if (ven->vendor_id == vendor) {
- dev = ambapp_get_dev(ven->devices, id);
- if (!dev)
- return NULL;
- return dev->desc;
- }
- ven++;
- }
- return NULL;
-}
-
-char *ambapp_vendor_id2str(int vendor)
-{
- ambapp_vendor_devnames *ven = &vendors[0];
-
- while (ven->vendor_id > 0) {
- if (ven->vendor_id == vendor) {
- return ven->name;
- }
- ven++;
- }
- return NULL;
-}
-
-static char *unknown = "unknown";
-
-char *ambapp_type_names[4] = {
- /* 0 */ "UNUSED",
- /* 1 */ "apb",
- /* 2 */ "ahbmem",
- /* 3 */ "ahbio"
-};
-
-/* Print one APB device */
-void ambapp_print_apb(ambapp_apbdev *dev, int index)
-{
- char *dev_str, *ven_str;
- unsigned int freq;
-
- ven_str = ambapp_vendor_id2str(dev->vendor);
- if (!ven_str) {
- ven_str = unknown;
- dev_str = unknown;
- } else {
- dev_str = ambapp_device_id2str(dev->vendor, dev->device);
- if (!dev_str)
- dev_str = unknown;
- }
-
- /* Get Frequency of Core */
- freq = ambapp_bus_freq(&ambapp_plb, dev->ahb_bus_index);
-
- printf("0x%02x:0x%02x:0x%02x: %s %s (%dkHz)\n"
- " apb: 0x%08x - 0x%08x\n"
- " irq: %-2d (ver: %-2d)\n",
- index, dev->vendor, dev->device, ven_str, dev_str, freq / 1000,
- dev->address, dev->address + (dev->mask-1),
- dev->irq, dev->ver);
-}
-
-void ambapp_print_ahb(ambapp_ahbdev *dev, int index)
-{
- char *dev_str, *ven_str, *type_str;
- int i;
- unsigned int freq;
-
- ven_str = ambapp_vendor_id2str(dev->vendor);
- if (!ven_str) {
- ven_str = unknown;
- dev_str = unknown;
- } else {
- dev_str = ambapp_device_id2str(dev->vendor, dev->device);
- if (!dev_str)
- dev_str = unknown;
- }
-
- /* Get Frequency of Core */
- freq = ambapp_bus_freq(&ambapp_plb, dev->ahb_bus_index);
-
- printf("0x%02x:0x%02x:0x%02x: %s %s (%dkHz)\n",
- index, dev->vendor, dev->device, ven_str, dev_str, freq / 1000);
-
- for (i = 0; i < 4; i++) {
- if (dev->type[i] == 0)
- continue;
- type_str = ambapp_type_names[dev->type[i]];
- printf(" %-7s: 0x%08x - 0x%08x\n", type_str, dev->address[i],
- dev->address[i] + (dev->mask[i]-1));
- }
-
- printf(" irq: %-2d (ver: %d)\n", dev->irq, dev->ver);
-}
-
-int do_ambapp_print(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int index;
- ambapp_apbdev apbdev;
- ambapp_ahbdev ahbdev;
-
- /* Print AHB Masters */
- puts("\n--------- AHB Masters ---------\n");
- index = 0;
- while (ambapp_ahbmst_find(&ambapp_plb, 0, 0, index, &ahbdev) == 1) {
- /* Found a AHB Master Device */
- ambapp_print_ahb(&ahbdev, index);
- index++;
- }
-
- /* Print AHB Slaves */
- puts("\n--------- AHB Slaves ---------\n");
- index = 0;
- while (ambapp_ahbslv_find(&ambapp_plb, 0, 0, index, &ahbdev) == 1) {
- /* Found a AHB Slave Device */
- ambapp_print_ahb(&ahbdev, index);
- index++;
- }
-
- /* Print APB Slaves */
- puts("\n--------- APB Slaves ---------\n");
- index = 0;
- while (ambapp_apb_find(&ambapp_plb, 0, 0, index, &apbdev) == 1) {
- /* Found a APB Slave Device */
- ambapp_print_apb(&apbdev, index);
- index++;
- }
-
- puts("\n");
- return 0;
-}
-
-int ambapp_init_reloc(void)
-{
- ambapp_vendor_devnames *vend = vendors;
- ambapp_device_name *dev;
-
- while (vend->vendor_id && vend->name) {
- vend->name = (char *)((unsigned int)vend->name + gd->reloc_off);
- vend->desc = (char *)((unsigned int)vend->desc + gd->reloc_off);
- vend->devices = (ambapp_device_name *)
- ((unsigned int)vend->devices + gd->reloc_off);
- dev = vend->devices;
- vend++;
- if (!dev)
- continue;
- while (dev->device_id && dev->name) {
- dev->name =
- (char *)((unsigned int)dev->name + gd->reloc_off);
- dev->desc =
- (char *)((unsigned int)dev->desc + gd->reloc_off);
- dev++;
- }
- }
- return 0;
-}
-
-U_BOOT_CMD(
- ambapp, 1, 1, do_ambapp_print,
- "list AMBA Plug&Play information",
- "ambapp\n"
- " - lists AMBA (AHB & APB) Plug&Play devices present on the system"
-);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 20a92320bde1..4a2e5e802213 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -152,8 +152,6 @@ static inline void print_baudrate(void)
{
#if defined(CONFIG_PPC)
printf("baudrate = %6u bps\n", gd->baudrate);
-#elif defined(CONFIG_SPARC)
- printf("baudrate = %6u bps\n", gd->baudrate);
#else
printf("baudrate = %u bps\n", gd->baudrate);
#endif
@@ -277,36 +275,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
-#elif defined(CONFIG_SPARC)
-
-int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- bd_t *bd = gd->bd;
-
-#ifdef DEBUG
- print_num("bd address ", (ulong) bd);
-#endif
- print_num("memstart ", bd->bi_memstart);
- print_lnum("memsize ", bd->bi_memsize);
- print_num("flashstart ", bd->bi_flashstart);
- print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
- print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
- printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
- CONFIG_SYS_MONITOR_LEN);
- printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
- CONFIG_SYS_MALLOC_LEN);
- printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
- CONFIG_SYS_STACK_SIZE);
- printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
- CONFIG_SYS_PROM_SIZE);
- printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
- GENERATED_GBL_DATA_SIZE);
-
- print_eth_ip_addr();
- print_baudrate();
- return 0;
-}
-
#elif defined(CONFIG_M68K)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/common/Kconfig b/common/Kconfig
index 0beeb0eff0bb..1e0c6273419f 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -387,7 +387,7 @@ config DISPLAY_CPUINFO
config DISPLAY_BOARDINFO
bool "Display information about the board during start up"
- default y if ARM || M68K || MIPS || PPC || SPARC || XTENSA
+ default y if ARM || M68K || MIPS || PPC || XTENSA
help
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
diff --git a/common/board_f.c b/common/board_f.c
index 1be0211d873f..063b86112aca 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -380,20 +380,6 @@ static int setup_dest_addr(void)
return 0;
}
-#if defined(CONFIG_SPARC)
-static int reserve_prom(void)
-{
- /* defined in arch/sparc/cpu/leon?/prom.c */
- extern void *__prom_start_reloc;
- int size = 8192; /* page table = 2k, prom = 6k */
- gd->relocaddr -= size;
- __prom_start_reloc = map_sysmem(gd->relocaddr + 2048, size - 2048);
- debug("Reserving %dk for PROM and page table at %08lx\n", size,
- gd->relocaddr);
- return 0;
-}
-#endif
-
#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
static int reserve_logbuffer(void)
{
@@ -880,8 +866,7 @@ static const init_fnc_t init_sequence_f[] = {
init_timebase,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
- defined(CONFIG_NDS32) || defined(CONFIG_SH) || \
- defined(CONFIG_SPARC)
+ defined(CONFIG_NDS32) || defined(CONFIG_SH)
timer_init, /* initialize timer */
#endif
#if defined(CONFIG_BOARD_POSTCLK_INIT)
@@ -973,9 +958,6 @@ static const init_fnc_t init_sequence_f[] = {
/* Blackfin u-boot monitor should be on top of the ram */
reserve_uboot,
#endif
-#if defined(CONFIG_SPARC)
- reserve_prom,
-#endif
#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
reserve_logbuffer,
#endif
diff --git a/common/board_r.c b/common/board_r.c
index 5c9e6987b9e1..ce8bf893d287 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -49,9 +49,6 @@
#include <timer.h>
#include <trace.h>
#include <watchdog.h>
-#ifdef CONFIG_CMD_AMBAPP
-#include <ambapp.h>
-#endif
#ifdef CONFIG_ADDR_MAP
#include <asm/mmu.h>
#endif
@@ -69,10 +66,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPARC)
-extern int prom_init(void);
-#endif
-
ulong monitor_flash_len;
__weak int board_flash_wp_on(void)
@@ -597,18 +590,6 @@ static int initr_status_led(void)
}
#endif
-#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
-extern int do_ambapp_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-static int initr_ambapp_print(void)
-{
- puts("AMBA:\n");
- do_ambapp_print(NULL, 0, 0, NULL);
-
- return 0;
-}
-#endif
-
#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
static int initr_scsi(void)
{
@@ -822,8 +803,7 @@ static init_fnc_t init_sequence_r[] = {
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86) || \
- defined(CONFIG_SPARC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
@@ -894,12 +874,6 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
-#if defined(CONFIG_CMD_AMBAPP)
- ambapp_init_reloc,
-#if defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
- initr_ambapp_print,
-#endif
-#endif
#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
INIT_FUNC_WATCHDOG_RESET
initr_scsi,
@@ -939,9 +913,6 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_PS2KBD
initr_kbd,
#endif
-#if defined(CONFIG_SPARC)
- prom_init,
-#endif
run_main_loop,
};
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
deleted file mode 100644
index 6dc0d322dce3..000000000000
--- a/configs/gr_cpci_ax2000_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-CPCI-AX2000"
-CONFIG_TARGET_GR_CPCI_AX2000=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
deleted file mode 100644
index 6b635e781014..000000000000
--- a/configs/gr_ep2s60_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 EP2S60"
-CONFIG_TARGET_GR_EP2S60=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
deleted file mode 100644
index 9f1d6a812390..000000000000
--- a/configs/gr_xc3s_1500_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-XC3S-1500"
-CONFIG_TARGET_GR_XC3S_1500=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
deleted file mode 100644
index 6cbbbe41febe..000000000000
--- a/configs/grsim_defconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler GRSIM"
-CONFIG_TARGET_GRSIM=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP=y
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_APBUART=y
-CONFIG_DEBUG_UART_BASE=0x80000100
-CONFIG_DEBUG_UART_CLOCK=40000000
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
deleted file mode 100644
index 75336a10fc0c..000000000000
--- a/configs/grsim_leon2_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-CONFIG_SPARC=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_IDENT_STRING=" Gaisler GRSIM LEON2"
-CONFIG_TARGET_GRSIM_LEON2=y
-CONFIG_BOOTDELAY=5
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_MEMORY is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
diff --git a/disk/Kconfig b/disk/Kconfig
index 16ff52da3eb4..8351b026262e 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -22,7 +22,6 @@ config PARTITIONS
config MAC_PARTITION
bool "Enable Apple's MacOS partition table"
depends on PARTITIONS
- default y if SPARC
help
Say Y here if you would like to use device under U-Boot which
were partitioned on a Macintosh.
@@ -36,7 +35,7 @@ config DOS_PARTITION
bool "Enable MS Dos partition table"
depends on PARTITIONS
default y if DISTRO_DEFAULTS
- default y if x86 || SPARC || CMD_FAT || USB_STORAGE
+ default y if x86 || CMD_FAT || USB_STORAGE
help
traditional on the Intel architecture, USB sticks, etc.
@@ -49,7 +48,7 @@ config ISO_PARTITION
bool "Enable ISO partition table"
depends on PARTITIONS
default y if DISTRO_DEFAULTS
- default y if SPARC || MIPS || TEGRA
+ default y if MIPS || TEGRA
config SPL_ISO_PARTITION
bool "Enable ISO partition table for SPL"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2493a48b88d4..ac7e07bfdf58 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
-obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
deleted file mode 100644
index aa5d7114a5b8..000000000000
--- a/drivers/net/greth.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
- *
- * Driver use polling mode (no Interrupt)
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <net.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <asm/processor.h>
-#include <ambapp.h>
-#include <asm/leon.h>
-
-#include <grlib/greth.h>
-
-/* Default to 3s timeout on autonegotiation */
-#ifndef GRETH_PHY_TIMEOUT_MS
-#define GRETH_PHY_TIMEOUT_MS 3000
-#endif
-
-/* Default to PHY adrress 0 not not specified */
-#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
-#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
-#else
-#define GRETH_PHY_ADR_DEFAULT 0
-#endif
-
-/* Let board select which GRETH to use as network interface, set
- * this to zero if only one GRETH is available.
- */
-#ifndef CONFIG_SYS_GRLIB_GRETH_INDEX
-#define CONFIG_SYS_GRLIB_GRETH_INDEX 0
-#endif
-
-/* ByPass Cache when reading regs */
-#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
-/* Write-through cache ==> no bypassing needed on writes */
-#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
-#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
-#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
-
-#define GRETH_RXBD_CNT 4
-#define GRETH_TXBD_CNT 1
-
-#define GRETH_RXBUF_SIZE 1540
-#define GRETH_BUF_ALIGN 4
-#define GRETH_RXBUF_EFF_SIZE \
- ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
-
-typedef struct {
- greth_regs *regs;
- int irq;
- struct eth_device *dev;
-
- /* Hardware info */
- unsigned char phyaddr;
- int gbit_mac;
-
- /* Current operating Mode */
- int gb; /* GigaBit */
- int fd; /* Full Duplex */
- int sp; /* 10/100Mbps speed (1=100,0=10) */
- int auto_neg; /* Auto negotiate done */
-
- unsigned char hwaddr[6]; /* MAC Address */
-
- /* Descriptors */
- greth_bd *rxbd_base, *rxbd_max;
- greth_bd *txbd_base, *txbd_max;
-
- greth_bd *rxbd_curr;
-
- /* rx buffers in rx descriptors */
- void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
-
- /* unused for gbit_mac, temp buffer for sending packets with unligned
- * start.
- * Pointer to packet allocated with malloc.
- */
- void *txbuf;
-
- struct {
- /* rx status */
- unsigned int rx_packets,
- rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
-
- /* tx stats */
- unsigned int tx_packets,
- tx_latecol_errors,
- tx_underrun_errors, tx_limit_errors, tx_errors;
- } stats;
-} greth_priv;
-
-/* Read MII register 'addr' from core 'regs' */
-static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
-{
- while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
- }
-
- GRETH_REGSAVE(®s->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
-
- while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
- }
-
- if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) {
- return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF;
- } else {
- return -1;
- }
-}
-
-static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
-{
- while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
- }
-
- GRETH_REGSAVE(®s->mdio,
- ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
- ((regaddr & 0x1F) << 6) | 1);
-
- while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
- }
-
-}
-
-/* init/start hardware and allocate descriptor buffers for rx side
- *
- */
-int greth_init(struct eth_device *dev, bd_t * bis)
-{
- int i;
-
- greth_priv *greth = dev->priv;
- greth_regs *regs = greth->regs;
-
- debug("greth_init\n");
-
- /* Reset core */
- GRETH_REGSAVE(®s->control, (GRETH_RESET | (greth->gb << 8) |
- (greth->sp << 7) | (greth->fd << 4)));
-
- /* Wait for Reset to complete */
- while ( GRETH_REGLOAD(®s->control) & GRETH_RESET) ;
-
- GRETH_REGSAVE(®s->control,
- ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
-
- if (!greth->rxbd_base) {
-
- /* allocate descriptors */
- greth->rxbd_base = (greth_bd *)
- memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
- greth->txbd_base = (greth_bd *)
- memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
-
- /* allocate buffers to all descriptors */
- greth->rxbuf_base =
- malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
- }
-
- /* initate rx decriptors */
- for (i = 0; i < GRETH_RXBD_CNT; i++) {
- greth->rxbd_base[i].addr = (unsigned int)
- greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
- /* enable desciptor & set wrap bit if last descriptor */
- if (i >= (GRETH_RXBD_CNT - 1)) {
- greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
- } else {
- greth->rxbd_base[i].stat = GRETH_BD_EN;
- }
- }
-
- /* initiate indexes */
- greth->rxbd_curr = greth->rxbd_base;
- greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
- greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
- /*
- * greth->txbd_base->addr = 0;
- * greth->txbd_base->stat = GRETH_BD_WR;
- */
-
- /* initate tx decriptors */
- for (i = 0; i < GRETH_TXBD_CNT; i++) {
- greth->txbd_base[i].addr = 0;
- /* enable desciptor & set wrap bit if last descriptor */
- if (i >= (GRETH_TXBD_CNT - 1)) {
- greth->txbd_base[i].stat = GRETH_BD_WR;
- } else {
- greth->txbd_base[i].stat = 0;
- }
- }
-
- /**** SET HARDWARE REGS ****/
-
- /* Set pointer to tx/rx descriptor areas */
- GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
- GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
-
- /* Enable Transmitter, GRETH will now scan descriptors for packets
- * to transmitt */
- debug("greth_init: enabling receiver\n");
- GRETH_REGORIN(®s->control, GRETH_RXEN);
-
- return 0;
-}
-
-/* Initiate PHY to a relevant speed
- * return:
- * - 0 = success
- * - 1 = timeout/fail
- */
-int greth_init_phy(greth_priv * dev, bd_t * bis)
-{
- greth_regs *regs = dev->regs;
- int tmp, tmp1, tmp2, i;
- unsigned int start, timeout;
- int phyaddr = GRETH_PHY_ADR_DEFAULT;
-
-#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
- /* If BSP doesn't provide a hardcoded PHY address the driver will
- * try to autodetect PHY address by stopping the search on the first
- * PHY address which has REG0 implemented.
- */
- for (i=0; i<32; i++) {
- tmp = read_mii(i, 0, regs);
- if ( (tmp != 0) && (tmp != 0xffff) ) {
- phyaddr = i;
- break;
- }
- }
-#endif
-
- /* Save PHY Address */
- dev->phyaddr = phyaddr;
-
- debug("GRETH PHY ADDRESS: %d\n", phyaddr);
-
- /* X msecs to ticks */
- timeout = GRETH_PHY_TIMEOUT_MS * 1000;
-
- /* Get system timer0 current value
- * Total timeout is 5s
- */
- start = get_timer(0);
-
- /* get phy control register default values */
-
- while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
- if (get_timer(start) > timeout) {
- debug("greth_init_phy: PHY read 1 failed\n");
- return 1; /* Fail */
- }
- }
-
- /* reset PHY and wait for completion */
- write_mii(phyaddr, 0, 0x8000 | tmp, regs);
-
- while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
- if (get_timer(start) > timeout) {
- debug("greth_init_phy: PHY read 2 failed\n");
- return 1; /* Fail */
- }
- }
-
- /* Check if PHY is autoneg capable and then determine operating
- * mode, otherwise force it to 10 Mbit halfduplex
- */
- dev->gb = 0;
- dev->fd = 0;
- dev->sp = 0;
- dev->auto_neg = 0;
- if (!((tmp >> 12) & 1)) {
- write_mii(phyaddr, 0, 0, regs);
- } else {
- /* wait for auto negotiation to complete and then check operating mode */
- dev->auto_neg = 1;
- i = 0;
- while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
- if (get_timer(start) > timeout) {
- printf("Auto negotiation timed out. "
- "Selecting default config\n");
- tmp = read_mii(phyaddr, 0, regs);
- dev->gb = ((tmp >> 6) & 1)
- && !((tmp >> 13) & 1);
- dev->sp = !((tmp >> 6) & 1)
- && ((tmp >> 13) & 1);
- dev->fd = (tmp >> 8) & 1;
- goto auto_neg_done;
- }
- }
- if ((tmp >> 8) & 1) {
- tmp1 = read_mii(phyaddr, 9, regs);
- tmp2 = read_mii(phyaddr, 10, regs);
- if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
- (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
- dev->gb = 1;
- dev->fd = 1;
- }
- if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
- (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
- dev->gb = 1;
- dev->fd = 0;
- }
- }
- if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
- tmp1 = read_mii(phyaddr, 4, regs);
- tmp2 = read_mii(phyaddr, 5, regs);
- if ((tmp1 & GRETH_MII_100TXFD) &&
- (tmp2 & GRETH_MII_100TXFD)) {
- dev->sp = 1;
- dev->fd = 1;
- }
- if ((tmp1 & GRETH_MII_100TXHD) &&
- (tmp2 & GRETH_MII_100TXHD)) {
- dev->sp = 1;
- dev->fd = 0;
- }
- if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
- dev->fd = 1;
- }
- if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
- dev->gb = 0;
- dev->fd = 0;
- write_mii(phyaddr, 0, dev->sp << 13, regs);
- }
- }
-
- }
- auto_neg_done:
- debug("%s GRETH Ethermac@[0x%x] irq %d. Running \
- %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
- /* Read out PHY info if extended registers are available */
- if (tmp & 1) {
- tmp1 = read_mii(phyaddr, 2, regs);
- tmp2 = read_mii(phyaddr, 3, regs);
- tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
- tmp = tmp2 & 0xF;
-
- tmp2 = (tmp2 >> 4) & 0x3F;
- debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
- tmp2, tmp);
- } else {
- printf("PHY info not available\n");
- }
-
- /* set speed and duplex bits in control register */
- GRETH_REGORIN(®s->control,
- (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
-
- return 0;
-}
-
-void greth_halt(struct eth_device *dev)
-{
- greth_priv *greth;
- greth_regs *regs;
- int i;
-
- debug("greth_halt\n");
-
- if (!dev || !dev->priv)
- return;
-
- greth = dev->priv;
- regs = greth->regs;
-
- if (!regs)
- return;
-
- /* disable receiver/transmitter by clearing the enable bits */
- GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN));
-
- /* reset rx/tx descriptors */
- if (greth->rxbd_base) {
- for (i = 0; i < GRETH_RXBD_CNT; i++) {
- greth->rxbd_base[i].stat =
- (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
- }
- }
-
- if (greth->txbd_base) {
- for (i = 0; i < GRETH_TXBD_CNT; i++) {
- greth->txbd_base[i].stat =
- (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
- }
- }
-}
-
-int greth_send(struct eth_device *dev, void *eth_data, int data_length)
-{
- greth_priv *greth = dev->priv;
- greth_regs *regs = greth->regs;
- greth_bd *txbd;
- void *txbuf;
- unsigned int status;
-
- debug("greth_send\n");
-
- /* send data, wait for data to be sent, then return */
- if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
- && !greth->gbit_mac) {
- /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
- * and copy data to before giving it to GRETH.
- */
- if (!greth->txbuf) {
- greth->txbuf = malloc(GRETH_RXBUF_SIZE);
- }
-
- txbuf = greth->txbuf;
-
- /* copy data info buffer */
- memcpy((char *)txbuf, (char *)eth_data, data_length);
-
- /* keep buffer to next time */
- } else {
- txbuf = (void *)eth_data;
- }
- /* get descriptor to use, only 1 supported... hehe easy */
- txbd = greth->txbd_base;
-
- /* setup descriptor to wrap around to it self */
- txbd->addr = (unsigned int)txbuf;
- txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
-
- /* Remind Core which descriptor to use when sending */
- GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd);
-
- /* initate send by enabling transmitter */
- GRETH_REGORIN(®s->control, GRETH_TXEN);
-
- /* Wait for data to be sent */
- while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
- ;
- }
-
- /* was the packet transmitted succesfully? */
- if (status & GRETH_TXBD_ERR_AL) {
- greth->stats.tx_limit_errors++;
- }
-
- if (status & GRETH_TXBD_ERR_UE) {
- greth->stats.tx_underrun_errors++;
- }
-
- if (status & GRETH_TXBD_ERR_LC) {
- greth->stats.tx_latecol_errors++;
- }
-
- if (status &
- (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
- /* any error */
- greth->stats.tx_errors++;
- return -1;
- }
-
- /* bump tx packet counter */
- greth->stats.tx_packets++;
-
- /* return succefully */
- return 0;
-}
-
-int greth_recv(struct eth_device *dev)
-{
- greth_priv *greth = dev->priv;
- greth_regs *regs = greth->regs;
- greth_bd *rxbd;
- unsigned int status, len = 0, bad;
- char *d;
- int enable = 0;
- int i;
-
- /* Receive One packet only, but clear as many error packets as there are
- * available.
- */
- {
- /* current receive descriptor */
- rxbd = greth->rxbd_curr;
-
- /* get status of next received packet */
- status = GRETH_REGLOAD(&rxbd->stat);
-
- bad = 0;
-
- /* stop if no more packets received */
- if (status & GRETH_BD_EN) {
- goto done;
- }
-
- debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
- (unsigned int)rxbd, status, status & GRETH_BD_LEN);
-
- /* Check status for errors.
- */
- if (status & GRETH_RXBD_ERR_FT) {
- greth->stats.rx_length_errors++;
- bad = 1;
- }
- if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
- greth->stats.rx_frame_errors++;
- bad = 1;
- }
- if (status & GRETH_RXBD_ERR_CRC) {
- greth->stats.rx_crc_errors++;
- bad = 1;
- }
- if (bad) {
- greth->stats.rx_errors++;
- printf
- ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
- greth->stats.rx_length_errors,
- greth->stats.rx_frame_errors,
- greth->stats.rx_crc_errors, status,
- greth->stats.rx_packets);
- /* print all rx descriptors */
- for (i = 0; i < GRETH_RXBD_CNT; i++) {
- printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
- GRETH_REGLOAD(&greth->rxbd_base[i].stat),
- GRETH_REGLOAD(&greth->rxbd_base[i].addr));
- }
- } else {
- /* Process the incoming packet. */
- len = status & GRETH_BD_LEN;
- d = (char *)rxbd->addr;
-
- debug
- ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
- len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
- d[7]);
-
- /* flush all data cache to make sure we're not reading old packet data */
- sparc_dcache_flush_all();
-
- /* pass packet on to network subsystem */
- net_process_received_packet((void *)d, len);
-
- /* bump stats counters */
- greth->stats.rx_packets++;
-
- /* bad is now 0 ==> will stop loop */
- }
-
- /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
- rxbd->stat =
- GRETH_BD_EN |
- (((unsigned int)greth->rxbd_curr >=
- (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
- enable = 1;
-
- /* increase index */
- greth->rxbd_curr =
- ((unsigned int)greth->rxbd_curr >=
- (unsigned int)greth->rxbd_max) ? greth->
- rxbd_base : (greth->rxbd_curr + 1);
-
- }
-
- if (enable) {
- GRETH_REGORIN(®s->control, GRETH_RXEN);
- }
- done:
- /* return positive length of packet or 0 if non received */
- return len;
-}
-
-void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
-{
- /* save new MAC address */
- greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
- greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
- greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
- greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
- greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
- greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
- greth->regs->esa_msb = (mac[0] << 8) | mac[1];
- greth->regs->esa_lsb =
- (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
-
- debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-}
-
-int greth_initialize(bd_t * bis)
-{
- greth_priv *greth;
- ambapp_apbdev apbdev;
- struct eth_device *dev;
- int i;
- char *addr_str, *end;
- unsigned char addr[6];
-
- debug("Scanning for GRETH\n");
-
- /* Find Device & IRQ via AMBA Plug&Play information,
- * CONFIG_SYS_GRLIB_GRETH_INDEX select which GRETH if multiple
- * GRETHs in system.
- */
- if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_ETHMAC,
- CONFIG_SYS_GRLIB_GRETH_INDEX, &apbdev) != 1) {
- return -1; /* GRETH not found */
- }
-
- greth = (greth_priv *) malloc(sizeof(greth_priv));
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- memset(dev, 0, sizeof(struct eth_device));
- memset(greth, 0, sizeof(greth_priv));
-
- greth->regs = (greth_regs *) apbdev.address;
- greth->irq = apbdev.irq;
- debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
- dev->priv = (void *)greth;
- dev->iobase = (unsigned int)greth->regs;
- dev->init = greth_init;
- dev->halt = greth_halt;
- dev->send = greth_send;
- dev->recv = greth_recv;
- greth->dev = dev;
-
- /* Reset Core */
- GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
-
- /* Wait for core to finish reset cycle */
- while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
-
- /* Get the phy address which assumed to have been set
- correctly with the reset value in hardware */
- greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
-
- /* Check if mac is gigabit capable */
- greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
-
- /* Make descriptor string */
- if (greth->gbit_mac) {
- strcpy(dev->name, "GRETH_10/100/GB");
- } else {
- strcpy(dev->name, "GRETH_10/100");
- }
-
- /* initiate PHY, select speed/duplex depending on connected PHY */
- if (greth_init_phy(greth, bis)) {
- /* Failed to init PHY (timedout) */
- debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
- return -1;
- }
-
- /* Register Device to EtherNet subsystem */
- eth_register(dev);
-
- /* Get MAC address */
- if ((addr_str = getenv("ethaddr")) != NULL) {
- for (i = 0; i < 6; i++) {
- addr[i] =
- addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
- if (addr_str) {
- addr_str = (*end) ? end + 1 : end;
- }
- }
- } else {
- /* No ethaddr set */
- return -EINVAL;
- }
-
- /* set and remember MAC address */
- greth_set_hwaddr(greth, addr);
-
- debug("GRETH[%p]: Initialized successfully\n", greth->regs);
- return 0;
-}
diff --git a/drivers/net/greth.h b/drivers/net/greth.h
deleted file mode 100644
index 5299b2861c30..000000000000
--- a/drivers/net/greth.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define GRETH_FD 0x10
-#define GRETH_RESET 0x40
-#define GRETH_MII_BUSY 0x8
-#define GRETH_MII_NVALID 0x10
-
-/* MII registers */
-#define GRETH_MII_EXTADV_1000FD 0x00000200
-#define GRETH_MII_EXTADV_1000HD 0x00000100
-#define GRETH_MII_EXTPRT_1000FD 0x00000800
-#define GRETH_MII_EXTPRT_1000HD 0x00000400
-
-#define GRETH_MII_100T4 0x00000200
-#define GRETH_MII_100TXFD 0x00000100
-#define GRETH_MII_100TXHD 0x00000080
-#define GRETH_MII_10FD 0x00000040
-#define GRETH_MII_10HD 0x00000020
-
-#define GRETH_BD_EN 0x800
-#define GRETH_BD_WR 0x1000
-#define GRETH_BD_IE 0x2000
-#define GRETH_BD_LEN 0x7FF
-
-#define GRETH_TXEN 0x1
-#define GRETH_INT_TX 0x8
-#define GRETH_TXI 0x4
-#define GRETH_TXBD_STATUS 0x0001C000
-#define GRETH_TXBD_MORE 0x20000
-#define GRETH_TXBD_IPCS 0x40000
-#define GRETH_TXBD_TCPCS 0x80000
-#define GRETH_TXBD_UDPCS 0x100000
-#define GRETH_TXBD_ERR_LC 0x10000
-#define GRETH_TXBD_ERR_UE 0x4000
-#define GRETH_TXBD_ERR_AL 0x8000
-#define GRETH_TXBD_NUM 128
-#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
-#define GRETH_TX_BUF_SIZE 2048
-
-#define GRETH_INT_RX 0x4
-#define GRETH_RXEN 0x2
-#define GRETH_RXI 0x8
-#define GRETH_RXBD_STATUS 0xFFFFC000
-#define GRETH_RXBD_ERR_AE 0x4000
-#define GRETH_RXBD_ERR_FT 0x8000
-#define GRETH_RXBD_ERR_CRC 0x10000
-#define GRETH_RXBD_ERR_OE 0x20000
-#define GRETH_RXBD_ERR_LE 0x40000
-#define GRETH_RXBD_IP_DEC 0x80000
-#define GRETH_RXBD_IP_CSERR 0x100000
-#define GRETH_RXBD_UDP_DEC 0x200000
-#define GRETH_RXBD_UDP_CSERR 0x400000
-#define GRETH_RXBD_TCP_DEC 0x800000
-#define GRETH_RXBD_TCP_CSERR 0x1000000
-
-#define GRETH_RXBD_NUM 128
-#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
-#define GRETH_RX_BUF_SIZE 2048
-
-/* Ethernet configuration registers */
-typedef struct _greth_regs {
- volatile unsigned int control;
- volatile unsigned int status;
- volatile unsigned int esa_msb;
- volatile unsigned int esa_lsb;
- volatile unsigned int mdio;
- volatile unsigned int tx_desc_p;
- volatile unsigned int rx_desc_p;
-} greth_regs;
-
-/* Ethernet buffer descriptor */
-typedef struct _greth_bd {
- volatile unsigned int stat;
- unsigned int addr; /* Buffer address not changed by HW */
-} greth_bd;
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index f7c973432ec9..bc9ff89527bc 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -172,21 +172,6 @@ gd_t *global_data;
" nop\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r1", "r2");
-#elif defined(CONFIG_SPARC)
-/*
- * g7 holds the pointer to the global_data. g1 is call clobbered.
- */
-#define EXPORT_FUNC(f, a, x, ...) \
- asm volatile( \
-" .globl\t" #x "\n" \
-#x ":\n" \
-" set %0, %%g1\n" \
-" or %%g1, %%g7, %%g1\n" \
-" ld [%%g1], %%g1\n" \
-" ld [%%g1 + %1], %%g1\n" \
-" jmp %%g1\n" \
-" nop\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "g1");
#elif defined(CONFIG_NDS32)
/*
* r16 holds the pointer to the global_data. gp is call clobbered.
diff --git a/include/ambapp.h b/include/ambapp.h
deleted file mode 100644
index d79fcedb4139..000000000000
--- a/include/ambapp.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Interface for accessing Gaisler AMBA Plug&Play Bus.
- * The AHB bus can be interfaced with a simpler bus -
- * the APB bus, also freely available in GRLIB at
- * www.gaisler.com.
- *
- * (C) Copyright 2009, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __AMBAPP_H__
-#define __AMBAPP_H__
-
-#include <ambapp_ids.h>
-
-#ifndef __ASSEMBLER__
-/* Structures used to access Plug&Play information directly */
-struct ambapp_pnp_ahb {
- const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
- const unsigned int custom[3];
- const unsigned int mbar[4]; /* MASK, ADDRESS, TYPE,
- * CACHABLE/PREFETCHABLE */
-};
-
-struct ambapp_pnp_apb {
- const unsigned int id; /* VENDOR, DEVICE, VER, IRQ, */
- const unsigned int iobar; /* MASK, ADDRESS, TYPE,
- * CACHABLE/PREFETCHABLE */
-};
-
-/* AMBA Plug&Play AHB Masters & Slaves information locations
- * Max devices is 64 supported by HW, however often only 16
- * are used.
- */
-struct ambapp_pnp_info {
- struct ambapp_pnp_ahb masters[64];
- struct ambapp_pnp_ahb slaves[63];
- const unsigned int unused[4];
- const unsigned int systemid[4];
-};
-
-/* Describes a AMBA PnP bus */
-struct ambapp_bus {
- int buses; /* Number of buses */
- unsigned int ioareas[6]; /* PnP I/O AREAs of AHB buses */
- unsigned int freq; /* Frequency of bus0 [Hz] */
-};
-
-/* Processor Local AMBA bus */
-extern struct ambapp_bus ambapp_plb;
-
-/* Get Bus frequency of a certain AMBA bus */
-extern unsigned int ambapp_bus_freq(
- struct ambapp_bus *abus,
- int ahb_bus_index
- );
-
-/* AMBA PnP information of a APB Device */
-typedef struct {
- unsigned int vendor;
- unsigned int device;
- unsigned char irq;
- unsigned char ver;
- unsigned int address;
- unsigned int mask;
- int ahb_bus_index;
-} ambapp_apbdev;
-
-/* AMBA PnP information of a AHB Device */
-typedef struct {
- unsigned int vendor;
- unsigned int device;
- unsigned char irq;
- unsigned char ver;
- unsigned int userdef[3];
- unsigned int address[4];
- unsigned int mask[4];
- int type[4];
- int ahb_bus_index;
-} ambapp_ahbdev;
-
-/* Scan AMBA Bus for AHB Bridges */
-extern void ambapp_bus_init(
- unsigned int ioarea,
- unsigned int freq,
- struct ambapp_bus *abus);
-
-/* Find APB Slave device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_apb_find(
- struct ambapp_bus *abus,
- int vendor,
- int device,
- int index,
- ambapp_apbdev *dev
- );
-
-/* Find AHB Master device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_ahbmst_find(
- struct ambapp_bus *abus,
- int vendor,
- int device,
- int index,
- ambapp_ahbdev *dev
- );
-
-/* Find AHB Slave device by index using breath first search.
- *
- * When vendor and device are both set to zero, any device
- * with a non-zero device ID will match the search. It may be
- * useful when processing all devices on a AMBA bus.
- */
-extern int ambapp_ahbslv_find(
- struct ambapp_bus *abus,
- int vendor,
- int device,
- int index,
- ambapp_ahbdev *dev
- );
-
-/* Return number of APB Slave devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_apb_count(struct ambapp_bus *abus, int vendor, int device);
-
-/* Return number of AHB Master devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_ahbmst_count(struct ambapp_bus *abus, int vendor, int device);
-
-/* Return number of AHB Slave devices of a certain ID (VENDOR:DEVICE)
- * zero is returned if no devices was found.
- */
-extern int ambapp_ahbslv_count(struct ambapp_bus *abus, int vendor, int device);
-
-#ifdef CONFIG_CMD_AMBAPP
-
-/* AMBA Plug&Play relocation & initialization */
-int ambapp_init_reloc(void);
-
-/* AMBA Plug&Play Name of Vendors and devices */
-
-/* Return name of device */
-char *ambapp_device_id2str(int vendor, int id);
-
-/* Return name of vendor */
-char *ambapp_vendor_id2str(int vendor);
-
-/* Return description of a device */
-char *ambapp_device_id2desc(int vendor, int id);
-
-#endif
-
-#endif /* defined(__ASSEMBLER__) */
-
-#define AMBA_DEFAULT_IOAREA 0xfff00000
-#define AMBA_CONF_AREA 0xff000
-#define AMBA_AHB_SLAVE_CONF_AREA 0x800
-
-#define DEV_NONE 0
-#define DEV_AHB_MST 1
-#define DEV_AHB_SLV 2
-#define DEV_APB_SLV 3
-
-#define AMBA_TYPE_APBIO 0x1
-#define AMBA_TYPE_MEM 0x2
-#define AMBA_TYPE_AHBIO 0x3
-
-/* ID layout for APB and AHB devices */
-#define AMBA_PNP_ID(vendor, device) (((vendor)<<24) | ((device)<<12))
-
-/* APB Slave PnP layout definitions */
-#define AMBA_APB_ID_OFS (0*4)
-#define AMBA_APB_IOBAR_OFS (1*4)
-#define AMBA_APB_CONF_LENGH (2*4)
-
-/* AHB Master/Slave layout PnP definitions */
-#define AMBA_AHB_ID_OFS (0*4)
-#define AMBA_AHB_CUSTOM0_OFS (1*4)
-#define AMBA_AHB_CUSTOM1_OFS (2*4)
-#define AMBA_AHB_CUSTOM2_OFS (3*4)
-#define AMBA_AHB_MBAR0_OFS (4*4)
-#define AMBA_AHB_MBAR1_OFS (5*4)
-#define AMBA_AHB_MBAR2_OFS (6*4)
-#define AMBA_AHB_MBAR3_OFS (7*4)
-#define AMBA_AHB_CONF_LENGH (8*4)
-
-/* Macros for extracting information from AMBA PnP information
- * registers.
- */
-
-#define amba_vendor(x) (((x) >> 24) & 0xff)
-
-#define amba_device(x) (((x) >> 12) & 0xfff)
-
-#define amba_irq(conf) ((conf) & 0x1f)
-
-#define amba_ver(conf) (((conf)>>5) & 0x1f)
-
-#define amba_iobar_start(base, iobar) \
- ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)))
-
-#define amba_membar_start(mbar) \
- (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
-
-#define amba_membar_type(mbar) ((mbar) & 0xf)
-
-#define amba_membar_mask(mbar) (((mbar) >> 4) & 0xfff)
-
-#define amba_ahbio_adr(addr, base_ioarea) \
- ((unsigned int)(base_ioarea) | ((addr) >> 12))
-
-#define amba_apb_mask(iobar) ((~(amba_membar_mask(iobar)<<8) & 0x000fffff) + 1)
-
-#endif
diff --git a/include/ambapp_ids.h b/include/ambapp_ids.h
deleted file mode 100644
index 1eae34e554a4..000000000000
--- a/include/ambapp_ids.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* AMBA Plug & Play Bus Vendor and Device IDs.
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#ifndef __AMBAPP_IDS_H__
-#define __AMBAPP_IDS_H__
-
-/* Vendor ID defines */
-#define VENDOR_GAISLER 0x01
-#define VENDOR_PENDER 0x02
-#define VENDOR_ESA 0x04
-#define VENDOR_ASTRIUM 0x06
-#define VENDOR_OPENCHIP 0x07
-#define VENDOR_OPENCORES 0x08
-#define VENDOR_CONTRIB 0x09
-#define VENDOR_EONIC 0x0b
-#define VENDOR_RADIONOR 0x0f
-#define VENDOR_GLEICHMANN 0x10
-#define VENDOR_MENTA 0x11
-#define VENDOR_SUN 0x13
-#define VENDOR_MOVIDIA 0x14
-#define VENDOR_ORBITA 0x17
-#define VENDOR_SYNOPSYS 0x21
-#define VENDOR_NASA 0x22
-#define VENDOR_S3 0x31
-#define VENDOR_CAL 0xca
-#define VENDOR_EMBEDDIT 0xea
-#define VENDOR_CETON 0xcb
-#define VENDOR_ACTEL 0xac
-#define VENDOR_APPLECORE 0xae
-
-/* Aeroflex Gaisler device ID defines */
-#define GAISLER_LEON2DSU 0x002
-#define GAISLER_LEON3 0x003
-#define GAISLER_LEON3DSU 0x004
-#define GAISLER_ETHAHB 0x005
-#define GAISLER_APBMST 0x006
-#define GAISLER_AHBUART 0x007
-#define GAISLER_SRCTRL 0x008
-#define GAISLER_SDCTRL 0x009
-#define GAISLER_SSRCTRL 0x00a
-#define GAISLER_APBUART 0x00c
-#define GAISLER_IRQMP 0x00d
-#define GAISLER_AHBRAM 0x00e
-#define GAISLER_AHBDPRAM 0x00f
-#define GAISLER_GPTIMER 0x011
-#define GAISLER_PCITRG 0x012
-#define GAISLER_PCISBRG 0x013
-#define GAISLER_PCIFBRG 0x014
-#define GAISLER_PCITRACE 0x015
-#define GAISLER_DMACTRL 0x016
-#define GAISLER_AHBTRACE 0x017
-#define GAISLER_DSUCTRL 0x018
-#define GAISLER_CANAHB 0x019
-#define GAISLER_GPIO 0x01a
-#define GAISLER_AHBROM 0x01b
-#define GAISLER_AHBJTAG 0x01c
-#define GAISLER_ETHMAC 0x01d
-#define GAISLER_SWNODE 0x01e
-#define GAISLER_SPW 0x01f
-#define GAISLER_AHB2AHB 0x020
-#define GAISLER_USBDC 0x021
-#define GAISLER_USB_DCL 0x022
-#define GAISLER_DDRMP 0x023
-#define GAISLER_ATACTRL 0x024
-#define GAISLER_DDRSP 0x025
-#define GAISLER_EHCI 0x026
-#define GAISLER_UHCI 0x027
-#define GAISLER_I2CMST 0x028
-#define GAISLER_SPW2 0x029
-#define GAISLER_AHBDMA 0x02a
-#define GAISLER_NUHOSP3 0x02b
-#define GAISLER_CLKGATE 0x02c
-#define GAISLER_SPICTRL 0x02d
-#define GAISLER_DDR2SP 0x02e
-#define GAISLER_SLINK 0x02f
-#define GAISLER_GRTM 0x030
-#define GAISLER_GRTC 0x031
-#define GAISLER_GRPW 0x032
-#define GAISLER_GRCTM 0x033
-#define GAISLER_GRHCAN 0x034
-#define GAISLER_GRFIFO 0x035
-#define GAISLER_GRADCDAC 0x036
-#define GAISLER_GRPULSE 0x037
-#define GAISLER_GRTIMER 0x038
-#define GAISLER_AHB2PP 0x039
-#define GAISLER_GRVERSION 0x03a
-#define GAISLER_APB2PW 0x03b
-#define GAISLER_PW2APB 0x03c
-#define GAISLER_GRCAN 0x03d
-#define GAISLER_I2CSLV 0x03e
-#define GAISLER_U16550 0x03f
-#define GAISLER_AHBMST_EM 0x040
-#define GAISLER_AHBSLV_EM 0x041
-#define GAISLER_GRTESTMOD 0x042
-#define GAISLER_ASCS 0x043
-#define GAISLER_IPMVBCTRL 0x044
-#define GAISLER_SPIMCTRL 0x045
-#define GAISLER_L4STAT 0x047
-#define GAISLER_LEON4 0x048
-#define GAISLER_LEON4DSU 0x049
-#define GAISLER_PWM 0x04a
-#define GAISLER_L2CACHE 0x04b
-#define GAISLER_SDCTRL64 0x04c
-#define GAISLER_GR1553B 0x04d
-#define GAISLER_1553TST 0x04e
-#define GAISLER_GRIOMMU 0x04f
-#define GAISLER_FTAHBRAM 0x050
-#define GAISLER_FTSRCTRL 0x051
-#define GAISLER_AHBSTAT 0x052
-#define GAISLER_LEON3FT 0x053
-#define GAISLER_FTMCTRL 0x054
-#define GAISLER_FTSDCTRL 0x055
-#define GAISLER_FTSRCTRL8 0x056
-#define GAISLER_MEMSCRUB 0x057
-#define GAISLER_FTSDCTRL64 0x058
-#define GAISLER_APBPS2 0x060
-#define GAISLER_VGACTRL 0x061
-#define GAISLER_LOGAN 0x062
-#define GAISLER_SVGACTRL 0x063
-#define GAISLER_T1AHB 0x064
-#define GAISLER_MP7WRAP 0x065
-#define GAISLER_GRSYSMON 0x066
-#define GAISLER_GRACECTRL 0x067
-#define GAISLER_ATAHBSLV 0x068
-#define GAISLER_ATAHBMST 0x069
-#define GAISLER_ATAPBSLV 0x06a
-#define GAISLER_B1553BC 0x070
-#define GAISLER_B1553RT 0x071
-#define GAISLER_B1553BRM 0x072
-#define GAISLER_AES 0x073
-#define GAISLER_ECC 0x074
-#define GAISLER_PCIF 0x075
-#define GAISLER_CLKMOD 0x076
-#define GAISLER_HAPSTRAK 0x077
-#define GAISLER_TEST_1X2 0x078
-#define GAISLER_WILD2AHB 0x079
-#define GAISLER_BIO1 0x07a
-#define GAISLER_AESDMA 0x07b
-#define GAISLER_SATCAN 0x080
-#define GAISLER_CANMUX 0x081
-#define GAISLER_GRTMRX 0x082
-#define GAISLER_GRTCTX 0x083
-#define GAISLER_GRTMDESC 0x084
-#define GAISLER_GRTMVC 0x085
-#define GAISLER_GEFFE 0x086
-#define GAISLER_GPREG 0x087
-#define GAISLER_GRTMPAHB 0x088
-#define GAISLER_SPWCUC 0x089
-#define GAISLER_SPW2_DMA 0x08a
-#define GAISLER_SPWROUTER 0x08b
-
-/* European Space Agency device ID defines */
-#define ESA_LEON2 0x002
-#define ESA_LEON2APB 0x003
-#define ESA_IRQ 0x005
-#define ESA_TIMER 0x006
-#define ESA_UART 0x007
-#define ESA_CFG 0x008
-#define ESA_IO 0x009
-#define ESA_MCTRL 0x00f
-#define ESA_PCIARB 0x010
-#define ESA_HURRICANE 0x011
-#define ESA_SPW_RMAP 0x012
-#define ESA_AHBUART 0x013
-#define ESA_SPWA 0x014
-#define ESA_BOSCHCAN 0x015
-#define ESA_IRQ2 0x016
-#define ESA_AHBSTAT 0x017
-#define ESA_WPROT 0x018
-#define ESA_WPROT2 0x019
-#define ESA_PDEC3AMBA 0x020
-#define ESA_PTME3AMBA 0x021
-
-/* OpenChip device ID defines */
-#define OPENCHIP_APBGPIO 0x001
-#define OPENCHIP_APBI2C 0x002
-#define OPENCHIP_APBSPI 0x003
-#define OPENCHIP_APBCHARLCD 0x004
-#define OPENCHIP_APBPWM 0x005
-#define OPENCHIP_APBPS2 0x006
-#define OPENCHIP_APBMMCSD 0x007
-#define OPENCHIP_APBNAND 0x008
-#define OPENCHIP_APBLPC 0x009
-#define OPENCHIP_APBCF 0x00a
-#define OPENCHIP_APBSYSACE 0x00b
-#define OPENCHIP_APB1WIRE 0x00c
-#define OPENCHIP_APBJTAG 0x00d
-#define OPENCHIP_APBSUI 0x00e
-
-/* Various contributions device ID defines */
-#define CONTRIB_CORE1 0x001
-#define CONTRIB_CORE2 0x002
-
-/* Gleichmann Electronics device ID defines */
-#define GLEICHMANN_CUSTOM 0x001
-#define GLEICHMANN_GEOLCD01 0x002
-#define GLEICHMANN_DAC 0x003
-#define GLEICHMANN_HPI 0x004
-#define GLEICHMANN_SPI 0x005
-#define GLEICHMANN_HIFC 0x006
-#define GLEICHMANN_ADCDAC 0x007
-#define GLEICHMANN_SPIOC 0x008
-#define GLEICHMANN_AC97 0x009
-
-/* Sun Microsystems device ID defines */
-#define SUN_T1 0x001
-#define SUN_S1 0x011
-
-/* Orbita device ID defines */
-#define ORBITA_1553B 0x001
-#define ORBITA_429 0x002
-#define ORBITA_SPI 0x003
-#define ORBITA_I2C 0x004
-#define ORBITA_SMARTCARD 0x064
-#define ORBITA_SDCARD 0x065
-#define ORBITA_UART16550 0x066
-#define ORBITA_CRYPTO 0x067
-#define ORBITA_SYSIF 0x068
-#define ORBITA_PIO 0x069
-#define ORBITA_RTC 0x0c8
-#define ORBITA_COLORLCD 0x12c
-#define ORBITA_PCI 0x190
-#define ORBITA_DSP 0x1f4
-#define ORBITA_USBHOST 0x258
-#define ORBITA_USBDEV 0x2bc
-
-/* NASA device ID defines */
-#define NASA_EP32 0x001
-
-/* CAL device ID defines */
-#define CAL_DDRCTRL 0x188
-
-/* Actel Corporation device ID defines */
-#define ACTEL_COREMP7 0x001
-
-/* AppleCore device ID defines */
-#define APPLECORE_UTLEON3 0x001
-#define APPLECORE_UTLEON3DSU 0x002
-
-/* Opencores device id's */
-#define OPENCORES_PCIBR 0x4
-#define OPENCORES_ETHMAC 0x5
-
-#endif
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
deleted file mode 100644
index c2655552f1c0..000000000000
--- a/include/configs/gr_cpci_ax2000.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/* Configuration header file for Gaisler GR-CPCI-AX2000
- * AX board. Note that since the AX is removable the configuration
- * for this board must be edited below.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_CPCI_AX2000 1 /* ... on GR-CPCI-AX2000 board */
-
-#define CONFIG_LEON_RAM_SRAM 1
-#define CONFIG_LEON_RAM_SDRAM 2
-#define CONFIG_LEON_RAM_SDRAM_NOSRAM 3
-
-/* Select Memory to run from
- *
- * SRAM - UBoot is run in SRAM, SRAM-0x40000000, SDRAM-0x60000000
- * SDRAM - UBoot is run in SDRAM, SRAM-0x40000000 and SDRAM-0x60000000
- * SDRAM_NOSRAM - UBoot is run in SDRAM, SRAM not available, SDRAM at 0x40000000
- *
- * Note, if Linux is to be used, SDRAM or SDRAM_NOSRAM is required since
- * it doesn't fit into the 4Mb SRAM.
- *
- * SRAM is default since it will work for all systems, however will not
- * be able to boot linux.
- */
-#define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS_BASE \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "getkernel=tftpboot $(scratch) $(bootfile)\0" \
- "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:ax2000:eth0\0"
-
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "scratch=40200000\0" \
- ""
-#elif CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
- "net_nfs=tftp 60000000 ${bootfile};run nfsargs addip;bootm\0" \
- "scratch=60800000\0" \
- ""
-#else
-/* More than 4Mb is assumed when running from SDRAM */
-#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "scratch=40800000\0" \
- ""
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_BASE CONFIG_EXTRA_ENV_SETTINGS_SELECT
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.206
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME ax2000
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* Memory MAP
- *
- * Flash:
- * |--------------------------------|
- * | 0x00000000 Text & Data & BSS | *
- * | for Monitor | *
- * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- * | UNUSED / Growth | * 256kb
- * |--------------------------------|
- * | 0x00050000 Base custom area | *
- * | kernel / FS | *
- * | | * Rest of Flash
- * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- * | END-0x00008000 Environment | * 32kb
- * |--------------------------------|
- *
- *
- *
- * Main Memory (4Mb SRAM or XMb SDRAM):
- * |--------------------------------|
- * | UNUSED / scratch area |
- * | |
- * | |
- * | |
- * | |
- * |--------------------------------|
- * | Monitor .Text / .DATA / .BSS | * 256kb
- * | Relocated! | *
- * |--------------------------------|
- * | Monitor Malloc | * 128kb (contains relocated environment)
- * |--------------------------------|
- * | Monitor/kernel STACK | * 64kb
- * |--------------------------------|
- * | Page Table for MMU systems | * 2k
- * |--------------------------------|
- * | PROM Code accessed from Linux | * 6kb-128b
- * |--------------------------------|
- * | Global data (avail from kernel)| * 128b
- * |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- *
- * Always 4Mb SRAM available
- * SDRAM module may be available on 0x60000000, SDRAM
- * is configured as if a 128Mb SDRAM module is available.
- */
-
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#else
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
-#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* 4Mb SRAM available */
-#if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_SRAM_BASE 0x40000000
-#define CONFIG_SYS_SRAM_SIZE 0x400000
-#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE)
-#endif
-
-/* Select RAM used to run U-BOOT from... */
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END
-#else
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-#endif
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration uses on board SMC91C111
- */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
-#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-/*#define CONFIG_SHOW_ACTIVITY*/
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Various low-level settings
- */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM 0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
-#else
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82205260
-#endif
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x0809a000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
-#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
-#else
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82205260
-#endif
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x0809a000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
deleted file mode 100644
index 0d513c551943..000000000000
--- a/include/configs/gr_ep2s60.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/* Configuration header file for Gaisler Research AB's Template
- * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
- * Development board Stratix II edition, with the FPGA device
- * EP2S60.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* Altera NIOS Development board, Stratix II board */
-#define CONFIG_GR_EP2S60 1
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
-
-/* Define this is the GR-2S60-MEZZ mezzanine is available and you
- * want to use the USB and GRETH functionality of the board
- */
-#undef GR_2S60_MEZZ
-
-#ifdef GR_2S60_MEZZ
-#define USE_GRETH 1
-#define USE_GRUSB 1
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/* USB support */
-#if USE_GRUSB
-#define CONFIG_USB_UHCI
-/* Enable needed helper functions */
-#endif
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "scratch=40800000\0" \
- "getkernel=tftpboot $(scratch) $(bootfile)\0" \
- "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
- ""
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.207
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME ml401
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* Memory MAP
- *
- * Flash:
- * |--------------------------------|
- * | 0x00000000 Text & Data & BSS | *
- * | for Monitor | *
- * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- * | UNUSED / Growth | * 256kb
- * |--------------------------------|
- * | 0x00050000 Base custom area | *
- * | kernel / FS | *
- * | | * Rest of Flash
- * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- * | END-0x00008000 Environment | * 32kb
- * |--------------------------------|
- *
- *
- *
- * Main Memory:
- * |--------------------------------|
- * | UNUSED / scratch area |
- * | |
- * | |
- * | |
- * | |
- * |--------------------------------|
- * | Monitor .Text / .DATA / .BSS | * 512kb
- * | Relocated! | *
- * |--------------------------------|
- * | Monitor Malloc | * 128kb (contains relocated environment)
- * |--------------------------------|
- * | Monitor/kernel STACK | * 64kb
- * |--------------------------------|
- * | Page Table for MMU systems | * 2k
- * |--------------------------------|
- * | PROM Code accessed from Linux | * 6kb-128b
- * |--------------------------------|
- * | Global data (avail from kernel)| * 128b
- * |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
-
-#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000
-#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration uses on board SMC91C111, however if a mezzanine
- * with a PHY is attached the GRETH can be used on this board.
- * Define USE_GRETH in order to use the mezzanine provided PHY with the
- * onchip GRETH network MAC, note that this is not supported by the
- * template design.
- */
-#ifndef USE_GRETH
-
-/* USE SMC91C111 MAC */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
-#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-/*#define CONFIG_SHOW_ACTIVITY*/
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-#else
-
-/* USE GRETH Ethernet Driver */
-#define CONFIG_GRETH 1
-#endif
-
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM 0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
-
-/* DDR controller */
-#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
deleted file mode 100644
index 20eeab33d9c9..000000000000
--- a/include/configs/gr_xc3s_1500.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/* Configuration header file for Gaisler GR-XC3S-1500
- * spartan board.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_IRQ
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "scratch=40200000\0" \
- "getkernel=tftpboot $(scratch) $(bootfile)\0" \
- "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
- ""
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.20
-#define CONFIG_IPADDR 192.168.0.206
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* Memory MAP
- *
- * Flash:
- * |--------------------------------|
- * | 0x00000000 Text & Data & BSS | *
- * | for Monitor | *
- * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- * | UNUSED / Growth | * 256kb
- * |--------------------------------|
- * | 0x00050000 Base custom area | *
- * | kernel / FS | *
- * | | * Rest of Flash
- * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- * | END-0x00008000 Environment | * 32kb
- * |--------------------------------|
- *
- *
- *
- * Main Memory:
- * |--------------------------------|
- * | UNUSED / scratch area |
- * | |
- * | |
- * | |
- * | |
- * |--------------------------------|
- * | Monitor .Text / .DATA / .BSS | * 256kb
- * | Relocated! | *
- * |--------------------------------|
- * | Monitor Malloc | * 128kb (contains relocated environment)
- * |--------------------------------|
- * | Monitor/kernel STACK | * 64kb
- * |--------------------------------|
- * | Page Table for MMU systems | * 2k
- * |--------------------------------|
- * | PROM Code accessed from Linux | * 6kb-128b
- * |--------------------------------|
- * | Global data (avail from kernel)| * 128b
- * |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Bypass cache when reading regs from flash memory */
-#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
-/* Buffered writes (32byte/go) instead of single accesses */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Environment settings
- */
-/*#define CONFIG_ENV_IS_NOWHERE 1*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-/* CONFIG_ENV_ADDR need to be at sector boundary */
-#define CONFIG_ENV_SIZE 0x8000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 0x4000000
-#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_GRETH 1
-
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Various low-level settings
- */
-
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM 0
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* See, GRLIB Docs (grip.pdf) on how to set up
- * These the memory controller registers.
- */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
deleted file mode 100644
index 18b8d3cbcbbe..000000000000
--- a/include/configs/grsim.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* Configuration header file for LEON3 GRSIM, trying to be similar
- * to Gaisler's GR-XC3S-1500 board.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- *
- * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
- *
- * TSIM command:
- * $ tsim-leon3 -sdram 32768 -ram 4096 -rom 2048 -mmu -cas
- *
- * In the evaluation version of TSIM, the -sdram/-ram/-rom arguments are
- * hard-coded to these values and need not be specified. (see below)
- *
- * Get TSIM from http://www.gaisler.com/index.php/downloads/simulators
- */
-
-#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
-#define CONFIG_TSIM 1 /* ... running on TSIM */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/export/roofs\0" \
- "scratch=40000000\0" \
- "getkernel=tftpboot $(scratch) $(bootfile)\0" \
- "bootargs=console=ttyS0,38400" \
- ""
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.81
-#define CONFIG_IPADDR 192.168.0.80
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* Memory MAP
- *
- * Flash:
- * |--------------------------------|
- * | 0x00000000 Text & Data & BSS | *
- * | for Monitor | *
- * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- * | UNUSED / Growth | * 256kb
- * |--------------------------------|
- * | 0x00050000 Base custom area | *
- * | kernel / FS | *
- * | | * Rest of Flash
- * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- * | END-0x00008000 Environment | * 32kb
- * |--------------------------------|
- *
- *
- *
- * Main Memory:
- * |--------------------------------|
- * | UNUSED / scratch area |
- * | |
- * | |
- * | |
- * | |
- * |--------------------------------|
- * | Monitor .Text / .DATA / .BSS | * 256kb
- * | Relocated! | *
- * |--------------------------------|
- * | Monitor Malloc | * 128kb (contains relocated environment)
- * |--------------------------------|
- * | Monitor/kernel STACK | * 64kb
- * |--------------------------------|
- * | Page Table for MMU systems | * 2k
- * |--------------------------------|
- * | PROM Code accessed from Linux | * 6kb-128b
- * |--------------------------------|
- * | Global data (avail from kernel)| * 128b
- * |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-#define CONFIG_ENV_SIZE 0x8000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-
-#ifdef ENABLE_FLASH_SUPPORT
-/* For use with grsim FLASH emulation extension */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_NOWHERE 1
-/*#define CONFIG_ENV_IS_IN_FLASH*/
-/*#define CONFIG_ENV_SIZE 0x8000*/
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000 /* 32MiB SDRAM */
-#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE)
-
-#define CONFIG_SYS_SRAM_BASE 0x40000000
-#define CONFIG_SYS_SRAM_SIZE 0x00400000 /* 4MiB SRAM */
-#define CONFIG_SYS_SRAM_END (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE)
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-#ifdef CONFIG_CMD_NET
-/*
- * Ethernet configuration
- */
-#define CONFIG_GRETH 1
-
-/*
- * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
- */
-/* #define CONFIG_GRETH_10MBIT 1 */
-#define CONFIG_PHY_ADDR 0x00
-
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM 0
-
-#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
-
-/* No SDRAM Configuration */
-#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
-
-/* LEON2 MCTRL configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x000000ff | (1<<11))
-#if CONFIG_GRSIM
-/* GRSIM configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x82206000
-#else
-/* TSIM configuration */
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x81805220
-#endif
-#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00136000
-
-/* GRLIB FT-MCTRL configuration */
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x000000ff | (1<<11))
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x82206000
-#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00136000
-
-/* no DDR controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
-
-/* no DDR2 Controller */
-#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-/* TSIM command:
- * $ ./tsim-leon3 -mmu -cas
- *
- * This TSIM evaluation version will expire 2015-04-02
- *
- *
- * TSIM/LEON3 SPARC simulator, version 2.0.35 (evaluation version)
- *
- * Copyright (C) 2014, Aeroflex Gaisler - all rights reserved.
- * This software may only be used with a valid license.
- * For latest updates, go to http://www.gaisler.com/
- * Comments or bug-reports to support@gaisler.com
- *
- * serial port A on stdin/stdout
- * allocated 4096 K SRAM memory, in 1 bank
- * allocated 32 M SDRAM memory, in 1 bank
- * allocated 2048 K ROM memory
- * icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
- * dcache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
- * tsim> leon
- * 0x80000000 Memory configuration register 1 0x000002ff
- * 0x80000004 Memory configuration register 2 0x81805220
- * 0x80000008 Memory configuration register 3 0x00000000
- */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
deleted file mode 100644
index ba570c38a9f2..000000000000
--- a/include/configs/grsim_leon2.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/* Configuration header file for LEON2 GRSIM.
- *
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-/*
- * High Level Configuration Options
- * (easy to change)
- *
- * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
- *
- * TSIM command
- * tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu
- *
- */
-
-#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
-#define CONFIG_TSIM 1 /* ... running on TSIM */
-
-/* CPU / AMBA BUS configuration */
-#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* Partitions */
-
-/*
- * Supported commands
- */
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-
-/*
- * Autobooting
- */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/export/roofs\0" \
- "scratch=40000000\0" \
- "getkernel=tftpboot $(scratch) $(bootfile)\0" \
- "bootargs=console=ttyS0,38400" \
- ""
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.81
-#define CONFIG_IPADDR 192.168.0.80
-#define CONFIG_ROOTPATH "/export/rootfs"
-#define CONFIG_HOSTNAME grxc3s1500
-#define CONFIG_BOOTFILE "/uImage"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/* Memory MAP
- *
- * Flash:
- * |--------------------------------|
- * | 0x00000000 Text & Data & BSS | *
- * | for Monitor | *
- * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
- * | UNUSED / Growth | * 256kb
- * |--------------------------------|
- * | 0x00050000 Base custom area | *
- * | kernel / FS | *
- * | | * Rest of Flash
- * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
- * | END-0x00008000 Environment | * 32kb
- * |--------------------------------|
- *
- *
- *
- * Main Memory:
- * |--------------------------------|
- * | UNUSED / scratch area |
- * | |
- * | |
- * | |
- * | |
- * |--------------------------------|
- * | Monitor .Text / .DATA / .BSS | * 256kb
- * | Relocated! | *
- * |--------------------------------|
- * | Monitor Malloc | * 128kb (contains relocated environment)
- * |--------------------------------|
- * | Monitor/kernel STACK | * 64kb
- * |--------------------------------|
- * | Page Table for MMU systems | * 2k
- * |--------------------------------|
- * | PROM Code accessed from Linux | * 6kb-128b
- * |--------------------------------|
- * | Global data (avail from kernel)| * 128b
- * |--------------------------------|
- *
- */
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x00800000
-#define CONFIG_ENV_SIZE 0x8000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
-
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-
-#ifdef ENABLE_FLASH_SUPPORT
-/* For use with grsim FLASH emulation extension */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */
-
-/*** CFI CONFIG ***/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_NOWHERE 1
-/*#define CONFIG_ENV_IS_IN_FLASH*/
-/*#define CONFIG_ENV_SIZE 0x8000*/
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 0x00800000
-#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
-
-/* no SRAM available */
-#undef CONFIG_SYS_SRAM_BASE
-#undef CONFIG_SYS_SRAM_SIZE
-
-/* Always Run U-Boot from SDRAM */
-#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
-#define CONFIG_SYS_STACK_SIZE (0x10000-32)
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
-
-/* relocated monitor area */
-#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
-#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
-
-/* make un relocated address from relocated address */
-#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
-
-/*
- * Ethernet configuration
- */
-/*#define CONFIG_GRETH 1*/
-
-/*
- * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
- */
-/* #define CONFIG_GRETH_10MBIT 1 */
-#define CONFIG_PHY_ADDR 0x00
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/***** Gaisler GRLIB IP-Cores Config ********/
-
-#define CONFIG_SYS_GRLIB_SDRAM 0
-#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
-#if CONFIG_GRSIM
-#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
-#else
-#define CONFIG_SYS_GRLIB_MEMCFG2 0x00001820
-#endif
-#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000
-
-/*** LEON2 UART 1 ***/
-
-/* UART1 Define to 1 or 0 */
-#define LEON2_UART1_LOOPBACK_ENABLE 0
-#define LEON2_UART1_FLOWCTRL_ENABLE 0
-#define LEON2_UART1_PARITY_ENABLE 0
-#define LEON2_UART1_ODDPAR_ENABLE 0
-
-/*** LEON2 UART 2 ***/
-
-/* UART2 Define to 1 or 0 */
-#define LEON2_UART2_LOOPBACK_ENABLE 0
-#define LEON2_UART2_FLOWCTRL_ENABLE 0
-#define LEON2_UART2_PARITY_ENABLE 0
-#define LEON2_UART2_ODDPAR_ENABLE 0
-
-#define LEON_CONSOLE_UART1 1
-#define LEON_CONSOLE_UART2 2
-
-/* Use UART2 as console */
-#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1
-
-/* LEON2 I/O Port */
-/*#define LEON2_IO_PORT_DIR 0x0000aa00*/
-
-/* default kernel command line */
-#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
-
-#endif /* __CONFIG_H */
diff --git a/include/grlib/apbuart.h b/include/grlib/apbuart.h
deleted file mode 100644
index 1e1eb9a77cad..000000000000
--- a/include/grlib/apbuart.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* GRLIB APBUART definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __GRLIB_APBUART_H__
-#define __GRLIB_APBUART_H__
-
-/* APBUART Register map */
-typedef struct {
- volatile unsigned int data;
- volatile unsigned int status;
- volatile unsigned int ctrl;
- volatile unsigned int scaler;
-} ambapp_dev_apbuart;
-
-/*
- * The following defines the bits in the LEON UART Status Registers.
- */
-
-#define APBUART_STATUS_DR 0x00000001 /* Data Ready */
-#define APBUART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
-#define APBUART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
-#define APBUART_STATUS_BR 0x00000008 /* Break Error */
-#define APBUART_STATUS_OE 0x00000010 /* RX Overrun Error */
-#define APBUART_STATUS_PE 0x00000020 /* RX Parity Error */
-#define APBUART_STATUS_FE 0x00000040 /* RX Framing Error */
-#define APBUART_STATUS_ERR 0x00000078 /* Error Mask */
-
-/*
- * The following defines the bits in the LEON UART Ctrl Registers.
- */
-
-#define APBUART_CTRL_RE 0x00000001 /* Receiver enable */
-#define APBUART_CTRL_TE 0x00000002 /* Transmitter enable */
-#define APBUART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
-#define APBUART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
-#define APBUART_CTRL_PS 0x00000010 /* Parity select */
-#define APBUART_CTRL_PE 0x00000020 /* Parity enable */
-#define APBUART_CTRL_FL 0x00000040 /* Flow control enable */
-#define APBUART_CTRL_LB 0x00000080 /* Loop Back enable */
-#define APBUART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */
-
-#endif
diff --git a/include/grlib/gptimer.h b/include/grlib/gptimer.h
deleted file mode 100644
index 8b2b1651b035..000000000000
--- a/include/grlib/gptimer.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* GRLIB GPTIMER (General Purpose Timer) definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __GRLIB_GPTIMER_H__
-#define __GRLIB_GPTIMER_H__
-
-typedef struct {
- volatile unsigned int val;
- volatile unsigned int rld;
- volatile unsigned int ctrl;
- volatile unsigned int unused;
-} ambapp_dev_gptimer_element;
-
-#define GPTIMER_CTRL_EN 0x1 /* Timer enable */
-#define GPTIMER_CTRL_RS 0x2 /* Timer reStart */
-#define GPTIMER_CTRL_LD 0x4 /* Timer reLoad */
-#define GPTIMER_CTRL_IE 0x8 /* interrupt enable */
-#define GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */
-#define GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */
-
-typedef struct {
- volatile unsigned int scalar;
- volatile unsigned int scalar_reload;
- volatile unsigned int config;
- volatile unsigned int unused;
- volatile ambapp_dev_gptimer_element e[8];
-} ambapp_dev_gptimer;
-
-#endif
diff --git a/include/grlib/greth.h b/include/grlib/greth.h
deleted file mode 100644
index 89c1e49387ed..000000000000
--- a/include/grlib/greth.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Gaisler.com GRETH 10/100/1000 Ethernet MAC definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel at gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __GRLIB_GRETH_H__
-#define __GRLIB_GRETH_H__
-
-#define GRETH_FD 0x10
-#define GRETH_RESET 0x40
-#define GRETH_MII_BUSY 0x8
-#define GRETH_MII_NVALID 0x10
-
-/* MII registers */
-#define GRETH_MII_EXTADV_1000FD 0x00000200
-#define GRETH_MII_EXTADV_1000HD 0x00000100
-#define GRETH_MII_EXTPRT_1000FD 0x00000800
-#define GRETH_MII_EXTPRT_1000HD 0x00000400
-
-#define GRETH_MII_100T4 0x00000200
-#define GRETH_MII_100TXFD 0x00000100
-#define GRETH_MII_100TXHD 0x00000080
-#define GRETH_MII_10FD 0x00000040
-#define GRETH_MII_10HD 0x00000020
-
-#define GRETH_BD_EN 0x800
-#define GRETH_BD_WR 0x1000
-#define GRETH_BD_IE 0x2000
-#define GRETH_BD_LEN 0x7FF
-
-#define GRETH_TXEN 0x1
-#define GRETH_INT_TX 0x8
-#define GRETH_TXI 0x4
-#define GRETH_TXBD_STATUS 0x0001C000
-#define GRETH_TXBD_MORE 0x20000
-#define GRETH_TXBD_IPCS 0x40000
-#define GRETH_TXBD_TCPCS 0x80000
-#define GRETH_TXBD_UDPCS 0x100000
-#define GRETH_TXBD_ERR_LC 0x10000
-#define GRETH_TXBD_ERR_UE 0x4000
-#define GRETH_TXBD_ERR_AL 0x8000
-#define GRETH_TXBD_NUM 128
-#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
-#define GRETH_TX_BUF_SIZE 2048
-
-#define GRETH_INT_RX 0x4
-#define GRETH_RXEN 0x2
-#define GRETH_RXI 0x8
-#define GRETH_RXBD_STATUS 0xFFFFC000
-#define GRETH_RXBD_ERR_AE 0x4000
-#define GRETH_RXBD_ERR_FT 0x8000
-#define GRETH_RXBD_ERR_CRC 0x10000
-#define GRETH_RXBD_ERR_OE 0x20000
-#define GRETH_RXBD_ERR_LE 0x40000
-#define GRETH_RXBD_IP_DEC 0x80000
-#define GRETH_RXBD_IP_CSERR 0x100000
-#define GRETH_RXBD_UDP_DEC 0x200000
-#define GRETH_RXBD_UDP_CSERR 0x400000
-#define GRETH_RXBD_TCP_DEC 0x800000
-#define GRETH_RXBD_TCP_CSERR 0x1000000
-
-#define GRETH_RXBD_NUM 128
-#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
-#define GRETH_RX_BUF_SIZE 2048
-
-/* Ethernet configuration registers */
-typedef struct _greth_regs {
- volatile unsigned int control;
- volatile unsigned int status;
- volatile unsigned int esa_msb;
- volatile unsigned int esa_lsb;
- volatile unsigned int mdio;
- volatile unsigned int tx_desc_p;
- volatile unsigned int rx_desc_p;
- volatile unsigned int edcl_ip;
-} greth_regs;
-
-/* Ethernet buffer descriptor */
-typedef struct _greth_bd {
- volatile unsigned int stat;
- unsigned int addr; /* Buffer address not changed by HW */
-} greth_bd;
-
-#endif
diff --git a/include/grlib/irqmp.h b/include/grlib/irqmp.h
deleted file mode 100644
index 0354d5c21c4c..000000000000
--- a/include/grlib/irqmp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* GRLIB IRQMP (IRQ Multi-processor controller) definitions
- *
- * (C) Copyright 2010, 2015
- * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __GRLIB_IRQMP_H__
-#define __GRLIB_IRQMP_H__
-
-typedef struct {
- volatile unsigned int ilevel;
- volatile unsigned int ipend;
- volatile unsigned int iforce;
- volatile unsigned int iclear;
- volatile unsigned int mstatus;
- volatile unsigned int notused[11];
- volatile unsigned int cpu_mask[16];
- volatile unsigned int cpu_force[16];
-} ambapp_dev_irqmp;
-
-#endif
diff --git a/include/netdev.h b/include/netdev.h
index 7a211bc609dd..8eb8b46619d2 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -50,7 +50,6 @@ int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
int ftgmac100_initialize(bd_t *bits);
int ftmac100_initialize(bd_t *bits);
int ftmac110_initialize(bd_t *bits);
-int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int ks8851_mll_initialize(u8 dev_num, int base_addr);
int lan91c96_initialize(u8 dev_num, int base_addr);
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 3/3] OpenRISC: Remove
2017-03-14 15:08 [U-Boot] [PATCH 1/3] Blackfin: Remove Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 2/3] SPARC: Remove Tom Rini
@ 2017-03-14 15:08 ` Tom Rini
2017-03-16 3:05 ` Simon Glass
2017-04-06 16:23 ` [U-Boot] [U-Boot,3/3] " Tom Rini
2017-04-06 16:23 ` [U-Boot] [U-Boot,1/3] Blackfin: Remove Tom Rini
2 siblings, 2 replies; 7+ messages in thread
From: Tom Rini @ 2017-03-14 15:08 UTC (permalink / raw)
To: u-boot
The OpenRISC architecture is currently unmaintained, remove.
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
MAINTAINERS | 5 -
arch/Kconfig | 4 -
arch/openrisc/Kconfig | 18 -
arch/openrisc/Makefile | 8 -
arch/openrisc/config.mk | 16 -
arch/openrisc/cpu/Makefile | 9 -
arch/openrisc/cpu/cache.c | 138 ----
arch/openrisc/cpu/cpu.c | 145 ----
arch/openrisc/cpu/exceptions.c | 72 --
arch/openrisc/cpu/interrupts.c | 108 ---
arch/openrisc/cpu/start.S | 352 ---------
arch/openrisc/cpu/u-boot.lds | 77 --
arch/openrisc/include/asm/bitops.h | 23 -
arch/openrisc/include/asm/bitops/ffs.h | 23 -
arch/openrisc/include/asm/bitops/fls.h | 23 -
arch/openrisc/include/asm/byteorder.h | 1 -
arch/openrisc/include/asm/cache.h | 22 -
arch/openrisc/include/asm/config.h | 10 -
arch/openrisc/include/asm/global_data.h | 21 -
arch/openrisc/include/asm/gpio.h | 71 --
arch/openrisc/include/asm/io.h | 99 ---
arch/openrisc/include/asm/linkage.h | 0
arch/openrisc/include/asm/openrisc_exc.h | 28 -
arch/openrisc/include/asm/posix_types.h | 72 --
arch/openrisc/include/asm/processor.h | 4 -
arch/openrisc/include/asm/ptrace.h | 128 ---
arch/openrisc/include/asm/sections.h | 11 -
arch/openrisc/include/asm/spr-defs.h | 575 --------------
arch/openrisc/include/asm/string.h | 4 -
arch/openrisc/include/asm/system.h | 26 -
arch/openrisc/include/asm/types.h | 66 --
arch/openrisc/include/asm/u-boot.h | 30 -
arch/openrisc/include/asm/unaligned.h | 1 -
arch/openrisc/lib/Makefile | 9 -
arch/openrisc/lib/bootm.c | 74 --
arch/openrisc/lib/timer.c | 98 ---
board/openrisc/openrisc-generic/Kconfig | 12 -
board/openrisc/openrisc-generic/MAINTAINERS | 6 -
board/openrisc/openrisc-generic/Makefile | 8 -
board/openrisc/openrisc-generic/config.mk | 11 -
board/openrisc/openrisc-generic/openrisc-generic.c | 39 -
board/openrisc/openrisc-generic/or1ksim.cfg | 871 ---------------------
cmd/bdinfo.c | 16 +-
configs/openrisc-generic_defconfig | 13 -
examples/standalone/stubs.c | 14 -
include/configs/openrisc-generic.h | 125 ---
46 files changed, 1 insertion(+), 3485 deletions(-)
delete mode 100644 arch/openrisc/Kconfig
delete mode 100644 arch/openrisc/Makefile
delete mode 100644 arch/openrisc/config.mk
delete mode 100644 arch/openrisc/cpu/Makefile
delete mode 100644 arch/openrisc/cpu/cache.c
delete mode 100644 arch/openrisc/cpu/cpu.c
delete mode 100644 arch/openrisc/cpu/exceptions.c
delete mode 100644 arch/openrisc/cpu/interrupts.c
delete mode 100644 arch/openrisc/cpu/start.S
delete mode 100644 arch/openrisc/cpu/u-boot.lds
delete mode 100644 arch/openrisc/include/asm/bitops.h
delete mode 100644 arch/openrisc/include/asm/bitops/ffs.h
delete mode 100644 arch/openrisc/include/asm/bitops/fls.h
delete mode 100644 arch/openrisc/include/asm/byteorder.h
delete mode 100644 arch/openrisc/include/asm/cache.h
delete mode 100644 arch/openrisc/include/asm/config.h
delete mode 100644 arch/openrisc/include/asm/global_data.h
delete mode 100644 arch/openrisc/include/asm/gpio.h
delete mode 100644 arch/openrisc/include/asm/io.h
delete mode 100644 arch/openrisc/include/asm/linkage.h
delete mode 100644 arch/openrisc/include/asm/openrisc_exc.h
delete mode 100644 arch/openrisc/include/asm/posix_types.h
delete mode 100644 arch/openrisc/include/asm/processor.h
delete mode 100644 arch/openrisc/include/asm/ptrace.h
delete mode 100644 arch/openrisc/include/asm/sections.h
delete mode 100644 arch/openrisc/include/asm/spr-defs.h
delete mode 100644 arch/openrisc/include/asm/string.h
delete mode 100644 arch/openrisc/include/asm/system.h
delete mode 100644 arch/openrisc/include/asm/types.h
delete mode 100644 arch/openrisc/include/asm/u-boot.h
delete mode 100644 arch/openrisc/include/asm/unaligned.h
delete mode 100644 arch/openrisc/lib/Makefile
delete mode 100644 arch/openrisc/lib/bootm.c
delete mode 100644 arch/openrisc/lib/timer.c
delete mode 100644 board/openrisc/openrisc-generic/Kconfig
delete mode 100644 board/openrisc/openrisc-generic/MAINTAINERS
delete mode 100644 board/openrisc/openrisc-generic/Makefile
delete mode 100644 board/openrisc/openrisc-generic/config.mk
delete mode 100644 board/openrisc/openrisc-generic/openrisc-generic.c
delete mode 100644 board/openrisc/openrisc-generic/or1ksim.cfg
delete mode 100644 configs/openrisc-generic_defconfig
delete mode 100644 include/configs/openrisc-generic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d628eb715aef..aec1c9ef90c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -302,11 +302,6 @@ S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
-OPENRISC
-M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S: Maintained
-F: arch/openrisc/
-
PATMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
diff --git a/arch/Kconfig b/arch/Kconfig
index 6750b5ddf640..c45637d4a589 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -48,9 +48,6 @@ config NIOS2
select DM
select CPU
-config OPENRISC
- bool "OpenRISC architecture"
-
config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
@@ -156,7 +153,6 @@ source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
-source "arch/openrisc/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
deleted file mode 100644
index 11014d1e32ce..000000000000
--- a/arch/openrisc/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-menu "OpenRISC architecture"
- depends on OPENRISC
-
-config SYS_ARCH
- default "openrisc"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_OPENRISC_GENERIC
- bool "Support openrisc-generic"
-
-endchoice
-
-source "board/openrisc/openrisc-generic/Kconfig"
-
-endmenu
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
deleted file mode 100644
index c4da3ce9d8da..000000000000
--- a/arch/openrisc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-head-y := arch/openrisc/cpu/start.o
-
-libs-y += arch/openrisc/cpu/
-libs-y += arch/openrisc/lib/
diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk
deleted file mode 100644
index bfdb71f0befa..000000000000
--- a/arch/openrisc/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := or1k-elf-
-endif
-
-# r10 used for global object pointer, already set in OR32 GCC but just to be
-# clear
-PLATFORM_CPPFLAGS += -D__OR1K__ -ffixed-r10
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile
deleted file mode 100644
index fc47d666fe61..000000000000
--- a/arch/openrisc/cpu/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cache.o cpu.o exceptions.o interrupts.o
diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c
deleted file mode 100644
index fe5b704fb061..000000000000
--- a/arch/openrisc/cpu/cache.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-
-void flush_dcache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_DCBFR, addr);
- addr += block_size;
- }
-}
-
-void invalidate_dcache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_DCBIR, addr);
- addr += block_size;
- }
-}
-
-static void invalidate_icache_range(unsigned long addr, unsigned long stop)
-{
- ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
-
- while (addr < stop) {
- mtspr(SPR_ICBIR, addr);
- addr += block_size;
- }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- flush_dcache_range(addr, addr + size);
- invalidate_icache_range(addr, addr + size);
-}
-
-int icache_status(void)
-{
- return mfspr(SPR_SR) & SPR_SR_ICE;
-}
-
-int checkicache(void)
-{
- unsigned long iccfgr;
- unsigned long cache_set_size;
- unsigned long cache_ways;
- unsigned long cache_block_size;
-
- iccfgr = mfspr(SPR_ICCFGR);
- cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
-
- return cache_set_size * cache_ways * cache_block_size;
-}
-
-int dcache_status(void)
-{
- return mfspr(SPR_SR) & SPR_SR_DCE;
-}
-
-int checkdcache(void)
-{
- unsigned long dccfgr;
- unsigned long cache_set_size;
- unsigned long cache_ways;
- unsigned long cache_block_size;
-
- dccfgr = mfspr(SPR_DCCFGR);
- cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
-
- return cache_set_size * cache_ways * cache_block_size;
-}
-
-void dcache_enable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
-}
-
-void dcache_disable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
-}
-
-void icache_enable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
- asm volatile("l.nop");
-}
-
-void icache_disable(void)
-{
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
-}
-
-int cache_init(void)
-{
- if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
- icache_disable();
- invalidate_icache_range(0, checkicache());
- icache_enable();
- }
-
- if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
- dcache_disable();
- invalidate_dcache_range(0, checkdcache());
- dcache_enable();
- }
-
- return 0;
-}
diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c
deleted file mode 100644
index 272656a361d7..000000000000
--- a/arch/openrisc/cpu/cpu.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static volatile int illegal_instruction;
-
-static void illegal_instruction_handler(void)
-{
- ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
-
- /* skip over the illegal instruction */
- mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
- illegal_instruction = 1;
-}
-
-static void checkinstructions(void)
-{
- ulong ra = 1, rb = 1, rc;
-
- exception_install_handler(EXC_ILLEGAL_INSTR,
- illegal_instruction_handler);
-
- illegal_instruction = 0;
- asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
- printf(" Hardware multiplier: %s\n",
- illegal_instruction ? "no" : "yes");
-
- illegal_instruction = 0;
- asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
- printf(" Hardware divider: %s\n",
- illegal_instruction ? "no" : "yes");
-
- exception_free_handler(EXC_ILLEGAL_INSTR);
-}
-
-int checkcpu(void)
-{
- ulong upr = mfspr(SPR_UPR);
- ulong vr = mfspr(SPR_VR);
- ulong iccfgr = mfspr(SPR_ICCFGR);
- ulong dccfgr = mfspr(SPR_DCCFGR);
- ulong immucfgr = mfspr(SPR_IMMUCFGR);
- ulong dmmucfgr = mfspr(SPR_DMMUCFGR);
- ulong cpucfgr = mfspr(SPR_CPUCFGR);
- uint ver = (vr & SPR_VR_VER) >> 24;
- uint rev = vr & SPR_VR_REV;
- uint block_size;
- uint ways;
- uint sets;
-
- printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n",
- ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
-
- if (upr & SPR_UPR_DCP) {
- block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
- ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
- printf(" D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
- checkdcache(), block_size, ways);
- } else {
- printf(" D-Cache: no\n");
- }
-
- if (upr & SPR_UPR_ICP) {
- block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
- ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
- printf(" I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
- checkicache(), block_size, ways);
- } else {
- printf(" I-Cache: no\n");
- }
-
- if (upr & SPR_UPR_DMP) {
- sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
- ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
- printf(" DMMU: %d sets, %d way(s)\n",
- sets, ways);
- } else {
- printf(" DMMU: no\n");
- }
-
- if (upr & SPR_UPR_IMP) {
- sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
- ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
- printf(" IMMU: %d sets, %d way(s)\n",
- sets, ways);
- } else {
- printf(" IMMU: no\n");
- }
-
- printf(" MAC unit: %s\n",
- (upr & SPR_UPR_MP) ? "yes" : "no");
- printf(" Debug unit: %s\n",
- (upr & SPR_UPR_DUP) ? "yes" : "no");
- printf(" Performance counters: %s\n",
- (upr & SPR_UPR_PCUP) ? "yes" : "no");
- printf(" Power management: %s\n",
- (upr & SPR_UPR_PMP) ? "yes" : "no");
- printf(" Interrupt controller: %s\n",
- (upr & SPR_UPR_PICP) ? "yes" : "no");
- printf(" Timer: %s\n",
- (upr & SPR_UPR_TTP) ? "yes" : "no");
- printf(" Custom unit(s): %s\n",
- (upr & SPR_UPR_CUP) ? "yes" : "no");
-
- printf(" Supported instructions:\n");
- printf(" ORBIS32: %s\n",
- (cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
- printf(" ORBIS64: %s\n",
- (cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
- printf(" ORFPX32: %s\n",
- (cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
- printf(" ORFPX64: %s\n",
- (cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
-
- checkinstructions();
-
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-extern void __reset(void);
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- /* Code the jump to __reset here as the compiler is prone to
- emitting a bad jump instruction if the function is in flash */
- __asm__("l.movhi r1,hi(__reset); \
- l.ori r1,r1,lo(__reset); \
- l.jr r1");
- /* not reached, __reset does not return */
- return 0;
-}
diff --git a/arch/openrisc/cpu/exceptions.c b/arch/openrisc/cpu/exceptions.c
deleted file mode 100644
index b33999748796..000000000000
--- a/arch/openrisc/cpu/exceptions.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <asm/system.h>
-
-static const char * const excp_table[] = {
- "Unknown exception",
- "Reset",
- "Bus Error",
- "Data Page Fault",
- "Instruction Page Fault",
- "Tick Timer",
- "Alignment",
- "Illegal Instruction",
- "External Interrupt",
- "D-TLB Miss",
- "I-TLB Miss",
- "Range",
- "System Call",
- "Floating Point",
- "Trap",
-};
-
-static void (*handlers[32])(void);
-
-void exception_install_handler(int exception, void (*handler)(void))
-{
- if (exception < 0 || exception > 31)
- return;
-
- handlers[exception] = handler;
-}
-
-void exception_free_handler(int exception)
-{
- if (exception < 0 || exception > 31)
- return;
-
- handlers[exception] = 0;
-}
-
-static void exception_hang(int vect)
-{
- printf("Unhandled exception at 0x%x ", vect & 0xff00);
-
- vect = ((vect >> 8) & 0xff);
- if (vect < ARRAY_SIZE(excp_table))
- printf("(%s)\n", excp_table[vect]);
- else
- printf("(%s)\n", excp_table[0]);
-
- printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE));
- printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE));
- printf("ESR: 0x%08lx\n", mfspr(SPR_ESR_BASE));
- hang();
-}
-
-void exception_handler(int vect)
-{
- int exception = vect >> 8;
-
- if (handlers[exception])
- handlers[exception]();
- else
- exception_hang(vect);
-}
diff --git a/arch/openrisc/cpu/interrupts.c b/arch/openrisc/cpu/interrupts.c
deleted file mode 100644
index 1ecfbf03ac08..000000000000
--- a/arch/openrisc/cpu/interrupts.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
-};
-
-static struct irq_action handlers[32];
-
-void interrupt_handler(void)
-{
- int irq;
-
- while ((irq = ffs(mfspr(SPR_PICSR)))) {
- if (handlers[--irq].handler) {
- handlers[irq].handler(handlers[irq].arg);
- handlers[irq].count++;
- } else {
- /* disable the interrupt */
- mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1 << irq));
- printf("Unhandled interrupt: %d\n", irq);
- }
- /* clear the interrupt */
- mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1 << irq));
- }
-}
-
-int interrupt_init(void)
-{
- /* install handler for external interrupt exception */
- exception_install_handler(EXC_EXT_IRQ, interrupt_handler);
- /* Enable interrupts in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
-
- return 0;
-}
-
-void enable_interrupts(void)
-{
- /* Set interrupt enable bit in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
- /* Enable timer exception */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-}
-
-int disable_interrupts(void)
-{
- /* Clear interrupt enable bit in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
- /* Disable timer exception */
- mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
-
- return 0;
-}
-
-void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
-{
- if (irq < 0 || irq > 31)
- return;
-
- handlers[irq].handler = handler;
- handlers[irq].arg = arg;
-}
-
-void irq_free_handler(int irq)
-{
- if (irq < 0 || irq > 31)
- return;
-
- handlers[irq].handler = 0;
- handlers[irq].arg = 0;
-}
-
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
-
- printf("\nInterrupt-Information:\n\n");
- printf("Nr Routine Arg Count\n");
- printf("-----------------------------\n");
-
- for (i = 0; i < 32; i++) {
- if (handlers[i].handler) {
- printf("%02d %08lx %08lx %d\n",
- i,
- (ulong)handlers[i].handler,
- (ulong)handlers[i].arg,
- handlers[i].count);
- }
- }
- printf("\n");
-
- return 0;
-}
-#endif
diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S
deleted file mode 100644
index 1ae3b75f3be0..000000000000
--- a/arch/openrisc/cpu/start.S
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm-offsets.h>
-#include <asm/spr-defs.h>
-
-#define EXCEPTION_STACK_SIZE (128+128)
-
-#define HANDLE_EXCEPTION \
- l.addi r1, r1, -EXCEPTION_STACK_SIZE ;\
- l.sw 0x00(r1), r2 ;\
- l.sw 0x1c(r1), r9 ;\
- l.movhi r2,hi(_exception_handler) ;\
- l.ori r2,r2,lo(_exception_handler) ;\
- l.jalr r2 ;\
- l.nop ;\
- l.lwz r9, 0x1c(r1) ;\
- l.addi r1, r1, EXCEPTION_STACK_SIZE ;\
- l.rfe ;\
- l.nop
-
- .section .vectors, "ax"
- .global __reset
-
- /* reset */
- .org 0x100
-__reset:
- /* there is no guarantee r0 is hardwired to zero, clear it here */
- l.andi r0, r0, 0
- /* reset stack and frame pointers */
- l.andi r1, r0, 0
- l.andi r2, r0, 0
-
- /* set supervisor mode */
- l.ori r3,r0,SPR_SR_SM
- l.mtspr r0,r3,SPR_SR
-
- l.jal _cur
- l.nop
-_cur:
- l.ori r8, r9, 0 /* Get _cur current address */
-
- l.movhi r3, hi(_cur)
- l.ori r3, r3, lo(_cur)
- l.sfeq r8, r3 /* If we are running at the linked address */
- l.bf _no_vector_reloc /* there is not need for relocation */
- l.sub r8, r8, r3
-
- l.mfspr r4, r0, SPR_CPUCFGR
- l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */
- l.sfnei r4,0
- l.bnf _reloc_vectors
- l.movhi r5, 0 /* Destination */
-
- l.mfspr r4, r0, SPR_EVBAR
- l.add r5, r5, r4
-
-_reloc_vectors:
- /* Relocate vectors*/
- l.movhi r5, 0 /* Destination */
- l.movhi r6, hi(__start) /* Length */
- l.ori r6, r6, lo(__start)
- l.ori r3, r8, 0
-
-.L_relocvectors:
- l.lwz r7, 0(r3)
- l.sw 0(r5), r7
- l.addi r5, r5, 4
- l.sfeq r5, r6
- l.bnf .L_relocvectors
- l.addi r3, r3, 4
-
-_no_vector_reloc:
-
- /* Relocate u-boot */
- l.movhi r3,hi(__start) /* source start offset */
- l.ori r3,r3,lo(__start)
- l.add r3,r8,r3
-
- l.movhi r4,hi(_stext) /* dest start address */
- l.ori r4,r4,lo(_stext)
- l.movhi r5,hi(__end) /* dest end address */
- l.ori r5,r5,lo(__end)
-
-.L_reloc:
- l.lwz r6,0(r3)
- l.sw 0(r4),r6
- l.addi r3,r3,4
- l.sfltu r4,r5
- l.bf .L_reloc
- l.addi r4,r4,4 /* delay slot */
-
- l.movhi r4,hi(_start)
- l.ori r4,r4,lo(_start)
- l.jr r4
- l.nop
-
- /* bus error */
- .org 0x200
- HANDLE_EXCEPTION
-
- /* data page fault */
- .org 0x300
- HANDLE_EXCEPTION
-
- /* instruction page fault */
- .org 0x400
- HANDLE_EXCEPTION
-
- /* tick timer */
- .org 0x500
- HANDLE_EXCEPTION
-
- /* alignment */
- .org 0x600
- HANDLE_EXCEPTION
-
- /* illegal instruction */
- .org 0x700
- HANDLE_EXCEPTION
-
- /* external interrupt */
- .org 0x800
- HANDLE_EXCEPTION
-
- /* D-TLB miss */
- .org 0x900
- HANDLE_EXCEPTION
-
- /* I-TLB miss */
- .org 0xa00
- HANDLE_EXCEPTION
-
- /* range */
- .org 0xb00
- HANDLE_EXCEPTION
-
- /* system call */
- .org 0xc00
- HANDLE_EXCEPTION
-
- /* floating point */
- .org 0xd00
- HANDLE_EXCEPTION
-
- /* trap */
- .org 0xe00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0xf00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1100
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1200
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1300
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1400
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1500
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1600
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1700
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1800
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1900
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1a00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1b00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1c00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1d00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1e00
- HANDLE_EXCEPTION
-
- /* reserved */
- .org 0x1f00
- HANDLE_EXCEPTION
-
- /* Startup routine */
- .text
- .global _start
-_start:
- /* Init stack and frame pointers */
- l.movhi r1, hi(CONFIG_SYS_INIT_SP_ADDR)
- l.ori r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
- l.or r2, r0, r1
-
- /* clear BSS segments */
- l.movhi r4, hi(_bss_start)
- l.ori r4, r4, lo(_bss_start)
- l.movhi r5, hi(_bss_end)
- l.ori r5, r5, lo(_bss_end)
-.L_clear_bss:
- l.sw 0(r4), r0
- l.sfltu r4,r5
- l.bf .L_clear_bss
- l.addi r4,r4,4
-
- /* Reset registers before jumping to board_init */
- l.andi r3, r0, 0
- l.andi r4, r0, 0
- l.andi r5, r0, 0
- l.andi r6, r0, 0
- l.andi r7, r0, 0
- l.andi r8, r0, 0
- l.andi r9, r0, 0
- l.andi r10, r0, 0
- l.andi r11, r0, 0
- l.andi r12, r0, 0
- l.andi r13, r0, 0
- l.andi r14, r0, 0
- l.andi r15, r0, 0
- l.andi r17, r0, 0
- l.andi r18, r0, 0
- l.andi r19, r0, 0
- l.andi r20, r0, 0
- l.andi r21, r0, 0
- l.andi r22, r0, 0
- l.andi r23, r0, 0
- l.andi r24, r0, 0
- l.andi r25, r0, 0
- l.andi r26, r0, 0
- l.andi r27, r0, 0
- l.andi r28, r0, 0
- l.andi r29, r0, 0
- l.andi r30, r0, 0
- l.andi r31, r0, 0
-
- l.j board_init
- l.nop
-
- .size _start, .-_start
-
-/*
- * Store state onto stack and call the real exception handler
- */
- .section .text
- .extern exception_handler
- .type _exception_handler, at function
-
-_exception_handler:
- /* Store state (r2 and r9 already saved)*/
- l.sw 0x04(r1), r3
- l.sw 0x08(r1), r4
- l.sw 0x0c(r1), r5
- l.sw 0x10(r1), r6
- l.sw 0x14(r1), r7
- l.sw 0x18(r1), r8
- l.sw 0x20(r1), r10
- l.sw 0x24(r1), r11
- l.sw 0x28(r1), r12
- l.sw 0x2c(r1), r13
- l.sw 0x30(r1), r14
- l.sw 0x34(r1), r15
- l.sw 0x38(r1), r16
- l.sw 0x3c(r1), r17
- l.sw 0x40(r1), r18
- l.sw 0x44(r1), r19
- l.sw 0x48(r1), r20
- l.sw 0x4c(r1), r21
- l.sw 0x50(r1), r22
- l.sw 0x54(r1), r23
- l.sw 0x58(r1), r24
- l.sw 0x5c(r1), r25
- l.sw 0x60(r1), r26
- l.sw 0x64(r1), r27
- l.sw 0x68(r1), r28
- l.sw 0x6c(r1), r29
- l.sw 0x70(r1), r30
- l.sw 0x74(r1), r31
-
- /* Save return address */
- l.or r14, r0, r9
- /* Call exception handler with the link address as argument */
- l.jal exception_handler
- l.or r3, r0, r14
- /* Load return address */
- l.or r9, r0, r14
-
- /* Restore state */
- l.lwz r2, 0x00(r1)
- l.lwz r3, 0x04(r1)
- l.lwz r4, 0x08(r1)
- l.lwz r5, 0x0c(r1)
- l.lwz r6, 0x10(r1)
- l.lwz r7, 0x14(r1)
- l.lwz r8, 0x18(r1)
- l.lwz r10, 0x20(r1)
- l.lwz r11, 0x24(r1)
- l.lwz r12, 0x28(r1)
- l.lwz r13, 0x2c(r1)
- l.lwz r14, 0x30(r1)
- l.lwz r15, 0x34(r1)
- l.lwz r16, 0x38(r1)
- l.lwz r17, 0x3c(r1)
- l.lwz r18, 0x40(r1)
- l.lwz r19, 0x44(r1)
- l.lwz r20, 0x48(r1)
- l.lwz r21, 0x4c(r1)
- l.lwz r22, 0x50(r1)
- l.lwz r23, 0x54(r1)
- l.lwz r24, 0x58(r1)
- l.lwz r25, 0x5c(r1)
- l.lwz r26, 0x60(r1)
- l.lwz r27, 0x64(r1)
- l.lwz r28, 0x68(r1)
- l.lwz r29, 0x6c(r1)
- l.lwz r30, 0x70(r1)
- l.lwz r31, 0x74(r1)
- l.jr r9
- l.nop
diff --git a/arch/openrisc/cpu/u-boot.lds b/arch/openrisc/cpu/u-boot.lds
deleted file mode 100644
index 854088b880a2..000000000000
--- a/arch/openrisc/cpu/u-boot.lds
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <config.h>
-OUTPUT_ARCH(or1k)
-__DYNAMIC = 0;
-
-MEMORY
-{
- vectors : ORIGIN = 0, LENGTH = 0x2000
- ram : ORIGIN = CONFIG_SYS_MONITOR_BASE,
- LENGTH = CONFIG_SYS_MONITOR_LEN
-}
-
-SECTIONS
-{
- .vectors :
- {
- *(.vectors)
- } > vectors
-
- __start = .;
- .text : AT (__start) {
- _stext = .;
- *(.text)
- _etext = .;
- *(.lit)
- *(.shdata)
- _endtext = .;
- } > ram
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- } > ram
-
- .rodata : {
- *(.rodata);
- *(.rodata.*)
- } > ram
-
- .shbss :
- {
- *(.shbss)
- } > ram
-
- .talias :
- {
- } > ram
-
- .data : {
- sdata = .;
- _sdata = .;
- *(.data)
- edata = .;
- _edata = .;
- } > ram
-
- .bss :
- {
- _bss_start = .;
- *(.bss)
- *(COMMON)
- _bss_end = .;
- } > ram
- __end = .;
-
- /* No stack specification - done manually */
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h
deleted file mode 100644
index 28c4658672a2..000000000000
--- a/arch/openrisc/include/asm/bitops.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_BITOPS_H
-#define __ASM_OPENRISC_BITOPS_H
-
-#define PLATFORM_FLS
-#include <asm/bitops/fls.h>
-#define PLATFORM_FFS
-#include <asm/bitops/ffs.h>
-
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#endif /* __ASM_GENERIC_BITOPS_H */
diff --git a/arch/openrisc/include/asm/bitops/ffs.h b/arch/openrisc/include/asm/bitops/ffs.h
deleted file mode 100644
index 50746cfa0b84..000000000000
--- a/arch/openrisc/include/asm/bitops/ffs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FFS_H
-#define __ASM_OPENRISC_FFS_H
-
-static inline int ffs(int x)
-{
- int ret;
-
- __asm__ ("l.ff1 %0,%1"
- : "=r" (ret)
- : "r" (x));
-
- return ret;
-}
-
-#endif /* __ASM_OPENRISC_FFS_H */
diff --git a/arch/openrisc/include/asm/bitops/fls.h b/arch/openrisc/include/asm/bitops/fls.h
deleted file mode 100644
index 74472299c523..000000000000
--- a/arch/openrisc/include/asm/bitops/fls.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_FLS_H
-#define __ASM_OPENRISC_FLS_H
-
-static inline int fls(int x)
-{
- int ret;
-
- __asm__ ("l.fl1 %0,%1"
- : "=r" (ret)
- : "r" (x));
-
- return ret;
-}
-
-#endif /* __ASM_OPENRISC_FLS_H */
diff --git a/arch/openrisc/include/asm/byteorder.h b/arch/openrisc/include/asm/byteorder.h
deleted file mode 100644
index 60d14f7e14e2..000000000000
--- a/arch/openrisc/include/asm/byteorder.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <linux/byteorder/big_endian.h>
diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h
deleted file mode 100644
index 22d43703f427..000000000000
--- a/arch/openrisc/include/asm/cache.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_CACHE_H_
-#define __ASM_OPENRISC_CACHE_H_
-
-/*
- * Valid L1 data cache line sizes for the OpenRISC architecture are
- * 16 and 32 bytes.
- * If the board configuration has not specified one we default to the
- * largest of these values for alignment of DMA buffers.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 32
-#endif
-
-#endif /* __ASM_OPENRISC_CACHE_H_ */
diff --git a/arch/openrisc/include/asm/config.h b/arch/openrisc/include/asm/config.h
deleted file mode 100644
index cd2973478944..000000000000
--- a/arch/openrisc/include/asm/config.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#endif
diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h
deleted file mode 100644
index 428ce1b4debd..000000000000
--- a/arch/openrisc/include/asm/global_data.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-/* Architecture-specific global data */
-struct arch_global_data {
-};
-
-#include <asm-generic/global_data.h>
-
-/* OR32 GCC already has r10 set as fixed-use */
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r10")
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h
deleted file mode 100644
index c57a430275a3..000000000000
--- a/arch/openrisc/include/asm/gpio.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * OpenRISC gpio driver
- *
- * Copyright (C) 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * based on nios2 gpio driver
- * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
- *
- * when CONFIG_SYS_GPIO_BASE is not defined, board may provide
- * its own driver.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef CONFIG_SYS_GPIO_BASE
-#include <asm/io.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
-static inline int gpio_free(unsigned gpio)
-{
- return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return (readb(CONFIG_SYS_GPIO_BASE + gpio/8) >> gpio%8) & 0x1;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- u8 tmp = readb(CONFIG_SYS_GPIO_BASE + gpio/8);
-
- if (value)
- tmp |= (1 << gpio%8);
- else
- tmp &= ~(1 << gpio%8);
- writeb(tmp, CONFIG_SYS_GPIO_BASE + gpio/8);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 0);
-
- return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 1);
- gpio_set_value(gpio, value);
-
- return 0;
-}
-
-static inline int gpio_is_valid(int number)
-{
- return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
-}
-#else
-extern int gpio_request(unsigned gpio, const char *label);
-extern int gpio_free(unsigned gpio);
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-extern int gpio_get_value(unsigned gpio);
-extern void gpio_set_value(unsigned gpio, int value);
-extern int gpio_is_valid(int number);
-#endif /* CONFIG_SYS_GPIO_BASE */
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
deleted file mode 100644
index 86fbbc46d35f..000000000000
--- a/arch/openrisc/include/asm/io.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_IO_H
-#define __ASM_OPENRISC_IO_H
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE (0)
-#define MAP_WRCOMBINE (0)
-#define MAP_WRBACK (0)
-#define MAP_WRTHROUGH (0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
- return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-/*
- * Change virtual addresses to physical addresses
- */
-static inline phys_addr_t virt_to_phys(void *vaddr)
-{
- return (phys_addr_t)(vaddr);
-}
-
-
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the openrisc architecture, we just read/write the
- * memory location directly.
- */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-
-#define writeb(b, addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b))
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define memset_io(a, b, c) memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
-
-/*
- * Again, OpenRISC does not require mem IO specific function.
- */
-
-
-#define IO_BASE 0x0
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define inb(port) readb((port + IO_BASE))
-#define outb(value, port) writeb((value), (port + IO_BASE))
-#define inb_p(port) inb((port))
-#define outb_p(value, port) outb((value), (port))
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#define ioread8(addr) readb(addr)
-#define ioread16(addr) readw(addr)
-#define ioread32(addr) readl(addr)
-
-#define iowrite8(v, addr) writeb((v), (addr))
-#define iowrite16(v, addr) writew((v), (addr))
-#define iowrite32(v, addr) writel((v), (addr))
-
-#endif
diff --git a/arch/openrisc/include/asm/linkage.h b/arch/openrisc/include/asm/linkage.h
deleted file mode 100644
index e69de29bb2d1..000000000000
diff --git a/arch/openrisc/include/asm/openrisc_exc.h b/arch/openrisc/include/asm/openrisc_exc.h
deleted file mode 100644
index a53ed826ddc9..000000000000
--- a/arch/openrisc/include/asm/openrisc_exc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _OPENRISC_EXC_H_
-#define _OPENRISC_EXC_H_
-
-#define EXC_RESET 0x01
-#define EXC_BUS_ERROR 0x02
-#define EXC_DATA_PAGE_FAULT 0x03
-#define EXC_INSTR_PAGE_FAULT 0x04
-#define EXC_TIMER 0x05
-#define EXC_ALIGNMENT 0x06
-#define EXC_ILLEGAL_INSTR 0x07
-#define EXC_EXT_IRQ 0x08
-#define EXC_DTLB_MISS 0x09
-#define EXC_ITLB_MISS 0x0a
-#define EXC_RANGE 0x0b
-#define EXC_SYSCALL 0x0c
-#define EXC_FLOAT_POINT 0x0d
-#define EXC_TRAP 0x0e
-
-void exception_install_handler(int exception, void (*handler)(void));
-void exception_free_handler(int exception);
-
-#endif
diff --git a/arch/openrisc/include/asm/posix_types.h b/arch/openrisc/include/asm/posix_types.h
deleted file mode 100644
index d1fffe0374b9..000000000000
--- a/arch/openrisc/include/asm/posix_types.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Based on microblaze implementation:
- * Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
- * Copyright (C) 2001,2002 NEC Corporation
- * Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file COPYING in the main directory of this
- * archive for more details.
- *
- * Written by Miles Bader <miles@gnu.org>
- * Microblaze port by John Williams
- */
-
-#ifndef __ASM_OPENRISC_POSIX_TYPES_H
-#define __ASM_OPENRISC_POSIX_TYPES_H
-
-typedef unsigned int __kernel_dev_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned long long __kernel_ino64_t;
-typedef unsigned int __kernel_mode_t;
-typedef unsigned int __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef long long __kernel_loff_t;
-typedef int __kernel_pid_t;
-typedef unsigned short __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
- int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef __FD_SET
-#define __FD_SET(fd, fd_set) \
- __set_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_CLR
-#define __FD_CLR(fd, fd_set) \
- __clear_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ISSET
-#define __FD_ISSET(fd, fd_set) \
- __test_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
-#undef __FD_ZERO
-#define __FD_ZERO(fd_set) \
- memset(fd_set, 0, sizeof(*(fd_set *)fd_set))
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-
-#endif /* __ASM_OPENRISC_POSIX_TYPES_H */
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
deleted file mode 100644
index 304c95fb3a69..000000000000
--- a/arch/openrisc/include/asm/processor.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_OPENRISC_PROCESSOR_H
-#define __ASM_OPENRISC_PROCESSOR_H
-
-#endif
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
deleted file mode 100644
index 6608d8a6ea32..000000000000
--- a/arch/openrisc/include/asm/ptrace.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * OpenRISC Linux
- *
- * Linux architectural port borrowing liberally from similar works of
- * others. All original copyrights apply as per the original source
- * declaration.
- *
- * OpenRISC implementation:
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_PTRACE_H
-#define __ASM_OPENRISC_PTRACE_H
-
-#include <asm/spr-defs.h>
-
-#ifndef __ASSEMBLY__
-/*
- * This is the layout of the regset returned by the GETREGSET ptrace call
- */
-struct user_regs_struct {
- /* GPR R0-R31... */
- unsigned long gpr[32];
- unsigned long pc;
- unsigned long sr;
- unsigned long pad1;
- unsigned long pad2;
-};
-#endif
-
-#ifdef __KERNEL__
-
-/*
- * Make kernel PTrace/register structures opaque to userspace... userspace can
- * access thread state via the regset mechanism. This allows us a bit of
- * flexibility in how we order the registers on the stack, permitting some
- * optimizations like packing call-clobbered registers together so that
- * they share a cacheline (not done yet, though... future optimization).
- */
-
-#ifndef __ASSEMBLY__
-/*
- * This struct describes how the registers are laid out on the kernel stack
- * during a syscall or other kernel entry.
- *
- * This structure should always be cacheline aligned on the stack.
- * FIXME: I don't think that's the case right now. The alignment is
- * taken care of elsewhere... head.S, process.c, etc.
- */
-
-struct pt_regs {
- union {
- struct {
- /* Named registers */
- long sr; /* Stored in place of r0 */
- long sp; /* r1 */
- };
- struct {
- /* Old style */
- long offset[2];
- long gprs[30];
- };
- struct {
- /* New style */
- long gpr[32];
- };
- };
- long pc;
- long orig_gpr11; /* For restarting system calls */
- long syscallno; /* Syscall number (used by strace) */
- long dummy; /* Cheap alignment fix */
-};
-#endif /* __ASSEMBLY__ */
-
-/* TODO: Rename this to REDZONE because that's what it is */
-#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */
-
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0)
-#define user_stack_pointer(regs) ((unsigned long)(regs)->sp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-#define PT_SR 0
-#define PT_SP 4
-#define PT_GPR2 8
-#define PT_GPR3 12
-#define PT_GPR4 16
-#define PT_GPR5 20
-#define PT_GPR6 24
-#define PT_GPR7 28
-#define PT_GPR8 32
-#define PT_GPR9 36
-#define PT_GPR10 40
-#define PT_GPR11 44
-#define PT_GPR12 48
-#define PT_GPR13 52
-#define PT_GPR14 56
-#define PT_GPR15 60
-#define PT_GPR16 64
-#define PT_GPR17 68
-#define PT_GPR18 72
-#define PT_GPR19 76
-#define PT_GPR20 80
-#define PT_GPR21 84
-#define PT_GPR22 88
-#define PT_GPR23 92
-#define PT_GPR24 96
-#define PT_GPR25 100
-#define PT_GPR26 104
-#define PT_GPR27 108
-#define PT_GPR28 112
-#define PT_GPR29 116
-#define PT_GPR30 120
-#define PT_GPR31 124
-#define PT_PC 128
-#define PT_ORIG_GPR11 132
-#define PT_SYSCALLNO 136
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_OPENRISC_PTRACE_H */
diff --git a/arch/openrisc/include/asm/sections.h b/arch/openrisc/include/asm/sections.h
deleted file mode 100644
index bbe20f738421..000000000000
--- a/arch/openrisc/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SECTIONS_H
-#define __ASM_OPENRISC_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h
deleted file mode 100644
index e30d2104a028..000000000000
--- a/arch/openrisc/include/asm/spr-defs.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/*
- * SPR Definitions
- *
- * Copyright (C) 2000 Damjan Lampret
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2008, 2010 Embecosm Limited
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- * et al.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * This file is part of OpenRISC 1000 Architectural Simulator.
- */
-
-#ifndef SPR_DEFS__H
-#define SPR_DEFS__H
-
-/* Definition of special-purpose registers (SPRs) */
-
-#define MAX_GRPS (32)
-#define MAX_SPRS_PER_GRP_BITS (11)
-#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
-#define MAX_SPRS (0x10000)
-
-/* Base addresses for the groups */
-#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)
-#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)
-
-/* System control and status group */
-#define SPR_VR (SPRGROUP_SYS + 0)
-#define SPR_UPR (SPRGROUP_SYS + 1)
-#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
-#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
-#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
-#define SPR_DCCFGR (SPRGROUP_SYS + 5)
-#define SPR_ICCFGR (SPRGROUP_SYS + 6)
-#define SPR_DCFGR (SPRGROUP_SYS + 7)
-#define SPR_PCCFGR (SPRGROUP_SYS + 8)
-#define SPR_VR2 (SPRGROUP_SYS + 9)
-#define SPR_AVR (SPRGROUP_SYS + 10)
-#define SPR_EVBAR (SPRGROUP_SYS + 11)
-#define SPR_AECR (SPRGROUP_SYS + 12)
-#define SPR_AESR (SPRGROUP_SYS + 13)
-#define SPR_NPC (SPRGROUP_SYS + 16)
-#define SPR_SR (SPRGROUP_SYS + 17)
-#define SPR_PPC (SPRGROUP_SYS + 18)
-#define SPR_FPCSR (SPRGROUP_SYS + 20)
-#define SPR_EPCR_BASE (SPRGROUP_SYS + 32)
-#define SPR_EPCR_LAST (SPRGROUP_SYS + 47)
-#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
-#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
-#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
-#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
-#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
-
-/* Data MMU group */
-#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
-#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
-#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
-#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
-#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
-#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
-
-/* Instruction MMU group */
-#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
-#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
-#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
-#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
-#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
-#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
-
-/* Data cache group */
-#define SPR_DCCR (SPRGROUP_DC + 0)
-#define SPR_DCBPR (SPRGROUP_DC + 1)
-#define SPR_DCBFR (SPRGROUP_DC + 2)
-#define SPR_DCBIR (SPRGROUP_DC + 3)
-#define SPR_DCBWR (SPRGROUP_DC + 4)
-#define SPR_DCBLR (SPRGROUP_DC + 5)
-#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
-#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
-
-/* Instruction cache group */
-#define SPR_ICCR (SPRGROUP_IC + 0)
-#define SPR_ICBPR (SPRGROUP_IC + 1)
-#define SPR_ICBIR (SPRGROUP_IC + 2)
-#define SPR_ICBLR (SPRGROUP_IC + 3)
-#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
-#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
-
-/* MAC group */
-#define SPR_MACLO (SPRGROUP_MAC + 1)
-#define SPR_MACHI (SPRGROUP_MAC + 2)
-
-/* Debug group */
-#define SPR_DVR(N) (SPRGROUP_D + (N))
-#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
-#define SPR_DMR1 (SPRGROUP_D + 16)
-#define SPR_DMR2 (SPRGROUP_D + 17)
-#define SPR_DWCR0 (SPRGROUP_D + 18)
-#define SPR_DWCR1 (SPRGROUP_D + 19)
-#define SPR_DSR (SPRGROUP_D + 20)
-#define SPR_DRR (SPRGROUP_D + 21)
-
-/* Performance counters group */
-#define SPR_PCCR(N) (SPRGROUP_PC + (N))
-#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
-
-/* Power management group */
-#define SPR_PMR (SPRGROUP_PM + 0)
-
-/* PIC group */
-#define SPR_PICMR (SPRGROUP_PIC + 0)
-#define SPR_PICPR (SPRGROUP_PIC + 1)
-#define SPR_PICSR (SPRGROUP_PIC + 2)
-
-/* Tick Timer group */
-#define SPR_TTMR (SPRGROUP_TT + 0)
-#define SPR_TTCR (SPRGROUP_TT + 1)
-
-/*
- * Bit definitions for the Version Register
- */
-#define SPR_VR_VER 0xff000000 /* Processor version */
-#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
-#define SPR_VR_RES 0x0000ffc0 /* Reserved */
-#define SPR_VR_REV 0x0000003f /* Processor revision */
-
-#define SPR_VR_VER_OFF 24
-#define SPR_VR_CFG_OFF 16
-#define SPR_VR_REV_OFF 0
-
-/*
- * Bit definitions for the Unit Present Register
- */
-#define SPR_UPR_UP 0x00000001 /* UPR present */
-#define SPR_UPR_DCP 0x00000002 /* Data cache present */
-#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
-#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
-#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
-#define SPR_UPR_MP 0x00000020 /* MAC present */
-#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
-#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
-#define SPR_UPR_PMP 0x00000100 /* Power management present */
-#define SPR_UPR_PICP 0x00000200 /* PIC present */
-#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
-#define SPR_UPR_RES 0x00fe0000 /* Reserved */
-#define SPR_UPR_CUP 0xff000000 /* Context units present */
-
-/*
- * Bit definitions for the CPU configuration register
- */
-#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
-#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
-#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
-#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
-#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
-#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
-#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
-#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
-#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
-#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
-#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
- /* Arithmetic Exception Status Register (AESR) presents */
-#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
-
-/*
- * Bit definitions for the Debug configuration register and other
- * constants.
- */
-
-#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
-#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
-#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
-#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
-#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
-#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
-#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
-#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
-#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
-#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
-
-#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
- 2 == n ? SPR_DCFGR_NDP2 : \
- 3 == n ? SPR_DCFGR_NDP3 : \
- 4 == n ? SPR_DCFGR_NDP4 : \
- 5 == n ? SPR_DCFGR_NDP5 : \
- 6 == n ? SPR_DCFGR_NDP6 : \
- 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
-#define MAX_MATCHPOINTS 8
-#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
-
-/*
- * Bit definitions for the Supervision Register
- */
-#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
-#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
-#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
-#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
-#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
-#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
-#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
-#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
-#define SPR_SR_CE 0x00000100 /* CID Enable */
-#define SPR_SR_F 0x00000200 /* Condition Flag */
-#define SPR_SR_CY 0x00000400 /* Carry flag */
-#define SPR_SR_OV 0x00000800 /* Overflow flag */
-#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
-#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
-#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
-#define SPR_SR_FO 0x00008000 /* Fixed one */
-#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
-#define SPR_SR_RES 0x0ffe0000 /* Reserved */
-#define SPR_SR_CID 0xf0000000 /* Context ID */
-
-/*
- * Bit definitions for the Data MMU Control Register
- */
-#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
-#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
-#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
-#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Instruction MMU Control Register
- */
-#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
-#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
-#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
-#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
-
-/*
- * Bit definitions for the Data TLB Match Register
- */
-#define SPR_DTLBMR_V 0x00000001 /* Valid */
-#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
-#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
-#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Data TLB Translate Register
- */
-#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
-#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
-#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
-#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
-#define SPR_DTLBTR_A 0x00000010 /* Accessed */
-#define SPR_DTLBTR_D 0x00000020 /* Dirty */
-#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
-#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
-#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
-#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
-#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Match Register
- */
-#define SPR_ITLBMR_V 0x00000001 /* Valid */
-#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
-#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
-#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
-#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
-
-/*
- * Bit definitions for the Instruction TLB Translate Register
- */
-#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
-#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
-#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
-#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
-#define SPR_ITLBTR_A 0x00000010 /* Accessed */
-#define SPR_ITLBTR_D 0x00000020 /* Dirty */
-#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
-#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
-#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
-
-/*
- * Bit definitions for Data Cache Control register
- */
-#define SPR_DCCR_EW 0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Insn Cache Control register
- */
-#define SPR_ICCR_EW 0x000000ff /* Enable ways */
-
-/*
- * Bit definitions for Data Cache Configuration Register
- */
-
-#define SPR_DCCFGR_NCW 0x00000007
-#define SPR_DCCFGR_NCS 0x00000078
-#define SPR_DCCFGR_CBS 0x00000080
-#define SPR_DCCFGR_CWS 0x00000100
-#define SPR_DCCFGR_CCRI 0x00000200
-#define SPR_DCCFGR_CBIRI 0x00000400
-#define SPR_DCCFGR_CBPRI 0x00000800
-#define SPR_DCCFGR_CBLRI 0x00001000
-#define SPR_DCCFGR_CBFRI 0x00002000
-#define SPR_DCCFGR_CBWBRI 0x00004000
-
-#define SPR_DCCFGR_NCW_OFF 0
-#define SPR_DCCFGR_NCS_OFF 3
-#define SPR_DCCFGR_CBS_OFF 7
-
-/*
- * Bit definitions for Instruction Cache Configuration Register
- */
-#define SPR_ICCFGR_NCW 0x00000007
-#define SPR_ICCFGR_NCS 0x00000078
-#define SPR_ICCFGR_CBS 0x00000080
-#define SPR_ICCFGR_CCRI 0x00000200
-#define SPR_ICCFGR_CBIRI 0x00000400
-#define SPR_ICCFGR_CBPRI 0x00000800
-#define SPR_ICCFGR_CBLRI 0x00001000
-
-#define SPR_ICCFGR_NCW_OFF 0
-#define SPR_ICCFGR_NCS_OFF 3
-#define SPR_ICCFGR_CBS_OFF 7
-
-/*
- * Bit definitions for Data MMU Configuration Register
- */
-#define SPR_DMMUCFGR_NTW 0x00000003
-#define SPR_DMMUCFGR_NTS 0x0000001C
-#define SPR_DMMUCFGR_NAE 0x000000E0
-#define SPR_DMMUCFGR_CRI 0x00000100
-#define SPR_DMMUCFGR_PRI 0x00000200
-#define SPR_DMMUCFGR_TEIRI 0x00000400
-#define SPR_DMMUCFGR_HTR 0x00000800
-
-#define SPR_DMMUCFGR_NTW_OFF 0
-#define SPR_DMMUCFGR_NTS_OFF 2
-
-/*
- * Bit definitions for Instruction MMU Configuration Register
- */
-#define SPR_IMMUCFGR_NTW 0x00000003
-#define SPR_IMMUCFGR_NTS 0x0000001C
-#define SPR_IMMUCFGR_NAE 0x000000E0
-#define SPR_IMMUCFGR_CRI 0x00000100
-#define SPR_IMMUCFGR_PRI 0x00000200
-#define SPR_IMMUCFGR_TEIRI 0x00000400
-#define SPR_IMMUCFGR_HTR 0x00000800
-
-#define SPR_IMMUCFGR_NTW_OFF 0
-#define SPR_IMMUCFGR_NTS_OFF 2
-
-/*
- * Bit definitions for Debug Control registers
- */
-#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
-#define SPR_DCR_CC 0x0000000e /* Compare condition */
-#define SPR_DCR_SC 0x00000010 /* Signed compare */
-#define SPR_DCR_CT 0x000000e0 /* Compare to */
-
-/* Bit results with SPR_DCR_CC mask */
-#define SPR_DCR_CC_MASKED 0x00000000
-#define SPR_DCR_CC_EQUAL 0x00000002
-#define SPR_DCR_CC_LESS 0x00000004
-#define SPR_DCR_CC_LESSE 0x00000006
-#define SPR_DCR_CC_GREAT 0x00000008
-#define SPR_DCR_CC_GREATE 0x0000000a
-#define SPR_DCR_CC_NEQUAL 0x0000000c
-
-/* Bit results with SPR_DCR_CT mask */
-#define SPR_DCR_CT_DISABLED 0x00000000
-#define SPR_DCR_CT_IFEA 0x00000020
-#define SPR_DCR_CT_LEA 0x00000040
-#define SPR_DCR_CT_SEA 0x00000060
-#define SPR_DCR_CT_LD 0x00000080
-#define SPR_DCR_CT_SD 0x000000a0
-#define SPR_DCR_CT_LSEA 0x000000c0
-#define SPR_DCR_CT_LSD 0x000000e0
-
-/*
- * Bit definitions for Debug Mode 1 register
- */
-#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
-#define SPR_DMR1_CW0_AND 0x00000001
-#define SPR_DMR1_CW0_OR 0x00000002
-#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
-#define SPR_DMR1_CW1_AND 0x00000004
-#define SPR_DMR1_CW1_OR 0x00000008
-#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
-#define SPR_DMR1_CW2_AND 0x00000010
-#define SPR_DMR1_CW2_OR 0x00000020
-#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
-#define SPR_DMR1_CW3_AND 0x00000040
-#define SPR_DMR1_CW3_OR 0x00000080
-#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
-#define SPR_DMR1_CW4_AND 0x00000100
-#define SPR_DMR1_CW4_OR 0x00000200
-#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
-#define SPR_DMR1_CW5_AND 0x00000400
-#define SPR_DMR1_CW5_OR 0x00000800
-#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
-#define SPR_DMR1_CW6_AND 0x00001000
-#define SPR_DMR1_CW6_OR 0x00002000
-#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
-#define SPR_DMR1_CW7_AND 0x00004000
-#define SPR_DMR1_CW7_OR 0x00008000
-#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
-#define SPR_DMR1_CW8_AND 0x00010000
-#define SPR_DMR1_CW8_OR 0x00020000
-#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
-#define SPR_DMR1_CW9_AND 0x00040000
-#define SPR_DMR1_CW9_OR 0x00080000
-#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
-#define SPR_DMR1_RES1 0x00300000 /* Reserved */
-#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
-#define SPR_DMR1_BT 0x00800000 /* Branch trace */
-#define SPR_DMR1_RES2 0xff000000 /* Reserved */
-
-/*
- * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
- */
-#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
-#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
-#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
-#define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */
-#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
-#define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */
-#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
-
-/*
- * Bit definitions for Debug watchpoint counter registers
- */
-#define SPR_DWCR_COUNT 0x0000ffff /* Count */
-#define SPR_DWCR_MATCH 0xffff0000 /* Match */
-#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
-
-/*
- * Bit definitions for Debug stop register
- *
- */
-#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
-#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
-#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
-#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
-#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
-#define SPR_DSR_AE 0x00000020 /* Alignment exception */
-#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
-#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
-#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
-#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
-#define SPR_DSR_RE 0x00000400 /* Range exception */
-#define SPR_DSR_SCE 0x00000800 /* System call exception */
-#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
-#define SPR_DSR_TE 0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Debug reason register
- */
-#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
-#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
-#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
-#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
-#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
-#define SPR_DRR_AE 0x00000020 /* Alignment exception */
-#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
-#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
-#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
-#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
-#define SPR_DRR_RE 0x00000400 /* Range exception */
-#define SPR_DRR_SCE 0x00000800 /* System call exception */
-#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
-#define SPR_DRR_TE 0x00002000 /* Trap exception */
-
-/*
- * Bit definitions for Performance counters mode registers
- */
-#define SPR_PCMR_CP 0x00000001 /* Counter present */
-#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
-#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
-#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
-#define SPR_PCMR_LA 0x00000010 /* Load access event */
-#define SPR_PCMR_SA 0x00000020 /* Store access event */
-#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
-#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
-#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
-#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
-#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
-#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
-#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
-#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
-#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
-#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
-
-/*
- * Bit definitions for the Power management register
- */
-#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
-#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
-#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
-#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
-#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
-
-/*
- * Bit definitions for PICMR
- */
-#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
-
-/*
- * Bit definitions for PICPR
- */
-#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
-
-/*
- * Bit definitions for PICSR
- */
-#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
-
-/*
- * Bit definitions for Tick Timer Control Register
- */
-#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
-#define SPR_TTMR_TP 0x0fffffff /* Time period */
-#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
-#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
-#define SPR_TTMR_DI 0x00000000 /* Disabled */
-#define SPR_TTMR_RT 0x40000000 /* Restart tick */
-#define SPR_TTMR_SR 0x80000000 /* Single run */
-#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
-#define SPR_TTMR_M 0xc0000000 /* Tick mode */
-
-/*
- * Bit definitions for the FP Control Status Register
- */
-#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
-#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
-#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
-#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
-#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
-#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
-#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
-#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
-#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
-#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
-#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
-#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
- SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
- SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
-
-#define FPCSR_RM_RN (0<<1)
-#define FPCSR_RM_RZ (1<<1)
-#define FPCSR_RM_RIP (2<<1)
-#define FPCSR_RM_RIN (3<<1)
-
-/*
- * l.nop constants
- */
-#define NOP_NOP 0x0000 /* Normal nop instruction */
-#define NOP_EXIT 0x0001 /* End of simulation */
-#define NOP_REPORT 0x0002 /* Simple report */
-#define NOP_PUTC 0x0004 /* Simputc instruction */
-#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
-#define NOP_GET_TICKS 0x0006 /* Get # ticks running */
-#define NOP_GET_PS 0x0007 /* Get picosecs/cycle */
-#define NOP_REPORT_FIRST 0x0400 /* Report with number */
-#define NOP_REPORT_LAST 0x03ff /* Report with number */
-
-#endif /* SPR_DEFS__H */
diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h
deleted file mode 100644
index 73e265564ae6..000000000000
--- a/arch/openrisc/include/asm/string.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_OPENRISC_STRING_H
-#define __ASM_OPENRISC_STRING_H
-
-#endif
diff --git a/arch/openrisc/include/asm/system.h b/arch/openrisc/include/asm/system.h
deleted file mode 100644
index 7adfd8809ccd..000000000000
--- a/arch/openrisc/include/asm/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_OPENRISC_SYSTEM_H
-#define __ASM_OPENRISC_SYSTEM_H
-
-#include <asm/spr-defs.h>
-
-static inline unsigned long mfspr(unsigned long add)
-{
- unsigned long ret;
-
- __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add));
-
- return ret;
-}
-
-static inline void mtspr(unsigned long add, unsigned long val)
-{
- __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val));
-}
-
-#endif /* __ASM_OPENRISC_SYSTEM_H */
diff --git a/arch/openrisc/include/asm/types.h b/arch/openrisc/include/asm/types.h
deleted file mode 100644
index 1fe00bf38aaf..000000000000
--- a/arch/openrisc/include/asm/types.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue. However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide. */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TYPES_H */
diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h
deleted file mode 100644
index cdb8ff996ed6..000000000000
--- a/arch/openrisc/include/asm/u-boot.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_
-
-typedef struct bd_info {
- unsigned long bi_arch_number; /* unique id for this board */
- unsigned long bi_boot_params; /* where this board expects params */
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
-} bd_t;
-
-#define IH_ARCH_DEFAULT IH_ARCH_OPENRISC
-
-#endif /* _U_BOOT_H_ */
diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb2111f..000000000000
--- a/arch/openrisc/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
deleted file mode 100644
index 3a2f6ec24374..000000000000
--- a/arch/openrisc/lib/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y += timer.o
diff --git a/arch/openrisc/lib/bootm.c b/arch/openrisc/lib/bootm.c
deleted file mode 100644
index a18748f61f91..000000000000
--- a/arch/openrisc/lib/bootm.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- *
- * Based on microblaze implementation by:
- * (C) Copyright 2007 Michal Simek
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Michal SIMEK <monstr@monstr.eu>
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*kernel) (unsigned int);
- ulong rd_data_start, rd_data_end;
-
- /*
- * allow the PREP bootm subcommand, it is required for bootm to work
- */
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
-
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- int ret;
-
- char *of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
- /* did generic code already find a device tree? */
- if (images->ft_len)
- of_flat_tree = images->ft_addr;
-#endif
-
- kernel = (void (*)(unsigned int))images->ep;
-
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_OPENRISC,
- &rd_data_start, &rd_data_end);
- if (ret)
- return 1;
-
- show_boot_progress(15);
-
- if (!of_flat_tree && argc > 1)
- of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-#ifdef DEBUG
- printf("## Transferring control to Linux (at address 0x%08lx) " \
- "ramdisk 0x%08lx, FDT 0x%08lx...\n",
- (ulong) kernel, rd_data_start, (ulong) of_flat_tree);
-#endif
- if (dcache_status() || icache_status())
- flush_cache((ulong)kernel, max(checkdcache(), checkicache()));
-
- /*
- * Linux Kernel Parameters (passing device tree):
- * r3: pointer to the fdt, followed by the board info data
- */
- kernel((unsigned int) of_flat_tree);
- /* does not return */
-
- return 1;
-}
diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c
deleted file mode 100644
index db8ddbdba54a..000000000000
--- a/arch/openrisc/lib/timer.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/system.h>
-#include <asm/openrisc_exc.h>
-
-static ulong timestamp;
-
-/* how many counter cycles in a jiffy */
-#define TIMER_COUNTER_CYCLES (CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many ms elapses between each timer interrupt */
-#define TIMER_TIMESTAMP_INC (1000/CONFIG_SYS_OPENRISC_TMR_HZ)
-/* how many cycles per ms */
-#define TIMER_CYCLES_MS (CONFIG_SYS_CLK_FREQ/1000)
-/* how many cycles per us */
-#define TIMER_CYCLES_US (CONFIG_SYS_CLK_FREQ/1000000uL)
-
-void timer_isr(void)
-{
- timestamp += TIMER_TIMESTAMP_INC;
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-int timer_init(void)
-{
- /* Install timer exception handler */
- exception_install_handler(EXC_TIMER, timer_isr);
-
- /* Set up the timer for the first expiration. */
- timestamp = 0;
-
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-
- /* Enable tick timer exception in supervisor register */
- mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
-
- return 0;
-}
-
-void reset_timer(void)
-{
- timestamp = 0;
-
- mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
- (TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
-}
-
-/*
- * The timer value in ms is calculated by taking the
- * value accumulated by full timer revolutions plus the value
- * accumulated in this period
- */
-ulong get_timer(ulong base)
-{
- return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
-}
-
-void set_timer(ulong t)
-{
- reset_timer();
- timestamp = t;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
-void __udelay(ulong usec)
-{
- ulong elapsed = 0;
- ulong tick;
- ulong last_tick;
-
- last_tick = mfspr(SPR_TTCR);
- while ((elapsed / TIMER_CYCLES_US) < usec) {
- tick = mfspr(SPR_TTCR);
- if (tick >= last_tick)
- elapsed += (tick - last_tick);
- else
- elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
- last_tick = tick;
- }
-}
diff --git a/board/openrisc/openrisc-generic/Kconfig b/board/openrisc/openrisc-generic/Kconfig
deleted file mode 100644
index cd2a94f025e7..000000000000
--- a/board/openrisc/openrisc-generic/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OPENRISC_GENERIC
-
-config SYS_BOARD
- default "openrisc-generic"
-
-config SYS_VENDOR
- default "openrisc"
-
-config SYS_CONFIG_NAME
- default "openrisc-generic"
-
-endif
diff --git a/board/openrisc/openrisc-generic/MAINTAINERS b/board/openrisc/openrisc-generic/MAINTAINERS
deleted file mode 100644
index c8dbc742e235..000000000000
--- a/board/openrisc/openrisc-generic/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OPENRISC-GENERIC BOARD
-M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S: Maintained
-F: board/openrisc/openrisc-generic/
-F: include/configs/openrisc-generic.h
-F: configs/openrisc-generic_defconfig
diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile
deleted file mode 100644
index 342bc80450d6..000000000000
--- a/board/openrisc/openrisc-generic/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := openrisc-generic.o
diff --git a/board/openrisc/openrisc-generic/config.mk b/board/openrisc/openrisc-generic/config.mk
deleted file mode 100644
index dd6595f757bf..000000000000
--- a/board/openrisc/openrisc-generic/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2011, Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mhard-mul -mhard-div
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/openrisc/openrisc-generic/openrisc-generic.c b/board/openrisc/openrisc-generic/openrisc-generic.c
deleted file mode 100644
index 4f82600bbbab..000000000000
--- a/board/openrisc/openrisc-generic/openrisc-generic.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on nios2-generic.c:
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-int checkboard(void)
-{
- printf("BOARD: %s\n", CONFIG_BOARD_NAME);
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_ETHOC
- rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg
deleted file mode 100644
index 2bd864293267..000000000000
--- a/board/openrisc/openrisc-generic/or1ksim.cfg
+++ /dev/null
@@ -1,871 +0,0 @@
-/* sim.cfg -- Simulator configuration script file
- Copyright (C) 2001-2002, Marko Mlinar, markom at opencores.org
-
-This file is part of OpenRISC 1000 Architectural Simulator.
-It contains the default configuration and help about configuring
-the simulator.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-/* INTRODUCTION
-
- The ork1sim has various parameters, that are set in configuration files
- like this one. The user can switch between configurations at startup by
- specifying the required configuration file with the -f <filename.cfg> option.
- If no configuration file is specified or1ksim searches for the default
- configuration file sim.cfg. First it searches for './sim.cfg'. If this
- file is not found, it searches for '~/or1k/sim.cfg'. If this file is
- not found too, it reverts to the built-in default configuration.
-
- NOTE: Users should not rely on the built-in configuration, since the
- default configuration may differ between version.
- Rather create a configuration file that sets all critical values.
-
- This file may contain (standard C) comments only - no // support.
-
- Configure files may be be included, using:
- include "file_name_to_include"
-
- Like normal configuration files, the included file is divided into
- sections. Each section is described in detail also.
-
- Some section have subsections. One example of such a subsection is:
-
- device <index>
- instance specific parameters...
- enddevice
-
- which creates a device instance.
-*/
-
-
-/* MEMORY SECTION
-
- This section specifies how the memory is generated and the blocks
- it consists of.
-
- type = random/unknown/pattern
- Specifies the initial memory values.
- 'random' generates random memory using seed 'random_seed'.
- 'pattern' fills memory with 'pattern'.
- 'unknown' does not specify how memory should be generated,
- leaving the memory in a undefined state. This is the fastest
- option.
-
- random_seed = <value>
- random seed for randomizer, used if type = 'random'.
-
- pattern = <value>
- pattern to fill memory, used if type = 'pattern'.
-
- nmemories = <value>
- number of memory instances connected
-
- baseaddr = <hex_value>
- memory start address
-
- size = <hex_value>
- memory size
-
- name = "<string>"
- memory block name
-
- ce = <value>
- chip enable index of the memory instance
-
- mc = <value>
- memory controller this memory is connected to
-
- delayr = <value>
- cycles, required for read access, -1 if instance does not support reading
-
- delayw = <value>
- cycles, required for write access, -1 if instance does not support writing
-
- log = "<filename>"
- filename, where to log memory accesses to, no log, if log command is not specified
-*/
-
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "FLASH"
- ce = 0
- mc = 0
- baseaddr = 0xf0000000
- size = 0x01000000
- delayr = 1
- delayw = -1
-end
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "RAM"
- ce = 1
- mc = 0
- baseaddr = 0x00000000
- size = 0x02000000
- delayr = 1
- delayw = 1
-end
-
-section memory
- pattern = 0x00
- type = unknown /* Fastest */
-
- name = "SRAM"
- mc = 0
- ce = 2
- baseaddr = 0xa4000000
- size = 0x00100000
- delayr = 1
- delayw = 2
-end
-
-
-/* IMMU SECTION
-
- This section configures the Instruction Memory Manangement Unit
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of ITLB sets; must be power of two
-
- nways = <value>
- number of ITLB ways
-
- pagesize = <value>
- instruction page size; must be power of two
-
- entrysize = <value>
- instruction entry size in bytes
-
- ustates = <value>
- number of ITLB usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles immu hit costs
-
- missdelay = <value>
- number of cycles immu miss costs
-*/
-
-section immu
- enabled = 1
- nsets = 64
- nways = 1
- pagesize = 8192
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* DMMU SECTION
-
- This section configures the Data Memory Manangement Unit
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of DTLB sets; must be power of two
-
- nways = <value>
- number of DTLB ways
-
- pagesize = <value>
- data page size; must be power of two
-
- entrysize = <value>
- data entry size in bytes
-
- ustates = <value>
- number of DTLB usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles dmmu hit costs
-
- missdelay = <value>
- number of cycles dmmu miss costs
-*/
-
-section dmmu
- enabled = 1
- nsets = 64
- nways = 1
- pagesize = 8192
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* IC SECTION
-
- This section configures the Instruction Cache
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of IC sets; must be power of two
-
- nways = <value>
- number of IC ways
-
- blocksize = <value>
- IC block size in bytes; must be power of two
-
- ustates = <value>
- number of IC usage states (2, 3, 4 etc., max is 4)
-
- hitdelay = <value>
- number of cycles ic hit costs
-
- missdelay = <value>
- number of cycles ic miss costs
-*/
-
-section ic
- enabled = 1
- nsets = 512
- nways = 1
- blocksize = 16
- hitdelay = 1
- missdelay = 1
-end
-
-
-/* DC SECTION
-
- This section configures the Data Cache
-
- enabled = 0/1
- '0': disabled
- '1': enabled
- (NOTE: UPR bit is set)
-
- nsets = <value>
- number of DC sets; must be power of two
-
- nways = <value>
- number of DC ways
-
- blocksize = <value>
- DC block size in bytes; must be power of two
-
- ustates = <value>
- number of DC usage states (2, 3, 4 etc., max is 4)
-
- load_hitdelay = <value>
- number of cycles dc load hit costs
-
- load_missdelay = <value>
- number of cycles dc load miss costs
-
- store_hitdelay = <value>
- number of cycles dc load hit costs
-
- store_missdelay = <value>
- number of cycles dc load miss costs
-*/
-
-section dc
- enabled = 1
- nsets = 512
- nways = 1
- blocksize = 16
- load_hitdelay = 1
- load_missdelay = 1
- store_hitdelay = 1
- store_missdelay = 1
-end
-
-
-/* SIM SECTION
-
- This section specifies how or1ksim should behave.
-
- verbose = 0/1
- '0': don't print extra messages
- '1': print extra messages
-
- debug = 0-9
- 0 : no debug messages
- 1-9: debug message level.
- higher numbers produce more messages
-
- profile = 0/1
- '0': don't generate profiling file 'sim.profile'
- '1': don't generate profiling file 'sim.profile'
-
- prof_fn = "<filename>"
- optional filename for the profiling file.
- valid only if 'profile' is set
-
- mprofile = 0/1
- '0': don't generate memory profiling file 'sim.mprofile'
- '1': generate memory profiling file 'sim.mprofile'
-
- mprof_fn = "<filename>"
- optional filename for the memory profiling file.
- valid only if 'mprofile' is set
-
- history = 0/1
- '0': don't track execution flow
- '1': track execution flow
- Execution flow can be tracked for the simulator's
- 'hist' command. Useful for back-trace debugging.
-
- iprompt = 0/1
- '0': start in <not interactive prompt> (so what do we start in ???)
- '1': start in interactive prompt.
-
- exe_log = 0/1
- '0': don't generate execution log.
- '1': generate execution log.
-
- exe_log = default/hardware/simple/software
- type of execution log, default is used when not specified
-
- exe_log_start = <value>
- index of first instruction to start logging, default = 0
-
- exe_log_end = <value>
- index of last instruction to end logging; not limited, if omitted
-
- exe_log_marker = <value>
- <value> specifies number of instructions before horizontal marker is
- printed; if zero, markers are disabled (default)
-
- exe_log_fn = "<filename>"
- filename for the exection log file.
- valid only if 'exe_log' is set
-
- clkcycle = <value>[ps|ns|us|ms]
- specifies time measurement for one cycle
-*/
-
-section sim
- verbose = 1
- debug = 0
- profile = 0
- history = 0
-
- clkcycle = 10ns
-end
-
-
-/* SECTION VAPI
-
- This section configures the Verification API, used for Advanced
- Core Verification.
-
- enabled = 0/1
- '0': disbable VAPI server
- '1': enable/start VAPI server
-
- server_port = <value>
- TCP/IP port to start VAPI server on
-
- log_enabled = 0/1
- '0': disable VAPI requests logging
- '1': enable VAPI requests logging
-
- hide_device_id = 0/1
- '0': don't log device id (for compatability with old version)
- '1': log device id
-
-
- vapi_fn = <filename>
- filename for the log file.
- valid only if log_enabled is set
-*/
-
-section VAPI
- enabled = 0
- server_port = 9998
- log_enabled = 0
- vapi_log_fn = "vapi.log"
-end
-
-
-/* CPU SECTION
-
- This section specifies various CPU parameters.
-
- ver = <value>
- rev = <value>
- specifies version and revision of the CPU used
-
- upr = <value>
- changes the upr register
-
- sr = <value>
- sets the initial Supervision Register value
- supervisor mode (SM) and fixed one (FO) set = 0x8001
- exception prefix high (EPH, vectors at 0xf0000000) = 0x4000
- together, (SM | FO | EPH) = 0xc001
- superscalar = 0/1
- '0': CPU is scalar
- '1': CPU is superscalar
- (modify cpu/or32/execute.c to tune superscalar model)
-
- hazards = 0/1
- '0': don't track data hazards in superscalar CPU
- '1': track data hazards in superscalar CPU
- If tracked, data hazards can be displayed using the
- simulator's 'r' command.
-
- dependstats = 0/1
- '0': don't calculate inter-instruction dependencies.
- '1': calculate inter-instruction dependencies.
- If calculated, inter-instruction dependencies can be
- displayed using the simulator's 'stat' command.
-
- sbuf_len = <value>
- length of store buffer (<= 256), 0 = disabled
-*/
-
-section cpu
- ver = 0x12
- cfg = 0x00
- rev = 0x01
- sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
- /* upr = */
- superscalar = 0
- hazards = 0
- dependstats = 0
- sbuf_len = 0
-end
-
-
-/* PM SECTION
-
- This section specifies Power Management parameters
-
- enabled = 0/1
- '0': disable power management
- '1': enable power management
-*/
-
-section pm
- enabled = 0
-end
-
-
-/* BPB SECTION
-
- This section specifies how branch prediction should behave.
-
- enabled = 0/1
- '0': disable branch prediction
- '1': enable branch prediction
-
- btic = 0/1
- '0': disable branch target instruction cache model
- '1': enable branch target instruction cache model
-
- sbp_bf_fwd = 0/1
- Static branch prediction for 'l.bf'
- '0': don't use forward prediction
- '1': use forward prediction
-
- sbp_bnf_fwd = 0/1
- Static branch prediction for 'l.bnf'
- '0': don't use forward prediction
- '1': use forward prediction
-
- hitdelay = <value>
- number of cycles bpb hit costs
-
- missdelay = <value>
- number of cycles bpb miss costs
-*/
-
-section bpb
- enabled = 0
- btic = 0
- sbp_bf_fwd = 0
- sbp_bnf_fwd = 0
- hitdelay = 0
- missdelay = 0
-end
-
-
-/* DEBUG SECTION
-
- This sections specifies how the debug unit should behave.
-
- enabled = 0/1
- '0': disable debug unit
- '1': enable debug unit
-
- gdb_enabled = 0/1
- '0': don't start gdb server
- '1': start gdb server at port 'server_port'
-
- server_port = <value>
- TCP/IP port to start gdb server on
- valid only if gdb_enabled is set
-
- vapi_id = <hex_value>
- Used to create "fake" vapi log file containing the JTAG proxy messages.
-*/
-section debug
- enabled = 0
-/* gdb_enabled = 0 */
-/* server_port = 9999*/
- rsp_enabled = 1
- rsp_port = 50001
-end
-
-
-/* MC SECTION
-
- This section configures the memory controller
-
- enabled = 0/1
- '0': disable memory controller
- '1': enable memory controller
-
- baseaddr = <hex_value>
- address of first MC register
-
- POC = <hex_value>
- Power On Configuration register
-
- index = <value>
- Index of this memory controller amongst all the memory controllers
-*/
-
-section mc
- enabled = 0
- baseaddr = 0x93000000
- POC = 0x00000008 /* Power on configuration register */
- index = 0
-end
-
-
-/* UART SECTION
-
- This section configures the UARTs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first UART register for this device
-
-
- channel = <channeltype>:<args>
-
- The channel parameter indicates the source of received UART characters
- and the sink for transmitted UART characters.
-
- The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
- (without quotes).
-
- A) To send/receive characters from a pair of files, use a file
- channel:
-
- channel=file:<rxfile>,<txfile>
-
- B) To create an interactive terminal window, use an xterm channel:
-
- channel=xterm:[<xterm_arg>]*
-
- C) To create a bidirectional tcp socket which one could, for example,
- access via telnet, use a tcp channel:
-
- channel=tcp:<port number>
-
- D) To cause the UART to read/write from existing numeric file
- descriptors, use an fd channel:
-
- channel=fd:<rx file descriptor num>,<tx file descriptor num>
-
- E) To connect the UART to a physical serial port, create a tty
- channel:
-
- channel=tty:device=/dev/ttyS0,baud=9600
-
- irq = <value>
- irq number for this device
-
- 16550 = 0/1
- '0': this device is a UART16450
- '1': this device is a UART16550
-
- jitter = <value>
- in msecs... time to block, -1 to disable it
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section uart
- enabled = 1
- baseaddr = 0x90000000
- irq = 2
- /* channel = "file:uart0.rx,uart0.tx" */
- /* channel = "tcp:10084" */
- channel = "xterm:"
- jitter = -1 /* async behaviour */
- 16550 = 1
-end
-
-
-/* DMA SECTION
-
- This section configures the DMAs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first DMA register for this device
-
- irq = <value>
- irq number for this device
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section dma
- enabled = 1
- baseaddr = 0x9a000000
- irq = 11
-end
-
-
-/* ETHERNET SECTION
-
- This section configures the ETHERNETs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first ethernet register for this device
-
- dma = <value>
- which controller is this ethernet "connected" to
-
- irq = <value>
- ethernet mac IRQ level
-
- rtx_type = <value>
- use 0 - file interface, 1 - socket interface
-
- rx_channel = <value>
- DMA channel used for RX
-
- tx_channel = <value>
- DMA channel used for TX
-
- rxfile = "<filename>"
- filename, where to read data from
-
- txfile = "<filename>"
- filename, where to write data to
-
- sockif = "<ifacename>"
- interface name of ethernet socket
-
- vapi_id = <hex_value>
- VAPI id of this instance
-*/
-
-section ethernet
- enabled = 1
- baseaddr = 0x92000000
- /* dma = 0 */
- irq = 4
- rtx_type = "tap"
- tap_dev = "tap0"
- /* tx_channel = 0 */
- /* rx_channel = 1 */
- rxfile = "eth0.rx"
- txfile = "eth0.tx"
- sockif = "eth0"
-end
-
-
-/* GPIO SECTION
-
- This section configures the GPIOs
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first GPIO register for this device
-
- irq = <value>
- irq number for this device
-
- base_vapi_id = <hex_value>
- first VAPI id of this instance
- GPIO uses 8 consecutive VAPI IDs
-*/
-
-section gpio
- enabled = 0
- baseaddr = 0x91000000
- irq = 3
- base_vapi_id = 0x0200
-end
-
-/* VGA SECTION
-
- This section configures the VGA/LCD controller
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- address of first VGA register
-
- irq = <value>
- irq number for this device
-
- refresh_rate = <value>
- number of cycles between screen dumps
-
- filename = "<filename>"
- template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section vga
- enabled = 0
- baseaddr = 0x97100000
- irq = 8
- refresh_rate = 100000
- filename = "primary"
-end
-
-
-/* TICK TIMER SECTION
-
- This section configures tick timer
-
- enabled = 0/1
- whether tick timer is enabled
-*/
-
-section pic
- enabled = 1
- edge_trigger = 1
-end
-
-/* FB SECTION
-
- This section configures the frame buffer
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- baseaddr = <hex_value>
- base address of frame buffer
-
- paladdr = <hex_value>
- base address of first palette entry
-
- refresh_rate = <value>
- number of cycles between screen dumps
-
- filename = "<filename>"
- template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section fb
- enabled = 0
- baseaddr = 0x97000000
- refresh_rate = 1000000
- filename = "primary"
-end
-
-
-/* KBD SECTION
-
- This section configures the PS/2 compatible keyboard
-
- baseaddr = <hex_value>
- base address of the keyboard device
-
- rxfile = "<filename>"
- filename, where to read data from
-*/
-
-section kbd
- enabled = 0
- irq = 5
- baseaddr = 0x94000000
- rxfile = "kbd.rx"
-end
-
-
-/* ATA SECTION
-
- This section configures the ATA/ATAPI host controller
-
- baseaddr = <hex_value>
- address of first ATA register
-
- enabled = <0|1>
- Enable/disable the peripheral. By default if it is enabled.
-
- irq = <value>
- irq number for this device
-
- debug = <value>
- debug level for ata models.
- 0: no debug messages
- 1: verbose messages
- 3: normal messages (more messages than verbose)
- 5: debug messages (normal debug messages)
- 7: flow control messages (debug statemachine flows)
- 9: low priority message (display everything the code does)
-
- dev_type0/1 = <value>
- ata device 0 type
- 0: NO_CONNeCT: none (not connected)
- 1: FILE : simulated harddisk
- 2: LOCAL : local system harddisk
-
- dev_file0/1 = "<filename>"
- filename for simulated ATA device
- valid only if dev_type0 == 1
-
- dev_size0/1 = <value>
- size of simulated hard-disk (in MBytes)
- valid only if dev_type0 == 1
-
- dev_packet0/1 = <value>
- 0: simulated ATA device does NOT implement PACKET command feature set
- 1: simulated ATA device does implement PACKET command feature set
-
- FIXME: irq number
-*/
-
-section ata
- enabled = 0
- baseaddr = 0x9e000000
- irq = 15
-
-end
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 4a2e5e802213..3cd8562fb9e6 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -114,7 +114,7 @@ static inline void print_bi_flash(const bd_t *bd)
print_num("flash size ", (ulong)bd->bi_flashsize);
print_num("flash offset ", (ulong)bd->bi_flashoffset);
-#elif defined(CONFIG_NIOS2) || defined(CONFIG_OPENRISC)
+#elif defined(CONFIG_NIOS2)
print_num("flash start", (ulong)bd->bi_flashstart);
print_num("flash size", (ulong)bd->bi_flashsize);
print_num("flash offset", (ulong)bd->bi_flashoffset);
@@ -439,20 +439,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
-#elif defined(CONFIG_OPENRISC)
-
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- bd_t *bd = gd->bd;
-
- print_bi_mem(bd);
- print_bi_flash(bd);
- print_eth_ip_addr();
- print_baudrate();
-
- return 0;
-}
-
#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/configs/openrisc-generic_defconfig b/configs/openrisc-generic_defconfig
deleted file mode 100644
index 55f0122b2323..000000000000
--- a/configs/openrisc-generic_defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-CONFIG_OPENRISC=y
-CONFIG_TARGET_OPENRISC_GENERIC=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_NETDEVICES=y
-CONFIG_ETHOC=y
-CONFIG_SYS_NS16550=y
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index bc9ff89527bc..a6a9fcf189a4 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -185,20 +185,6 @@ gd_t *global_data;
" lwi $r16, [$r16 + (%1)]\n" \
" jr $r16\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
-#elif defined(CONFIG_OPENRISC)
-/*
- * r10 holds the pointer to the global_data, r13 is a call-clobbered
- * register
- */
-#define EXPORT_FUNC(f, a, x, ...) \
- asm volatile ( \
-" .globl " #x "\n" \
-#x ":\n" \
-" l.lwz r13, %0(r10)\n" \
-" l.lwz r13, %1(r13)\n" \
-" l.jr r13\n" \
-" l.nop\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r13");
#elif defined(CONFIG_ARC)
/*
* r25 holds the pointer to the global_data. r10 is call clobbered.
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
deleted file mode 100644
index 7b2ce789cc4e..000000000000
--- a/include/configs/openrisc-generic.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons at saunalahti.fi
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * BOARD/CPU
- */
-#define CONFIG_SYS_CLK_FREQ 50000000
-#define CONFIG_SYS_RESET_ADDR 0x00000100
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 0x02000000
-
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define CONFIG_SYS_UART_BASE 0x90000000
-#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_UART_BAUD 115200
-
-#define CONFIG_BOARD_NAME "OpenRISC Generic"
-
-#define CONFIG_SYS_MAX_FLASH_SECT 0
-
-/*
- * SERIAL
- */
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_COM1 (0x90000000)
-# define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
-
-#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD
-#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
-#define CONSOLE_ARG "console=console=ttyS0,115200\0"
-
-/*
- * Ethernet
- */
-#define CONFIG_SYS_ETHOC_BASE 0x92000000
-
-#define CONFIG_BOOTFILE "boot.img"
-#define CONFIG_LOADADDR 0x100000 /* 1MB mark */
-
-/*
- * TIMER
- */
-#define CONFIG_SYS_OPENRISC_TMR_HZ 100
-
-/*
- * Memory organisation:
- *
- * RAM start ---------------------------
- * | ... |
- * ---------------------------
- * | Stack |
- * ---------------------------
- * | Global data |
- * ---------------------------
- * | Environment |
- * ---------------------------
- * | Monitor |
- * RAM end ---------------------------
- */
-/* We're running in RAM */
-#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_SDRAM_SIZE - \
- CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment, 128KB */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
-
-/*
- * Global data object and stack pointer
- */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_ENV_ADDR \
- - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_GBL_DATA_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_STACK_LENGTH 0x10000 /* 64KB */
-#define CONFIG_SYS_MALLOC_LEN 0x400000 /* 4MB */
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_INIT_SP_OFFSET \
- - CONFIG_SYS_STACK_LENGTH \
- - CONFIG_SYS_MALLOC_LEN)
-/*
- * MISC
- */
-#define CONFIG_SYS_LONGHELP /* Provide extended help */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS 16 /* Max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x2000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP_ADDR - 0x20000)
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_BSP
-
-#define CONFIG_LMB
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#endif /* __CONFIG_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 3/3] OpenRISC: Remove
2017-03-14 15:08 ` [U-Boot] [PATCH 3/3] OpenRISC: Remove Tom Rini
@ 2017-03-16 3:05 ` Simon Glass
2017-04-06 16:23 ` [U-Boot] [U-Boot,3/3] " Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Simon Glass @ 2017-03-16 3:05 UTC (permalink / raw)
To: u-boot
On 14 March 2017 at 09:08, Tom Rini <trini@konsulko.com> wrote:
> The OpenRISC architecture is currently unmaintained, remove.
>
> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> MAINTAINERS | 5 -
Reviewed-by: Simon Glass <sjg@chromium.org>
There are a few more small things that could go, but this gets most of
it, and certainly makes it clear that it is gone.
(BTW I did not get the other two remove patches in my email)
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [U-Boot,1/3] Blackfin: Remove
2017-03-14 15:08 [U-Boot] [PATCH 1/3] Blackfin: Remove Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 2/3] SPARC: Remove Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 3/3] OpenRISC: Remove Tom Rini
@ 2017-04-06 16:23 ` Tom Rini
2 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2017-04-06 16:23 UTC (permalink / raw)
To: u-boot
On Tue, Mar 14, 2017 at 11:08:10AM -0400, Tom Rini wrote:
> The architecture is currently unmaintained, remove.
>
> Cc: Benjamin Matthews <mben12@gmail.com>
> Cc: Chong Huang <chuang@ucrobotics.com>
> Cc: Dimitar Penev <dpn@switchfin.org>
> Cc: Haitao Zhang <hzhang@ucrobotics.com>
> Cc: I-SYST Micromodule <support@i-syst.com>
> Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Martin Strubel <strubel@section5.ch>
> Cc: Peter Meerwald <devel@bct-electronic.com>
> Cc: Sonic Zhang <sonic.adi@gmail.com>
> Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
> Cc: Wojtek Skulski <info@skutek.com>
> Cc: Wojtek Skulski <skulski@pas.rochester.edu>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170406/c2f636b8/attachment.sig>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [U-Boot,2/3] SPARC: Remove
2017-03-14 15:08 ` [U-Boot] [PATCH 2/3] SPARC: Remove Tom Rini
@ 2017-04-06 16:23 ` Tom Rini
0 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2017-04-06 16:23 UTC (permalink / raw)
To: u-boot
On Tue, Mar 14, 2017 at 11:08:11AM -0400, Tom Rini wrote:
> The SPARC architecture is currently unmaintained, remove.
>
> Cc: Francois Retief <fgretief@spaceteq.co.za>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170406/0f42c59d/attachment.sig>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [U-Boot,3/3] OpenRISC: Remove
2017-03-14 15:08 ` [U-Boot] [PATCH 3/3] OpenRISC: Remove Tom Rini
2017-03-16 3:05 ` Simon Glass
@ 2017-04-06 16:23 ` Tom Rini
1 sibling, 0 replies; 7+ messages in thread
From: Tom Rini @ 2017-04-06 16:23 UTC (permalink / raw)
To: u-boot
On Tue, Mar 14, 2017 at 11:08:12AM -0400, Tom Rini wrote:
> The OpenRISC architecture is currently unmaintained, remove.
>
> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170406/10bebb8b/attachment.sig>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-04-06 16:23 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-14 15:08 [U-Boot] [PATCH 1/3] Blackfin: Remove Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 2/3] SPARC: Remove Tom Rini
2017-04-06 16:23 ` [U-Boot] [U-Boot,2/3] " Tom Rini
2017-03-14 15:08 ` [U-Boot] [PATCH 3/3] OpenRISC: Remove Tom Rini
2017-03-16 3:05 ` Simon Glass
2017-04-06 16:23 ` [U-Boot] [U-Boot,3/3] " Tom Rini
2017-04-06 16:23 ` [U-Boot] [U-Boot,1/3] Blackfin: Remove Tom Rini
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.