* [PATCH 0/3] ZX296718 clock update for VGA support
@ 2017-03-21 8:38 ` Shawn Guo
0 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-arm-kernel, Jun Nie, Baoyou Xie, Xin Zhou, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
This is a series which makes necessary changes on zx296718 clock driver
in order to support VGA display. The second patch actually fixes a bug
that is discovered by VGA driver debugging.
Shawn Guo (3):
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
zte: clk: pd_bit is not 0 on zx296718
clk: zte: add pll_vga clock for zx296718
drivers/clk/zte/clk-zx296718.c | 30 +++++++++++++++++++++++++++---
drivers/clk/zte/clk.c | 12 +++++++++++-
drivers/clk/zte/clk.h | 6 +++++-
3 files changed, 43 insertions(+), 5 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 0/3] ZX296718 clock update for VGA support
@ 2017-03-21 8:38 ` Shawn Guo
0 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawn.guo@linaro.org>
This is a series which makes necessary changes on zx296718 clock driver
in order to support VGA display. The second patch actually fixes a bug
that is discovered by VGA driver debugging.
Shawn Guo (3):
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
zte: clk: pd_bit is not 0 on zx296718
clk: zte: add pll_vga clock for zx296718
drivers/clk/zte/clk-zx296718.c | 30 +++++++++++++++++++++++++++---
drivers/clk/zte/clk.c | 12 +++++++++++-
drivers/clk/zte/clk.h | 6 +++++-
3 files changed, 43 insertions(+), 5 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-21 8:38 ` Shawn Guo
-1 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-arm-kernel, Jun Nie, Baoyou Xie, Xin Zhou, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.
While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index 2f7c668643fe..f2e1e8b3a8d5 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -409,7 +409,7 @@
FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
/* vga */
FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
- FFACTOR(0, "clk_vga", "pll_vga", 1, 2, 0),
+ FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
/* pll ddr */
FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
@@ -458,8 +458,8 @@
MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
- MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3),
- MUX(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3),
+ MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
@ 2017-03-21 8:38 ` Shawn Guo
0 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawn.guo@linaro.org>
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.
While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index 2f7c668643fe..f2e1e8b3a8d5 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -409,7 +409,7 @@
FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
/* vga */
FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
- FFACTOR(0, "clk_vga", "pll_vga", 1, 2, 0),
+ FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
/* pll ddr */
FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
@@ -458,8 +458,8 @@
MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
- MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3),
- MUX(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3),
+ MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-21 8:38 ` Shawn Guo
-1 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-arm-kernel, Jun Nie, Baoyou Xie, Xin Zhou, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field. The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk.c | 12 +++++++++++-
drivers/clk/zte/clk.h | 6 +++++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c
index 878d879b23ff..b82031766ffa 100644
--- a/drivers/clk/zte/clk.c
+++ b/drivers/clk/zte/clk.c
@@ -52,7 +52,10 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll)
/* For matching the value in lookup table */
hw_cfg0 &= ~BIT(zx_pll->lock_bit);
- hw_cfg0 |= BIT(zx_pll->pd_bit);
+
+ /* Check availability of pd_bit */
+ if (zx_pll->pd_bit < 32)
+ hw_cfg0 |= BIT(zx_pll->pd_bit);
for (i = 0; i < zx_pll->count; i++) {
if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
@@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
+ /* If pd_bit is not available, simply return success. */
+ if (zx_pll->pd_bit > 31)
+ return 0;
+
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
@@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
+ if (zx_pll->pd_bit > 31)
+ return;
+
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
}
diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 84a55a3e2bd4..4df0f121b56d 100644
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -66,8 +66,12 @@ struct clk_zx_pll {
CLK_GET_RATE_NOCACHE), \
}
+/*
+ * The pd_bit is not available on ZX296718, so let's pass something
+ * bigger than 31, e.g. 0xff, to indicate that.
+ */
#define ZX296718_PLL(_name, _parent, _reg, _table) \
-ZX_PLL(_name, _parent, _reg, _table, 0, 30)
+ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
struct zx_clk_gate {
struct clk_gate gate;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
@ 2017-03-21 8:38 ` Shawn Guo
0 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawn.guo@linaro.org>
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field. The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk.c | 12 +++++++++++-
drivers/clk/zte/clk.h | 6 +++++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c
index 878d879b23ff..b82031766ffa 100644
--- a/drivers/clk/zte/clk.c
+++ b/drivers/clk/zte/clk.c
@@ -52,7 +52,10 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll)
/* For matching the value in lookup table */
hw_cfg0 &= ~BIT(zx_pll->lock_bit);
- hw_cfg0 |= BIT(zx_pll->pd_bit);
+
+ /* Check availability of pd_bit */
+ if (zx_pll->pd_bit < 32)
+ hw_cfg0 |= BIT(zx_pll->pd_bit);
for (i = 0; i < zx_pll->count; i++) {
if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
@@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
+ /* If pd_bit is not available, simply return success. */
+ if (zx_pll->pd_bit > 31)
+ return 0;
+
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
@@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw)
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
u32 reg;
+ if (zx_pll->pd_bit > 31)
+ return;
+
reg = readl_relaxed(zx_pll->reg_base);
writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
}
diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 84a55a3e2bd4..4df0f121b56d 100644
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -66,8 +66,12 @@ struct clk_zx_pll {
CLK_GET_RATE_NOCACHE), \
}
+/*
+ * The pd_bit is not available on ZX296718, so let's pass something
+ * bigger than 31, e.g. 0xff, to indicate that.
+ */
#define ZX296718_PLL(_name, _parent, _reg, _table) \
-ZX_PLL(_name, _parent, _reg, _table, 0, 30)
+ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
struct zx_clk_gate {
struct clk_gate gate;
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-21 8:38 ` Shawn Guo
-1 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-arm-kernel, Jun Nie, Baoyou Xie, Xin Zhou, Shawn Guo
From: Shawn Guo <shawn.guo@linaro.org>
It adds zx296718 pll_vga clock for VGA support, so that VGA device can
get required pixel rate from clock driver for different display mode.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index f2e1e8b3a8d5..8db0119bc6f7 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -101,6 +101,29 @@
PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
};
+static struct zx_pll_config pll_vga_table[] = {
+ PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */
+ PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */
+ PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */
+ PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600@72 */
+ PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600@85 */
+ PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768@60 */
+ PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720@60 */
+ PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768@70 */
+ PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768@75 */
+ PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768@60 */
+ PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
+ PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
+ PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
+ PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
+ PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
+ PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
+ PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
+ PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
+ PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
+ PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
+};
+
PNAME(osc) = {
"osc24m",
"osc32k",
@@ -369,6 +392,7 @@
static struct clk_zx_pll zx296718_pll_clk[] = {
ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table),
+ ZX296718_PLL("pll_vga", "osc24m", PLL_VGA_REG, pll_vga_table),
};
static struct zx_clk_fixed_factor top_ffactor_clk[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
@ 2017-03-21 8:38 ` Shawn Guo
0 siblings, 0 replies; 20+ messages in thread
From: Shawn Guo @ 2017-03-21 8:38 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawn.guo@linaro.org>
It adds zx296718 pll_vga clock for VGA support, so that VGA device can
get required pixel rate from clock driver for different display mode.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index f2e1e8b3a8d5..8db0119bc6f7 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -101,6 +101,29 @@
PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
};
+static struct zx_pll_config pll_vga_table[] = {
+ PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600 at 56 */
+ PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600 at 60 */
+ PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600 at 75 */
+ PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600 at 72 */
+ PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600 at 85 */
+ PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768 at 60 */
+ PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720 at 60 */
+ PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768 at 70 */
+ PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768 at 75 */
+ PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768 at 60 */
+ PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900 at 60 */
+ PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024 at 60 */
+ PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768 at 85 */
+ PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024 at 75 */
+ PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900 at 75 */
+ PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080 at 60 */
+ PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900 at 85 */
+ PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024 at 85 */
+ PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200 at 60 */
+ PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200 at 60 */
+};
+
PNAME(osc) = {
"osc24m",
"osc32k",
@@ -369,6 +392,7 @@
static struct clk_zx_pll zx296718_pll_clk[] = {
ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table),
+ ZX296718_PLL("pll_vga", "osc24m", PLL_VGA_REG, pll_vga_table),
};
static struct zx_clk_fixed_factor top_ffactor_clk[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-23 1:34 ` Jun Nie
-1 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Baoyou Xie, Xin Zhou, Shawn Guo
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
@ 2017-03-23 1:34 ` Jun Nie
0 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:34 UTC (permalink / raw)
To: linux-arm-kernel
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-23 1:36 ` Jun Nie
-1 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:36 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Baoyou Xie, Xin Zhou, Shawn Guo
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds zx296718 pll_vga clock for VGA support, so that VGA device can
> get required pixel rate from clock driver for different display mode.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
@ 2017-03-23 1:36 ` Jun Nie
0 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:36 UTC (permalink / raw)
To: linux-arm-kernel
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds zx296718 pll_vga clock for VGA support, so that VGA device can
> get required pixel rate from clock driver for different display mode.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
2017-03-21 8:38 ` Shawn Guo
@ 2017-03-23 1:37 ` Jun Nie
-1 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:37 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel,
Baoyou Xie, Xin Zhou, Shawn Guo
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> To support VOU VGA display driver with different modes, we need to set
> flag for a few clocks, so that clk_set_rate() call in VOU driver can get
> VGA device desired pixel rate.
>
> While at it, the divider between pll_vga and clk_vga gets corrected, as
> it's 1:1 instead of 1:2.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
@ 2017-03-23 1:37 ` Jun Nie
0 siblings, 0 replies; 20+ messages in thread
From: Jun Nie @ 2017-03-23 1:37 UTC (permalink / raw)
To: linux-arm-kernel
2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo@kernel.org>:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> To support VOU VGA display driver with different modes, we need to set
> flag for a few clocks, so that clk_set_rate() call in VOU driver can get
> VGA device desired pixel rate.
>
> While at it, the divider between pll_vga and clk_vga gets corrected, as
> it's 1:1 instead of 1:2.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
2017-03-21 8:38 ` Shawn Guo
@ 2017-04-07 19:22 ` Stephen Boyd
-1 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, linux-clk, linux-arm-kernel, Jun Nie,
Baoyou Xie, Xin Zhou, Shawn Guo
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> To support VOU VGA display driver with different modes, we need to set
> flag for a few clocks, so that clk_set_rate() call in VOU driver can get
> VGA device desired pixel rate.
>
> While at it, the divider between pll_vga and clk_vga gets corrected, as
> it's 1:1 instead of 1:2.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
@ 2017-04-07 19:22 ` Stephen Boyd
0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: linux-arm-kernel
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> To support VOU VGA display driver with different modes, we need to set
> flag for a few clocks, so that clk_set_rate() call in VOU driver can get
> VGA device desired pixel rate.
>
> While at it, the divider between pll_vga and clk_vga gets corrected, as
> it's 1:1 instead of 1:2.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-04-07 19:22 ` Stephen Boyd
-1 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, linux-clk, linux-arm-kernel, Jun Nie,
Baoyou Xie, Xin Zhou, Shawn Guo
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
@ 2017-04-07 19:22 ` Stephen Boyd
0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: linux-arm-kernel
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
2017-03-21 8:38 ` Shawn Guo
@ 2017-04-07 19:22 ` Stephen Boyd
-1 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: Shawn Guo
Cc: Michael Turquette, linux-clk, linux-arm-kernel, Jun Nie,
Baoyou Xie, Xin Zhou, Shawn Guo
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds zx296718 pll_vga clock for VGA support, so that VGA device can
> get required pixel rate from clock driver for different display mode.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/3] clk: zte: add pll_vga clock for zx296718
@ 2017-04-07 19:22 ` Stephen Boyd
0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2017-04-07 19:22 UTC (permalink / raw)
To: linux-arm-kernel
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> It adds zx296718 pll_vga clock for VGA support, so that VGA device can
> get required pixel rate from clock driver for different display mode.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2017-04-07 19:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-21 8:38 [PATCH 0/3] ZX296718 clock update for VGA support Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-21 8:38 ` [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:37 ` Jun Nie
2017-03-23 1:37 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd
2017-04-07 19:22 ` Stephen Boyd
2017-03-21 8:38 ` [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718 Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:34 ` Jun Nie
2017-03-23 1:34 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd
2017-04-07 19:22 ` Stephen Boyd
2017-03-21 8:38 ` [PATCH 3/3] clk: zte: add pll_vga clock for zx296718 Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:36 ` Jun Nie
2017-03-23 1:36 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd
2017-04-07 19:22 ` Stephen Boyd
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.