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* [RFC] drm/i915: add slice shutdown debugfs interface
@ 2017-04-07 10:41 Dmitry Rogozhkin
  2017-04-07 18:50 ` Chris Wilson
  2017-04-07 19:06 ` ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 2 replies; 5+ messages in thread
From: Dmitry Rogozhkin @ 2017-04-07 10:41 UTC (permalink / raw)
  To: intel-gfx

Slice shutdown override interface (i915_slice_enabled) permits
to power on/off GPGPU slices in Gen8 and Gen9. This is helpful
in performance investigations amd checking scalability across
hw platforms.

Change-Id: I4f2fe5fefb8d1df4519fd0eb58237759c7d1a930
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
CC: Zhipeng Gong <zhipeng.gong@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c      | 36 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
 4 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d689e51..977bdb03 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4812,6 +4812,39 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	{"i915_drrs_status", i915_drrs_status, 0},
 	{"i915_rps_boost_info", i915_rps_boost_info, 0},
 };
+
+static int
+i915_slice_enabled_get(void *data, u64 *val)
+{
+	struct drm_device *dev = data;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	*val = INTEL_INFO(dev_priv)->sseu.slice_enabled;
+	return 0;
+}
+
+static int
+i915_slice_enabled_set(void *data, u64 val)
+{
+	struct drm_device *dev = data;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_device_info *info;
+
+	info = mkwrite_device_info(dev_priv);
+	if (!IS_SKYLAKE(dev_priv) || !info->sseu.has_slice_pg)
+		return -EINVAL;
+
+	if (val > hweight8(info->sseu.slice_mask))
+		return -EINVAL;
+
+	info->sseu.slice_enabled = (u8)val;
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_slice_enabled_fops,
+			i915_slice_enabled_get, i915_slice_enabled_set,
+			"%llu\n");
+
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
 
 static const struct i915_debugfs_files {
@@ -4839,7 +4872,8 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
 	{"i915_dp_test_type", &i915_displayport_test_type_fops},
 	{"i915_dp_test_active", &i915_displayport_test_active_fops},
 	{"i915_guc_log_control", &i915_guc_log_control_fops},
-	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
+	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
+	{"i915_slice_enabled", &i915_slice_enabled_fops}
 };
 
 int i915_debugfs_register(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb6fc1e..7455d43 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -852,6 +852,7 @@ struct sseu_dev_info {
 	u8 has_slice_pg:1;
 	u8 has_subslice_pg:1;
 	u8 has_eu_pg:1;
+	u8 slice_enabled;
 };
 
 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7d01dfe..2eee76b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -412,6 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		gen9_sseu_info_init(dev_priv);
 
 	info->has_snoop = !info->has_llc;
+	info->sseu.slice_enabled = hweight8(info->sseu.slice_mask);
 
 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..bc650df 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1732,7 +1732,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
 	 * No explicit RPCS request is needed to ensure full
 	 * slice/subslice/EU enablement prior to Gen9.
 	*/
-	if (INTEL_GEN(dev_priv) < 9)
+	if (INTEL_GEN(dev_priv) < 8)
 		return 0;
 
 	/*
@@ -1743,7 +1743,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
 	*/
 	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
 		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
-		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
+		rpcs |= INTEL_INFO(dev_priv)->sseu.slice_enabled <<
 			GEN8_RPCS_S_CNT_SHIFT;
 		rpcs |= GEN8_RPCS_ENABLE;
 	}
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [RFC] drm/i915: add slice shutdown debugfs interface
  2017-04-07 10:41 [RFC] drm/i915: add slice shutdown debugfs interface Dmitry Rogozhkin
@ 2017-04-07 18:50 ` Chris Wilson
  2017-04-07 19:11   ` Dmitry Rogozhkin
  2017-04-07 19:06 ` ✓ Fi.CI.BAT: success for " Patchwork
  1 sibling, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2017-04-07 18:50 UTC (permalink / raw)
  To: Dmitry Rogozhkin; +Cc: intel-gfx

On Fri, Apr 07, 2017 at 03:41:41AM -0700, Dmitry Rogozhkin wrote:
> Slice shutdown override interface (i915_slice_enabled) permits
> to power on/off GPGPU slices in Gen8 and Gen9. This is helpful
> in performance investigations amd checking scalability across
> hw platforms.
> 
> Change-Id: I4f2fe5fefb8d1df4519fd0eb58237759c7d1a930
> Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
> CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> CC: Zhipeng Gong <zhipeng.gong@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c      | 36 +++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  drivers/gpu/drm/i915/intel_device_info.c |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
>  4 files changed, 39 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d689e51..977bdb03 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4812,6 +4812,39 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
>  	{"i915_drrs_status", i915_drrs_status, 0},
>  	{"i915_rps_boost_info", i915_rps_boost_info, 0},
>  };
> +
> +static int
> +i915_slice_enabled_get(void *data, u64 *val)
> +{
> +	struct drm_device *dev = data;

? data is the drm_i915_private pointer.

> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
> +	*val = INTEL_INFO(dev_priv)->sseu.slice_enabled;
> +	return 0;
> +}
> +
> +static int
> +i915_slice_enabled_set(void *data, u64 val)
> +{
> +	struct drm_device *dev = data;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_device_info *info;
> +
> +	info = mkwrite_device_info(dev_priv);
> +	if (!IS_SKYLAKE(dev_priv) || !info->sseu.has_slice_pg)
> +		return -EINVAL;
> +
> +	if (val > hweight8(info->sseu.slice_mask))
> +		return -EINVAL;
> +
> +	info->sseu.slice_enabled = (u8)val;

Why the explicit cast?

> +	return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(i915_slice_enabled_fops,
> +			i915_slice_enabled_get, i915_slice_enabled_set,
> +			"%llu\n");
> +
>  #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>  
>  static const struct i915_debugfs_files {
> @@ -4839,7 +4872,8 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
>  	{"i915_dp_test_type", &i915_displayport_test_type_fops},
>  	{"i915_dp_test_active", &i915_displayport_test_active_fops},
>  	{"i915_guc_log_control", &i915_guc_log_control_fops},
> -	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
> +	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
> +	{"i915_slice_enabled", &i915_slice_enabled_fops}
>  };
>  
>  int i915_debugfs_register(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bb6fc1e..7455d43 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -852,6 +852,7 @@ struct sseu_dev_info {
>  	u8 has_slice_pg:1;
>  	u8 has_subslice_pg:1;
>  	u8 has_eu_pg:1;
> +	u8 slice_enabled;
>  };
>  
>  static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7d01dfe..2eee76b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -412,6 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  		gen9_sseu_info_init(dev_priv);
>  
>  	info->has_snoop = !info->has_llc;
> +	info->sseu.slice_enabled = hweight8(info->sseu.slice_mask);
>  
>  	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
>  	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0dc1cc4..bc650df 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1732,7 +1732,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
>  	 * No explicit RPCS request is needed to ensure full
>  	 * slice/subslice/EU enablement prior to Gen9.
>  	*/
> -	if (INTEL_GEN(dev_priv) < 9)
> +	if (INTEL_GEN(dev_priv) < 8)

Unrelated?

>  		return 0;
>  
>  	/*
> @@ -1743,7 +1743,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
>  	*/
>  	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
>  		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> -		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
> +		rpcs |= INTEL_INFO(dev_priv)->sseu.slice_enabled <<
>  			GEN8_RPCS_S_CNT_SHIFT;

logical_xcs_ring_init() is never called after debugfs is registered.
What is the connection to the debugfs interface?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: add slice shutdown debugfs interface
  2017-04-07 10:41 [RFC] drm/i915: add slice shutdown debugfs interface Dmitry Rogozhkin
  2017-04-07 18:50 ` Chris Wilson
@ 2017-04-07 19:06 ` Patchwork
  1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-04-07 19:06 UTC (permalink / raw)
  To: Rogozhkin, Dmitry V; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: add slice shutdown debugfs interface
URL   : https://patchwork.freedesktop.org/series/22694/
State : success

== Summary ==

Series 22694v1 drm/i915: add slice shutdown debugfs interface
https://patchwork.freedesktop.org/api/1.0/series/22694/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test kms_frontbuffer_tracking:
        Subgroup basic:
                none       -> INCOMPLETE (fi-byt-n2820)
                none       -> INCOMPLETE (fi-bxt-j4205)

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u     total:215  pass:206  dwarn:0   dfail:0   fail:0   skip:8  
fi-bdw-gvtdvm    total:215  pass:203  dwarn:2   dfail:0   fail:0   skip:9  
fi-bsw-n3050     total:215  pass:194  dwarn:0   dfail:0   fail:0   skip:20 
fi-bxt-j4205     total:215  pass:198  dwarn:0   dfail:0   fail:0   skip:16 
fi-byt-j1900     total:215  pass:199  dwarn:0   dfail:0   fail:0   skip:15 
fi-byt-n2820     total:215  pass:195  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770      total:215  pass:201  dwarn:0   dfail:0   fail:0   skip:13 
fi-hsw-4770r     total:215  pass:201  dwarn:0   dfail:0   fail:0   skip:13 
fi-ilk-650       total:215  pass:177  dwarn:0   dfail:0   fail:0   skip:37 
fi-ivb-3520m     total:215  pass:201  dwarn:0   dfail:0   fail:0   skip:13 
fi-ivb-3770      total:215  pass:201  dwarn:0   dfail:0   fail:0   skip:13 
fi-kbl-7500u     total:215  pass:199  dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-7560u     total:215  pass:206  dwarn:1   dfail:0   fail:0   skip:7  
fi-skl-6260u     total:215  pass:207  dwarn:0   dfail:0   fail:0   skip:7  
fi-skl-6700hq    total:215  pass:199  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700k     total:215  pass:199  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6770hq    total:215  pass:207  dwarn:0   dfail:0   fail:0   skip:7  
fi-skl-gvtdvm    total:215  pass:206  dwarn:0   dfail:0   fail:0   skip:8  
fi-snb-2520m     total:215  pass:196  dwarn:0   dfail:0   fail:0   skip:18 
fi-snb-2600      total:215  pass:195  dwarn:0   dfail:0   fail:1   skip:18 

c9c537bbdea40e52ffd1e144edd3a915f8e8572f drm-tip: 2017y-04m-07d-17h-50m-41s UTC integration manifest
fbd2cef drm/i915: add slice shutdown debugfs interface

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4446/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [RFC] drm/i915: add slice shutdown debugfs interface
  2017-04-07 18:50 ` Chris Wilson
@ 2017-04-07 19:11   ` Dmitry Rogozhkin
  2017-04-07 19:41     ` Chris Wilson
  0 siblings, 1 reply; 5+ messages in thread
From: Dmitry Rogozhkin @ 2017-04-07 19:11 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx



On 4/7/2017 11:50 AM, Chris Wilson wrote:
> On Fri, Apr 07, 2017 at 03:41:41AM -0700, Dmitry Rogozhkin wrote:
>> Slice shutdown override interface (i915_slice_enabled) permits
>> to power on/off GPGPU slices in Gen8 and Gen9. This is helpful
>> in performance investigations amd checking scalability across
>> hw platforms.
>>
>> Change-Id: I4f2fe5fefb8d1df4519fd0eb58237759c7d1a930
>> Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
>> CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> CC: Zhipeng Gong <zhipeng.gong@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c      | 36 +++++++++++++++++++++++++++++++-
>>   drivers/gpu/drm/i915/i915_drv.h          |  1 +
>>   drivers/gpu/drm/i915/intel_device_info.c |  1 +
>>   drivers/gpu/drm/i915/intel_lrc.c         |  4 ++--
>>   4 files changed, 39 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index d689e51..977bdb03 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -4812,6 +4812,39 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
>>   	{"i915_drrs_status", i915_drrs_status, 0},
>>   	{"i915_rps_boost_info", i915_rps_boost_info, 0},
>>   };
>> +
>> +static int
>> +i915_slice_enabled_get(void *data, u64 *val)
>> +{
>> +	struct drm_device *dev = data;
> ? data is the drm_i915_private pointer.
noted. just saw your patch on that in the list for guc. will change.
>
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +
>> +	*val = INTEL_INFO(dev_priv)->sseu.slice_enabled;
>> +	return 0;
>> +}
>> +
>> +static int
>> +i915_slice_enabled_set(void *data, u64 val)
>> +{
>> +	struct drm_device *dev = data;
>> +	struct drm_i915_private *dev_priv = to_i915(dev);
>> +	struct intel_device_info *info;
>> +
>> +	info = mkwrite_device_info(dev_priv);
>> +	if (!IS_SKYLAKE(dev_priv) || !info->sseu.has_slice_pg)
>> +		return -EINVAL;
>> +
>> +	if (val > hweight8(info->sseu.slice_mask))
>> +		return -EINVAL;
>> +
>> +	info->sseu.slice_enabled = (u8)val;
> Why the explicit cast?
>> +	return 0;
>> +}
>> +
>> +DEFINE_SIMPLE_ATTRIBUTE(i915_slice_enabled_fops,
>> +			i915_slice_enabled_get, i915_slice_enabled_set,
>> +			"%llu\n");
>> +
>>   #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>>   
>>   static const struct i915_debugfs_files {
>> @@ -4839,7 +4872,8 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
>>   	{"i915_dp_test_type", &i915_displayport_test_type_fops},
>>   	{"i915_dp_test_active", &i915_displayport_test_active_fops},
>>   	{"i915_guc_log_control", &i915_guc_log_control_fops},
>> -	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
>> +	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
>> +	{"i915_slice_enabled", &i915_slice_enabled_fops}
>>   };
>>   
>>   int i915_debugfs_register(struct drm_i915_private *dev_priv)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index bb6fc1e..7455d43 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -852,6 +852,7 @@ struct sseu_dev_info {
>>   	u8 has_slice_pg:1;
>>   	u8 has_subslice_pg:1;
>>   	u8 has_eu_pg:1;
>> +	u8 slice_enabled;
>>   };
>>   
>>   static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 7d01dfe..2eee76b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -412,6 +412,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>   		gen9_sseu_info_init(dev_priv);
>>   
>>   	info->has_snoop = !info->has_llc;
>> +	info->sseu.slice_enabled = hweight8(info->sseu.slice_mask);
>>   
>>   	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
>>   	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 0dc1cc4..bc650df 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1732,7 +1732,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
>>   	 * No explicit RPCS request is needed to ensure full
>>   	 * slice/subslice/EU enablement prior to Gen9.
>>   	*/
>> -	if (INTEL_GEN(dev_priv) < 9)
>> +	if (INTEL_GEN(dev_priv) < 8)
> Unrelated?
Directly related. BDW also permits to program number of powered-on 
slices, but since (as written in the comment) by default all slices are 
enabled, there was no need to execute the below code. But if you want to 
switch slices on/off, you need to run it.
>
>>   		return 0;
>>   
>>   	/*
>> @@ -1743,7 +1743,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
>>   	*/
>>   	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
>>   		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
>> -		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
>> +		rpcs |= INTEL_INFO(dev_priv)->sseu.slice_enabled <<
>>   			GEN8_RPCS_S_CNT_SHIFT;
> logical_xcs_ring_init() is never called after debugfs is registered.
> What is the connection to the debugfs interface?
For some reason Git incorrectly identifies in which function the change 
was done. I did not touch logical_xcs_ring_init(), I have modified 
make_rpcs(). So once user executes 'echo 2 > 
/sys/kernel/debug/dri/0/i915_slice_enabled' he will notice changes in 
slice configuration once he will run some workload getting use of RCS 
engine. Changes will be seen in /sys/kernel/debug/dri/0/i915_sseu_status.
> -Chris
>

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [RFC] drm/i915: add slice shutdown debugfs interface
  2017-04-07 19:11   ` Dmitry Rogozhkin
@ 2017-04-07 19:41     ` Chris Wilson
  0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2017-04-07 19:41 UTC (permalink / raw)
  To: Dmitry Rogozhkin; +Cc: intel-gfx

On Fri, Apr 07, 2017 at 12:11:18PM -0700, Dmitry Rogozhkin wrote:
> 
> 
> On 4/7/2017 11:50 AM, Chris Wilson wrote:
> >On Fri, Apr 07, 2017 at 03:41:41AM -0700, Dmitry Rogozhkin wrote:
> >>Slice shutdown override interface (i915_slice_enabled) permits
> >>to power on/off GPGPU slices in Gen8 and Gen9. This is helpful
> >>in performance investigations amd checking scalability across
> >>hw platforms.

A comment (both here in the changelog and debugfs) to say that this will
effect any lrc created after the write would be nice (and not affect
older ones) and might help prevent some confusion in future.

> >>diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> >>index 0dc1cc4..bc650df 100644
> >>--- a/drivers/gpu/drm/i915/intel_lrc.c
> >>+++ b/drivers/gpu/drm/i915/intel_lrc.c
> >>@@ -1732,7 +1732,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
> >>  	 * No explicit RPCS request is needed to ensure full
> >>  	 * slice/subslice/EU enablement prior to Gen9.
> >>  	*/
> >>-	if (INTEL_GEN(dev_priv) < 9)
> >>+	if (INTEL_GEN(dev_priv) < 8)
> >Unrelated?
> Directly related. BDW also permits to program number of powered-on
> slices, but since (as written in the comment) by default all slices
> are enabled, there was no need to execute the below code. But if you
> want to switch slices on/off, you need to run it.

Ok, looks like we set has_slice_pg on bdw, so this will change the
currently executed code. Please make the changes to make_rpcs as a
seperate patch so we can check/bisect to this if required.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-04-07 19:41 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-07 10:41 [RFC] drm/i915: add slice shutdown debugfs interface Dmitry Rogozhkin
2017-04-07 18:50 ` Chris Wilson
2017-04-07 19:11   ` Dmitry Rogozhkin
2017-04-07 19:41     ` Chris Wilson
2017-04-07 19:06 ` ✓ Fi.CI.BAT: success for " Patchwork

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