* [U-Boot] [PATCH v5 1/3] sunxi: add basic V3s support
2017-04-08 7:30 [U-Boot] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL) Icenowy Zheng
@ 2017-04-08 7:30 ` Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 2/3] sunxi: add DTSI file for V3s Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero Icenowy Zheng
2 siblings, 0 replies; 5+ messages in thread
From: Icenowy Zheng @ 2017-04-08 7:30 UTC (permalink / raw)
To: u-boot
From: Icenowy Zheng <icenowy@aosc.xyz>
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
---
Changes in v5:
- Fixed the regression that A64 cannot build after applying this patch.
(Added BOOTM_SIZE for 64-bit environment)
- Rebased on current sunxi/next.
Changes in v4:
- Enable PSCI for the SoC. (For virtualization support, although it
seems to be a joke to use virtualization on systems with 64MiB DRAM)
- Add Maxime's ACK and Jagan's Reviewed-By.
Changes in v3:
- Remove some dead codes.
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/board.c | 4 ++++
arch/arm/mach-sunxi/cpu_info.c | 2 ++
board/sunxi/Kconfig | 15 +++++++++++++--
include/configs/sun8i.h | 2 ++
include/configs/sunxi-common.h | 29 +++++++++++++++++++++++++++--
6 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 85a4ec3b0e..24f85206c8 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -161,6 +161,7 @@ enum sunxi_gpio_number {
#define SUN8I_GPB_UART2 2
#define SUN8I_A33_GPB_UART0 3
#define SUN8I_A83T_GPB_UART0 2
+#define SUN8I_V3S_GPB_UART0 3
#define SUN50I_GPB_UART0 4
#define SUNXI_GPC_NAND 2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 5e03d03943..4a8b52389e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -110,6 +110,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index 85633ccec2..46a51c6659 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -87,6 +87,8 @@ int print_cpuinfo(void)
printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_H3
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V3S
+ printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 32b2e3e2c0..5670ce42f3 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -132,6 +132,15 @@ config MACH_SUN8I_H3
select MACH_SUNXI_H3_H5
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_V3S
+ bool "sun8i (Allwinner V3s)"
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
+ select SUNXI_GEN_SUN6I
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -157,7 +166,8 @@ endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T
+ default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || \
+ MACH_SUN8I_A83T || MACH_SUN8I_V3S
config RESERVE_ALLWINNER_BOOT0_HEADER
bool "reserve space for Allwinner boot0 header"
@@ -517,7 +527,8 @@ config AXP_GPIO
config VIDEO
bool "Enable graphical uboot console on HDMI, LCD or VGA"
- depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
+ depends on !MACH_SUN8I_A83T && !MACH_SUN8I_V3S && \
+ !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index a4c3fb69e4..6ac42acaea 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -21,6 +21,8 @@
#define CONFIG_SUNXI_USB_PHYS 4
#elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS 3
+#elif defined CONFIG_MACH_SUN8I_V3S
+ #define CONFIG_SUNXI_USB_PHYS 1
#else
#define CONFIG_SUNXI_USB_PHYS 2
#endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 67e1465b69..6e4acbf617 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -76,7 +76,12 @@
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
+/* V3s do not have enough memory to place code at 0x4a000000 */
+#ifndef CONFIG_MACH_SUN8I_V3S
#define CONFIG_SYS_TEXT_BASE 0x4a000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x42e00000
+#endif
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
* since it needs to fit in with the other values. By also #defining it
* we get warnings if the Kconfig value mismatches. */
@@ -153,8 +158,13 @@
#define CONFIG_ENV_SIZE (128 << 10)
#endif
+#ifndef CONFIG_MACH_SUN8I_V3S
/* 64MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
+#else
+/* 2MB of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20))
+#endif
/*
* Miscellaneous configurable options
@@ -353,6 +363,7 @@ extern int soft_i2c_gpio_scl;
* Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
* Align the initrd to a 2MB page.
*/
+#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000))
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000))
@@ -365,16 +376,30 @@ extern int soft_i2c_gpio_scl;
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
-
+#ifndef CONFIG_MACH_SUN8I_V3S
+#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#else
+/*
+ * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
+ * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk@the end.
+ */
+#define BOOTM_SIZE __stringify(0x2e00000)
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
+#endif
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0xa000000\0" \
+ "bootm_size=" BOOTM_SIZE "\0" \
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
"fdt_addr_r=" FDT_ADDR_R "\0" \
"scriptaddr=" SCRIPT_ADDR_R "\0" \
--
2.12.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [U-Boot] [PATCH v5 2/3] sunxi: add DTSI file for V3s
2017-04-08 7:30 [U-Boot] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL) Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 1/3] sunxi: add basic V3s support Icenowy Zheng
@ 2017-04-08 7:30 ` Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero Icenowy Zheng
2 siblings, 0 replies; 5+ messages in thread
From: Icenowy Zheng @ 2017-04-08 7:30 UTC (permalink / raw)
To: u-boot
From: Icenowy Zheng <icenowy@aosc.xyz>
As we have now V3s support in board code, the V3s DTSI file should also
be added.
Add also some CCU include headers to satisfy the DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Changes in v4:
- Add Maxime's ACK.
arch/arm/dts/sun8i-v3s.dtsi | 284 ++++++++++++++++++++++++++++++
include/dt-bindings/clock/sun8i-v3s-ccu.h | 107 +++++++++++
include/dt-bindings/reset/sun8i-v3s-ccu.h | 78 ++++++++
3 files changed, 469 insertions(+)
create mode 100644 arch/arm/dts/sun8i-v3s.dtsi
create mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
new file mode 100644
index 0000000000..ebefc0fefe
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_CPU>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mmc0: mmc at 01c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc at 01c10000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc at 01c11000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb at 01c19000 {
+ compatible = "allwinner,sun8i-h3-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
+ usbphy: phy at 01c19400 {
+ compatible = "allwinner,sun8i-v3s-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ccu: clock at 01c20000 {
+ compatible = "allwinner,sun8i-v3s-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc at 01c20400 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01c20400 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pio: pinctrl at 01c20800 {
+ compatible = "allwinner,sun8i-v3s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ uart0_pins_a: uart0 at 0 {
+ pins = "PB8", "PB9";
+ function = "uart0";
+ bias-pull-up;
+ };
+
+ mmc0_pins_a: mmc0 at 0 {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+ };
+
+ timer at 01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog at 01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial at 01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial at 01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial at 01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at 01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
new file mode 100644
index 0000000000..c0d5d5599c
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-ccu.h, which is:
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
+#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
+
+#define CLK_CPU 14
+
+#define CLK_BUS_CE 20
+#define CLK_BUS_DMA 21
+#define CLK_BUS_MMC0 22
+#define CLK_BUS_MMC1 23
+#define CLK_BUS_MMC2 24
+#define CLK_BUS_DRAM 25
+#define CLK_BUS_EMAC 26
+#define CLK_BUS_HSTIMER 27
+#define CLK_BUS_SPI0 28
+#define CLK_BUS_OTG 29
+#define CLK_BUS_EHCI0 30
+#define CLK_BUS_OHCI0 31
+#define CLK_BUS_VE 32
+#define CLK_BUS_TCON0 33
+#define CLK_BUS_CSI 34
+#define CLK_BUS_DE 35
+#define CLK_BUS_CODEC 36
+#define CLK_BUS_PIO 37
+#define CLK_BUS_I2C0 38
+#define CLK_BUS_I2C1 39
+#define CLK_BUS_UART0 40
+#define CLK_BUS_UART1 41
+#define CLK_BUS_UART2 42
+#define CLK_BUS_EPHY 43
+#define CLK_BUS_DBG 44
+
+#define CLK_MMC0 45
+#define CLK_MMC0_SAMPLE 46
+#define CLK_MMC0_OUTPUT 47
+#define CLK_MMC1 48
+#define CLK_MMC1_SAMPLE 49
+#define CLK_MMC1_OUTPUT 50
+#define CLK_MMC2 51
+#define CLK_MMC2_SAMPLE 52
+#define CLK_MMC2_OUTPUT 53
+#define CLK_CE 54
+#define CLK_SPI0 55
+#define CLK_USB_PHY0 56
+#define CLK_USB_OHCI0 57
+
+#define CLK_DRAM_VE 59
+#define CLK_DRAM_CSI 60
+#define CLK_DRAM_EHCI 61
+#define CLK_DRAM_OHCI 62
+#define CLK_DE 63
+#define CLK_TCON0 64
+#define CLK_CSI_MISC 65
+#define CLK_CSI0_MCLK 66
+#define CLK_CSI1_SCLK 67
+#define CLK_CSI1_MCLK 68
+#define CLK_VE 69
+#define CLK_AC_DIG 70
+#define CLK_AVS 71
+
+#define CLK_MIPI_CSI 73
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
new file mode 100644
index 0000000000..b58ef21a2e
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-v3s-ccu.h, which is
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
+#define _DT_BINDINGS_RST_SUN8I_V3S_H_
+
+#define RST_USB_PHY0 0
+
+#define RST_MBUS 1
+
+#define RST_BUS_CE 5
+#define RST_BUS_DMA 6
+#define RST_BUS_MMC0 7
+#define RST_BUS_MMC1 8
+#define RST_BUS_MMC2 9
+#define RST_BUS_DRAM 11
+#define RST_BUS_EMAC 12
+#define RST_BUS_HSTIMER 14
+#define RST_BUS_SPI0 15
+#define RST_BUS_OTG 17
+#define RST_BUS_EHCI0 18
+#define RST_BUS_OHCI0 22
+#define RST_BUS_VE 26
+#define RST_BUS_TCON0 27
+#define RST_BUS_CSI 30
+#define RST_BUS_DE 34
+#define RST_BUS_DBG 38
+#define RST_BUS_EPHY 39
+#define RST_BUS_CODEC 40
+#define RST_BUS_I2C0 46
+#define RST_BUS_I2C1 47
+#define RST_BUS_UART0 49
+#define RST_BUS_UART1 50
+#define RST_BUS_UART2 51
+
+#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
--
2.12.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [U-Boot] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero
2017-04-08 7:30 [U-Boot] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL) Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 1/3] sunxi: add basic V3s support Icenowy Zheng
2017-04-08 7:30 ` [U-Boot] [PATCH v5 2/3] sunxi: add DTSI file for V3s Icenowy Zheng
@ 2017-04-08 7:30 ` Icenowy Zheng
2 siblings, 0 replies; 5+ messages in thread
From: Icenowy Zheng @ 2017-04-08 7:30 UTC (permalink / raw)
To: u-boot
From: Icenowy Zheng <icenowy@aosc.xyz>
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v4:
- Removed NONSEC disabling for Lichee Pi Zero board.
- Enriched commit message.
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83 ++++++++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 ++
configs/LicheePi_Zero_defconfig | 12 +++++
4 files changed, 104 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
create mode 100644 configs/LicheePi_Zero_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eafc661da1..6d918a6750 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -295,7 +295,10 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-neo.dtb \
- sun8i-h3-nanopi-neo-air.dtb
+ sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-neo.dtb
+dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
new file mode 100644
index 0000000000..3d9168cbae
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-v3s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Lichee Pi Zero";
+ compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-names = "default";
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 91ca6eaf7a..04e19daee1 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -182,6 +182,11 @@ M: Jelle de Jong <jelledejong@powercraft.nl>
S: Maintained
F: configs/Lamobo_R1_defconfig
+LICHEEPI-ZERO BOARD
+M: Icenowy Zheng <icenowy@aosc.xyz>
+S: Maintained
+F: configs/LicheePi_Zero_defconfig
+
LINKSPRITE-PCDUINO BOARD
M: Zoltan Herpai <wigyori@uid0.hu>
S: Maintained
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
new file mode 100644
index 0000000000..c147084849
--- /dev/null
+++ b/configs/LicheePi_Zero_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_V3S=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=14779
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_NETDEVICES is not set
--
2.12.2
^ permalink raw reply related [flat|nested] 5+ messages in thread