* [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1
@ 2017-04-08 12:10 Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 2/7] can: m_can: Removed initialization of FIFO water marks Mario Hüttel
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
* Disabled interrupt line 1. The driver didn't use it.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 7a6554e..6797977 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -349,7 +349,8 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
{
- m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
+ /* Only interrupt line 0 is used in this driver */
+ m_can_write(priv, M_CAN_ILE, ILE_EINT0);
}
static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 2/7] can: m_can: Removed initialization of FIFO water marks
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 3/7] can: m_can: Removed virtual address from print Mario Hüttel
` (4 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
FIFO water marks disabled because the driver doesn't handle water mark events.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 6797977..ddcbe8b 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -864,11 +864,11 @@ static void m_can_chip_config(struct net_device *dev)
/* rx fifo configuration, blocking mode, fifo size 1 */
m_can_write(priv, M_CAN_RXF0C,
(priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
- RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
+ priv->mcfg[MRAM_RXF0].off);
m_can_write(priv, M_CAN_RXF1C,
(priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
- RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
+ priv->mcfg[MRAM_RXF1].off);
cccr = m_can_read(priv, M_CAN_CCCR);
cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 3/7] can: m_can: Removed virtual address from print
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 2/7] can: m_can: Removed initialization of FIFO water marks Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 4/7] can: m_can: Updated register defines to newest version Mario Hüttel
` (3 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
The virtual address of the device was printed. I removed it
because it leaks internal information.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index ddcbe8b..a966ed5 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -1231,8 +1231,8 @@ static int m_can_plat_probe(struct platform_device *pdev)
devm_can_led_init(dev);
- dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
- KBUILD_MODNAME, priv->base, dev->irq);
+ dev_info(&pdev->dev, "%s device registered (irq=%d)\n",
+ KBUILD_MODNAME, dev->irq);
return 0;
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 4/7] can: m_can: Updated register defines to newest version
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 2/7] can: m_can: Removed initialization of FIFO water marks Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 3/7] can: m_can: Removed virtual address from print Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 5/7] can: m_can: Enable M_CAN version dependent initialization Mario Hüttel
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
* Updated register defines to newest M_CAN version (v3.2.1).
* Changed defines in the whole code.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 190 +++++++++++++++++++++++++++---------------
1 file changed, 125 insertions(+), 65 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index a966ed5..15b5e1a 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -37,17 +37,19 @@ enum m_can_reg {
M_CAN_CREL = 0x0,
M_CAN_ENDN = 0x4,
M_CAN_CUST = 0x8,
- M_CAN_FBTP = 0xc,
+ M_CAN_DBTP = 0xc,
M_CAN_TEST = 0x10,
M_CAN_RWD = 0x14,
M_CAN_CCCR = 0x18,
- M_CAN_BTP = 0x1c,
+ M_CAN_NBTP = 0x1c,
M_CAN_TSCC = 0x20,
M_CAN_TSCV = 0x24,
M_CAN_TOCC = 0x28,
M_CAN_TOCV = 0x2c,
M_CAN_ECR = 0x40,
M_CAN_PSR = 0x44,
+/* TDCR Register only available for version >=3.1.x */
+ M_CAN_TDCR = 0x48,
M_CAN_IR = 0x50,
M_CAN_IE = 0x54,
M_CAN_ILS = 0x58,
@@ -105,21 +107,21 @@ enum m_can_mram_cfg {
MRAM_CFG_NUM,
};
-/* Fast Bit Timing & Prescaler Register (FBTP) */
-#define FBTR_FBRP_MASK 0x1f
-#define FBTR_FBRP_SHIFT 16
-#define FBTR_FTSEG1_SHIFT 8
-#define FBTR_FTSEG1_MASK (0xf << FBTR_FTSEG1_SHIFT)
-#define FBTR_FTSEG2_SHIFT 4
-#define FBTR_FTSEG2_MASK (0x7 << FBTR_FTSEG2_SHIFT)
-#define FBTR_FSJW_SHIFT 0
-#define FBTR_FSJW_MASK 0x3
+/* Data Bit Timing & Prescaler Register (DBTP) */
+#define DBTP_TDC BIT(23)
+#define DBTP_DBRP_SHIFT 16
+#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
+#define DBTP_DTSEG1_SHIFT 8
+#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
+#define DBTP_DTSEG2_SHIFT 4
+#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
+#define DBTP_DSJW_SHIFT 0
+#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
/* Test Register (TEST) */
-#define TEST_LBCK BIT(4)
+#define TEST_LBCK BIT(4)
/* CC Control Register(CCCR) */
-#define CCCR_TEST BIT(7)
#define CCCR_CMR_MASK 0x3
#define CCCR_CMR_SHIFT 10
#define CCCR_CMR_CANFD 0x1
@@ -130,21 +132,32 @@ enum m_can_mram_cfg {
#define CCCR_CME_CAN 0
#define CCCR_CME_CANFD 0x1
#define CCCR_CME_CANFD_BRS 0x2
+#define CCCR_TXP BIT(14)
#define CCCR_TEST BIT(7)
#define CCCR_MON BIT(5)
+#define CCCR_CSR BIT(4)
+#define CCCR_CSA BIT(3)
+#define CCCR_ASM BIT(2)
#define CCCR_CCE BIT(1)
#define CCCR_INIT BIT(0)
#define CCCR_CANFD 0x10
-
-/* Bit Timing & Prescaler Register (BTP) */
-#define BTR_BRP_MASK 0x3ff
-#define BTR_BRP_SHIFT 16
-#define BTR_TSEG1_SHIFT 8
-#define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
-#define BTR_TSEG2_SHIFT 4
-#define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
-#define BTR_SJW_SHIFT 0
-#define BTR_SJW_MASK 0xf
+/* for version >=3.1.x */
+#define CCCR_EFBI BIT(13)
+#define CCCR_PXHD BIT(12)
+#define CCCR_BRSE BIT(9)
+#define CCCR_FDOE BIT(8)
+/* only for version >=3.2.x */
+#define CCCR_NISO BIT(15)
+
+/* Nominal Bit Timing & Prescaler Register (NBTP) */
+#define NBTP_NSJW_SHIFT 25
+#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
+#define NBTP_NBRP_SHIFT 16
+#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
+#define NBTP_NTSEG1_SHIFT 8
+#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
+#define NBTP_NTSEG2_SHIFT 0
+#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
/* Error Counter Register(ECR) */
#define ECR_RP BIT(15)
@@ -161,6 +174,13 @@ enum m_can_mram_cfg {
/* Interrupt Register(IR) */
#define IR_ALL_INT 0xffffffff
+
+/* Renamed bits for versions > 3.1.x */
+#define IR_ARA BIT(29)
+#define IR_PED BIT(28)
+#define IR_PEA BIT(27)
+
+/* Bits for version 3.0.x */
#define IR_STE BIT(31)
#define IR_FOE BIT(30)
#define IR_ACKE BIT(29)
@@ -194,33 +214,40 @@ enum m_can_mram_cfg {
#define IR_RF0W BIT(1)
#define IR_RF0N BIT(0)
#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
-#define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
-#define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
+
+/* Interrupts for version 3.0.x */
+#define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
+#define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
+ IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
+ IR_RF1L | IR_RF0L)
+#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
+/* Interrupts for version >= 3.1.x */
+#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
+#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
IR_RF1L | IR_RF0L)
-#define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
+#define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
/* Interrupt Line Select (ILS) */
#define ILS_ALL_INT0 0x0
#define ILS_ALL_INT1 0xFFFFFFFF
/* Interrupt Line Enable (ILE) */
-#define ILE_EINT0 BIT(0)
#define ILE_EINT1 BIT(1)
+#define ILE_EINT0 BIT(0)
/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
-#define RXFC_FWM_OFF 24
-#define RXFC_FWM_MASK 0x7f
-#define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
-#define RXFC_FS_OFF 16
-#define RXFC_FS_MASK 0x7f
+#define RXFC_FWM_SHIFT 24
+#define RXFC_FWM_MASK (0x7f < RXFC_FWM_SHIFT)
+#define RXFC_FS_SHIFT 16
+#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
#define RXFS_RFL BIT(25)
#define RXFS_FF BIT(24)
-#define RXFS_FPI_OFF 16
+#define RXFS_FPI_SHIFT 16
#define RXFS_FPI_MASK 0x3f0000
-#define RXFS_FGI_OFF 8
+#define RXFS_FGI_SHIFT 8
#define RXFS_FGI_MASK 0x3f00
#define RXFS_FFL_MASK 0x7f
@@ -229,23 +256,46 @@ enum m_can_mram_cfg {
#define M_CAN_RXESC_64BYTES 0x777
/* Tx Buffer Configuration(TXBC) */
-#define TXBC_NDTB_OFF 16
-#define TXBC_NDTB_MASK 0x3f
+#define TXBC_NDTB_SHIFT 16
+#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
+#define TXBC_TFQS_SHIFT 24
+#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
+
+/* Tx FIFO/Queue Status (TXFQS) */
+#define TXFQS_TFQF BIT(21)
+#define TXFQS_TFQPI_SHIFT 16
+#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
+#define TXFQS_TFGI_SHIFT 8
+#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
+#define TXFQS_TFFL_SHIFT 0
+#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
/* Tx Buffer Element Size Configuration(TXESC) */
#define TXESC_TBDS_8BYTES 0x0
#define TXESC_TBDS_64BYTES 0x7
-/* Tx Event FIFO Con.guration (TXEFC) */
-#define TXEFC_EFS_OFF 16
-#define TXEFC_EFS_MASK 0x3f
+/* Tx Event FIFO Configuration (TXEFC) */
+#define TXEFC_EFS_SHIFT 16
+#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
+
+/* Tx Event FIFO Status (TXEFS) */
+#define TXEFS_TEFL BIT(25)
+#define TXEFS_EFF BIT(24)
+#define TXEFS_EFGI_SHIFT 8
+#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
+#define TXEFS_EFFL_SHIFT 0
+#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
+
+/* Tx Event FIFO Acknowledge (TXEFA) */
+#define TXEFA_EFAI_SHIFT 0
+#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
/* Message RAM Configuration (in bytes) */
#define SIDF_ELEMENT_SIZE 4
#define XIDF_ELEMENT_SIZE 8
#define RXF0_ELEMENT_SIZE 72
#define RXF1_ELEMENT_SIZE 72
-#define RXB_ELEMENT_SIZE 16
+#define RXB_ELEMENT_SIZE 72
#define TXE_ELEMENT_SIZE 8
#define TXB_ELEMENT_SIZE 72
@@ -261,13 +311,20 @@ enum m_can_mram_cfg {
#define RX_BUF_RTR BIT(29)
/* R1 */
#define RX_BUF_ANMF BIT(31)
-#define RX_BUF_EDL BIT(21)
+#define RX_BUF_FDF BIT(21)
#define RX_BUF_BRS BIT(20)
/* Tx Buffer Element */
-/* R0 */
+/* T0 */
+#define TX_BUF_ESI BIT(31)
#define TX_BUF_XTD BIT(30)
#define TX_BUF_RTR BIT(29)
+/* T1 */
+#define TX_BUF_EFC BIT(23)
+#define TX_BUF_FDF BIT(21)
+#define TX_BUF_BRS BIT(20)
+#define TX_BUF_MM_SHIFT 24
+#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
/* address offset and element number for each FIFO/Buffer in the Message RAM */
struct mram_cfg {
@@ -368,9 +425,9 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
int i;
/* calculate the fifo get index for where to read data */
- fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
+ fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
- if (dlc & RX_BUF_EDL)
+ if (dlc & RX_BUF_FDF)
skb = alloc_canfd_skb(dev, &cf);
else
skb = alloc_can_skb(dev, (struct can_frame **)&cf);
@@ -379,7 +436,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
return;
}
- if (dlc & RX_BUF_EDL)
+ if (dlc & RX_BUF_FDF)
cf->len = can_dlc2len((dlc >> 16) & 0x0F);
else
cf->len = get_can_dlc((dlc >> 16) & 0x0F);
@@ -395,7 +452,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
netdev_dbg(dev, "ESI Error\n");
}
- if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) {
+ if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
cf->can_id |= CAN_RTR_FLAG;
} else {
if (dlc & RX_BUF_BRS)
@@ -533,7 +590,7 @@ static int __m_can_get_berr_counter(const struct net_device *dev,
ecr = m_can_read(priv, M_CAN_ECR);
bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
- bec->txerr = ecr & ECR_TEC_MASK;
+ bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
return 0;
}
@@ -724,7 +781,7 @@ static int m_can_poll(struct napi_struct *napi, int quota)
if (irqstatus & IR_ERR_STATE)
work_done += m_can_handle_state_errors(dev, psr);
- if (irqstatus & IR_ERR_BUS)
+ if (irqstatus & IR_ERR_BUS_30X)
work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
if (irqstatus & IR_RF0N)
@@ -759,7 +816,7 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
* - state change IRQ
* - bus error IRQ and bus error reporting
*/
- if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
+ if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
priv->irqstatus = ir;
m_can_disable_all_interrupts(priv);
napi_schedule(&priv->napi);
@@ -812,19 +869,19 @@ static int m_can_set_bittiming(struct net_device *dev)
sjw = bt->sjw - 1;
tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
tseg2 = bt->phase_seg2 - 1;
- reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
- (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
- m_can_write(priv, M_CAN_BTP, reg_btp);
+ reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
+ (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
+ m_can_write(priv, M_CAN_NBTP, reg_btp);
if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
brp = dbt->brp - 1;
sjw = dbt->sjw - 1;
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
tseg2 = dbt->phase_seg2 - 1;
- reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) |
- (tseg1 << FBTR_FTSEG1_SHIFT) |
- (tseg2 << FBTR_FTSEG2_SHIFT);
- m_can_write(priv, M_CAN_FBTP, reg_btp);
+ reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
+ (tseg1 << DBTP_DTSEG1_SHIFT) |
+ (tseg2 << DBTP_DTSEG2_SHIFT);
+ m_can_write(priv, M_CAN_DBTP, reg_btp);
}
return 0;
@@ -852,22 +909,22 @@ static void m_can_chip_config(struct net_device *dev)
m_can_write(priv, M_CAN_GFC, 0x0);
/* only support one Tx Buffer currently */
- m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
+ m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
priv->mcfg[MRAM_TXB].off);
/* support 64 bytes payload */
m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
- m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
+ m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
priv->mcfg[MRAM_TXE].off);
/* rx fifo configuration, blocking mode, fifo size 1 */
m_can_write(priv, M_CAN_RXF0C,
- (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
+ (priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
priv->mcfg[MRAM_RXF0].off);
m_can_write(priv, M_CAN_RXF1C,
- (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
+ (priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
priv->mcfg[MRAM_RXF1].off);
cccr = m_can_read(priv, M_CAN_CCCR);
@@ -893,7 +950,7 @@ static void m_can_chip_config(struct net_device *dev)
/* enable interrupts */
m_can_write(priv, M_CAN_IR, IR_ALL_INT);
if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
- m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
+ m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC_30X);
else
m_can_write(priv, M_CAN_IE, IR_ALL_INT);
@@ -1144,10 +1201,12 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
priv->mcfg[MRAM_XIDF].num = out_val[2];
priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
- priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
+ priv->mcfg[MRAM_RXF0].num = out_val[3] &
+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
- priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
+ priv->mcfg[MRAM_RXF1].num = out_val[4] &
+ (RXFC_FS_MASK >> RXFC_FS_SHIFT);
priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
priv->mcfg[MRAM_RXB].num = out_val[5];
@@ -1156,7 +1215,8 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
priv->mcfg[MRAM_TXE].num = out_val[6];
priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
- priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
+ priv->mcfg[MRAM_TXB].num = out_val[7] &
+ (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
priv->mram_base,
@@ -1192,7 +1252,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
hclk = devm_clk_get(&pdev->dev, "hclk");
cclk = devm_clk_get(&pdev->dev, "cclk");
if (IS_ERR(hclk) || IS_ERR(cclk)) {
- dev_err(&pdev->dev, "no clock find\n");
+ dev_err(&pdev->dev, "no clock found\n");
return -ENODEV;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 5/7] can: m_can: Enable M_CAN version dependent initialization
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
` (2 preceding siblings ...)
2017-04-08 12:10 ` [PATCH v4 4/7] can: m_can: Updated register defines to newest version Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 6/7] can: m_can: Configuration for TX and TX event FIFOs Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x Mario Hüttel
5 siblings, 0 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
This patch adapts the initialization of the M_CAN. So it can be used with
all versions >= 3.0.x.
Changes:
* Added version element to m_can_priv structure to hold M_CAN version.
* Renamed bittiming structs for version 3.0.x
* Added new bittiming structs for version >= 3.1.x
* Function alloc_m_can_dev takes 2 new arguments. The TX FIFO size and the
base address of the module.
* Chip configuration for CAN_CTRLMODE_LOOPBACK is changed: Enabled
CCCR_MON bit. In combination with TEST_LBCK it activates the internal
loopback mode. Leaving CCCR_MON '0' results in external loopback mode.
* Clocks are temporarily enabled by platform_propbe function in order to
allow read access to the Core Release register and the Control Register.
Registers are used to detect M_CAN version and optional Non-ISO Feature.
Initialization of M_CAN for version >= 3.1.x:
* TX FIFO of M_CAN is used to transmit frames. The driver does not need to
stop the tx queue after each frame sent.
* Initialization of TX Event FIFO is added.
* NON-ISO is fixed for all M_CAN versions < 3.2.x. Version 3.2.x _can_ have
the NISO (Non-ISO) bit which can switch the mode of the M_CAN to Non-ISO
mode. This bit does not have to be writeable. Therefore it is checked.
If it is writable Non-ISO support is added to the controllers supported
CAN modes.
New Functions:
* Function to check the Core Release version. The read value determines the
behaviour of the driver.
* Function to check if the NISO bit for version >= 3.2.x is implemented.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 340 +++++++++++++++++++++++++++++++++---------
1 file changed, 269 insertions(+), 71 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 15b5e1a..6b36066 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -23,7 +23,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
-
+#include <linux/iopoll.h>
#include <linux/can/dev.h>
/* napi related */
@@ -107,6 +107,14 @@ enum m_can_mram_cfg {
MRAM_CFG_NUM,
};
+/* Core Release Register (CREL) */
+#define CREL_REL_SHIFT 28
+#define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
+#define CREL_STEP_SHIFT 24
+#define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
+#define CREL_SUBSTEP_SHIFT 20
+#define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
+
/* Data Bit Timing & Prescaler Register (DBTP) */
#define DBTP_TDC BIT(23)
#define DBTP_DBRP_SHIFT 16
@@ -342,6 +350,7 @@ struct m_can_priv {
struct clk *cclk;
void __iomem *base;
u32 irqstatus;
+ int version;
/* message ram configuration */
void __iomem *mram_base;
@@ -833,7 +842,7 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static const struct can_bittiming_const m_can_bittiming_const = {
+static const struct can_bittiming_const m_can_bittiming_const_30X = {
.name = KBUILD_MODNAME,
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
.tseg1_max = 64,
@@ -845,7 +854,7 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
.brp_inc = 1,
};
-static const struct can_bittiming_const m_can_data_bittiming_const = {
+static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
.name = KBUILD_MODNAME,
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
.tseg1_max = 16,
@@ -857,6 +866,30 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
.brp_inc = 1,
};
+static const struct can_bittiming_const m_can_bittiming_const_31X = {
+ .name = KBUILD_MODNAME,
+ .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
+ .tseg1_max = 256,
+ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
+ .tseg2_max = 128,
+ .sjw_max = 128,
+ .brp_min = 1,
+ .brp_max = 512,
+ .brp_inc = 1,
+};
+
+static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
+ .name = KBUILD_MODNAME,
+ .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
+ .tseg1_max = 32,
+ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
+ .tseg2_max = 16,
+ .sjw_max = 16,
+ .brp_min = 1,
+ .brp_max = 32,
+ .brp_inc = 1,
+};
+
static int m_can_set_bittiming(struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
@@ -928,29 +961,53 @@ static void m_can_chip_config(struct net_device *dev)
priv->mcfg[MRAM_RXF1].off);
cccr = m_can_read(priv, M_CAN_CCCR);
- cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
- (CCCR_CME_MASK << CCCR_CME_SHIFT));
test = m_can_read(priv, M_CAN_TEST);
test &= ~TEST_LBCK;
+ if (priv->version == 30) {
+ /* Version 3.0.x */
- if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
- cccr |= CCCR_MON;
+ cccr &= ~(CCCR_TEST | CCCR_MON |
+ (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
+ (CCCR_CME_MASK << CCCR_CME_SHIFT));
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
+ cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
+
+ } else {
+ /* Version 3.1.x or 3.2.x */
+ cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE);
+
+ /* Only 3.2.x has NISO Bit implemented */
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
+ cccr |= CCCR_NISO;
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
+ cccr |= (CCCR_BRSE | CCCR_FDOE);
+ }
+ /* Loopback Mode */
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
- cccr |= CCCR_TEST;
+ cccr |= CCCR_TEST | CCCR_MON;
test |= TEST_LBCK;
}
- if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
- cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
+ /* Enable Monitoring (all versions) */
+ if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
+ cccr |= CCCR_MON;
+ /* Write config */
m_can_write(priv, M_CAN_CCCR, cccr);
m_can_write(priv, M_CAN_TEST, test);
- /* enable interrupts */
+ /* Enable interrupts */
m_can_write(priv, M_CAN_IR, IR_ALL_INT);
if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
- m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC_30X);
+ if (priv->version == 30)
+ m_can_write(priv, M_CAN_IE, IR_ALL_INT &
+ ~(IR_ERR_LEC_30X));
+ else
+ m_can_write(priv, M_CAN_IE, IR_ALL_INT &
+ ~(IR_ERR_LEC_31X));
else
m_can_write(priv, M_CAN_IE, IR_ALL_INT);
@@ -994,33 +1051,140 @@ static void free_m_can_dev(struct net_device *dev)
free_candev(dev);
}
-static struct net_device *alloc_m_can_dev(void)
+/* Checks core release number of M_CAN
+ * returns 0 if an unsupported device is detected
+ * else it returns the release and step coded as:
+ * return value = 10 * <release> + 1 * <step>
+ */
+static int m_can_check_core_release(void * __iomem m_can_base)
+{
+ u32 crel_reg;
+ u8 rel;
+ u8 step;
+ int res;
+ struct m_can_priv temp_priv = {
+ .base = m_can_base
+ };
+
+ /* Read Core Release Version and split into version number
+ * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
+ */
+ crel_reg = m_can_read(&temp_priv, M_CAN_CREL);
+ rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
+ step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
+
+ if (rel == 3) {
+ /* M_CAN v3.x.y: create return value */
+ res = 30 + step;
+ } else {
+ /* Unsupported M_CAN version */
+ res = 0;
+ }
+
+ return res;
+}
+
+/* Selectable Non ISO support only in version 3.2.x
+ * This function checks if the bit is writable.
+ */
+static bool m_can_niso_supported(const struct m_can_priv *priv)
+{
+ u32 cccr_reg, cccr_poll;
+ int niso_timeout;
+
+ m_can_config_endisable(priv, true);
+ cccr_reg = m_can_read(priv, M_CAN_CCCR);
+ cccr_reg |= CCCR_NISO;
+ m_can_write(priv, M_CAN_CCCR, cccr_reg);
+
+ niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll,
+ (cccr_poll == cccr_reg), 0, 10);
+
+ /* Clear NISO */
+ cccr_reg &= ~(CCCR_NISO);
+ m_can_write(priv, M_CAN_CCCR, cccr_reg);
+
+ m_can_config_endisable(priv, false);
+
+ /* return false if time out (-ETIMEDOUT), else return true */
+ return !niso_timeout;
+}
+
+static struct net_device *alloc_m_can_dev(struct platform_device *pdev,
+ void __iomem *addr, u32 tx_fifo_size)
{
struct net_device *dev;
struct m_can_priv *priv;
+ int m_can_version;
+ unsigned int echo_buffer_count;
+
+ m_can_version = m_can_check_core_release(addr);
+ /* return if unsupported version */
+ if (!m_can_version) {
+ dev = NULL;
+ goto return_dev;
+ }
- dev = alloc_candev(sizeof(*priv), 1);
- if (!dev)
- return NULL;
+ /* If version < 3.1.x, then only one echo buffer is used */
+ echo_buffer_count = ((m_can_version == 30)
+ ? 1U
+ : (unsigned int)tx_fifo_size);
+ dev = alloc_candev(sizeof(*priv), echo_buffer_count);
+ if (!dev) {
+ dev = NULL;
+ goto return_dev;
+ }
priv = netdev_priv(dev);
netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
+ /* Shared properties of all M_CAN versions */
+ priv->version = m_can_version;
priv->dev = dev;
- priv->can.bittiming_const = &m_can_bittiming_const;
- priv->can.data_bittiming_const = &m_can_data_bittiming_const;
+ priv->base = addr;
priv->can.do_set_mode = m_can_set_mode;
priv->can.do_get_berr_counter = m_can_get_berr_counter;
- /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.1 */
- can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
-
- /* CAN_CTRLMODE_FD_NON_ISO can not be changed with M_CAN IP v3.0.1 */
+ /* Set M_CAN supported operations */
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
CAN_CTRLMODE_LISTENONLY |
CAN_CTRLMODE_BERR_REPORTING |
CAN_CTRLMODE_FD;
+ /* Set properties depending on M_CAN version */
+ switch (priv->version) {
+ case 30:
+ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
+ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
+ priv->can.bittiming_const = &m_can_bittiming_const_30X;
+ priv->can.data_bittiming_const =
+ &m_can_data_bittiming_const_30X;
+ break;
+ case 31:
+ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
+ can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
+ priv->can.bittiming_const = &m_can_bittiming_const_31X;
+ priv->can.data_bittiming_const =
+ &m_can_data_bittiming_const_31X;
+ break;
+ case 32:
+ priv->can.bittiming_const = &m_can_bittiming_const_31X;
+ priv->can.data_bittiming_const =
+ &m_can_data_bittiming_const_31X;
+ priv->can.ctrlmode_supported |= (m_can_niso_supported(priv)
+ ? CAN_CTRLMODE_FD_NON_ISO
+ : 0);
+ break;
+ default:
+ /* Unsupported device: free candev */
+ free_m_can_dev(dev);
+ dev_err(&pdev->dev, "Unsupported version number: %2d",
+ priv->version);
+ dev = NULL;
+ break;
+ }
+
+return_dev:
return dev;
}
@@ -1167,58 +1331,37 @@ static int register_m_can_dev(struct net_device *dev)
return register_candev(dev);
}
-static int m_can_of_parse_mram(struct platform_device *pdev,
- struct m_can_priv *priv)
+static void m_can_of_parse_mram(struct m_can_priv *priv,
+ const u32 *mram_config_vals)
{
- struct device_node *np = pdev->dev.of_node;
- struct resource *res;
- void __iomem *addr;
- u32 out_val[MRAM_CFG_LEN];
- int i, start, end, ret;
+ int i, start, end;
- /* message ram could be shared */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
- if (!res)
- return -ENODEV;
-
- addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!addr)
- return -ENOMEM;
-
- /* get message ram configuration */
- ret = of_property_read_u32_array(np, "bosch,mram-cfg",
- out_val, sizeof(out_val) / 4);
- if (ret) {
- dev_err(&pdev->dev, "can not get message ram configuration\n");
- return -ENODEV;
- }
-
- priv->mram_base = addr;
- priv->mcfg[MRAM_SIDF].off = out_val[0];
- priv->mcfg[MRAM_SIDF].num = out_val[1];
+ priv->mcfg[MRAM_SIDF].off = mram_config_vals[0];
+ priv->mcfg[MRAM_SIDF].num = mram_config_vals[1];
priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
- priv->mcfg[MRAM_XIDF].num = out_val[2];
+ priv->mcfg[MRAM_XIDF].num = mram_config_vals[2];
priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
- priv->mcfg[MRAM_RXF0].num = out_val[3] &
+ priv->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
- priv->mcfg[MRAM_RXF1].num = out_val[4] &
+ priv->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
- priv->mcfg[MRAM_RXB].num = out_val[5];
+ priv->mcfg[MRAM_RXB].num = mram_config_vals[5];
priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
- priv->mcfg[MRAM_TXE].num = out_val[6];
+ priv->mcfg[MRAM_TXE].num = mram_config_vals[6];
priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
- priv->mcfg[MRAM_TXB].num = out_val[7] &
+ priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
- dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
+ dev_dbg(priv->device,
+ "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
priv->mram_base,
priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
@@ -1237,7 +1380,6 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
for (i = start; i < end; i += 4)
writel(0x0, priv->mram_base + i);
- return 0;
}
static int m_can_plat_probe(struct platform_device *pdev)
@@ -1246,38 +1388,86 @@ static int m_can_plat_probe(struct platform_device *pdev)
struct m_can_priv *priv;
struct resource *res;
void __iomem *addr;
+ void __iomem *mram_addr;
struct clk *hclk, *cclk;
int irq, ret;
+ struct device_node *np;
+ u32 mram_config_vals[MRAM_CFG_LEN];
+ u32 tx_fifo_size;
+
+ np = pdev->dev.of_node;
hclk = devm_clk_get(&pdev->dev, "hclk");
cclk = devm_clk_get(&pdev->dev, "cclk");
+
if (IS_ERR(hclk) || IS_ERR(cclk)) {
dev_err(&pdev->dev, "no clock found\n");
- return -ENODEV;
+ ret = -ENODEV;
+ goto failed_ret;
}
+ /* Enable clocks. Necessary to read Core Release in order to determine
+ * M_CAN version
+ */
+ ret = clk_prepare_enable(hclk);
+ if (ret)
+ goto disable_hclk_ret;
+
+ ret = clk_prepare_enable(cclk);
+ if (ret)
+ goto disable_cclk_ret;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
addr = devm_ioremap_resource(&pdev->dev, res);
irq = platform_get_irq_byname(pdev, "int0");
- if (IS_ERR(addr) || irq < 0)
- return -EINVAL;
- /* allocate the m_can device */
- dev = alloc_m_can_dev();
- if (!dev)
- return -ENOMEM;
+ if (IS_ERR(addr) || irq < 0) {
+ ret = -EINVAL;
+ goto disable_cclk_ret;
+ }
+ /* message ram could be shared */
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
+ if (!res) {
+ ret = -ENODEV;
+ goto disable_cclk_ret;
+ }
+
+ mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!mram_addr) {
+ ret = -ENOMEM;
+ goto disable_cclk_ret;
+ }
+
+ /* get message ram configuration */
+ ret = of_property_read_u32_array(np, "bosch,mram-cfg",
+ mram_config_vals,
+ sizeof(mram_config_vals) / 4);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not get Message RAM configuration.");
+ goto disable_cclk_ret;
+ }
+
+ /* Get TX FIFO size
+ * Defines the total amount of echo buffers for loopback
+ */
+ tx_fifo_size = mram_config_vals[7];
+
+ /* allocate the m_can device */
+ dev = alloc_m_can_dev(pdev, addr, tx_fifo_size);
+ if (!dev) {
+ ret = -ENOMEM;
+ goto disable_cclk_ret;
+ }
priv = netdev_priv(dev);
dev->irq = irq;
- priv->base = addr;
priv->device = &pdev->dev;
priv->hclk = hclk;
priv->cclk = cclk;
priv->can.clock.freq = clk_get_rate(cclk);
+ priv->mram_base = mram_addr;
- ret = m_can_of_parse_mram(pdev, priv);
- if (ret)
- goto failed_free_dev;
+ m_can_of_parse_mram(priv, mram_config_vals);
platform_set_drvdata(pdev, dev);
SET_NETDEV_DEV(dev, &pdev->dev);
@@ -1291,13 +1481,21 @@ static int m_can_plat_probe(struct platform_device *pdev)
devm_can_led_init(dev);
- dev_info(&pdev->dev, "%s device registered (irq=%d)\n",
- KBUILD_MODNAME, dev->irq);
+ dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n",
+ KBUILD_MODNAME, dev->irq, priv->version);
- return 0;
+ /* Probe finished
+ * Stop clocks. They will be reactivated once the M_CAN device is opened
+ */
+ goto disable_cclk_ret;
failed_free_dev:
free_m_can_dev(dev);
+disable_cclk_ret:
+ clk_disable_unprepare(cclk);
+disable_hclk_ret:
+ clk_disable_unprepare(hclk);
+failed_ret:
return ret;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 6/7] can: m_can: Configuration for TX and TX event FIFOs
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
` (3 preceding siblings ...)
2017-04-08 12:10 ` [PATCH v4 5/7] can: m_can: Enable M_CAN version dependent initialization Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x Mario Hüttel
5 siblings, 0 replies; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
* TX/TX Event FIFO sizes are configured for version >= v3.1.x
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 39 ++++++++++++++++++++++++++++++++++-----
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 6b36066..2fa0f44 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -382,6 +382,18 @@ static inline void m_can_fifo_write(const struct m_can_priv *priv,
fpi * TXB_ELEMENT_SIZE + offset);
}
+static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv,
+ u32 fgi,
+ u32 offset) {
+ return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off +
+ fgi * TXE_ELEMENT_SIZE + offset);
+}
+
+static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv)
+{
+ return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
+}
+
static inline void m_can_config_endisable(const struct m_can_priv *priv,
bool enable)
{
@@ -925,6 +937,7 @@ static int m_can_set_bittiming(struct net_device *dev)
* - configure rx fifo
* - accept non-matching frame into fifo 0
* - configure tx buffer
+ * - >= v3.1.x: TX FIFO is used
* - configure mode
* - setup bittiming
*/
@@ -941,15 +954,31 @@ static void m_can_chip_config(struct net_device *dev)
/* Accept Non-matching Frames Into FIFO 0 */
m_can_write(priv, M_CAN_GFC, 0x0);
- /* only support one Tx Buffer currently */
- m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
- priv->mcfg[MRAM_TXB].off);
+ if (priv->version == 30) {
+ /* only support one Tx Buffer currently */
+ m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
+ priv->mcfg[MRAM_TXB].off);
+ } else {
+ /* TX FIFO is used for newer IP Core versions */
+ m_can_write(priv, M_CAN_TXBC,
+ (priv->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
+ (priv->mcfg[MRAM_TXB].off));
+ }
/* support 64 bytes payload */
m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
- m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
- priv->mcfg[MRAM_TXE].off);
+ /* TX Event FIFO */
+ if (priv->version == 30) {
+ m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
+ priv->mcfg[MRAM_TXE].off);
+ } else {
+ /* Full TX Event FIFO is used */
+ m_can_write(priv, M_CAN_TXEFC,
+ ((priv->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
+ & TXEFC_EFS_MASK) |
+ priv->mcfg[MRAM_TXE].off);
+ }
/* rx fifo configuration, blocking mode, fifo size 1 */
m_can_write(priv, M_CAN_RXF0C,
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
` (4 preceding siblings ...)
2017-04-08 12:10 ` [PATCH v4 6/7] can: m_can: Configuration for TX and TX event FIFOs Mario Hüttel
@ 2017-04-08 12:10 ` Mario Hüttel
[not found] ` <1f88411b-aa58-4e17-02cb-43fc0ffb953c@Microchip.com>
5 siblings, 1 reply; 18+ messages in thread
From: Mario Hüttel @ 2017-04-08 12:10 UTC (permalink / raw)
To: linux-can; +Cc: Mario Huettel
From: Mario Huettel <mario.huettel@gmx.net>
* Added defines for TX Event FIFO Element
* Adapted ndo_start_xmit function.
For versions >= v3.1.x it uses the TX FIFO to optimize the data
throughput. It stores the echo skb at the same index as in the
M_CAN's TX FIFO. The frame's message marker is set to this index.
This message marker is received in the TX Event FIFO after
the message was successfully transmitted. It is used to echo the
correct echo skb back to the network stack.
* Added m_can_echo_tx_event function. It reads all received
message markers in the TX Event FIFO and loops back the
corresponding echo skbs.
* ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
---
drivers/net/can/m_can/m_can.c | 188 +++++++++++++++++++++++++++++++++++-------
1 file changed, 159 insertions(+), 29 deletions(-)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index 2fa0f44..5361e07 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -334,6 +334,11 @@ enum m_can_mram_cfg {
#define TX_BUF_MM_SHIFT 24
#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
+/* Tx event FIFO Element */
+/* E1 */
+#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
+#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
+
/* address offset and element number for each FIFO/Buffer in the Message RAM */
struct mram_cfg {
u16 off;
@@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi, int quota)
return work_done;
}
+static void m_can_echo_tx_event(struct net_device *dev)
+{
+ u32 txe_count = 0;
+ u32 m_can_txefs;
+ u32 fgi = 0;
+ int i = 0;
+ unsigned int msg_mark;
+
+ struct m_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+
+ /* read tx event fifo status */
+ m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
+
+ /* Get Tx Event fifo element count */
+ txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
+ >> TXEFS_EFFL_SHIFT;
+
+ /* Get and process all sent elements */
+ for (i = 0; i < txe_count; i++) {
+ /* retrieve get index */
+ fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
+ >> TXEFS_EFGI_SHIFT;
+
+ /* get message marker */
+ msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
+ TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
+
+ /* ack txe element */
+ m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
+ (fgi << TXEFA_EFAI_SHIFT)));
+
+ /* update stats */
+ stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
+ stats->tx_packets++;
+ }
+}
+
static irqreturn_t m_can_isr(int irq, void *dev_id)
{
struct net_device *dev = (struct net_device *)dev_id;
@@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
napi_schedule(&priv->napi);
}
- /* transmission complete interrupt */
- if (ir & IR_TC) {
- stats->tx_bytes += can_get_echo_skb(dev, 0);
- stats->tx_packets++;
- can_led_event(dev, CAN_LED_EVENT_TX);
- netif_wake_queue(dev);
+ if (priv->version == 30) {
+ if (ir & IR_TC) {
+ /* Transmission Complete Interrupt*/
+ stats->tx_bytes += can_get_echo_skb(dev, 0);
+ stats->tx_packets++;
+ can_led_event(dev, CAN_LED_EVENT_TX);
+ netif_wake_queue(dev);
+ }
+ } else {
+ if (ir & IR_TEFN) {
+ /* New TX FIFO Element arrived */
+ m_can_echo_tx_event(dev);
+ can_led_event(dev, CAN_LED_EVENT_TX);
+ if (netif_queue_stopped(dev) &&
+ !m_can_tx_fifo_full(priv))
+ netif_wake_queue(dev);
+ }
}
return IRQ_HANDLED;
@@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
return 0;
}
+static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
+{
+ struct m_can_priv *priv = netdev_priv(dev);
+ /*get wrap around for loopback skb index */
+ unsigned int wrap = priv->can.echo_skb_max;
+ int next_idx;
+
+ /* calculate next index */
+ next_idx = (++putidx >= wrap ? 0 : putidx);
+
+ /* check if occupied */
+ return !!priv->can.echo_skb[next_idx];
+}
+
static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
struct canfd_frame *cf = (struct canfd_frame *)skb->data;
- u32 id, cccr;
+ u32 id, cccr, fdflags;
int i;
+ int putidx;
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
- netif_stop_queue(dev);
-
+ /* Generate ID field for TX buffer Element */
+ /* Common to all supported M_CAN versions */
if (cf->can_id & CAN_EFF_FLAG) {
id = cf->can_id & CAN_EFF_MASK;
id |= TX_BUF_XTD;
@@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
if (cf->can_id & CAN_RTR_FLAG)
id |= TX_BUF_RTR;
- /* message ram configuration */
- m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
- m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
+ if (priv->version == 30) {
+ netif_stop_queue(dev);
+
+ /* message ram configuration */
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
+ can_len2dlc(cf->len) << 16);
- for (i = 0; i < cf->len; i += 4)
- m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
- *(u32 *)(cf->data + i));
+ for (i = 0; i < cf->len; i += 4)
+ m_can_fifo_write(priv, 0,
+ M_CAN_FIFO_DATA(i / 4),
+ *(u32 *)(cf->data + i));
+
+ can_put_echo_skb(skb, dev, 0);
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
+ cccr = m_can_read(priv, M_CAN_CCCR);
+ cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
+ if (can_is_canfd_skb(skb)) {
+ if (cf->flags & CANFD_BRS)
+ cccr |= CCCR_CMR_CANFD_BRS <<
+ CCCR_CMR_SHIFT;
+ else
+ cccr |= CCCR_CMR_CANFD <<
+ CCCR_CMR_SHIFT;
+ } else {
+ cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
+ }
+ m_can_write(priv, M_CAN_CCCR, cccr);
+ }
+ m_can_write(priv, M_CAN_TXBTIE, 0x1);
+ m_can_write(priv, M_CAN_TXBAR, 0x1);
+ /* End of xmit function for version 3.0.x */
+ } else {
+ /* Transmit routine for version >= v3.1.x */
+
+ /* Check if FIFO full */
+ if (m_can_tx_fifo_full(priv)) {
+ /* This shouldn't happen */
+ netif_stop_queue(dev);
+ netdev_warn(dev,
+ "TX queue active although FIFO is full.");
+ return NETDEV_TX_BUSY;
+ }
- can_put_echo_skb(skb, dev, 0);
+ /* get put index for frame */
+ putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
+ >> TXFQS_TFQPI_SHIFT);
+ /* Write ID Field to FIFO Element */
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
- if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
- cccr = m_can_read(priv, M_CAN_CCCR);
- cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
+ /* get CAN FD configuration of frame */
+ fdflags = 0;
if (can_is_canfd_skb(skb)) {
+ fdflags |= TX_BUF_FDF;
if (cf->flags & CANFD_BRS)
- cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
- else
- cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
- } else {
- cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
+ fdflags |= TX_BUF_BRS;
}
- m_can_write(priv, M_CAN_CCCR, cccr);
- }
- /* enable first TX buffer to start transfer */
- m_can_write(priv, M_CAN_TXBTIE, 0x1);
- m_can_write(priv, M_CAN_TXBAR, 0x1);
+ /* Construct DLC Field. Also contains CAN-FD configuration
+ * use put index of fifo as message marker
+ * it is used in TX interrupt for
+ * sending the correct echo frame
+ */
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
+ ((putidx << TX_BUF_MM_SHIFT) &
+ TX_BUF_MM_MASK) |
+ (can_len2dlc(cf->len) << 16) |
+ fdflags | TX_BUF_EFC);
+
+ for (i = 0; i < cf->len; i += 4)
+ m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
+ *(u32 *)(cf->data + i));
+
+ /* Push loopback echo.
+ * Will be looped back on TX interrupt based on message marker
+ */
+ can_put_echo_skb(skb, dev, putidx);
+
+ /* Enable TX FIFO element to start transfer */
+ m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
+
+ /* stop network queue if fifo full */
+ if (m_can_tx_fifo_full(priv) ||
+ m_can_next_echo_skb_occupied(dev, putidx))
+ netif_stop_queue(dev);
+ }
return NETDEV_TX_OK;
}
@@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
/* Probe finished
* Stop clocks. They will be reactivated once the M_CAN device is opened
*/
+
goto disable_cclk_ret;
failed_free_dev:
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
[not found] ` <1f88411b-aa58-4e17-02cb-43fc0ffb953c@Microchip.com>
@ 2017-04-13 6:30 ` Oliver Hartkopp
2017-04-13 6:50 ` Quentin Schulz
2017-04-14 6:04 ` Yang, Wenyou
[not found] ` <0f51bfad-b6ac-6cb5-0487-5b746eecb8b7@Microchip.com>
1 sibling, 2 replies; 18+ messages in thread
From: Oliver Hartkopp @ 2017-04-13 6:30 UTC (permalink / raw)
To: Yang, Wenyou, Mario Hüttel, linux-can, "socketcan,
nicolas.ferre, quentin.schulz, Alexandre Belloni, Yang, Wenyou
Hi Wenyou,
as Quentin had no problems in his setup:
Did you test this (hardware) setup in the same way with the other
patches before?
The fact that you see exactly one CAN frame on the receiver side can be
usually observed when the receiving node does not send an ACK.
The latter usually happens when the node is in listen-only mode or not
terminated properly.
Best regards,
Oliver
On 04/12/2017 10:47 AM, Yang, Wenyou wrote:
> Hi Mario,
>
> I tried to test this patch series on M_CAN IP 3.1.0 (CREL = 0x31040730)
> of SAMA5D2 Xplained board,
>
> I applied the patches on both v4.11-rc6 and v4.9.21.
>
> But it didn't work well
>
> Connected the two CAN interfaces on the same chips, CAN0 as a sender,
> the CAN1 as receiver.
>
> At the first time, the CAN1 received the data correctly from the CAN0,
> from the second time, it didn't receive data any more.
>
> Here are the configuration and log.
>
> --->8---
>
> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
> fd-non-iso on
> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
> fd-non-iso on
> # ip link set can0 up
> # ip link set can1 up
> # ip -details link show can0
> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
> mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
> restart-ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # ip -details link show can1
> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
> mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
> restart-ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # candump can1 &
> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> #
>
> ---8<---
>
> I don't know if the configuration is right.
>
> Do you have some advice? Thank you.
>
> Best Regards,
> Wenyou Yang
>
>
> On 2017/4/8 20:10, Mario Hüttel wrote:
>> From: Mario Huettel <mario.huettel@gmx.net>
>>
>> * Added defines for TX Event FIFO Element
>> * Adapted ndo_start_xmit function.
>> For versions >= v3.1.x it uses the TX FIFO to optimize the data
>> throughput. It stores the echo skb at the same index as in the
>> M_CAN's TX FIFO. The frame's message marker is set to this index.
>> This message marker is received in the TX Event FIFO after
>> the message was successfully transmitted. It is used to echo the
>> correct echo skb back to the network stack.
>> * Added m_can_echo_tx_event function. It reads all received
>> message markers in the TX Event FIFO and loops back the
>> corresponding echo skbs.
>> * ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
>>
>> Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
>> ---
>> drivers/net/can/m_can/m_can.c | 188 +++++++++++++++++++++++++++++++++++-------
>> 1 file changed, 159 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
>> index 2fa0f44..5361e07 100644
>> --- a/drivers/net/can/m_can/m_can.c
>> +++ b/drivers/net/can/m_can/m_can.c
>> @@ -334,6 +334,11 @@ enum m_can_mram_cfg {
>> #define TX_BUF_MM_SHIFT 24
>> #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
>>
>> +/* Tx event FIFO Element */
>> +/* E1 */
>> +#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
>> +#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
>> +
>> /* address offset and element number for each FIFO/Buffer in the Message RAM */
>> struct mram_cfg {
>> u16 off;
>> @@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi, int quota)
>> return work_done;
>> }
>>
>> +static void m_can_echo_tx_event(struct net_device *dev)
>> +{
>> + u32 txe_count = 0;
>> + u32 m_can_txefs;
>> + u32 fgi = 0;
>> + int i = 0;
>> + unsigned int msg_mark;
>> +
>> + struct m_can_priv *priv = netdev_priv(dev);
>> + struct net_device_stats *stats = &dev->stats;
>> +
>> + /* read tx event fifo status */
>> + m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
>> +
>> + /* Get Tx Event fifo element count */
>> + txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
>> + >> TXEFS_EFFL_SHIFT;
>> +
>> + /* Get and process all sent elements */
>> + for (i = 0; i < txe_count; i++) {
>> + /* retrieve get index */
>> + fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
>> + >> TXEFS_EFGI_SHIFT;
>> +
>> + /* get message marker */
>> + msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
>> + TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
>> +
>> + /* ack txe element */
>> + m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
>> + (fgi << TXEFA_EFAI_SHIFT)));
>> +
>> + /* update stats */
>> + stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
>> + stats->tx_packets++;
>> + }
>> +}
>> +
>> static irqreturn_t m_can_isr(int irq, void *dev_id)
>> {
>> struct net_device *dev = (struct net_device *)dev_id;
>> @@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
>> napi_schedule(&priv->napi);
>> }
>>
>> - /* transmission complete interrupt */
>> - if (ir & IR_TC) {
>> - stats->tx_bytes += can_get_echo_skb(dev, 0);
>> - stats->tx_packets++;
>> - can_led_event(dev, CAN_LED_EVENT_TX);
>> - netif_wake_queue(dev);
>> + if (priv->version == 30) {
>> + if (ir & IR_TC) {
>> + /* Transmission Complete Interrupt*/
>> + stats->tx_bytes += can_get_echo_skb(dev, 0);
>> + stats->tx_packets++;
>> + can_led_event(dev, CAN_LED_EVENT_TX);
>> + netif_wake_queue(dev);
>> + }
>> + } else {
>> + if (ir & IR_TEFN) {
>> + /* New TX FIFO Element arrived */
>> + m_can_echo_tx_event(dev);
>> + can_led_event(dev, CAN_LED_EVENT_TX);
>> + if (netif_queue_stopped(dev) &&
>> + !m_can_tx_fifo_full(priv))
>> + netif_wake_queue(dev);
>> + }
>> }
>>
>> return IRQ_HANDLED;
>> @@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
>> return 0;
>> }
>>
>> +static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
>> +{
>> + struct m_can_priv *priv = netdev_priv(dev);
>> + /*get wrap around for loopback skb index */
>> + unsigned int wrap = priv->can.echo_skb_max;
>> + int next_idx;
>> +
>> + /* calculate next index */
>> + next_idx = (++putidx >= wrap ? 0 : putidx);
>> +
>> + /* check if occupied */
>> + return !!priv->can.echo_skb[next_idx];
>> +}
>> +
>> static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>> struct net_device *dev)
>> {
>> struct m_can_priv *priv = netdev_priv(dev);
>> struct canfd_frame *cf = (struct canfd_frame *)skb->data;
>> - u32 id, cccr;
>> + u32 id, cccr, fdflags;
>> int i;
>> + int putidx;
>>
>> if (can_dropped_invalid_skb(dev, skb))
>> return NETDEV_TX_OK;
>>
>> - netif_stop_queue(dev);
>> -
>> + /* Generate ID field for TX buffer Element */
>> + /* Common to all supported M_CAN versions */
>> if (cf->can_id & CAN_EFF_FLAG) {
>> id = cf->can_id & CAN_EFF_MASK;
>> id |= TX_BUF_XTD;
>> @@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>> if (cf->can_id & CAN_RTR_FLAG)
>> id |= TX_BUF_RTR;
>>
>> - /* message ram configuration */
>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
>> + if (priv->version == 30) {
>> + netif_stop_queue(dev);
>> +
>> + /* message ram configuration */
>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
>> + can_len2dlc(cf->len) << 16);
>>
>> - for (i = 0; i < cf->len; i += 4)
>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
>> - *(u32 *)(cf->data + i));
>> + for (i = 0; i < cf->len; i += 4)
>> + m_can_fifo_write(priv, 0,
>> + M_CAN_FIFO_DATA(i / 4),
>> + *(u32 *)(cf->data + i));
>> +
>> + can_put_echo_skb(skb, dev, 0);
>> +
>> + if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>> + cccr = m_can_read(priv, M_CAN_CCCR);
>> + cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>> + if (can_is_canfd_skb(skb)) {
>> + if (cf->flags & CANFD_BRS)
>> + cccr |= CCCR_CMR_CANFD_BRS <<
>> + CCCR_CMR_SHIFT;
>> + else
>> + cccr |= CCCR_CMR_CANFD <<
>> + CCCR_CMR_SHIFT;
>> + } else {
>> + cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>> + }
>> + m_can_write(priv, M_CAN_CCCR, cccr);
>> + }
>> + m_can_write(priv, M_CAN_TXBTIE, 0x1);
>> + m_can_write(priv, M_CAN_TXBAR, 0x1);
>> + /* End of xmit function for version 3.0.x */
>> + } else {
>> + /* Transmit routine for version >= v3.1.x */
>> +
>> + /* Check if FIFO full */
>> + if (m_can_tx_fifo_full(priv)) {
>> + /* This shouldn't happen */
>> + netif_stop_queue(dev);
>> + netdev_warn(dev,
>> + "TX queue active although FIFO is full.");
>> + return NETDEV_TX_BUSY;
>> + }
>>
>> - can_put_echo_skb(skb, dev, 0);
>> + /* get put index for frame */
>> + putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
>> + >> TXFQS_TFQPI_SHIFT);
>> + /* Write ID Field to FIFO Element */
>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
>>
>> - if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>> - cccr = m_can_read(priv, M_CAN_CCCR);
>> - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>> + /* get CAN FD configuration of frame */
>> + fdflags = 0;
>> if (can_is_canfd_skb(skb)) {
>> + fdflags |= TX_BUF_FDF;
>> if (cf->flags & CANFD_BRS)
>> - cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
>> - else
>> - cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
>> - } else {
>> - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>> + fdflags |= TX_BUF_BRS;
>> }
>> - m_can_write(priv, M_CAN_CCCR, cccr);
>> - }
>>
>> - /* enable first TX buffer to start transfer */
>> - m_can_write(priv, M_CAN_TXBTIE, 0x1);
>> - m_can_write(priv, M_CAN_TXBAR, 0x1);
>> + /* Construct DLC Field. Also contains CAN-FD configuration
>> + * use put index of fifo as message marker
>> + * it is used in TX interrupt for
>> + * sending the correct echo frame
>> + */
>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
>> + ((putidx << TX_BUF_MM_SHIFT) &
>> + TX_BUF_MM_MASK) |
>> + (can_len2dlc(cf->len) << 16) |
>> + fdflags | TX_BUF_EFC);
>> +
>> + for (i = 0; i < cf->len; i += 4)
>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
>> + *(u32 *)(cf->data + i));
>> +
>> + /* Push loopback echo.
>> + * Will be looped back on TX interrupt based on message marker
>> + */
>> + can_put_echo_skb(skb, dev, putidx);
>> +
>> + /* Enable TX FIFO element to start transfer */
>> + m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
>> +
>> + /* stop network queue if fifo full */
>> + if (m_can_tx_fifo_full(priv) ||
>> + m_can_next_echo_skb_occupied(dev, putidx))
>> + netif_stop_queue(dev);
>> + }
>>
>> return NETDEV_TX_OK;
>> }
>> @@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
>> /* Probe finished
>> * Stop clocks. They will be reactivated once the M_CAN device is opened
>> */
>> +
>> goto disable_cclk_ret;
>>
>> failed_free_dev:
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-13 6:30 ` Oliver Hartkopp
@ 2017-04-13 6:50 ` Quentin Schulz
2017-04-18 6:04 ` AW: " Huettel Mario (AE/PJ-SCI1)
2017-04-14 6:04 ` Yang, Wenyou
1 sibling, 1 reply; 18+ messages in thread
From: Quentin Schulz @ 2017-04-13 6:50 UTC (permalink / raw)
To: Oliver Hartkopp, Yang, Wenyou, Mario Hüttel, linux-can,
"socketcan, nicolas.ferre, Alexandre Belloni, Yang, Wenyou
Hi Oliver,
On 13/04/2017 08:30, Oliver Hartkopp wrote:
> Hi Wenyou,
>
> as Quentin had no problems in his setup:
>
Actually just retested by doing the same as Wenyou on my SAMA5D2
Xplained and I can attest I'm having the same behavior as Wenyou.
Best regards,
Quentin
> Did you test this (hardware) setup in the same way with the other
> patches before?
>
> The fact that you see exactly one CAN frame on the receiver side can be
> usually observed when the receiving node does not send an ACK.
>
> The latter usually happens when the node is in listen-only mode or not
> terminated properly.
>
> Best regards,
> Oliver
>
> On 04/12/2017 10:47 AM, Yang, Wenyou wrote:
>> Hi Mario,
>>
>> I tried to test this patch series on M_CAN IP 3.1.0 (CREL = 0x31040730)
>> of SAMA5D2 Xplained board,
>>
>> I applied the patches on both v4.11-rc6 and v4.9.21.
>>
>> But it didn't work well
>>
>> Connected the two CAN interfaces on the same chips, CAN0 as a sender,
>> the CAN1 as receiver.
>>
>> At the first time, the CAN1 received the data correctly from the CAN0,
>> from the second time, it didn't receive data any more.
>>
>> Here are the configuration and log.
>>
>> --->8---
>>
>> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can0 up
>> # ip link set can1 up
>> # ip -details link show can0
>> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
>> mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512
>> brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # ip -details link show can1
>> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
>> mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512
>> brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # candump can1 &
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> #
>>
>> ---8<---
>>
>> I don't know if the configuration is right.
>>
>> Do you have some advice? Thank you.
>>
>> Best Regards,
>> Wenyou Yang
>>
>>
>> On 2017/4/8 20:10, Mario Hüttel wrote:
>>> From: Mario Huettel <mario.huettel@gmx.net>
>>>
>>> * Added defines for TX Event FIFO Element
>>> * Adapted ndo_start_xmit function.
>>> For versions >= v3.1.x it uses the TX FIFO to optimize the data
>>> throughput. It stores the echo skb at the same index as in the
>>> M_CAN's TX FIFO. The frame's message marker is set to this index.
>>> This message marker is received in the TX Event FIFO after
>>> the message was successfully transmitted. It is used to echo the
>>> correct echo skb back to the network stack.
>>> * Added m_can_echo_tx_event function. It reads all received
>>> message markers in the TX Event FIFO and loops back the
>>> corresponding echo skbs.
>>> * ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
>>>
>>> Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
>>> ---
>>> drivers/net/can/m_can/m_can.c | 188
>>> +++++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 159 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/net/can/m_can/m_can.c
>>> b/drivers/net/can/m_can/m_can.c
>>> index 2fa0f44..5361e07 100644
>>> --- a/drivers/net/can/m_can/m_can.c
>>> +++ b/drivers/net/can/m_can/m_can.c
>>> @@ -334,6 +334,11 @@ enum m_can_mram_cfg {
>>> #define TX_BUF_MM_SHIFT 24
>>> #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
>>>
>>> +/* Tx event FIFO Element */
>>> +/* E1 */
>>> +#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
>>> +#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
>>> +
>>> /* address offset and element number for each FIFO/Buffer in the
>>> Message RAM */
>>> struct mram_cfg {
>>> u16 off;
>>> @@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi,
>>> int quota)
>>> return work_done;
>>> }
>>>
>>> +static void m_can_echo_tx_event(struct net_device *dev)
>>> +{
>>> + u32 txe_count = 0;
>>> + u32 m_can_txefs;
>>> + u32 fgi = 0;
>>> + int i = 0;
>>> + unsigned int msg_mark;
>>> +
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + struct net_device_stats *stats = &dev->stats;
>>> +
>>> + /* read tx event fifo status */
>>> + m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
>>> +
>>> + /* Get Tx Event fifo element count */
>>> + txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
>>> + >> TXEFS_EFFL_SHIFT;
>>> +
>>> + /* Get and process all sent elements */
>>> + for (i = 0; i < txe_count; i++) {
>>> + /* retrieve get index */
>>> + fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
>>> + >> TXEFS_EFGI_SHIFT;
>>> +
>>> + /* get message marker */
>>> + msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
>>> + TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
>>> +
>>> + /* ack txe element */
>>> + m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
>>> + (fgi << TXEFA_EFAI_SHIFT)));
>>> +
>>> + /* update stats */
>>> + stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
>>> + stats->tx_packets++;
>>> + }
>>> +}
>>> +
>>> static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> {
>>> struct net_device *dev = (struct net_device *)dev_id;
>>> @@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void
>>> *dev_id)
>>> napi_schedule(&priv->napi);
>>> }
>>>
>>> - /* transmission complete interrupt */
>>> - if (ir & IR_TC) {
>>> - stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> - stats->tx_packets++;
>>> - can_led_event(dev, CAN_LED_EVENT_TX);
>>> - netif_wake_queue(dev);
>>> + if (priv->version == 30) {
>>> + if (ir & IR_TC) {
>>> + /* Transmission Complete Interrupt*/
>>> + stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> + stats->tx_packets++;
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + netif_wake_queue(dev);
>>> + }
>>> + } else {
>>> + if (ir & IR_TEFN) {
>>> + /* New TX FIFO Element arrived */
>>> + m_can_echo_tx_event(dev);
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + if (netif_queue_stopped(dev) &&
>>> + !m_can_tx_fifo_full(priv))
>>> + netif_wake_queue(dev);
>>> + }
>>> }
>>>
>>> return IRQ_HANDLED;
>>> @@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
>>> return 0;
>>> }
>>>
>>> +static int m_can_next_echo_skb_occupied(struct net_device *dev, int
>>> putidx)
>>> +{
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + /*get wrap around for loopback skb index */
>>> + unsigned int wrap = priv->can.echo_skb_max;
>>> + int next_idx;
>>> +
>>> + /* calculate next index */
>>> + next_idx = (++putidx >= wrap ? 0 : putidx);
>>> +
>>> + /* check if occupied */
>>> + return !!priv->can.echo_skb[next_idx];
>>> +}
>>> +
>>> static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> struct net_device *dev)
>>> {
>>> struct m_can_priv *priv = netdev_priv(dev);
>>> struct canfd_frame *cf = (struct canfd_frame *)skb->data;
>>> - u32 id, cccr;
>>> + u32 id, cccr, fdflags;
>>> int i;
>>> + int putidx;
>>>
>>> if (can_dropped_invalid_skb(dev, skb))
>>> return NETDEV_TX_OK;
>>>
>>> - netif_stop_queue(dev);
>>> -
>>> + /* Generate ID field for TX buffer Element */
>>> + /* Common to all supported M_CAN versions */
>>> if (cf->can_id & CAN_EFF_FLAG) {
>>> id = cf->can_id & CAN_EFF_MASK;
>>> id |= TX_BUF_XTD;
>>> @@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct
>>> sk_buff *skb,
>>> if (cf->can_id & CAN_RTR_FLAG)
>>> id |= TX_BUF_RTR;
>>>
>>> - /* message ram configuration */
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len)
>>> << 16);
>>> + if (priv->version == 30) {
>>> + netif_stop_queue(dev);
>>> +
>>> + /* message ram configuration */
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
>>> + can_len2dlc(cf->len) << 16);
>>>
>>> - for (i = 0; i < cf->len; i += 4)
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
>>> - *(u32 *)(cf->data + i));
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, 0,
>>> + M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + can_put_echo_skb(skb, dev, 0);
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> + cccr = m_can_read(priv, M_CAN_CCCR);
>>> + cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + if (can_is_canfd_skb(skb)) {
>>> + if (cf->flags & CANFD_BRS)
>>> + cccr |= CCCR_CMR_CANFD_BRS <<
>>> + CCCR_CMR_SHIFT;
>>> + else
>>> + cccr |= CCCR_CMR_CANFD <<
>>> + CCCR_CMR_SHIFT;
>>> + } else {
>>> + cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + }
>>> + m_can_write(priv, M_CAN_CCCR, cccr);
>>> + }
>>> + m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> + m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* End of xmit function for version 3.0.x */
>>> + } else {
>>> + /* Transmit routine for version >= v3.1.x */
>>> +
>>> + /* Check if FIFO full */
>>> + if (m_can_tx_fifo_full(priv)) {
>>> + /* This shouldn't happen */
>>> + netif_stop_queue(dev);
>>> + netdev_warn(dev,
>>> + "TX queue active although FIFO is full.");
>>> + return NETDEV_TX_BUSY;
>>> + }
>>>
>>> - can_put_echo_skb(skb, dev, 0);
>>> + /* get put index for frame */
>>> + putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
>>> + >> TXFQS_TFQPI_SHIFT);
>>> + /* Write ID Field to FIFO Element */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
>>>
>>> - if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> - cccr = m_can_read(priv, M_CAN_CCCR);
>>> - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + /* get CAN FD configuration of frame */
>>> + fdflags = 0;
>>> if (can_is_canfd_skb(skb)) {
>>> + fdflags |= TX_BUF_FDF;
>>> if (cf->flags & CANFD_BRS)
>>> - cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
>>> - else
>>> - cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
>>> - } else {
>>> - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + fdflags |= TX_BUF_BRS;
>>> }
>>> - m_can_write(priv, M_CAN_CCCR, cccr);
>>> - }
>>>
>>> - /* enable first TX buffer to start transfer */
>>> - m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> - m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* Construct DLC Field. Also contains CAN-FD configuration
>>> + * use put index of fifo as message marker
>>> + * it is used in TX interrupt for
>>> + * sending the correct echo frame
>>> + */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
>>> + ((putidx << TX_BUF_MM_SHIFT) &
>>> + TX_BUF_MM_MASK) |
>>> + (can_len2dlc(cf->len) << 16) |
>>> + fdflags | TX_BUF_EFC);
>>> +
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + /* Push loopback echo.
>>> + * Will be looped back on TX interrupt based on message marker
>>> + */
>>> + can_put_echo_skb(skb, dev, putidx);
>>> +
>>> + /* Enable TX FIFO element to start transfer */
>>> + m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
>>> +
>>> + /* stop network queue if fifo full */
>>> + if (m_can_tx_fifo_full(priv) ||
>>> + m_can_next_echo_skb_occupied(dev, putidx))
>>> + netif_stop_queue(dev);
>>> + }
>>>
>>> return NETDEV_TX_OK;
>>> }
>>> @@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct
>>> platform_device *pdev)
>>> /* Probe finished
>>> * Stop clocks. They will be reactivated once the M_CAN device
>>> is opened
>>> */
>>> +
>>> goto disable_cclk_ret;
>>>
>>> failed_free_dev:
>>
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-13 6:30 ` Oliver Hartkopp
2017-04-13 6:50 ` Quentin Schulz
@ 2017-04-14 6:04 ` Yang, Wenyou
1 sibling, 0 replies; 18+ messages in thread
From: Yang, Wenyou @ 2017-04-14 6:04 UTC (permalink / raw)
To: Oliver Hartkopp, Mario Hüttel, linux-can, "socketcan,
nicolas.ferre, quentin.schulz, Alexandre Belloni, Yang, Wenyou
Hi Oliver,
On 2017/4/13 14:30, Oliver Hartkopp wrote:
> Hi Wenyou,
>
> as Quentin had no problems in his setup:
>
> Did you test this (hardware) setup in the same way with the other
> patches before?
Yes, it is in same way. It is okay with the other patches before.
> The fact that you see exactly one CAN frame on the receiver side can
> be usually observed when the receiving node does not send an ACK.
>
> The latter usually happens when the node is in listen-only mode or not
> terminated properly.
>
> Best regards,
> Oliver
>
> On 04/12/2017 10:47 AM, Yang, Wenyou wrote:
>> Hi Mario,
>>
>> I tried to test this patch series on M_CAN IP 3.1.0 (CREL = 0x31040730)
>> of SAMA5D2 Xplained board,
>>
>> I applied the patches on both v4.11-rc6 and v4.9.21.
>>
>> But it didn't work well
>>
>> Connected the two CAN interfaces on the same chips, CAN0 as a sender,
>> the CAN1 as receiver.
>>
>> At the first time, the CAN1 received the data correctly from the CAN0,
>> from the second time, it didn't receive data any more.
>>
>> Here are the configuration and log.
>>
>> --->8---
>>
>> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can0 up
>> # ip link set can1 up
>> # ip -details link show can0
>> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
>> mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512
>> brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # ip -details link show can1
>> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
>> mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512
>> brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # candump can1 &
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> #
>>
>> ---8<---
>>
>> I don't know if the configuration is right.
>>
>> Do you have some advice? Thank you.
>>
>> Best Regards,
>> Wenyou Yang
>>
>>
>> On 2017/4/8 20:10, Mario Hüttel wrote:
>>> From: Mario Huettel <mario.huettel@gmx.net>
>>>
>>> * Added defines for TX Event FIFO Element
>>> * Adapted ndo_start_xmit function.
>>> For versions >= v3.1.x it uses the TX FIFO to optimize the data
>>> throughput. It stores the echo skb at the same index as in the
>>> M_CAN's TX FIFO. The frame's message marker is set to this index.
>>> This message marker is received in the TX Event FIFO after
>>> the message was successfully transmitted. It is used to echo the
>>> correct echo skb back to the network stack.
>>> * Added m_can_echo_tx_event function. It reads all received
>>> message markers in the TX Event FIFO and loops back the
>>> corresponding echo skbs.
>>> * ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
>>>
>>> Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
>>> ---
>>> drivers/net/can/m_can/m_can.c | 188
>>> +++++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 159 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/net/can/m_can/m_can.c
>>> b/drivers/net/can/m_can/m_can.c
>>> index 2fa0f44..5361e07 100644
>>> --- a/drivers/net/can/m_can/m_can.c
>>> +++ b/drivers/net/can/m_can/m_can.c
>>> @@ -334,6 +334,11 @@ enum m_can_mram_cfg {
>>> #define TX_BUF_MM_SHIFT 24
>>> #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
>>>
>>> +/* Tx event FIFO Element */
>>> +/* E1 */
>>> +#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
>>> +#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
>>> +
>>> /* address offset and element number for each FIFO/Buffer in the
>>> Message RAM */
>>> struct mram_cfg {
>>> u16 off;
>>> @@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi,
>>> int quota)
>>> return work_done;
>>> }
>>>
>>> +static void m_can_echo_tx_event(struct net_device *dev)
>>> +{
>>> + u32 txe_count = 0;
>>> + u32 m_can_txefs;
>>> + u32 fgi = 0;
>>> + int i = 0;
>>> + unsigned int msg_mark;
>>> +
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + struct net_device_stats *stats = &dev->stats;
>>> +
>>> + /* read tx event fifo status */
>>> + m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
>>> +
>>> + /* Get Tx Event fifo element count */
>>> + txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
>>> + >> TXEFS_EFFL_SHIFT;
>>> +
>>> + /* Get and process all sent elements */
>>> + for (i = 0; i < txe_count; i++) {
>>> + /* retrieve get index */
>>> + fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
>>> + >> TXEFS_EFGI_SHIFT;
>>> +
>>> + /* get message marker */
>>> + msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
>>> + TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
>>> +
>>> + /* ack txe element */
>>> + m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
>>> + (fgi << TXEFA_EFAI_SHIFT)));
>>> +
>>> + /* update stats */
>>> + stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
>>> + stats->tx_packets++;
>>> + }
>>> +}
>>> +
>>> static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> {
>>> struct net_device *dev = (struct net_device *)dev_id;
>>> @@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void
>>> *dev_id)
>>> napi_schedule(&priv->napi);
>>> }
>>>
>>> - /* transmission complete interrupt */
>>> - if (ir & IR_TC) {
>>> - stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> - stats->tx_packets++;
>>> - can_led_event(dev, CAN_LED_EVENT_TX);
>>> - netif_wake_queue(dev);
>>> + if (priv->version == 30) {
>>> + if (ir & IR_TC) {
>>> + /* Transmission Complete Interrupt*/
>>> + stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> + stats->tx_packets++;
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + netif_wake_queue(dev);
>>> + }
>>> + } else {
>>> + if (ir & IR_TEFN) {
>>> + /* New TX FIFO Element arrived */
>>> + m_can_echo_tx_event(dev);
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + if (netif_queue_stopped(dev) &&
>>> + !m_can_tx_fifo_full(priv))
>>> + netif_wake_queue(dev);
>>> + }
>>> }
>>>
>>> return IRQ_HANDLED;
>>> @@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
>>> return 0;
>>> }
>>>
>>> +static int m_can_next_echo_skb_occupied(struct net_device *dev, int
>>> putidx)
>>> +{
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + /*get wrap around for loopback skb index */
>>> + unsigned int wrap = priv->can.echo_skb_max;
>>> + int next_idx;
>>> +
>>> + /* calculate next index */
>>> + next_idx = (++putidx >= wrap ? 0 : putidx);
>>> +
>>> + /* check if occupied */
>>> + return !!priv->can.echo_skb[next_idx];
>>> +}
>>> +
>>> static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> struct net_device *dev)
>>> {
>>> struct m_can_priv *priv = netdev_priv(dev);
>>> struct canfd_frame *cf = (struct canfd_frame *)skb->data;
>>> - u32 id, cccr;
>>> + u32 id, cccr, fdflags;
>>> int i;
>>> + int putidx;
>>>
>>> if (can_dropped_invalid_skb(dev, skb))
>>> return NETDEV_TX_OK;
>>>
>>> - netif_stop_queue(dev);
>>> -
>>> + /* Generate ID field for TX buffer Element */
>>> + /* Common to all supported M_CAN versions */
>>> if (cf->can_id & CAN_EFF_FLAG) {
>>> id = cf->can_id & CAN_EFF_MASK;
>>> id |= TX_BUF_XTD;
>>> @@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct
>>> sk_buff *skb,
>>> if (cf->can_id & CAN_RTR_FLAG)
>>> id |= TX_BUF_RTR;
>>>
>>> - /* message ram configuration */
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len)
>>> << 16);
>>> + if (priv->version == 30) {
>>> + netif_stop_queue(dev);
>>> +
>>> + /* message ram configuration */
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
>>> + can_len2dlc(cf->len) << 16);
>>>
>>> - for (i = 0; i < cf->len; i += 4)
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
>>> - *(u32 *)(cf->data + i));
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, 0,
>>> + M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + can_put_echo_skb(skb, dev, 0);
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> + cccr = m_can_read(priv, M_CAN_CCCR);
>>> + cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + if (can_is_canfd_skb(skb)) {
>>> + if (cf->flags & CANFD_BRS)
>>> + cccr |= CCCR_CMR_CANFD_BRS <<
>>> + CCCR_CMR_SHIFT;
>>> + else
>>> + cccr |= CCCR_CMR_CANFD <<
>>> + CCCR_CMR_SHIFT;
>>> + } else {
>>> + cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + }
>>> + m_can_write(priv, M_CAN_CCCR, cccr);
>>> + }
>>> + m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> + m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* End of xmit function for version 3.0.x */
>>> + } else {
>>> + /* Transmit routine for version >= v3.1.x */
>>> +
>>> + /* Check if FIFO full */
>>> + if (m_can_tx_fifo_full(priv)) {
>>> + /* This shouldn't happen */
>>> + netif_stop_queue(dev);
>>> + netdev_warn(dev,
>>> + "TX queue active although FIFO is full.");
>>> + return NETDEV_TX_BUSY;
>>> + }
>>>
>>> - can_put_echo_skb(skb, dev, 0);
>>> + /* get put index for frame */
>>> + putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
>>> + >> TXFQS_TFQPI_SHIFT);
>>> + /* Write ID Field to FIFO Element */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
>>>
>>> - if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> - cccr = m_can_read(priv, M_CAN_CCCR);
>>> - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + /* get CAN FD configuration of frame */
>>> + fdflags = 0;
>>> if (can_is_canfd_skb(skb)) {
>>> + fdflags |= TX_BUF_FDF;
>>> if (cf->flags & CANFD_BRS)
>>> - cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
>>> - else
>>> - cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
>>> - } else {
>>> - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + fdflags |= TX_BUF_BRS;
>>> }
>>> - m_can_write(priv, M_CAN_CCCR, cccr);
>>> - }
>>>
>>> - /* enable first TX buffer to start transfer */
>>> - m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> - m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* Construct DLC Field. Also contains CAN-FD configuration
>>> + * use put index of fifo as message marker
>>> + * it is used in TX interrupt for
>>> + * sending the correct echo frame
>>> + */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
>>> + ((putidx << TX_BUF_MM_SHIFT) &
>>> + TX_BUF_MM_MASK) |
>>> + (can_len2dlc(cf->len) << 16) |
>>> + fdflags | TX_BUF_EFC);
>>> +
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + /* Push loopback echo.
>>> + * Will be looped back on TX interrupt based on message marker
>>> + */
>>> + can_put_echo_skb(skb, dev, putidx);
>>> +
>>> + /* Enable TX FIFO element to start transfer */
>>> + m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
>>> +
>>> + /* stop network queue if fifo full */
>>> + if (m_can_tx_fifo_full(priv) ||
>>> + m_can_next_echo_skb_occupied(dev, putidx))
>>> + netif_stop_queue(dev);
>>> + }
>>>
>>> return NETDEV_TX_OK;
>>> }
>>> @@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct
>>> platform_device *pdev)
>>> /* Probe finished
>>> * Stop clocks. They will be reactivated once the M_CAN device
>>> is opened
>>> */
>>> +
>>> goto disable_cclk_ret;
>>>
>>> failed_free_dev:
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-can" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Best Regards,
Wenyou Yang
^ permalink raw reply [flat|nested] 18+ messages in thread
* AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-13 6:50 ` Quentin Schulz
@ 2017-04-18 6:04 ` Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:17 ` Yang, Wenyou
0 siblings, 1 reply; 18+ messages in thread
From: Huettel Mario (AE/PJ-SCI1) @ 2017-04-18 6:04 UTC (permalink / raw)
To: Quentin Schulz, wenyou.yang; +Cc: linux-can
Hi Quentin, hi Wenyou,
Today I've received another email that the driver is not working with the
M_CAN in Atmel's SAMA5D2.
Can you send me the device tree you're using and post the dmesg output
of the m_can driver?
There might be a clue why it isn't working.
The fact that it is working one time and then stops working looks like some problem
In the TX FIFO to me. Can you please check with some third device/oscilloscope,
if the controller is sending data. I want to know ehre the problem lies. If it's in the TX or
RX path.
As for now I can only throw some ideas into the round:
* What are the PCLK and CCLK values? CCLK >= PCLK?
* TX FIFO configured to one element and something happens in that case.
* No TX Event FIFO element configured. The driver also doesn't work in this case.
Quentin wrote:
> Hi Oliver,
>
> On 13/04/2017 08:30, Oliver Hartkopp wrote:
>> Hi Wenyou,
>>
>> as Quentin had no problems in his setup:
>>
>
> Actually just retested by doing the same as Wenyou on my SAMA5D2
> Xplained and I can attest I'm having the same behavior as Wenyou.
>
> Best regards,
> Quentin
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-18 6:04 ` AW: " Huettel Mario (AE/PJ-SCI1)
@ 2017-04-18 6:17 ` Yang, Wenyou
2017-04-18 6:37 ` AW: " Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
0 siblings, 2 replies; 18+ messages in thread
From: Yang, Wenyou @ 2017-04-18 6:17 UTC (permalink / raw)
To: Huettel Mario (AE/PJ-SCI1), Quentin Schulz; +Cc: linux-can
[-- Attachment #1: Type: text/plain, Size: 3344 bytes --]
Hi Mario,
The device tree patch is attached.
Here is the configure and log.
---8<----
# ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can0 up
# ip link set can1 up
# ip -details link show can0
2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# ip -details link show can1
3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# candump can1 &
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
#
--->8----
Hope it is helpful for you.
Any question, please don't hesitate to come back.
Best Regards,
Wenyou Yang
On 2017/4/18 14:04, Huettel Mario (AE/PJ-SCI1) wrote:
> Hi Quentin, hi Wenyou,
>
> Today I've received another email that the driver is not working with the
> M_CAN in Atmel's SAMA5D2.
>
> Can you send me the device tree you're using and post the dmesg output
> of the m_can driver?
>
> There might be a clue why it isn't working.
> The fact that it is working one time and then stops working looks like some problem
> In the TX FIFO to me. Can you please check with some third device/oscilloscope,
> if the controller is sending data. I want to know ehre the problem lies. If it's in the TX or
> RX path.
>
> As for now I can only throw some ideas into the round:
> * What are the PCLK and CCLK values? CCLK >= PCLK?
> * TX FIFO configured to one element and something happens in that case.
> * No TX Event FIFO element configured. The driver also doesn't work in this case.
>
>
> Quentin wrote:
>> Hi Oliver,
>>
>> On 13/04/2017 08:30, Oliver Hartkopp wrote:
>>> Hi Wenyou,
>>>
>>> as Quentin had no problems in his setup:
>>>
>> Actually just retested by doing the same as Wenyou on my SAMA5D2
>> Xplained and I can attest I'm having the same behavior as Wenyou.
>>
>> Best regards,
>> Quentin
>
> \x13��칻\x1c�&�~�&�\x18��+-��ݶ\x17��w��˛���m�b��\jx��\x17��ܨ}���Ơz�&j:+v���\a����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
[-- Attachment #2: 0001-ARM-dts-at91-sama5d2-add-m_can-nodes.patch --]
[-- Type: text/plain, Size: 4717 bytes --]
From 930f560c9e53d87c7c5a007498120d1b1efc7f0a Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Tue, 10 Nov 2015 14:49:04 +0800
Subject: [PATCH 1/2] ARM: dts: at91: sama5d2: add m_can nodes
Add nodes to support the Controller Area Network(M_CAN) on SAMA5D2.
As said in SAMA5D2 datasheet, the CAN clock is recommended to use
frequencies of 20, 40 or 80 MHz. To achieve these frequencies,
PMC GCLK3 must select the UPLLCK(480 MHz) as source clock and
divide by 24, 12, or 6. So, the "assigned-clock-rates" property
has three options: 20000000, 40000000, and 80000000.
The "assigned-clock-parents" property should be referred to utmi
fixedly.
The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are
default configured in 0x00200000. To avoid conflict with SRAM map
for pm, change them to 0x00210000 in the AT91Bootstrap via setting
the CAN Memories Address-based Register(SFR_CAN) of SFR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Series-to: nicolas, alex, dt-guys, king
Series-cc: dt-list, arm-list, linux-kernel, wyang
---
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 24 +++++++++++++
arch/arm/boot/dts/sama5d2.dtsi | 56 +++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 9f7f8a7d8ff9..2f19b08dc226 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -257,6 +257,12 @@
status = "okay";
};
+ can0: can@f8054000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+ status = "okay";
+ };
+
uart3: serial@fc008000 {
atmel,use-dma-rx;
atmel,use-dma-tx;
@@ -321,6 +327,18 @@
bias-disable;
};
+ pinctrl_can0_default: can0_default {
+ pinmux = <PIN_PC10__CANTX0>,
+ <PIN_PC11__CANRX0>;
+ bias-disable;
+ };
+
+ pinctrl_can1_default: can1_default {
+ pinmux = <PIN_PC26__CANTX1>,
+ <PIN_PC27__CANRX1>;
+ bias-disable;
+ };
+
pinctrl_charger_chglev: charger_chglev {
pinmux = <PIN_PA12__GPIO>;
bias-disable;
@@ -468,6 +486,12 @@
};
};
+
+ can1: can@fc050000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 528b4e9c6d3d..1200d52ff0a5 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -762,6 +762,18 @@
atmel,clk-output-range = <0 83000000>;
};
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ reg = <56>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ reg = <57>;
+ atmel,clk-output-range = <0 83000000>;
+ };
+
classd_clk: classd_clk {
#clock-cells = <0>;
reg = <59>;
@@ -890,6 +902,18 @@
#clock-cells = <0>;
reg = <55>;
};
+
+ can0_gclk: can0_gclk {
+ #clock-cells = <0>;
+ reg = <56>;
+ atmel,clk-output-range = <0 80000000>;
+ };
+
+ can1_gclk: can1_gclk {
+ #clock-cells = <0>;
+ reg = <57>;
+ atmel,clk-output-range = <0 80000000>;
+ };
};
};
@@ -1144,6 +1168,22 @@
clocks = <&clk32k>;
};
+ can0: can@f8054000 {
+ compatible = "bosch,m_can";
+ reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
+ <64 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-names = "int0", "int1";
+ clocks = <&can0_clk>, <&can0_gclk>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&can0_gclk>;
+ assigned-clock-parents = <&utmi>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
+ status = "disabled";
+ };
+
spi1: spi@fc000000 {
compatible = "atmel,at91rm9200-spi";
reg = <0xfc000000 0x100>;
@@ -1305,6 +1345,22 @@
status = "okay";
};
+ can1: can@fc050000 {
+ compatible = "bosch,m_can";
+ reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
+ <65 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-names = "int0", "int1";
+ clocks = <&can1_clk>, <&can1_gclk>;
+ clock-names = "hclk", "cclk";
+ assigned-clocks = <&can1_gclk>;
+ assigned-clock-parents = <&utmi>;
+ assigned-clock-rates = <40000000>;
+ bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
+ status = "disabled";
+ };
+
chipid@fc069000 {
compatible = "atmel,sama5d2-chipid";
reg = <0xfc069000 0x8>;
--
2.11.0
[-- Attachment #3: 0002-ARM-at91-defconfig-add-MCAN-driver-to-sama5_defconfi.patch --]
[-- Type: text/plain, Size: 946 bytes --]
From e6b189e618fc90a23e7f13b2daf393ca97ac7865 Mon Sep 17 00:00:00 2001
From: Wenyou Yang <wenyou.yang@atmel.com>
Date: Fri, 17 Feb 2017 16:36:57 +0800
Subject: [PATCH 2/2] ARM: at91/defconfig: add MCAN driver to sama5_defconfig
Add the Controller Area Network (MCAN) driver compilation
for sama5 default configuration. Is used by sama5d2 SoC for instance.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Series-to: alex, nicolas, king, marek
Series-cc: arm-list, linux-kernel
---
arch/arm/configs/sama5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 777c9e986425..01f7dedd570d 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -52,6 +52,7 @@ CONFIG_IP_PNP_RARP=y
CONFIG_IPV6_SIT_6RD=y
CONFIG_CAN=y
CONFIG_CAN_AT91=y
+CONFIG_CAN_M_CAN=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MAC80211_LEDS=y
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* AW: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-18 6:17 ` Yang, Wenyou
@ 2017-04-18 6:37 ` Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
1 sibling, 0 replies; 18+ messages in thread
From: Huettel Mario (AE/PJ-SCI1) @ 2017-04-18 6:37 UTC (permalink / raw)
To: Yang, Wenyou, Quentin Schulz; +Cc: linux-can
Hello Wenyou,
I think I've found something suspicious:
*Both* M_CAN nodes are configured like this:
> bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
This means they're operating in the same memory region with exactly the same memory layout.
This does not have to be the cause of your problem but I think this is an error.
-----Ursprüngliche Nachricht-----
Von: Yang, Wenyou [mailto:Wenyou.Yang@Microchip.com]
Gesendet: Dienstag, 18. April 2017 08:18
An: Huettel Mario (AE/PJ-SCI1) <Mario.Huettel@de.bosch.com>; Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: linux-can@vger.kernel.org
Betreff: Re: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
Hi Mario,
The device tree patch is attached.
Here is the configure and log.
---8<----
# ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can0 up
# ip link set can1 up
# ip -details link show can0
2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# ip -details link show can1
3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# candump can1 &
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
#
--->8----
Hope it is helpful for you.
Any question, please don't hesitate to come back.
Best Regards,
Wenyou Yang
On 2017/4/18 14:04, Huettel Mario (AE/PJ-SCI1) wrote:
> Hi Quentin, hi Wenyou,
>
> Today I've received another email that the driver is not working with the
> M_CAN in Atmel's SAMA5D2.
>
> Can you send me the device tree you're using and post the dmesg output
> of the m_can driver?
>
> There might be a clue why it isn't working.
> The fact that it is working one time and then stops working looks like some problem
> In the TX FIFO to me. Can you please check with some third device/oscilloscope,
> if the controller is sending data. I want to know ehre the problem lies. If it's in the TX or
> RX path.
>
> As for now I can only throw some ideas into the round:
> * What are the PCLK and CCLK values? CCLK >= PCLK?
> * TX FIFO configured to one element and something happens in that case.
> * No TX Event FIFO element configured. The driver also doesn't work in this case.
>
>
> Quentin wrote:
>> Hi Oliver,
>>
>> On 13/04/2017 08:30, Oliver Hartkopp wrote:
>>> Hi Wenyou,
>>>
>>> as Quentin had no problems in his setup:
>>>
>> Actually just retested by doing the same as Wenyou on my SAMA5D2
>> Xplained and I can attest I'm having the same behavior as Wenyou.
>>
>> Best regards,
>> Quentin
>
> \x13��칻\x1c�&�~�&�\x18��+-��ݶ\x17��w��˛���m�b��\jx��\x17��ܨ}���Ơz�&j:+v���\r����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
^ permalink raw reply [flat|nested] 18+ messages in thread
* AW: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-18 6:17 ` Yang, Wenyou
2017-04-18 6:37 ` AW: " Huettel Mario (AE/PJ-SCI1)
@ 2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:52 ` Wenyou.Yang
2017-04-19 7:11 ` AW: " Yang, Wenyou
1 sibling, 2 replies; 18+ messages in thread
From: Huettel Mario (AE/PJ-SCI1) @ 2017-04-18 6:50 UTC (permalink / raw)
To: Yang, Wenyou, Quentin Schulz; +Cc: linux-can
Hello Wenyou,
The line
bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
configures:
addr. Offset: 0
0x sidf
0x xidf
32x RX FIFO 0
0x RX FIFO 1
0x RX Buffer
0x TXE FIFO
1x TX Buffer
Because you are not using the TXE FIFO the driver doesn't detect the transmission of the message and therefore doesn't ree the Buffer.
The TXE FIFO is needed in my driver approach. And the TX buffer doesn't have to be 1 element. It can be more.
I would recommend testing something like:
bosch,mram-cfg = <0x0 0 0 32 0 0 10 10>;
This configures 10 TX Event FIFO elements and 10 TX Buffers/FIFO slots.
The values are only an example. You can set them to whatever you want as long as they stay in the specified range according to the user's manual.
Mario
-----Ursprüngliche Nachricht-----
Von: Yang, Wenyou [mailto:Wenyou.Yang@Microchip.com]
Gesendet: Dienstag, 18. April 2017 08:18
An: Huettel Mario (AE/PJ-SCI1) <Mario.Huettel@de.bosch.com>; Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: linux-can@vger.kernel.org
Betreff: Re: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
Hi Mario,
The device tree patch is attached.
Here is the configure and log.
---8<----
# ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
fd-non-iso on
# ip link set can0 up
# ip link set can1 up
# ip -details link show can0
2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# ip -details link show can1
3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
mode DEFAULT group default qlen 10
link/can promiscuity 0
can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
restart-ms 0
bitrate 125000 sample-point 0.875
tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
dbitrate 4000000 dsample-point 0.700
dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
clock 40000000
# candump can1 &
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
# cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
#
--->8----
Hope it is helpful for you.
Any question, please don't hesitate to come back.
Best Regards,
Wenyou Yang
On 2017/4/18 14:04, Huettel Mario (AE/PJ-SCI1) wrote:
> Hi Quentin, hi Wenyou,
>
> Today I've received another email that the driver is not working with the
> M_CAN in Atmel's SAMA5D2.
>
> Can you send me the device tree you're using and post the dmesg output
> of the m_can driver?
>
> There might be a clue why it isn't working.
> The fact that it is working one time and then stops working looks like some problem
> In the TX FIFO to me. Can you please check with some third device/oscilloscope,
> if the controller is sending data. I want to know ehre the problem lies. If it's in the TX or
> RX path.
>
> As for now I can only throw some ideas into the round:
> * What are the PCLK and CCLK values? CCLK >= PCLK?
> * TX FIFO configured to one element and something happens in that case.
> * No TX Event FIFO element configured. The driver also doesn't work in this case.
>
>
> Quentin wrote:
>> Hi Oliver,
>>
>> On 13/04/2017 08:30, Oliver Hartkopp wrote:
>>> Hi Wenyou,
>>>
>>> as Quentin had no problems in his setup:
>>>
>> Actually just retested by doing the same as Wenyou on my SAMA5D2
>> Xplained and I can attest I'm having the same behavior as Wenyou.
>>
>> Best regards,
>> Quentin
>
> \x13��칻\x1c�&�~�&�\x18��+-��ݶ\x17��w��˛���m�b��\jx��\x17��ܨ}���Ơz�&j:+v���
����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
@ 2017-04-18 6:52 ` Wenyou.Yang
2017-04-19 7:11 ` AW: " Yang, Wenyou
1 sibling, 0 replies; 18+ messages in thread
From: Wenyou.Yang @ 2017-04-18 6:52 UTC (permalink / raw)
To: Mario.Huettel, quentin.schulz; +Cc: linux-can
Hi Mario,
> -----Original Message-----
> From: linux-can-owner@vger.kernel.org [mailto:linux-can-owner@vger.kernel.org]
> On Behalf Of Huettel Mario (AE/PJ-SCI1)
> Sent: 2017年4月18日 14:50
> To: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>; Quentin Schulz
> <quentin.schulz@free-electrons.com>
> Cc: linux-can@vger.kernel.org
> Subject: AW: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for
> M_CAN IP version >= v3.1.x
>
> Hello Wenyou,
>
> The line
> bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
> configures:
> addr. Offset: 0
> 0x sidf
> 0x xidf
> 32x RX FIFO 0
> 0x RX FIFO 1
> 0x RX Buffer
> 0x TXE FIFO
> 1x TX Buffer
>
> Because you are not using the TXE FIFO the driver doesn't detect the
> transmission of the message and therefore doesn't ree the Buffer.
> The TXE FIFO is needed in my driver approach. And the TX buffer doesn't have to
> be 1 element. It can be more.
> I would recommend testing something like:
>
> bosch,mram-cfg = <0x0 0 0 32 0 0 10 10>; This configures 10 TX Event FIFO
> elements and 10 TX Buffers/FIFO slots.
> The values are only an example. You can set them to whatever you want as long
> as they stay in the specified range according to the user's manual.
Thank you for your information.
I will test it on my side.
Any progress, I will let you know. Thank you.
>
> Mario
>
Best Regards,
Wenyou Yang
> -----Ursprüngliche Nachricht-----
> Von: Yang, Wenyou [mailto:Wenyou.Yang@Microchip.com]
> Gesendet: Dienstag, 18. April 2017 08:18
> An: Huettel Mario (AE/PJ-SCI1) <Mario.Huettel@de.bosch.com>; Quentin Schulz
> <quentin.schulz@free-electrons.com>
> Cc: linux-can@vger.kernel.org
> Betreff: Re: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for
> M_CAN IP version >= v3.1.x
>
> Hi Mario,
>
> The device tree patch is attached.
>
> Here is the configure and log.
>
> ---8<----
>
> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on fd-non-iso on # ip
> link set can1 type can bitrate 125000 dbitrate 4000000 fd on fd-non-iso on # ip link
> set can0 up # ip link set can1 up # ip -details link show can0
> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
> UNKNOWN mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-
> ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # ip -details link show can1
> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
> UNKNOWN mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-
> ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # candump can1 &
> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC # cansend can0
> 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> #
>
> --->8----
>
> Hope it is helpful for you.
>
> Any question, please don't hesitate to come back.
>
>
> Best Regards,
>
> Wenyou Yang
>
>
> On 2017/4/18 14:04, Huettel Mario (AE/PJ-SCI1) wrote:
> > Hi Quentin, hi Wenyou,
> >
> > Today I've received another email that the driver is not working with
> > the M_CAN in Atmel's SAMA5D2.
> >
> > Can you send me the device tree you're using and post the dmesg output
> > of the m_can driver?
> >
> > There might be a clue why it isn't working.
> > The fact that it is working one time and then stops working looks like
> > some problem In the TX FIFO to me. Can you please check with some
> > third device/oscilloscope, if the controller is sending data. I want
> > to know ehre the problem lies. If it's in the TX or RX path.
> >
> > As for now I can only throw some ideas into the round:
> > * What are the PCLK and CCLK values? CCLK >= PCLK?
> > * TX FIFO configured to one element and something happens in that case.
> > * No TX Event FIFO element configured. The driver also doesn't work in this
> case.
> >
> >
> > Quentin wrote:
> >> Hi Oliver,
> >>
> >> On 13/04/2017 08:30, Oliver Hartkopp wrote:
> >>> Hi Wenyou,
> >>>
> >>> as Quentin had no problems in his setup:
> >>>
> >> Actually just retested by doing the same as Wenyou on my SAMA5D2
> >> Xplained and I can attest I'm having the same behavior as Wenyou.
> >>
> >> Best regards,
> >> Quentin
> >
> > \x13 칻\x1c & ~ & \x18 +- ݶ\x17 w ˛ m b \jx \x17 ܨ} Ơz &j:+v
> zZ+ +zf h ~ i z \x1e w ? & )ߢ^[f
>
> \x13 칻\x1c & ~ & \x18 +- ݶ\x17 w ˛ m b \jx \x17 ܨ} Ơz &j:+v zZ+ +zf h ~ i
> z \x1e w ? & )ߢ^[f
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: AW: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:52 ` Wenyou.Yang
@ 2017-04-19 7:11 ` Yang, Wenyou
1 sibling, 0 replies; 18+ messages in thread
From: Yang, Wenyou @ 2017-04-19 7:11 UTC (permalink / raw)
To: Huettel Mario (AE/PJ-SCI1), Quentin Schulz; +Cc: linux-can
Hi Mario,
On 2017/4/18 14:50, Huettel Mario (AE/PJ-SCI1) wrote:
> Hello Wenyou,
>
> The line
> bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
> configures:
> addr. Offset: 0
> 0x sidf
> 0x xidf
> 32x RX FIFO 0
> 0x RX FIFO 1
> 0x RX Buffer
> 0x TXE FIFO
> 1x TX Buffer
>
> Because you are not using the TXE FIFO the driver doesn't detect the transmission of the message and therefore doesn't ree the Buffer.
> The TXE FIFO is needed in my driver approach. And the TX buffer doesn't have to be 1 element. It can be more.
> I would recommend testing something like:
>
> bosch,mram-cfg = <0x0 0 0 32 0 0 10 10>;
> This configures 10 TX Event FIFO elements and 10 TX Buffers/FIFO slots.
> The values are only an example. You can set them to whatever you want as long as they stay in the specified range according to the user's manual.
As your advice, I tested it, it works.
Thanks a lot.
>
> Mario
>
> -----Ursprüngliche Nachricht-----
> Von: Yang, Wenyou [mailto:Wenyou.Yang@Microchip.com]
> Gesendet: Dienstag, 18. April 2017 08:18
> An: Huettel Mario (AE/PJ-SCI1) <Mario.Huettel@de.bosch.com>; Quentin Schulz <quentin.schulz@free-electrons.com>
> Cc: linux-can@vger.kernel.org
> Betreff: Re: AW: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
>
> Hi Mario,
>
> The device tree patch is attached.
>
> Here is the configure and log.
>
> ---8<----
>
> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
> fd-non-iso on
> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
> fd-non-iso on
> # ip link set can0 up
> # ip link set can1 up
> # ip -details link show can0
> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
> mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
> restart-ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # ip -details link show can1
> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UNKNOWN
> mode DEFAULT group default qlen 10
> link/can promiscuity 0
> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
> restart-ms 0
> bitrate 125000 sample-point 0.875
> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
> dbitrate 4000000 dsample-point 0.700
> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp-inc 1
> clock 40000000
> # candump can1 &
> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
> #
>
> --->8----
>
> Hope it is helpful for you.
>
> Any question, please don't hesitate to come back.
>
>
> Best Regards,
>
> Wenyou Yang
>
>
> On 2017/4/18 14:04, Huettel Mario (AE/PJ-SCI1) wrote:
>> Hi Quentin, hi Wenyou,
>>
>> Today I've received another email that the driver is not working with the
>> M_CAN in Atmel's SAMA5D2.
>>
>> Can you send me the device tree you're using and post the dmesg output
>> of the m_can driver?
>>
>> There might be a clue why it isn't working.
>> The fact that it is working one time and then stops working looks like some problem
>> In the TX FIFO to me. Can you please check with some third device/oscilloscope,
>> if the controller is sending data. I want to know ehre the problem lies. If it's in the TX or
>> RX path.
>>
>> As for now I can only throw some ideas into the round:
>> * What are the PCLK and CCLK values? CCLK >= PCLK?
>> * TX FIFO configured to one element and something happens in that case.
>> * No TX Event FIFO element configured. The driver also doesn't work in this case.
>>
>>
>> Quentin wrote:
>>> Hi Oliver,
>>>
>>> On 13/04/2017 08:30, Oliver Hartkopp wrote:
>>>> Hi Wenyou,
>>>>
>>>> as Quentin had no problems in his setup:
>>>>
>>> Actually just retested by doing the same as Wenyou on my SAMA5D2
>>> Xplained and I can attest I'm having the same behavior as Wenyou.
>>>
>>> Best regards,
>>> Quentin
>> \x13��칻\x1c�&�~�&�\x18��+-��ݶ\x17��w��˛���m�b��\jx��\x17��ܨ}���Ơz�&j:+v���
> ����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
>
> \x13��칻\x1c�&�~�&�\x18��+-��ݶ\x17��w��˛���m�b��\jx��\x17��ܨ}���Ơz�&j:+v���\a����zZ+��+zf���h���~����i���z�\x1e�w���?����&�)ߢ^[f
Best Regards,
Wenyou Yang
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
[not found] ` <0f51bfad-b6ac-6cb5-0487-5b746eecb8b7@Microchip.com>
@ 2017-04-19 13:05 ` Quentin Schulz
2017-04-19 13:08 ` Oliver Hartkopp
1 sibling, 0 replies; 18+ messages in thread
From: Quentin Schulz @ 2017-04-19 13:05 UTC (permalink / raw)
To: Yang, Wenyou, Mario Hüttel, linux-can, Oliver Hartkopp,
nicolas.ferre, Alexandre Belloni, Yang, Wenyou
Hi Oliver,
On 19/04/2017 09:19, Yang, Wenyou wrote:
> Hi Oliver,
>
> According to the feedback from Mario, its cause is the dt configuration
> is not adapted.
>
> I tested it again. It works fine.
>
Same here.
I've tested with the updated DT Wenyou sent on the LAKML (so on a
SAMA5D2 Xplained) and did the following:
# ip link set can0 down
# ip link set can0 up type can bitrate 125000
# cansend can0 500#1E.10.10
Last line at least 10 times, every message is received on my computer.
Same with can1. Tested with candump can0 as well, everything looks fine.
Thank you Mario and Wenyou,
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Best regards,
Quentin
> On 2017/4/12 16:47, Yang, Wenyou wrote:
>>
>> Hi Mario,
>>
>> I tried to test this patch series on M_CAN IP 3.1.0 (CREL =
>> 0x31040730) of SAMA5D2 Xplained board,
>>
>> I applied the patches on both v4.11-rc6 and v4.9.21.
>>
>> But it didn't work well
>>
>> Connected the two CAN interfaces on the same chips, CAN0 as a sender,
>> the CAN1 as receiver.
>>
>> At the first time, the CAN1 received the data correctly from the CAN0,
>> from the second time, it didn't receive data any more.
>>
>> Here are the configuration and log.
>>
>> --->8---
>>
>> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can0 up
>> # ip link set can1 up
>> # ip -details link show can0
>> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
>> UNKNOWN mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # ip -details link show can1
>> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
>> UNKNOWN mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # candump can1 &
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> #
>>
>> ---8<---
>>
>> I don't know if the configuration is right.
>>
>> Do you have some advice? Thank you.
>>
>> Best Regards,
>> Wenyou Yang
>>
>>
>> On 2017/4/8 20:10, Mario Hüttel wrote:
>>> From: Mario Huettel <mario.huettel@gmx.net>
>>>
>>> * Added defines for TX Event FIFO Element
>>> * Adapted ndo_start_xmit function.
>>> For versions >= v3.1.x it uses the TX FIFO to optimize the data
>>> throughput. It stores the echo skb at the same index as in the
>>> M_CAN's TX FIFO. The frame's message marker is set to this index.
>>> This message marker is received in the TX Event FIFO after
>>> the message was successfully transmitted. It is used to echo the
>>> correct echo skb back to the network stack.
>>> * Added m_can_echo_tx_event function. It reads all received
>>> message markers in the TX Event FIFO and loops back the
>>> corresponding echo skbs.
>>> * ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
>>>
>>> Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
>>> ---
>>> drivers/net/can/m_can/m_can.c | 188 +++++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 159 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
>>> index 2fa0f44..5361e07 100644
>>> --- a/drivers/net/can/m_can/m_can.c
>>> +++ b/drivers/net/can/m_can/m_can.c
>>> @@ -334,6 +334,11 @@ enum m_can_mram_cfg {
>>> #define TX_BUF_MM_SHIFT 24
>>> #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
>>>
>>> +/* Tx event FIFO Element */
>>> +/* E1 */
>>> +#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
>>> +#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
>>> +
>>> /* address offset and element number for each FIFO/Buffer in the Message RAM */
>>> struct mram_cfg {
>>> u16 off;
>>> @@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi, int quota)
>>> return work_done;
>>> }
>>>
>>> +static void m_can_echo_tx_event(struct net_device *dev)
>>> +{
>>> + u32 txe_count = 0;
>>> + u32 m_can_txefs;
>>> + u32 fgi = 0;
>>> + int i = 0;
>>> + unsigned int msg_mark;
>>> +
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + struct net_device_stats *stats = &dev->stats;
>>> +
>>> + /* read tx event fifo status */
>>> + m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
>>> +
>>> + /* Get Tx Event fifo element count */
>>> + txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
>>> + >> TXEFS_EFFL_SHIFT;
>>> +
>>> + /* Get and process all sent elements */
>>> + for (i = 0; i < txe_count; i++) {
>>> + /* retrieve get index */
>>> + fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
>>> + >> TXEFS_EFGI_SHIFT;
>>> +
>>> + /* get message marker */
>>> + msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
>>> + TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
>>> +
>>> + /* ack txe element */
>>> + m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
>>> + (fgi << TXEFA_EFAI_SHIFT)));
>>> +
>>> + /* update stats */
>>> + stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
>>> + stats->tx_packets++;
>>> + }
>>> +}
>>> +
>>> static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> {
>>> struct net_device *dev = (struct net_device *)dev_id;
>>> @@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> napi_schedule(&priv->napi);
>>> }
>>>
>>> - /* transmission complete interrupt */
>>> - if (ir & IR_TC) {
>>> - stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> - stats->tx_packets++;
>>> - can_led_event(dev, CAN_LED_EVENT_TX);
>>> - netif_wake_queue(dev);
>>> + if (priv->version == 30) {
>>> + if (ir & IR_TC) {
>>> + /* Transmission Complete Interrupt*/
>>> + stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> + stats->tx_packets++;
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + netif_wake_queue(dev);
>>> + }
>>> + } else {
>>> + if (ir & IR_TEFN) {
>>> + /* New TX FIFO Element arrived */
>>> + m_can_echo_tx_event(dev);
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + if (netif_queue_stopped(dev) &&
>>> + !m_can_tx_fifo_full(priv))
>>> + netif_wake_queue(dev);
>>> + }
>>> }
>>>
>>> return IRQ_HANDLED;
>>> @@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
>>> return 0;
>>> }
>>>
>>> +static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
>>> +{
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + /*get wrap around for loopback skb index */
>>> + unsigned int wrap = priv->can.echo_skb_max;
>>> + int next_idx;
>>> +
>>> + /* calculate next index */
>>> + next_idx = (++putidx >= wrap ? 0 : putidx);
>>> +
>>> + /* check if occupied */
>>> + return !!priv->can.echo_skb[next_idx];
>>> +}
>>> +
>>> static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> struct net_device *dev)
>>> {
>>> struct m_can_priv *priv = netdev_priv(dev);
>>> struct canfd_frame *cf = (struct canfd_frame *)skb->data;
>>> - u32 id, cccr;
>>> + u32 id, cccr, fdflags;
>>> int i;
>>> + int putidx;
>>>
>>> if (can_dropped_invalid_skb(dev, skb))
>>> return NETDEV_TX_OK;
>>>
>>> - netif_stop_queue(dev);
>>> -
>>> + /* Generate ID field for TX buffer Element */
>>> + /* Common to all supported M_CAN versions */
>>> if (cf->can_id & CAN_EFF_FLAG) {
>>> id = cf->can_id & CAN_EFF_MASK;
>>> id |= TX_BUF_XTD;
>>> @@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> if (cf->can_id & CAN_RTR_FLAG)
>>> id |= TX_BUF_RTR;
>>>
>>> - /* message ram configuration */
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
>>> + if (priv->version == 30) {
>>> + netif_stop_queue(dev);
>>> +
>>> + /* message ram configuration */
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
>>> + can_len2dlc(cf->len) << 16);
>>>
>>> - for (i = 0; i < cf->len; i += 4)
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
>>> - *(u32 *)(cf->data + i));
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, 0,
>>> + M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + can_put_echo_skb(skb, dev, 0);
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> + cccr = m_can_read(priv, M_CAN_CCCR);
>>> + cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + if (can_is_canfd_skb(skb)) {
>>> + if (cf->flags & CANFD_BRS)
>>> + cccr |= CCCR_CMR_CANFD_BRS <<
>>> + CCCR_CMR_SHIFT;
>>> + else
>>> + cccr |= CCCR_CMR_CANFD <<
>>> + CCCR_CMR_SHIFT;
>>> + } else {
>>> + cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + }
>>> + m_can_write(priv, M_CAN_CCCR, cccr);
>>> + }
>>> + m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> + m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* End of xmit function for version 3.0.x */
>>> + } else {
>>> + /* Transmit routine for version >= v3.1.x */
>>> +
>>> + /* Check if FIFO full */
>>> + if (m_can_tx_fifo_full(priv)) {
>>> + /* This shouldn't happen */
>>> + netif_stop_queue(dev);
>>> + netdev_warn(dev,
>>> + "TX queue active although FIFO is full.");
>>> + return NETDEV_TX_BUSY;
>>> + }
>>>
>>> - can_put_echo_skb(skb, dev, 0);
>>> + /* get put index for frame */
>>> + putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
>>> + >> TXFQS_TFQPI_SHIFT);
>>> + /* Write ID Field to FIFO Element */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
>>>
>>> - if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> - cccr = m_can_read(priv, M_CAN_CCCR);
>>> - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + /* get CAN FD configuration of frame */
>>> + fdflags = 0;
>>> if (can_is_canfd_skb(skb)) {
>>> + fdflags |= TX_BUF_FDF;
>>> if (cf->flags & CANFD_BRS)
>>> - cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
>>> - else
>>> - cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
>>> - } else {
>>> - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + fdflags |= TX_BUF_BRS;
>>> }
>>> - m_can_write(priv, M_CAN_CCCR, cccr);
>>> - }
>>>
>>> - /* enable first TX buffer to start transfer */
>>> - m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> - m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* Construct DLC Field. Also contains CAN-FD configuration
>>> + * use put index of fifo as message marker
>>> + * it is used in TX interrupt for
>>> + * sending the correct echo frame
>>> + */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
>>> + ((putidx << TX_BUF_MM_SHIFT) &
>>> + TX_BUF_MM_MASK) |
>>> + (can_len2dlc(cf->len) << 16) |
>>> + fdflags | TX_BUF_EFC);
>>> +
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + /* Push loopback echo.
>>> + * Will be looped back on TX interrupt based on message marker
>>> + */
>>> + can_put_echo_skb(skb, dev, putidx);
>>> +
>>> + /* Enable TX FIFO element to start transfer */
>>> + m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
>>> +
>>> + /* stop network queue if fifo full */
>>> + if (m_can_tx_fifo_full(priv) ||
>>> + m_can_next_echo_skb_occupied(dev, putidx))
>>> + netif_stop_queue(dev);
>>> + }
>>>
>>> return NETDEV_TX_OK;
>>> }
>>> @@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
>>> /* Probe finished
>>> * Stop clocks. They will be reactivated once the M_CAN device is opened
>>> */
>>> +
>>> goto disable_cclk_ret;
>>>
>>> failed_free_dev:
>>
>
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x
[not found] ` <0f51bfad-b6ac-6cb5-0487-5b746eecb8b7@Microchip.com>
2017-04-19 13:05 ` Quentin Schulz
@ 2017-04-19 13:08 ` Oliver Hartkopp
1 sibling, 0 replies; 18+ messages in thread
From: Oliver Hartkopp @ 2017-04-19 13:08 UTC (permalink / raw)
To: Yang, Wenyou, Mario Hüttel, quentin.schulz, Marc Kleine-Budde
Cc: linux-can, nicolas.ferre, Alexandre Belloni, Yang, Wenyou
Hi Wenyou and Quentin,
many thanks for testing! So Marc can upstream Mario's latest version
when he's back in the office.
Good work, Mario!
Best regards,
Oliver
On 04/19/2017 09:19 AM, Yang, Wenyou wrote:
> Hi Oliver,
>
> According to the feedback from Mario, its cause is the dt configuration
> is not adapted.
>
> I tested it again. It works fine.
>
> Added,
>
> Tested-by: Wenyou Yang <wenyou.yang@microchip.com>
>
> I will send the new version patch of dt configuration later.
>
>
> Best Regards,
> Wenyou Yang
>
> On 2017/4/12 16:47, Yang, Wenyou wrote:
>>
>> Hi Mario,
>>
>> I tried to test this patch series on M_CAN IP 3.1.0 (CREL =
>> 0x31040730) of SAMA5D2 Xplained board,
>>
>> I applied the patches on both v4.11-rc6 and v4.9.21.
>>
>> But it didn't work well
>>
>> Connected the two CAN interfaces on the same chips, CAN0 as a sender,
>> the CAN1 as receiver.
>>
>> At the first time, the CAN1 received the data correctly from the CAN0,
>> from the second time, it didn't receive data any more.
>>
>> Here are the configuration and log.
>>
>> --->8---
>>
>> # ip link set can0 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can1 type can bitrate 125000 dbitrate 4000000 fd on
>> fd-non-iso on
>> # ip link set can0 up
>> # ip link set can1 up
>> # ip -details link show can0
>> 2: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
>> UNKNOWN mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # ip -details link show can1
>> 3: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state
>> UNKNOWN mode DEFAULT group default qlen 10
>> link/can promiscuity 0
>> can <FD,FD-NON-ISO> state ERROR-ACTIVE (berr-counter tx 0 rx 0)
>> restart-ms 0
>> bitrate 125000 sample-point 0.875
>> tq 50 prop-seg 69 phase-seg1 70 phase-seg2 20 sjw 1
>> m_can: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..512 brp-inc 1
>> dbitrate 4000000 dsample-point 0.700
>> dtq 25 dprop-seg 3 dphase-seg1 3 dphase-seg2 3 dsjw 1
>> m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32
>> dbrp-inc 1
>> clock 40000000
>> # candump can1 &
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> can1 5A1 [12] 11 22 33 44 55 66 77 88 99 AA BB CC
>> # cansend can0 5A1##111.22.33.44.55.66.77.88.99.aa.bb.cc
>> #
>>
>> ---8<---
>>
>> I don't know if the configuration is right.
>>
>> Do you have some advice? Thank you.
>>
>> Best Regards,
>> Wenyou Yang
>>
>>
>> On 2017/4/8 20:10, Mario Hüttel wrote:
>>> From: Mario Huettel <mario.huettel@gmx.net>
>>>
>>> * Added defines for TX Event FIFO Element
>>> * Adapted ndo_start_xmit function.
>>> For versions >= v3.1.x it uses the TX FIFO to optimize the data
>>> throughput. It stores the echo skb at the same index as in the
>>> M_CAN's TX FIFO. The frame's message marker is set to this index.
>>> This message marker is received in the TX Event FIFO after
>>> the message was successfully transmitted. It is used to echo the
>>> correct echo skb back to the network stack.
>>> * Added m_can_echo_tx_event function. It reads all received
>>> message markers in the TX Event FIFO and loops back the
>>> corresponding echo skbs.
>>> * ISR checks for new TX Event Entry interrupt for version >= 3.1.x.
>>>
>>> Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
>>> ---
>>> drivers/net/can/m_can/m_can.c | 188 +++++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 159 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
>>> index 2fa0f44..5361e07 100644
>>> --- a/drivers/net/can/m_can/m_can.c
>>> +++ b/drivers/net/can/m_can/m_can.c
>>> @@ -334,6 +334,11 @@ enum m_can_mram_cfg {
>>> #define TX_BUF_MM_SHIFT 24
>>> #define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
>>>
>>> +/* Tx event FIFO Element */
>>> +/* E1 */
>>> +#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
>>> +#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
>>> +
>>> /* address offset and element number for each FIFO/Buffer in the Message RAM */
>>> struct mram_cfg {
>>> u16 off;
>>> @@ -817,6 +822,44 @@ static int m_can_poll(struct napi_struct *napi, int quota)
>>> return work_done;
>>> }
>>>
>>> +static void m_can_echo_tx_event(struct net_device *dev)
>>> +{
>>> + u32 txe_count = 0;
>>> + u32 m_can_txefs;
>>> + u32 fgi = 0;
>>> + int i = 0;
>>> + unsigned int msg_mark;
>>> +
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + struct net_device_stats *stats = &dev->stats;
>>> +
>>> + /* read tx event fifo status */
>>> + m_can_txefs = m_can_read(priv, M_CAN_TXEFS);
>>> +
>>> + /* Get Tx Event fifo element count */
>>> + txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
>>> + >> TXEFS_EFFL_SHIFT;
>>> +
>>> + /* Get and process all sent elements */
>>> + for (i = 0; i < txe_count; i++) {
>>> + /* retrieve get index */
>>> + fgi = (m_can_read(priv, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
>>> + >> TXEFS_EFGI_SHIFT;
>>> +
>>> + /* get message marker */
>>> + msg_mark = (m_can_txe_fifo_read(priv, fgi, 4) &
>>> + TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
>>> +
>>> + /* ack txe element */
>>> + m_can_write(priv, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
>>> + (fgi << TXEFA_EFAI_SHIFT)));
>>> +
>>> + /* update stats */
>>> + stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
>>> + stats->tx_packets++;
>>> + }
>>> +}
>>> +
>>> static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> {
>>> struct net_device *dev = (struct net_device *)dev_id;
>>> @@ -843,12 +886,23 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
>>> napi_schedule(&priv->napi);
>>> }
>>>
>>> - /* transmission complete interrupt */
>>> - if (ir & IR_TC) {
>>> - stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> - stats->tx_packets++;
>>> - can_led_event(dev, CAN_LED_EVENT_TX);
>>> - netif_wake_queue(dev);
>>> + if (priv->version == 30) {
>>> + if (ir & IR_TC) {
>>> + /* Transmission Complete Interrupt*/
>>> + stats->tx_bytes += can_get_echo_skb(dev, 0);
>>> + stats->tx_packets++;
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + netif_wake_queue(dev);
>>> + }
>>> + } else {
>>> + if (ir & IR_TEFN) {
>>> + /* New TX FIFO Element arrived */
>>> + m_can_echo_tx_event(dev);
>>> + can_led_event(dev, CAN_LED_EVENT_TX);
>>> + if (netif_queue_stopped(dev) &&
>>> + !m_can_tx_fifo_full(priv))
>>> + netif_wake_queue(dev);
>>> + }
>>> }
>>>
>>> return IRQ_HANDLED;
>>> @@ -1291,19 +1345,34 @@ static int m_can_close(struct net_device *dev)
>>> return 0;
>>> }
>>>
>>> +static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
>>> +{
>>> + struct m_can_priv *priv = netdev_priv(dev);
>>> + /*get wrap around for loopback skb index */
>>> + unsigned int wrap = priv->can.echo_skb_max;
>>> + int next_idx;
>>> +
>>> + /* calculate next index */
>>> + next_idx = (++putidx >= wrap ? 0 : putidx);
>>> +
>>> + /* check if occupied */
>>> + return !!priv->can.echo_skb[next_idx];
>>> +}
>>> +
>>> static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> struct net_device *dev)
>>> {
>>> struct m_can_priv *priv = netdev_priv(dev);
>>> struct canfd_frame *cf = (struct canfd_frame *)skb->data;
>>> - u32 id, cccr;
>>> + u32 id, cccr, fdflags;
>>> int i;
>>> + int putidx;
>>>
>>> if (can_dropped_invalid_skb(dev, skb))
>>> return NETDEV_TX_OK;
>>>
>>> - netif_stop_queue(dev);
>>> -
>>> + /* Generate ID field for TX buffer Element */
>>> + /* Common to all supported M_CAN versions */
>>> if (cf->can_id & CAN_EFF_FLAG) {
>>> id = cf->can_id & CAN_EFF_MASK;
>>> id |= TX_BUF_XTD;
>>> @@ -1314,33 +1383,93 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
>>> if (cf->can_id & CAN_RTR_FLAG)
>>> id |= TX_BUF_RTR;
>>>
>>> - /* message ram configuration */
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
>>> + if (priv->version == 30) {
>>> + netif_stop_queue(dev);
>>> +
>>> + /* message ram configuration */
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
>>> + m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC,
>>> + can_len2dlc(cf->len) << 16);
>>>
>>> - for (i = 0; i < cf->len; i += 4)
>>> - m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
>>> - *(u32 *)(cf->data + i));
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, 0,
>>> + M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + can_put_echo_skb(skb, dev, 0);
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> + cccr = m_can_read(priv, M_CAN_CCCR);
>>> + cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + if (can_is_canfd_skb(skb)) {
>>> + if (cf->flags & CANFD_BRS)
>>> + cccr |= CCCR_CMR_CANFD_BRS <<
>>> + CCCR_CMR_SHIFT;
>>> + else
>>> + cccr |= CCCR_CMR_CANFD <<
>>> + CCCR_CMR_SHIFT;
>>> + } else {
>>> + cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + }
>>> + m_can_write(priv, M_CAN_CCCR, cccr);
>>> + }
>>> + m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> + m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* End of xmit function for version 3.0.x */
>>> + } else {
>>> + /* Transmit routine for version >= v3.1.x */
>>> +
>>> + /* Check if FIFO full */
>>> + if (m_can_tx_fifo_full(priv)) {
>>> + /* This shouldn't happen */
>>> + netif_stop_queue(dev);
>>> + netdev_warn(dev,
>>> + "TX queue active although FIFO is full.");
>>> + return NETDEV_TX_BUSY;
>>> + }
>>>
>>> - can_put_echo_skb(skb, dev, 0);
>>> + /* get put index for frame */
>>> + putidx = ((m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
>>> + >> TXFQS_TFQPI_SHIFT);
>>> + /* Write ID Field to FIFO Element */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_ID, id);
>>>
>>> - if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
>>> - cccr = m_can_read(priv, M_CAN_CCCR);
>>> - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
>>> + /* get CAN FD configuration of frame */
>>> + fdflags = 0;
>>> if (can_is_canfd_skb(skb)) {
>>> + fdflags |= TX_BUF_FDF;
>>> if (cf->flags & CANFD_BRS)
>>> - cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
>>> - else
>>> - cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
>>> - } else {
>>> - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
>>> + fdflags |= TX_BUF_BRS;
>>> }
>>> - m_can_write(priv, M_CAN_CCCR, cccr);
>>> - }
>>>
>>> - /* enable first TX buffer to start transfer */
>>> - m_can_write(priv, M_CAN_TXBTIE, 0x1);
>>> - m_can_write(priv, M_CAN_TXBAR, 0x1);
>>> + /* Construct DLC Field. Also contains CAN-FD configuration
>>> + * use put index of fifo as message marker
>>> + * it is used in TX interrupt for
>>> + * sending the correct echo frame
>>> + */
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DLC,
>>> + ((putidx << TX_BUF_MM_SHIFT) &
>>> + TX_BUF_MM_MASK) |
>>> + (can_len2dlc(cf->len) << 16) |
>>> + fdflags | TX_BUF_EFC);
>>> +
>>> + for (i = 0; i < cf->len; i += 4)
>>> + m_can_fifo_write(priv, putidx, M_CAN_FIFO_DATA(i / 4),
>>> + *(u32 *)(cf->data + i));
>>> +
>>> + /* Push loopback echo.
>>> + * Will be looped back on TX interrupt based on message marker
>>> + */
>>> + can_put_echo_skb(skb, dev, putidx);
>>> +
>>> + /* Enable TX FIFO element to start transfer */
>>> + m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
>>> +
>>> + /* stop network queue if fifo full */
>>> + if (m_can_tx_fifo_full(priv) ||
>>> + m_can_next_echo_skb_occupied(dev, putidx))
>>> + netif_stop_queue(dev);
>>> + }
>>>
>>> return NETDEV_TX_OK;
>>> }
>>> @@ -1516,6 +1645,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
>>> /* Probe finished
>>> * Stop clocks. They will be reactivated once the M_CAN device is opened
>>> */
>>> +
>>> goto disable_cclk_ret;
>>>
>>> failed_free_dev:
>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2017-04-19 13:08 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-08 12:10 [PATCH v4 1/7] can: m_can: Disabled Interrupt Line 1 Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 2/7] can: m_can: Removed initialization of FIFO water marks Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 3/7] can: m_can: Removed virtual address from print Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 4/7] can: m_can: Updated register defines to newest version Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 5/7] can: m_can: Enable M_CAN version dependent initialization Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 6/7] can: m_can: Configuration for TX and TX event FIFOs Mario Hüttel
2017-04-08 12:10 ` [PATCH v4 7/7] can: m_can: Enable TX FIFO Handling for M_CAN IP version >= v3.1.x Mario Hüttel
[not found] ` <1f88411b-aa58-4e17-02cb-43fc0ffb953c@Microchip.com>
2017-04-13 6:30 ` Oliver Hartkopp
2017-04-13 6:50 ` Quentin Schulz
2017-04-18 6:04 ` AW: " Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:17 ` Yang, Wenyou
2017-04-18 6:37 ` AW: " Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:50 ` Huettel Mario (AE/PJ-SCI1)
2017-04-18 6:52 ` Wenyou.Yang
2017-04-19 7:11 ` AW: " Yang, Wenyou
2017-04-14 6:04 ` Yang, Wenyou
[not found] ` <0f51bfad-b6ac-6cb5-0487-5b746eecb8b7@Microchip.com>
2017-04-19 13:05 ` Quentin Schulz
2017-04-19 13:08 ` Oliver Hartkopp
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