* [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
#phy-cells = <1>;
};
+ ehci0: usb at 01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb at 01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb at 01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-14 13:15 ` Icenowy Zheng
0 siblings, 0 replies; 9+ messages in thread
From: Icenowy Zheng @ 2017-04-14 13:15 UTC (permalink / raw)
To: linux-arm-kernel
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-17 7:49 ` Maxime Ripard
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Ripard @ 2017-04-17 7:49 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 374 bytes --]
On Fri, Apr 14, 2017 at 09:15:55PM +0800, Icenowy Zheng wrote:
> As we have USB0 controller switch available on A64, we should now enable
> the EHCI0/OHCI0 controllers for Pine64.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied both, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-17 7:49 ` Maxime Ripard
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Ripard @ 2017-04-17 7:49 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
[-- Attachment #1: Type: text/plain, Size: 381 bytes --]
On Fri, Apr 14, 2017 at 09:15:55PM +0800, Icenowy Zheng wrote:
> As we have USB0 controller switch available on A64, we should now enable
> the EHCI0/OHCI0 controllers for Pine64.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Applied both, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64
@ 2017-04-17 7:49 ` Maxime Ripard
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Ripard @ 2017-04-17 7:49 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 14, 2017 at 09:15:55PM +0800, Icenowy Zheng wrote:
> As we have USB0 controller switch available on A64, we should now enable
> the EHCI0/OHCI0 controllers for Pine64.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied both, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-04-17 7:50 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-14 13:15 [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI Icenowy Zheng
2017-04-14 13:15 ` Icenowy Zheng
2017-04-14 13:15 ` Icenowy Zheng
2017-04-14 13:15 ` [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64 Icenowy Zheng
2017-04-14 13:15 ` Icenowy Zheng
2017-04-14 13:15 ` Icenowy Zheng
2017-04-17 7:49 ` Maxime Ripard
2017-04-17 7:49 ` Maxime Ripard
2017-04-17 7:49 ` Maxime Ripard
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