* [PATCH 00/24] DC Linux Patches Apr 25, 2017
@ 2017-04-25 18:38 Harry Wentland
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
A lot of patches this time around since I haven't gotten around to
this for a while.
* Clean up contexts in DC in preparation for DC atomic state tracking
* Some backports from drm-next tree that won't break on 4.9
* get_atomic_property implementation
* Populate YUV plane types in preparation for underlay
* Bunch of fixes in DC
Charlene Liu (2):
drm/amd/display: adding FCLK and DPPCLK clock types
drm/amd/display: use full surface update when stream is NULL
Ding Wang (1):
drm/amd/display: Fix for tile MST
Dmytro Laktyushkin (1):
drm/amd/display: update dce8 & 10 bw programming
Eric Cook (1):
drm/amd/display: FreeSync LFC MIN/MAX update on current frame
Harry Wentland (8):
drm/amd/display: Allow planes on all crtcs
drm/amd/display: Remove unused scratch_val_ctx
drm/amd/display: Get rid of temp_flip_context
drm/amd/display: Add lock around updating freesync property
drm/amd/display: pull commit_surfaces out of atomic_commit into helper
function
drm/amd/display: Copy ctx to current_context instead of assign
drm/amd/display: Move resource_validate_ctx_destruct to dc.h
drm/amd/display: Return context from validate_context
Jordan Lazare (1):
drm/amd/display: Fix missing irq refactor causing potential i2c race
Leon Elazar (2):
drm/amd/display: Memory was freed twice during disable
drm/amd/display: set NULL value during removal for remoteSink
Pratik Vishwakarma (1):
drm/amd/display: get_atomic_property missing for drm_connector_funcs
Shirish S (1):
drm/amd/display: initialize YUV plane capabilities
Sylvia Tsai (2):
drm/amd/display: Adding dm controlled signal type in dc_stream
drm/amd/display: Parse scanline registers
Vitaly Prosyak (1):
drm/amd/display: Add support for programming stereo sync
Yongqiang Sun (2):
drm/amd/display: Add same check as reset pipes for programing backend
regs.
drm/amd/display: change mpo surface update check condition.
Zeyu Fan (1):
drm/amd/display: Fix hotspot programming during set cursor position.
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 277 ++++++++++++++-------
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 6 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 108 ++++----
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 34 +--
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 21 +-
drivers/gpu/drm/amd/display/dc/dc.h | 19 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 -
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 -
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 11 +-
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 12 +
.../drm/amd/display/dc/dce/dce_stream_encoder.h | 14 +-
.../amd/display/dc/dce100/dce100_hw_sequencer.c | 28 +--
.../amd/display/dc/dce100/dce100_hw_sequencer.h | 7 +-
.../drm/amd/display/dc/dce100/dce100_resource.c | 1 +
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 18 +-
.../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 11 +-
.../display/dc/dce110/dce110_timing_generator.c | 54 ++--
.../display/dc/dce110/dce110_timing_generator.h | 8 +-
.../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 15 +-
.../display/dc/dce120/dce120_timing_generator.c | 42 ++--
.../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 19 +-
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 4 +-
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 2 -
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 +
.../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 5 +
.../drm/amd/display/dc/inc/hw/timing_generator.h | 8 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 -
drivers/gpu/drm/amd/display/dc/inc/resource.h | 6 -
.../drm/amd/display/modules/freesync/freesync.c | 67 ++---
34 files changed, 528 insertions(+), 324 deletions(-)
--
2.11.0
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 01/24] drm/amd/display: adding FCLK and DPPCLK clock types
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 02/24] drm/amd/display: Fix hotspot programming during set cursor position Harry Wentland
` (22 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
Change-Id: I7f551ed36a23f98340ca048c954ef25fe05208f0
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index f89395e0c107..408141c6776e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -71,7 +71,9 @@ enum dm_pp_clock_type {
DM_PP_CLOCK_TYPE_DCFCLK,
DM_PP_CLOCK_TYPE_SOCCLK,
DM_PP_CLOCK_TYPE_PIXELCLK,
- DM_PP_CLOCK_TYPE_DISPLAYPHYCLK
+ DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
+ DM_PP_CLOCK_TYPE_DPPCLK,
+ DM_PP_CLOCK_TYPE_FCLK,
};
#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 02/24] drm/amd/display: Fix hotspot programming during set cursor position.
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-04-25 18:38 ` [PATCH 01/24] drm/amd/display: adding FCLK and DPPCLK clock types Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 03/24] drm/amd/display: Memory was freed twice during disable Harry Wentland
` (21 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
- Remove x,y hotspot from dc_cursor_attributes. Only program it
through setPosition.
Change-Id: I0b47eee65618494406fe65b17847ff5c32bb5b39
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 5 -----
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 7 -------
drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 11 ++++-------
drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 15 ++++-----------
4 files changed, 8 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 93a96f0fcee4..36540e1e9281 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -91,8 +91,6 @@ static void dm_set_cursor(
attributes.address.low_part = lower_32_bits(gpu_addr);
attributes.width = width;
attributes.height = height;
- attributes.x_hot = 0;
- attributes.y_hot = 0;
attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
attributes.rotation_angle = 0;
attributes.attribute_flags.value = 0;
@@ -119,7 +117,6 @@ static void dm_set_cursor(
position.x = x;
position.y = y;
- position.hot_spot_enable = true;
position.x_hotspot = xorigin;
position.y_hotspot = yorigin;
@@ -261,7 +258,6 @@ static int dm_crtc_cursor_set(
position.enable = false;
position.x = 0;
position.y = 0;
- position.hot_spot_enable = false;
if (amdgpu_crtc->stream) {
/*set cursor visible false*/
@@ -345,7 +341,6 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc,
position.x = x;
position.y = y;
- position.hot_spot_enable = true;
position.x_hotspot = xorigin;
position.y_hotspot = yorigin;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 568b7f0569f8..b785dd7b3a97 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -395,11 +395,6 @@ struct dc_cursor_position {
*/
bool enable;
- /*
- * This parameter indicates whether cursor hot spot should be
- * programmed
- */
- bool hot_spot_enable;
};
struct dc_cursor_mi_param {
@@ -464,8 +459,6 @@ struct dc_cursor_attributes {
/* Width and height should correspond to cursor surface width x heigh */
uint32_t width;
uint32_t height;
- uint32_t x_hot;
- uint32_t y_hot;
enum dc_cursor_color_format color_format;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c
index 1cab12ba8447..5b230b17fc5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c
@@ -86,11 +86,10 @@ void dce110_ipp_cursor_set_position(
program_position(ipp110, position->x, position->y);
- if (position->hot_spot_enable)
- program_hotspot(
- ipp110,
- position->x_hotspot,
- position->y_hotspot);
+ program_hotspot(
+ ipp110,
+ position->x_hotspot,
+ position->y_hotspot);
/* unlock cursor registers */
lock(ipp110, false);
@@ -111,8 +110,6 @@ bool dce110_ipp_cursor_set_attributes(
attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
- /* Program hot spot coordinates */
- program_hotspot(ipp110, attributes->x_hot, attributes->y_hot);
/*
* Program cursor size -- NOTE: HW spec specifies that HW register
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
index d520b5d7aa81..15671fd2cb9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
@@ -151,11 +151,10 @@ void dce120_ipp_cursor_set_position(
CURSOR_X_POSITION, position->x,
CURSOR_Y_POSITION, position->y);
- if (position->hot_spot_enable)
- DCP_REG_SET_2(
- DCP0_CUR_HOT_SPOT,
- CURSOR_HOT_SPOT_X, position->x_hotspot,
- CURSOR_HOT_SPOT_Y, position->y_hotspot);
+ DCP_REG_SET_2(
+ DCP0_CUR_HOT_SPOT,
+ CURSOR_HOT_SPOT_X, position->x_hotspot,
+ CURSOR_HOT_SPOT_Y, position->y_hotspot);
/* unlock cursor registers */
lock(ipp110, false);
@@ -176,12 +175,6 @@ bool dce120_ipp_cursor_set_attributes(
attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
- /* Program hot spot coordinates */
- DCP_REG_SET_2(
- DCP0_CUR_HOT_SPOT,
- CURSOR_HOT_SPOT_X, attributes->x_hot,
- CURSOR_HOT_SPOT_Y, attributes->y_hot);
-
/*
* Program cursor size -- NOTE: HW spec specifies that HW register
* stores size as (height - 1, width - 1)
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 03/24] drm/amd/display: Memory was freed twice during disable
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-04-25 18:38 ` [PATCH 01/24] drm/amd/display: adding FCLK and DPPCLK clock types Harry Wentland
2017-04-25 18:38 ` [PATCH 02/24] drm/amd/display: Fix hotspot programming during set cursor position Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 04/24] drm/amd/display: Adding dm controlled signal type in dc_stream Harry Wentland
` (20 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leon Elazar
From: Leon Elazar <leon.elazar@amd.com>
1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer
but them freeing the memory.
Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction
Change-Id: I225fb14741a30ca131aa7df179860c48964977eb
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 8ddad3a877d6..bd4524ef3a37 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1035,7 +1035,6 @@ static void get_ss_info_from_atombios(
}
*spread_spectrum_data = ss_data;
- dm_free(ss_data);
dm_free(ss_info);
return;
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 04/24] drm/amd/display: Adding dm controlled signal type in dc_stream
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 03/24] drm/amd/display: Memory was freed twice during disable Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 05/24] drm/amd/display: Add same check as reset pipes for programing backend regs Harry Wentland
` (19 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Sylvia Tsai
From: Sylvia Tsai <sylvia.tsai@amd.com>
- Adding dm controlled signal type in dc_stream
- Adding fallback to dvi signal when output signal is hdmi and the connector
type is not
Change-Id: Iec44e4035f2b9d1fb862a37bbd4e629515a97337
Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Sylvia Tsai <Sylvia.Tsai@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 30 +++++++++++------------
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 069f588a9e02..2d40864b7b48 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1237,22 +1237,22 @@ static struct audio *find_first_free_audio(struct resource_context *res_ctx)
static void update_stream_signal(struct core_stream *stream)
{
- const struct dc_sink *dc_sink = stream->public.sink;
-
- if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
- stream->signal = stream->sink->link->public.connector_signal;
- else if (dc_sink->sink_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
- dc_sink->sink_signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- /* For asic supports dual link DVI, we should adjust signal type
- * based on timing pixel clock. If pixel clock more than 165Mhz,
- * signal is dual link, otherwise, single link.
- */
- if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
- stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
+ if (stream->public.output_signal == SIGNAL_TYPE_NONE) {
+ const struct dc_sink *dc_sink = stream->public.sink;
+
+ if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
+ stream->signal =
+ stream->sink->link->
+ public.connector_signal;
else
- stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- else
- stream->signal = dc_sink->sink_signal;
+ stream->signal = dc_sink->sink_signal;
+ } else {
+ stream->signal = stream->public.output_signal;
+ }
+
+ if (stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK &&
+ stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ)
+ stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
}
bool resource_is_stream_unchanged(
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index a27a6aba0df1..97af8f63eec3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -411,6 +411,7 @@ enum surface_update_type {
struct dc_stream {
const struct dc_sink *sink;
struct dc_crtc_timing timing;
+ enum signal_type output_signal;
enum dc_color_space output_color_space;
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 05/24] drm/amd/display: Add same check as reset pipes for programing backend regs.
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 04/24] drm/amd/display: Adding dm controlled signal type in dc_stream Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 06/24] drm/amd/display: change mpo surface update check condition Harry Wentland
` (18 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: I195ba4aa84abbc2cfa3c29fe6b6f98bc65ec72e8
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 839c34409c63..7430be502efd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1689,6 +1689,10 @@ enum dc_status dce110_apply_ctx_to_hw(
if (pipe_ctx->stream == pipe_ctx_old->stream)
continue;
+ if (pipe_ctx->stream && pipe_ctx_old->stream
+ && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+ continue;
+
if (pipe_ctx->top_pipe)
continue;
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 06/24] drm/amd/display: change mpo surface update check condition.
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 05/24] drm/amd/display: Add same check as reset pipes for programing backend regs Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 07/24] drm/amd/display: set NULL value during removal for remoteSink Harry Wentland
` (17 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: If787d1384eae0cdee917effc939464e0abc8453d
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9a3507e743cf..203cb9d0c89d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1024,7 +1024,8 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
}
static enum surface_update_type get_plane_info_update_type(
- const struct dc_surface_update *u)
+ const struct dc_surface_update *u,
+ int surface_index)
{
struct dc_plane_info temp_plane_info = { { { { 0 } } } };
@@ -1049,7 +1050,11 @@ static enum surface_update_type get_plane_info_update_type(
/* Special Validation parameters */
temp_plane_info.format = u->plane_info->format;
- temp_plane_info.visible = u->plane_info->visible;
+
+ if (surface_index == 0)
+ temp_plane_info.visible = u->plane_info->visible;
+ else
+ temp_plane_info.visible = u->surface->visible;
if (memcmp(u->plane_info, &temp_plane_info,
sizeof(struct dc_plane_info)) != 0)
@@ -1111,7 +1116,8 @@ static enum surface_update_type get_scaling_info_update_type(
static enum surface_update_type det_surface_update(
const struct core_dc *dc,
- const struct dc_surface_update *u)
+ const struct dc_surface_update *u,
+ int surface_index)
{
const struct validate_context *context = dc->current_context;
enum surface_update_type type = UPDATE_TYPE_FAST;
@@ -1120,7 +1126,7 @@ static enum surface_update_type det_surface_update(
if (!is_surface_in_context(context, u->surface))
return UPDATE_TYPE_FULL;
- type = get_plane_info_update_type(u);
+ type = get_plane_info_update_type(u, surface_index);
if (overall_type < type)
overall_type = type;
@@ -1157,7 +1163,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
for (i = 0 ; i < surface_count; i++) {
enum surface_update_type type =
- det_surface_update(core_dc, &updates[i]);
+ det_surface_update(core_dc, &updates[i], i);
if (type == UPDATE_TYPE_FULL)
return type;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 07/24] drm/amd/display: set NULL value during removal for remoteSink
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 06/24] drm/amd/display: change mpo surface update check condition Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 08/24] drm/amd/display: Fix for tile MST Harry Wentland
` (16 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leon Elazar
From: Leon Elazar <leon.elazar@amd.com>
In MST case during removal of remote sink its descriptor pointer wasn't freed corectly.
Change-Id: I1fb201b44cf79d95a02253efe90cf032200c27c3
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 203cb9d0c89d..70dc02cf4dbb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1787,7 +1787,7 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink
dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
i++;
}
-
+ dc_link->remote_sinks[i] = NULL;
dc_link->sink_count--;
return;
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 08/24] drm/amd/display: Fix for tile MST
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 07/24] drm/amd/display: set NULL value during removal for remoteSink Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 09/24] drm/amd/display: Allow planes on all crtcs Harry Wentland
` (15 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ding Wang
From: Ding Wang <Ding.Wang@amd.com>
- Set stream signal type to be SST when setting non-tile timing on MST
tiled display.
- Disable MST on sink after disabling MST link.
- Enable MST on sink before enabling MST link.
Change-Id: I809c4fb6b7a83d544c4495230ced16909a7c1bef
Signed-off-by: Ding Wang <Ding.Wang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 ++
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b878fb9697d7..426f7f8187a6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1250,6 +1250,9 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx)
if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
return DC_OK;
+ /* set the sink to MST mode before enabling the link */
+ dp_enable_mst_on_sink(link, true);
+
return enable_link_dp(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9f12ba87827a..913b01cd7159 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2453,3 +2453,16 @@ bool dc_link_dp_set_test_pattern(
return true;
}
+
+void dp_enable_mst_on_sink(struct core_link *link, bool enable)
+{
+ unsigned char mstmCntl;
+
+ core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+ if (enable)
+ mstmCntl |= DP_MST_EN;
+ else
+ mstmCntl &= (~DP_MST_EN);
+
+ core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 3b814592fd70..316df150c1d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -129,6 +129,9 @@ void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal)
return;
dp_disable_link_phy(link, signal);
+
+ /* set the sink to SST mode after disabling the link */
+ dp_enable_mst_on_sink(link, false);
}
bool dp_set_hw_training_pattern(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index b0cf8e00059c..92c56e6f7588 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -57,4 +57,6 @@ void detect_dp_sink_caps(struct core_link *link);
bool is_dp_active_dongle(const struct core_link *link);
+void dp_enable_mst_on_sink(struct core_link *link, bool enable);
+
#endif /* __DC_LINK_DP_H__ */
--
2.11.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 09/24] drm/amd/display: Allow planes on all crtcs
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 08/24] drm/amd/display: Fix for tile MST Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:38 ` [PATCH 10/24] drm/amd/display: Fix missing irq refactor causing potential i2c race Harry Wentland
` (14 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
4.9 kernel will always add the assigned crtc to possible_crtcs on a
plane. This is no longer the case on newer kernels. Make sure we allow
any plane on any crtc.
Change-Id: I7c6ead102e9c0bb4d98160c344278f76418b1cc6
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 00b5ff467ded..222c3dcfed08 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1099,7 +1099,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail_free_planes;
}
mode_info->planes[i]->plane_type = mode_info->plane_type[i];
- if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) {
+ if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) {
DRM_ERROR("KMS: Failed to initialize plane\n");
goto fail_free_planes;
}
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 10/24] drm/amd/display: Fix missing irq refactor causing potential i2c race
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 09/24] drm/amd/display: Allow planes on all crtcs Harry Wentland
@ 2017-04-25 18:38 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 11/24] drm/amd/display: use full surface update when stream is NULL Harry Wentland
` (13 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jordan Lazare
From: Jordan Lazare <Jordan.Lazare@amd.com>
Change-Id: I3bd022ac9de6a68ba937d4df6396c0c90417eb5c
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 36540e1e9281..70826c7739c2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -31,8 +31,10 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_atomic.h>
+
#include "amdgpu.h"
#include "amdgpu_pm.h"
+#include "dm_helpers.h"
#include "dm_services_types.h"
#include "drm_edid.h"
@@ -3205,13 +3207,16 @@ static bool is_dp_capable_without_timing_msa(
{
uint8_t dpcd_data;
bool capable = false;
+
if (amdgpu_connector->dc_link &&
- dc_read_aux_dpcd(
- dc,
- amdgpu_connector->dc_link->link_index,
- DP_DOWN_STREAM_PORT_COUNT,
- &dpcd_data, sizeof(dpcd_data)))
+ dm_helpers_dp_read_dpcd(
+ NULL,
+ amdgpu_connector->dc_link,
+ DP_DOWN_STREAM_PORT_COUNT,
+ &dpcd_data,
+ sizeof(dpcd_data))) {
capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
+ }
return capable;
}
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 11/24] drm/amd/display: use full surface update when stream is NULL
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2017-04-25 18:38 ` [PATCH 10/24] drm/amd/display: Fix missing irq refactor causing potential i2c race Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 12/24] drm/amd/display: Parse scanline registers Harry Wentland
` (12 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
Change-Id: I70cb09ed6bbc3f368aedef36c5a4a4708823606c
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 70dc02cf4dbb..6576137ee189 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1155,7 +1155,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
int i;
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
- if (stream_status->surface_count != surface_count)
+ if (stream_status == NULL || stream_status->surface_count != surface_count)
return UPDATE_TYPE_FULL;
if (stream_update)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7430be502efd..1401331080c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1599,11 +1599,11 @@ enum dc_status dce110_apply_ctx_to_hw(
apply_min_clocks(dc, context, &clocks_state, true);
if (context->dispclk_khz
- > dc->current_context->dispclk_khz)
+ > dc->current_context->dispclk_khz) {
context->res_ctx.pool->display_clock->funcs->set_clock(
context->res_ctx.pool->display_clock,
context->dispclk_khz * 115 / 100);
-
+ }
/* program audio wall clock. use HDMI as clock source if HDMI
* audio active. Otherwise, use DP as clock source
* first, loop to find any HDMI audio, if not, loop find DP audio
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 12/24] drm/amd/display: Parse scanline registers
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 11/24] drm/amd/display: use full surface update when stream is NULL Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 13/24] drm/amd/display: Add support for programming stereo sync Harry Wentland
` (11 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Sylvia Tsai, Harry Wentland
From: Sylvia Tsai <sylvia.tsai@amd.com>
They could differ between ASIC generations
Change-Id: Ia352ae206273fe3a025579554cae4e3711a26fcc
Signed-off-by: Sylvia Tsai <sylvia.tsai@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++-
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 21 ++++++---
drivers/gpu/drm/amd/display/dc/dc.h | 7 ++-
.../display/dc/dce110/dce110_timing_generator.c | 54 ++++++++++------------
.../display/dc/dce110/dce110_timing_generator.h | 8 ++--
.../display/dc/dce120/dce120_timing_generator.c | 42 ++++++++---------
.../drm/amd/display/dc/inc/hw/timing_generator.h | 8 ++--
7 files changed, 89 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 222c3dcfed08..acd4c6751f56 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -109,6 +109,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
u32 *vbl, u32 *position)
{
+ uint32_t v_blank_start, v_blank_end, h_position, v_position;
+
if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL;
else {
@@ -119,7 +121,18 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
return 0;
}
- return dc_stream_get_scanoutpos(acrtc->stream, vbl, position);
+ /*
+ * TODO rework base driver to use values directly.
+ * for now parse it back into reg-format
+ */
+ dc_stream_get_scanoutpos(acrtc->stream,
+ &v_blank_start,
+ &v_blank_end,
+ &h_position,
+ &v_position);
+
+ *position = (v_position) || (h_position << 16);
+ *vbl = (v_blank_start) || (v_blank_end << 16);
}
return 0;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index bf209f7bbf98..3dbd6c0885d8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -282,12 +282,14 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream)
return 0;
}
-uint32_t dc_stream_get_scanoutpos(
- const struct dc_stream *dc_stream,
- uint32_t *vbl,
- uint32_t *position)
+bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream,
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position)
{
uint8_t i;
+ bool ret = false;
struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc);
struct resource_context *res_ctx =
@@ -299,10 +301,17 @@ uint32_t dc_stream_get_scanoutpos(
if (res_ctx->pipe_ctx[i].stream != stream)
continue;
- return tg->funcs->get_scanoutpos(tg, vbl, position);
+ tg->funcs->get_scanoutpos(tg,
+ v_blank_start,
+ v_blank_end,
+ h_position,
+ v_position);
+
+ ret = true;
+ break;
}
- return 0;
+ return ret;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 97af8f63eec3..7d548b4d0299 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -484,8 +484,11 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream);
* This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
* being refactored properly to be dce-specific
*/
-uint32_t dc_stream_get_scanoutpos(
- const struct dc_stream *stream, uint32_t *vbl, uint32_t *position);
+bool dc_stream_get_scanoutpos(const struct dc_stream *stream,
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position);
/*
* Structure to store surface/stream associations for validation
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 006412be7a02..7070aaf9e433 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -574,29 +574,26 @@ void dce110_timing_generator_get_crtc_positions(
* @param [out] vpos, hpos
*****************************************************************************
*/
-uint32_t dce110_timing_generator_get_crtc_scanoutpos(
+void dce110_timing_generator_get_crtc_scanoutpos(
struct timing_generator *tg,
- uint32_t *vbl,
- uint32_t *position)
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- /* TODO 1: Update the implementation once caller is updated
- * WARNING!! This function is returning the whole register value
- * because the caller is expecting it instead of proper vertical and
- * horizontal position. This should be a temporary implementation
- * until the caller is updated. */
- /* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */
-
- *vbl = dm_read_reg(tg->ctx,
+ uint32_t v_blank_start_end = dm_read_reg(tg->ctx,
CRTC_REG(mmCRTC_V_BLANK_START_END));
- *position = dm_read_reg(tg->ctx,
- CRTC_REG(mmCRTC_STATUS_POSITION));
+ *v_blank_start = get_reg_field_value(v_blank_start_end,
+ CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_START);
+ *v_blank_end = get_reg_field_value(v_blank_start_end,
+ CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_END);
- /* @TODO: return value should indicate if current
- * crtc is inside vblank*/
- return 0;
+ dce110_timing_generator_get_crtc_positions(tg, h_position, v_position);
}
/* TODO: is it safe to assume that mask/shift of Primary and Underlay
@@ -1875,34 +1872,31 @@ void dce110_tg_set_colors(struct timing_generator *tg,
bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- uint32_t vbl = 0;
+ uint32_t v_blank_start = 0;
+ uint32_t v_blank_end = 0;
uint32_t val = 0;
- uint32_t position, vbl_start;
+ uint32_t h_position, v_position;
tg->funcs->get_scanoutpos(
tg,
- &vbl,
- &position);
+ &v_blank_start,
+ &v_blank_end,
+ &h_position,
+ &v_position);
- if (vbl == 0)
+ if (v_blank_start == 0 || v_blank_end == 0)
return false;
- vbl_start =
- get_reg_field_value(
- vbl,
- CRTC_V_BLANK_START_END,
- CRTC_V_BLANK_START);
-
set_reg_field_value(
val,
- vbl_start,
+ v_blank_start,
CRTC_VERTICAL_INTERRUPT0_POSITION,
CRTC_VERTICAL_INTERRUPT0_LINE_START);
- /* Set interaval width for interrupt to fire to 1 scanline */
+ /* Set interval width for interrupt to fire to 1 scanline */
set_reg_field_value(
val,
- vbl_start + width,
+ v_blank_start + width,
CRTC_VERTICAL_INTERRUPT0_POSITION,
CRTC_VERTICAL_INTERRUPT0_LINE_END);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
index ca387b40fc67..f14a4d91cd8e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h
@@ -230,10 +230,12 @@ void dce110_timing_generator_set_static_screen_control(
struct timing_generator *tg,
uint32_t value);
-uint32_t dce110_timing_generator_get_crtc_scanoutpos(
+void dce110_timing_generator_get_crtc_scanoutpos(
struct timing_generator *tg,
- uint32_t *vbl,
- uint32_t *position);
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position);
void dce110_timing_generator_enable_advanced_request(
struct timing_generator *tg,
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 95cb1768aeb5..1318df7ed47e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -576,24 +576,28 @@ void dce120_timing_generator_set_drr(
}
}
-uint32_t dce120_timing_generator_get_crtc_scanoutpos(
+void dce120_timing_generator_get_crtc_scanoutpos(
struct timing_generator *tg,
- uint32_t *vbl,
- uint32_t *position)
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- *vbl = dm_read_reg_soc15(
+ uint32_t v_blank_start_end = dm_read_reg_soc15(
tg->ctx,
mmCRTC0_CRTC_V_BLANK_START_END,
tg110->offsets.crtc);
- *position = dm_read_reg_soc15(
- tg->ctx,
- mmCRTC0_CRTC_STATUS_POSITION,
- tg110->offsets.crtc);
+ *v_blank_start = get_reg_field_value(v_blank_start_end,
+ CRTC0_CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_START);
+ *v_blank_end = get_reg_field_value(v_blank_start_end,
+ CRTC0_CRTC_V_BLANK_START_END,
+ CRTC_V_BLANK_END);
- return 0;
+ dce120_timing_generator_get_crtc_positions(tg, h_position, v_position);
}
void dce120_timing_generator_enable_advanced_request(
@@ -1044,26 +1048,22 @@ static bool dce120_arm_vert_intr(
uint8_t width)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
- uint32_t vbl, position, vbl_start;
+ uint32_t v_blank_start, v_blank_end, h_position, v_position;
tg->funcs->get_scanoutpos(
tg,
- &vbl,
- &position);
+ &v_blank_start,
+ &v_blank_end,
+ &h_position,
+ &v_position);
- if (vbl == 0)
+ if (v_blank_start == 0 || v_blank_end == 0)
return false;
- vbl_start =
- get_reg_field_value(
- vbl,
- CRTC0_CRTC_V_BLANK_START_END,
- CRTC_V_BLANK_START);
-
CRTC_REG_SET_2(
CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION,
- CRTC_VERTICAL_INTERRUPT0_LINE_START, vbl_start,
- CRTC_VERTICAL_INTERRUPT0_LINE_END, vbl_start + width);
+ CRTC_VERTICAL_INTERRUPT0_LINE_START, v_blank_start,
+ CRTC_VERTICAL_INTERRUPT0_LINE_END, v_blank_start + width);
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 51902a4f8798..b3deaf2d8173 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -120,10 +120,12 @@ struct timing_generator_funcs {
int32_t *h_position,
int32_t *v_position);
uint32_t (*get_frame_count)(struct timing_generator *tg);
- uint32_t (*get_scanoutpos)(
+ void (*get_scanoutpos)(
struct timing_generator *tg,
- uint32_t *vbl,
- uint32_t *position);
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position);
void (*set_early_control)(struct timing_generator *tg,
uint32_t early_cntl);
void (*wait_for_state)(struct timing_generator *tg,
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 13/24] drm/amd/display: Add support for programming stereo sync
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 12/24] drm/amd/display: Parse scanline registers Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 14/24] drm/amd/display: FreeSync LFC MIN/MAX update on current frame Harry Wentland
` (10 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Change-Id: I7e9150b3a2a6aa9c99c84abf2960d3a72f5425ee
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 11 ++++++++---
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 12 ++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 14 ++++++++++++--
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 7 +++++++
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 +++++
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 5 +++++
6 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index 03ce9ba50b64..e5045d21a05c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -174,7 +174,8 @@ enum dce110_opp_reg_type {
OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
#define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\
OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
@@ -182,7 +183,8 @@ enum dce110_opp_reg_type {
OPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
OPP_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
#define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
@@ -195,7 +197,8 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
- OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh)
+ OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
#define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\
OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
@@ -244,6 +247,7 @@ enum dce110_opp_reg_type {
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
+ OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\
OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
@@ -308,6 +312,7 @@ enum dce110_opp_reg_type {
type FMT_RGB_RANDOM_ENABLE; \
type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
+ type FMT_STEREOSYNC_OVERRIDE; \
type FMT_RAND_R_SEED; \
type FMT_RAND_G_SEED; \
type FMT_RAND_B_SEED; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index f3e1a293351f..9713def6e481 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -1286,6 +1286,17 @@ void dce110_se_hdmi_audio_disable(
dce110_se_enable_audio_clock(enc, false);
}
+
+static void setup_stereo_sync(
+ struct stream_encoder *enc,
+ int tg_inst, bool enable)
+{
+ struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
+}
+
+
static const struct stream_encoder_funcs dce110_str_enc_funcs = {
.dp_set_stream_attribute =
dce110_stream_encoder_dp_set_stream_attribute,
@@ -1316,6 +1327,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
.hdmi_audio_setup = dce110_se_hdmi_audio_setup,
.hdmi_audio_disable = dce110_se_hdmi_audio_disable,
+ .setup_stereo_sync = setup_stereo_sync,
};
bool dce110_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
index c2f4050fc6dc..850e12a8db61 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
@@ -151,6 +151,8 @@
SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
+ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
@@ -265,7 +267,9 @@
SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
- SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@@ -281,7 +285,9 @@
SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
- SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
+ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+ SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
@@ -416,6 +422,8 @@ struct dce_stream_encoder_shift {
uint8_t AFMT_AUDIO_CLOCK_EN;
uint8_t TMDS_PIXEL_ENCODING;
uint8_t TMDS_COLOR_FORMAT;
+ uint8_t DIG_STEREOSYNC_SELECT;
+ uint8_t DIG_STEREOSYNC_GATE_EN;
uint8_t DP_DB_DISABLE;
uint8_t DP_MSA_MISC0;
uint8_t DP_MSA_HTOTAL;
@@ -543,6 +551,8 @@ struct dce_stream_encoder_mask {
uint32_t AFMT_AUDIO_SAMPLE_SEND;
uint32_t AFMT_AUDIO_CLOCK_EN;
uint32_t TMDS_PIXEL_ENCODING;
+ uint32_t DIG_STEREOSYNC_SELECT;
+ uint32_t DIG_STEREOSYNC_GATE_EN;
uint32_t TMDS_COLOR_FORMAT;
uint32_t DP_DB_DISABLE;
uint32_t DP_MSA_MISC0;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1401331080c5..6bf03d680314 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1056,6 +1056,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
stream->sink->link->link_enc,
pipe_ctx->stream->signal);
+ if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
+ pipe_ctx->stream_enc->funcs->setup_stereo_sync(
+ pipe_ctx->stream_enc,
+ pipe_ctx->tg->inst,
+ stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
+
+
/*vbios crtc_source_selection and encoder_setup will override fmt_C*/
pipe_ctx->opp->funcs->opp_program_fmt(
pipe_ctx->opp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index e01b831a7e7f..521bd21eb5df 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -316,6 +316,11 @@ struct opp_funcs {
struct hw_adjustment_range *range);
void (*opp_destroy)(struct output_pixel_processor **opp);
+
+ void (*opp_set_stereo_polarity)(
+ struct output_pixel_processor *opp,
+ bool enable,
+ bool rightEyePolarity);
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 674bebfe3bd2..9fb27bd360ac 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -118,6 +118,11 @@ struct stream_encoder_funcs {
void (*hdmi_audio_disable) (
struct stream_encoder *enc);
+
+ void (*setup_stereo_sync) (
+ struct stream_encoder *enc,
+ int tg_inst,
+ bool enable);
};
#endif /* STREAM_ENCODER_H_ */
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 14/24] drm/amd/display: FreeSync LFC MIN/MAX update on current frame
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 13/24] drm/amd/display: Add support for programming stereo sync Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 15/24] drm/amd/display: Remove unused scratch_val_ctx Harry Wentland
` (9 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Eric Cook
From: Eric Cook <Eric.Cook@amd.com>
- Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame
- Add in FreeSync update to MPO code path
Change-Id: I12fb498254086fbae8f19b4b3c718104dab62486
Signed-off-by: Eric Cook <Eric.Cook@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
---
.../drm/amd/display/modules/freesync/freesync.c | 67 +++++++++++++---------
1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 7a0731e2dbb0..94566c0a0e62 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -641,7 +641,8 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync,
void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
const struct dc_stream **streams, int num_streams)
{
- unsigned int index, v_total = 0;
+ unsigned int index, v_total, inserted_frame_v_total = 0;
+ unsigned int min_frame_duration_in_ns, vmax, vmin = 0;
struct freesync_state *state;
struct core_freesync *core_freesync = NULL;
@@ -665,19 +666,48 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
/* Only execute if in fullscreen mode */
if (state->fullscreen == true &&
- core_freesync->map[index].user_enable.enable_for_gaming) {
+ core_freesync->map[index].user_enable.enable_for_gaming &&
+ core_freesync->map[index].caps->btr_supported &&
+ state->btr.btr_active) {
+
+ /* TODO: pass in flag for Pre-DCE12 ASIC
+ * in order for frame variable duration to take affect,
+ * it needs to be done one VSYNC early, which is at
+ * frameCounter == 1.
+ * For DCE12 and newer updates to V_TOTAL_MIN/MAX
+ * will take affect on current frame
+ */
+ if (state->btr.frames_to_insert == state->btr.frame_counter) {
+
+ min_frame_duration_in_ns = ((unsigned int) (div64_u64(
+ (1000000000ULL * 1000000),
+ state->nominal_refresh_rate_in_micro_hz)));
+
+ calc_vmin_vmax(core_freesync, *streams, &vmin, &vmax);
- if (state->btr.btr_active)
- if (state->btr.frame_counter > 0)
+ inserted_frame_v_total = vmin;
- state->btr.frame_counter--;
+ if (min_frame_duration_in_ns / 1000)
+ inserted_frame_v_total =
+ state->btr.inserted_frame_duration_in_us *
+ vmin / (min_frame_duration_in_ns / 1000);
- if (state->btr.frame_counter == 1) {
+ /* Set length of inserted frames as v_total_max*/
+ vmax = inserted_frame_v_total;
+ vmin = inserted_frame_v_total;
- /* Restore FreeSync */
- set_freesync_on_streams(core_freesync, streams,
- num_streams);
+ /* Program V_TOTAL */
+ core_freesync->dc->stream_funcs.adjust_vmin_vmax(
+ core_freesync->dc, streams,
+ num_streams, vmin, vmax);
}
+
+ if (state->btr.frame_counter > 0)
+ state->btr.frame_counter--;
+
+ /* Restore FreeSync */
+ if (state->btr.frame_counter == 0)
+ set_freesync_on_streams(core_freesync, streams, num_streams);
}
/* If in fullscreen freesync mode or in video, do not program
@@ -1022,8 +1052,6 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
unsigned int frames_to_insert = 0;
- unsigned int inserted_frame_v_total = 0;
- unsigned int vmin = 0, vmax = 0;
unsigned int min_frame_duration_in_ns = 0;
struct freesync_state *state = &core_freesync->map[map_index].state;
@@ -1101,23 +1129,6 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
inserted_frame_duration_in_us =
state->time.min_render_time_in_us;
- /* We need the v_total_min from capability */
- calc_vmin_vmax(core_freesync, stream, &vmin, &vmax);
-
- inserted_frame_v_total = vmin;
- if (min_frame_duration_in_ns / 1000)
- inserted_frame_v_total = inserted_frame_duration_in_us *
- vmin / (min_frame_duration_in_ns / 1000);
-
- /* Set length of inserted frames as v_total_max*/
- vmax = inserted_frame_v_total;
-
- /* Program V_TOTAL */
- core_freesync->dc->stream_funcs.adjust_vmin_vmax(
- core_freesync->dc, &stream,
- 1, vmin,
- vmax);
-
/* Cache the calculated variables */
state->btr.inserted_frame_duration_in_us =
inserted_frame_duration_in_us;
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 15/24] drm/amd/display: Remove unused scratch_val_ctx
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 14/24] drm/amd/display: FreeSync LFC MIN/MAX update on current frame Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 16/24] drm/amd/display: Get rid of temp_flip_context Harry Wentland
` (8 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Change-Id: If74542b9c3d69f735147747f4a9bc41b0d70477a
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ---
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6576137ee189..7b0b7356ae89 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -411,8 +411,6 @@ static void destruct(struct core_dc *dc)
dc->current_context = NULL;
dm_free(dc->temp_flip_context);
dc->temp_flip_context = NULL;
- dm_free(dc->scratch_val_ctx);
- dc->scratch_val_ctx = NULL;
dm_free(dc->ctx);
dc->ctx = NULL;
@@ -432,7 +430,6 @@ static bool construct(struct core_dc *dc,
dc->current_context = dm_alloc(sizeof(*dc->current_context));
dc->temp_flip_context = dm_alloc(sizeof(*dc->temp_flip_context));
- dc->scratch_val_ctx = dm_alloc(sizeof(*dc->scratch_val_ctx));
if (!dc->current_context || !dc->temp_flip_context) {
dm_error("%s: failed to create validate ctx\n", __func__);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index 8d87f490dc1c..ec3edbe20d85 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -23,7 +23,6 @@ struct core_dc {
struct validate_context *current_context;
struct validate_context *temp_flip_context;
- struct validate_context *scratch_val_ctx;
struct resource_pool *res_pool;
/* Display Engine Clock levels */
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 16/24] drm/amd/display: Get rid of temp_flip_context
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 15/24] drm/amd/display: Remove unused scratch_val_ctx Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 17/24] drm/amd/display: update dce8 & 10 bw programming Harry Wentland
` (7 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
If we need to update our context we can allocate memory.
No need to keep temporary memory for this.
Change-Id: Ie91d318a1dd2283fe12e5380f015faa866f93230
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 26 +++++++++++++-------------
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 -
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7b0b7356ae89..e8499e744595 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -409,8 +409,6 @@ static void destruct(struct core_dc *dc)
dm_free(dc->current_context);
dc->current_context = NULL;
- dm_free(dc->temp_flip_context);
- dc->temp_flip_context = NULL;
dm_free(dc->ctx);
dc->ctx = NULL;
@@ -429,9 +427,8 @@ static bool construct(struct core_dc *dc,
}
dc->current_context = dm_alloc(sizeof(*dc->current_context));
- dc->temp_flip_context = dm_alloc(sizeof(*dc->temp_flip_context));
- if (!dc->current_context || !dc->temp_flip_context) {
+ if (!dc->current_context) {
dm_error("%s: failed to create validate ctx\n", __func__);
goto val_ctx_fail;
}
@@ -874,13 +871,9 @@ bool dc_commit_streams(
}
resource_validate_ctx_destruct(core_dc->current_context);
+ dm_free(core_dc->current_context);
- if (core_dc->temp_flip_context != core_dc->current_context) {
- dm_free(core_dc->temp_flip_context);
- core_dc->temp_flip_context = core_dc->current_context;
- }
core_dc->current_context = context;
- memset(core_dc->temp_flip_context, 0, sizeof(*core_dc->temp_flip_context));
return (result == DC_OK);
@@ -1212,7 +1205,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
new_surfaces[i] = srf_updates[i].surface;
/* initialize scratch memory for building context */
- context = core_dc->temp_flip_context;
+ context = dm_alloc(sizeof(*context));
resource_validate_ctx_copy_construct(
core_dc->current_context, context);
@@ -1220,7 +1213,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!resource_attach_surfaces_to_context(
new_surfaces, surface_count, dc_stream, context)) {
BREAK_TO_DEBUGGER();
- return;
+ goto fail;
}
} else {
context = core_dc->current_context;
@@ -1326,7 +1319,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (update_type == UPDATE_TYPE_FULL) {
if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
BREAK_TO_DEBUGGER();
- return;
+ goto fail;
} else
core_dc->hwss.set_bandwidth(core_dc, context, false);
}
@@ -1418,10 +1411,17 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (core_dc->current_context != context) {
resource_validate_ctx_destruct(core_dc->current_context);
- core_dc->temp_flip_context = core_dc->current_context;
+ dm_free(core_dc->current_context);
core_dc->current_context = context;
}
+ return;
+
+fail:
+ if (core_dc->current_context != context) {
+ resource_validate_ctx_destruct(context);
+ dm_free(context);
+ }
}
uint8_t dc_get_current_stream_count(const struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index ec3edbe20d85..f9363f642f92 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -22,7 +22,6 @@ struct core_dc {
struct core_link *links[MAX_PIPES * 2];
struct validate_context *current_context;
- struct validate_context *temp_flip_context;
struct resource_pool *res_pool;
/* Display Engine Clock levels */
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 17/24] drm/amd/display: update dce8 & 10 bw programming
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 16/24] drm/amd/display: Get rid of temp_flip_context Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 18/24] drm/amd/display: Add lock around updating freesync property Harry Wentland
` (6 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ie849339294198186c47ce21a26b082edf853762f
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
.../amd/display/dc/dce100/dce100_hw_sequencer.c | 28 +++++++++++-----------
.../amd/display/dc/dce100/dce100_hw_sequencer.h | 7 +++---
.../drm/amd/display/dc/dce100/dce100_resource.c | 1 +
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +--
.../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 19 +--------------
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ----
6 files changed, 21 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index f11044e0245c..dd6f0b1bd8ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -28,6 +28,8 @@
#include "core_types.h"
#include "hw_sequencer.h"
#include "dce100_hw_sequencer.h"
+#include "resource.h"
+
#include "dce110/dce110_hw_sequencer.h"
/* include DCE10 register header files */
@@ -104,7 +106,7 @@ static bool dce100_enable_display_power_gating(
return false;
}
-void dce100_pplib_apply_display_requirements(
+static void dce100_pplib_apply_display_requirements(
struct core_dc *dc,
struct validate_context *context)
{
@@ -112,6 +114,8 @@ void dce100_pplib_apply_display_requirements(
pp_display_cfg->avail_mclk_switch_time_us =
dce110_get_min_vblank_time_us(context);
+ pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
+ / MEMORY_TYPE_MULTIPLIER;
dce110_fill_display_configs(context, pp_display_cfg);
@@ -122,20 +126,18 @@ void dce100_pplib_apply_display_requirements(
dc->prev_display_config = *pp_display_cfg;
}
-
-
-static void set_displaymarks(
- const struct core_dc *dc, struct validate_context *context)
-{
- /* Do nothing until we have proper bandwitdth calcs */
-}
-
-static void set_bandwidth(
+void dce100_set_bandwidth(
struct core_dc *dc,
struct validate_context *context,
bool decrease_allowed)
{
- dc->hwss.set_displaymarks(dc, context);
+ if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
+ context->res_ctx.pool->display_clock->funcs->set_clock(
+ context->res_ctx.pool->display_clock,
+ context->dispclk_khz * 115 / 100);
+ dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
+ dc->current_context->dispclk_khz = context->dispclk_khz;
+ }
dce100_pplib_apply_display_requirements(dc, context);
}
@@ -146,10 +148,8 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
{
dce110_hw_sequencer_construct(dc);
- /* TODO: dce80 is empty implementation at the moment*/
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
- dc->hwss.set_displaymarks = set_displaymarks;
- dc->hwss.set_bandwidth = set_bandwidth;
+ dc->hwss.set_bandwidth = dce100_set_bandwidth;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
index f51d04a66a49..24433f0e770b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
@@ -33,9 +33,10 @@ struct validate_context;
bool dce100_hw_sequencer_construct(struct core_dc *dc);
-void dce100_pplib_apply_display_requirements(
- struct core_dc *dc,
- struct validate_context *context);
+void dce100_set_bandwidth(
+ struct core_dc *dc,
+ struct validate_context *context,
+ bool decrease_allowed);
#endif /* __DC_HWSS_DCE100_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 7fae8537e18a..9b365597cec5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -771,6 +771,7 @@ bool dce100_validate_bandwidth(
{
/* TODO implement when needed but for now hardcode max value*/
context->dispclk_khz = 681000;
+ context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6bf03d680314..2fbf6ddcf3be 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2266,7 +2266,7 @@ static void dce110_set_bandwidth(
struct validate_context *context,
bool decrease_allowed)
{
- dc->hwss.set_displaymarks(dc, context);
+ dce110_set_displaymarks(dc, context);
if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
context->res_ctx.pool->display_clock->funcs->set_clock(
@@ -2468,7 +2468,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
- .set_displaymarks = dce110_set_displaymarks,
.set_bandwidth = dce110_set_bandwidth,
.set_drr = set_drr,
.set_static_screen_control = set_static_screen_control,
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
index 9d4e7d8b836e..4cba80ff6ca4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
@@ -107,30 +107,13 @@ static bool dce80_enable_display_power_gating(
return false;
}
-static void set_displaymarks(
- const struct core_dc *dc, struct validate_context *context)
-{
- /* Do nothing until we have proper bandwitdth calcs */
-}
-
-static void set_bandwidth(
- struct core_dc *dc,
- struct validate_context *context,
- bool decrease_allowed)
-{
- dc->hwss.set_displaymarks(dc, context);
- dce100_pplib_apply_display_requirements(dc, context);
-}
-
-
bool dce80_hw_sequencer_construct(struct core_dc *dc)
{
dce110_hw_sequencer_construct(dc);
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
- dc->hwss.set_displaymarks = set_displaymarks;
- dc->hwss.set_bandwidth = set_bandwidth;
+ dc->hwss.set_bandwidth = dce100_set_bandwidth;
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 077dc7573c52..9bfaaad09bea 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -123,10 +123,6 @@ struct hw_sequencer_funcs {
struct pipe_ctx *pipe,
bool lock);
- void (*set_displaymarks)(
- const struct core_dc *dc,
- struct validate_context *context);
-
void (*set_bandwidth)(
struct core_dc *dc,
struct validate_context *context,
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 18/24] drm/amd/display: Add lock around updating freesync property
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 17/24] drm/amd/display: update dce8 & 10 bw programming Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 19/24] drm/amd/display: pull commit_surfaces out of atomic_commit into helper function Harry Wentland
` (5 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Getting rid of the WARN_ONs in atomic_get_property
Change-Id: Ie1ecc69e06b2fc7d798902f308bc4b07e8a6e1f7
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 70826c7739c2..4eb3d819404a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1193,6 +1193,7 @@ static int amdgpu_freesync_update_property_atomic(
dev = connector->dev;
adev = dev->dev_private;
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
ret = drm_object_property_get_value(
&connector->base,
adev->mode_info.freesync_property,
@@ -1202,6 +1203,8 @@ static int amdgpu_freesync_update_property_atomic(
&connector->base,
adev->mode_info.freesync_property,
val_capable);
+ drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
return ret;
}
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 19/24] drm/amd/display: pull commit_surfaces out of atomic_commit into helper function
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 18/24] drm/amd/display: Add lock around updating freesync property Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 20/24] drm/amd/display: Copy ctx to current_context instead of assign Harry Wentland
` (4 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
This should make things simpler when we try to rework this later when we
pass validate_context from atomic_check to atomic_commit.
Change-Id: Icbf1514abff4b25163f4a54e73f41310e9bc970c
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 113 +++++++++++----------
1 file changed, 62 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 4eb3d819404a..78c346a4affa 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2483,6 +2483,67 @@ static void amdgpu_dm_do_flip(
acrtc->crtc_id);
}
+void dc_commit_surfaces(struct drm_atomic_state *state,
+ struct drm_device *dev, struct amdgpu_display_manager *dm)
+{
+ uint32_t i;
+ struct drm_plane *plane;
+ struct drm_plane_state *old_plane_state;
+
+ /* update planes when needed */
+ for_each_plane_in_state(state, plane, old_plane_state, i) {
+ struct drm_plane_state *plane_state = plane->state;
+ struct drm_crtc *crtc = plane_state->crtc;
+ struct drm_framebuffer *fb = plane_state->fb;
+ struct drm_connector *connector;
+ struct dm_connector_state *dm_state = NULL;
+ enum dm_commit_action action;
+ bool pflip_needed;
+
+ if (!fb || !crtc || !crtc->state->active)
+ continue;
+
+ action = get_dm_commit_action(crtc->state);
+
+ /* Surfaces are created under two scenarios:
+ * 1. This commit is not a page flip.
+ * 2. This commit is a page flip, and streams are created.
+ */
+ pflip_needed = !state->allow_modeset;
+ if (!pflip_needed || action == DM_COMMIT_ACTION_DPMS_ON
+ || action == DM_COMMIT_ACTION_SET) {
+ list_for_each_entry(connector,
+ &dev->mode_config.connector_list,
+ head) {
+ if (connector->state->crtc == crtc) {
+ dm_state = to_dm_connector_state(
+ connector->state);
+ break;
+ }
+ }
+
+ /*
+ * This situation happens in the following case:
+ * we are about to get set mode for connector who's only
+ * possible crtc (in encoder crtc mask) is used by
+ * another connector, that is why it will try to
+ * re-assing crtcs in order to make configuration
+ * supported. For our implementation we need to make all
+ * encoders support all crtcs, then this issue will
+ * never arise again. But to guard code from this issue
+ * check is left.
+ *
+ * Also it should be needed when used with actual
+ * drm_atomic_commit ioctl in future
+ */
+ if (!dm_state)
+ continue;
+
+ dm_dc_surface_commit(dm->dc, crtc);
+ }
+ }
+}
+
void amdgpu_dm_atomic_commit_tail(
struct drm_atomic_state *state)
{
@@ -2654,57 +2715,7 @@ void amdgpu_dm_atomic_commit_tail(
}
/* update planes when needed */
- for_each_plane_in_state(state, plane, old_plane_state, i) {
- struct drm_plane_state *plane_state = plane->state;
- struct drm_crtc *crtc = plane_state->crtc;
- struct drm_framebuffer *fb = plane_state->fb;
- struct drm_connector *connector;
- struct dm_connector_state *dm_state = NULL;
- enum dm_commit_action action;
- bool pflip_needed;
-
- if (!fb || !crtc || !crtc->state->active)
- continue;
-
- action = get_dm_commit_action(crtc->state);
-
- /* Surfaces are created under two scenarios:
- * 1. This commit is not a page flip.
- * 2. This commit is a page flip, and streams are created.
- */
- pflip_needed = !state->allow_modeset;
- if (!pflip_needed ||
- action == DM_COMMIT_ACTION_DPMS_ON ||
- action == DM_COMMIT_ACTION_SET) {
- list_for_each_entry(connector,
- &dev->mode_config.connector_list, head) {
- if (connector->state->crtc == crtc) {
- dm_state = to_dm_connector_state(
- connector->state);
- break;
- }
- }
-
- /*
- * This situation happens in the following case:
- * we are about to get set mode for connector who's only
- * possible crtc (in encoder crtc mask) is used by
- * another connector, that is why it will try to
- * re-assing crtcs in order to make configuration
- * supported. For our implementation we need to make all
- * encoders support all crtcs, then this issue will
- * never arise again. But to guard code from this issue
- * check is left.
- *
- * Also it should be needed when used with actual
- * drm_atomic_commit ioctl in future
- */
- if (!dm_state)
- continue;
-
- dm_dc_surface_commit(dm->dc, crtc);
- }
- }
+ dc_commit_surfaces(state, dev, dm);
for (i = 0; i < new_crtcs_count; i++) {
/*
--
2.11.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 20/24] drm/amd/display: Copy ctx to current_context instead of assign
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 19/24] drm/amd/display: pull commit_surfaces out of atomic_commit into helper function Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 21/24] drm/amd/display: Move resource_validate_ctx_destruct to dc.h Harry Wentland
` (3 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Change-Id: Iebcdb340c6ff5938886dc69fd6f005c3ab43c6e2
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e8499e744595..0d870e9c7c99 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -906,13 +906,13 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
resource_validate_ctx_copy_construct(core_dc->current_context, context);
post_surface_trace(dc);
-
for (i = 0; i < context->res_ctx.pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].stream == NULL) {
context->res_ctx.pipe_ctx[i].pipe_idx = i;
core_dc->hwss.power_down_front_end(
core_dc, &context->res_ctx.pipe_ctx[i]);
}
+
if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
BREAK_TO_DEBUGGER();
return false;
@@ -920,11 +920,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
core_dc->hwss.set_bandwidth(core_dc, context, true);
- resource_validate_ctx_destruct(core_dc->current_context);
- if (core_dc->current_context)
- dm_free(core_dc->current_context);
+ resource_validate_ctx_copy_construct(context, core_dc->current_context);
- core_dc->current_context = context;
+ resource_validate_ctx_destruct(context);
+ dm_free(context);
return true;
}
--
2.11.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 21/24] drm/amd/display: Move resource_validate_ctx_destruct to dc.h
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 20/24] drm/amd/display: Copy ctx to current_context instead of assign Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 22/24] drm/amd/display: Return context from validate_context Harry Wentland
` (2 subsequent siblings)
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
This will be needed to clean up context once we add it to private
atomic state.
Change-Id: I8722d0aa9652bf7ea44e7197588f0f8abbaeac58
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 22 +++++++++++-----------
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dc.h | 6 ++++++
drivers/gpu/drm/amd/display/dc/inc/resource.h | 6 ------
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0d870e9c7c99..5620fe361173 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -389,7 +389,7 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc)
static void destruct(struct core_dc *dc)
{
- resource_validate_ctx_destruct(dc->current_context);
+ dc_resource_validate_ctx_destruct(dc->current_context);
destroy_links(dc);
@@ -654,7 +654,7 @@ bool dc_validate_resources(
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, set_count, context);
- resource_validate_ctx_destruct(context);
+ dc_resource_validate_ctx_destruct(context);
dm_free(context);
context_alloc_fail:
@@ -684,7 +684,7 @@ bool dc_validate_guaranteed(
result = core_dc->res_pool->funcs->validate_guaranteed(
core_dc, stream, context);
- resource_validate_ctx_destruct(context);
+ dc_resource_validate_ctx_destruct(context);
dm_free(context);
context_alloc_fail:
@@ -838,7 +838,7 @@ bool dc_commit_streams(
__func__,
result);
BREAK_TO_DEBUGGER();
- resource_validate_ctx_destruct(context);
+ dc_resource_validate_ctx_destruct(context);
goto fail;
}
@@ -870,7 +870,7 @@ bool dc_commit_streams(
context->streams[i]->public.timing.pix_clk_khz);
}
- resource_validate_ctx_destruct(core_dc->current_context);
+ dc_resource_validate_ctx_destruct(core_dc->current_context);
dm_free(core_dc->current_context);
core_dc->current_context = context;
@@ -903,7 +903,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
dm_error("%s: failed to create validate ctx\n", __func__);
return false;
}
- resource_validate_ctx_copy_construct(core_dc->current_context, context);
+ dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
post_surface_trace(dc);
for (i = 0; i < context->res_ctx.pool->pipe_count; i++)
@@ -920,9 +920,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
core_dc->hwss.set_bandwidth(core_dc, context, true);
- resource_validate_ctx_copy_construct(context, core_dc->current_context);
+ dc_resource_validate_ctx_copy_construct(context, core_dc->current_context);
- resource_validate_ctx_destruct(context);
+ dc_resource_validate_ctx_destruct(context);
dm_free(context);
return true;
@@ -1205,7 +1205,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
/* initialize scratch memory for building context */
context = dm_alloc(sizeof(*context));
- resource_validate_ctx_copy_construct(
+ dc_resource_validate_ctx_copy_construct(
core_dc->current_context, context);
/* add surface to context */
@@ -1409,7 +1409,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
}
if (core_dc->current_context != context) {
- resource_validate_ctx_destruct(core_dc->current_context);
+ dc_resource_validate_ctx_destruct(core_dc->current_context);
dm_free(core_dc->current_context);
core_dc->current_context = context;
@@ -1418,7 +1418,7 @@ void dc_update_surfaces_and_stream(struct dc *dc,
fail:
if (core_dc->current_context != context) {
- resource_validate_ctx_destruct(context);
+ dc_resource_validate_ctx_destruct(context);
dm_free(context);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2d40864b7b48..2e12a0ba5ddf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2050,7 +2050,7 @@ static void set_vsc_info_packet(
/*TODO: stereo 3D support and extend pixel encoding colorimetry*/
}
-void resource_validate_ctx_destruct(struct validate_context *context)
+void dc_resource_validate_ctx_destruct(struct validate_context *context)
{
int i, j;
@@ -2069,7 +2069,7 @@ void resource_validate_ctx_destruct(struct validate_context *context)
* Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
* by the src_ctx
*/
-void resource_validate_ctx_copy_construct(
+void dc_resource_validate_ctx_copy_construct(
const struct validate_context *src_ctx,
struct validate_context *dst_ctx)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7d548b4d0299..7de2080e13ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -522,6 +522,12 @@ bool dc_validate_guaranteed(
const struct dc *dc,
const struct dc_stream *stream);
+void dc_resource_validate_ctx_copy_construct(
+ const struct validate_context *src_ctx,
+ struct validate_context *dst_ctx);
+
+void dc_resource_validate_ctx_destruct(struct validate_context *context);
+
/*
* Set up streams and links associated to drive sinks
* The streams parameter is an absolute set of all active streams.
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index eb9c96634578..b1987cab9751 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -141,12 +141,6 @@ void resource_validate_ctx_update_pointer_after_copy(
const struct validate_context *src_ctx,
struct validate_context *dst_ctx);
-void resource_validate_ctx_copy_construct(
- const struct validate_context *src_ctx,
- struct validate_context *dst_ctx);
-
-void resource_validate_ctx_destruct(struct validate_context *context);
-
enum dc_status resource_map_clock_resources(
const struct core_dc *dc,
struct validate_context *context);
--
2.11.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 22/24] drm/amd/display: Return context from validate_context
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 21/24] drm/amd/display: Move resource_validate_ctx_destruct to dc.h Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 23/24] drm/amd/display: initialize YUV plane capabilities Harry Wentland
2017-04-25 18:39 ` [PATCH 24/24] drm/amd/display: get_atomic_property missing for drm_connector_funcs Harry Wentland
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
This will allow us to carry it from check to commit
Change-Id: I367aa586498b2ff1a4bb2527d395a6451054cdf2
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 26 +++++++++++-----
drivers/gpu/drm/amd/display/dc/core/dc.c | 36 +++++++++++++++++-----
drivers/gpu/drm/amd/display/dc/dc.h | 5 +++
3 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 78c346a4affa..f6d41cf29cea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1508,6 +1508,7 @@ int amdgpu_dm_connector_mode_valid(
/* TODO: Unhardcode stream count */
struct dc_stream *stream;
struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
+ struct validate_context *context;
if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
(mode->flags & DRM_MODE_FLAG_DBLSCAN))
@@ -1542,8 +1543,13 @@ int amdgpu_dm_connector_mode_valid(
stream->src.height = mode->vdisplay;
stream->dst = stream->src;
- if (dc_validate_resources(adev->dm.dc, &val_set, 1))
+ context = dc_get_validate_context(adev->dm.dc, &val_set, 1);
+
+ if (context) {
result = MODE_OK;
+ dc_resource_validate_ctx_destruct(context);
+ dm_free(context);
+ }
dc_stream_release(stream);
@@ -2975,6 +2981,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
+ struct validate_context *context;
ret = drm_atomic_helper_check(dev, state);
@@ -3197,15 +3204,20 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
}
- if (need_to_validate == false || set_count == 0 ||
- dc_validate_resources(dc, set, set_count))
+ context = dc_get_validate_context(dc, set, set_count);
+
+ if (need_to_validate == false || set_count == 0 || context)
ret = 0;
- for (i = 0; i < set_count; i++) {
- for (j = 0; j < set[i].surface_count; j++) {
- dc_surface_release(set[i].surfaces[j]);
- }
+ if (context) {
+ dc_resource_validate_ctx_destruct(context);
+ dm_free(context);
}
+
+ for (i = 0; i < set_count; i++)
+ for (j = 0; j < set[i].surface_count; j++)
+ dc_surface_release(set[i].surfaces[j]);
+
for (i = 0; i < new_stream_count; i++)
dc_stream_release(new_streams[i]);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5620fe361173..64b5216fb920 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -635,7 +635,7 @@ static bool is_validation_required(
return false;
}
-bool dc_validate_resources(
+struct validate_context *dc_get_validate_context(
const struct dc *dc,
const struct dc_validation_set set[],
uint8_t set_count)
@@ -644,31 +644,51 @@ bool dc_validate_resources(
enum dc_status result = DC_ERROR_UNEXPECTED;
struct validate_context *context;
- if (!is_validation_required(core_dc, set, set_count))
- return true;
-
context = dm_alloc(sizeof(struct validate_context));
if(context == NULL)
goto context_alloc_fail;
+ if (!is_validation_required(core_dc, set, set_count)) {
+ dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
+ return context;
+ }
+
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, set_count, context);
- dc_resource_validate_ctx_destruct(context);
- dm_free(context);
-
context_alloc_fail:
if (result != DC_OK) {
dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
"%s:resource validation failed, dc_status:%d\n",
__func__,
result);
+
+ dc_resource_validate_ctx_destruct(context);
+ dm_free(context);
+ context = NULL;
}
- return (result == DC_OK);
+ return context;
}
+bool dc_validate_resources(
+ const struct dc *dc,
+ const struct dc_validation_set set[],
+ uint8_t set_count)
+{
+ struct validate_context *ctx;
+
+ ctx = dc_get_validate_context(dc, set, set_count);
+ if (ctx) {
+ dc_resource_validate_ctx_destruct(ctx);
+ dm_free(ctx);
+ return true;
+ }
+
+ return false;
+}
+
bool dc_validate_guaranteed(
const struct dc *dc,
const struct dc_stream *stream)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7de2080e13ed..1b3fd79ce624 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -505,6 +505,11 @@ struct dc_validation_set {
* After this call:
* No hardware is programmed for call. Only validation is done.
*/
+struct validate_context *dc_get_validate_context(
+ const struct dc *dc,
+ const struct dc_validation_set set[],
+ uint8_t set_count);
+
bool dc_validate_resources(
const struct dc *dc,
const struct dc_validation_set set[],
--
2.11.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 23/24] drm/amd/display: initialize YUV plane capabilities
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 22/24] drm/amd/display: Return context from validate_context Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
2017-04-25 18:39 ` [PATCH 24/24] drm/amd/display: get_atomic_property missing for drm_connector_funcs Harry Wentland
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Shirish S
From: Shirish S <shirish.s@amd.com>
This patch populates the YUV surface configurations.
Tests: (On Chromium OS for Stoney Only)
builds without any errors.
Change-Id: Ie6d6782cfe4b7cc470d27b664fcaf287499c00c6
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 62 ++++++++++++++++------
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index f6d41cf29cea..96f3cc1fc694 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -462,9 +462,6 @@ static void fill_plane_attributes_from_fb(
&tiling_flags,
addReq == true ? &fb_location:NULL);
- surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
- surface->address.grph.addr.low_part = lower_32_bits(fb_location);
- surface->address.grph.addr.high_part = upper_32_bits(fb_location);
switch (fb->pixel_format) {
case DRM_FORMAT_C8:
@@ -485,11 +482,54 @@ static void fill_plane_attributes_from_fb(
case DRM_FORMAT_ABGR2101010:
surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
+ case DRM_FORMAT_YUV420:
+ surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
+ break;
+ case DRM_FORMAT_YVU420:
+ surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
+ break;
default:
DRM_ERROR("Unsupported screen depth %d\n", fb->bits_per_pixel);
return;
}
+ if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+ surface->address.type = PLN_ADDR_TYPE_GRAPHICS;
+ surface->address.grph.addr.low_part = lower_32_bits(fb_location);
+ surface->address.grph.addr.high_part = upper_32_bits(fb_location);
+ surface->plane_size.grph.surface_size.x = 0;
+ surface->plane_size.grph.surface_size.y = 0;
+ surface->plane_size.grph.surface_size.width = fb->width;
+ surface->plane_size.grph.surface_size.height = fb->height;
+ surface->plane_size.grph.surface_pitch =
+ fb->pitches[0] / (fb->bits_per_pixel / 8);
+ /* TODO: unhardcode */
+ surface->color_space = COLOR_SPACE_SRGB;
+
+ } else {
+ surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
+ surface->address.video_progressive.luma_addr.low_part
+ = lower_32_bits(fb_location);
+ surface->address.video_progressive.chroma_addr.high_part
+ = upper_32_bits(fb_location);
+ surface->plane_size.video.luma_size.x = 0;
+ surface->plane_size.video.luma_size.y = 0;
+ surface->plane_size.video.luma_size.width = fb->width;
+ surface->plane_size.video.luma_size.height = fb->height;
+ /* TODO: unhardcode */
+ surface->plane_size.video.luma_pitch = fb->pitches[0] / 4;
+
+ surface->plane_size.video.chroma_size.x = 0;
+ surface->plane_size.video.chroma_size.y = 0;
+ surface->plane_size.video.chroma_size.width = fb->width;
+ surface->plane_size.video.chroma_size.height = fb->height;
+ surface->plane_size.video.chroma_pitch =
+ fb->pitches[0] / 4;
+
+ /* TODO: unhardcode */
+ surface->color_space = COLOR_SPACE_YCBCR709;
+ }
+
memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
/* Fill GFX params */
@@ -540,20 +580,10 @@ static void fill_plane_attributes_from_fb(
surface->tiling_info.gfx9.shaderEnable = 1;
}
-
- surface->plane_size.grph.surface_size.x = 0;
- surface->plane_size.grph.surface_size.y = 0;
- surface->plane_size.grph.surface_size.width = fb->width;
- surface->plane_size.grph.surface_size.height = fb->height;
- surface->plane_size.grph.surface_pitch =
- fb->pitches[0] / (fb->bits_per_pixel / 8);
-
surface->visible = true;
surface->scaling_quality.h_taps_c = 0;
surface->scaling_quality.v_taps_c = 0;
- /* TODO: unhardcode */
- surface->color_space = COLOR_SPACE_SRGB;
/* is this needed? is surface zeroed at allocation? */
surface->scaling_quality.h_taps = 0;
surface->scaling_quality.v_taps = 0;
@@ -1795,10 +1825,8 @@ static uint32_t rgb_formats[] = {
};
static uint32_t yuv_formats[] = {
- DRM_FORMAT_YUYV,
- DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY,
- DRM_FORMAT_VYUY,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
};
int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
--
2.11.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 24/24] drm/amd/display: get_atomic_property missing for drm_connector_funcs
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2017-04-25 18:39 ` [PATCH 23/24] drm/amd/display: initialize YUV plane capabilities Harry Wentland
@ 2017-04-25 18:39 ` Harry Wentland
23 siblings, 0 replies; 25+ messages in thread
From: Harry Wentland @ 2017-04-25 18:39 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
DRM_IOCTL_MODE_GETCONNECTOR fails with EINVAL on enabling DRIVER_ATOMIC
With this DRM_IOCTL_MODE_GETCONNECTOR returns all the connector properties.
freesync_property and freesync_capable_property return 0 currently.
TESTS(On Chromium OS on Stoney Only)
* Builds without compilation errors.
* 'atomictest' proceeds after applying patch and fails with vblank event
timed out.
* Chromium OS ui comes up.
Change-Id: Ia020a085e27a95492b15934223f8da8ee6b635bf
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 53 +++++++++++++++++++++-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 6 +++
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 96f3cc1fc694..1ae492c51481 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1376,6 +1376,56 @@ int amdgpu_dm_connector_atomic_set_property(
return ret;
}
+int amdgpu_dm_connector_atomic_get_property(
+ struct drm_connector *connector,
+ const struct drm_connector_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+ struct dm_connector_state *dm_state =
+ to_dm_connector_state(state);
+ int ret = -EINVAL;
+
+ if (property == dev->mode_config.scaling_mode_property) {
+ switch (dm_state->scaling) {
+ case RMX_CENTER:
+ *val = DRM_MODE_SCALE_CENTER;
+ break;
+ case RMX_ASPECT:
+ *val = DRM_MODE_SCALE_ASPECT;
+ break;
+ case RMX_FULL:
+ *val = DRM_MODE_SCALE_FULLSCREEN;
+ break;
+ case RMX_OFF:
+ default:
+ *val = DRM_MODE_SCALE_NONE;
+ break;
+ }
+ ret = 0;
+ } else if (property == adev->mode_info.underscan_hborder_property) {
+ *val = dm_state->underscan_hborder;
+ ret = 0;
+ } else if (property == adev->mode_info.underscan_vborder_property) {
+ *val = dm_state->underscan_vborder;
+ ret = 0;
+ } else if (property == adev->mode_info.underscan_property) {
+ *val = dm_state->underscan_enable;
+ ret = 0;
+ } else if (property == adev->mode_info.freesync_property) {
+ //TODO
+ *val = 0;
+ ret = 0;
+ } else if (property == adev->mode_info.freesync_capable_property) {
+ //TODO
+ *val = 0;
+ ret = 0;
+ }
+ return ret;
+}
+
void amdgpu_dm_connector_destroy(struct drm_connector *connector)
{
struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
@@ -1447,7 +1497,8 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
.destroy = amdgpu_dm_connector_destroy,
.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
- .atomic_set_property = amdgpu_dm_connector_atomic_set_property
+ .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
+ .atomic_get_property = amdgpu_dm_connector_atomic_get_property
};
static struct drm_encoder *best_encoder(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index ab6d51dbbf4b..b69c86826b1a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -71,6 +71,12 @@ int amdgpu_dm_connector_atomic_set_property(
struct drm_property *property,
uint64_t val);
+int amdgpu_dm_connector_atomic_get_property(
+ struct drm_connector *connector,
+ const struct drm_connector_state *state,
+ struct drm_property *property,
+ uint64_t *val);
+
int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
void amdgpu_dm_connector_init_helper(
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
end of thread, other threads:[~2017-04-25 18:39 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-25 18:38 [PATCH 00/24] DC Linux Patches Apr 25, 2017 Harry Wentland
[not found] ` <20170425183913.16759-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2017-04-25 18:38 ` [PATCH 01/24] drm/amd/display: adding FCLK and DPPCLK clock types Harry Wentland
2017-04-25 18:38 ` [PATCH 02/24] drm/amd/display: Fix hotspot programming during set cursor position Harry Wentland
2017-04-25 18:38 ` [PATCH 03/24] drm/amd/display: Memory was freed twice during disable Harry Wentland
2017-04-25 18:38 ` [PATCH 04/24] drm/amd/display: Adding dm controlled signal type in dc_stream Harry Wentland
2017-04-25 18:38 ` [PATCH 05/24] drm/amd/display: Add same check as reset pipes for programing backend regs Harry Wentland
2017-04-25 18:38 ` [PATCH 06/24] drm/amd/display: change mpo surface update check condition Harry Wentland
2017-04-25 18:38 ` [PATCH 07/24] drm/amd/display: set NULL value during removal for remoteSink Harry Wentland
2017-04-25 18:38 ` [PATCH 08/24] drm/amd/display: Fix for tile MST Harry Wentland
2017-04-25 18:38 ` [PATCH 09/24] drm/amd/display: Allow planes on all crtcs Harry Wentland
2017-04-25 18:38 ` [PATCH 10/24] drm/amd/display: Fix missing irq refactor causing potential i2c race Harry Wentland
2017-04-25 18:39 ` [PATCH 11/24] drm/amd/display: use full surface update when stream is NULL Harry Wentland
2017-04-25 18:39 ` [PATCH 12/24] drm/amd/display: Parse scanline registers Harry Wentland
2017-04-25 18:39 ` [PATCH 13/24] drm/amd/display: Add support for programming stereo sync Harry Wentland
2017-04-25 18:39 ` [PATCH 14/24] drm/amd/display: FreeSync LFC MIN/MAX update on current frame Harry Wentland
2017-04-25 18:39 ` [PATCH 15/24] drm/amd/display: Remove unused scratch_val_ctx Harry Wentland
2017-04-25 18:39 ` [PATCH 16/24] drm/amd/display: Get rid of temp_flip_context Harry Wentland
2017-04-25 18:39 ` [PATCH 17/24] drm/amd/display: update dce8 & 10 bw programming Harry Wentland
2017-04-25 18:39 ` [PATCH 18/24] drm/amd/display: Add lock around updating freesync property Harry Wentland
2017-04-25 18:39 ` [PATCH 19/24] drm/amd/display: pull commit_surfaces out of atomic_commit into helper function Harry Wentland
2017-04-25 18:39 ` [PATCH 20/24] drm/amd/display: Copy ctx to current_context instead of assign Harry Wentland
2017-04-25 18:39 ` [PATCH 21/24] drm/amd/display: Move resource_validate_ctx_destruct to dc.h Harry Wentland
2017-04-25 18:39 ` [PATCH 22/24] drm/amd/display: Return context from validate_context Harry Wentland
2017-04-25 18:39 ` [PATCH 23/24] drm/amd/display: initialize YUV plane capabilities Harry Wentland
2017-04-25 18:39 ` [PATCH 24/24] drm/amd/display: get_atomic_property missing for drm_connector_funcs Harry Wentland
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