Re: [PATCH 1/2] drm/i915: Pre-calculate engine context size

[Chris Wilson <chris@chris-wilson.co.uk>]

On Wed, Apr 26, 2017 at 12:11:53PM +0300, Joonas Lahtinen wrote:
> Pre-calculate engine context size based on engine class and device
> generation and store it in the engine instance.
> 
> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: intel-gvt-dev@lists.freedesktop.org
> ---
>  drivers/gpu/drm/i915/gvt/scheduler.c       |  6 ++--
>  drivers/gpu/drm/i915/i915_guc_submission.c |  3 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c     | 46 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_lrc.c           | 54 +-----------------------------
>  drivers/gpu/drm/i915/intel_lrc.h           |  2 --
>  drivers/gpu/drm/i915/intel_ringbuffer.h    |  5 +--
>  6 files changed, 53 insertions(+), 63 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index a77db23..ac538dc 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -69,8 +69,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
>  	gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
>  			workload->ctx_desc.lrca);
>  
> -	context_page_num = intel_lr_context_size(
> -			gvt->dev_priv->engine[ring_id]);
> +	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
>  
>  	context_page_num = context_page_num >> PAGE_SHIFT;
>  
> @@ -333,8 +332,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
>  	gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
>  			workload->ctx_desc.lrca);
>  
> -	context_page_num = intel_lr_context_size(
> -			gvt->dev_priv->engine[ring_id]);
> +	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
>  
>  	context_page_num = context_page_num >> PAGE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index ab5140b..6c78637 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1051,8 +1051,7 @@ static int guc_ads_create(struct intel_guc *guc)
>  		dev_priv->engine[RCS]->status_page.ggtt_offset;
>  
>  	for_each_engine(engine, dev_priv, id)
> -		blob->ads.eng_state_size[engine->guc_id] =
> -			intel_lr_context_size(engine);
> +		blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
>  
>  	base = guc_ggtt_offset(vma);
>  	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 82a274b..091c0c7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,6 +26,10 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> +#define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
> +#define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
> +#define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
> +
>  struct engine_class_info {
>  	const char *name;
>  	int (*init_legacy)(struct intel_engine_cs *engine);
> @@ -107,6 +111,46 @@ static const struct engine_info intel_engines[] = {
>  	},
>  };
>  
> +/**
> + * ___intel_engine_context_size() - return the size of the context for an engine
> + * @dev_priv: i915 device private
> + * @class: engine class
> + *
> + * Each engine class may require a different amount of space for a context
> + * image.
> + *
> + * Return: size (in bytes) of an engine class specific context image
> + *
> + * Note: this size includes the HWSP, which is part of the context image
> + * in LRC mode, but does not include the "shared data page" used with
> + * GuC submission. The caller should account for this if using the GuC.
> + */
> +static u32
> +__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
> +{
> +	WARN_ON(INTEL_GEN(dev_priv) < 8);
> +
> +	switch (class) {
> +	case RENDER_CLASS:
> +		switch (INTEL_GEN(dev_priv)) {
> +		default:
> +			MISSING_CASE(INTEL_GEN(dev_priv));
> +		case 9:
> +			return GEN9_LR_CONTEXT_RENDER_SIZE;
> +		case 8:
> +			return GEN8_LR_CONTEXT_RENDER_SIZE;
> +		}
> +		break;
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +	case COPY_ENGINE_CLASS:
> +		return GEN8_LR_CONTEXT_OTHER_SIZE;
> +	}
> +
> +	MISSING_CASE(class);
> +	return GEN8_LR_CONTEXT_OTHER_SIZE;
> +}
> +
>  static int
>  intel_engine_setup(struct drm_i915_private *dev_priv,
>  		   enum intel_engine_id id)
> @@ -134,6 +178,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
>  	engine->irq_shift = info->irq_shift;
>  	engine->class = info->class;
>  	engine->instance = info->instance;
> +	engine->context_size = __intel_engine_context_size(dev_priv,
> +							   engine->class);

Isn't intel_engine_setup() common for all gen?

Hmm, I would like to dev_priv->hw_context_size just die, and be able to
use dev_priv->engine[RCS]->context_size instead. That makes
contexts_enabled() much simpler, for example, and kills yet another
i915.enable_execlists. But does make __create_hw_context() a bit more
ugly until we do deferred allocation for legacy as well (the framework
is in place!)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx