[U-Boot] [PATCH 0/3] arm: am33xx: Add support for dynamic programming of PLL

[U-Boot] [PATCH 0/3] arm: am33xx: Add support for dynamic programming of PLL

[Lokesh Vutla]

As am33xx supports various sysclk frequencies, this series support
PLL configuration for all supported sysclk frequencies.

Lokesh Vutla (3):
  arm: am33xx: Fix MPU opp selection
  board: am335x: Introduce scale_vcores
  arm: am33xx: Add support for mulitiple PLL input frequencies

 arch/arm/include/asm/arch-am33xx/clock.h           |   7 +
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |   6 +-
 arch/arm/include/asm/arch-am33xx/cpu.h             |   8 +
 arch/arm/include/asm/arch-am33xx/hardware.h        |  13 +
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |  13 -
 arch/arm/include/asm/arch-am33xx/sys_proto.h       |   1 +
 arch/arm/mach-omap2/am33xx/board.c                 |   2 -
 arch/arm/mach-omap2/am33xx/clock_am33xx.c          |  93 +++++-
 arch/arm/mach-omap2/am33xx/sys_info.c              |  51 +++-
 board/ti/am335x/board.c                            | 313 ++++++++++++---------
 board/ti/am43xx/board.c                            |  21 --
 include/power/tps65910.h                           |   1 +
 12 files changed, 341 insertions(+), 188 deletions(-)

-- 
2.11.0

[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Lokesh Vutla]

Update MPU frequencies and voltages as per the latest
DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
Below is the consolidated data:

MPU values for PG 2.0 and later(Package ZCZ and ZCE):

 -------------------------------------------------------
|	|	  ZCZ		|	  ZCE		|
|-------------------------------------------------------|
|	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
|-------|----------|------------|----------|------------|
| NITRO |  1.325   |   1000     |   NA     |    NA      |
|-------|----------|------------|----------|------------|
| TURBO |   1.26   |    800	|   NA     |    NA      |
|-------|----------|------------|----------|------------|
|OPP120 |   1.20   |    720     |   NA     |    NA      |
|-------|----------|------------|----------|------------|
|OPP100 |   1.10   |    600     |   1.10   |    600     |
|-------|----------|------------|----------|------------|
| OPP50 |   0.95   |    300     |   0.95   |    300     |
 -------------------------------------------------------

There is no eFuse blown on PG1.0 Silicons due to which there is
no way to detect the maximum frequencies supported. So default
to OPP100 for which both frequency and voltages are common on both
the packages.

[1] http://www.ti.com/lit/ds/symlink/am3356.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |  4 +--
 arch/arm/include/asm/arch-am33xx/cpu.h           |  8 ++++++
 arch/arm/mach-omap2/am33xx/sys_info.c            | 33 +++++++++++++++---------
 include/power/tps65910.h                         |  1 +
 4 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 4c9352a2ed..5f11c72323 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -16,12 +16,12 @@
 #define MPUPLL_M_800	800
 #define MPUPLL_M_720	720
 #define MPUPLL_M_600	600
-#define MPUPLL_M_550	550
+#define MPUPLL_M_500	500
 #define MPUPLL_M_300	300
 
 /* MAIN PLL Fdll = 550 MHz, by default */
 #ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
+#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
 #endif
 
 #define UART_RESET		(0x1 << 1)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 54f449f6e6..8cae291ea0 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -49,6 +49,14 @@
 #define TI81XX				0xB81E
 #define DEVICE_ID			(CTRL_BASE + 0x0600)
 #define DEVICE_ID_MASK			0x1FFF
+#define PACKAGE_TYPE_SHIFT		16
+#define PACKAGE_TYPE_MASK		(3 << 16)
+
+/* Package Type */
+#define PACKAGE_TYPE_UNDEFINED		0x0
+#define PACKAGE_TYPE_ZCZ		0x1
+#define PACKAGE_TYPE_ZCE		0x2
+#define PACKAGE_TYPE_RESERVED		0x3
 
 /* MPU max frequencies */
 #define AM335X_ZCZ_300			0x1FEF
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index e4fc461bd8..c2df5b3ec5 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 
 	sil_rev = readl(&cdev->deviceid) >> 28;
 
-	if (sil_rev == 1)
-		/* PG 2.0, efuse may not be set. */
-		return MPUPLL_M_800;
-	else if (sil_rev >= 2) {
+	if (sil_rev == 0) {
+		/* No efuse in PG 1.0. So use OPP100 */
+		return MPUPLL_M_500;
+	} else if (sil_rev >= 1) {
 		/* Check what the efuse says our max speed is. */
-		int efuse_arm_mpu_max_freq;
+		int efuse_arm_mpu_max_freq, package_type;
 		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
+				PACKAGE_TYPE_SHIFT;
+
+		/* PG 2.0, efuse may not be set. */
+		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
+		    PACKAGE_TYPE_RESERVED)
+			return MPUPLL_M_800;
+
 		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
 		case AM335X_ZCZ_1000:
 			return MPUPLL_M_1000;
@@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 		}
 	}
 
-	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
-	return MPUPLL_M_720;
+	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
+	return MPUPLL_M_500;
 }
 
 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 {
-	/* For PG2.1 and later, we have one set of values. */
-	if (sil_rev >= 2) {
+	/* For PG2.0 and later, we have one set of values. */
+	if (sil_rev >= 1) {
 		switch (frequency) {
 		case MPUPLL_M_1000:
 			return TPS65910_OP_REG_SEL_1_3_2_5;
@@ -171,12 +179,13 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 		case MPUPLL_M_720:
 			return TPS65910_OP_REG_SEL_1_2_0;
 		case MPUPLL_M_600:
+		case MPUPLL_M_500:
 		case MPUPLL_M_300:
-			return TPS65910_OP_REG_SEL_1_1_3;
+			return TPS65910_OP_REG_SEL_1_1_0;
 		}
 	}
 
-	/* Default to PG1.0/PG2.0 values. */
-	return TPS65910_OP_REG_SEL_1_1_3;
+	/* Default to PG1.0 values. */
+	return TPS65910_OP_REG_SEL_1_1_0;
 }
 #endif
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
index ca8430145b..976130dc3e 100644
--- a/include/power/tps65910.h
+++ b/include/power/tps65910.h
@@ -62,6 +62,7 @@ enum {
 
 #define TPS65910_OP_REG_SEL_MASK			(0x7F)
 #define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
 #define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
 #define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
 #define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
-- 
2.11.0

[U-Boot] [PATCH 2/3] board: am335x: Introduce scale_vcores

[Lokesh Vutla]

Update voltages before programming plls.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 board/ti/am335x/board.c | 267 +++++++++++++++++++++++++++---------------------
 1 file changed, 148 insertions(+), 119 deletions(-)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 6786229680..c6e20b0499 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -264,155 +264,184 @@ const struct dpll_params dpll_ddr_evm_sk = {
 const struct dpll_params dpll_ddr_bone_black = {
 		400, OSC-1, 1, -1, -1, -1, -1};
 
-void am33xx_spl_board_init(void)
+const struct dpll_params *get_dpll_ddr_params(void)
 {
-	int mpu_vdd;
+	if (board_is_evm_sk())
+		return &dpll_ddr_evm_sk;
+	else if (board_is_bone_lt() || board_is_icev2())
+		return &dpll_ddr_bone_black;
+	else if (board_is_evm_15_or_later())
+		return &dpll_ddr_evm_sk;
+	else
+		return &dpll_ddr;
+}
 
-	/* Get the frequency */
-	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+static void scale_vcores_bone(int freq)
+{
+	int usb_cur_lim, mpu_vdd;
 
-	if (board_is_bone() || board_is_bone_lt()) {
-		/* BeagleBone PMIC Code */
-		int usb_cur_lim;
+	/*
+	 * Only perform PMIC configurations if board rev > A1
+	 * on Beaglebone White
+	 */
+	if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
+		return;
 
-		/*
-		 * Only perform PMIC configurations if board rev > A1
-		 * on Beaglebone White
-		 */
-		if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
-			return;
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
 
-		if (i2c_probe(TPS65217_CHIP_PM))
+	/*
+	 * On Beaglebone White we need to ensure we have AC power
+	 * before increasing the frequency.
+	 */
+	if (board_is_bone()) {
+		uchar pmic_status_reg;
+		if (tps65217_reg_read(TPS65217_STATUS,
+				      &pmic_status_reg))
 			return;
-
-		/*
-		 * On Beaglebone White we need to ensure we have AC power
-		 * before increasing the frequency.
-		 */
-		if (board_is_bone()) {
-			uchar pmic_status_reg;
-			if (tps65217_reg_read(TPS65217_STATUS,
-					      &pmic_status_reg))
-				return;
-			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
-				puts("No AC power, disabling frequency switch\n");
-				return;
-			}
+		if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+			puts("No AC power, switching to default OPP\n");
+			freq = MPUPLL_M_600;
 		}
+	}
 
-		/*
-		 * Override what we have detected since we know if we have
-		 * a Beaglebone Black it supports 1GHz.
-		 */
-		if (board_is_bone_lt())
-			dpll_mpu_opp100.m = MPUPLL_M_1000;
-
-		/*
-		 * Increase USB current limit to 1300mA or 1800mA and set
-		 * the MPU voltage controller as needed.
-		 */
-		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
-		} else {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
-		}
+	/*
+	 * Override what we have detected since we know if we have
+	 * a Beaglebone Black it supports 1GHz.
+	 */
+	if (board_is_bone_lt())
+		freq = MPUPLL_M_1000;
 
-		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
-				       TPS65217_POWER_PATH,
-				       usb_cur_lim,
-				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
-			puts("tps65217_reg_write failure\n");
+	if (freq == MPUPLL_M_1000) {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+	} else {
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+	}
 
-		/* Set DCDC3 (CORE) voltage to 1.125V */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
-					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
+	switch (freq) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		break;
+	case MPUPLL_M_600:
+	case MPUPLL_M_500:
+	case MPUPLL_M_300:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	}
 
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
 
-		/* Set DCDC2 (MPU) voltage */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
+	/* Set DCDC3 (CORE) voltage to 1.10V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1100MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
 
-		/*
-		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
-		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
-		 */
-		if (board_is_bone()) {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_3_3,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		} else {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_1_8,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		}
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
 
+	/*
+	 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+	 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+	 */
+	if (board_is_bone()) {
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-				       TPS65217_DEFLS2,
+				       TPS65217_DEFLS1,
 				       TPS65217_LDO_VOLTAGE_OUT_3_3,
 				       TPS65217_LDO_MASK))
 			puts("tps65217_reg_write failure\n");
 	} else {
-		int sil_rev;
+		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+				       TPS65217_DEFLS1,
+				       TPS65217_LDO_VOLTAGE_OUT_1_8,
+				       TPS65217_LDO_MASK))
+			puts("tps65217_reg_write failure\n");
+	}
 
-		/*
-		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
-		 * MPU frequencies we support we use a CORE voltage of
-		 * 1.1375V.  For MPU voltage we need to switch based on
-		 * the frequency we are running at.
-		 */
-		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
-			return;
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+}
 
-		/*
-		 * Depending on MPU clock and PG we will need a different
-		 * VDD to drive at that speed.
-		 */
-		sil_rev = readl(&cdev->deviceid) >> 28;
-		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
-						      dpll_mpu_opp100.m);
+void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
 
-		/* Tell the TPS65910 to use i2c */
-		tps65910_set_i2c_control();
+	/*
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * MPU frequencies we support we use a CORE voltage of
+	 * 1.10V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+		return;
 
-		/* First update MPU voltage. */
-		if (tps65910_voltage_update(MPU, mpu_vdd))
-			return;
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 
-		/* Second, update the CORE voltage. */
-		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
-			return;
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
 
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-	}
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
 
-	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
-const struct dpll_params *get_dpll_ddr_params(void)
+void gpi2c_init(void)
 {
-	if (board_is_evm_sk())
-		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt() || board_is_icev2())
-		return &dpll_ddr_bone_black;
-	else if (board_is_evm_15_or_later())
-		return &dpll_ddr_evm_sk;
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+		first_time = false;
+	}
+}
+
+void scale_vcores(void)
+{
+	int freq;;
+
+	gpi2c_init();
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (board_is_bone())
+		scale_vcores_bone(freq);
 	else
-		return &dpll_ddr;
+		scale_vcores_generic(freq);
 }
 
 void set_uart_mux_conf(void)
-- 
2.11.0

[U-Boot] [PATCH 3/3] arm: am33xx: Add support for mulitiple PLL input frequencies

[Lokesh Vutla]

am335x supports various sysclk frequencies which can be determined
using sysboot pins. PLLs should be configures based on this
sysclk frequency. Add PLL configurations for all supported
frequencies.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/clock.h           |  7 ++
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |  2 +
 arch/arm/include/asm/arch-am33xx/hardware.h        | 13 +++
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 13 ---
 arch/arm/include/asm/arch-am33xx/sys_proto.h       |  1 +
 arch/arm/mach-omap2/am33xx/board.c                 |  2 -
 arch/arm/mach-omap2/am33xx/clock_am33xx.c          | 93 +++++++++++++++++++---
 arch/arm/mach-omap2/am33xx/sys_info.c              | 18 +++++
 board/ti/am335x/board.c                            | 74 ++++++++++++-----
 board/ti/am43xx/board.c                            | 21 -----
 10 files changed, 175 insertions(+), 69 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index acf3fd55a8..19ccf5c8db 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -12,6 +12,7 @@
 #define _CLOCKS_H_
 
 #include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/hardware.h>
 
 #ifdef CONFIG_TI81XX
 #include <asm/arch/clock_ti81xx.h>
@@ -103,6 +104,12 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
+extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
 
 extern struct cm_wkuppll *const cmwkup;
 
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 5f11c72323..abbd5adfdc 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -31,6 +31,8 @@
 #define CM_DLL_CTRL_NO_OVERRIDE	0x0
 #define CM_DLL_READYST		0x4
 
+#define NUM_OPPS	6
+
 extern void enable_dmm_clocks(void);
 extern const struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index dd950e5ac4..3437e6116d 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,5 +61,18 @@
 /* CPSW Config space */
 #define CPSW_BASE			0x4A100000
 
+/* Control status register */
+#define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
+#define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
+#define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
+#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
+#define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
+#define CTRL_SYSBOOT_15_14_SHIFT		22
+
+#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
+#define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
+
+#define NUM_CRYSTAL_FREQ			0x4
+
 int clk_get(int clk);
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index a7da6b5cfd..af69ac6f2c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -85,19 +85,6 @@
 #define	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960	(1 << 8)
 #define	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
 
-/* Control status register */
-#define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
-#define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
-#define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
-#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
-#define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
-#define CTRL_SYSBOOT_15_14_SHIFT		22
-
-#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
-#define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
-
-#define NUM_CRYSTAL_FREQ			0x4
-
 /* EDMA3 Base Address */
 #define EDMA3_BASE				0x49000000
 
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 903398fe8f..4e78aafb0b 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -46,3 +46,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
 void enable_usb_clocks(int index);
 void disable_usb_clocks(int index);
 void do_board_detect(void);
+u32 get_sys_clk_index(void);
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 956fcc8b95..f674ab029c 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -243,8 +243,6 @@ int board_early_init_f(void)
  */
 __weak void am33xx_spl_board_init(void)
 {
-	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index 7b841b2d55..b246247916 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
@@ -55,26 +56,96 @@ struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_core_opp100 = {
 		1000, OSC-1, -1, -1, 10, 8, 4};
-const struct dpll_params dpll_mpu = {
-		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-		50, OSC-1, -1, -1, 1, 1, 1};
-const struct dpll_params dpll_per = {
-		960, OSC-1, 5, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_mpu_params(void)
+
+const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+	{	/* 19.2 MHz */
+		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
+		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 24 MHz */
+		{25, 0, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{25, 0, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{30, 0, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{100, 3, 1, -1, -1, -1, -1},	/* OPP TB */
+		{125, 2, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 25 MHz */
+		{24, 0, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{24, 0, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{144, 4, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{32, 0, 1, -1, -1, -1, -1},	/* OPP TB */
+		{40, 0, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+	{	/* 26 MHz */
+		{300, 12, 2, -1, -1, -1, -1},	/* OPP 50 */
+		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
+		{300, 12, 1, -1, -1, -1, -1},	/* OPP 100 */
+		{360, 12, 1, -1, -1, -1, -1},	/* OPP 120 */
+		{400, 12, 1, -1, -1, -1, -1},	/* OPP TB */
+		{500, 12, 1, -1, -1, -1, -1}	/* OPP NT */
+	},
+};
+
+const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
+		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
+		{125, 2, -1, -1, 10, 8, 4},	/* 24 MHz */
+		{40, 0, -1, -1, 10, 8, 4},	/* 25 MHz */
+		{500, 12, -1, -1, 10, 8, 4}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
+		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
+		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
+		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
+};
+
+const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
+		{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
+		{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
+		{303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{303, 12, 2, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
+		{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
+		{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
+		{16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{200, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
+		{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
+		{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
+		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
+		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
+};
+
+__weak const struct dpll_params *get_dpll_mpu_params(void)
 {
-	return &dpll_mpu;
+	int ind = get_sys_clk_index();
+
+	return &dpll_mpu_opp[ind][2];
 }
 
 const struct dpll_params *get_dpll_core_params(void)
 {
-	return &dpll_core;
+	int ind = get_sys_clk_index();
+
+	return &dpll_core_1000MHz[ind];
 }
 
 const struct dpll_params *get_dpll_per_params(void)
 {
-	return &dpll_per;
+	int ind = get_sys_clk_index();
+
+	return &dpll_per_192MHz[ind];
 }
 
 void setup_clocks_for_console(void)
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index c2df5b3ec5..a7f985ee17 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -68,6 +68,24 @@ u32 get_sysboot_value(void)
 	return readl(&cstat->statusreg) & SYSBOOT_MASK;
 }
 
+u32 get_sys_clk_index(void)
+{
+	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+	u32 ind = readl(&ctrl->statusreg);
+
+#ifdef CONFIG_AM43XX
+	u32 src;
+	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+	else /* Value read from SYS BOOT pins */
+#endif
+		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+			CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+
 #ifdef CONFIG_DISPLAY_CPUINFO
 static char *cpu_revs[] = {
 		"1.0",
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index c6e20b0499..0f2e22c5eb 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -256,24 +256,62 @@ int spl_start_uboot(void)
 }
 #endif
 
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
-		303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
-		400, OSC-1, 1, -1, -1, -1, -1};
-
 const struct dpll_params *get_dpll_ddr_params(void)
 {
+	int ind = get_sys_clk_index();
+
 	if (board_is_evm_sk())
-		return &dpll_ddr_evm_sk;
+		return &dpll_ddr3_303MHz[ind];
 	else if (board_is_bone_lt() || board_is_icev2())
-		return &dpll_ddr_bone_black;
+		return &dpll_ddr3_400MHz[ind];
 	else if (board_is_evm_15_or_later())
-		return &dpll_ddr_evm_sk;
+		return &dpll_ddr3_303MHz[ind];
 	else
-		return &dpll_ddr;
+		return &dpll_ddr2_266MHz[ind];
+}
+
+u8 bone_not_connected_to_ac_power(void)
+{
+	if (board_is_bone()) {
+		uchar pmic_status_reg;
+		if (tps65217_reg_read(TPS65217_STATUS,
+				      &pmic_status_reg))
+			return 1;
+		if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+			puts("No AC power, switching to default OPP\n");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
+
+	if (board_is_bone_lt())
+		freq = MPUPLL_M_1000;
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
 }
 
 static void scale_vcores_bone(int freq)
@@ -294,16 +332,8 @@ static void scale_vcores_bone(int freq)
 	 * On Beaglebone White we need to ensure we have AC power
 	 * before increasing the frequency.
 	 */
-	if (board_is_bone()) {
-		uchar pmic_status_reg;
-		if (tps65217_reg_read(TPS65217_STATUS,
-				      &pmic_status_reg))
-			return;
-		if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
-			puts("No AC power, switching to default OPP\n");
-			freq = MPUPLL_M_600;
-		}
-	}
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
 
 	/*
 	 * Override what we have detected since we know if we have
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 390cc168cd..299a72ad72 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -49,8 +49,6 @@ void do_board_detect(void)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 
-#define NUM_OPPS	6
-
 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
 	{	/* 19.2 MHz */
 		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
@@ -317,25 +315,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 	return;
 }
 
-/*
- * get_sys_clk_index : returns the index of the sys_clk read from
- *			ctrl status register. This value is either
- *			read from efuse or sysboot pins.
- */
-static u32 get_sys_clk_index(void)
-{
-	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
-	u32 ind = readl(&ctrl->statusreg), src;
-
-	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
-	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
-		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
-			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
-	else /* Value read from SYS BOOT pins */
-		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
-			CTRL_SYSBOOT_15_14_SHIFT);
-}
-
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	int ind = get_sys_clk_index();
-- 
2.11.0

[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Tom Rini]

On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
> Update MPU frequencies and voltages as per the latest
> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
> Below is the consolidated data:
> 
> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
> 
>  -------------------------------------------------------
> |	|	  ZCZ		|	  ZCE		|
> |-------------------------------------------------------|
> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
> |-------|----------|------------|----------|------------|
> | NITRO |  1.325   |   1000     |   NA     |    NA      |
> |-------|----------|------------|----------|------------|
> | TURBO |   1.26   |    800	|   NA     |    NA      |
> |-------|----------|------------|----------|------------|
> |OPP120 |   1.20   |    720     |   NA     |    NA      |
> |-------|----------|------------|----------|------------|
> |OPP100 |   1.10   |    600     |   1.10   |    600     |
> |-------|----------|------------|----------|------------|
> | OPP50 |   0.95   |    300     |   0.95   |    300     |
>  -------------------------------------------------------
> 
> There is no eFuse blown on PG1.0 Silicons due to which there is
> no way to detect the maximum frequencies supported. So default
> to OPP100 for which both frequency and voltages are common on both
> the packages.

You say OPP100 here, but the code (and table) is for OPP50.  Which means
a good bit of a speed cut.

[snip]
>  /* MAIN PLL Fdll = 550 MHz, by default */
>  #ifndef CONFIG_SYS_MPUCLK
> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
>  #endif

Update the comment please.  Better yet, Kconfig migration (as this is
only an am33xx thing).

[snip]
> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>  
>  	sil_rev = readl(&cdev->deviceid) >> 28;
>  
> -	if (sil_rev == 1)
> -		/* PG 2.0, efuse may not be set. */
> -		return MPUPLL_M_800;
> -	else if (sil_rev >= 2) {
> +	if (sil_rev == 0) {
> +		/* No efuse in PG 1.0. So use OPP100 */
> +		return MPUPLL_M_500;

Isn't that OPP50?

> +	} else if (sil_rev >= 1) {
>  		/* Check what the efuse says our max speed is. */
> -		int efuse_arm_mpu_max_freq;
> +		int efuse_arm_mpu_max_freq, package_type;
>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
> +				PACKAGE_TYPE_SHIFT;
> +
> +		/* PG 2.0, efuse may not be set. */
> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
> +		    PACKAGE_TYPE_RESERVED)
> +			return MPUPLL_M_800;
> +
>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
>  		case AM335X_ZCZ_1000:
>  			return MPUPLL_M_1000;
> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>  		}
>  	}
>  
> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
> -	return MPUPLL_M_720;
> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
> +	return MPUPLL_M_500;

Is the problem here new PG values getting unsafe values?  I'm concerned
about slowing down PG1.0 stuff which is also in the wild, in numbers.

-- 
Tom
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[U-Boot] [PATCH 2/3] board: am335x: Introduce scale_vcores

[Tom Rini]

On Tue, May 02, 2017 at 07:40:25PM +0530, Lokesh Vutla wrote:

> Update voltages before programming plls.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 3/3] arm: am33xx: Add support for mulitiple PLL input frequencies

[Tom Rini]

On Tue, May 02, 2017 at 07:40:26PM +0530, Lokesh Vutla wrote:

> am335x supports various sysclk frequencies which can be determined
> using sysboot pins. PLLs should be configures based on this
> sysclk frequency. Add PLL configurations for all supported
> frequencies.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[snip]
> +u8 bone_not_connected_to_ac_power(void)
> +{

Should be static.  Thanks!

-- 
Tom
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[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Lokesh Vutla]

On Wednesday 03 May 2017 06:03 PM, Tom Rini wrote:
> On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
>> Update MPU frequencies and voltages as per the latest
>> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
>> Below is the consolidated data:
>>
>> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
>>
>>  -------------------------------------------------------
>> |	|	  ZCZ		|	  ZCE		|
>> |-------------------------------------------------------|
>> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
>> |-------|----------|------------|----------|------------|
>> | NITRO |  1.325   |   1000     |   NA     |    NA      |
>> |-------|----------|------------|----------|------------|
>> | TURBO |   1.26   |    800	|   NA     |    NA      |
>> |-------|----------|------------|----------|------------|
>> |OPP120 |   1.20   |    720     |   NA     |    NA      |
>> |-------|----------|------------|----------|------------|
>> |OPP100 |   1.10   |    600     |   1.10   |    600     |
>> |-------|----------|------------|----------|------------|
>> | OPP50 |   0.95   |    300     |   0.95   |    300     |
>>  -------------------------------------------------------
>>
>> There is no eFuse blown on PG1.0 Silicons due to which there is
>> no way to detect the maximum frequencies supported. So default
>> to OPP100 for which both frequency and voltages are common on both
>> the packages.
> 
> You say OPP100 here, but the code (and table) is for OPP50.  Which means
> a good bit of a speed cut.

The above table is for PG2.0 and later versions. For PG1.0 ARM runs at
500MHz in OPP100. Refer Table 5.3 and Table 5.5 in
DM(http://www.ti.com/lit/ds/symlink/am3356.pdf)

> 
> [snip]
>>  /* MAIN PLL Fdll = 550 MHz, by default */
>>  #ifndef CONFIG_SYS_MPUCLK
>> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
>> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
>>  #endif
> 
> Update the comment please.  Better yet, Kconfig migration (as this is
> only an am33xx thing).

Hmm.. The above value is used only for PG1.0 silicons and the value is
fixed per SoC. Do we need a Kconfig symbol for that?

> 
> [snip]
>> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>  
>>  	sil_rev = readl(&cdev->deviceid) >> 28;
>>  
>> -	if (sil_rev == 1)
>> -		/* PG 2.0, efuse may not be set. */
>> -		return MPUPLL_M_800;
>> -	else if (sil_rev >= 2) {
>> +	if (sil_rev == 0) {
>> +		/* No efuse in PG 1.0. So use OPP100 */
>> +		return MPUPLL_M_500;
> 
> Isn't that OPP50?
> 
>> +	} else if (sil_rev >= 1) {
>>  		/* Check what the efuse says our max speed is. */
>> -		int efuse_arm_mpu_max_freq;
>> +		int efuse_arm_mpu_max_freq, package_type;
>>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
>> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
>> +				PACKAGE_TYPE_SHIFT;
>> +
>> +		/* PG 2.0, efuse may not be set. */
>> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
>> +		    PACKAGE_TYPE_RESERVED)
>> +			return MPUPLL_M_800;
>> +
>>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
>>  		case AM335X_ZCZ_1000:
>>  			return MPUPLL_M_1000;
>> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>  		}
>>  	}
>>  
>> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
>> -	return MPUPLL_M_720;
>> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
>> +	return MPUPLL_M_500;
> 
> Is the problem here new PG values getting unsafe values?  I'm concerned
> about slowing down PG1.0 stuff which is also in the wild, in numbers.
> 

No, I just wanted to return a value as it is a non-void function, may be
I should update the comment properly.

Thanks and regards,
Lokesh

[U-Boot] [PATCH 3/3] arm: am33xx: Add support for mulitiple PLL input frequencies

[Lokesh Vutla]

On Wednesday 03 May 2017 06:09 PM, Tom Rini wrote:
> On Tue, May 02, 2017 at 07:40:26PM +0530, Lokesh Vutla wrote:
> 
>> am335x supports various sysclk frequencies which can be determined
>> using sysboot pins. PLLs should be configures based on this
>> sysclk frequency. Add PLL configurations for all supported
>> frequencies.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> [snip]
>> +u8 bone_not_connected_to_ac_power(void)
>> +{
> 
> Should be static.  Thanks!

Sure. will update it and repost.

Thanks and regards,
Lokesh

> 

[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Tom Rini]

On Wed, May 03, 2017 at 07:36:32PM +0530, Lokesh Vutla wrote:
> 
> 
> On Wednesday 03 May 2017 06:03 PM, Tom Rini wrote:
> > On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
> >> Update MPU frequencies and voltages as per the latest
> >> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
> >> Below is the consolidated data:
> >>
> >> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
> >>
> >>  -------------------------------------------------------
> >> |	|	  ZCZ		|	  ZCE		|
> >> |-------------------------------------------------------|
> >> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
> >> |-------|----------|------------|----------|------------|
> >> | NITRO |  1.325   |   1000     |   NA     |    NA      |
> >> |-------|----------|------------|----------|------------|
> >> | TURBO |   1.26   |    800	|   NA     |    NA      |
> >> |-------|----------|------------|----------|------------|
> >> |OPP120 |   1.20   |    720     |   NA     |    NA      |
> >> |-------|----------|------------|----------|------------|
> >> |OPP100 |   1.10   |    600     |   1.10   |    600     |
> >> |-------|----------|------------|----------|------------|
> >> | OPP50 |   0.95   |    300     |   0.95   |    300     |
> >>  -------------------------------------------------------
> >>
> >> There is no eFuse blown on PG1.0 Silicons due to which there is
> >> no way to detect the maximum frequencies supported. So default
> >> to OPP100 for which both frequency and voltages are common on both
> >> the packages.
> > 
> > You say OPP100 here, but the code (and table) is for OPP50.  Which means
> > a good bit of a speed cut.
> 
> The above table is for PG2.0 and later versions. For PG1.0 ARM runs at
> 500MHz in OPP100. Refer Table 5.3 and Table 5.5 in
> DM(http://www.ti.com/lit/ds/symlink/am3356.pdf)
> 
> > 
> > [snip]
> >>  /* MAIN PLL Fdll = 550 MHz, by default */
> >>  #ifndef CONFIG_SYS_MPUCLK
> >> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
> >> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
> >>  #endif
> > 
> > Update the comment please.  Better yet, Kconfig migration (as this is
> > only an am33xx thing).
> 
> Hmm.. The above value is used only for PG1.0 silicons and the value is
> fixed per SoC. Do we need a Kconfig symbol for that?

If you can get rid of it, do so, but please make sure to check on how
the other am335x boards are making use of it (ie the Siemens stuff).

> > [snip]
> >> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
> >>  
> >>  	sil_rev = readl(&cdev->deviceid) >> 28;
> >>  
> >> -	if (sil_rev == 1)
> >> -		/* PG 2.0, efuse may not be set. */
> >> -		return MPUPLL_M_800;
> >> -	else if (sil_rev >= 2) {
> >> +	if (sil_rev == 0) {
> >> +		/* No efuse in PG 1.0. So use OPP100 */
> >> +		return MPUPLL_M_500;
> > 
> > Isn't that OPP50?
> > 
> >> +	} else if (sil_rev >= 1) {
> >>  		/* Check what the efuse says our max speed is. */
> >> -		int efuse_arm_mpu_max_freq;
> >> +		int efuse_arm_mpu_max_freq, package_type;
> >>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
> >> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
> >> +				PACKAGE_TYPE_SHIFT;
> >> +
> >> +		/* PG 2.0, efuse may not be set. */
> >> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
> >> +		    PACKAGE_TYPE_RESERVED)
> >> +			return MPUPLL_M_800;
> >> +
> >>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
> >>  		case AM335X_ZCZ_1000:
> >>  			return MPUPLL_M_1000;
> >> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
> >>  		}
> >>  	}
> >>  
> >> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
> >> -	return MPUPLL_M_720;
> >> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
> >> +	return MPUPLL_M_500;
> > 
> > Is the problem here new PG values getting unsafe values?  I'm concerned
> > about slowing down PG1.0 stuff which is also in the wild, in numbers.
> 
> No, I just wanted to return a value as it is a non-void function, may be
> I should update the comment properly.

My concern is that PG1.0 stuff was previously being clocked at 720MHz,
but now will be down to 500MHz.  I'm not sure if in these cases anything
else (ie Linux) touches this and would be kicking it back up.  It'll
also slow down boot there a bit.  Thanks!

-- 
Tom
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[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Lokesh Vutla]

On Wednesday 03 May 2017 08:53 PM, Tom Rini wrote:
> On Wed, May 03, 2017 at 07:36:32PM +0530, Lokesh Vutla wrote:
>>
>>
>> On Wednesday 03 May 2017 06:03 PM, Tom Rini wrote:
>>> On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
>>>> Update MPU frequencies and voltages as per the latest
>>>> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
>>>> Below is the consolidated data:
>>>>
>>>> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
>>>>
>>>>  -------------------------------------------------------
>>>> |	|	  ZCZ		|	  ZCE		|
>>>> |-------------------------------------------------------|
>>>> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
>>>> |-------|----------|------------|----------|------------|
>>>> | NITRO |  1.325   |   1000     |   NA     |    NA      |
>>>> |-------|----------|------------|----------|------------|
>>>> | TURBO |   1.26   |    800	|   NA     |    NA      |
>>>> |-------|----------|------------|----------|------------|
>>>> |OPP120 |   1.20   |    720     |   NA     |    NA      |
>>>> |-------|----------|------------|----------|------------|
>>>> |OPP100 |   1.10   |    600     |   1.10   |    600     |
>>>> |-------|----------|------------|----------|------------|
>>>> | OPP50 |   0.95   |    300     |   0.95   |    300     |
>>>>  -------------------------------------------------------
>>>>
>>>> There is no eFuse blown on PG1.0 Silicons due to which there is
>>>> no way to detect the maximum frequencies supported. So default
>>>> to OPP100 for which both frequency and voltages are common on both
>>>> the packages.
>>>
>>> You say OPP100 here, but the code (and table) is for OPP50.  Which means
>>> a good bit of a speed cut.
>>
>> The above table is for PG2.0 and later versions. For PG1.0 ARM runs at
>> 500MHz in OPP100. Refer Table 5.3 and Table 5.5 in
>> DM(http://www.ti.com/lit/ds/symlink/am3356.pdf)
>>
>>>
>>> [snip]
>>>>  /* MAIN PLL Fdll = 550 MHz, by default */
>>>>  #ifndef CONFIG_SYS_MPUCLK
>>>> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
>>>> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
>>>>  #endif
>>>
>>> Update the comment please.  Better yet, Kconfig migration (as this is
>>> only an am33xx thing).
>>
>> Hmm.. The above value is used only for PG1.0 silicons and the value is
>> fixed per SoC. Do we need a Kconfig symbol for that?
> 
> If you can get rid of it, do so, but please make sure to check on how
> the other am335x boards are making use of it (ie the Siemens stuff).

okay Ill check it.

> 
>>> [snip]
>>>> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>>>  
>>>>  	sil_rev = readl(&cdev->deviceid) >> 28;
>>>>  
>>>> -	if (sil_rev == 1)
>>>> -		/* PG 2.0, efuse may not be set. */
>>>> -		return MPUPLL_M_800;
>>>> -	else if (sil_rev >= 2) {
>>>> +	if (sil_rev == 0) {
>>>> +		/* No efuse in PG 1.0. So use OPP100 */
>>>> +		return MPUPLL_M_500;
>>>
>>> Isn't that OPP50?
>>>
>>>> +	} else if (sil_rev >= 1) {
>>>>  		/* Check what the efuse says our max speed is. */
>>>> -		int efuse_arm_mpu_max_freq;
>>>> +		int efuse_arm_mpu_max_freq, package_type;
>>>>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
>>>> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
>>>> +				PACKAGE_TYPE_SHIFT;
>>>> +
>>>> +		/* PG 2.0, efuse may not be set. */
>>>> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
>>>> +		    PACKAGE_TYPE_RESERVED)
>>>> +			return MPUPLL_M_800;
>>>> +
>>>>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
>>>>  		case AM335X_ZCZ_1000:
>>>>  			return MPUPLL_M_1000;
>>>> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>>>  		}
>>>>  	}
>>>>  
>>>> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
>>>> -	return MPUPLL_M_720;
>>>> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
>>>> +	return MPUPLL_M_500;
>>>
>>> Is the problem here new PG values getting unsafe values?  I'm concerned
>>> about slowing down PG1.0 stuff which is also in the wild, in numbers.
>>
>> No, I just wanted to return a value as it is a non-void function, may be
>> I should update the comment properly.
> 
> My concern is that PG1.0 stuff was previously being clocked at 720MHz,
> but now will be down to 500MHz.  I'm not sure if in these cases anything
> else (ie Linux) touches this and would be kicking it back up.  It'll
> also slow down boot there a bit.  Thanks!

Till now for PG 1.0 we are clocking at 720MHz(OPP_NITRO for ZCZ package)
and configuring voltages at 1.13V(OPP_100) which is wrong(Especially for
ZCE package 500MHz is the maximum supported value.) I tried to make a
common value for everything.

Do you want me to run at 720MHz then increase the voltage accordingly
and handle ZCE package separately?

Thanks and regards,
Lokesh

[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Tom Rini]

On Wed, May 03, 2017 at 09:10:35PM +0530, Lokesh Vutla wrote:
> 
> 
> On Wednesday 03 May 2017 08:53 PM, Tom Rini wrote:
> > On Wed, May 03, 2017 at 07:36:32PM +0530, Lokesh Vutla wrote:
> >>
> >>
> >> On Wednesday 03 May 2017 06:03 PM, Tom Rini wrote:
> >>> On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
> >>>> Update MPU frequencies and voltages as per the latest
> >>>> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
> >>>> Below is the consolidated data:
> >>>>
> >>>> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
> >>>>
> >>>>  -------------------------------------------------------
> >>>> |	|	  ZCZ		|	  ZCE		|
> >>>> |-------------------------------------------------------|
> >>>> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
> >>>> |-------|----------|------------|----------|------------|
> >>>> | NITRO |  1.325   |   1000     |   NA     |    NA      |
> >>>> |-------|----------|------------|----------|------------|
> >>>> | TURBO |   1.26   |    800	|   NA     |    NA      |
> >>>> |-------|----------|------------|----------|------------|
> >>>> |OPP120 |   1.20   |    720     |   NA     |    NA      |
> >>>> |-------|----------|------------|----------|------------|
> >>>> |OPP100 |   1.10   |    600     |   1.10   |    600     |
> >>>> |-------|----------|------------|----------|------------|
> >>>> | OPP50 |   0.95   |    300     |   0.95   |    300     |
> >>>>  -------------------------------------------------------
> >>>>
> >>>> There is no eFuse blown on PG1.0 Silicons due to which there is
> >>>> no way to detect the maximum frequencies supported. So default
> >>>> to OPP100 for which both frequency and voltages are common on both
> >>>> the packages.
> >>>
> >>> You say OPP100 here, but the code (and table) is for OPP50.  Which means
> >>> a good bit of a speed cut.
> >>
> >> The above table is for PG2.0 and later versions. For PG1.0 ARM runs at
> >> 500MHz in OPP100. Refer Table 5.3 and Table 5.5 in
> >> DM(http://www.ti.com/lit/ds/symlink/am3356.pdf)
> >>
> >>>
> >>> [snip]
> >>>>  /* MAIN PLL Fdll = 550 MHz, by default */
> >>>>  #ifndef CONFIG_SYS_MPUCLK
> >>>> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
> >>>> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
> >>>>  #endif
> >>>
> >>> Update the comment please.  Better yet, Kconfig migration (as this is
> >>> only an am33xx thing).
> >>
> >> Hmm.. The above value is used only for PG1.0 silicons and the value is
> >> fixed per SoC. Do we need a Kconfig symbol for that?
> > 
> > If you can get rid of it, do so, but please make sure to check on how
> > the other am335x boards are making use of it (ie the Siemens stuff).
> 
> okay Ill check it.
> 
> > 
> >>> [snip]
> >>>> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
> >>>>  
> >>>>  	sil_rev = readl(&cdev->deviceid) >> 28;
> >>>>  
> >>>> -	if (sil_rev == 1)
> >>>> -		/* PG 2.0, efuse may not be set. */
> >>>> -		return MPUPLL_M_800;
> >>>> -	else if (sil_rev >= 2) {
> >>>> +	if (sil_rev == 0) {
> >>>> +		/* No efuse in PG 1.0. So use OPP100 */
> >>>> +		return MPUPLL_M_500;
> >>>
> >>> Isn't that OPP50?
> >>>
> >>>> +	} else if (sil_rev >= 1) {
> >>>>  		/* Check what the efuse says our max speed is. */
> >>>> -		int efuse_arm_mpu_max_freq;
> >>>> +		int efuse_arm_mpu_max_freq, package_type;
> >>>>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
> >>>> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
> >>>> +				PACKAGE_TYPE_SHIFT;
> >>>> +
> >>>> +		/* PG 2.0, efuse may not be set. */
> >>>> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
> >>>> +		    PACKAGE_TYPE_RESERVED)
> >>>> +			return MPUPLL_M_800;
> >>>> +
> >>>>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
> >>>>  		case AM335X_ZCZ_1000:
> >>>>  			return MPUPLL_M_1000;
> >>>> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
> >>>>  		}
> >>>>  	}
> >>>>  
> >>>> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
> >>>> -	return MPUPLL_M_720;
> >>>> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
> >>>> +	return MPUPLL_M_500;
> >>>
> >>> Is the problem here new PG values getting unsafe values?  I'm concerned
> >>> about slowing down PG1.0 stuff which is also in the wild, in numbers.
> >>
> >> No, I just wanted to return a value as it is a non-void function, may be
> >> I should update the comment properly.
> > 
> > My concern is that PG1.0 stuff was previously being clocked at 720MHz,
> > but now will be down to 500MHz.  I'm not sure if in these cases anything
> > else (ie Linux) touches this and would be kicking it back up.  It'll
> > also slow down boot there a bit.  Thanks!
> 
> Till now for PG 1.0 we are clocking at 720MHz(OPP_NITRO for ZCZ package)
> and configuring voltages at 1.13V(OPP_100) which is wrong(Especially for
> ZCE package 500MHz is the maximum supported value.) I tried to make a
> common value for everything.
> 
> Do you want me to run at 720MHz then increase the voltage accordingly
> and handle ZCE package separately?

Well, part of the big open question here I have is, what does and
doesn't exist (and was shipped) for PG 1.0?  My recollection at the time
was that we didn't care about ZCZ vs ZCE packages as it basically came
down to Beaglebone White (and some lead customers) that got ZCZ PG 1.0
and everything else got PG2.x (with PG2.0 also being selective and PG2.1
being the general release).  I really don't want to start handicapping
BBW for in-theory stuff.  OTOH, if we can fix it up in the am335x_evm
specific code, that'll be good enough.  Thanks!

-- 
Tom
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[U-Boot] [PATCH 1/3] arm: am33xx: Fix MPU opp selection

[Lokesh Vutla]

On Wednesday 03 May 2017 09:19 PM, Tom Rini wrote:
> On Wed, May 03, 2017 at 09:10:35PM +0530, Lokesh Vutla wrote:
>>
>>
>> On Wednesday 03 May 2017 08:53 PM, Tom Rini wrote:
>>> On Wed, May 03, 2017 at 07:36:32PM +0530, Lokesh Vutla wrote:
>>>>
>>>>
>>>> On Wednesday 03 May 2017 06:03 PM, Tom Rini wrote:
>>>>> On Tue, May 02, 2017 at 07:40:24PM +0530, Lokesh Vutla wrote:
>>>>>> Update MPU frequencies and voltages as per the latest
>>>>>> DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
>>>>>> Below is the consolidated data:
>>>>>>
>>>>>> MPU values for PG 2.0 and later(Package ZCZ and ZCE):
>>>>>>
>>>>>>  -------------------------------------------------------
>>>>>> |	|	  ZCZ		|	  ZCE		|
>>>>>> |-------------------------------------------------------|
>>>>>> |	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
>>>>>> |-------|----------|------------|----------|------------|
>>>>>> | NITRO |  1.325   |   1000     |   NA     |    NA      |
>>>>>> |-------|----------|------------|----------|------------|
>>>>>> | TURBO |   1.26   |    800	|   NA     |    NA      |
>>>>>> |-------|----------|------------|----------|------------|
>>>>>> |OPP120 |   1.20   |    720     |   NA     |    NA      |
>>>>>> |-------|----------|------------|----------|------------|
>>>>>> |OPP100 |   1.10   |    600     |   1.10   |    600     |
>>>>>> |-------|----------|------------|----------|------------|
>>>>>> | OPP50 |   0.95   |    300     |   0.95   |    300     |
>>>>>>  -------------------------------------------------------
>>>>>>
>>>>>> There is no eFuse blown on PG1.0 Silicons due to which there is
>>>>>> no way to detect the maximum frequencies supported. So default
>>>>>> to OPP100 for which both frequency and voltages are common on both
>>>>>> the packages.
>>>>>
>>>>> You say OPP100 here, but the code (and table) is for OPP50.  Which means
>>>>> a good bit of a speed cut.
>>>>
>>>> The above table is for PG2.0 and later versions. For PG1.0 ARM runs at
>>>> 500MHz in OPP100. Refer Table 5.3 and Table 5.5 in
>>>> DM(http://www.ti.com/lit/ds/symlink/am3356.pdf)
>>>>
>>>>>
>>>>> [snip]
>>>>>>  /* MAIN PLL Fdll = 550 MHz, by default */
>>>>>>  #ifndef CONFIG_SYS_MPUCLK
>>>>>> -#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
>>>>>> +#define CONFIG_SYS_MPUCLK	MPUPLL_M_500
>>>>>>  #endif
>>>>>
>>>>> Update the comment please.  Better yet, Kconfig migration (as this is
>>>>> only an am33xx thing).
>>>>
>>>> Hmm.. The above value is used only for PG1.0 silicons and the value is
>>>> fixed per SoC. Do we need a Kconfig symbol for that?
>>>
>>> If you can get rid of it, do so, but please make sure to check on how
>>> the other am335x boards are making use of it (ie the Siemens stuff).
>>
>> okay Ill check it.

As you said, looks like lot of other users are using it. Ill convert to
Kconfig symbol.

>>
>>>
>>>>> [snip]
>>>>>> @@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>>>>>  
>>>>>>  	sil_rev = readl(&cdev->deviceid) >> 28;
>>>>>>  
>>>>>> -	if (sil_rev == 1)
>>>>>> -		/* PG 2.0, efuse may not be set. */
>>>>>> -		return MPUPLL_M_800;
>>>>>> -	else if (sil_rev >= 2) {
>>>>>> +	if (sil_rev == 0) {
>>>>>> +		/* No efuse in PG 1.0. So use OPP100 */
>>>>>> +		return MPUPLL_M_500;
>>>>>
>>>>> Isn't that OPP50?
>>>>>
>>>>>> +	} else if (sil_rev >= 1) {
>>>>>>  		/* Check what the efuse says our max speed is. */
>>>>>> -		int efuse_arm_mpu_max_freq;
>>>>>> +		int efuse_arm_mpu_max_freq, package_type;
>>>>>>  		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
>>>>>> +		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
>>>>>> +				PACKAGE_TYPE_SHIFT;
>>>>>> +
>>>>>> +		/* PG 2.0, efuse may not be set. */
>>>>>> +		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
>>>>>> +		    PACKAGE_TYPE_RESERVED)
>>>>>> +			return MPUPLL_M_800;
>>>>>> +
>>>>>>  		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
>>>>>>  		case AM335X_ZCZ_1000:
>>>>>>  			return MPUPLL_M_1000;
>>>>>> @@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
>>>>>>  		}
>>>>>>  	}
>>>>>>  
>>>>>> -	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
>>>>>> -	return MPUPLL_M_720;
>>>>>> +	/* PG 1.0 or otherwise unknown, use the PG1.0 safe */
>>>>>> +	return MPUPLL_M_500;
>>>>>
>>>>> Is the problem here new PG values getting unsafe values?  I'm concerned
>>>>> about slowing down PG1.0 stuff which is also in the wild, in numbers.
>>>>
>>>> No, I just wanted to return a value as it is a non-void function, may be
>>>> I should update the comment properly.
>>>
>>> My concern is that PG1.0 stuff was previously being clocked at 720MHz,
>>> but now will be down to 500MHz.  I'm not sure if in these cases anything
>>> else (ie Linux) touches this and would be kicking it back up.  It'll
>>> also slow down boot there a bit.  Thanks!
>>
>> Till now for PG 1.0 we are clocking at 720MHz(OPP_NITRO for ZCZ package)
>> and configuring voltages at 1.13V(OPP_100) which is wrong(Especially for
>> ZCE package 500MHz is the maximum supported value.) I tried to make a
>> common value for everything.
>>
>> Do you want me to run at 720MHz then increase the voltage accordingly
>> and handle ZCE package separately?
> 
> Well, part of the big open question here I have is, what does and
> doesn't exist (and was shipped) for PG 1.0?  My recollection at the time
> was that we didn't care about ZCZ vs ZCE packages as it basically came
> down to Beaglebone White (and some lead customers) that got ZCZ PG 1.0
> and everything else got PG2.x (with PG2.0 also being selective and PG2.1
> being the general release).  I really don't want to start handicapping

Okay. Then Ill use 720MHz for PG1.0 and repost the series.

Thanks and regards,
Lokesh