[RFC 0/7] drm/i915: Convert gen4- watermarks to atomic.

[RFC 0/7] drm/i915: Convert gen4- watermarks to atomic.

[Maarten Lankhorst]

I've only compile time tested this and the series depends on
Ville's gen4x watermark conversion so CI will fail to apply it.

Maarten Lankhorst (7):
  drm/i915: Calculate gen3- watermarks semi-atomically.
  drm/i915: Program gen3- watermarks atomically
  drm/i915: Convert pineview watermarks to atomic
  drm/i915: Calculate gen4 watermarks semiatomically.
  drm/i915: Program gen4 watermarks atomically
  drm/i915: Kill off intel_crtc_active.
  drm/i915: Rip out legacy watermark infrastructure

 drivers/gpu/drm/i915/i915_drv.h      |   6 +-
 drivers/gpu/drm/i915/intel_atomic.c  |   2 -
 drivers/gpu/drm/i915/intel_display.c |  97 +-----
 drivers/gpu/drm/i915/intel_drv.h     |  18 +-
 drivers/gpu/drm/i915/intel_fbc.c     |   2 +-
 drivers/gpu/drm/i915/intel_pm.c      | 635 ++++++++++++++++++++++-------------
 6 files changed, 433 insertions(+), 327 deletions(-)

-- 
2.9.3

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[RFC 1/7] drm/i915: Calculate gen3- watermarks semi-atomically.

[Maarten Lankhorst]

The gen3 watermark calculations are converted to atomic,
but the wm update calls are still done through the legacy
functions.

This will make it easier to bisect things if they go wrong.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h     |  14 +++
 drivers/gpu/drm/i915/intel_pm.c      | 231 +++++++++++++++++++++--------------
 3 files changed, 152 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4991ef2ac77d..c7d295a0895d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15518,7 +15518,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 		skl_wm_get_hw_state(dev);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_wm_get_hw_state(dev);
-	}
+	} else if (INTEL_GEN(dev_priv) <= 3 && !IS_PINEVIEW(dev_priv))
+		i9xx_wm_get_hw_state(dev);
 
 	for_each_intel_crtc(dev, crtc) {
 		u64 put_domains;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ae9173707959..d9e49f2b3c22 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -546,6 +546,15 @@ struct g4x_wm_state {
 	bool fbc_en;
 };
 
+struct i9xx_wm_state {
+	uint16_t plane_wm;
+	bool cxsr;
+
+	struct {
+		uint16_t plane;
+	} sr;
+};
+
 struct intel_crtc_wm_state {
 	union {
 		struct {
@@ -590,6 +599,9 @@ struct intel_crtc_wm_state {
 			/* optimal watermarks */
 			struct g4x_wm_state optimal;
 		} g4x;
+		struct {
+			struct i9xx_wm_state optimal;
+		} i9xx;
 	};
 
 	/*
@@ -828,6 +840,7 @@ struct intel_crtc {
 			struct intel_pipe_wm ilk;
 			struct vlv_wm_state vlv;
 			struct g4x_wm_state g4x;
+			struct i9xx_wm_state i9xx;
 		} active;
 	} wm;
 
@@ -1868,6 +1881,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
 		    unsigned long submitted);
 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
 void g4x_wm_get_hw_state(struct drm_device *dev);
+void i9xx_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
 void skl_wm_get_hw_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d2cec3249e87..0c933cfad02c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2226,89 +2226,154 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 
 #undef FW_WM
 
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static const struct intel_watermark_params *i9xx_get_wm_info(struct drm_i915_private *dev_priv,
+							     struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	const struct intel_watermark_params *wm_info;
-	uint32_t fwater_lo;
-	uint32_t fwater_hi;
-	int cwm, srwm = 1;
-	int fifo_size;
-	int planea_wm, planeb_wm;
-	struct intel_crtc *crtc, *enabled = NULL;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 
 	if (IS_I945GM(dev_priv))
-		wm_info = &i945_wm_info;
+		return &i945_wm_info;
 	else if (!IS_GEN2(dev_priv))
-		wm_info = &i915_wm_info;
+		return &i915_wm_info;
+	else if (plane->plane == PLANE_A)
+		return &i830_a_wm_info;
 	else
-		wm_info = &i830_a_wm_info;
+		return &i830_bc_wm_info;
+}
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
-	crtc = intel_get_crtc_for_plane(dev_priv, 0);
-	if (intel_crtc_active(crtc)) {
+static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->base.state);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct drm_plane_state *plane_state = NULL;
+	int fifo_size;
+	const struct intel_watermark_params *wm_info;
+
+	fifo_size = dev_priv->display.get_fifo_size(dev_priv, plane->plane);
+
+	wm_info = i9xx_get_wm_info(dev_priv, crtc);
+
+	wm_state->cxsr = false;
+	memset(&wm_state->sr, 0, sizeof(wm_state->sr));
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (!plane_state || !intel_wm_plane_visible(crtc_state, to_intel_plane_state(plane_state))) {
+		wm_state->plane_wm = fifo_size - wm_info->guard_size;
+		if (wm_state->plane_wm > (long)wm_info->max_wm)
+			wm_state->plane_wm = wm_info->max_wm;
+	} else if (HAS_FW_BLC(dev_priv)) {
+		struct drm_framebuffer *fb = plane_state->fb;
+		unsigned cpp = IS_GEN2(dev_priv) ? 4 : fb->format->cpp[0];
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int cpp;
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+		bool may_cxsr;
 
-		if (IS_GEN2(dev_priv))
-			cpp = 4;
+		if (state->modeset)
+			active_crtcs = state->active_crtcs;
 		else
-			cpp = fb->format->cpp[0];
+			active_crtcs = dev_priv->active_crtcs;
 
-		planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-					       wm_info, fifo_size, cpp,
-					       pessimal_latency_ns);
-		enabled = crtc;
-	} else {
-		planea_wm = fifo_size - wm_info->guard_size;
-		if (planea_wm > (long)wm_info->max_wm)
-			planea_wm = wm_info->max_wm;
+		may_cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+		wm_state->plane_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
+							wm_info, fifo_size, cpp,
+							pessimal_latency_ns);
+
+		DRM_DEBUG_KMS("FIFO watermarks - plane watermarks: %d\n", wm_state->plane_wm);
+
+		if (IS_I915GM(dev_priv) && i915_gem_object_is_tiled(intel_fb_obj(fb)))
+			may_cxsr = false;
+
+		if (may_cxsr) {
+			static const int sr_latency_ns = 6000;
+			unsigned long entries;
+
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   crtc_state->pipe_src_w, cpp,
+						   sr_latency_ns / 100);
+			entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
+
+			DRM_DEBUG_KMS("self-refresh entries: %ld\n", entries);
+
+			if (wm_info->fifo_size >= entries) {
+				wm_state->cxsr = true;
+				wm_state->sr.plane = wm_info->fifo_size - entries;
+			} else
+				may_cxsr = false;
+		}
+
+		DRM_DEBUG_KMS("FIFO watermarks - plane watermarks: %d, can cxsr: %s, SR size: %d\n",
+			      wm_state->plane_wm, yesno(wm_state->cxsr), wm_state->sr.plane);
 	}
 
-	if (IS_GEN2(dev_priv))
-		wm_info = &i830_bc_wm_info;
+	return 0;
+}
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
-	crtc = intel_get_crtc_for_plane(dev_priv, 1);
-	if (intel_crtc_active(crtc)) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int cpp;
+void i9xx_wm_get_hw_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *crtc;
+	uint32_t fwater_lo, planea_wm, planeb_wm;
+
+	fwater_lo = I915_READ(FW_BLC);
+
+	planea_wm = fwater_lo & 0x3f;
+	planeb_wm = (fwater_lo >> 16) & 0x3f;
+
+	for_each_intel_crtc(dev, crtc) {
+		struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
+		struct i9xx_wm_state *wm_state = &cstate->wm.i9xx.optimal;
+		struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+
+		memset(&wm_state->sr, 0, sizeof(wm_state->sr));
+		wm_state->cxsr = false;
 
-		if (IS_GEN2(dev_priv))
-			cpp = 4;
+		if (plane == PLANE_A)
+			wm_state->plane_wm = planea_wm;
 		else
-			cpp = fb->format->cpp[0];
+			wm_state->plane_wm = planeb_wm;
+
+		crtc->wm.active.i9xx = *wm_state;
+	}
+}
 
-		planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-					       wm_info, fifo_size, cpp,
-					       pessimal_latency_ns);
+static void i9xx_update_wm(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	uint32_t fwater_lo;
+	uint32_t fwater_hi;
+	int cwm, srwm = -1;
+	int planea_wm, planeb_wm;
+	struct intel_crtc *enabled = NULL;
+
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
+
+	crtc = intel_get_crtc_for_plane(dev_priv, 0);
+	planea_wm = crtc->wm.active.i9xx.plane_wm;
+	if (intel_crtc_active(crtc))
+		enabled = crtc;
+
+	crtc = intel_get_crtc_for_plane(dev_priv, 1);
+	if (intel_crtc_active(crtc)) {
 		if (enabled == NULL)
 			enabled = crtc;
 		else
 			enabled = NULL;
-	} else {
-		planeb_wm = fifo_size - wm_info->guard_size;
-		if (planeb_wm > (long)wm_info->max_wm)
-			planeb_wm = wm_info->max_wm;
 	}
+	planeb_wm = crtc->wm.active.i9xx.plane_wm;
 
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
-	if (IS_I915GM(dev_priv) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->base.primary->state->fb);
-
-		/* self-refresh seems busted with untiled */
-		if (!i915_gem_object_is_tiled(obj))
-			enabled = NULL;
-	}
+	if (!enabled->wm.active.i9xx.cxsr)
+		enabled = NULL;
 
 	/*
 	 * Overlay gets an aggressive default since video jitter is bad.
@@ -2319,31 +2384,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	intel_set_memory_cxsr(dev_priv, false);
 
 	/* Calc sr entries for one plane configs */
-	if (HAS_FW_BLC(dev_priv) && enabled) {
-		/* self-refresh has much higher latency */
-		static const int sr_latency_ns = 6000;
-		const struct drm_display_mode *adjusted_mode =
-			&enabled->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			enabled->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
-		int hdisplay = enabled->config->pipe_src_w;
-		int cpp;
-		int entries;
-
-		if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
-			cpp = 4;
-		else
-			cpp = fb->format->cpp[0];
-
-		entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
-					   sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
-		DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
-		srwm = wm_info->fifo_size - entries;
-		if (srwm < 0)
-			srwm = 1;
+	if (enabled) {
+		srwm = enabled->wm.active.i9xx.sr.plane;
 
 		if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
 			I915_WRITE(FW_BLC_SELF,
@@ -2369,23 +2411,18 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		intel_set_memory_cxsr(dev_priv, true);
 }
 
-static void i845_update_wm(struct intel_crtc *unused_crtc)
+static void i845_update_wm(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
-	const struct drm_display_mode *adjusted_mode;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t fwater_lo;
 	int planea_wm;
 
-	crtc = single_enabled_crtc(dev_priv);
-	if (crtc == NULL)
+	if (!intel_crtc_active(crtc))
 		return;
 
-	adjusted_mode = &crtc->config->base.adjusted_mode;
-	planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
-				       &i845_wm_info,
-				       dev_priv->display.get_fifo_size(dev_priv, 0),
-				       4, pessimal_latency_ns);
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
+	planea_wm = crtc->wm.active.i9xx.plane_wm;
+
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
 
@@ -8705,9 +8742,13 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
 		dev_priv->display.update_wm = i9xx_update_wm;
+
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (IS_GEN2(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+
 		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
 			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
-- 
2.9.3

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[RFC 2/7] drm/i915: Program gen3- watermarks atomically

[Maarten Lankhorst]

With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 ++
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 103 +++++++++++++++++++++++++++++++++------
 3 files changed, 95 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91b945cd39f9..7af4f908b2cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1793,6 +1793,10 @@ struct g4x_wm_values {
 	bool fbc_en;
 };
 
+struct i9xx_wm_values {
+	bool cxsr;
+};
+
 struct skl_ddb_entry {
 	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
 };
@@ -2422,6 +2426,7 @@ struct drm_i915_private {
 			struct skl_wm_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
+			struct i9xx_wm_values i9xx;
 		};
 
 		uint8_t max_level;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9e49f2b3c22..73e74fc7383c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -600,7 +600,7 @@ struct intel_crtc_wm_state {
 			struct g4x_wm_state optimal;
 		} g4x;
 		struct {
-			struct i9xx_wm_state optimal;
+			struct i9xx_wm_state optimal, intermediate;
 		} i9xx;
 	};
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0c933cfad02c..c39f63aff4a5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -433,6 +433,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		dev_priv->wm.vlv.cxsr = enable;
 	else if (IS_G4X(dev_priv))
 		dev_priv->wm.g4x.cxsr = enable;
+	else if (INTEL_GEN(dev_priv) <= 4)
+		dev_priv->wm.i9xx.cxsr = enable;
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 
 	return ret;
@@ -2317,6 +2319,44 @@ static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static int i9xx_compute_intermediate_wm(struct drm_device *dev,
+				       struct intel_crtc *intel_crtc,
+				       struct intel_crtc_state *newstate)
+{
+	struct i9xx_wm_state *intermediate = &newstate->wm.i9xx.intermediate;
+	const struct drm_crtc_state *old_drm_state =
+		drm_atomic_get_old_crtc_state(newstate->base.state, &intel_crtc->base);
+	const struct i9xx_wm_state *old = &to_intel_crtc_state(old_drm_state)->wm.i9xx.optimal;
+	const struct i9xx_wm_state *optimal = &newstate->wm.i9xx.optimal;
+
+	/*
+	 * Start with the final, target watermarks, then combine with the
+	 * currently active watermarks to get values that are safe both before
+	 * and after the vblank.
+	 */
+	*intermediate = *optimal;
+	if (newstate->disable_cxsr)
+		intermediate->cxsr = false;
+
+	if (!newstate->base.active ||
+	    drm_atomic_crtc_needs_modeset(&newstate->base))
+		goto out;
+
+	intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm);
+	intermediate->sr.plane = min(old->sr.plane, optimal->sr.plane);
+
+out:
+	/*
+	 * If our intermediate WM are identical to the final WM, then we can
+	 * omit the post-vblank programming; only update if it's different.
+	 */
+	if (newstate->base.active &&
+	    memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
+		newstate->wm.need_postvbl_update = true;
+
+	return 0;
+}
+
 void i9xx_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2345,17 +2385,15 @@ void i9xx_wm_get_hw_state(struct drm_device *dev)
 	}
 }
 
-static void i9xx_update_wm(struct intel_crtc *crtc)
+static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc *crtc;
 	uint32_t fwater_lo;
 	uint32_t fwater_hi;
 	int cwm, srwm = -1;
 	int planea_wm, planeb_wm;
 	struct intel_crtc *enabled = NULL;
 
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
 	crtc = intel_get_crtc_for_plane(dev_priv, 0);
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 	if (intel_crtc_active(crtc))
@@ -2381,7 +2419,7 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	cwm = 2;
 
 	/* Play safe and disable self-refresh before adjusting watermarks. */
-	intel_set_memory_cxsr(dev_priv, false);
+	_intel_set_memory_cxsr(dev_priv, false);
 
 	/* Calc sr entries for one plane configs */
 	if (enabled) {
@@ -2408,19 +2446,17 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC2, fwater_hi);
 
 	if (enabled)
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+
+	dev_priv->wm.i9xx.cxsr = enabled;
 }
 
-static void i845_update_wm(struct intel_crtc *crtc)
+static void i845_program_watermarks(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t fwater_lo;
 	int planea_wm;
 
-	if (!intel_crtc_active(crtc))
-		return;
-
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -2431,6 +2467,41 @@ static void i845_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC, fwater_lo);
 }
 
+
+static void i9xx_initial_watermarks(struct intel_atomic_state *state,
+				   struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate;
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
+static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
+				    struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	if (!crtc_state->wm.need_postvbl_update)
+		return;
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal;
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
 /* latency must be in 0.1us units. */
 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
 				   unsigned int cpp,
@@ -8743,17 +8814,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
-		dev_priv->display.update_wm = i9xx_update_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (IS_GEN2(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
-			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
 		} else {
-			dev_priv->display.update_wm = i9xx_update_wm;
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 		}
 	} else {
-- 
2.9.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 3/7] drm/i915: Convert pineview watermarks to atomic

[Maarten Lankhorst]

Pineview seems to have different watermarks from the other
platforms and are calculated separately.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h |   3 +-
 drivers/gpu/drm/i915/intel_pm.c  | 134 ++++++++++++++++++++++++++-------------
 2 files changed, 92 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 73e74fc7383c..62f690c7691e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -552,7 +552,8 @@ struct i9xx_wm_state {
 
 	struct {
 		uint16_t plane;
-	} sr;
+		uint16_t cursor;
+	} sr, hpll;
 };
 
 struct intel_crtc_wm_state {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c39f63aff4a5..eb1bb8b3f9a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -824,13 +824,17 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 	return enabled;
 }
 
-static void pineview_update_wm(struct intel_crtc *unused_crtc)
+static int pnv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
+	const struct drm_plane_state *primary_plane_state = NULL;
 	const struct cxsr_latency *latency;
-	u32 reg;
-	unsigned int wm;
+
+	memset(wm_state, 0, sizeof(*wm_state));
 
 	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 					 dev_priv->is_ddr3,
@@ -838,60 +842,90 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
 					 dev_priv->mem_freq);
 	if (!latency) {
 		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
-		intel_set_memory_cxsr(dev_priv, false);
-		return;
+
+		return 0;
 	}
 
-	crtc = single_enabled_crtc(dev_priv);
-	if (crtc) {
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (primary_plane_state) {
 		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
+			primary_plane_state->fb;
 		int cpp = fb->format->cpp[0];
-		int clock = adjusted_mode->crtc_clock;
+		const struct drm_display_mode *adjusted_mode =
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+
+		if (state->modeset)
+			active_crtcs = state->active_crtcs;
+		else
+			active_crtcs = dev_priv->active_crtcs;
+
+		wm_state->cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+		wm_state->sr.plane = intel_calculate_wm(adjusted_mode->crtc_clock,
+							&pineview_display_wm,
+							pineview_display_wm.fifo_size,
+							cpp, latency->display_sr);
+
+		wm_state->sr.cursor = intel_calculate_wm(adjusted_mode->crtc_clock,
+							 &pineview_cursor_wm,
+							 pineview_display_wm.fifo_size,
+							 4, latency->cursor_sr);
+
+		wm_state->hpll.plane = intel_calculate_wm(adjusted_mode->crtc_clock,
+								 &pineview_display_hplloff_wm,
+								 pineview_display_hplloff_wm.fifo_size,
+								 cpp, latency->display_hpll_disable);
+
+		wm_state->hpll.cursor = intel_calculate_wm(adjusted_mode->crtc_clock,
+								  &pineview_cursor_hplloff_wm,
+								  pineview_display_hplloff_wm.fifo_size,
+								  4, latency->cursor_hpll_disable);
+
+		DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n",
+			      yesno(wm_state->cxsr), wm_state->sr.plane, wm_state->sr.cursor);
+	} else
+		wm_state->cxsr = false;
+
+	return 0;
+}
+
+static void pnv_program_watermarks(struct drm_i915_private *dev_priv)
+{
+	struct intel_crtc *crtc;
+	struct i9xx_wm_state *wm_state = NULL;
+
+	crtc = single_enabled_crtc(dev_priv);
+	if (crtc)
+		wm_state = &crtc->wm.active.i9xx;
+
+	if (wm_state && wm_state->cxsr) {
+		u32 reg;
 
 		/* Display SR */
-		wm = intel_calculate_wm(clock, &pineview_display_wm,
-					pineview_display_wm.fifo_size,
-					cpp, latency->display_sr);
 		reg = I915_READ(DSPFW1);
 		reg &= ~DSPFW_SR_MASK;
-		reg |= FW_WM(wm, SR);
+		reg |= FW_WM(wm_state->sr.plane, SR);
 		I915_WRITE(DSPFW1, reg);
 		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 
 		/* cursor SR */
-		wm = intel_calculate_wm(clock, &pineview_cursor_wm,
-					pineview_display_wm.fifo_size,
-					4, latency->cursor_sr);
 		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_CURSOR_SR_MASK;
-		reg |= FW_WM(wm, CURSOR_SR);
+		reg &= ~(DSPFW_CURSOR_SR_MASK | DSPFW_HPLL_SR_MASK | DSPFW_HPLL_CURSOR_MASK);
+		reg |= FW_WM(wm_state->sr.cursor, CURSOR_SR);
+		reg |= FW_WM(wm_state->hpll.plane, HPLL_SR);
+		reg |= FW_WM(wm_state->hpll.cursor, HPLL_SR);
 		I915_WRITE(DSPFW3, reg);
 
-		/* Display HPLL off SR */
-		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
-					pineview_display_hplloff_wm.fifo_size,
-					cpp, latency->display_hpll_disable);
-		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_HPLL_SR_MASK;
-		reg |= FW_WM(wm, HPLL_SR);
-		I915_WRITE(DSPFW3, reg);
-
-		/* cursor HPLL off SR */
-		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
-					pineview_display_hplloff_wm.fifo_size,
-					4, latency->cursor_hpll_disable);
-		reg = I915_READ(DSPFW3);
-		reg &= ~DSPFW_HPLL_CURSOR_MASK;
-		reg |= FW_WM(wm, HPLL_CURSOR);
-		I915_WRITE(DSPFW3, reg);
 		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 
 		intel_set_memory_cxsr(dev_priv, true);
+		dev_priv->wm.i9xx.cxsr = true;
 	} else {
 		intel_set_memory_cxsr(dev_priv, false);
+		dev_priv->wm.i9xx.cxsr = false;
 	}
 }
 
@@ -2344,6 +2378,9 @@ static int i9xx_compute_intermediate_wm(struct drm_device *dev,
 
 	intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm);
 	intermediate->sr.plane = min(old->sr.plane, optimal->sr.plane);
+	intermediate->sr.cursor = min(old->sr.cursor, optimal->sr.cursor);
+	intermediate->hpll.plane = min(old->hpll.plane, optimal->hpll.plane);
+	intermediate->hpll.cursor = min(old->hpll.cursor, optimal->hpll.cursor);
 
 out:
 	/*
@@ -2477,7 +2514,9 @@ static void i9xx_initial_watermarks(struct intel_atomic_state *state,
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate;
-	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+	if (IS_PINEVIEW(dev_priv))
+		pnv_program_watermarks(dev_priv);
+	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
 	else
 		i9xx_program_watermarks(dev_priv);
@@ -2495,7 +2534,9 @@ static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
 
 	mutex_lock(&dev_priv->wm.wm_mutex);
 	intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal;
-	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+	if (IS_PINEVIEW(dev_priv))
+		pnv_program_watermarks(dev_priv);
+	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
 	else
 		i9xx_program_watermarks(dev_priv);
@@ -8807,9 +8848,14 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
-			dev_priv->display.update_wm = NULL;
-		} else
-			dev_priv->display.update_wm = pineview_update_wm;
+			dev_priv->display.compute_pipe_wm = NULL;
+			dev_priv->display.initial_watermarks = NULL;
+			dev_priv->display.optimize_watermarks = NULL;
+		} else {
+			dev_priv->display.compute_pipe_wm = pnv_compute_pipe_wm;
+			dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+			dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
+		}
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
-- 
2.9.3

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[RFC 4/7] drm/i915: Calculate gen4 watermarks semiatomically.

[Maarten Lankhorst]

Gen4 watermark is handled same as gen3-. Calculate
the optimal watermarks atomically first, and program
it in the legacy helper.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 136 ++++++++++++++++++++++++++++------------
 1 file changed, 95 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb1bb8b3f9a6..c5bdef6281f3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2189,58 +2189,109 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static int i965_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
-	struct intel_crtc *crtc;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->base.state);
+	struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal;
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct drm_plane_state *primary_plane_state = NULL;
+	const struct drm_plane_state *cursor_plane_state = NULL;
+
+	memset(wm_state, 0, sizeof(*wm_state));
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base)))
+		primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base);
+
+	if (crtc_state->base.plane_mask & BIT(drm_plane_index(crtc->base.cursor)))
+		cursor_plane_state = __drm_atomic_get_current_plane_state(&state->base, crtc->base.cursor);
+
+	if (primary_plane_state) {
+		static const int sr_latency_ns = 12000;
+		const struct drm_display_mode *adjusted_mode =
+			&crtc_state->base.adjusted_mode;
+		unsigned active_crtcs;
+		unsigned long entries;
+		bool may_cxsr;
+
+		if (state->modeset)
+			active_crtcs = state->active_crtcs;
+		else
+			active_crtcs = dev_priv->active_crtcs;
+
+		may_cxsr = active_crtcs == drm_crtc_mask(&crtc->base);
+
+		if (may_cxsr && intel_wm_plane_visible(crtc_state, to_intel_plane_state(primary_plane_state))) {
+			struct drm_framebuffer *fb = primary_plane_state->fb;
+			unsigned cpp = fb->format->cpp[0];
+
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   crtc_state->pipe_src_w, cpp,
+						   sr_latency_ns / 100);
+			entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
+			if (entries < I965_FIFO_SIZE)
+				wm_state->sr.plane = I965_FIFO_SIZE - entries;
+			else
+				may_cxsr = false;
+
+			DRM_DEBUG_KMS("self-refresh entries: %ld\n", entries);
+		}
+
+		/* No need to use intel_wm_plane_visible here, since cursor. */
+		if (may_cxsr && cursor_plane_state && crtc_state->base.active) {
+			entries = intel_wm_method2(adjusted_mode->crtc_clock,
+						   adjusted_mode->crtc_htotal,
+						   cursor_plane_state->crtc_w, 4,
+						   sr_latency_ns / 100);
+
+			entries = DIV_ROUND_UP(entries,
+					      i965_cursor_wm_info.cacheline_size) +
+				i965_cursor_wm_info.guard_size;
+
+			if (entries < i965_cursor_wm_info.fifo_size)
+				wm_state->sr.cursor = min(i965_cursor_wm_info.fifo_size - entries,
+							  (unsigned long)(i965_cursor_wm_info.max_wm));
+			else
+				may_cxsr = false;
+		} else if (may_cxsr)
+			wm_state->sr.cursor = 16;
+
+		wm_state->cxsr = may_cxsr;
+
+		DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n",
+			      yesno(wm_state->cxsr), wm_state->sr.plane, wm_state->sr.cursor);
+	}
+
+	return 0;
+}
+
+static void i965_update_wm(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int srwm = 1;
 	int cursor_sr = 16;
-	bool cxsr_enabled;
+	bool cxsr_enabled = false;
+
+	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
 
 	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev_priv);
-	if (crtc) {
-		/* self-refresh has much higher latency */
-		static const int sr_latency_ns = 12000;
-		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
-		const struct drm_framebuffer *fb =
-			crtc->base.primary->state->fb;
-		int clock = adjusted_mode->crtc_clock;
-		int htotal = adjusted_mode->crtc_htotal;
-		int hdisplay = crtc->config->pipe_src_w;
-		int cpp = fb->format->cpp[0];
-		int entries;
-
-		entries = intel_wm_method2(clock, htotal,
-					   hdisplay, cpp, sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
-		srwm = I965_FIFO_SIZE - entries;
-		if (srwm < 0)
-			srwm = 1;
-		srwm &= 0x1ff;
-		DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
-			      entries, srwm);
-
-		entries = intel_wm_method2(clock, htotal,
-					   crtc->base.cursor->state->crtc_w, 4,
-					   sr_latency_ns / 100);
-		entries = DIV_ROUND_UP(entries,
-				       i965_cursor_wm_info.cacheline_size) +
-			i965_cursor_wm_info.guard_size;
-
-		cursor_sr = i965_cursor_wm_info.fifo_size - entries;
-		if (cursor_sr > i965_cursor_wm_info.max_wm)
-			cursor_sr = i965_cursor_wm_info.max_wm;
+	if (crtc && crtc->wm.active.i9xx.cxsr) {
+		struct i9xx_wm_state *wm_state = &crtc->wm.active.i9xx;
+
+		srwm = wm_state->sr.plane;
+		cursor_sr = wm_state->sr.cursor;
 
 		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
 			      "cursor %d\n", srwm, cursor_sr);
 
 		cxsr_enabled = true;
-	} else {
-		cxsr_enabled = false;
+	} else if (dev_priv->wm.i9xx.cxsr) {
 		/* Turn off self refresh if both pipes are enabled */
-		intel_set_memory_cxsr(dev_priv, false);
+		_intel_set_memory_cxsr(dev_priv, false);
 	}
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2257,7 +2308,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 	I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
 
 	if (cxsr_enabled)
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+
+	dev_priv->wm.i9xx.cxsr = cxsr_enabled;
 }
 
 #undef FW_WM
@@ -8857,6 +8910,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 			dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 		}
 	} else if (IS_GEN4(dev_priv)) {
+		dev_priv->display.compute_pipe_wm = i965_compute_pipe_wm;
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
-- 
2.9.3

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[RFC 5/7] drm/i915: Program gen4 watermarks atomically

[Maarten Lankhorst]

We're already calculating the watermarks correctly, now we have to
program them too.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c5bdef6281f3..969eb11ed5cd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2268,20 +2268,20 @@ static int i965_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static void i965_update_wm(struct intel_crtc *crtc)
+static void i965_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc *crtc;
+	struct i9xx_wm_state *wm_state = NULL;
 	int srwm = 1;
 	int cursor_sr = 16;
 	bool cxsr_enabled = false;
 
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
-	/* Calc sr entries for one plane configs */
 	crtc = single_enabled_crtc(dev_priv);
-	if (crtc && crtc->wm.active.i9xx.cxsr) {
-		struct i9xx_wm_state *wm_state = &crtc->wm.active.i9xx;
+	if (crtc)
+		wm_state = &crtc->wm.active.i9xx;
 
+	/* Calc sr entries for one plane configs */
+	if (wm_state && wm_state->cxsr) {
 		srwm = wm_state->sr.plane;
 		cursor_sr = wm_state->sr.cursor;
 
@@ -2571,8 +2571,10 @@ static void i9xx_initial_watermarks(struct intel_atomic_state *state,
 		pnv_program_watermarks(dev_priv);
 	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
-	else
+	else if (INTEL_GEN(dev_priv) < 4)
 		i9xx_program_watermarks(dev_priv);
+	else
+		i965_program_watermarks(dev_priv);
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -2591,8 +2593,10 @@ static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
 		pnv_program_watermarks(dev_priv);
 	else if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		i845_program_watermarks(intel_crtc);
-	else
+	else if (INTEL_GEN(dev_priv) < 4)
 		i9xx_program_watermarks(dev_priv);
+	else
+		i965_program_watermarks(dev_priv);
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -8911,7 +8915,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		}
 	} else if (IS_GEN4(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i965_compute_pipe_wm;
-		dev_priv->display.update_wm = i965_update_wm;
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
 		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
-- 
2.9.3

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[RFC 6/7] drm/i915: Kill off intel_crtc_active.

[Maarten Lankhorst]

Use crtc->active directly instead. This is still not completely
optimal and needs fixing, but it's about as good as using
intel_crtc_active.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 19 -------------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 drivers/gpu/drm/i915/intel_fbc.c     |  2 +-
 drivers/gpu/drm/i915/intel_pm.c      |  6 +++---
 4 files changed, 4 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c7d295a0895d..8538c0246015 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -948,25 +948,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 				  target_clock, refclk, NULL, best_clock);
 }
 
-bool intel_crtc_active(struct intel_crtc *crtc)
-{
-	/* Be paranoid as we can arrive here with only partial
-	 * state retrieved from the hardware during setup.
-	 *
-	 * We can ditch the adjusted_mode.crtc_clock check as soon
-	 * as Haswell has gained clock readout/fastboot support.
-	 *
-	 * We can ditch the crtc->primary->fb check as soon as we can
-	 * properly reconstruct framebuffers.
-	 *
-	 * FIXME: The intel_crtc->active here should be switched to
-	 * crtc->state->active once we have proper CRTC states wired up
-	 * for atomic.
-	 */
-	return crtc->active && crtc->base.primary->state->fb &&
-		crtc->config->base.adjusted_mode.crtc_clock;
-}
-
 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 					     enum pipe pipe)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 62f690c7691e..dbe33b7bcf67 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1490,7 +1490,6 @@ bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 			struct dpll *best_clock);
 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
 
-bool intel_crtc_active(struct intel_crtc *crtc);
 void hsw_enable_ips(struct intel_crtc *crtc);
 void hsw_disable_ips(struct intel_crtc *crtc);
 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add18b26..a93214d0388e 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1282,7 +1282,7 @@ void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
 		return;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc)
-		if (intel_crtc_active(crtc) &&
+		if (crtc->base.state->active &&
 		    crtc->base.primary->state->visible)
 			dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 969eb11ed5cd..bf2127a3f730 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -814,7 +814,7 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 	struct intel_crtc *crtc, *enabled = NULL;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
-		if (intel_crtc_active(crtc)) {
+		if (crtc->active) {
 			if (enabled)
 				return NULL;
 			enabled = crtc;
@@ -2486,11 +2486,11 @@ static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
 
 	crtc = intel_get_crtc_for_plane(dev_priv, 0);
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
-	if (intel_crtc_active(crtc))
+	if (crtc->active)
 		enabled = crtc;
 
 	crtc = intel_get_crtc_for_plane(dev_priv, 1);
-	if (intel_crtc_active(crtc)) {
+	if (crtc->active) {
 		if (enabled == NULL)
 			enabled = crtc;
 		else
-- 
2.9.3

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[RFC 7/7] drm/i915: Rip out legacy watermark infrastructure

[Maarten Lankhorst]

The legacy watermark infrastructure is now unused, so remove it.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 -
 drivers/gpu/drm/i915/intel_atomic.c  |  2 -
 drivers/gpu/drm/i915/intel_display.c | 75 ++----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 -
 drivers/gpu/drm/i915/intel_pm.c      | 42 --------------------
 5 files changed, 3 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7af4f908b2cd..46b317c991f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -637,7 +637,6 @@ struct drm_i915_display_funcs {
 	void (*optimize_watermarks)(struct intel_atomic_state *state,
 				    struct intel_crtc_state *cstate);
 	int (*compute_global_watermarks)(struct drm_atomic_state *state);
-	void (*update_wm)(struct intel_crtc *crtc);
 	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 87b1dd464eee..7a4acaa45edd 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -173,8 +173,6 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->update_pipe = false;
 	crtc_state->disable_lp_wm = false;
 	crtc_state->disable_cxsr = false;
-	crtc_state->update_wm_pre = false;
-	crtc_state->update_wm_post = false;
 	crtc_state->fb_changed = false;
 	crtc_state->fifo_changed = false;
 	crtc_state->wm.need_postvbl_update = false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8538c0246015..295e17d0f272 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4958,9 +4958,6 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
 
 	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
 
-	if (pipe_config->update_wm_post && pipe_config->base.active)
-		intel_update_watermarks(crtc);
-
 	if (old_pri_state) {
 		struct intel_plane_state *primary_state =
 			to_intel_plane_state(primary->state);
@@ -5050,8 +5047,6 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
 						     pipe_config);
-	else if (pipe_config->update_wm_pre)
-		intel_update_watermarks(crtc);
 }
 
 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
@@ -5737,8 +5732,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
 						     intel_crtc->config);
-	else
-		intel_update_watermarks(intel_crtc);
 	intel_enable_pipe(intel_crtc);
 
 	assert_vblank_disabled(crtc);
@@ -5802,9 +5795,6 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
 
 	if (!IS_GEN2(dev_priv))
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
-	if (!dev_priv->display.initial_watermarks)
-		intel_update_watermarks(intel_crtc);
 }
 
 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
@@ -5863,7 +5853,6 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
 		encoder->base.crtc = NULL;
 
 	intel_fbc_disable(intel_crtc);
-	intel_update_watermarks(intel_crtc);
 	intel_disable_shared_dpll(intel_crtc);
 
 	domains = intel_crtc->enabled_power_domains;
@@ -10738,40 +10727,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 }
 
 
-/**
- * intel_wm_need_update - Check whether watermarks need updating
- * @plane: drm plane
- * @state: new plane state
- *
- * Check current plane state versus the new one to determine whether
- * watermarks need to be recalculated.
- *
- * Returns true or false.
- */
-static bool intel_wm_need_update(struct drm_plane *plane,
-				 struct drm_plane_state *state)
-{
-	struct intel_plane_state *new = to_intel_plane_state(state);
-	struct intel_plane_state *cur = to_intel_plane_state(plane->state);
-
-	/* Update watermarks on tiling or size changes. */
-	if (new->base.visible != cur->base.visible)
-		return true;
-
-	if (!cur->base.fb || !new->base.fb)
-		return false;
-
-	if (cur->base.fb->modifier != new->base.fb->modifier ||
-	    cur->base.rotation != new->base.rotation ||
-	    drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
-	    drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
-	    drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
-	    drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
-		return true;
-
-	return false;
-}
-
 static bool needs_scaling(struct intel_plane_state *state)
 {
 	int src_w = drm_rect_width(&state->base.src) >> 16;
@@ -10848,27 +10803,9 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
 			 was_visible, visible,
 			 turn_off, turn_on, mode_changed);
 
-	if (turn_on) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
-			pipe_config->update_wm_pre = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			pipe_config->disable_cxsr = true;
-	} else if (turn_off) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
-			pipe_config->update_wm_post = true;
-
-		/* must disable cxsr around plane enable/disable */
-		if (plane->id != PLANE_CURSOR)
-			pipe_config->disable_cxsr = true;
-	} else if (intel_wm_need_update(&plane->base, plane_state)) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
-			/* FIXME bollocks */
-			pipe_config->update_wm_pre = true;
-			pipe_config->update_wm_post = true;
-		}
-	}
+	/* must disable cxsr around plane enable/disable */
+	if ((turn_on || turn_off) && plane->id != PLANE_CURSOR)
+		pipe_config->disable_cxsr = true;
 
 	if (visible || was_visible)
 		pipe_config->fb_bits |= plane->frontbuffer_bit;
@@ -10929,9 +10866,6 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	int ret;
 	bool mode_changed = needs_modeset(crtc_state);
 
-	if (mode_changed && !crtc_state->active)
-		pipe_config->update_wm_post = true;
-
 	if (mode_changed && crtc_state->enable &&
 	    dev_priv->display.crtc_compute_clock &&
 	    !WARN_ON(pipe_config->shared_dpll)) {
@@ -12625,9 +12559,6 @@ static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
 		return true;
 
 	/* wm changes, need vblank before final wm's */
-	if (crtc_state->update_wm_post)
-		return true;
-
 	if (crtc_state->wm.need_postvbl_update)
 		return true;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dbe33b7bcf67..094a047a40bc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -631,7 +631,6 @@ struct intel_crtc_state {
 	unsigned fb_bits; /* framebuffers to flip */
 	bool update_pipe; /* can a fast modeset be performed? */
 	bool disable_cxsr;
-	bool update_wm_pre, update_wm_post; /* watermarks are updated */
 	bool fb_changed; /* fb on any of the planes is changed */
 	bool fifo_changed; /* FIFO split is changed */
 
@@ -1860,7 +1859,6 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_i915_private *dev_priv);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct intel_crtc *crtc);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf2127a3f730..80d4b07f0636 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5071,8 +5071,6 @@ skl_compute_wm(struct drm_atomic_state *state)
 		if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
 			/* This pipe's WM's did not change */
 			continue;
-
-		intel_cstate->update_wm_pre = true;
 	}
 
 	skl_print_wm_changes(state);
@@ -5758,46 +5756,6 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
 		!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
-/**
- * intel_update_watermarks - update FIFO watermark values based on current modes
- *
- * Calculate watermark values for the various WM regs based on current mode
- * and plane configuration.
- *
- * There are several cases to deal with here:
- *   - normal (i.e. non-self-refresh)
- *   - self-refresh (SR) mode
- *   - lines are large relative to FIFO size (buffer can hold up to 2)
- *   - lines are small relative to FIFO size (buffer can hold more than 2
- *     lines), so need to account for TLB latency
- *
- *   The normal calculation is:
- *     watermark = dotclock * bytes per pixel * latency
- *   where latency is platform & configuration dependent (we assume pessimal
- *   values here).
- *
- *   The SR calculation is:
- *     watermark = (trunc(latency/line time)+1) * surface width *
- *       bytes per pixel
- *   where
- *     line time = htotal / dotclock
- *     surface width = hdisplay for normal plane and 64 for cursor
- *   and latency is assumed to be high, as above.
- *
- * The final value programmed to the register should always be rounded up,
- * and include an extra 2 entries to account for clock crossings.
- *
- * We don't use the sprite, so we can ignore that.  And on Crestline we have
- * to set the non-SR watermarks to 8.
- */
-void intel_update_watermarks(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	if (dev_priv->display.update_wm)
-		dev_priv->display.update_wm(crtc);
-}
-
 /*
  * Lock protecting IPS related data structures
  */
-- 
2.9.3

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