[Qemu-devel] [PATCH 0/3] target/s390x: misc patches

[Qemu-devel] [PATCH 0/3] target/s390x: misc patches

[Aurelien Jarno]

Those are just random patches I have written while trying to get a MTTCG
version of qemu/s390x. I just send them to avoid duplicated work.

Aurelien Jarno (3):
  target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK
  target/s390x: fix SIGNAL PROCESSOR return value
  target/s390x: implement serialization in BRANCH CONDITION

 target/s390x/cpu.h         |  3 +++
 target/s390x/kvm.c         |  2 --
 target/s390x/misc_helper.c |  3 +--
 target/s390x/translate.c   | 16 ++++++++++++++++
 4 files changed, 20 insertions(+), 4 deletions(-)

-- 
2.11.0

[Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

[Aurelien Jarno]

For that move the definition from kvm.c to cpu.h

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/s390x/cpu.h         | 3 +++
 target/s390x/kvm.c         | 2 --
 target/s390x/misc_helper.c | 3 +--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index df823280a5..2471db920d 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -1081,6 +1081,9 @@ struct sysib_322 {
 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 
+/* SIGP order code mask corresponding to bit positions 56-63 */
+#define SIGP_ORDER_MASK 0x000000ff
+
 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
                   target_ulong *raddr, int *flags, bool exc);
diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
index 1a249d8359..fb105429be 100644
--- a/target/s390x/kvm.c
+++ b/target/s390x/kvm.c
@@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
     return SIGP_CC_ORDER_CODE_ACCEPTED;
 }
 
-#define SIGP_ORDER_MASK 0x000000ff
-
 static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
 {
     CPUS390XState *env = &cpu->env;
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index 53cb3b8ac6..395f38dea5 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -521,8 +521,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
 
     qemu_mutex_lock_iothread();
 
-    /* sigp contains the order code in bit positions 56-63, mask it here. */
-    switch (order_code & 0xff) {
+    switch (order_code & SIGP_ORDER_MASK) {
     case SIGP_SET_ARCH:
         cc = SIGP_CC_ORDER_CODE_ACCEPTED;
         /* switch arch */
-- 
2.11.0

[Qemu-devel] [PATCH 2/3] target/s390x: fix SIGNAL PROCESSOR return value

[Aurelien Jarno]

The SIGNAL PROCESSOR helper returns its value through the CC register.
set_cc_static should be called just after the helper.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/s390x/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 558ff78084..c58c27f8e9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3363,6 +3363,7 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
     check_privileged(s);
     potential_page_fault(s);
     gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
+    set_cc_static(s);
     tcg_temp_free_i32(r1);
     return NO_EXIT;
 }
-- 
2.11.0

[Qemu-devel] [PATCH 3/3] target/s390x: implement serialization in BRANCH CONDITION

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/s390x/translate.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index c58c27f8e9..2f07ce2be9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1517,6 +1517,21 @@ static ExitStatus op_bc(DisasContext *s, DisasOps *o)
     int imm = is_imm ? get_field(s->fields, i2) : 0;
     DisasCompare c;
 
+    /* BCR with R2 = 0 causes no branching */
+    if (have_field(s->fields, r2) && get_field(s->fields, r2) == 0) {
+        if (m1 == 14) {
+            /* Perform serialization */
+            /* FIXME: check for fast-BCR-serialization facility */
+            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+        }
+        if (m1 == 15) {
+            /* Perform serialization */
+            /* FIXME: perform checkpoint-synchronisation */
+            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+        }
+        return NO_EXIT;
+    }
+
     disas_jcc(s, &c, m1);
     return help_branch(s, &c, is_imm, imm, o->in2);
 }
-- 
2.11.0

Re: [Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

[Thomas Huth]

On 09.05.2017 10:27, Aurelien Jarno wrote:
> For that move the definition from kvm.c to cpu.h
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target/s390x/cpu.h         | 3 +++
>  target/s390x/kvm.c         | 2 --
>  target/s390x/misc_helper.c | 3 +--
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index df823280a5..2471db920d 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -1081,6 +1081,9 @@ struct sysib_322 {
>  #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
>  #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
>  
> +/* SIGP order code mask corresponding to bit positions 56-63 */
> +#define SIGP_ORDER_MASK 0x000000ff
> +
>  void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
>  int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>                    target_ulong *raddr, int *flags, bool exc);
> diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
> index 1a249d8359..fb105429be 100644
> --- a/target/s390x/kvm.c
> +++ b/target/s390x/kvm.c
> @@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
>      return SIGP_CC_ORDER_CODE_ACCEPTED;
>  }
>  
> -#define SIGP_ORDER_MASK 0x000000ff
> -
>  static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
>  {
>      CPUS390XState *env = &cpu->env;
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index 53cb3b8ac6..395f38dea5 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -521,8 +521,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
>  
>      qemu_mutex_lock_iothread();
>  
> -    /* sigp contains the order code in bit positions 56-63, mask it here. */
> -    switch (order_code & 0xff) {
> +    switch (order_code & SIGP_ORDER_MASK) {
>      case SIGP_SET_ARCH:
>          cc = SIGP_CC_ORDER_CODE_ACCEPTED;
>          /* switch arch */

Reviewed-by: Thomas Huth <thuth@redhat.com>

Re: [Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

[Richard Henderson]

On 05/09/2017 01:27 AM, Aurelien Jarno wrote:
> For that move the definition from kvm.c to cpu.h
> 
> Signed-off-by: Aurelien Jarno<aurelien@aurel32.net>
> ---
>   target/s390x/cpu.h         | 3 +++
>   target/s390x/kvm.c         | 2 --
>   target/s390x/misc_helper.c | 3 +--
>   3 files changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 2/3] target/s390x: fix SIGNAL PROCESSOR return value

[Richard Henderson]

On 05/09/2017 01:27 AM, Aurelien Jarno wrote:
> The SIGNAL PROCESSOR helper returns its value through the CC register.
> set_cc_static should be called just after the helper.
> 
> Signed-off-by: Aurelien Jarno<aurelien@aurel32.net>
> ---
>   target/s390x/translate.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 3/3] target/s390x: implement serialization in BRANCH CONDITION

[Richard Henderson]

On 05/09/2017 01:28 AM, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>   target/s390x/translate.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index c58c27f8e9..2f07ce2be9 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -1517,6 +1517,21 @@ static ExitStatus op_bc(DisasContext *s, DisasOps *o)
>       int imm = is_imm ? get_field(s->fields, i2) : 0;
>       DisasCompare c;
>   
> +    /* BCR with R2 = 0 causes no branching */
> +    if (have_field(s->fields, r2) && get_field(s->fields, r2) == 0) {
> +        if (m1 == 14) {
> +            /* Perform serialization */
> +            /* FIXME: check for fast-BCR-serialization facility */
> +            tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
> +        }
> +        if (m1 == 15) {
> +            /* Perform serialization */
> +            /* FIXME: perform checkpoint-synchronisation */

I don't know if we'll ever need to do anything with this side effect, but I 
guess it's good to document.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

[Cornelia Huck]

On Tue,  9 May 2017 10:27:58 +0200
Aurelien Jarno <aurelien@aurel32.net> wrote:

> For that move the definition from kvm.c to cpu.h
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target/s390x/cpu.h         | 3 +++
>  target/s390x/kvm.c         | 2 --
>  target/s390x/misc_helper.c | 3 +--
>  3 files changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>

I guess this will go with the other patches in this series?

Re: [Qemu-devel] [PATCH 1/3] target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

[Philippe Mathieu-Daudé]

On 05/09/2017 05:27 AM, Aurelien Jarno wrote:
> For that move the definition from kvm.c to cpu.h
>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/s390x/cpu.h         | 3 +++
>  target/s390x/kvm.c         | 2 --
>  target/s390x/misc_helper.c | 3 +--
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index df823280a5..2471db920d 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -1081,6 +1081,9 @@ struct sysib_322 {
>  #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
>  #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
>
> +/* SIGP order code mask corresponding to bit positions 56-63 */
> +#define SIGP_ORDER_MASK 0x000000ff
> +
>  void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
>  int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
>                    target_ulong *raddr, int *flags, bool exc);
> diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
> index 1a249d8359..fb105429be 100644
> --- a/target/s390x/kvm.c
> +++ b/target/s390x/kvm.c
> @@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
>      return SIGP_CC_ORDER_CODE_ACCEPTED;
>  }
>
> -#define SIGP_ORDER_MASK 0x000000ff
> -
>  static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
>  {
>      CPUS390XState *env = &cpu->env;
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index 53cb3b8ac6..395f38dea5 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -521,8 +521,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
>
>      qemu_mutex_lock_iothread();
>
> -    /* sigp contains the order code in bit positions 56-63, mask it here. */
> -    switch (order_code & 0xff) {
> +    switch (order_code & SIGP_ORDER_MASK) {
>      case SIGP_SET_ARCH:
>          cc = SIGP_CC_ORDER_CODE_ACCEPTED;
>          /* switch arch */
>